; -------------------------------------------------------------------------------- ; @Title: K80 On-Chip Peripherals ; @Props: Released ; @Author: BGI, JAS ; @Changelog: 2017-04-26 BGI ; 2019-07-01 JAS ; @Manufacturer: NXP - NXP Semiconductors ; @Doc: K80 Sub-Family Reference Manual.pdf, (Rev.4 2015-09) ; K82 Sub-Family Reference Manual.pdf, (Rev.2 2015-09) ; @Core: Cortex-M4F ; @Chip: MK80FN256VDC15, MK80FN256VLL15, ; MK81FN256VDC15, MK81FN256VLL15, MK81FN256VDC15R, ; MK82FN256VDC15, MK82FN256VLL15 ; @Copyright: (C) 1989-2019 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: perk80.per 17736 2024-04-08 09:26:07Z kwisniewski $ tree.close "Core Registers (Cortex-M4F)" AUTOINDENT.PUSH AUTOINDENT.OFF tree "System Control" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 12. group.long 0x08++0x03 line.long 0x00 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 9. " DISFPCA ,Disables lazy stacking of floating point context" "No,Yes" bitfld.long 0x00 8. " DISOOFP ,Disables floating point instructions completing" "No,Yes" bitfld.long 0x00 2. " DISFOLD ,Disables folding of IT instructions" "No,Yes" textline " " bitfld.long 0x00 1. " DISDEFWBUF ,Disables write buffer use during default memory map accesses" "No,Yes" bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle instructions" "No,Yes" group.long 0x10++0x0B line.long 0x00 "SYST_CSR,SysTick Control and Status Register" rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted" bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core" bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick" textline " " bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled" line.long 0x04 "SYST_RVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0" line.long 0x08 "SYST_CVR,SysTick Current Value Register" rgroup.long 0x1C++0x03 line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented" bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact" hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing" rgroup.long 0xD00++0x03 line.long 0x00 "CPUID,CPU ID Base Register" hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer Code" bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,?..." bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number" bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xD04++0x23 line.long 0x00 "ICSR,Interrupt Control State Register" bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Inactive,Active" bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not pending,Pending" bitfld.long 0x00 27. " PENDSVCLR ,Removes the pending status of the PendSV exception" "No effect,Removed" textline " " bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not pending,Pending" bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "No effect,Removed" bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active" textline " " bitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt" "Not pending,Pending" hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,Pending ISR Number Field" bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active" textline " " hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception" line.long 0x04 "VTOR,Vector Table Offset Register" hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Vector table address" line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register" hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key" rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big" bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" textline " " bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested" bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "No effect,Clear" bitfld.long 0x08 0. " VECTRESET ,System Reset" "No effect,Reset" line.long 0x0C "SCR,System Control Register" bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup" bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep" bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled" line.long 0x10 "CCR,Configuration Control Register" bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled" bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled" bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled" textline " " bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment" bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled" bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled" textline " " bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled" bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Denied,Allowed" bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level" line.long 0x14 "SHPR1,SSystem Handler Priority Register 1" hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7" hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)" hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)" textline " " hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)" line.long 0x18 "SHPR2,System Handler Priority Register 2" hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)" hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10" hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9" textline " " hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8" line.long 0x1C "SHPR3,System Handler Priority Register 3" hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)" hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)" hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13" textline " " hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)" line.long 0x20 "SHCSR,System Handler Control and State Register" bitfld.long 0x20 18. " USGFAULTENA ,Enable UsageFault" "Disabled,Enabled" bitfld.long 0x20 17. " BUSFAULTENA ,Enable BusFault" "Disabled,Enabled" bitfld.long 0x20 16. " MEMFAULTENA ,Enable MemManage fault" "Disabled,Enabled" textline " " bitfld.long 0x20 15. " SVCALLPENDED ,SVCall is pending" "Not pending,Pending" bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending" bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage is pending" "Not pending,Pending" textline " " bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending" bitfld.long 0x20 11. " SYSTICKACT ,SysTick is Active" "Not active,Active" bitfld.long 0x20 10. " PENDSVACT ,PendSV is Active" "Not active,Active" textline " " bitfld.long 0x20 8. " MONITORACT ,Monitor is Active" "Not active,Active" bitfld.long 0x20 7. " SVCALLACT ,SVCall is Active" "Not active,Active" bitfld.long 0x20 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active" textline " " bitfld.long 0x20 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active" bitfld.long 0x20 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active" group.byte 0xD28++0x1 line.byte 0x00 "MMFSR,MemManage Status Register" bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred" textline " " bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred" bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred" bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred" line.byte 0x01 "BFSR,Bus Fault Status Register" bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred" textline " " bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred" bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred" bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred" textline " " bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred" group.word 0xD2A++0x1 line.word 0x00 "USAFAULT,Usage Fault Status Register" bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error" bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error" bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error" textline " " bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error" bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error" bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error" group.long 0xD2C++0x07 line.long 0x00 "HFSR,Hard Fault Status Register" bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred" bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority" "Not occurred,Occurred" bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred" line.long 0x04 "DFSR,Debug Fault Status Register" bitfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted" bitfld.long 0x04 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred" bitfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred" textline " " bitfld.long 0x04 1. " BKPT ,BKPT Flag" "Not executed,Executed" bitfld.long 0x04 0. " HALTED ,Indicates a debug event generated by either" "Not requested,Requested" group.long 0xD34++0x0B line.long 0x00 "MMFAR,MemManage Fault Address Register" line.long 0x04 "BFAR,BusFault Address Register" line.long 0x08 "AFSR,Auxiliary Fault Status Register" group.long 0xD88++0x03 line.long 0x00 "CPACR,Coprocessor Access Control Register" bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access" wgroup.long 0xF00++0x03 line.long 0x00 "STIR,Software Trigger Interrupt Register" hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered" width 10. tree "Feature Registers" rgroup.long 0xD40++0x0B line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..." bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..." line.long 0x04 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..." line.long 0x08 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..." hgroup.long 0xD4C++0x03 hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" rgroup.long 0xD50++0x03 line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..." bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..." bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..." textline " " bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored" bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..." hgroup.long 0xD54++0x03 hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1" rgroup.long 0xD58++0x03 line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..." rgroup.long 0xD60++0x13 line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0" bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..." bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..." bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..." textline " " bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..." bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..." bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..." line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1" bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..." bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..." bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..." textline " " bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..." line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2" bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..." bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..." bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..." textline " " bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..." bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..." bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..." textline " " bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..." line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3" bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..." bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..." bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..." textline " " bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..." bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..." textline " " bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..." line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4" bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..." bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..." textline " " bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..." bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..." bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..." tree.end width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0C "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0C "CID3,Component ID3" tree.end width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Memory Protection Unit" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 15. rgroup.long 0xD90++0x03 line.long 0x00 "MPU_TYPE,MPU Type Register" bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported" group.long 0xD94++0x03 line.long 0x00 "MPU_CTRL,MPU Control Register" bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled" bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled" bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled" group.long 0xD98++0x03 line.long 0x00 "MPU_RNR,MPU Region Number Register" hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR" tree.close "MPU regions" if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0 group.long 0xD9C++0x03 "Region 0" saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 0 (not implemented)" saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1 group.long 0xD9C++0x03 "Region 1" saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 1 (not implemented)" saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2 group.long 0xD9C++0x03 "Region 2" saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 2 (not implemented)" saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3 group.long 0xD9C++0x03 "Region 3" saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 3 (not implemented)" saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4 group.long 0xD9C++0x03 "Region 4" saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 4 (not implemented)" saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5 group.long 0xD9C++0x03 "Region 5" saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 5 (not implemented)" saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6 group.long 0xD9C++0x03 "Region 6" saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 6 (not implemented)" saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7 group.long 0xD9C++0x03 "Region 7" saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 7 (not implemented)" saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8 group.long 0xD9C++0x03 "Region 8" saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 8 (not implemented)" saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9 group.long 0xD9C++0x03 "Region 9" saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 9 (not implemented)" saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA group.long 0xD9C++0x03 "Region 10" saveout 0xD98 %l 0xA line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xA line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 10 (not implemented)" saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB group.long 0xD9C++0x03 "Region 11" saveout 0xD98 %l 0xB line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xB line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 11 (not implemented)" saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC group.long 0xD9C++0x03 "Region 12" saveout 0xD98 %l 0xC line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xC line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 12 (not implemented)" saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD group.long 0xD9C++0x03 "Region 13" saveout 0xD98 %l 0xD line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xD line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 13 (not implemented)" saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE group.long 0xD9C++0x03 "Region 14" saveout 0xD98 %l 0xE line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xE line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 14 (not implemented)" saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF group.long 0xD9C++0x03 "Region 15" saveout 0xD98 %l 0xF line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xF line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 15 (not implemented)" saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15" textline " " textline " " endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Nested Vectored Interrupt Controller" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 6. rgroup.long 0x04++0x03 line.long 0x00 "ICTR,Interrupt Controller Type Register" bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..." tree "Interrupt Enable Registers" width 23. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x100++0x03 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x100++0x7 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x100++0x0B line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x100++0x0F line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x100++0x13 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x100++0x17 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x100++0x1B line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x100++0x1F line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x100++0x1F hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register" endif tree.end tree "Interrupt Pending Registers" width 23. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x200++0x03 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x200++0x07 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x200++0x0B line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x200++0x0F line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x200++0x13 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x200++0x17 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x200++0x1B line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x200++0x1F line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x200++0x1F hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register" endif tree.end tree "Interrupt Active Bit Registers" width 9. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) rgroup.long 0x300++0x03 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) rgroup.long 0x300++0x07 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) rgroup.long 0x300++0x0B line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) rgroup.long 0x300++0x0F line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) rgroup.long 0x300++0x13 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) rgroup.long 0x300++0x17 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) rgroup.long 0x300++0x1B line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" line.long 0x18 "ACTIVE7,Active Bit Register 7" bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) rgroup.long 0x300++0x1F line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" line.long 0x18 "ACTIVE7,Active Bit Register 7" bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" line.long 0x1c "ACTIVE8,Active Bit Register 8" bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x300++0x1F hide.long 0x00 "ACTIVE1,Active Bit Register 1" hide.long 0x04 "ACTIVE2,Active Bit Register 2" hide.long 0x08 "ACTIVE3,Active Bit Register 3" hide.long 0x0c "ACTIVE4,Active Bit Register 4" hide.long 0x10 "ACTIVE5,Active Bit Register 5" hide.long 0x14 "ACTIVE6,Active Bit Register 6" hide.long 0x18 "ACTIVE7,Active Bit Register 7" hide.long 0x1c "ACTIVE8,Active Bit Register 8" endif tree.end tree "Interrupt Priority Registers" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x400++0x1F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x400++0x3F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x400++0x5F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x400++0x7F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x400++0x9F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x400++0xBF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x400++0xDF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" line.long 0xC0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0xC4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0xC8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xCC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0xD0 "IPR52,Interrupt Priority Register" hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0xD4 "IPR53,Interrupt Priority Register" hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0xD8 "IPR54,Interrupt Priority Register" hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0xDC "IPR55,Interrupt Priority Register" hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x400++0xEF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" line.long 0xC0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0xC4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0xC8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xCC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0xD0 "IPR52,Interrupt Priority Register" hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0xD4 "IPR53,Interrupt Priority Register" hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0xD8 "IPR54,Interrupt Priority Register" hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0xDC "IPR55,Interrupt Priority Register" hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" line.long 0xE0 "IPR56,Interrupt Priority Register" hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority" hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority" hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority" hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority" line.long 0xE4 "IPR57,Interrupt Priority Register" hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority" hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority" hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority" hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority" line.long 0xE8 "IPR58,Interrupt Priority Register" hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority" hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority" hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority" hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority" line.long 0xEC "IPR59,Interrupt Priority Register" hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority" hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority" hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority" hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority" else hgroup.long 0x400++0xEF hide.long 0x0 "IPR0,Interrupt Priority Register" hide.long 0x4 "IPR1,Interrupt Priority Register" hide.long 0x8 "IPR2,Interrupt Priority Register" hide.long 0xC "IPR3,Interrupt Priority Register" hide.long 0x10 "IPR4,Interrupt Priority Register" hide.long 0x14 "IPR5,Interrupt Priority Register" hide.long 0x18 "IPR6,Interrupt Priority Register" hide.long 0x1C "IPR7,Interrupt Priority Register" hide.long 0x20 "IPR8,Interrupt Priority Register" hide.long 0x24 "IPR9,Interrupt Priority Register" hide.long 0x28 "IPR10,Interrupt Priority Register" hide.long 0x2C "IPR11,Interrupt Priority Register" hide.long 0x30 "IPR12,Interrupt Priority Register" hide.long 0x34 "IPR13,Interrupt Priority Register" hide.long 0x38 "IPR14,Interrupt Priority Register" hide.long 0x3C "IPR15,Interrupt Priority Register" hide.long 0x40 "IPR16,Interrupt Priority Register" hide.long 0x44 "IPR17,Interrupt Priority Register" hide.long 0x48 "IPR18,Interrupt Priority Register" hide.long 0x4C "IPR19,Interrupt Priority Register" hide.long 0x50 "IPR20,Interrupt Priority Register" hide.long 0x54 "IPR21,Interrupt Priority Register" hide.long 0x58 "IPR22,Interrupt Priority Register" hide.long 0x5C "IPR23,Interrupt Priority Register" hide.long 0x60 "IPR24,Interrupt Priority Register" hide.long 0x64 "IPR25,Interrupt Priority Register" hide.long 0x68 "IPR26,Interrupt Priority Register" hide.long 0x6C "IPR27,Interrupt Priority Register" hide.long 0x70 "IPR28,Interrupt Priority Register" hide.long 0x74 "IPR29,Interrupt Priority Register" hide.long 0x78 "IPR30,Interrupt Priority Register" hide.long 0x7C "IPR31,Interrupt Priority Register" hide.long 0x80 "IPR32,Interrupt Priority Register" hide.long 0x84 "IPR33,Interrupt Priority Register" hide.long 0x88 "IPR34,Interrupt Priority Register" hide.long 0x8C "IPR35,Interrupt Priority Register" hide.long 0x90 "IPR36,Interrupt Priority Register" hide.long 0x94 "IPR37,Interrupt Priority Register" hide.long 0x98 "IPR38,Interrupt Priority Register" hide.long 0x9C "IPR39,Interrupt Priority Register" hide.long 0xA0 "IPR40,Interrupt Priority Register" hide.long 0xA4 "IPR41,Interrupt Priority Register" hide.long 0xA8 "IPR42,Interrupt Priority Register" hide.long 0xAC "IPR43,Interrupt Priority Register" hide.long 0xB0 "IPR44,Interrupt Priority Register" hide.long 0xB4 "IPR45,Interrupt Priority Register" hide.long 0xB8 "IPR46,Interrupt Priority Register" hide.long 0xBC "IPR47,Interrupt Priority Register" hide.long 0xC0 "IPR48,Interrupt Priority Register" hide.long 0xC4 "IPR49,Interrupt Priority Register" hide.long 0xC8 "IPR50,Interrupt Priority Register" hide.long 0xCC "IPR51,Interrupt Priority Register" hide.long 0xD0 "IPR52,Interrupt Priority Register" hide.long 0xD4 "IPR53,Interrupt Priority Register" hide.long 0xD8 "IPR54,Interrupt Priority Register" hide.long 0xDC "IPR55,Interrupt Priority Register" hide.long 0xE0 "IPR56,Interrupt Priority Register" hide.long 0xE4 "IPR57,Interrupt Priority Register" hide.long 0xE8 "IPR58,Interrupt Priority Register" hide.long 0xEC "IPR59,Interrupt Priority Register" endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end sif CORENAME()=="CORTEXM4F" tree "Floating-point Unit (FPU)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 8. group.long 0xF34++0x0B line.long 0x00 "FPCCR,Floating-Point Context Control Register" bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled" bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled" bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able" textline " " bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able" bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able" bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able" textline " " bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread" bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged" bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active" line.long 0x04 "FPCAR,Floating-Point Context Address Register" hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame" line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register" bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative" bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation" bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode" textline " " bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero" rgroup.long 0xF40++0x07 line.long 0x00 "MVFR0,Media and FP Feature Register 0" bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..." bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..." bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..." textline " " bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..." bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..." bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..." bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..." line.long 0x04 "MVFR1,Media and FP Feature Register 1" bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..." bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..." textline " " bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..." bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..." width 0xB else newline textline "COREDEBUG component base address not specified" newline endif tree.end endif tree "Debug" tree "Core Debug" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 7. group.long 0xD30++0x03 line.long 0x00 "DFSR,Debug Fault Status Register" eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated" eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered" eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated" newline eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated" eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated" newline hgroup.long 0xDF0++0x03 hide.long 0x00 "DHCSR,Debug Halting Control and Status Register" in newline wgroup.long 0xDF4++0x03 line.long 0x00 "DCRSR,Debug Core Register Selector Register" bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write" hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register or special-purpose register or Floating-point extension register" group.long 0xDF8++0x03 line.long 0x00 "DCRDR,Debug Core Register Data Register" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000) group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step" newline bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" newline bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" newline bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" newline bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" else group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" newline bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" newline bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" newline bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" newline bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" endif width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Flash Patch and Breakpoint Unit (FPB)" sif COMPonent.AVAILABLE("FPB") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1)) width 10. group.long 0x00++0x07 line.long 0x00 "FP_CTRL,Flash Patch Control Register" bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..." rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127" bitfld.long 0x00 1. " KEY ,Key Field" "Low,High" bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled" textline "" line.long 0x04 "FP_REMAP,Flash Patch Remap Register" bitfld.long 0x04 29. " RMPSPT ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region" hexmask.long.tbyte 0x04 5.--28. 0x20 " REMAP ,Remap Base Address Field" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00) group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00) group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00) group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00) group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00) group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00) group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00) group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00) group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0c "CID3,Component ID3" tree.end width 0xB else newline textline "FPB component base address not specified" newline endif tree.end tree "Data Watchpoint and Trace Unit (DWT)" sif COMPonent.AVAILABLE("DWT") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)) width 15. group.long 0x00++0x1B line.long 0x00 "DWT_CTRL,Control Register" rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported" rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported" textline " " rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported" rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported" bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled" bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled" bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled" bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled" bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled" bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]" bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]" textline " " bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled" line.long 0x04 "DWT_CYCCNT,Cycle Count Register" line.long 0x08 "DWT_CPICNT,CPI Count Register" hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter" line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register" hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter" line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register" hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter" line.long 0x14 "DWT_LSUCNT,LSU Count Register" hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter" line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register" hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter" rgroup.long 0x1C++0x03 line.long 0x00 "DWT_PCSR,Program Counter Sample register" textline " " group.long 0x20++0x07 line.long 0x00 "DWT_COMP0,DWT Comparator Register 0" line.long 0x04 "DWT_MASK0,DWT Mask Registers 0" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" else group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x30)++0x07 line.long 0x00 "DWT_COMP1,DWT Comparator Register 1" line.long 0x04 "DWT_MASK1,DWT Mask Registers 1" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20) group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00) group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x40)++0x07 line.long 0x00 "DWT_COMP2,DWT Comparator Register 2" line.long 0x04 "DWT_MASK2,DWT Mask Registers 2" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20) group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00) group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x50)++0x07 line.long 0x00 "DWT_COMP3,DWT Comparator Register 3" line.long 0x04 "DWT_MASK3,DWT Mask Registers 3" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20) group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00) group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0c "CID3,Component ID3" tree.end width 0x0B else newline textline "DWT component base address not specified" newline endif tree.end tree.end AUTOINDENT.POP tree.end config 16. 8. tree.open "PORT (Pin Control and Interrupts)" tree "PORT_A" base ad:0x40049000 width 13. tree "PORT A Pin Control Registers" sif cpuis("MK8?FN256V*") ; 0x0 - adres ; A - litera portu (A,B,C,...) ; 0 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(0>=1)&&(0<=5)) group.long 0x0++0x03 line.long 0x00 "PORTA_PCR_0,PORTA Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(0==0)) group.long 0x0++0x03 line.long 0x00 "PORTA_PCR_0,PORTA Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x0++0x03 line.long 0x00 "PORTA_PCR_0,PORTA Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(0>=1)&&(0<=4)) group.long 0x0++0x03 line.long 0x00 "PORTA_PCR_0,PORTA Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(0==5)) group.long 0x0++0x03 line.long 0x00 "PORTA_PCR_0,PORTA Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(0==0)) group.long 0x0++0x03 line.long 0x00 "PORTA_PCR_0,PORTA Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x0++0x03 line.long 0x00 "PORTA_PCR_0,PORTA Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x0++0x03 line.long 0x00 "PORTA_PCR_0,PORTA Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x0++0x03 line.long 0x00 "PORTA_PCR_0,PORTA Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x0++0x03 line.long 0x00 "PORTA_PCR_0,PORTA Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B else ; 0x0 - adres ; A - litera portu (A,B,C,...) ; 0 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(0>=1)&&(0<=5)) group.long 0x0++0x03 line.long 0x00 "PORTA_PCR_0,PORTA Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(0==0)) group.long 0x0++0x03 line.long 0x00 "PORTA_PCR_0,PORTA Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x0++0x03 line.long 0x00 "PORTA_PCR_0,PORTA Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(0>=1)&&(0<=4)) group.long 0x0++0x03 line.long 0x00 "PORTA_PCR_0,PORTA Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(0==5)) group.long 0x0++0x03 line.long 0x00 "PORTA_PCR_0,PORTA Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(0==0)) group.long 0x0++0x03 line.long 0x00 "PORTA_PCR_0,PORTA Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x0++0x03 line.long 0x00 "PORTA_PCR_0,PORTA Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x0++0x03 line.long 0x00 "PORTA_PCR_0,PORTA Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x0++0x03 line.long 0x00 "PORTA_PCR_0,PORTA Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x0++0x03 line.long 0x00 "PORTA_PCR_0,PORTA Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B endif sif cpuis("MK8?FN256V*") ; 0x4 - adres ; A - litera portu (A,B,C,...) ; 1 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(1>=1)&&(1<=5)) group.long 0x4++0x03 line.long 0x00 "PORTA_PCR_1,PORTA Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(1==0)) group.long 0x4++0x03 line.long 0x00 "PORTA_PCR_1,PORTA Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4++0x03 line.long 0x00 "PORTA_PCR_1,PORTA Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(1>=1)&&(1<=4)) group.long 0x4++0x03 line.long 0x00 "PORTA_PCR_1,PORTA Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(1==5)) group.long 0x4++0x03 line.long 0x00 "PORTA_PCR_1,PORTA Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(1==0)) group.long 0x4++0x03 line.long 0x00 "PORTA_PCR_1,PORTA Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4++0x03 line.long 0x00 "PORTA_PCR_1,PORTA Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x4++0x03 line.long 0x00 "PORTA_PCR_1,PORTA Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x4++0x03 line.long 0x00 "PORTA_PCR_1,PORTA Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4++0x03 line.long 0x00 "PORTA_PCR_1,PORTA Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B else ; 0x4 - adres ; A - litera portu (A,B,C,...) ; 1 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(1>=1)&&(1<=5)) group.long 0x4++0x03 line.long 0x00 "PORTA_PCR_1,PORTA Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(1==0)) group.long 0x4++0x03 line.long 0x00 "PORTA_PCR_1,PORTA Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4++0x03 line.long 0x00 "PORTA_PCR_1,PORTA Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(1>=1)&&(1<=4)) group.long 0x4++0x03 line.long 0x00 "PORTA_PCR_1,PORTA Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(1==5)) group.long 0x4++0x03 line.long 0x00 "PORTA_PCR_1,PORTA Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(1==0)) group.long 0x4++0x03 line.long 0x00 "PORTA_PCR_1,PORTA Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4++0x03 line.long 0x00 "PORTA_PCR_1,PORTA Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x4++0x03 line.long 0x00 "PORTA_PCR_1,PORTA Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x4++0x03 line.long 0x00 "PORTA_PCR_1,PORTA Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4++0x03 line.long 0x00 "PORTA_PCR_1,PORTA Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B endif sif cpuis("MK8?FN256V*") ; 0x8 - adres ; A - litera portu (A,B,C,...) ; 2 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(2>=1)&&(2<=5)) group.long 0x8++0x03 line.long 0x00 "PORTA_PCR_2,PORTA Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(2==0)) group.long 0x8++0x03 line.long 0x00 "PORTA_PCR_2,PORTA Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x8++0x03 line.long 0x00 "PORTA_PCR_2,PORTA Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(2>=1)&&(2<=4)) group.long 0x8++0x03 line.long 0x00 "PORTA_PCR_2,PORTA Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(2==5)) group.long 0x8++0x03 line.long 0x00 "PORTA_PCR_2,PORTA Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(2==0)) group.long 0x8++0x03 line.long 0x00 "PORTA_PCR_2,PORTA Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x8++0x03 line.long 0x00 "PORTA_PCR_2,PORTA Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x8++0x03 line.long 0x00 "PORTA_PCR_2,PORTA Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x8++0x03 line.long 0x00 "PORTA_PCR_2,PORTA Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x8++0x03 line.long 0x00 "PORTA_PCR_2,PORTA Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B else ; 0x8 - adres ; A - litera portu (A,B,C,...) ; 2 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(2>=1)&&(2<=5)) group.long 0x8++0x03 line.long 0x00 "PORTA_PCR_2,PORTA Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(2==0)) group.long 0x8++0x03 line.long 0x00 "PORTA_PCR_2,PORTA Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x8++0x03 line.long 0x00 "PORTA_PCR_2,PORTA Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(2>=1)&&(2<=4)) group.long 0x8++0x03 line.long 0x00 "PORTA_PCR_2,PORTA Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(2==5)) group.long 0x8++0x03 line.long 0x00 "PORTA_PCR_2,PORTA Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(2==0)) group.long 0x8++0x03 line.long 0x00 "PORTA_PCR_2,PORTA Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x8++0x03 line.long 0x00 "PORTA_PCR_2,PORTA Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x8++0x03 line.long 0x00 "PORTA_PCR_2,PORTA Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x8++0x03 line.long 0x00 "PORTA_PCR_2,PORTA Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x8++0x03 line.long 0x00 "PORTA_PCR_2,PORTA Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B endif sif cpuis("MK8?FN256V*") ; 0xC - adres ; A - litera portu (A,B,C,...) ; 3 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(3>=1)&&(3<=5)) group.long 0xC++0x03 line.long 0x00 "PORTA_PCR_3,PORTA Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(3==0)) group.long 0xC++0x03 line.long 0x00 "PORTA_PCR_3,PORTA Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0xC++0x03 line.long 0x00 "PORTA_PCR_3,PORTA Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(3>=1)&&(3<=4)) group.long 0xC++0x03 line.long 0x00 "PORTA_PCR_3,PORTA Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(3==5)) group.long 0xC++0x03 line.long 0x00 "PORTA_PCR_3,PORTA Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(3==0)) group.long 0xC++0x03 line.long 0x00 "PORTA_PCR_3,PORTA Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0xC++0x03 line.long 0x00 "PORTA_PCR_3,PORTA Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0xC++0x03 line.long 0x00 "PORTA_PCR_3,PORTA Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0xC++0x03 line.long 0x00 "PORTA_PCR_3,PORTA Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0xC++0x03 line.long 0x00 "PORTA_PCR_3,PORTA Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B else ; 0xC - adres ; A - litera portu (A,B,C,...) ; 3 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(3>=1)&&(3<=5)) group.long 0xC++0x03 line.long 0x00 "PORTA_PCR_3,PORTA Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(3==0)) group.long 0xC++0x03 line.long 0x00 "PORTA_PCR_3,PORTA Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0xC++0x03 line.long 0x00 "PORTA_PCR_3,PORTA Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(3>=1)&&(3<=4)) group.long 0xC++0x03 line.long 0x00 "PORTA_PCR_3,PORTA Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(3==5)) group.long 0xC++0x03 line.long 0x00 "PORTA_PCR_3,PORTA Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(3==0)) group.long 0xC++0x03 line.long 0x00 "PORTA_PCR_3,PORTA Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0xC++0x03 line.long 0x00 "PORTA_PCR_3,PORTA Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0xC++0x03 line.long 0x00 "PORTA_PCR_3,PORTA Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0xC++0x03 line.long 0x00 "PORTA_PCR_3,PORTA Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0xC++0x03 line.long 0x00 "PORTA_PCR_3,PORTA Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B endif sif cpuis("MK8?FN256V*") ; 0x10 - adres ; A - litera portu (A,B,C,...) ; 4 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(4>=1)&&(4<=5)) group.long 0x10++0x03 line.long 0x00 "PORTA_PCR_4,PORTA Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(4==0)) group.long 0x10++0x03 line.long 0x00 "PORTA_PCR_4,PORTA Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x10++0x03 line.long 0x00 "PORTA_PCR_4,PORTA Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(4>=1)&&(4<=4)) group.long 0x10++0x03 line.long 0x00 "PORTA_PCR_4,PORTA Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(4==5)) group.long 0x10++0x03 line.long 0x00 "PORTA_PCR_4,PORTA Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(4==0)) group.long 0x10++0x03 line.long 0x00 "PORTA_PCR_4,PORTA Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x10++0x03 line.long 0x00 "PORTA_PCR_4,PORTA Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x10++0x03 line.long 0x00 "PORTA_PCR_4,PORTA Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x10++0x03 line.long 0x00 "PORTA_PCR_4,PORTA Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x10++0x03 line.long 0x00 "PORTA_PCR_4,PORTA Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B else ; 0x10 - adres ; A - litera portu (A,B,C,...) ; 4 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(4>=1)&&(4<=5)) group.long 0x10++0x03 line.long 0x00 "PORTA_PCR_4,PORTA Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(4==0)) group.long 0x10++0x03 line.long 0x00 "PORTA_PCR_4,PORTA Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x10++0x03 line.long 0x00 "PORTA_PCR_4,PORTA Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(4>=1)&&(4<=4)) group.long 0x10++0x03 line.long 0x00 "PORTA_PCR_4,PORTA Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(4==5)) group.long 0x10++0x03 line.long 0x00 "PORTA_PCR_4,PORTA Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(4==0)) group.long 0x10++0x03 line.long 0x00 "PORTA_PCR_4,PORTA Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x10++0x03 line.long 0x00 "PORTA_PCR_4,PORTA Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x10++0x03 line.long 0x00 "PORTA_PCR_4,PORTA Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x10++0x03 line.long 0x00 "PORTA_PCR_4,PORTA Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x10++0x03 line.long 0x00 "PORTA_PCR_4,PORTA Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B endif sif cpuis("MK8?FN256V*") ; 0x14 - adres ; A - litera portu (A,B,C,...) ; 5 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(5>=1)&&(5<=5)) group.long 0x14++0x03 line.long 0x00 "PORTA_PCR_5,PORTA Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(5==0)) group.long 0x14++0x03 line.long 0x00 "PORTA_PCR_5,PORTA Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x14++0x03 line.long 0x00 "PORTA_PCR_5,PORTA Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(5>=1)&&(5<=4)) group.long 0x14++0x03 line.long 0x00 "PORTA_PCR_5,PORTA Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(5==5)) group.long 0x14++0x03 line.long 0x00 "PORTA_PCR_5,PORTA Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(5==0)) group.long 0x14++0x03 line.long 0x00 "PORTA_PCR_5,PORTA Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x14++0x03 line.long 0x00 "PORTA_PCR_5,PORTA Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x14++0x03 line.long 0x00 "PORTA_PCR_5,PORTA Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x14++0x03 line.long 0x00 "PORTA_PCR_5,PORTA Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x14++0x03 line.long 0x00 "PORTA_PCR_5,PORTA Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B else ; 0x14 - adres ; A - litera portu (A,B,C,...) ; 5 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(5>=1)&&(5<=5)) group.long 0x14++0x03 line.long 0x00 "PORTA_PCR_5,PORTA Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(5==0)) group.long 0x14++0x03 line.long 0x00 "PORTA_PCR_5,PORTA Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x14++0x03 line.long 0x00 "PORTA_PCR_5,PORTA Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(5>=1)&&(5<=4)) group.long 0x14++0x03 line.long 0x00 "PORTA_PCR_5,PORTA Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(5==5)) group.long 0x14++0x03 line.long 0x00 "PORTA_PCR_5,PORTA Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(5==0)) group.long 0x14++0x03 line.long 0x00 "PORTA_PCR_5,PORTA Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x14++0x03 line.long 0x00 "PORTA_PCR_5,PORTA Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x14++0x03 line.long 0x00 "PORTA_PCR_5,PORTA Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x14++0x03 line.long 0x00 "PORTA_PCR_5,PORTA Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x14++0x03 line.long 0x00 "PORTA_PCR_5,PORTA Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B endif sif cpuis("MK8?FN256V*") else ; 0x18 - adres ; A - litera portu (A,B,C,...) ; 6 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(6>=1)&&(6<=5)) group.long 0x18++0x03 line.long 0x00 "PORTA_PCR_6,PORTA Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(6==0)) group.long 0x18++0x03 line.long 0x00 "PORTA_PCR_6,PORTA Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x18++0x03 line.long 0x00 "PORTA_PCR_6,PORTA Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(6>=1)&&(6<=4)) group.long 0x18++0x03 line.long 0x00 "PORTA_PCR_6,PORTA Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(6==5)) group.long 0x18++0x03 line.long 0x00 "PORTA_PCR_6,PORTA Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(6==0)) group.long 0x18++0x03 line.long 0x00 "PORTA_PCR_6,PORTA Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x18++0x03 line.long 0x00 "PORTA_PCR_6,PORTA Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x18++0x03 line.long 0x00 "PORTA_PCR_6,PORTA Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x18++0x03 line.long 0x00 "PORTA_PCR_6,PORTA Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x18++0x03 line.long 0x00 "PORTA_PCR_6,PORTA Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B endif sif cpuis("MK8?FN256V*") else ; 0x1C - adres ; A - litera portu (A,B,C,...) ; 7 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(7>=1)&&(7<=5)) group.long 0x1C++0x03 line.long 0x00 "PORTA_PCR_7,PORTA Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(7==0)) group.long 0x1C++0x03 line.long 0x00 "PORTA_PCR_7,PORTA Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x1C++0x03 line.long 0x00 "PORTA_PCR_7,PORTA Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(7>=1)&&(7<=4)) group.long 0x1C++0x03 line.long 0x00 "PORTA_PCR_7,PORTA Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(7==5)) group.long 0x1C++0x03 line.long 0x00 "PORTA_PCR_7,PORTA Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(7==0)) group.long 0x1C++0x03 line.long 0x00 "PORTA_PCR_7,PORTA Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x1C++0x03 line.long 0x00 "PORTA_PCR_7,PORTA Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x1C++0x03 line.long 0x00 "PORTA_PCR_7,PORTA Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x1C++0x03 line.long 0x00 "PORTA_PCR_7,PORTA Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x1C++0x03 line.long 0x00 "PORTA_PCR_7,PORTA Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B endif sif cpuis("MK8?FN256V*") else ; 0x20 - adres ; A - litera portu (A,B,C,...) ; 8 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(8>=1)&&(8<=5)) group.long 0x20++0x03 line.long 0x00 "PORTA_PCR_8,PORTA Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(8==0)) group.long 0x20++0x03 line.long 0x00 "PORTA_PCR_8,PORTA Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x20++0x03 line.long 0x00 "PORTA_PCR_8,PORTA Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(8>=1)&&(8<=4)) group.long 0x20++0x03 line.long 0x00 "PORTA_PCR_8,PORTA Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(8==5)) group.long 0x20++0x03 line.long 0x00 "PORTA_PCR_8,PORTA Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(8==0)) group.long 0x20++0x03 line.long 0x00 "PORTA_PCR_8,PORTA Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x20++0x03 line.long 0x00 "PORTA_PCR_8,PORTA Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x20++0x03 line.long 0x00 "PORTA_PCR_8,PORTA Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x20++0x03 line.long 0x00 "PORTA_PCR_8,PORTA Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x20++0x03 line.long 0x00 "PORTA_PCR_8,PORTA Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B endif sif cpuis("MK8?FN256V*") else ; 0x24 - adres ; A - litera portu (A,B,C,...) ; 9 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(9>=1)&&(9<=5)) group.long 0x24++0x03 line.long 0x00 "PORTA_PCR_9,PORTA Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(9==0)) group.long 0x24++0x03 line.long 0x00 "PORTA_PCR_9,PORTA Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x24++0x03 line.long 0x00 "PORTA_PCR_9,PORTA Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(9>=1)&&(9<=4)) group.long 0x24++0x03 line.long 0x00 "PORTA_PCR_9,PORTA Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(9==5)) group.long 0x24++0x03 line.long 0x00 "PORTA_PCR_9,PORTA Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(9==0)) group.long 0x24++0x03 line.long 0x00 "PORTA_PCR_9,PORTA Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x24++0x03 line.long 0x00 "PORTA_PCR_9,PORTA Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x24++0x03 line.long 0x00 "PORTA_PCR_9,PORTA Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x24++0x03 line.long 0x00 "PORTA_PCR_9,PORTA Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x24++0x03 line.long 0x00 "PORTA_PCR_9,PORTA Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B endif sif cpuis("MK8?FN256V*") ; 0x28 - adres ; A - litera portu (A,B,C,...) ; 10 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(10>=1)&&(10<=5)) group.long 0x28++0x03 line.long 0x00 "PORTA_PCR_10,PORTA Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(10==0)) group.long 0x28++0x03 line.long 0x00 "PORTA_PCR_10,PORTA Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x28++0x03 line.long 0x00 "PORTA_PCR_10,PORTA Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(10>=1)&&(10<=4)) group.long 0x28++0x03 line.long 0x00 "PORTA_PCR_10,PORTA Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(10==5)) group.long 0x28++0x03 line.long 0x00 "PORTA_PCR_10,PORTA Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(10==0)) group.long 0x28++0x03 line.long 0x00 "PORTA_PCR_10,PORTA Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x28++0x03 line.long 0x00 "PORTA_PCR_10,PORTA Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x28++0x03 line.long 0x00 "PORTA_PCR_10,PORTA Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x28++0x03 line.long 0x00 "PORTA_PCR_10,PORTA Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x28++0x03 line.long 0x00 "PORTA_PCR_10,PORTA Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B else ; 0x28 - adres ; A - litera portu (A,B,C,...) ; 10 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(10>=1)&&(10<=5)) group.long 0x28++0x03 line.long 0x00 "PORTA_PCR_10,PORTA Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(10==0)) group.long 0x28++0x03 line.long 0x00 "PORTA_PCR_10,PORTA Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x28++0x03 line.long 0x00 "PORTA_PCR_10,PORTA Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(10>=1)&&(10<=4)) group.long 0x28++0x03 line.long 0x00 "PORTA_PCR_10,PORTA Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(10==5)) group.long 0x28++0x03 line.long 0x00 "PORTA_PCR_10,PORTA Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(10==0)) group.long 0x28++0x03 line.long 0x00 "PORTA_PCR_10,PORTA Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x28++0x03 line.long 0x00 "PORTA_PCR_10,PORTA Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x28++0x03 line.long 0x00 "PORTA_PCR_10,PORTA Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x28++0x03 line.long 0x00 "PORTA_PCR_10,PORTA Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x28++0x03 line.long 0x00 "PORTA_PCR_10,PORTA Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B endif sif cpuis("MK8?FN256V*") ; 0x2C - adres ; A - litera portu (A,B,C,...) ; 11 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(11>=1)&&(11<=5)) group.long 0x2C++0x03 line.long 0x00 "PORTA_PCR_11,PORTA Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(11==0)) group.long 0x2C++0x03 line.long 0x00 "PORTA_PCR_11,PORTA Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x2C++0x03 line.long 0x00 "PORTA_PCR_11,PORTA Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(11>=1)&&(11<=4)) group.long 0x2C++0x03 line.long 0x00 "PORTA_PCR_11,PORTA Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(11==5)) group.long 0x2C++0x03 line.long 0x00 "PORTA_PCR_11,PORTA Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(11==0)) group.long 0x2C++0x03 line.long 0x00 "PORTA_PCR_11,PORTA Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x2C++0x03 line.long 0x00 "PORTA_PCR_11,PORTA Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x2C++0x03 line.long 0x00 "PORTA_PCR_11,PORTA Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x2C++0x03 line.long 0x00 "PORTA_PCR_11,PORTA Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x2C++0x03 line.long 0x00 "PORTA_PCR_11,PORTA Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B else ; 0x2C - adres ; A - litera portu (A,B,C,...) ; 11 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(11>=1)&&(11<=5)) group.long 0x2C++0x03 line.long 0x00 "PORTA_PCR_11,PORTA Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(11==0)) group.long 0x2C++0x03 line.long 0x00 "PORTA_PCR_11,PORTA Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x2C++0x03 line.long 0x00 "PORTA_PCR_11,PORTA Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(11>=1)&&(11<=4)) group.long 0x2C++0x03 line.long 0x00 "PORTA_PCR_11,PORTA Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(11==5)) group.long 0x2C++0x03 line.long 0x00 "PORTA_PCR_11,PORTA Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(11==0)) group.long 0x2C++0x03 line.long 0x00 "PORTA_PCR_11,PORTA Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x2C++0x03 line.long 0x00 "PORTA_PCR_11,PORTA Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x2C++0x03 line.long 0x00 "PORTA_PCR_11,PORTA Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x2C++0x03 line.long 0x00 "PORTA_PCR_11,PORTA Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x2C++0x03 line.long 0x00 "PORTA_PCR_11,PORTA Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B endif sif cpuis("MK8?FN256V*") ; 0x30 - adres ; A - litera portu (A,B,C,...) ; 12 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(12>=1)&&(12<=5)) group.long 0x30++0x03 line.long 0x00 "PORTA_PCR_12,PORTA Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(12==0)) group.long 0x30++0x03 line.long 0x00 "PORTA_PCR_12,PORTA Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x30++0x03 line.long 0x00 "PORTA_PCR_12,PORTA Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(12>=1)&&(12<=4)) group.long 0x30++0x03 line.long 0x00 "PORTA_PCR_12,PORTA Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(12==5)) group.long 0x30++0x03 line.long 0x00 "PORTA_PCR_12,PORTA Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(12==0)) group.long 0x30++0x03 line.long 0x00 "PORTA_PCR_12,PORTA Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x30++0x03 line.long 0x00 "PORTA_PCR_12,PORTA Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x30++0x03 line.long 0x00 "PORTA_PCR_12,PORTA Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x30++0x03 line.long 0x00 "PORTA_PCR_12,PORTA Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x30++0x03 line.long 0x00 "PORTA_PCR_12,PORTA Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B else ; 0x30 - adres ; A - litera portu (A,B,C,...) ; 12 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(12>=1)&&(12<=5)) group.long 0x30++0x03 line.long 0x00 "PORTA_PCR_12,PORTA Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(12==0)) group.long 0x30++0x03 line.long 0x00 "PORTA_PCR_12,PORTA Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x30++0x03 line.long 0x00 "PORTA_PCR_12,PORTA Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(12>=1)&&(12<=4)) group.long 0x30++0x03 line.long 0x00 "PORTA_PCR_12,PORTA Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(12==5)) group.long 0x30++0x03 line.long 0x00 "PORTA_PCR_12,PORTA Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(12==0)) group.long 0x30++0x03 line.long 0x00 "PORTA_PCR_12,PORTA Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x30++0x03 line.long 0x00 "PORTA_PCR_12,PORTA Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x30++0x03 line.long 0x00 "PORTA_PCR_12,PORTA Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x30++0x03 line.long 0x00 "PORTA_PCR_12,PORTA Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x30++0x03 line.long 0x00 "PORTA_PCR_12,PORTA Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B endif sif cpuis("MK8?FN256V*") ; 0x34 - adres ; A - litera portu (A,B,C,...) ; 13 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(13>=1)&&(13<=5)) group.long 0x34++0x03 line.long 0x00 "PORTA_PCR_13,PORTA Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(13==0)) group.long 0x34++0x03 line.long 0x00 "PORTA_PCR_13,PORTA Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x34++0x03 line.long 0x00 "PORTA_PCR_13,PORTA Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(13>=1)&&(13<=4)) group.long 0x34++0x03 line.long 0x00 "PORTA_PCR_13,PORTA Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(13==5)) group.long 0x34++0x03 line.long 0x00 "PORTA_PCR_13,PORTA Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(13==0)) group.long 0x34++0x03 line.long 0x00 "PORTA_PCR_13,PORTA Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x34++0x03 line.long 0x00 "PORTA_PCR_13,PORTA Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x34++0x03 line.long 0x00 "PORTA_PCR_13,PORTA Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x34++0x03 line.long 0x00 "PORTA_PCR_13,PORTA Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x34++0x03 line.long 0x00 "PORTA_PCR_13,PORTA Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B else ; 0x34 - adres ; A - litera portu (A,B,C,...) ; 13 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(13>=1)&&(13<=5)) group.long 0x34++0x03 line.long 0x00 "PORTA_PCR_13,PORTA Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(13==0)) group.long 0x34++0x03 line.long 0x00 "PORTA_PCR_13,PORTA Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x34++0x03 line.long 0x00 "PORTA_PCR_13,PORTA Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(13>=1)&&(13<=4)) group.long 0x34++0x03 line.long 0x00 "PORTA_PCR_13,PORTA Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(13==5)) group.long 0x34++0x03 line.long 0x00 "PORTA_PCR_13,PORTA Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(13==0)) group.long 0x34++0x03 line.long 0x00 "PORTA_PCR_13,PORTA Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x34++0x03 line.long 0x00 "PORTA_PCR_13,PORTA Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x34++0x03 line.long 0x00 "PORTA_PCR_13,PORTA Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x34++0x03 line.long 0x00 "PORTA_PCR_13,PORTA Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x34++0x03 line.long 0x00 "PORTA_PCR_13,PORTA Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B endif sif cpuis("MK8?FN256V*") ; 0x38 - adres ; A - litera portu (A,B,C,...) ; 14 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(14>=1)&&(14<=5)) group.long 0x38++0x03 line.long 0x00 "PORTA_PCR_14,PORTA Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(14==0)) group.long 0x38++0x03 line.long 0x00 "PORTA_PCR_14,PORTA Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x38++0x03 line.long 0x00 "PORTA_PCR_14,PORTA Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(14>=1)&&(14<=4)) group.long 0x38++0x03 line.long 0x00 "PORTA_PCR_14,PORTA Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(14==5)) group.long 0x38++0x03 line.long 0x00 "PORTA_PCR_14,PORTA Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(14==0)) group.long 0x38++0x03 line.long 0x00 "PORTA_PCR_14,PORTA Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x38++0x03 line.long 0x00 "PORTA_PCR_14,PORTA Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x38++0x03 line.long 0x00 "PORTA_PCR_14,PORTA Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x38++0x03 line.long 0x00 "PORTA_PCR_14,PORTA Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x38++0x03 line.long 0x00 "PORTA_PCR_14,PORTA Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B else ; 0x38 - adres ; A - litera portu (A,B,C,...) ; 14 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(14>=1)&&(14<=5)) group.long 0x38++0x03 line.long 0x00 "PORTA_PCR_14,PORTA Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(14==0)) group.long 0x38++0x03 line.long 0x00 "PORTA_PCR_14,PORTA Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x38++0x03 line.long 0x00 "PORTA_PCR_14,PORTA Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(14>=1)&&(14<=4)) group.long 0x38++0x03 line.long 0x00 "PORTA_PCR_14,PORTA Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(14==5)) group.long 0x38++0x03 line.long 0x00 "PORTA_PCR_14,PORTA Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(14==0)) group.long 0x38++0x03 line.long 0x00 "PORTA_PCR_14,PORTA Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x38++0x03 line.long 0x00 "PORTA_PCR_14,PORTA Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x38++0x03 line.long 0x00 "PORTA_PCR_14,PORTA Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x38++0x03 line.long 0x00 "PORTA_PCR_14,PORTA Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x38++0x03 line.long 0x00 "PORTA_PCR_14,PORTA Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B endif sif cpuis("MK8?FN256V*") ; 0x3C - adres ; A - litera portu (A,B,C,...) ; 15 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(15>=1)&&(15<=5)) group.long 0x3C++0x03 line.long 0x00 "PORTA_PCR_15,PORTA Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(15==0)) group.long 0x3C++0x03 line.long 0x00 "PORTA_PCR_15,PORTA Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x3C++0x03 line.long 0x00 "PORTA_PCR_15,PORTA Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(15>=1)&&(15<=4)) group.long 0x3C++0x03 line.long 0x00 "PORTA_PCR_15,PORTA Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(15==5)) group.long 0x3C++0x03 line.long 0x00 "PORTA_PCR_15,PORTA Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(15==0)) group.long 0x3C++0x03 line.long 0x00 "PORTA_PCR_15,PORTA Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x3C++0x03 line.long 0x00 "PORTA_PCR_15,PORTA Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x3C++0x03 line.long 0x00 "PORTA_PCR_15,PORTA Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x3C++0x03 line.long 0x00 "PORTA_PCR_15,PORTA Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x3C++0x03 line.long 0x00 "PORTA_PCR_15,PORTA Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B else ; 0x3C - adres ; A - litera portu (A,B,C,...) ; 15 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(15>=1)&&(15<=5)) group.long 0x3C++0x03 line.long 0x00 "PORTA_PCR_15,PORTA Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(15==0)) group.long 0x3C++0x03 line.long 0x00 "PORTA_PCR_15,PORTA Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x3C++0x03 line.long 0x00 "PORTA_PCR_15,PORTA Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(15>=1)&&(15<=4)) group.long 0x3C++0x03 line.long 0x00 "PORTA_PCR_15,PORTA Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(15==5)) group.long 0x3C++0x03 line.long 0x00 "PORTA_PCR_15,PORTA Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(15==0)) group.long 0x3C++0x03 line.long 0x00 "PORTA_PCR_15,PORTA Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x3C++0x03 line.long 0x00 "PORTA_PCR_15,PORTA Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x3C++0x03 line.long 0x00 "PORTA_PCR_15,PORTA Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x3C++0x03 line.long 0x00 "PORTA_PCR_15,PORTA Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x3C++0x03 line.long 0x00 "PORTA_PCR_15,PORTA Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B endif sif cpuis("MK8?FN256V*") ; 0x40 - adres ; A - litera portu (A,B,C,...) ; 16 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(16>=1)&&(16<=5)) group.long 0x40++0x03 line.long 0x00 "PORTA_PCR_16,PORTA Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(16==0)) group.long 0x40++0x03 line.long 0x00 "PORTA_PCR_16,PORTA Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x40++0x03 line.long 0x00 "PORTA_PCR_16,PORTA Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(16>=1)&&(16<=4)) group.long 0x40++0x03 line.long 0x00 "PORTA_PCR_16,PORTA Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(16==5)) group.long 0x40++0x03 line.long 0x00 "PORTA_PCR_16,PORTA Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(16==0)) group.long 0x40++0x03 line.long 0x00 "PORTA_PCR_16,PORTA Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x40++0x03 line.long 0x00 "PORTA_PCR_16,PORTA Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x40++0x03 line.long 0x00 "PORTA_PCR_16,PORTA Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x40++0x03 line.long 0x00 "PORTA_PCR_16,PORTA Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x40++0x03 line.long 0x00 "PORTA_PCR_16,PORTA Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B else ; 0x40 - adres ; A - litera portu (A,B,C,...) ; 16 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(16>=1)&&(16<=5)) group.long 0x40++0x03 line.long 0x00 "PORTA_PCR_16,PORTA Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(16==0)) group.long 0x40++0x03 line.long 0x00 "PORTA_PCR_16,PORTA Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x40++0x03 line.long 0x00 "PORTA_PCR_16,PORTA Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(16>=1)&&(16<=4)) group.long 0x40++0x03 line.long 0x00 "PORTA_PCR_16,PORTA Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(16==5)) group.long 0x40++0x03 line.long 0x00 "PORTA_PCR_16,PORTA Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(16==0)) group.long 0x40++0x03 line.long 0x00 "PORTA_PCR_16,PORTA Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x40++0x03 line.long 0x00 "PORTA_PCR_16,PORTA Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x40++0x03 line.long 0x00 "PORTA_PCR_16,PORTA Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x40++0x03 line.long 0x00 "PORTA_PCR_16,PORTA Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x40++0x03 line.long 0x00 "PORTA_PCR_16,PORTA Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B endif sif cpuis("MK8?FN256V*") ; 0x44 - adres ; A - litera portu (A,B,C,...) ; 17 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(17>=1)&&(17<=5)) group.long 0x44++0x03 line.long 0x00 "PORTA_PCR_17,PORTA Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(17==0)) group.long 0x44++0x03 line.long 0x00 "PORTA_PCR_17,PORTA Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x44++0x03 line.long 0x00 "PORTA_PCR_17,PORTA Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(17>=1)&&(17<=4)) group.long 0x44++0x03 line.long 0x00 "PORTA_PCR_17,PORTA Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(17==5)) group.long 0x44++0x03 line.long 0x00 "PORTA_PCR_17,PORTA Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(17==0)) group.long 0x44++0x03 line.long 0x00 "PORTA_PCR_17,PORTA Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x44++0x03 line.long 0x00 "PORTA_PCR_17,PORTA Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x44++0x03 line.long 0x00 "PORTA_PCR_17,PORTA Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x44++0x03 line.long 0x00 "PORTA_PCR_17,PORTA Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x44++0x03 line.long 0x00 "PORTA_PCR_17,PORTA Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B else ; 0x44 - adres ; A - litera portu (A,B,C,...) ; 17 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(17>=1)&&(17<=5)) group.long 0x44++0x03 line.long 0x00 "PORTA_PCR_17,PORTA Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(17==0)) group.long 0x44++0x03 line.long 0x00 "PORTA_PCR_17,PORTA Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x44++0x03 line.long 0x00 "PORTA_PCR_17,PORTA Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(17>=1)&&(17<=4)) group.long 0x44++0x03 line.long 0x00 "PORTA_PCR_17,PORTA Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(17==5)) group.long 0x44++0x03 line.long 0x00 "PORTA_PCR_17,PORTA Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(17==0)) group.long 0x44++0x03 line.long 0x00 "PORTA_PCR_17,PORTA Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x44++0x03 line.long 0x00 "PORTA_PCR_17,PORTA Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x44++0x03 line.long 0x00 "PORTA_PCR_17,PORTA Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x44++0x03 line.long 0x00 "PORTA_PCR_17,PORTA Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x44++0x03 line.long 0x00 "PORTA_PCR_17,PORTA Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B endif sif cpuis("MK8?FN256V*") ; 0x48 - adres ; A - litera portu (A,B,C,...) ; 18 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(18>=1)&&(18<=5)) group.long 0x48++0x03 line.long 0x00 "PORTA_PCR_18,PORTA Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(18==0)) group.long 0x48++0x03 line.long 0x00 "PORTA_PCR_18,PORTA Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x48++0x03 line.long 0x00 "PORTA_PCR_18,PORTA Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(18>=1)&&(18<=4)) group.long 0x48++0x03 line.long 0x00 "PORTA_PCR_18,PORTA Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(18==5)) group.long 0x48++0x03 line.long 0x00 "PORTA_PCR_18,PORTA Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(18==0)) group.long 0x48++0x03 line.long 0x00 "PORTA_PCR_18,PORTA Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x48++0x03 line.long 0x00 "PORTA_PCR_18,PORTA Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x48++0x03 line.long 0x00 "PORTA_PCR_18,PORTA Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x48++0x03 line.long 0x00 "PORTA_PCR_18,PORTA Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x48++0x03 line.long 0x00 "PORTA_PCR_18,PORTA Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B else ; 0x48 - adres ; A - litera portu (A,B,C,...) ; 18 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(18>=1)&&(18<=5)) group.long 0x48++0x03 line.long 0x00 "PORTA_PCR_18,PORTA Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(18==0)) group.long 0x48++0x03 line.long 0x00 "PORTA_PCR_18,PORTA Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x48++0x03 line.long 0x00 "PORTA_PCR_18,PORTA Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(18>=1)&&(18<=4)) group.long 0x48++0x03 line.long 0x00 "PORTA_PCR_18,PORTA Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(18==5)) group.long 0x48++0x03 line.long 0x00 "PORTA_PCR_18,PORTA Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(18==0)) group.long 0x48++0x03 line.long 0x00 "PORTA_PCR_18,PORTA Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x48++0x03 line.long 0x00 "PORTA_PCR_18,PORTA Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x48++0x03 line.long 0x00 "PORTA_PCR_18,PORTA Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x48++0x03 line.long 0x00 "PORTA_PCR_18,PORTA Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x48++0x03 line.long 0x00 "PORTA_PCR_18,PORTA Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B endif sif cpuis("MK8?FN256V*") ; 0x4C - adres ; A - litera portu (A,B,C,...) ; 19 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(19>=1)&&(19<=5)) group.long 0x4C++0x03 line.long 0x00 "PORTA_PCR_19,PORTA Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(19==0)) group.long 0x4C++0x03 line.long 0x00 "PORTA_PCR_19,PORTA Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4C++0x03 line.long 0x00 "PORTA_PCR_19,PORTA Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(19>=1)&&(19<=4)) group.long 0x4C++0x03 line.long 0x00 "PORTA_PCR_19,PORTA Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(19==5)) group.long 0x4C++0x03 line.long 0x00 "PORTA_PCR_19,PORTA Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(19==0)) group.long 0x4C++0x03 line.long 0x00 "PORTA_PCR_19,PORTA Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4C++0x03 line.long 0x00 "PORTA_PCR_19,PORTA Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x4C++0x03 line.long 0x00 "PORTA_PCR_19,PORTA Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x4C++0x03 line.long 0x00 "PORTA_PCR_19,PORTA Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4C++0x03 line.long 0x00 "PORTA_PCR_19,PORTA Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B else ; 0x4C - adres ; A - litera portu (A,B,C,...) ; 19 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(19>=1)&&(19<=5)) group.long 0x4C++0x03 line.long 0x00 "PORTA_PCR_19,PORTA Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(19==0)) group.long 0x4C++0x03 line.long 0x00 "PORTA_PCR_19,PORTA Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4C++0x03 line.long 0x00 "PORTA_PCR_19,PORTA Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(19>=1)&&(19<=4)) group.long 0x4C++0x03 line.long 0x00 "PORTA_PCR_19,PORTA Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(19==5)) group.long 0x4C++0x03 line.long 0x00 "PORTA_PCR_19,PORTA Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(19==0)) group.long 0x4C++0x03 line.long 0x00 "PORTA_PCR_19,PORTA Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4C++0x03 line.long 0x00 "PORTA_PCR_19,PORTA Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x4C++0x03 line.long 0x00 "PORTA_PCR_19,PORTA Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x4C++0x03 line.long 0x00 "PORTA_PCR_19,PORTA Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4C++0x03 line.long 0x00 "PORTA_PCR_19,PORTA Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B endif sif cpuis("MK8?FN256V*") ; 0x50 - adres ; A - litera portu (A,B,C,...) ; 20 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(20>=1)&&(20<=5)) group.long 0x50++0x03 line.long 0x00 "PORTA_PCR_20,PORTA Pin Control Register 20" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(20==0)) group.long 0x50++0x03 line.long 0x00 "PORTA_PCR_20,PORTA Pin Control Register 20" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x50++0x03 line.long 0x00 "PORTA_PCR_20,PORTA Pin Control Register 20" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(20>=1)&&(20<=4)) group.long 0x50++0x03 line.long 0x00 "PORTA_PCR_20,PORTA Pin Control Register 20" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(20==5)) group.long 0x50++0x03 line.long 0x00 "PORTA_PCR_20,PORTA Pin Control Register 20" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(20==0)) group.long 0x50++0x03 line.long 0x00 "PORTA_PCR_20,PORTA Pin Control Register 20" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x50++0x03 line.long 0x00 "PORTA_PCR_20,PORTA Pin Control Register 20" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x50++0x03 line.long 0x00 "PORTA_PCR_20,PORTA Pin Control Register 20" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x50++0x03 line.long 0x00 "PORTA_PCR_20,PORTA Pin Control Register 20" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x50++0x03 line.long 0x00 "PORTA_PCR_20,PORTA Pin Control Register 20" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B else ; 0x50 - adres ; A - litera portu (A,B,C,...) ; 20 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(20>=1)&&(20<=5)) group.long 0x50++0x03 line.long 0x00 "PORTA_PCR_20,PORTA Pin Control Register 20" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(20==0)) group.long 0x50++0x03 line.long 0x00 "PORTA_PCR_20,PORTA Pin Control Register 20" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x50++0x03 line.long 0x00 "PORTA_PCR_20,PORTA Pin Control Register 20" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(20>=1)&&(20<=4)) group.long 0x50++0x03 line.long 0x00 "PORTA_PCR_20,PORTA Pin Control Register 20" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(20==5)) group.long 0x50++0x03 line.long 0x00 "PORTA_PCR_20,PORTA Pin Control Register 20" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(20==0)) group.long 0x50++0x03 line.long 0x00 "PORTA_PCR_20,PORTA Pin Control Register 20" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x50++0x03 line.long 0x00 "PORTA_PCR_20,PORTA Pin Control Register 20" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x50++0x03 line.long 0x00 "PORTA_PCR_20,PORTA Pin Control Register 20" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x50++0x03 line.long 0x00 "PORTA_PCR_20,PORTA Pin Control Register 20" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x50++0x03 line.long 0x00 "PORTA_PCR_20,PORTA Pin Control Register 20" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B endif sif cpuis("MK8?FN256V*") ; 0x54 - adres ; A - litera portu (A,B,C,...) ; 21 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(21>=1)&&(21<=5)) group.long 0x54++0x03 line.long 0x00 "PORTA_PCR_21,PORTA Pin Control Register 21" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(21==0)) group.long 0x54++0x03 line.long 0x00 "PORTA_PCR_21,PORTA Pin Control Register 21" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x54++0x03 line.long 0x00 "PORTA_PCR_21,PORTA Pin Control Register 21" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(21>=1)&&(21<=4)) group.long 0x54++0x03 line.long 0x00 "PORTA_PCR_21,PORTA Pin Control Register 21" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(21==5)) group.long 0x54++0x03 line.long 0x00 "PORTA_PCR_21,PORTA Pin Control Register 21" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(21==0)) group.long 0x54++0x03 line.long 0x00 "PORTA_PCR_21,PORTA Pin Control Register 21" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x54++0x03 line.long 0x00 "PORTA_PCR_21,PORTA Pin Control Register 21" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x54++0x03 line.long 0x00 "PORTA_PCR_21,PORTA Pin Control Register 21" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x54++0x03 line.long 0x00 "PORTA_PCR_21,PORTA Pin Control Register 21" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x54++0x03 line.long 0x00 "PORTA_PCR_21,PORTA Pin Control Register 21" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B else ; 0x54 - adres ; A - litera portu (A,B,C,...) ; 21 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(21>=1)&&(21<=5)) group.long 0x54++0x03 line.long 0x00 "PORTA_PCR_21,PORTA Pin Control Register 21" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(21==0)) group.long 0x54++0x03 line.long 0x00 "PORTA_PCR_21,PORTA Pin Control Register 21" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x54++0x03 line.long 0x00 "PORTA_PCR_21,PORTA Pin Control Register 21" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(21>=1)&&(21<=4)) group.long 0x54++0x03 line.long 0x00 "PORTA_PCR_21,PORTA Pin Control Register 21" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(21==5)) group.long 0x54++0x03 line.long 0x00 "PORTA_PCR_21,PORTA Pin Control Register 21" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(21==0)) group.long 0x54++0x03 line.long 0x00 "PORTA_PCR_21,PORTA Pin Control Register 21" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x54++0x03 line.long 0x00 "PORTA_PCR_21,PORTA Pin Control Register 21" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x54++0x03 line.long 0x00 "PORTA_PCR_21,PORTA Pin Control Register 21" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x54++0x03 line.long 0x00 "PORTA_PCR_21,PORTA Pin Control Register 21" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x54++0x03 line.long 0x00 "PORTA_PCR_21,PORTA Pin Control Register 21" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B endif sif cpuis("MK8?FN256V*") else endif sif cpuis("MK8?FN256V*") else endif sif cpuis("MK8?FN256V*") else ; 0x60 - adres ; A - litera portu (A,B,C,...) ; 24 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(24>=1)&&(24<=5)) group.long 0x60++0x03 line.long 0x00 "PORTA_PCR_24,PORTA Pin Control Register 24" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(24==0)) group.long 0x60++0x03 line.long 0x00 "PORTA_PCR_24,PORTA Pin Control Register 24" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x60++0x03 line.long 0x00 "PORTA_PCR_24,PORTA Pin Control Register 24" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(24>=1)&&(24<=4)) group.long 0x60++0x03 line.long 0x00 "PORTA_PCR_24,PORTA Pin Control Register 24" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(24==5)) group.long 0x60++0x03 line.long 0x00 "PORTA_PCR_24,PORTA Pin Control Register 24" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(24==0)) group.long 0x60++0x03 line.long 0x00 "PORTA_PCR_24,PORTA Pin Control Register 24" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x60++0x03 line.long 0x00 "PORTA_PCR_24,PORTA Pin Control Register 24" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x60++0x03 line.long 0x00 "PORTA_PCR_24,PORTA Pin Control Register 24" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x60++0x03 line.long 0x00 "PORTA_PCR_24,PORTA Pin Control Register 24" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x60++0x03 line.long 0x00 "PORTA_PCR_24,PORTA Pin Control Register 24" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B endif sif cpuis("MK8?FN256V*") else ; 0x64 - adres ; A - litera portu (A,B,C,...) ; 25 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(25>=1)&&(25<=5)) group.long 0x64++0x03 line.long 0x00 "PORTA_PCR_25,PORTA Pin Control Register 25" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(25==0)) group.long 0x64++0x03 line.long 0x00 "PORTA_PCR_25,PORTA Pin Control Register 25" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x64++0x03 line.long 0x00 "PORTA_PCR_25,PORTA Pin Control Register 25" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(25>=1)&&(25<=4)) group.long 0x64++0x03 line.long 0x00 "PORTA_PCR_25,PORTA Pin Control Register 25" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(25==5)) group.long 0x64++0x03 line.long 0x00 "PORTA_PCR_25,PORTA Pin Control Register 25" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(25==0)) group.long 0x64++0x03 line.long 0x00 "PORTA_PCR_25,PORTA Pin Control Register 25" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x64++0x03 line.long 0x00 "PORTA_PCR_25,PORTA Pin Control Register 25" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x64++0x03 line.long 0x00 "PORTA_PCR_25,PORTA Pin Control Register 25" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x64++0x03 line.long 0x00 "PORTA_PCR_25,PORTA Pin Control Register 25" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x64++0x03 line.long 0x00 "PORTA_PCR_25,PORTA Pin Control Register 25" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B endif sif cpuis("MK8?FN256V*") else ; 0x68 - adres ; A - litera portu (A,B,C,...) ; 26 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(26>=1)&&(26<=5)) group.long 0x68++0x03 line.long 0x00 "PORTA_PCR_26,PORTA Pin Control Register 26" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(26==0)) group.long 0x68++0x03 line.long 0x00 "PORTA_PCR_26,PORTA Pin Control Register 26" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x68++0x03 line.long 0x00 "PORTA_PCR_26,PORTA Pin Control Register 26" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(26>=1)&&(26<=4)) group.long 0x68++0x03 line.long 0x00 "PORTA_PCR_26,PORTA Pin Control Register 26" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(26==5)) group.long 0x68++0x03 line.long 0x00 "PORTA_PCR_26,PORTA Pin Control Register 26" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(26==0)) group.long 0x68++0x03 line.long 0x00 "PORTA_PCR_26,PORTA Pin Control Register 26" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x68++0x03 line.long 0x00 "PORTA_PCR_26,PORTA Pin Control Register 26" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x68++0x03 line.long 0x00 "PORTA_PCR_26,PORTA Pin Control Register 26" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x68++0x03 line.long 0x00 "PORTA_PCR_26,PORTA Pin Control Register 26" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x68++0x03 line.long 0x00 "PORTA_PCR_26,PORTA Pin Control Register 26" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B endif sif cpuis("MK8?FN256V*") else ; 0x6C - adres ; A - litera portu (A,B,C,...) ; 27 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(27>=1)&&(27<=5)) group.long 0x6C++0x03 line.long 0x00 "PORTA_PCR_27,PORTA Pin Control Register 27" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(27==0)) group.long 0x6C++0x03 line.long 0x00 "PORTA_PCR_27,PORTA Pin Control Register 27" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x6C++0x03 line.long 0x00 "PORTA_PCR_27,PORTA Pin Control Register 27" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(27>=1)&&(27<=4)) group.long 0x6C++0x03 line.long 0x00 "PORTA_PCR_27,PORTA Pin Control Register 27" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(27==5)) group.long 0x6C++0x03 line.long 0x00 "PORTA_PCR_27,PORTA Pin Control Register 27" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(27==0)) group.long 0x6C++0x03 line.long 0x00 "PORTA_PCR_27,PORTA Pin Control Register 27" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x6C++0x03 line.long 0x00 "PORTA_PCR_27,PORTA Pin Control Register 27" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x6C++0x03 line.long 0x00 "PORTA_PCR_27,PORTA Pin Control Register 27" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x6C++0x03 line.long 0x00 "PORTA_PCR_27,PORTA Pin Control Register 27" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x6C++0x03 line.long 0x00 "PORTA_PCR_27,PORTA Pin Control Register 27" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B endif sif cpuis("MK8?FN256V*") else ; 0x70 - adres ; A - litera portu (A,B,C,...) ; 28 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(28>=1)&&(28<=5)) group.long 0x70++0x03 line.long 0x00 "PORTA_PCR_28,PORTA Pin Control Register 28" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(28==0)) group.long 0x70++0x03 line.long 0x00 "PORTA_PCR_28,PORTA Pin Control Register 28" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x70++0x03 line.long 0x00 "PORTA_PCR_28,PORTA Pin Control Register 28" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(28>=1)&&(28<=4)) group.long 0x70++0x03 line.long 0x00 "PORTA_PCR_28,PORTA Pin Control Register 28" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(28==5)) group.long 0x70++0x03 line.long 0x00 "PORTA_PCR_28,PORTA Pin Control Register 28" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(28==0)) group.long 0x70++0x03 line.long 0x00 "PORTA_PCR_28,PORTA Pin Control Register 28" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x70++0x03 line.long 0x00 "PORTA_PCR_28,PORTA Pin Control Register 28" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x70++0x03 line.long 0x00 "PORTA_PCR_28,PORTA Pin Control Register 28" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x70++0x03 line.long 0x00 "PORTA_PCR_28,PORTA Pin Control Register 28" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x70++0x03 line.long 0x00 "PORTA_PCR_28,PORTA Pin Control Register 28" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B endif sif cpuis("MK8?FN256V*") ; 0x74 - adres ; A - litera portu (A,B,C,...) ; 29 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(29>=1)&&(29<=5)) group.long 0x74++0x03 line.long 0x00 "PORTA_PCR_29,PORTA Pin Control Register 29" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(29==0)) group.long 0x74++0x03 line.long 0x00 "PORTA_PCR_29,PORTA Pin Control Register 29" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x74++0x03 line.long 0x00 "PORTA_PCR_29,PORTA Pin Control Register 29" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(29>=1)&&(29<=4)) group.long 0x74++0x03 line.long 0x00 "PORTA_PCR_29,PORTA Pin Control Register 29" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(29==5)) group.long 0x74++0x03 line.long 0x00 "PORTA_PCR_29,PORTA Pin Control Register 29" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(29==0)) group.long 0x74++0x03 line.long 0x00 "PORTA_PCR_29,PORTA Pin Control Register 29" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x74++0x03 line.long 0x00 "PORTA_PCR_29,PORTA Pin Control Register 29" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x74++0x03 line.long 0x00 "PORTA_PCR_29,PORTA Pin Control Register 29" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x74++0x03 line.long 0x00 "PORTA_PCR_29,PORTA Pin Control Register 29" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x74++0x03 line.long 0x00 "PORTA_PCR_29,PORTA Pin Control Register 29" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B else ; 0x74 - adres ; A - litera portu (A,B,C,...) ; 29 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(29>=1)&&(29<=5)) group.long 0x74++0x03 line.long 0x00 "PORTA_PCR_29,PORTA Pin Control Register 29" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(29==0)) group.long 0x74++0x03 line.long 0x00 "PORTA_PCR_29,PORTA Pin Control Register 29" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x74++0x03 line.long 0x00 "PORTA_PCR_29,PORTA Pin Control Register 29" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(29>=1)&&(29<=4)) group.long 0x74++0x03 line.long 0x00 "PORTA_PCR_29,PORTA Pin Control Register 29" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(29==5)) group.long 0x74++0x03 line.long 0x00 "PORTA_PCR_29,PORTA Pin Control Register 29" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(29==0)) group.long 0x74++0x03 line.long 0x00 "PORTA_PCR_29,PORTA Pin Control Register 29" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x74++0x03 line.long 0x00 "PORTA_PCR_29,PORTA Pin Control Register 29" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x74++0x03 line.long 0x00 "PORTA_PCR_29,PORTA Pin Control Register 29" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x74++0x03 line.long 0x00 "PORTA_PCR_29,PORTA Pin Control Register 29" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x74++0x03 line.long 0x00 "PORTA_PCR_29,PORTA Pin Control Register 29" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B endif sif cpuis("MK8?FN256V*") else endif sif cpuis("MK8?FN256V*") else endif tree.end newline width 13. wgroup.long 0x80++0x07 line.long 0x00 "PORTA_GPCLR,PORTA Global Pin Control Low Register" bitfld.long 0x00 31. " GPWE_15 ,Global Pin 15 Write Enable" "Disable,Enable" bitfld.long 0x00 30. " GPWE_14 ,Global Pin 14 Write Enable" "Disable,Enable" bitfld.long 0x00 29. " GPWE_13 ,Global Pin 13 Write Enable" "Disable,Enable" bitfld.long 0x00 28. " GPWE_12 ,Global Pin 12 Write Enable" "Disable,Enable" newline bitfld.long 0x00 27. " GPWE_11 ,Global Pin 11 Write Enable" "Disable,Enable" bitfld.long 0x00 26. " GPWE_10 ,Global Pin 10 Write Enable" "Disable,Enable" sif !cpuis("MK8?FN256V*") bitfld.long 0x00 25. " GPWE_9 ,Global Pin 9 Write Enable" "Disable,Enable" bitfld.long 0x00 24. " GPWE_8 ,Global Pin 8 Write Enable" "Disable,Enable" newline bitfld.long 0x00 23. " GPWE_7 ,Global Pin 7 Write Enable" "Disable,Enable" bitfld.long 0x00 22. " GPWE_6 ,Global Pin 6 Write Enable" "Disable,Enable" endif bitfld.long 0x00 21. " GPWE_5 ,Global Pin 5 Write Enable" "Disable,Enable" bitfld.long 0x00 20. " GPWE_4 ,Global Pin 4 Write Enable" "Disable,Enable" newline bitfld.long 0x00 19. " GPWE_3 ,Global Pin 3 Write Enable" "Disable,Enable" bitfld.long 0x00 18. " GPWE_2 ,Global Pin 2 Write Enable" "Disable,Enable" bitfld.long 0x00 17. " GPWE_1 ,Global Pin 1 Write Enable" "Disable,Enable" bitfld.long 0x00 16. " GPWE_0 ,Global Pin 0 Write Enable" "Disable,Enable" newline hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global Pin Write Data" line.long 0x04 "PORTA_GPCHR,PORTA Global Pin Control High Register" bitfld.long 0x04 29. " GPWE_29 ,Global Pin 29 Write Enable" "Disable,Enable" sif !cpuis("MK8?FN256V*") bitfld.long 0x04 28. " GPWE_28 ,Global Pin 28 Write Enable" "Disable,Enable" bitfld.long 0x04 27. " GPWE_27 ,Global Pin 27 Write Enable" "Disable,Enable" bitfld.long 0x04 26. " GPWE_26 ,Global Pin 26 Write Enable" "Disable,Enable" newline bitfld.long 0x04 25. " GPWE_25 ,Global Pin 25 Write Enable" "Disable,Enable" bitfld.long 0x04 24. " GPWE_24 ,Global Pin 24 Write Enable" "Disable,Enable" endif bitfld.long 0x04 21. " GPWE_21 ,Global Pin 21 Write Enable" "Disable,Enable" bitfld.long 0x04 20. " GPWE_20 ,Global Pin 20 Write Enable" "Disable,Enable" newline bitfld.long 0x04 19. " GPWE_19 ,Global Pin 19 Write Enable" "Disable,Enable" bitfld.long 0x04 18. " GPWE_18 ,Global Pin 18 Write Enable" "Disable,Enable" bitfld.long 0x04 17. " GPWE_17 ,Global Pin 17 Write Enable" "Disable,Enable" bitfld.long 0x04 16. " GPWE_16 ,Global Pin 16 Write Enable" "Disable,Enable" newline hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global Pin Write Data" group.long 0xA0++0x03 line.long 0x00 "PORTA_ISFR,PORTA Interrupt Status Flag Register" eventfld.long 0x00 29. " ISF_29 ,Interrupt Status Flag 29 (In Digital Modes only)" "No interrupt,Interrupt" sif !cpuis("MK8?FN256V*") eventfld.long 0x00 28. " ISF_28 ,Interrupt Status Flag 28 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 27. " ISF_27 ,Interrupt Status Flag 27 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 26. " ISF_26 ,Interrupt Status Flag 26 (In Digital Modes only)" "No interrupt,Interrupt" newline eventfld.long 0x00 25. " ISF_25 ,Interrupt Status Flag 25 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 24. " ISF_24 ,Interrupt Status Flag 24 (In Digital Modes only)" "No interrupt,Interrupt" endif eventfld.long 0x00 21. " ISF_21 ,Interrupt Status Flag 21 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 20. " ISF_20 ,Interrupt Status Flag 20 (In Digital Modes only)" "No interrupt,Interrupt" newline eventfld.long 0x00 19. " ISF_19 ,Interrupt Status Flag 19 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 18. " ISF_18 ,Interrupt Status Flag 18 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 17. " ISF_17 ,Interrupt Status Flag 17 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 16. " ISF_16 ,Interrupt Status Flag 16 (In Digital Modes only)" "No interrupt,Interrupt" newline eventfld.long 0x00 15. " ISF_15 ,Interrupt Status Flag 15 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 14. " ISF_14 ,Interrupt Status Flag 14 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 13. " ISF_13 ,Interrupt Status Flag 13 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 12. " ISF_12 ,Interrupt Status Flag 12 (In Digital Modes only)" "No interrupt,Interrupt" newline eventfld.long 0x00 11. " ISF_11 ,Interrupt Status Flag 11 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 10. " ISF_10 ,Interrupt Status Flag 10 (In Digital Modes only)" "No interrupt,Interrupt" sif !cpuis("MK8?FN256V*") eventfld.long 0x00 9. " ISF_9 ,Interrupt Status Flag 9 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 8. " ISF_8 ,Interrupt Status Flag 8 (In Digital Modes only)" "No interrupt,Interrupt" newline eventfld.long 0x00 7. " ISF_7 ,Interrupt Status Flag 7 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 6. " ISF_6 ,Interrupt Status Flag 6 (In Digital Modes only)" "No interrupt,Interrupt" endif eventfld.long 0x00 5. " ISF_5 ,Interrupt Status Flag 5 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 4. " ISF_4 ,Interrupt Status Flag 4 (In Digital Modes only)" "No interrupt,Interrupt" newline eventfld.long 0x00 3. " ISF_3 ,Interrupt Status Flag 3 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 2. " ISF_2 ,Interrupt Status Flag 2 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 1. " ISF_1 ,Interrupt Status Flag 1 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 0. " ISF_0 ,Interrupt Status Flag 0 (In Digital Modes only)" "No interrupt,Interrupt" group.long 0xC0++0x0B line.long 0x00 "PORTA_DFER,Digital Filter Enable Register" bitfld.long 0x00 29. " DFE_29 ,Pin 29 digital filter enable" "Disabled,Enabled" sif !cpuis("MK8?FN256V*") bitfld.long 0x00 28. " DFE_28 ,Pin 28 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 27. " DFE_27 ,Pin 27 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 26. " DFE_26 ,Pin 26 digital filter enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " DFE_25 ,Pin 25 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 24. " DFE_24 ,Pin 24 digital filter enable" "Disabled,Enabled" endif bitfld.long 0x00 21. " DFE_21 ,Pin 21 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 20. " DFE_20 ,Pin 20 digital filter enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " DFE_19 ,Pin 19 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 18. " DFE_18 ,Pin 18 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 17. " DFE_17 ,Pin 17 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 16. " DFE_16 ,Pin 16 digital filter enable" "Disabled,Enabled" newline bitfld.long 0x00 15. " DFE_15 ,Pin 15 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 14. " DFE_14 ,Pin 14 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 13. " DFE_13 ,Pin 13 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 12. " DFE_12 ,Pin 12 digital filter enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " DFE_11 ,Pin 11 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 10. " DFE_10 ,Pin 10 digital filter enable" "Disabled,Enabled" sif !cpuis("MK8?FN256V*") bitfld.long 0x00 9. " DFE_9 ,Pin 9 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 8. " DFE_8 ,Pin 8 digital filter enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " DFE_7 ,Pin 7 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " DFE_6 ,Pin 6 digital filter enable" "Disabled,Enabled" endif bitfld.long 0x00 5. " DFE_5 ,Pin 5 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 4. " DFE_4 ,Pin 4 digital filter enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " DFE_3 ,Pin 3 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " DFE_2 ,Pin 2 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 1. " DFE_1 ,Pin 1 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 0. " DFE_0 ,Pin 0 digital filter enable" "Disabled,Enabled" line.long 0x04 "PORTA_DFCR,Digital Filter Clock Register" bitfld.long 0x04 0. " CS ,Clock source" "Bus clock,LPO clock" line.long 0x08 "PORTA_DFWR,Digital Filter Width Register" bitfld.long 0x08 0.--4. " FILT ,Filter length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "PORT_B" base ad:0x4004A000 width 13. tree "PORT B Pin Control Registers" ; 0x0 - adres ; B - litera portu (A,B,C,...) ; 0 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('B'=='A')&&(0>=1)&&(0<=5)) group.long 0x0++0x03 line.long 0x00 "PORTB_PCR_0,PORTB Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(0==0)) group.long 0x0++0x03 line.long 0x00 "PORTB_PCR_0,PORTB Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x0++0x03 line.long 0x00 "PORTB_PCR_0,PORTB Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('B'=='A')&&(0>=1)&&(0<=4)) group.long 0x0++0x03 line.long 0x00 "PORTB_PCR_0,PORTB Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(0==5)) group.long 0x0++0x03 line.long 0x00 "PORTB_PCR_0,PORTB Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(0==0)) group.long 0x0++0x03 line.long 0x00 "PORTB_PCR_0,PORTB Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x0++0x03 line.long 0x00 "PORTB_PCR_0,PORTB Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x0++0x03 line.long 0x00 "PORTB_PCR_0,PORTB Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x0++0x03 line.long 0x00 "PORTB_PCR_0,PORTB Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x0++0x03 line.long 0x00 "PORTB_PCR_0,PORTB Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x4 - adres ; B - litera portu (A,B,C,...) ; 1 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('B'=='A')&&(1>=1)&&(1<=5)) group.long 0x4++0x03 line.long 0x00 "PORTB_PCR_1,PORTB Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(1==0)) group.long 0x4++0x03 line.long 0x00 "PORTB_PCR_1,PORTB Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4++0x03 line.long 0x00 "PORTB_PCR_1,PORTB Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('B'=='A')&&(1>=1)&&(1<=4)) group.long 0x4++0x03 line.long 0x00 "PORTB_PCR_1,PORTB Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(1==5)) group.long 0x4++0x03 line.long 0x00 "PORTB_PCR_1,PORTB Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(1==0)) group.long 0x4++0x03 line.long 0x00 "PORTB_PCR_1,PORTB Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4++0x03 line.long 0x00 "PORTB_PCR_1,PORTB Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x4++0x03 line.long 0x00 "PORTB_PCR_1,PORTB Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x4++0x03 line.long 0x00 "PORTB_PCR_1,PORTB Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4++0x03 line.long 0x00 "PORTB_PCR_1,PORTB Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x8 - adres ; B - litera portu (A,B,C,...) ; 2 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('B'=='A')&&(2>=1)&&(2<=5)) group.long 0x8++0x03 line.long 0x00 "PORTB_PCR_2,PORTB Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(2==0)) group.long 0x8++0x03 line.long 0x00 "PORTB_PCR_2,PORTB Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x8++0x03 line.long 0x00 "PORTB_PCR_2,PORTB Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('B'=='A')&&(2>=1)&&(2<=4)) group.long 0x8++0x03 line.long 0x00 "PORTB_PCR_2,PORTB Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(2==5)) group.long 0x8++0x03 line.long 0x00 "PORTB_PCR_2,PORTB Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(2==0)) group.long 0x8++0x03 line.long 0x00 "PORTB_PCR_2,PORTB Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x8++0x03 line.long 0x00 "PORTB_PCR_2,PORTB Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x8++0x03 line.long 0x00 "PORTB_PCR_2,PORTB Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x8++0x03 line.long 0x00 "PORTB_PCR_2,PORTB Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x8++0x03 line.long 0x00 "PORTB_PCR_2,PORTB Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0xC - adres ; B - litera portu (A,B,C,...) ; 3 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('B'=='A')&&(3>=1)&&(3<=5)) group.long 0xC++0x03 line.long 0x00 "PORTB_PCR_3,PORTB Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(3==0)) group.long 0xC++0x03 line.long 0x00 "PORTB_PCR_3,PORTB Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0xC++0x03 line.long 0x00 "PORTB_PCR_3,PORTB Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('B'=='A')&&(3>=1)&&(3<=4)) group.long 0xC++0x03 line.long 0x00 "PORTB_PCR_3,PORTB Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(3==5)) group.long 0xC++0x03 line.long 0x00 "PORTB_PCR_3,PORTB Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(3==0)) group.long 0xC++0x03 line.long 0x00 "PORTB_PCR_3,PORTB Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0xC++0x03 line.long 0x00 "PORTB_PCR_3,PORTB Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0xC++0x03 line.long 0x00 "PORTB_PCR_3,PORTB Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0xC++0x03 line.long 0x00 "PORTB_PCR_3,PORTB Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0xC++0x03 line.long 0x00 "PORTB_PCR_3,PORTB Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x10 - adres ; B - litera portu (A,B,C,...) ; 4 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('B'=='A')&&(4>=1)&&(4<=5)) group.long 0x10++0x03 line.long 0x00 "PORTB_PCR_4,PORTB Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(4==0)) group.long 0x10++0x03 line.long 0x00 "PORTB_PCR_4,PORTB Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x10++0x03 line.long 0x00 "PORTB_PCR_4,PORTB Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('B'=='A')&&(4>=1)&&(4<=4)) group.long 0x10++0x03 line.long 0x00 "PORTB_PCR_4,PORTB Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(4==5)) group.long 0x10++0x03 line.long 0x00 "PORTB_PCR_4,PORTB Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(4==0)) group.long 0x10++0x03 line.long 0x00 "PORTB_PCR_4,PORTB Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x10++0x03 line.long 0x00 "PORTB_PCR_4,PORTB Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x10++0x03 line.long 0x00 "PORTB_PCR_4,PORTB Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x10++0x03 line.long 0x00 "PORTB_PCR_4,PORTB Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x10++0x03 line.long 0x00 "PORTB_PCR_4,PORTB Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x14 - adres ; B - litera portu (A,B,C,...) ; 5 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('B'=='A')&&(5>=1)&&(5<=5)) group.long 0x14++0x03 line.long 0x00 "PORTB_PCR_5,PORTB Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(5==0)) group.long 0x14++0x03 line.long 0x00 "PORTB_PCR_5,PORTB Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x14++0x03 line.long 0x00 "PORTB_PCR_5,PORTB Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('B'=='A')&&(5>=1)&&(5<=4)) group.long 0x14++0x03 line.long 0x00 "PORTB_PCR_5,PORTB Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(5==5)) group.long 0x14++0x03 line.long 0x00 "PORTB_PCR_5,PORTB Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(5==0)) group.long 0x14++0x03 line.long 0x00 "PORTB_PCR_5,PORTB Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x14++0x03 line.long 0x00 "PORTB_PCR_5,PORTB Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x14++0x03 line.long 0x00 "PORTB_PCR_5,PORTB Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x14++0x03 line.long 0x00 "PORTB_PCR_5,PORTB Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x14++0x03 line.long 0x00 "PORTB_PCR_5,PORTB Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x18 - adres ; B - litera portu (A,B,C,...) ; 6 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('B'=='A')&&(6>=1)&&(6<=5)) group.long 0x18++0x03 line.long 0x00 "PORTB_PCR_6,PORTB Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(6==0)) group.long 0x18++0x03 line.long 0x00 "PORTB_PCR_6,PORTB Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x18++0x03 line.long 0x00 "PORTB_PCR_6,PORTB Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('B'=='A')&&(6>=1)&&(6<=4)) group.long 0x18++0x03 line.long 0x00 "PORTB_PCR_6,PORTB Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(6==5)) group.long 0x18++0x03 line.long 0x00 "PORTB_PCR_6,PORTB Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(6==0)) group.long 0x18++0x03 line.long 0x00 "PORTB_PCR_6,PORTB Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x18++0x03 line.long 0x00 "PORTB_PCR_6,PORTB Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x18++0x03 line.long 0x00 "PORTB_PCR_6,PORTB Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x18++0x03 line.long 0x00 "PORTB_PCR_6,PORTB Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x18++0x03 line.long 0x00 "PORTB_PCR_6,PORTB Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x1C - adres ; B - litera portu (A,B,C,...) ; 7 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('B'=='A')&&(7>=1)&&(7<=5)) group.long 0x1C++0x03 line.long 0x00 "PORTB_PCR_7,PORTB Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(7==0)) group.long 0x1C++0x03 line.long 0x00 "PORTB_PCR_7,PORTB Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x1C++0x03 line.long 0x00 "PORTB_PCR_7,PORTB Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('B'=='A')&&(7>=1)&&(7<=4)) group.long 0x1C++0x03 line.long 0x00 "PORTB_PCR_7,PORTB Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(7==5)) group.long 0x1C++0x03 line.long 0x00 "PORTB_PCR_7,PORTB Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(7==0)) group.long 0x1C++0x03 line.long 0x00 "PORTB_PCR_7,PORTB Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x1C++0x03 line.long 0x00 "PORTB_PCR_7,PORTB Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x1C++0x03 line.long 0x00 "PORTB_PCR_7,PORTB Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x1C++0x03 line.long 0x00 "PORTB_PCR_7,PORTB Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x1C++0x03 line.long 0x00 "PORTB_PCR_7,PORTB Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x20 - adres ; B - litera portu (A,B,C,...) ; 8 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('B'=='A')&&(8>=1)&&(8<=5)) group.long 0x20++0x03 line.long 0x00 "PORTB_PCR_8,PORTB Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(8==0)) group.long 0x20++0x03 line.long 0x00 "PORTB_PCR_8,PORTB Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x20++0x03 line.long 0x00 "PORTB_PCR_8,PORTB Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('B'=='A')&&(8>=1)&&(8<=4)) group.long 0x20++0x03 line.long 0x00 "PORTB_PCR_8,PORTB Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(8==5)) group.long 0x20++0x03 line.long 0x00 "PORTB_PCR_8,PORTB Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(8==0)) group.long 0x20++0x03 line.long 0x00 "PORTB_PCR_8,PORTB Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x20++0x03 line.long 0x00 "PORTB_PCR_8,PORTB Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x20++0x03 line.long 0x00 "PORTB_PCR_8,PORTB Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x20++0x03 line.long 0x00 "PORTB_PCR_8,PORTB Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x20++0x03 line.long 0x00 "PORTB_PCR_8,PORTB Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x24 - adres ; B - litera portu (A,B,C,...) ; 9 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('B'=='A')&&(9>=1)&&(9<=5)) group.long 0x24++0x03 line.long 0x00 "PORTB_PCR_9,PORTB Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(9==0)) group.long 0x24++0x03 line.long 0x00 "PORTB_PCR_9,PORTB Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x24++0x03 line.long 0x00 "PORTB_PCR_9,PORTB Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('B'=='A')&&(9>=1)&&(9<=4)) group.long 0x24++0x03 line.long 0x00 "PORTB_PCR_9,PORTB Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(9==5)) group.long 0x24++0x03 line.long 0x00 "PORTB_PCR_9,PORTB Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(9==0)) group.long 0x24++0x03 line.long 0x00 "PORTB_PCR_9,PORTB Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x24++0x03 line.long 0x00 "PORTB_PCR_9,PORTB Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x24++0x03 line.long 0x00 "PORTB_PCR_9,PORTB Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x24++0x03 line.long 0x00 "PORTB_PCR_9,PORTB Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x24++0x03 line.long 0x00 "PORTB_PCR_9,PORTB Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x28 - adres ; B - litera portu (A,B,C,...) ; 10 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('B'=='A')&&(10>=1)&&(10<=5)) group.long 0x28++0x03 line.long 0x00 "PORTB_PCR_10,PORTB Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(10==0)) group.long 0x28++0x03 line.long 0x00 "PORTB_PCR_10,PORTB Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x28++0x03 line.long 0x00 "PORTB_PCR_10,PORTB Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('B'=='A')&&(10>=1)&&(10<=4)) group.long 0x28++0x03 line.long 0x00 "PORTB_PCR_10,PORTB Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(10==5)) group.long 0x28++0x03 line.long 0x00 "PORTB_PCR_10,PORTB Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(10==0)) group.long 0x28++0x03 line.long 0x00 "PORTB_PCR_10,PORTB Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x28++0x03 line.long 0x00 "PORTB_PCR_10,PORTB Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x28++0x03 line.long 0x00 "PORTB_PCR_10,PORTB Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x28++0x03 line.long 0x00 "PORTB_PCR_10,PORTB Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x28++0x03 line.long 0x00 "PORTB_PCR_10,PORTB Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x2C - adres ; B - litera portu (A,B,C,...) ; 11 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('B'=='A')&&(11>=1)&&(11<=5)) group.long 0x2C++0x03 line.long 0x00 "PORTB_PCR_11,PORTB Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(11==0)) group.long 0x2C++0x03 line.long 0x00 "PORTB_PCR_11,PORTB Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x2C++0x03 line.long 0x00 "PORTB_PCR_11,PORTB Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('B'=='A')&&(11>=1)&&(11<=4)) group.long 0x2C++0x03 line.long 0x00 "PORTB_PCR_11,PORTB Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(11==5)) group.long 0x2C++0x03 line.long 0x00 "PORTB_PCR_11,PORTB Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(11==0)) group.long 0x2C++0x03 line.long 0x00 "PORTB_PCR_11,PORTB Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x2C++0x03 line.long 0x00 "PORTB_PCR_11,PORTB Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x2C++0x03 line.long 0x00 "PORTB_PCR_11,PORTB Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x2C++0x03 line.long 0x00 "PORTB_PCR_11,PORTB Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x2C++0x03 line.long 0x00 "PORTB_PCR_11,PORTB Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x40 - adres ; B - litera portu (A,B,C,...) ; 16 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('B'=='A')&&(16>=1)&&(16<=5)) group.long 0x40++0x03 line.long 0x00 "PORTB_PCR_16,PORTB Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(16==0)) group.long 0x40++0x03 line.long 0x00 "PORTB_PCR_16,PORTB Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x40++0x03 line.long 0x00 "PORTB_PCR_16,PORTB Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('B'=='A')&&(16>=1)&&(16<=4)) group.long 0x40++0x03 line.long 0x00 "PORTB_PCR_16,PORTB Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(16==5)) group.long 0x40++0x03 line.long 0x00 "PORTB_PCR_16,PORTB Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(16==0)) group.long 0x40++0x03 line.long 0x00 "PORTB_PCR_16,PORTB Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x40++0x03 line.long 0x00 "PORTB_PCR_16,PORTB Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x40++0x03 line.long 0x00 "PORTB_PCR_16,PORTB Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x40++0x03 line.long 0x00 "PORTB_PCR_16,PORTB Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x40++0x03 line.long 0x00 "PORTB_PCR_16,PORTB Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x44 - adres ; B - litera portu (A,B,C,...) ; 17 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('B'=='A')&&(17>=1)&&(17<=5)) group.long 0x44++0x03 line.long 0x00 "PORTB_PCR_17,PORTB Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(17==0)) group.long 0x44++0x03 line.long 0x00 "PORTB_PCR_17,PORTB Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x44++0x03 line.long 0x00 "PORTB_PCR_17,PORTB Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('B'=='A')&&(17>=1)&&(17<=4)) group.long 0x44++0x03 line.long 0x00 "PORTB_PCR_17,PORTB Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(17==5)) group.long 0x44++0x03 line.long 0x00 "PORTB_PCR_17,PORTB Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(17==0)) group.long 0x44++0x03 line.long 0x00 "PORTB_PCR_17,PORTB Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x44++0x03 line.long 0x00 "PORTB_PCR_17,PORTB Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x44++0x03 line.long 0x00 "PORTB_PCR_17,PORTB Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x44++0x03 line.long 0x00 "PORTB_PCR_17,PORTB Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x44++0x03 line.long 0x00 "PORTB_PCR_17,PORTB Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x48 - adres ; B - litera portu (A,B,C,...) ; 18 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('B'=='A')&&(18>=1)&&(18<=5)) group.long 0x48++0x03 line.long 0x00 "PORTB_PCR_18,PORTB Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(18==0)) group.long 0x48++0x03 line.long 0x00 "PORTB_PCR_18,PORTB Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x48++0x03 line.long 0x00 "PORTB_PCR_18,PORTB Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('B'=='A')&&(18>=1)&&(18<=4)) group.long 0x48++0x03 line.long 0x00 "PORTB_PCR_18,PORTB Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(18==5)) group.long 0x48++0x03 line.long 0x00 "PORTB_PCR_18,PORTB Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(18==0)) group.long 0x48++0x03 line.long 0x00 "PORTB_PCR_18,PORTB Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x48++0x03 line.long 0x00 "PORTB_PCR_18,PORTB Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x48++0x03 line.long 0x00 "PORTB_PCR_18,PORTB Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x48++0x03 line.long 0x00 "PORTB_PCR_18,PORTB Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x48++0x03 line.long 0x00 "PORTB_PCR_18,PORTB Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x4C - adres ; B - litera portu (A,B,C,...) ; 19 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('B'=='A')&&(19>=1)&&(19<=5)) group.long 0x4C++0x03 line.long 0x00 "PORTB_PCR_19,PORTB Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(19==0)) group.long 0x4C++0x03 line.long 0x00 "PORTB_PCR_19,PORTB Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4C++0x03 line.long 0x00 "PORTB_PCR_19,PORTB Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('B'=='A')&&(19>=1)&&(19<=4)) group.long 0x4C++0x03 line.long 0x00 "PORTB_PCR_19,PORTB Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(19==5)) group.long 0x4C++0x03 line.long 0x00 "PORTB_PCR_19,PORTB Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(19==0)) group.long 0x4C++0x03 line.long 0x00 "PORTB_PCR_19,PORTB Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4C++0x03 line.long 0x00 "PORTB_PCR_19,PORTB Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x4C++0x03 line.long 0x00 "PORTB_PCR_19,PORTB Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x4C++0x03 line.long 0x00 "PORTB_PCR_19,PORTB Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4C++0x03 line.long 0x00 "PORTB_PCR_19,PORTB Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x50 - adres ; B - litera portu (A,B,C,...) ; 20 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('B'=='A')&&(20>=1)&&(20<=5)) group.long 0x50++0x03 line.long 0x00 "PORTB_PCR_20,PORTB Pin Control Register 20" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(20==0)) group.long 0x50++0x03 line.long 0x00 "PORTB_PCR_20,PORTB Pin Control Register 20" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x50++0x03 line.long 0x00 "PORTB_PCR_20,PORTB Pin Control Register 20" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('B'=='A')&&(20>=1)&&(20<=4)) group.long 0x50++0x03 line.long 0x00 "PORTB_PCR_20,PORTB Pin Control Register 20" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(20==5)) group.long 0x50++0x03 line.long 0x00 "PORTB_PCR_20,PORTB Pin Control Register 20" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(20==0)) group.long 0x50++0x03 line.long 0x00 "PORTB_PCR_20,PORTB Pin Control Register 20" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x50++0x03 line.long 0x00 "PORTB_PCR_20,PORTB Pin Control Register 20" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x50++0x03 line.long 0x00 "PORTB_PCR_20,PORTB Pin Control Register 20" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x50++0x03 line.long 0x00 "PORTB_PCR_20,PORTB Pin Control Register 20" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x50++0x03 line.long 0x00 "PORTB_PCR_20,PORTB Pin Control Register 20" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x54 - adres ; B - litera portu (A,B,C,...) ; 21 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('B'=='A')&&(21>=1)&&(21<=5)) group.long 0x54++0x03 line.long 0x00 "PORTB_PCR_21,PORTB Pin Control Register 21" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(21==0)) group.long 0x54++0x03 line.long 0x00 "PORTB_PCR_21,PORTB Pin Control Register 21" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x54++0x03 line.long 0x00 "PORTB_PCR_21,PORTB Pin Control Register 21" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('B'=='A')&&(21>=1)&&(21<=4)) group.long 0x54++0x03 line.long 0x00 "PORTB_PCR_21,PORTB Pin Control Register 21" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(21==5)) group.long 0x54++0x03 line.long 0x00 "PORTB_PCR_21,PORTB Pin Control Register 21" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(21==0)) group.long 0x54++0x03 line.long 0x00 "PORTB_PCR_21,PORTB Pin Control Register 21" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x54++0x03 line.long 0x00 "PORTB_PCR_21,PORTB Pin Control Register 21" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x54++0x03 line.long 0x00 "PORTB_PCR_21,PORTB Pin Control Register 21" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x54++0x03 line.long 0x00 "PORTB_PCR_21,PORTB Pin Control Register 21" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x54++0x03 line.long 0x00 "PORTB_PCR_21,PORTB Pin Control Register 21" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x58 - adres ; B - litera portu (A,B,C,...) ; 22 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('B'=='A')&&(22>=1)&&(22<=5)) group.long 0x58++0x03 line.long 0x00 "PORTB_PCR_22,PORTB Pin Control Register 22" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(22==0)) group.long 0x58++0x03 line.long 0x00 "PORTB_PCR_22,PORTB Pin Control Register 22" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x58++0x03 line.long 0x00 "PORTB_PCR_22,PORTB Pin Control Register 22" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('B'=='A')&&(22>=1)&&(22<=4)) group.long 0x58++0x03 line.long 0x00 "PORTB_PCR_22,PORTB Pin Control Register 22" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(22==5)) group.long 0x58++0x03 line.long 0x00 "PORTB_PCR_22,PORTB Pin Control Register 22" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(22==0)) group.long 0x58++0x03 line.long 0x00 "PORTB_PCR_22,PORTB Pin Control Register 22" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x58++0x03 line.long 0x00 "PORTB_PCR_22,PORTB Pin Control Register 22" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x58++0x03 line.long 0x00 "PORTB_PCR_22,PORTB Pin Control Register 22" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x58++0x03 line.long 0x00 "PORTB_PCR_22,PORTB Pin Control Register 22" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x58++0x03 line.long 0x00 "PORTB_PCR_22,PORTB Pin Control Register 22" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x5C - adres ; B - litera portu (A,B,C,...) ; 23 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('B'=='A')&&(23>=1)&&(23<=5)) group.long 0x5C++0x03 line.long 0x00 "PORTB_PCR_23,PORTB Pin Control Register 23" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(23==0)) group.long 0x5C++0x03 line.long 0x00 "PORTB_PCR_23,PORTB Pin Control Register 23" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x5C++0x03 line.long 0x00 "PORTB_PCR_23,PORTB Pin Control Register 23" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('B'=='A')&&(23>=1)&&(23<=4)) group.long 0x5C++0x03 line.long 0x00 "PORTB_PCR_23,PORTB Pin Control Register 23" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(23==5)) group.long 0x5C++0x03 line.long 0x00 "PORTB_PCR_23,PORTB Pin Control Register 23" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(23==0)) group.long 0x5C++0x03 line.long 0x00 "PORTB_PCR_23,PORTB Pin Control Register 23" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x5C++0x03 line.long 0x00 "PORTB_PCR_23,PORTB Pin Control Register 23" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x5C++0x03 line.long 0x00 "PORTB_PCR_23,PORTB Pin Control Register 23" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x5C++0x03 line.long 0x00 "PORTB_PCR_23,PORTB Pin Control Register 23" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x5C++0x03 line.long 0x00 "PORTB_PCR_23,PORTB Pin Control Register 23" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B tree.end newline width 13. wgroup.long 0x80++0x07 line.long 0x00 "PORTB_GPCLR,PORTB Global Pin Control Low Register" bitfld.long 0x00 27. " GPWE_11 ,Global Pin 11 Write Enable" "Disable,Enable" bitfld.long 0x00 26. " GPWE_10 ,Global Pin 10 Write Enable" "Disable,Enable" bitfld.long 0x00 25. " GPWE_9 ,Global Pin 9 Write Enable" "Disable,Enable" bitfld.long 0x00 24. " GPWE_8 ,Global Pin 8 Write Enable" "Disable,Enable" newline bitfld.long 0x00 23. " GPWE_7 ,Global Pin 7 Write Enable" "Disable,Enable" bitfld.long 0x00 22. " GPWE_6 ,Global Pin 6 Write Enable" "Disable,Enable" bitfld.long 0x00 21. " GPWE_5 ,Global Pin 5 Write Enable" "Disable,Enable" bitfld.long 0x00 20. " GPWE_4 ,Global Pin 4 Write Enable" "Disable,Enable" newline bitfld.long 0x00 19. " GPWE_3 ,Global Pin 3 Write Enable" "Disable,Enable" bitfld.long 0x00 18. " GPWE_2 ,Global Pin 2 Write Enable" "Disable,Enable" bitfld.long 0x00 17. " GPWE_1 ,Global Pin 1 Write Enable" "Disable,Enable" bitfld.long 0x00 16. " GPWE_0 ,Global Pin 0 Write Enable" "Disable,Enable" newline hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global Pin Write Data" line.long 0x04 "PORTB_GPCHR,PORTB Global Pin Control High Register" bitfld.long 0x04 23. " GPWE_23 ,Global Pin 23 Write Enable" "Disable,Enable" bitfld.long 0x04 22. " GPWE_22 ,Global Pin 22 Write Enable" "Disable,Enable" bitfld.long 0x04 21. " GPWE_21 ,Global Pin 21 Write Enable" "Disable,Enable" bitfld.long 0x04 20. " GPWE_20 ,Global Pin 20 Write Enable" "Disable,Enable" newline bitfld.long 0x04 19. " GPWE_19 ,Global Pin 19 Write Enable" "Disable,Enable" bitfld.long 0x04 18. " GPWE_18 ,Global Pin 18 Write Enable" "Disable,Enable" bitfld.long 0x04 17. " GPWE_17 ,Global Pin 17 Write Enable" "Disable,Enable" bitfld.long 0x04 16. " GPWE_16 ,Global Pin 16 Write Enable" "Disable,Enable" newline hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global Pin Write Data" group.long 0xA0++0x03 line.long 0x00 "PORTB_ISFR,PORTB Interrupt Status Flag Register" eventfld.long 0x00 23. " ISF_23 ,Interrupt Status Flag 23 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 22. " ISF_22 ,Interrupt Status Flag 22 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 21. " ISF_21 ,Interrupt Status Flag 21 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 20. " ISF_20 ,Interrupt Status Flag 20 (In Digital Modes only)" "No interrupt,Interrupt" newline eventfld.long 0x00 19. " ISF_19 ,Interrupt Status Flag 19 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 18. " ISF_18 ,Interrupt Status Flag 18 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 17. " ISF_17 ,Interrupt Status Flag 17 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 16. " ISF_16 ,Interrupt Status Flag 16 (In Digital Modes only)" "No interrupt,Interrupt" newline eventfld.long 0x00 11. " ISF_11 ,Interrupt Status Flag 11 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 10. " ISF_10 ,Interrupt Status Flag 10 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 9. " ISF_9 ,Interrupt Status Flag 9 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 8. " ISF_8 ,Interrupt Status Flag 8 (In Digital Modes only)" "No interrupt,Interrupt" newline eventfld.long 0x00 7. " ISF_7 ,Interrupt Status Flag 7 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 6. " ISF_6 ,Interrupt Status Flag 6 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 5. " ISF_5 ,Interrupt Status Flag 5 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 4. " ISF_4 ,Interrupt Status Flag 4 (In Digital Modes only)" "No interrupt,Interrupt" newline eventfld.long 0x00 3. " ISF_3 ,Interrupt Status Flag 3 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 2. " ISF_2 ,Interrupt Status Flag 2 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 1. " ISF_1 ,Interrupt Status Flag 1 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 0. " ISF_0 ,Interrupt Status Flag 0 (In Digital Modes only)" "No interrupt,Interrupt" group.long 0xC0++0x0B line.long 0x00 "PORTB_DFER,Digital Filter Enable Register" bitfld.long 0x00 23. " DFE_23 ,Pin 23 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 22. " DFE_22 ,Pin 22 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 21. " DFE_21 ,Pin 21 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 20. " DFE_20 ,Pin 20 digital filter enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " DFE_19 ,Pin 19 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 18. " DFE_18 ,Pin 18 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 17. " DFE_17 ,Pin 17 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 16. " DFE_16 ,Pin 16 digital filter enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " DFE_11 ,Pin 11 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 10. " DFE_10 ,Pin 10 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 9. " DFE_9 ,Pin 9 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 8. " DFE_8 ,Pin 8 digital filter enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " DFE_7 ,Pin 7 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " DFE_6 ,Pin 6 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " DFE_5 ,Pin 5 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 4. " DFE_4 ,Pin 4 digital filter enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " DFE_3 ,Pin 3 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " DFE_2 ,Pin 2 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 1. " DFE_1 ,Pin 1 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 0. " DFE_0 ,Pin 0 digital filter enable" "Disabled,Enabled" line.long 0x04 "PORTB_DFCR,Digital Filter Clock Register" bitfld.long 0x04 0. " CS ,Clock source" "Bus clock,LPO clock" line.long 0x08 "PORTB_DFWR,Digital Filter Width Register" bitfld.long 0x08 0.--4. " FILT ,Filter length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "PORT_C" base ad:0x4004B000 width 13. sif cpuis("MK8?FN256V*") tree "PORT C Pin Control Registers" ; 0x0 - adres ; C - litera portu (A,B,C,...) ; 0 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(0>=1)&&(0<=5)) group.long 0x0++0x03 line.long 0x00 "PORTC_PCR_0,PORTC Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(0==0)) group.long 0x0++0x03 line.long 0x00 "PORTC_PCR_0,PORTC Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x0++0x03 line.long 0x00 "PORTC_PCR_0,PORTC Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(0>=1)&&(0<=4)) group.long 0x0++0x03 line.long 0x00 "PORTC_PCR_0,PORTC Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(0==5)) group.long 0x0++0x03 line.long 0x00 "PORTC_PCR_0,PORTC Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(0==0)) group.long 0x0++0x03 line.long 0x00 "PORTC_PCR_0,PORTC Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x0++0x03 line.long 0x00 "PORTC_PCR_0,PORTC Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x0++0x03 line.long 0x00 "PORTC_PCR_0,PORTC Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x0++0x03 line.long 0x00 "PORTC_PCR_0,PORTC Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x0++0x03 line.long 0x00 "PORTC_PCR_0,PORTC Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x4 - adres ; C - litera portu (A,B,C,...) ; 1 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(1>=1)&&(1<=5)) group.long 0x4++0x03 line.long 0x00 "PORTC_PCR_1,PORTC Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(1==0)) group.long 0x4++0x03 line.long 0x00 "PORTC_PCR_1,PORTC Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4++0x03 line.long 0x00 "PORTC_PCR_1,PORTC Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(1>=1)&&(1<=4)) group.long 0x4++0x03 line.long 0x00 "PORTC_PCR_1,PORTC Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(1==5)) group.long 0x4++0x03 line.long 0x00 "PORTC_PCR_1,PORTC Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(1==0)) group.long 0x4++0x03 line.long 0x00 "PORTC_PCR_1,PORTC Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4++0x03 line.long 0x00 "PORTC_PCR_1,PORTC Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x4++0x03 line.long 0x00 "PORTC_PCR_1,PORTC Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x4++0x03 line.long 0x00 "PORTC_PCR_1,PORTC Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4++0x03 line.long 0x00 "PORTC_PCR_1,PORTC Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x8 - adres ; C - litera portu (A,B,C,...) ; 2 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(2>=1)&&(2<=5)) group.long 0x8++0x03 line.long 0x00 "PORTC_PCR_2,PORTC Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(2==0)) group.long 0x8++0x03 line.long 0x00 "PORTC_PCR_2,PORTC Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x8++0x03 line.long 0x00 "PORTC_PCR_2,PORTC Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(2>=1)&&(2<=4)) group.long 0x8++0x03 line.long 0x00 "PORTC_PCR_2,PORTC Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(2==5)) group.long 0x8++0x03 line.long 0x00 "PORTC_PCR_2,PORTC Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(2==0)) group.long 0x8++0x03 line.long 0x00 "PORTC_PCR_2,PORTC Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x8++0x03 line.long 0x00 "PORTC_PCR_2,PORTC Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x8++0x03 line.long 0x00 "PORTC_PCR_2,PORTC Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x8++0x03 line.long 0x00 "PORTC_PCR_2,PORTC Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x8++0x03 line.long 0x00 "PORTC_PCR_2,PORTC Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0xC - adres ; C - litera portu (A,B,C,...) ; 3 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(3>=1)&&(3<=5)) group.long 0xC++0x03 line.long 0x00 "PORTC_PCR_3,PORTC Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(3==0)) group.long 0xC++0x03 line.long 0x00 "PORTC_PCR_3,PORTC Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0xC++0x03 line.long 0x00 "PORTC_PCR_3,PORTC Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(3>=1)&&(3<=4)) group.long 0xC++0x03 line.long 0x00 "PORTC_PCR_3,PORTC Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(3==5)) group.long 0xC++0x03 line.long 0x00 "PORTC_PCR_3,PORTC Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(3==0)) group.long 0xC++0x03 line.long 0x00 "PORTC_PCR_3,PORTC Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0xC++0x03 line.long 0x00 "PORTC_PCR_3,PORTC Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0xC++0x03 line.long 0x00 "PORTC_PCR_3,PORTC Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0xC++0x03 line.long 0x00 "PORTC_PCR_3,PORTC Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0xC++0x03 line.long 0x00 "PORTC_PCR_3,PORTC Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x10 - adres ; C - litera portu (A,B,C,...) ; 4 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(4>=1)&&(4<=5)) group.long 0x10++0x03 line.long 0x00 "PORTC_PCR_4,PORTC Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(4==0)) group.long 0x10++0x03 line.long 0x00 "PORTC_PCR_4,PORTC Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x10++0x03 line.long 0x00 "PORTC_PCR_4,PORTC Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(4>=1)&&(4<=4)) group.long 0x10++0x03 line.long 0x00 "PORTC_PCR_4,PORTC Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(4==5)) group.long 0x10++0x03 line.long 0x00 "PORTC_PCR_4,PORTC Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(4==0)) group.long 0x10++0x03 line.long 0x00 "PORTC_PCR_4,PORTC Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x10++0x03 line.long 0x00 "PORTC_PCR_4,PORTC Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x10++0x03 line.long 0x00 "PORTC_PCR_4,PORTC Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x10++0x03 line.long 0x00 "PORTC_PCR_4,PORTC Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x10++0x03 line.long 0x00 "PORTC_PCR_4,PORTC Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x14 - adres ; C - litera portu (A,B,C,...) ; 5 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(5>=1)&&(5<=5)) group.long 0x14++0x03 line.long 0x00 "PORTC_PCR_5,PORTC Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(5==0)) group.long 0x14++0x03 line.long 0x00 "PORTC_PCR_5,PORTC Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x14++0x03 line.long 0x00 "PORTC_PCR_5,PORTC Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(5>=1)&&(5<=4)) group.long 0x14++0x03 line.long 0x00 "PORTC_PCR_5,PORTC Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(5==5)) group.long 0x14++0x03 line.long 0x00 "PORTC_PCR_5,PORTC Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(5==0)) group.long 0x14++0x03 line.long 0x00 "PORTC_PCR_5,PORTC Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x14++0x03 line.long 0x00 "PORTC_PCR_5,PORTC Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x14++0x03 line.long 0x00 "PORTC_PCR_5,PORTC Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x14++0x03 line.long 0x00 "PORTC_PCR_5,PORTC Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x14++0x03 line.long 0x00 "PORTC_PCR_5,PORTC Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x18 - adres ; C - litera portu (A,B,C,...) ; 6 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(6>=1)&&(6<=5)) group.long 0x18++0x03 line.long 0x00 "PORTC_PCR_6,PORTC Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(6==0)) group.long 0x18++0x03 line.long 0x00 "PORTC_PCR_6,PORTC Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x18++0x03 line.long 0x00 "PORTC_PCR_6,PORTC Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(6>=1)&&(6<=4)) group.long 0x18++0x03 line.long 0x00 "PORTC_PCR_6,PORTC Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(6==5)) group.long 0x18++0x03 line.long 0x00 "PORTC_PCR_6,PORTC Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(6==0)) group.long 0x18++0x03 line.long 0x00 "PORTC_PCR_6,PORTC Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x18++0x03 line.long 0x00 "PORTC_PCR_6,PORTC Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x18++0x03 line.long 0x00 "PORTC_PCR_6,PORTC Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x18++0x03 line.long 0x00 "PORTC_PCR_6,PORTC Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x18++0x03 line.long 0x00 "PORTC_PCR_6,PORTC Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x1C - adres ; C - litera portu (A,B,C,...) ; 7 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(7>=1)&&(7<=5)) group.long 0x1C++0x03 line.long 0x00 "PORTC_PCR_7,PORTC Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(7==0)) group.long 0x1C++0x03 line.long 0x00 "PORTC_PCR_7,PORTC Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x1C++0x03 line.long 0x00 "PORTC_PCR_7,PORTC Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(7>=1)&&(7<=4)) group.long 0x1C++0x03 line.long 0x00 "PORTC_PCR_7,PORTC Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(7==5)) group.long 0x1C++0x03 line.long 0x00 "PORTC_PCR_7,PORTC Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(7==0)) group.long 0x1C++0x03 line.long 0x00 "PORTC_PCR_7,PORTC Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x1C++0x03 line.long 0x00 "PORTC_PCR_7,PORTC Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x1C++0x03 line.long 0x00 "PORTC_PCR_7,PORTC Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x1C++0x03 line.long 0x00 "PORTC_PCR_7,PORTC Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x1C++0x03 line.long 0x00 "PORTC_PCR_7,PORTC Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x20 - adres ; C - litera portu (A,B,C,...) ; 8 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(8>=1)&&(8<=5)) group.long 0x20++0x03 line.long 0x00 "PORTC_PCR_8,PORTC Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(8==0)) group.long 0x20++0x03 line.long 0x00 "PORTC_PCR_8,PORTC Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x20++0x03 line.long 0x00 "PORTC_PCR_8,PORTC Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(8>=1)&&(8<=4)) group.long 0x20++0x03 line.long 0x00 "PORTC_PCR_8,PORTC Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(8==5)) group.long 0x20++0x03 line.long 0x00 "PORTC_PCR_8,PORTC Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(8==0)) group.long 0x20++0x03 line.long 0x00 "PORTC_PCR_8,PORTC Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x20++0x03 line.long 0x00 "PORTC_PCR_8,PORTC Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x20++0x03 line.long 0x00 "PORTC_PCR_8,PORTC Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x20++0x03 line.long 0x00 "PORTC_PCR_8,PORTC Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x20++0x03 line.long 0x00 "PORTC_PCR_8,PORTC Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x24 - adres ; C - litera portu (A,B,C,...) ; 9 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(9>=1)&&(9<=5)) group.long 0x24++0x03 line.long 0x00 "PORTC_PCR_9,PORTC Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(9==0)) group.long 0x24++0x03 line.long 0x00 "PORTC_PCR_9,PORTC Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x24++0x03 line.long 0x00 "PORTC_PCR_9,PORTC Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(9>=1)&&(9<=4)) group.long 0x24++0x03 line.long 0x00 "PORTC_PCR_9,PORTC Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(9==5)) group.long 0x24++0x03 line.long 0x00 "PORTC_PCR_9,PORTC Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(9==0)) group.long 0x24++0x03 line.long 0x00 "PORTC_PCR_9,PORTC Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x24++0x03 line.long 0x00 "PORTC_PCR_9,PORTC Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x24++0x03 line.long 0x00 "PORTC_PCR_9,PORTC Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x24++0x03 line.long 0x00 "PORTC_PCR_9,PORTC Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x24++0x03 line.long 0x00 "PORTC_PCR_9,PORTC Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x28 - adres ; C - litera portu (A,B,C,...) ; 10 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(10>=1)&&(10<=5)) group.long 0x28++0x03 line.long 0x00 "PORTC_PCR_10,PORTC Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(10==0)) group.long 0x28++0x03 line.long 0x00 "PORTC_PCR_10,PORTC Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x28++0x03 line.long 0x00 "PORTC_PCR_10,PORTC Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(10>=1)&&(10<=4)) group.long 0x28++0x03 line.long 0x00 "PORTC_PCR_10,PORTC Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(10==5)) group.long 0x28++0x03 line.long 0x00 "PORTC_PCR_10,PORTC Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(10==0)) group.long 0x28++0x03 line.long 0x00 "PORTC_PCR_10,PORTC Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x28++0x03 line.long 0x00 "PORTC_PCR_10,PORTC Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x28++0x03 line.long 0x00 "PORTC_PCR_10,PORTC Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x28++0x03 line.long 0x00 "PORTC_PCR_10,PORTC Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x28++0x03 line.long 0x00 "PORTC_PCR_10,PORTC Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x2C - adres ; C - litera portu (A,B,C,...) ; 11 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(11>=1)&&(11<=5)) group.long 0x2C++0x03 line.long 0x00 "PORTC_PCR_11,PORTC Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(11==0)) group.long 0x2C++0x03 line.long 0x00 "PORTC_PCR_11,PORTC Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x2C++0x03 line.long 0x00 "PORTC_PCR_11,PORTC Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(11>=1)&&(11<=4)) group.long 0x2C++0x03 line.long 0x00 "PORTC_PCR_11,PORTC Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(11==5)) group.long 0x2C++0x03 line.long 0x00 "PORTC_PCR_11,PORTC Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(11==0)) group.long 0x2C++0x03 line.long 0x00 "PORTC_PCR_11,PORTC Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x2C++0x03 line.long 0x00 "PORTC_PCR_11,PORTC Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x2C++0x03 line.long 0x00 "PORTC_PCR_11,PORTC Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x2C++0x03 line.long 0x00 "PORTC_PCR_11,PORTC Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x2C++0x03 line.long 0x00 "PORTC_PCR_11,PORTC Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x30 - adres ; C - litera portu (A,B,C,...) ; 12 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(12>=1)&&(12<=5)) group.long 0x30++0x03 line.long 0x00 "PORTC_PCR_12,PORTC Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(12==0)) group.long 0x30++0x03 line.long 0x00 "PORTC_PCR_12,PORTC Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x30++0x03 line.long 0x00 "PORTC_PCR_12,PORTC Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(12>=1)&&(12<=4)) group.long 0x30++0x03 line.long 0x00 "PORTC_PCR_12,PORTC Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(12==5)) group.long 0x30++0x03 line.long 0x00 "PORTC_PCR_12,PORTC Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(12==0)) group.long 0x30++0x03 line.long 0x00 "PORTC_PCR_12,PORTC Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x30++0x03 line.long 0x00 "PORTC_PCR_12,PORTC Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x30++0x03 line.long 0x00 "PORTC_PCR_12,PORTC Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x30++0x03 line.long 0x00 "PORTC_PCR_12,PORTC Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x30++0x03 line.long 0x00 "PORTC_PCR_12,PORTC Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x34 - adres ; C - litera portu (A,B,C,...) ; 13 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(13>=1)&&(13<=5)) group.long 0x34++0x03 line.long 0x00 "PORTC_PCR_13,PORTC Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(13==0)) group.long 0x34++0x03 line.long 0x00 "PORTC_PCR_13,PORTC Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x34++0x03 line.long 0x00 "PORTC_PCR_13,PORTC Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(13>=1)&&(13<=4)) group.long 0x34++0x03 line.long 0x00 "PORTC_PCR_13,PORTC Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(13==5)) group.long 0x34++0x03 line.long 0x00 "PORTC_PCR_13,PORTC Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(13==0)) group.long 0x34++0x03 line.long 0x00 "PORTC_PCR_13,PORTC Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x34++0x03 line.long 0x00 "PORTC_PCR_13,PORTC Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x34++0x03 line.long 0x00 "PORTC_PCR_13,PORTC Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x34++0x03 line.long 0x00 "PORTC_PCR_13,PORTC Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x34++0x03 line.long 0x00 "PORTC_PCR_13,PORTC Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x38 - adres ; C - litera portu (A,B,C,...) ; 14 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(14>=1)&&(14<=5)) group.long 0x38++0x03 line.long 0x00 "PORTC_PCR_14,PORTC Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(14==0)) group.long 0x38++0x03 line.long 0x00 "PORTC_PCR_14,PORTC Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x38++0x03 line.long 0x00 "PORTC_PCR_14,PORTC Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(14>=1)&&(14<=4)) group.long 0x38++0x03 line.long 0x00 "PORTC_PCR_14,PORTC Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(14==5)) group.long 0x38++0x03 line.long 0x00 "PORTC_PCR_14,PORTC Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(14==0)) group.long 0x38++0x03 line.long 0x00 "PORTC_PCR_14,PORTC Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x38++0x03 line.long 0x00 "PORTC_PCR_14,PORTC Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x38++0x03 line.long 0x00 "PORTC_PCR_14,PORTC Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x38++0x03 line.long 0x00 "PORTC_PCR_14,PORTC Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x38++0x03 line.long 0x00 "PORTC_PCR_14,PORTC Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x3C - adres ; C - litera portu (A,B,C,...) ; 15 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(15>=1)&&(15<=5)) group.long 0x3C++0x03 line.long 0x00 "PORTC_PCR_15,PORTC Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(15==0)) group.long 0x3C++0x03 line.long 0x00 "PORTC_PCR_15,PORTC Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x3C++0x03 line.long 0x00 "PORTC_PCR_15,PORTC Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(15>=1)&&(15<=4)) group.long 0x3C++0x03 line.long 0x00 "PORTC_PCR_15,PORTC Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(15==5)) group.long 0x3C++0x03 line.long 0x00 "PORTC_PCR_15,PORTC Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(15==0)) group.long 0x3C++0x03 line.long 0x00 "PORTC_PCR_15,PORTC Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x3C++0x03 line.long 0x00 "PORTC_PCR_15,PORTC Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x3C++0x03 line.long 0x00 "PORTC_PCR_15,PORTC Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x3C++0x03 line.long 0x00 "PORTC_PCR_15,PORTC Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x3C++0x03 line.long 0x00 "PORTC_PCR_15,PORTC Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x40 - adres ; C - litera portu (A,B,C,...) ; 16 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(16>=1)&&(16<=5)) group.long 0x40++0x03 line.long 0x00 "PORTC_PCR_16,PORTC Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(16==0)) group.long 0x40++0x03 line.long 0x00 "PORTC_PCR_16,PORTC Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x40++0x03 line.long 0x00 "PORTC_PCR_16,PORTC Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(16>=1)&&(16<=4)) group.long 0x40++0x03 line.long 0x00 "PORTC_PCR_16,PORTC Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(16==5)) group.long 0x40++0x03 line.long 0x00 "PORTC_PCR_16,PORTC Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(16==0)) group.long 0x40++0x03 line.long 0x00 "PORTC_PCR_16,PORTC Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x40++0x03 line.long 0x00 "PORTC_PCR_16,PORTC Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x40++0x03 line.long 0x00 "PORTC_PCR_16,PORTC Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x40++0x03 line.long 0x00 "PORTC_PCR_16,PORTC Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x40++0x03 line.long 0x00 "PORTC_PCR_16,PORTC Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x44 - adres ; C - litera portu (A,B,C,...) ; 17 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(17>=1)&&(17<=5)) group.long 0x44++0x03 line.long 0x00 "PORTC_PCR_17,PORTC Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(17==0)) group.long 0x44++0x03 line.long 0x00 "PORTC_PCR_17,PORTC Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x44++0x03 line.long 0x00 "PORTC_PCR_17,PORTC Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(17>=1)&&(17<=4)) group.long 0x44++0x03 line.long 0x00 "PORTC_PCR_17,PORTC Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(17==5)) group.long 0x44++0x03 line.long 0x00 "PORTC_PCR_17,PORTC Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(17==0)) group.long 0x44++0x03 line.long 0x00 "PORTC_PCR_17,PORTC Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x44++0x03 line.long 0x00 "PORTC_PCR_17,PORTC Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x44++0x03 line.long 0x00 "PORTC_PCR_17,PORTC Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x44++0x03 line.long 0x00 "PORTC_PCR_17,PORTC Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x44++0x03 line.long 0x00 "PORTC_PCR_17,PORTC Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x48 - adres ; C - litera portu (A,B,C,...) ; 18 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(18>=1)&&(18<=5)) group.long 0x48++0x03 line.long 0x00 "PORTC_PCR_18,PORTC Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(18==0)) group.long 0x48++0x03 line.long 0x00 "PORTC_PCR_18,PORTC Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x48++0x03 line.long 0x00 "PORTC_PCR_18,PORTC Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(18>=1)&&(18<=4)) group.long 0x48++0x03 line.long 0x00 "PORTC_PCR_18,PORTC Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(18==5)) group.long 0x48++0x03 line.long 0x00 "PORTC_PCR_18,PORTC Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(18==0)) group.long 0x48++0x03 line.long 0x00 "PORTC_PCR_18,PORTC Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x48++0x03 line.long 0x00 "PORTC_PCR_18,PORTC Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x48++0x03 line.long 0x00 "PORTC_PCR_18,PORTC Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x48++0x03 line.long 0x00 "PORTC_PCR_18,PORTC Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x48++0x03 line.long 0x00 "PORTC_PCR_18,PORTC Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x4C - adres ; C - litera portu (A,B,C,...) ; 19 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(19>=1)&&(19<=5)) group.long 0x4C++0x03 line.long 0x00 "PORTC_PCR_19,PORTC Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(19==0)) group.long 0x4C++0x03 line.long 0x00 "PORTC_PCR_19,PORTC Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4C++0x03 line.long 0x00 "PORTC_PCR_19,PORTC Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(19>=1)&&(19<=4)) group.long 0x4C++0x03 line.long 0x00 "PORTC_PCR_19,PORTC Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(19==5)) group.long 0x4C++0x03 line.long 0x00 "PORTC_PCR_19,PORTC Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(19==0)) group.long 0x4C++0x03 line.long 0x00 "PORTC_PCR_19,PORTC Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4C++0x03 line.long 0x00 "PORTC_PCR_19,PORTC Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x4C++0x03 line.long 0x00 "PORTC_PCR_19,PORTC Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x4C++0x03 line.long 0x00 "PORTC_PCR_19,PORTC Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4C++0x03 line.long 0x00 "PORTC_PCR_19,PORTC Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B tree.end newline width 13. wgroup.long 0x80++0x07 line.long 0x00 "PORTC_GPCLR,PORTC Global Pin Control Low Register" bitfld.long 0x00 31. " GPWE_15 ,Global Pin 15 Write Enable" "Disable,Enable" bitfld.long 0x00 30. " GPWE_14 ,Global Pin 14 Write Enable" "Disable,Enable" bitfld.long 0x00 29. " GPWE_13 ,Global Pin 13 Write Enable" "Disable,Enable" bitfld.long 0x00 28. " GPWE_12 ,Global Pin 12 Write Enable" "Disable,Enable" newline bitfld.long 0x00 27. " GPWE_11 ,Global Pin 11 Write Enable" "Disable,Enable" bitfld.long 0x00 26. " GPWE_10 ,Global Pin 10 Write Enable" "Disable,Enable" bitfld.long 0x00 25. " GPWE_9 ,Global Pin 9 Write Enable" "Disable,Enable" bitfld.long 0x00 24. " GPWE_8 ,Global Pin 8 Write Enable" "Disable,Enable" newline bitfld.long 0x00 23. " GPWE_7 ,Global Pin 7 Write Enable" "Disable,Enable" bitfld.long 0x00 22. " GPWE_6 ,Global Pin 6 Write Enable" "Disable,Enable" bitfld.long 0x00 21. " GPWE_5 ,Global Pin 5 Write Enable" "Disable,Enable" bitfld.long 0x00 20. " GPWE_4 ,Global Pin 4 Write Enable" "Disable,Enable" newline bitfld.long 0x00 19. " GPWE_3 ,Global Pin 3 Write Enable" "Disable,Enable" bitfld.long 0x00 18. " GPWE_2 ,Global Pin 2 Write Enable" "Disable,Enable" bitfld.long 0x00 17. " GPWE_1 ,Global Pin 1 Write Enable" "Disable,Enable" bitfld.long 0x00 16. " GPWE_0 ,Global Pin 0 Write Enable" "Disable,Enable" newline hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global Pin Write Data" line.long 0x04 "PORTC_GPCHR,PORTC Global Pin Control High Register" bitfld.long 0x04 19. " GPWE_19 ,Global Pin 19 Write Enable" "Disable,Enable" bitfld.long 0x04 18. " GPWE_18 ,Global Pin 18 Write Enable" "Disable,Enable" bitfld.long 0x04 17. " GPWE_17 ,Global Pin 17 Write Enable" "Disable,Enable" bitfld.long 0x04 16. " GPWE_16 ,Global Pin 16 Write Enable" "Disable,Enable" newline hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global Pin Write Data" group.long 0xA0++0x03 line.long 0x00 "PORTC_ISFR,PORTC Interrupt Status Flag Register" eventfld.long 0x00 19. " ISF_19 ,Interrupt Status Flag 19 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 18. " ISF_18 ,Interrupt Status Flag 18 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 17. " ISF_17 ,Interrupt Status Flag 17 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 16. " ISF_16 ,Interrupt Status Flag 16 (In Digital Modes only)" "No interrupt,Interrupt" newline eventfld.long 0x00 15. " ISF_15 ,Interrupt Status Flag 15 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 14. " ISF_14 ,Interrupt Status Flag 14 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 13. " ISF_13 ,Interrupt Status Flag 13 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 12. " ISF_12 ,Interrupt Status Flag 12 (In Digital Modes only)" "No interrupt,Interrupt" newline eventfld.long 0x00 11. " ISF_11 ,Interrupt Status Flag 11 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 10. " ISF_10 ,Interrupt Status Flag 10 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 9. " ISF_9 ,Interrupt Status Flag 9 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 8. " ISF_8 ,Interrupt Status Flag 8 (In Digital Modes only)" "No interrupt,Interrupt" newline eventfld.long 0x00 7. " ISF_7 ,Interrupt Status Flag 7 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 6. " ISF_6 ,Interrupt Status Flag 6 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 5. " ISF_5 ,Interrupt Status Flag 5 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 4. " ISF_4 ,Interrupt Status Flag 4 (In Digital Modes only)" "No interrupt,Interrupt" newline eventfld.long 0x00 3. " ISF_3 ,Interrupt Status Flag 3 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 2. " ISF_2 ,Interrupt Status Flag 2 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 1. " ISF_1 ,Interrupt Status Flag 1 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 0. " ISF_0 ,Interrupt Status Flag 0 (In Digital Modes only)" "No interrupt,Interrupt" group.long 0xC0++0x0B line.long 0x00 "PORTC_DFER,Digital Filter Enable Register" bitfld.long 0x00 19. " DFE_19 ,Pin 19 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 18. " DFE_18 ,Pin 18 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 17. " DFE_17 ,Pin 17 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 16. " DFE_16 ,Pin 16 digital filter enable" "Disabled,Enabled" newline bitfld.long 0x00 15. " DFE_15 ,Pin 15 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 14. " DFE_14 ,Pin 14 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 13. " DFE_13 ,Pin 13 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 12. " DFE_12 ,Pin 12 digital filter enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " DFE_11 ,Pin 11 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 10. " DFE_10 ,Pin 10 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 9. " DFE_9 ,Pin 9 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 8. " DFE_8 ,Pin 8 digital filter enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " DFE_7 ,Pin 7 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " DFE_6 ,Pin 6 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " DFE_5 ,Pin 5 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 4. " DFE_4 ,Pin 4 digital filter enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " DFE_3 ,Pin 3 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " DFE_2 ,Pin 2 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 1. " DFE_1 ,Pin 1 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 0. " DFE_0 ,Pin 0 digital filter enable" "Disabled,Enabled" line.long 0x04 "PORTC_DFCR,Digital Filter Clock Register" bitfld.long 0x04 0. " CS ,Clock source" "Bus clock,LPO clock" line.long 0x08 "PORTC_DFWR,Digital Filter Width Register" bitfld.long 0x08 0.--4. " FILT ,Filter length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else tree "PORT C Pin Control Registers" ; 0x0 - adres ; C - litera portu (A,B,C,...) ; 0 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(0>=1)&&(0<=5)) group.long 0x0++0x03 line.long 0x00 "PORTC_PCR_0,PORTC Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(0==0)) group.long 0x0++0x03 line.long 0x00 "PORTC_PCR_0,PORTC Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x0++0x03 line.long 0x00 "PORTC_PCR_0,PORTC Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(0>=1)&&(0<=4)) group.long 0x0++0x03 line.long 0x00 "PORTC_PCR_0,PORTC Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(0==5)) group.long 0x0++0x03 line.long 0x00 "PORTC_PCR_0,PORTC Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(0==0)) group.long 0x0++0x03 line.long 0x00 "PORTC_PCR_0,PORTC Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x0++0x03 line.long 0x00 "PORTC_PCR_0,PORTC Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x0++0x03 line.long 0x00 "PORTC_PCR_0,PORTC Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x0++0x03 line.long 0x00 "PORTC_PCR_0,PORTC Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x0++0x03 line.long 0x00 "PORTC_PCR_0,PORTC Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x4 - adres ; C - litera portu (A,B,C,...) ; 1 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(1>=1)&&(1<=5)) group.long 0x4++0x03 line.long 0x00 "PORTC_PCR_1,PORTC Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(1==0)) group.long 0x4++0x03 line.long 0x00 "PORTC_PCR_1,PORTC Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4++0x03 line.long 0x00 "PORTC_PCR_1,PORTC Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(1>=1)&&(1<=4)) group.long 0x4++0x03 line.long 0x00 "PORTC_PCR_1,PORTC Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(1==5)) group.long 0x4++0x03 line.long 0x00 "PORTC_PCR_1,PORTC Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(1==0)) group.long 0x4++0x03 line.long 0x00 "PORTC_PCR_1,PORTC Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4++0x03 line.long 0x00 "PORTC_PCR_1,PORTC Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x4++0x03 line.long 0x00 "PORTC_PCR_1,PORTC Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x4++0x03 line.long 0x00 "PORTC_PCR_1,PORTC Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4++0x03 line.long 0x00 "PORTC_PCR_1,PORTC Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x8 - adres ; C - litera portu (A,B,C,...) ; 2 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(2>=1)&&(2<=5)) group.long 0x8++0x03 line.long 0x00 "PORTC_PCR_2,PORTC Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(2==0)) group.long 0x8++0x03 line.long 0x00 "PORTC_PCR_2,PORTC Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x8++0x03 line.long 0x00 "PORTC_PCR_2,PORTC Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(2>=1)&&(2<=4)) group.long 0x8++0x03 line.long 0x00 "PORTC_PCR_2,PORTC Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(2==5)) group.long 0x8++0x03 line.long 0x00 "PORTC_PCR_2,PORTC Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(2==0)) group.long 0x8++0x03 line.long 0x00 "PORTC_PCR_2,PORTC Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x8++0x03 line.long 0x00 "PORTC_PCR_2,PORTC Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x8++0x03 line.long 0x00 "PORTC_PCR_2,PORTC Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x8++0x03 line.long 0x00 "PORTC_PCR_2,PORTC Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x8++0x03 line.long 0x00 "PORTC_PCR_2,PORTC Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0xC - adres ; C - litera portu (A,B,C,...) ; 3 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(3>=1)&&(3<=5)) group.long 0xC++0x03 line.long 0x00 "PORTC_PCR_3,PORTC Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(3==0)) group.long 0xC++0x03 line.long 0x00 "PORTC_PCR_3,PORTC Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0xC++0x03 line.long 0x00 "PORTC_PCR_3,PORTC Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(3>=1)&&(3<=4)) group.long 0xC++0x03 line.long 0x00 "PORTC_PCR_3,PORTC Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(3==5)) group.long 0xC++0x03 line.long 0x00 "PORTC_PCR_3,PORTC Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(3==0)) group.long 0xC++0x03 line.long 0x00 "PORTC_PCR_3,PORTC Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0xC++0x03 line.long 0x00 "PORTC_PCR_3,PORTC Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0xC++0x03 line.long 0x00 "PORTC_PCR_3,PORTC Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0xC++0x03 line.long 0x00 "PORTC_PCR_3,PORTC Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0xC++0x03 line.long 0x00 "PORTC_PCR_3,PORTC Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x10 - adres ; C - litera portu (A,B,C,...) ; 4 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(4>=1)&&(4<=5)) group.long 0x10++0x03 line.long 0x00 "PORTC_PCR_4,PORTC Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(4==0)) group.long 0x10++0x03 line.long 0x00 "PORTC_PCR_4,PORTC Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x10++0x03 line.long 0x00 "PORTC_PCR_4,PORTC Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(4>=1)&&(4<=4)) group.long 0x10++0x03 line.long 0x00 "PORTC_PCR_4,PORTC Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(4==5)) group.long 0x10++0x03 line.long 0x00 "PORTC_PCR_4,PORTC Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(4==0)) group.long 0x10++0x03 line.long 0x00 "PORTC_PCR_4,PORTC Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x10++0x03 line.long 0x00 "PORTC_PCR_4,PORTC Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x10++0x03 line.long 0x00 "PORTC_PCR_4,PORTC Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x10++0x03 line.long 0x00 "PORTC_PCR_4,PORTC Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x10++0x03 line.long 0x00 "PORTC_PCR_4,PORTC Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x14 - adres ; C - litera portu (A,B,C,...) ; 5 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(5>=1)&&(5<=5)) group.long 0x14++0x03 line.long 0x00 "PORTC_PCR_5,PORTC Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(5==0)) group.long 0x14++0x03 line.long 0x00 "PORTC_PCR_5,PORTC Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x14++0x03 line.long 0x00 "PORTC_PCR_5,PORTC Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(5>=1)&&(5<=4)) group.long 0x14++0x03 line.long 0x00 "PORTC_PCR_5,PORTC Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(5==5)) group.long 0x14++0x03 line.long 0x00 "PORTC_PCR_5,PORTC Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(5==0)) group.long 0x14++0x03 line.long 0x00 "PORTC_PCR_5,PORTC Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x14++0x03 line.long 0x00 "PORTC_PCR_5,PORTC Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x14++0x03 line.long 0x00 "PORTC_PCR_5,PORTC Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x14++0x03 line.long 0x00 "PORTC_PCR_5,PORTC Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x14++0x03 line.long 0x00 "PORTC_PCR_5,PORTC Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x18 - adres ; C - litera portu (A,B,C,...) ; 6 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(6>=1)&&(6<=5)) group.long 0x18++0x03 line.long 0x00 "PORTC_PCR_6,PORTC Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(6==0)) group.long 0x18++0x03 line.long 0x00 "PORTC_PCR_6,PORTC Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x18++0x03 line.long 0x00 "PORTC_PCR_6,PORTC Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(6>=1)&&(6<=4)) group.long 0x18++0x03 line.long 0x00 "PORTC_PCR_6,PORTC Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(6==5)) group.long 0x18++0x03 line.long 0x00 "PORTC_PCR_6,PORTC Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(6==0)) group.long 0x18++0x03 line.long 0x00 "PORTC_PCR_6,PORTC Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x18++0x03 line.long 0x00 "PORTC_PCR_6,PORTC Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x18++0x03 line.long 0x00 "PORTC_PCR_6,PORTC Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x18++0x03 line.long 0x00 "PORTC_PCR_6,PORTC Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x18++0x03 line.long 0x00 "PORTC_PCR_6,PORTC Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x1C - adres ; C - litera portu (A,B,C,...) ; 7 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(7>=1)&&(7<=5)) group.long 0x1C++0x03 line.long 0x00 "PORTC_PCR_7,PORTC Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(7==0)) group.long 0x1C++0x03 line.long 0x00 "PORTC_PCR_7,PORTC Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x1C++0x03 line.long 0x00 "PORTC_PCR_7,PORTC Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(7>=1)&&(7<=4)) group.long 0x1C++0x03 line.long 0x00 "PORTC_PCR_7,PORTC Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(7==5)) group.long 0x1C++0x03 line.long 0x00 "PORTC_PCR_7,PORTC Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(7==0)) group.long 0x1C++0x03 line.long 0x00 "PORTC_PCR_7,PORTC Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x1C++0x03 line.long 0x00 "PORTC_PCR_7,PORTC Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x1C++0x03 line.long 0x00 "PORTC_PCR_7,PORTC Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x1C++0x03 line.long 0x00 "PORTC_PCR_7,PORTC Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x1C++0x03 line.long 0x00 "PORTC_PCR_7,PORTC Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x20 - adres ; C - litera portu (A,B,C,...) ; 8 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(8>=1)&&(8<=5)) group.long 0x20++0x03 line.long 0x00 "PORTC_PCR_8,PORTC Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(8==0)) group.long 0x20++0x03 line.long 0x00 "PORTC_PCR_8,PORTC Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x20++0x03 line.long 0x00 "PORTC_PCR_8,PORTC Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(8>=1)&&(8<=4)) group.long 0x20++0x03 line.long 0x00 "PORTC_PCR_8,PORTC Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(8==5)) group.long 0x20++0x03 line.long 0x00 "PORTC_PCR_8,PORTC Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(8==0)) group.long 0x20++0x03 line.long 0x00 "PORTC_PCR_8,PORTC Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x20++0x03 line.long 0x00 "PORTC_PCR_8,PORTC Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x20++0x03 line.long 0x00 "PORTC_PCR_8,PORTC Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x20++0x03 line.long 0x00 "PORTC_PCR_8,PORTC Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x20++0x03 line.long 0x00 "PORTC_PCR_8,PORTC Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x24 - adres ; C - litera portu (A,B,C,...) ; 9 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(9>=1)&&(9<=5)) group.long 0x24++0x03 line.long 0x00 "PORTC_PCR_9,PORTC Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(9==0)) group.long 0x24++0x03 line.long 0x00 "PORTC_PCR_9,PORTC Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x24++0x03 line.long 0x00 "PORTC_PCR_9,PORTC Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(9>=1)&&(9<=4)) group.long 0x24++0x03 line.long 0x00 "PORTC_PCR_9,PORTC Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(9==5)) group.long 0x24++0x03 line.long 0x00 "PORTC_PCR_9,PORTC Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(9==0)) group.long 0x24++0x03 line.long 0x00 "PORTC_PCR_9,PORTC Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x24++0x03 line.long 0x00 "PORTC_PCR_9,PORTC Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x24++0x03 line.long 0x00 "PORTC_PCR_9,PORTC Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x24++0x03 line.long 0x00 "PORTC_PCR_9,PORTC Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x24++0x03 line.long 0x00 "PORTC_PCR_9,PORTC Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x28 - adres ; C - litera portu (A,B,C,...) ; 10 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(10>=1)&&(10<=5)) group.long 0x28++0x03 line.long 0x00 "PORTC_PCR_10,PORTC Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(10==0)) group.long 0x28++0x03 line.long 0x00 "PORTC_PCR_10,PORTC Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x28++0x03 line.long 0x00 "PORTC_PCR_10,PORTC Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(10>=1)&&(10<=4)) group.long 0x28++0x03 line.long 0x00 "PORTC_PCR_10,PORTC Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(10==5)) group.long 0x28++0x03 line.long 0x00 "PORTC_PCR_10,PORTC Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(10==0)) group.long 0x28++0x03 line.long 0x00 "PORTC_PCR_10,PORTC Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x28++0x03 line.long 0x00 "PORTC_PCR_10,PORTC Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x28++0x03 line.long 0x00 "PORTC_PCR_10,PORTC Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x28++0x03 line.long 0x00 "PORTC_PCR_10,PORTC Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x28++0x03 line.long 0x00 "PORTC_PCR_10,PORTC Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x2C - adres ; C - litera portu (A,B,C,...) ; 11 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(11>=1)&&(11<=5)) group.long 0x2C++0x03 line.long 0x00 "PORTC_PCR_11,PORTC Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(11==0)) group.long 0x2C++0x03 line.long 0x00 "PORTC_PCR_11,PORTC Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x2C++0x03 line.long 0x00 "PORTC_PCR_11,PORTC Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(11>=1)&&(11<=4)) group.long 0x2C++0x03 line.long 0x00 "PORTC_PCR_11,PORTC Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(11==5)) group.long 0x2C++0x03 line.long 0x00 "PORTC_PCR_11,PORTC Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(11==0)) group.long 0x2C++0x03 line.long 0x00 "PORTC_PCR_11,PORTC Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x2C++0x03 line.long 0x00 "PORTC_PCR_11,PORTC Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x2C++0x03 line.long 0x00 "PORTC_PCR_11,PORTC Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x2C++0x03 line.long 0x00 "PORTC_PCR_11,PORTC Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x2C++0x03 line.long 0x00 "PORTC_PCR_11,PORTC Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x30 - adres ; C - litera portu (A,B,C,...) ; 12 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(12>=1)&&(12<=5)) group.long 0x30++0x03 line.long 0x00 "PORTC_PCR_12,PORTC Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(12==0)) group.long 0x30++0x03 line.long 0x00 "PORTC_PCR_12,PORTC Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x30++0x03 line.long 0x00 "PORTC_PCR_12,PORTC Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(12>=1)&&(12<=4)) group.long 0x30++0x03 line.long 0x00 "PORTC_PCR_12,PORTC Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(12==5)) group.long 0x30++0x03 line.long 0x00 "PORTC_PCR_12,PORTC Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(12==0)) group.long 0x30++0x03 line.long 0x00 "PORTC_PCR_12,PORTC Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x30++0x03 line.long 0x00 "PORTC_PCR_12,PORTC Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x30++0x03 line.long 0x00 "PORTC_PCR_12,PORTC Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x30++0x03 line.long 0x00 "PORTC_PCR_12,PORTC Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x30++0x03 line.long 0x00 "PORTC_PCR_12,PORTC Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x34 - adres ; C - litera portu (A,B,C,...) ; 13 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(13>=1)&&(13<=5)) group.long 0x34++0x03 line.long 0x00 "PORTC_PCR_13,PORTC Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(13==0)) group.long 0x34++0x03 line.long 0x00 "PORTC_PCR_13,PORTC Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x34++0x03 line.long 0x00 "PORTC_PCR_13,PORTC Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(13>=1)&&(13<=4)) group.long 0x34++0x03 line.long 0x00 "PORTC_PCR_13,PORTC Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(13==5)) group.long 0x34++0x03 line.long 0x00 "PORTC_PCR_13,PORTC Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(13==0)) group.long 0x34++0x03 line.long 0x00 "PORTC_PCR_13,PORTC Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x34++0x03 line.long 0x00 "PORTC_PCR_13,PORTC Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x34++0x03 line.long 0x00 "PORTC_PCR_13,PORTC Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x34++0x03 line.long 0x00 "PORTC_PCR_13,PORTC Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x34++0x03 line.long 0x00 "PORTC_PCR_13,PORTC Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x38 - adres ; C - litera portu (A,B,C,...) ; 14 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(14>=1)&&(14<=5)) group.long 0x38++0x03 line.long 0x00 "PORTC_PCR_14,PORTC Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(14==0)) group.long 0x38++0x03 line.long 0x00 "PORTC_PCR_14,PORTC Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x38++0x03 line.long 0x00 "PORTC_PCR_14,PORTC Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(14>=1)&&(14<=4)) group.long 0x38++0x03 line.long 0x00 "PORTC_PCR_14,PORTC Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(14==5)) group.long 0x38++0x03 line.long 0x00 "PORTC_PCR_14,PORTC Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(14==0)) group.long 0x38++0x03 line.long 0x00 "PORTC_PCR_14,PORTC Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x38++0x03 line.long 0x00 "PORTC_PCR_14,PORTC Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x38++0x03 line.long 0x00 "PORTC_PCR_14,PORTC Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x38++0x03 line.long 0x00 "PORTC_PCR_14,PORTC Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x38++0x03 line.long 0x00 "PORTC_PCR_14,PORTC Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x3C - adres ; C - litera portu (A,B,C,...) ; 15 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(15>=1)&&(15<=5)) group.long 0x3C++0x03 line.long 0x00 "PORTC_PCR_15,PORTC Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(15==0)) group.long 0x3C++0x03 line.long 0x00 "PORTC_PCR_15,PORTC Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x3C++0x03 line.long 0x00 "PORTC_PCR_15,PORTC Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(15>=1)&&(15<=4)) group.long 0x3C++0x03 line.long 0x00 "PORTC_PCR_15,PORTC Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(15==5)) group.long 0x3C++0x03 line.long 0x00 "PORTC_PCR_15,PORTC Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(15==0)) group.long 0x3C++0x03 line.long 0x00 "PORTC_PCR_15,PORTC Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x3C++0x03 line.long 0x00 "PORTC_PCR_15,PORTC Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x3C++0x03 line.long 0x00 "PORTC_PCR_15,PORTC Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x3C++0x03 line.long 0x00 "PORTC_PCR_15,PORTC Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x3C++0x03 line.long 0x00 "PORTC_PCR_15,PORTC Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x40 - adres ; C - litera portu (A,B,C,...) ; 16 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(16>=1)&&(16<=5)) group.long 0x40++0x03 line.long 0x00 "PORTC_PCR_16,PORTC Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(16==0)) group.long 0x40++0x03 line.long 0x00 "PORTC_PCR_16,PORTC Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x40++0x03 line.long 0x00 "PORTC_PCR_16,PORTC Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(16>=1)&&(16<=4)) group.long 0x40++0x03 line.long 0x00 "PORTC_PCR_16,PORTC Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(16==5)) group.long 0x40++0x03 line.long 0x00 "PORTC_PCR_16,PORTC Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(16==0)) group.long 0x40++0x03 line.long 0x00 "PORTC_PCR_16,PORTC Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x40++0x03 line.long 0x00 "PORTC_PCR_16,PORTC Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x40++0x03 line.long 0x00 "PORTC_PCR_16,PORTC Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x40++0x03 line.long 0x00 "PORTC_PCR_16,PORTC Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x40++0x03 line.long 0x00 "PORTC_PCR_16,PORTC Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x44 - adres ; C - litera portu (A,B,C,...) ; 17 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(17>=1)&&(17<=5)) group.long 0x44++0x03 line.long 0x00 "PORTC_PCR_17,PORTC Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(17==0)) group.long 0x44++0x03 line.long 0x00 "PORTC_PCR_17,PORTC Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x44++0x03 line.long 0x00 "PORTC_PCR_17,PORTC Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(17>=1)&&(17<=4)) group.long 0x44++0x03 line.long 0x00 "PORTC_PCR_17,PORTC Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(17==5)) group.long 0x44++0x03 line.long 0x00 "PORTC_PCR_17,PORTC Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(17==0)) group.long 0x44++0x03 line.long 0x00 "PORTC_PCR_17,PORTC Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x44++0x03 line.long 0x00 "PORTC_PCR_17,PORTC Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x44++0x03 line.long 0x00 "PORTC_PCR_17,PORTC Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x44++0x03 line.long 0x00 "PORTC_PCR_17,PORTC Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x44++0x03 line.long 0x00 "PORTC_PCR_17,PORTC Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x48 - adres ; C - litera portu (A,B,C,...) ; 18 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(18>=1)&&(18<=5)) group.long 0x48++0x03 line.long 0x00 "PORTC_PCR_18,PORTC Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(18==0)) group.long 0x48++0x03 line.long 0x00 "PORTC_PCR_18,PORTC Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x48++0x03 line.long 0x00 "PORTC_PCR_18,PORTC Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(18>=1)&&(18<=4)) group.long 0x48++0x03 line.long 0x00 "PORTC_PCR_18,PORTC Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(18==5)) group.long 0x48++0x03 line.long 0x00 "PORTC_PCR_18,PORTC Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(18==0)) group.long 0x48++0x03 line.long 0x00 "PORTC_PCR_18,PORTC Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x48++0x03 line.long 0x00 "PORTC_PCR_18,PORTC Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x48++0x03 line.long 0x00 "PORTC_PCR_18,PORTC Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x48++0x03 line.long 0x00 "PORTC_PCR_18,PORTC Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x48++0x03 line.long 0x00 "PORTC_PCR_18,PORTC Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x4C - adres ; C - litera portu (A,B,C,...) ; 19 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(19>=1)&&(19<=5)) group.long 0x4C++0x03 line.long 0x00 "PORTC_PCR_19,PORTC Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(19==0)) group.long 0x4C++0x03 line.long 0x00 "PORTC_PCR_19,PORTC Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4C++0x03 line.long 0x00 "PORTC_PCR_19,PORTC Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(19>=1)&&(19<=4)) group.long 0x4C++0x03 line.long 0x00 "PORTC_PCR_19,PORTC Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(19==5)) group.long 0x4C++0x03 line.long 0x00 "PORTC_PCR_19,PORTC Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(19==0)) group.long 0x4C++0x03 line.long 0x00 "PORTC_PCR_19,PORTC Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4C++0x03 line.long 0x00 "PORTC_PCR_19,PORTC Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x4C++0x03 line.long 0x00 "PORTC_PCR_19,PORTC Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x4C++0x03 line.long 0x00 "PORTC_PCR_19,PORTC Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4C++0x03 line.long 0x00 "PORTC_PCR_19,PORTC Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x60 - adres ; C - litera portu (A,B,C,...) ; 24 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(24>=1)&&(24<=5)) group.long 0x60++0x03 line.long 0x00 "PORTC_PCR_24,PORTC Pin Control Register 24" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(24==0)) group.long 0x60++0x03 line.long 0x00 "PORTC_PCR_24,PORTC Pin Control Register 24" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x60++0x03 line.long 0x00 "PORTC_PCR_24,PORTC Pin Control Register 24" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(24>=1)&&(24<=4)) group.long 0x60++0x03 line.long 0x00 "PORTC_PCR_24,PORTC Pin Control Register 24" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(24==5)) group.long 0x60++0x03 line.long 0x00 "PORTC_PCR_24,PORTC Pin Control Register 24" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(24==0)) group.long 0x60++0x03 line.long 0x00 "PORTC_PCR_24,PORTC Pin Control Register 24" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x60++0x03 line.long 0x00 "PORTC_PCR_24,PORTC Pin Control Register 24" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x60++0x03 line.long 0x00 "PORTC_PCR_24,PORTC Pin Control Register 24" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x60++0x03 line.long 0x00 "PORTC_PCR_24,PORTC Pin Control Register 24" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x60++0x03 line.long 0x00 "PORTC_PCR_24,PORTC Pin Control Register 24" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x64 - adres ; C - litera portu (A,B,C,...) ; 25 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(25>=1)&&(25<=5)) group.long 0x64++0x03 line.long 0x00 "PORTC_PCR_25,PORTC Pin Control Register 25" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(25==0)) group.long 0x64++0x03 line.long 0x00 "PORTC_PCR_25,PORTC Pin Control Register 25" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x64++0x03 line.long 0x00 "PORTC_PCR_25,PORTC Pin Control Register 25" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(25>=1)&&(25<=4)) group.long 0x64++0x03 line.long 0x00 "PORTC_PCR_25,PORTC Pin Control Register 25" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(25==5)) group.long 0x64++0x03 line.long 0x00 "PORTC_PCR_25,PORTC Pin Control Register 25" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(25==0)) group.long 0x64++0x03 line.long 0x00 "PORTC_PCR_25,PORTC Pin Control Register 25" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x64++0x03 line.long 0x00 "PORTC_PCR_25,PORTC Pin Control Register 25" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x64++0x03 line.long 0x00 "PORTC_PCR_25,PORTC Pin Control Register 25" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x64++0x03 line.long 0x00 "PORTC_PCR_25,PORTC Pin Control Register 25" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x64++0x03 line.long 0x00 "PORTC_PCR_25,PORTC Pin Control Register 25" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x68 - adres ; C - litera portu (A,B,C,...) ; 26 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(26>=1)&&(26<=5)) group.long 0x68++0x03 line.long 0x00 "PORTC_PCR_26,PORTC Pin Control Register 26" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(26==0)) group.long 0x68++0x03 line.long 0x00 "PORTC_PCR_26,PORTC Pin Control Register 26" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x68++0x03 line.long 0x00 "PORTC_PCR_26,PORTC Pin Control Register 26" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(26>=1)&&(26<=4)) group.long 0x68++0x03 line.long 0x00 "PORTC_PCR_26,PORTC Pin Control Register 26" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(26==5)) group.long 0x68++0x03 line.long 0x00 "PORTC_PCR_26,PORTC Pin Control Register 26" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(26==0)) group.long 0x68++0x03 line.long 0x00 "PORTC_PCR_26,PORTC Pin Control Register 26" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x68++0x03 line.long 0x00 "PORTC_PCR_26,PORTC Pin Control Register 26" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x68++0x03 line.long 0x00 "PORTC_PCR_26,PORTC Pin Control Register 26" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x68++0x03 line.long 0x00 "PORTC_PCR_26,PORTC Pin Control Register 26" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x68++0x03 line.long 0x00 "PORTC_PCR_26,PORTC Pin Control Register 26" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x6C - adres ; C - litera portu (A,B,C,...) ; 27 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(27>=1)&&(27<=5)) group.long 0x6C++0x03 line.long 0x00 "PORTC_PCR_27,PORTC Pin Control Register 27" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(27==0)) group.long 0x6C++0x03 line.long 0x00 "PORTC_PCR_27,PORTC Pin Control Register 27" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x6C++0x03 line.long 0x00 "PORTC_PCR_27,PORTC Pin Control Register 27" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(27>=1)&&(27<=4)) group.long 0x6C++0x03 line.long 0x00 "PORTC_PCR_27,PORTC Pin Control Register 27" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(27==5)) group.long 0x6C++0x03 line.long 0x00 "PORTC_PCR_27,PORTC Pin Control Register 27" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(27==0)) group.long 0x6C++0x03 line.long 0x00 "PORTC_PCR_27,PORTC Pin Control Register 27" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x6C++0x03 line.long 0x00 "PORTC_PCR_27,PORTC Pin Control Register 27" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x6C++0x03 line.long 0x00 "PORTC_PCR_27,PORTC Pin Control Register 27" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x6C++0x03 line.long 0x00 "PORTC_PCR_27,PORTC Pin Control Register 27" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x6C++0x03 line.long 0x00 "PORTC_PCR_27,PORTC Pin Control Register 27" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x70 - adres ; C - litera portu (A,B,C,...) ; 28 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(28>=1)&&(28<=5)) group.long 0x70++0x03 line.long 0x00 "PORTC_PCR_28,PORTC Pin Control Register 28" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(28==0)) group.long 0x70++0x03 line.long 0x00 "PORTC_PCR_28,PORTC Pin Control Register 28" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x70++0x03 line.long 0x00 "PORTC_PCR_28,PORTC Pin Control Register 28" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(28>=1)&&(28<=4)) group.long 0x70++0x03 line.long 0x00 "PORTC_PCR_28,PORTC Pin Control Register 28" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(28==5)) group.long 0x70++0x03 line.long 0x00 "PORTC_PCR_28,PORTC Pin Control Register 28" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(28==0)) group.long 0x70++0x03 line.long 0x00 "PORTC_PCR_28,PORTC Pin Control Register 28" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x70++0x03 line.long 0x00 "PORTC_PCR_28,PORTC Pin Control Register 28" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x70++0x03 line.long 0x00 "PORTC_PCR_28,PORTC Pin Control Register 28" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x70++0x03 line.long 0x00 "PORTC_PCR_28,PORTC Pin Control Register 28" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x70++0x03 line.long 0x00 "PORTC_PCR_28,PORTC Pin Control Register 28" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x74 - adres ; C - litera portu (A,B,C,...) ; 29 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(29>=1)&&(29<=5)) group.long 0x74++0x03 line.long 0x00 "PORTC_PCR_29,PORTC Pin Control Register 29" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(29==0)) group.long 0x74++0x03 line.long 0x00 "PORTC_PCR_29,PORTC Pin Control Register 29" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x74++0x03 line.long 0x00 "PORTC_PCR_29,PORTC Pin Control Register 29" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(29>=1)&&(29<=4)) group.long 0x74++0x03 line.long 0x00 "PORTC_PCR_29,PORTC Pin Control Register 29" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(29==5)) group.long 0x74++0x03 line.long 0x00 "PORTC_PCR_29,PORTC Pin Control Register 29" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(29==0)) group.long 0x74++0x03 line.long 0x00 "PORTC_PCR_29,PORTC Pin Control Register 29" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x74++0x03 line.long 0x00 "PORTC_PCR_29,PORTC Pin Control Register 29" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x74++0x03 line.long 0x00 "PORTC_PCR_29,PORTC Pin Control Register 29" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x74++0x03 line.long 0x00 "PORTC_PCR_29,PORTC Pin Control Register 29" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x74++0x03 line.long 0x00 "PORTC_PCR_29,PORTC Pin Control Register 29" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B tree.end newline width 13. wgroup.long 0x80++0x07 line.long 0x00 "PORTC_GPCLR,PORTC Global Pin Control Low Register" bitfld.long 0x00 31. " GPWE_15 ,Global Pin 15 Write Enable" "Disable,Enable" bitfld.long 0x00 30. " GPWE_14 ,Global Pin 14 Write Enable" "Disable,Enable" bitfld.long 0x00 29. " GPWE_13 ,Global Pin 13 Write Enable" "Disable,Enable" bitfld.long 0x00 28. " GPWE_12 ,Global Pin 12 Write Enable" "Disable,Enable" newline bitfld.long 0x00 27. " GPWE_11 ,Global Pin 11 Write Enable" "Disable,Enable" bitfld.long 0x00 26. " GPWE_10 ,Global Pin 10 Write Enable" "Disable,Enable" bitfld.long 0x00 25. " GPWE_9 ,Global Pin 9 Write Enable" "Disable,Enable" bitfld.long 0x00 24. " GPWE_8 ,Global Pin 8 Write Enable" "Disable,Enable" newline bitfld.long 0x00 23. " GPWE_7 ,Global Pin 7 Write Enable" "Disable,Enable" bitfld.long 0x00 22. " GPWE_6 ,Global Pin 6 Write Enable" "Disable,Enable" bitfld.long 0x00 21. " GPWE_5 ,Global Pin 5 Write Enable" "Disable,Enable" bitfld.long 0x00 20. " GPWE_4 ,Global Pin 4 Write Enable" "Disable,Enable" newline bitfld.long 0x00 19. " GPWE_3 ,Global Pin 3 Write Enable" "Disable,Enable" bitfld.long 0x00 18. " GPWE_2 ,Global Pin 2 Write Enable" "Disable,Enable" bitfld.long 0x00 17. " GPWE_1 ,Global Pin 1 Write Enable" "Disable,Enable" bitfld.long 0x00 16. " GPWE_0 ,Global Pin 0 Write Enable" "Disable,Enable" newline hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global Pin Write Data" line.long 0x04 "PORTC_GPCHR,PORTC Global Pin Control High Register" bitfld.long 0x04 29. " GPWE_29 ,Global Pin 29 Write Enable" "Disable,Enable" bitfld.long 0x04 28. " GPWE_28 ,Global Pin 28 Write Enable" "Disable,Enable" bitfld.long 0x04 27. " GPWE_27 ,Global Pin 27 Write Enable" "Disable,Enable" bitfld.long 0x04 26. " GPWE_26 ,Global Pin 26 Write Enable" "Disable,Enable" newline bitfld.long 0x04 25. " GPWE_25 ,Global Pin 25 Write Enable" "Disable,Enable" bitfld.long 0x04 24. " GPWE_24 ,Global Pin 24 Write Enable" "Disable,Enable" bitfld.long 0x04 19. " GPWE_19 ,Global Pin 19 Write Enable" "Disable,Enable" bitfld.long 0x04 18. " GPWE_18 ,Global Pin 18 Write Enable" "Disable,Enable" newline bitfld.long 0x04 17. " GPWE_17 ,Global Pin 17 Write Enable" "Disable,Enable" bitfld.long 0x04 16. " GPWE_16 ,Global Pin 16 Write Enable" "Disable,Enable" newline hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global Pin Write Data" group.long 0xA0++0x03 line.long 0x00 "PORTC_ISFR,PORTC Interrupt Status Flag Register" eventfld.long 0x00 29. " ISF_29 ,Interrupt Status Flag 29 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 28. " ISF_28 ,Interrupt Status Flag 28 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 27. " ISF_27 ,Interrupt Status Flag 27 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 26. " ISF_26 ,Interrupt Status Flag 26 (In Digital Modes only)" "No interrupt,Interrupt" newline eventfld.long 0x00 25. " ISF_25 ,Interrupt Status Flag 25 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 24. " ISF_24 ,Interrupt Status Flag 24 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 19. " ISF_19 ,Interrupt Status Flag 19 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 18. " ISF_18 ,Interrupt Status Flag 18 (In Digital Modes only)" "No interrupt,Interrupt" newline eventfld.long 0x00 17. " ISF_17 ,Interrupt Status Flag 17 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 16. " ISF_16 ,Interrupt Status Flag 16 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 15. " ISF_15 ,Interrupt Status Flag 15 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 14. " ISF_14 ,Interrupt Status Flag 14 (In Digital Modes only)" "No interrupt,Interrupt" newline eventfld.long 0x00 13. " ISF_13 ,Interrupt Status Flag 13 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 12. " ISF_12 ,Interrupt Status Flag 12 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 11. " ISF_11 ,Interrupt Status Flag 11 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 10. " ISF_10 ,Interrupt Status Flag 10 (In Digital Modes only)" "No interrupt,Interrupt" newline eventfld.long 0x00 9. " ISF_9 ,Interrupt Status Flag 9 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 8. " ISF_8 ,Interrupt Status Flag 8 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 7. " ISF_7 ,Interrupt Status Flag 7 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 6. " ISF_6 ,Interrupt Status Flag 6 (In Digital Modes only)" "No interrupt,Interrupt" newline eventfld.long 0x00 5. " ISF_5 ,Interrupt Status Flag 5 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 4. " ISF_4 ,Interrupt Status Flag 4 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 3. " ISF_3 ,Interrupt Status Flag 3 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 2. " ISF_2 ,Interrupt Status Flag 2 (In Digital Modes only)" "No interrupt,Interrupt" newline eventfld.long 0x00 1. " ISF_1 ,Interrupt Status Flag 1 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 0. " ISF_0 ,Interrupt Status Flag 0 (In Digital Modes only)" "No interrupt,Interrupt" group.long 0xC0++0x0B line.long 0x00 "PORTC_DFER,Digital Filter Enable Register" bitfld.long 0x00 29. " DFE_29 ,Pin 29 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 28. " DFE_28 ,Pin 28 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 27. " DFE_27 ,Pin 27 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 26. " DFE_26 ,Pin 26 digital filter enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " DFE_25 ,Pin 25 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 24. " DFE_24 ,Pin 24 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 19. " DFE_19 ,Pin 19 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 18. " DFE_18 ,Pin 18 digital filter enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " DFE_17 ,Pin 17 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 16. " DFE_16 ,Pin 16 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 15. " DFE_15 ,Pin 15 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 14. " DFE_14 ,Pin 14 digital filter enable" "Disabled,Enabled" newline bitfld.long 0x00 13. " DFE_13 ,Pin 13 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 12. " DFE_12 ,Pin 12 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 11. " DFE_11 ,Pin 11 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 10. " DFE_10 ,Pin 10 digital filter enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " DFE_9 ,Pin 9 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 8. " DFE_8 ,Pin 8 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DFE_7 ,Pin 7 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " DFE_6 ,Pin 6 digital filter enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " DFE_5 ,Pin 5 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 4. " DFE_4 ,Pin 4 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 3. " DFE_3 ,Pin 3 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " DFE_2 ,Pin 2 digital filter enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " DFE_1 ,Pin 1 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 0. " DFE_0 ,Pin 0 digital filter enable" "Disabled,Enabled" line.long 0x04 "PORTC_DFCR,Digital Filter Clock Register" bitfld.long 0x04 0. " CS ,Clock source" "Bus clock,LPO clock" line.long 0x08 "PORTC_DFWR,Digital Filter Width Register" bitfld.long 0x08 0.--4. " FILT ,Filter length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif width 0x0B tree.end tree "PORT_D" base ad:0x4004C000 width 13. tree "PORT D Pin Control Registers" ; 0x0 - adres ; D - litera portu (A,B,C,...) ; 0 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('D'=='A')&&(0>=1)&&(0<=5)) group.long 0x0++0x03 line.long 0x00 "PORTD_PCR_0,PORTD Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(0==0)) group.long 0x0++0x03 line.long 0x00 "PORTD_PCR_0,PORTD Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x0++0x03 line.long 0x00 "PORTD_PCR_0,PORTD Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('D'=='A')&&(0>=1)&&(0<=4)) group.long 0x0++0x03 line.long 0x00 "PORTD_PCR_0,PORTD Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(0==5)) group.long 0x0++0x03 line.long 0x00 "PORTD_PCR_0,PORTD Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(0==0)) group.long 0x0++0x03 line.long 0x00 "PORTD_PCR_0,PORTD Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x0++0x03 line.long 0x00 "PORTD_PCR_0,PORTD Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x0++0x03 line.long 0x00 "PORTD_PCR_0,PORTD Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x0++0x03 line.long 0x00 "PORTD_PCR_0,PORTD Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x0++0x03 line.long 0x00 "PORTD_PCR_0,PORTD Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x4 - adres ; D - litera portu (A,B,C,...) ; 1 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('D'=='A')&&(1>=1)&&(1<=5)) group.long 0x4++0x03 line.long 0x00 "PORTD_PCR_1,PORTD Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(1==0)) group.long 0x4++0x03 line.long 0x00 "PORTD_PCR_1,PORTD Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4++0x03 line.long 0x00 "PORTD_PCR_1,PORTD Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('D'=='A')&&(1>=1)&&(1<=4)) group.long 0x4++0x03 line.long 0x00 "PORTD_PCR_1,PORTD Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(1==5)) group.long 0x4++0x03 line.long 0x00 "PORTD_PCR_1,PORTD Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(1==0)) group.long 0x4++0x03 line.long 0x00 "PORTD_PCR_1,PORTD Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4++0x03 line.long 0x00 "PORTD_PCR_1,PORTD Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x4++0x03 line.long 0x00 "PORTD_PCR_1,PORTD Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x4++0x03 line.long 0x00 "PORTD_PCR_1,PORTD Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4++0x03 line.long 0x00 "PORTD_PCR_1,PORTD Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x8 - adres ; D - litera portu (A,B,C,...) ; 2 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('D'=='A')&&(2>=1)&&(2<=5)) group.long 0x8++0x03 line.long 0x00 "PORTD_PCR_2,PORTD Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(2==0)) group.long 0x8++0x03 line.long 0x00 "PORTD_PCR_2,PORTD Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x8++0x03 line.long 0x00 "PORTD_PCR_2,PORTD Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('D'=='A')&&(2>=1)&&(2<=4)) group.long 0x8++0x03 line.long 0x00 "PORTD_PCR_2,PORTD Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(2==5)) group.long 0x8++0x03 line.long 0x00 "PORTD_PCR_2,PORTD Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(2==0)) group.long 0x8++0x03 line.long 0x00 "PORTD_PCR_2,PORTD Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x8++0x03 line.long 0x00 "PORTD_PCR_2,PORTD Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x8++0x03 line.long 0x00 "PORTD_PCR_2,PORTD Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x8++0x03 line.long 0x00 "PORTD_PCR_2,PORTD Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x8++0x03 line.long 0x00 "PORTD_PCR_2,PORTD Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0xC - adres ; D - litera portu (A,B,C,...) ; 3 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('D'=='A')&&(3>=1)&&(3<=5)) group.long 0xC++0x03 line.long 0x00 "PORTD_PCR_3,PORTD Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(3==0)) group.long 0xC++0x03 line.long 0x00 "PORTD_PCR_3,PORTD Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0xC++0x03 line.long 0x00 "PORTD_PCR_3,PORTD Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('D'=='A')&&(3>=1)&&(3<=4)) group.long 0xC++0x03 line.long 0x00 "PORTD_PCR_3,PORTD Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(3==5)) group.long 0xC++0x03 line.long 0x00 "PORTD_PCR_3,PORTD Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(3==0)) group.long 0xC++0x03 line.long 0x00 "PORTD_PCR_3,PORTD Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0xC++0x03 line.long 0x00 "PORTD_PCR_3,PORTD Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0xC++0x03 line.long 0x00 "PORTD_PCR_3,PORTD Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0xC++0x03 line.long 0x00 "PORTD_PCR_3,PORTD Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0xC++0x03 line.long 0x00 "PORTD_PCR_3,PORTD Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x10 - adres ; D - litera portu (A,B,C,...) ; 4 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('D'=='A')&&(4>=1)&&(4<=5)) group.long 0x10++0x03 line.long 0x00 "PORTD_PCR_4,PORTD Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(4==0)) group.long 0x10++0x03 line.long 0x00 "PORTD_PCR_4,PORTD Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x10++0x03 line.long 0x00 "PORTD_PCR_4,PORTD Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('D'=='A')&&(4>=1)&&(4<=4)) group.long 0x10++0x03 line.long 0x00 "PORTD_PCR_4,PORTD Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(4==5)) group.long 0x10++0x03 line.long 0x00 "PORTD_PCR_4,PORTD Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(4==0)) group.long 0x10++0x03 line.long 0x00 "PORTD_PCR_4,PORTD Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x10++0x03 line.long 0x00 "PORTD_PCR_4,PORTD Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x10++0x03 line.long 0x00 "PORTD_PCR_4,PORTD Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x10++0x03 line.long 0x00 "PORTD_PCR_4,PORTD Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x10++0x03 line.long 0x00 "PORTD_PCR_4,PORTD Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x14 - adres ; D - litera portu (A,B,C,...) ; 5 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('D'=='A')&&(5>=1)&&(5<=5)) group.long 0x14++0x03 line.long 0x00 "PORTD_PCR_5,PORTD Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(5==0)) group.long 0x14++0x03 line.long 0x00 "PORTD_PCR_5,PORTD Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x14++0x03 line.long 0x00 "PORTD_PCR_5,PORTD Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('D'=='A')&&(5>=1)&&(5<=4)) group.long 0x14++0x03 line.long 0x00 "PORTD_PCR_5,PORTD Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(5==5)) group.long 0x14++0x03 line.long 0x00 "PORTD_PCR_5,PORTD Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(5==0)) group.long 0x14++0x03 line.long 0x00 "PORTD_PCR_5,PORTD Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x14++0x03 line.long 0x00 "PORTD_PCR_5,PORTD Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x14++0x03 line.long 0x00 "PORTD_PCR_5,PORTD Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x14++0x03 line.long 0x00 "PORTD_PCR_5,PORTD Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x14++0x03 line.long 0x00 "PORTD_PCR_5,PORTD Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x18 - adres ; D - litera portu (A,B,C,...) ; 6 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('D'=='A')&&(6>=1)&&(6<=5)) group.long 0x18++0x03 line.long 0x00 "PORTD_PCR_6,PORTD Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(6==0)) group.long 0x18++0x03 line.long 0x00 "PORTD_PCR_6,PORTD Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x18++0x03 line.long 0x00 "PORTD_PCR_6,PORTD Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('D'=='A')&&(6>=1)&&(6<=4)) group.long 0x18++0x03 line.long 0x00 "PORTD_PCR_6,PORTD Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(6==5)) group.long 0x18++0x03 line.long 0x00 "PORTD_PCR_6,PORTD Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(6==0)) group.long 0x18++0x03 line.long 0x00 "PORTD_PCR_6,PORTD Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x18++0x03 line.long 0x00 "PORTD_PCR_6,PORTD Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x18++0x03 line.long 0x00 "PORTD_PCR_6,PORTD Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x18++0x03 line.long 0x00 "PORTD_PCR_6,PORTD Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x18++0x03 line.long 0x00 "PORTD_PCR_6,PORTD Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x1C - adres ; D - litera portu (A,B,C,...) ; 7 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('D'=='A')&&(7>=1)&&(7<=5)) group.long 0x1C++0x03 line.long 0x00 "PORTD_PCR_7,PORTD Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(7==0)) group.long 0x1C++0x03 line.long 0x00 "PORTD_PCR_7,PORTD Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x1C++0x03 line.long 0x00 "PORTD_PCR_7,PORTD Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('D'=='A')&&(7>=1)&&(7<=4)) group.long 0x1C++0x03 line.long 0x00 "PORTD_PCR_7,PORTD Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(7==5)) group.long 0x1C++0x03 line.long 0x00 "PORTD_PCR_7,PORTD Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(7==0)) group.long 0x1C++0x03 line.long 0x00 "PORTD_PCR_7,PORTD Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x1C++0x03 line.long 0x00 "PORTD_PCR_7,PORTD Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x1C++0x03 line.long 0x00 "PORTD_PCR_7,PORTD Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x1C++0x03 line.long 0x00 "PORTD_PCR_7,PORTD Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x1C++0x03 line.long 0x00 "PORTD_PCR_7,PORTD Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x20 - adres ; D - litera portu (A,B,C,...) ; 8 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('D'=='A')&&(8>=1)&&(8<=5)) group.long 0x20++0x03 line.long 0x00 "PORTD_PCR_8,PORTD Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(8==0)) group.long 0x20++0x03 line.long 0x00 "PORTD_PCR_8,PORTD Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x20++0x03 line.long 0x00 "PORTD_PCR_8,PORTD Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('D'=='A')&&(8>=1)&&(8<=4)) group.long 0x20++0x03 line.long 0x00 "PORTD_PCR_8,PORTD Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(8==5)) group.long 0x20++0x03 line.long 0x00 "PORTD_PCR_8,PORTD Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(8==0)) group.long 0x20++0x03 line.long 0x00 "PORTD_PCR_8,PORTD Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x20++0x03 line.long 0x00 "PORTD_PCR_8,PORTD Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x20++0x03 line.long 0x00 "PORTD_PCR_8,PORTD Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x20++0x03 line.long 0x00 "PORTD_PCR_8,PORTD Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x20++0x03 line.long 0x00 "PORTD_PCR_8,PORTD Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x24 - adres ; D - litera portu (A,B,C,...) ; 9 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('D'=='A')&&(9>=1)&&(9<=5)) group.long 0x24++0x03 line.long 0x00 "PORTD_PCR_9,PORTD Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(9==0)) group.long 0x24++0x03 line.long 0x00 "PORTD_PCR_9,PORTD Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x24++0x03 line.long 0x00 "PORTD_PCR_9,PORTD Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('D'=='A')&&(9>=1)&&(9<=4)) group.long 0x24++0x03 line.long 0x00 "PORTD_PCR_9,PORTD Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(9==5)) group.long 0x24++0x03 line.long 0x00 "PORTD_PCR_9,PORTD Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(9==0)) group.long 0x24++0x03 line.long 0x00 "PORTD_PCR_9,PORTD Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x24++0x03 line.long 0x00 "PORTD_PCR_9,PORTD Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x24++0x03 line.long 0x00 "PORTD_PCR_9,PORTD Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x24++0x03 line.long 0x00 "PORTD_PCR_9,PORTD Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x24++0x03 line.long 0x00 "PORTD_PCR_9,PORTD Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x28 - adres ; D - litera portu (A,B,C,...) ; 10 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('D'=='A')&&(10>=1)&&(10<=5)) group.long 0x28++0x03 line.long 0x00 "PORTD_PCR_10,PORTD Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(10==0)) group.long 0x28++0x03 line.long 0x00 "PORTD_PCR_10,PORTD Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x28++0x03 line.long 0x00 "PORTD_PCR_10,PORTD Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('D'=='A')&&(10>=1)&&(10<=4)) group.long 0x28++0x03 line.long 0x00 "PORTD_PCR_10,PORTD Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(10==5)) group.long 0x28++0x03 line.long 0x00 "PORTD_PCR_10,PORTD Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(10==0)) group.long 0x28++0x03 line.long 0x00 "PORTD_PCR_10,PORTD Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x28++0x03 line.long 0x00 "PORTD_PCR_10,PORTD Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x28++0x03 line.long 0x00 "PORTD_PCR_10,PORTD Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x28++0x03 line.long 0x00 "PORTD_PCR_10,PORTD Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x28++0x03 line.long 0x00 "PORTD_PCR_10,PORTD Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x2C - adres ; D - litera portu (A,B,C,...) ; 11 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('D'=='A')&&(11>=1)&&(11<=5)) group.long 0x2C++0x03 line.long 0x00 "PORTD_PCR_11,PORTD Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(11==0)) group.long 0x2C++0x03 line.long 0x00 "PORTD_PCR_11,PORTD Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x2C++0x03 line.long 0x00 "PORTD_PCR_11,PORTD Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('D'=='A')&&(11>=1)&&(11<=4)) group.long 0x2C++0x03 line.long 0x00 "PORTD_PCR_11,PORTD Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(11==5)) group.long 0x2C++0x03 line.long 0x00 "PORTD_PCR_11,PORTD Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(11==0)) group.long 0x2C++0x03 line.long 0x00 "PORTD_PCR_11,PORTD Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x2C++0x03 line.long 0x00 "PORTD_PCR_11,PORTD Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x2C++0x03 line.long 0x00 "PORTD_PCR_11,PORTD Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x2C++0x03 line.long 0x00 "PORTD_PCR_11,PORTD Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x2C++0x03 line.long 0x00 "PORTD_PCR_11,PORTD Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x30 - adres ; D - litera portu (A,B,C,...) ; 12 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('D'=='A')&&(12>=1)&&(12<=5)) group.long 0x30++0x03 line.long 0x00 "PORTD_PCR_12,PORTD Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(12==0)) group.long 0x30++0x03 line.long 0x00 "PORTD_PCR_12,PORTD Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x30++0x03 line.long 0x00 "PORTD_PCR_12,PORTD Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('D'=='A')&&(12>=1)&&(12<=4)) group.long 0x30++0x03 line.long 0x00 "PORTD_PCR_12,PORTD Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(12==5)) group.long 0x30++0x03 line.long 0x00 "PORTD_PCR_12,PORTD Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(12==0)) group.long 0x30++0x03 line.long 0x00 "PORTD_PCR_12,PORTD Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x30++0x03 line.long 0x00 "PORTD_PCR_12,PORTD Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x30++0x03 line.long 0x00 "PORTD_PCR_12,PORTD Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x30++0x03 line.long 0x00 "PORTD_PCR_12,PORTD Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x30++0x03 line.long 0x00 "PORTD_PCR_12,PORTD Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x34 - adres ; D - litera portu (A,B,C,...) ; 13 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('D'=='A')&&(13>=1)&&(13<=5)) group.long 0x34++0x03 line.long 0x00 "PORTD_PCR_13,PORTD Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(13==0)) group.long 0x34++0x03 line.long 0x00 "PORTD_PCR_13,PORTD Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x34++0x03 line.long 0x00 "PORTD_PCR_13,PORTD Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('D'=='A')&&(13>=1)&&(13<=4)) group.long 0x34++0x03 line.long 0x00 "PORTD_PCR_13,PORTD Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(13==5)) group.long 0x34++0x03 line.long 0x00 "PORTD_PCR_13,PORTD Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(13==0)) group.long 0x34++0x03 line.long 0x00 "PORTD_PCR_13,PORTD Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x34++0x03 line.long 0x00 "PORTD_PCR_13,PORTD Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x34++0x03 line.long 0x00 "PORTD_PCR_13,PORTD Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x34++0x03 line.long 0x00 "PORTD_PCR_13,PORTD Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x34++0x03 line.long 0x00 "PORTD_PCR_13,PORTD Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x38 - adres ; D - litera portu (A,B,C,...) ; 14 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('D'=='A')&&(14>=1)&&(14<=5)) group.long 0x38++0x03 line.long 0x00 "PORTD_PCR_14,PORTD Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(14==0)) group.long 0x38++0x03 line.long 0x00 "PORTD_PCR_14,PORTD Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x38++0x03 line.long 0x00 "PORTD_PCR_14,PORTD Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('D'=='A')&&(14>=1)&&(14<=4)) group.long 0x38++0x03 line.long 0x00 "PORTD_PCR_14,PORTD Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(14==5)) group.long 0x38++0x03 line.long 0x00 "PORTD_PCR_14,PORTD Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(14==0)) group.long 0x38++0x03 line.long 0x00 "PORTD_PCR_14,PORTD Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x38++0x03 line.long 0x00 "PORTD_PCR_14,PORTD Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x38++0x03 line.long 0x00 "PORTD_PCR_14,PORTD Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x38++0x03 line.long 0x00 "PORTD_PCR_14,PORTD Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x38++0x03 line.long 0x00 "PORTD_PCR_14,PORTD Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x3C - adres ; D - litera portu (A,B,C,...) ; 15 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('D'=='A')&&(15>=1)&&(15<=5)) group.long 0x3C++0x03 line.long 0x00 "PORTD_PCR_15,PORTD Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(15==0)) group.long 0x3C++0x03 line.long 0x00 "PORTD_PCR_15,PORTD Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x3C++0x03 line.long 0x00 "PORTD_PCR_15,PORTD Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('D'=='A')&&(15>=1)&&(15<=4)) group.long 0x3C++0x03 line.long 0x00 "PORTD_PCR_15,PORTD Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(15==5)) group.long 0x3C++0x03 line.long 0x00 "PORTD_PCR_15,PORTD Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(15==0)) group.long 0x3C++0x03 line.long 0x00 "PORTD_PCR_15,PORTD Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x3C++0x03 line.long 0x00 "PORTD_PCR_15,PORTD Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x3C++0x03 line.long 0x00 "PORTD_PCR_15,PORTD Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x3C++0x03 line.long 0x00 "PORTD_PCR_15,PORTD Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x3C++0x03 line.long 0x00 "PORTD_PCR_15,PORTD Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B tree.end newline width 13. wgroup.long 0x80++0x03 line.long 0x00 "PORTD_GPCLR,PORTD Global Pin Control Low Register" bitfld.long 0x00 31. " GPWE_15 ,Global Pin 15 Write Enable" "Disable,Enable" bitfld.long 0x00 30. " GPWE_14 ,Global Pin 14 Write Enable" "Disable,Enable" bitfld.long 0x00 29. " GPWE_13 ,Global Pin 13 Write Enable" "Disable,Enable" bitfld.long 0x00 28. " GPWE_12 ,Global Pin 12 Write Enable" "Disable,Enable" newline bitfld.long 0x00 27. " GPWE_11 ,Global Pin 11 Write Enable" "Disable,Enable" bitfld.long 0x00 26. " GPWE_10 ,Global Pin 10 Write Enable" "Disable,Enable" bitfld.long 0x00 25. " GPWE_9 ,Global Pin 9 Write Enable" "Disable,Enable" bitfld.long 0x00 24. " GPWE_8 ,Global Pin 8 Write Enable" "Disable,Enable" newline bitfld.long 0x00 23. " GPWE_7 ,Global Pin 7 Write Enable" "Disable,Enable" bitfld.long 0x00 22. " GPWE_6 ,Global Pin 6 Write Enable" "Disable,Enable" bitfld.long 0x00 21. " GPWE_5 ,Global Pin 5 Write Enable" "Disable,Enable" bitfld.long 0x00 20. " GPWE_4 ,Global Pin 4 Write Enable" "Disable,Enable" newline bitfld.long 0x00 19. " GPWE_3 ,Global Pin 3 Write Enable" "Disable,Enable" bitfld.long 0x00 18. " GPWE_2 ,Global Pin 2 Write Enable" "Disable,Enable" bitfld.long 0x00 17. " GPWE_1 ,Global Pin 1 Write Enable" "Disable,Enable" bitfld.long 0x00 16. " GPWE_0 ,Global Pin 0 Write Enable" "Disable,Enable" newline hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global Pin Write Data" group.long 0xA0++0x03 line.long 0x00 "PORTD_ISFR,PORTD Interrupt Status Flag Register" eventfld.long 0x00 15. " ISF_15 ,Interrupt Status Flag 15 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 14. " ISF_14 ,Interrupt Status Flag 14 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 13. " ISF_13 ,Interrupt Status Flag 13 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 12. " ISF_12 ,Interrupt Status Flag 12 (In Digital Modes only)" "No interrupt,Interrupt" newline eventfld.long 0x00 11. " ISF_11 ,Interrupt Status Flag 11 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 10. " ISF_10 ,Interrupt Status Flag 10 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 9. " ISF_9 ,Interrupt Status Flag 9 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 8. " ISF_8 ,Interrupt Status Flag 8 (In Digital Modes only)" "No interrupt,Interrupt" newline eventfld.long 0x00 7. " ISF_7 ,Interrupt Status Flag 7 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 6. " ISF_6 ,Interrupt Status Flag 6 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 5. " ISF_5 ,Interrupt Status Flag 5 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 4. " ISF_4 ,Interrupt Status Flag 4 (In Digital Modes only)" "No interrupt,Interrupt" newline eventfld.long 0x00 3. " ISF_3 ,Interrupt Status Flag 3 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 2. " ISF_2 ,Interrupt Status Flag 2 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 1. " ISF_1 ,Interrupt Status Flag 1 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 0. " ISF_0 ,Interrupt Status Flag 0 (In Digital Modes only)" "No interrupt,Interrupt" group.long 0xC0++0x0B line.long 0x00 "PORTD_DFER,Digital Filter Enable Register" bitfld.long 0x00 15. " DFE_15 ,Pin 15 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 14. " DFE_14 ,Pin 14 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 13. " DFE_13 ,Pin 13 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 12. " DFE_12 ,Pin 12 digital filter enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " DFE_11 ,Pin 11 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 10. " DFE_10 ,Pin 10 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 9. " DFE_9 ,Pin 9 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 8. " DFE_8 ,Pin 8 digital filter enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " DFE_7 ,Pin 7 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " DFE_6 ,Pin 6 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " DFE_5 ,Pin 5 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 4. " DFE_4 ,Pin 4 digital filter enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " DFE_3 ,Pin 3 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " DFE_2 ,Pin 2 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 1. " DFE_1 ,Pin 1 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 0. " DFE_0 ,Pin 0 digital filter enable" "Disabled,Enabled" line.long 0x04 "PORTD_DFCR,Digital Filter Clock Register" bitfld.long 0x04 0. " CS ,Clock source" "Bus clock,LPO clock" line.long 0x08 "PORTD_DFWR,Digital Filter Width Register" bitfld.long 0x08 0.--4. " FILT ,Filter length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "PORT_E" base ad:0x4004D000 width 13. tree "PORT E Pin Control Registers" sif cpuis("MK8?FN256V*") ; 0x0 - adres ; E - litera portu (A,B,C,...) ; 0 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(0>=1)&&(0<=5)) group.long 0x0++0x03 line.long 0x00 "PORTE_PCR_0,PORTE Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(0==0)) group.long 0x0++0x03 line.long 0x00 "PORTE_PCR_0,PORTE Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x0++0x03 line.long 0x00 "PORTE_PCR_0,PORTE Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(0>=1)&&(0<=4)) group.long 0x0++0x03 line.long 0x00 "PORTE_PCR_0,PORTE Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(0==5)) group.long 0x0++0x03 line.long 0x00 "PORTE_PCR_0,PORTE Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(0==0)) group.long 0x0++0x03 line.long 0x00 "PORTE_PCR_0,PORTE Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x0++0x03 line.long 0x00 "PORTE_PCR_0,PORTE Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x0++0x03 line.long 0x00 "PORTE_PCR_0,PORTE Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x0++0x03 line.long 0x00 "PORTE_PCR_0,PORTE Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x0++0x03 line.long 0x00 "PORTE_PCR_0,PORTE Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B else ; 0x0 - adres ; E - litera portu (A,B,C,...) ; 0 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(0>=1)&&(0<=5)) group.long 0x0++0x03 line.long 0x00 "PORTE_PCR_0,PORTE Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(0==0)) group.long 0x0++0x03 line.long 0x00 "PORTE_PCR_0,PORTE Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x0++0x03 line.long 0x00 "PORTE_PCR_0,PORTE Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(0>=1)&&(0<=4)) group.long 0x0++0x03 line.long 0x00 "PORTE_PCR_0,PORTE Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(0==5)) group.long 0x0++0x03 line.long 0x00 "PORTE_PCR_0,PORTE Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(0==0)) group.long 0x0++0x03 line.long 0x00 "PORTE_PCR_0,PORTE Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x0++0x03 line.long 0x00 "PORTE_PCR_0,PORTE Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x0++0x03 line.long 0x00 "PORTE_PCR_0,PORTE Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x0++0x03 line.long 0x00 "PORTE_PCR_0,PORTE Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x0++0x03 line.long 0x00 "PORTE_PCR_0,PORTE Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B endif sif cpuis("MK8?FN256V*") ; 0x4 - adres ; E - litera portu (A,B,C,...) ; 1 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(1>=1)&&(1<=5)) group.long 0x4++0x03 line.long 0x00 "PORTE_PCR_1,PORTE Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(1==0)) group.long 0x4++0x03 line.long 0x00 "PORTE_PCR_1,PORTE Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4++0x03 line.long 0x00 "PORTE_PCR_1,PORTE Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(1>=1)&&(1<=4)) group.long 0x4++0x03 line.long 0x00 "PORTE_PCR_1,PORTE Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(1==5)) group.long 0x4++0x03 line.long 0x00 "PORTE_PCR_1,PORTE Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(1==0)) group.long 0x4++0x03 line.long 0x00 "PORTE_PCR_1,PORTE Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4++0x03 line.long 0x00 "PORTE_PCR_1,PORTE Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x4++0x03 line.long 0x00 "PORTE_PCR_1,PORTE Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x4++0x03 line.long 0x00 "PORTE_PCR_1,PORTE Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4++0x03 line.long 0x00 "PORTE_PCR_1,PORTE Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B else ; 0x4 - adres ; E - litera portu (A,B,C,...) ; 1 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(1>=1)&&(1<=5)) group.long 0x4++0x03 line.long 0x00 "PORTE_PCR_1,PORTE Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(1==0)) group.long 0x4++0x03 line.long 0x00 "PORTE_PCR_1,PORTE Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4++0x03 line.long 0x00 "PORTE_PCR_1,PORTE Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(1>=1)&&(1<=4)) group.long 0x4++0x03 line.long 0x00 "PORTE_PCR_1,PORTE Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(1==5)) group.long 0x4++0x03 line.long 0x00 "PORTE_PCR_1,PORTE Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(1==0)) group.long 0x4++0x03 line.long 0x00 "PORTE_PCR_1,PORTE Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4++0x03 line.long 0x00 "PORTE_PCR_1,PORTE Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x4++0x03 line.long 0x00 "PORTE_PCR_1,PORTE Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x4++0x03 line.long 0x00 "PORTE_PCR_1,PORTE Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4++0x03 line.long 0x00 "PORTE_PCR_1,PORTE Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B endif sif cpuis("MK8?FN256V*") ; 0x8 - adres ; E - litera portu (A,B,C,...) ; 2 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(2>=1)&&(2<=5)) group.long 0x8++0x03 line.long 0x00 "PORTE_PCR_2,PORTE Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(2==0)) group.long 0x8++0x03 line.long 0x00 "PORTE_PCR_2,PORTE Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x8++0x03 line.long 0x00 "PORTE_PCR_2,PORTE Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(2>=1)&&(2<=4)) group.long 0x8++0x03 line.long 0x00 "PORTE_PCR_2,PORTE Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(2==5)) group.long 0x8++0x03 line.long 0x00 "PORTE_PCR_2,PORTE Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(2==0)) group.long 0x8++0x03 line.long 0x00 "PORTE_PCR_2,PORTE Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x8++0x03 line.long 0x00 "PORTE_PCR_2,PORTE Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x8++0x03 line.long 0x00 "PORTE_PCR_2,PORTE Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x8++0x03 line.long 0x00 "PORTE_PCR_2,PORTE Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x8++0x03 line.long 0x00 "PORTE_PCR_2,PORTE Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B else ; 0x8 - adres ; E - litera portu (A,B,C,...) ; 2 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(2>=1)&&(2<=5)) group.long 0x8++0x03 line.long 0x00 "PORTE_PCR_2,PORTE Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(2==0)) group.long 0x8++0x03 line.long 0x00 "PORTE_PCR_2,PORTE Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x8++0x03 line.long 0x00 "PORTE_PCR_2,PORTE Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(2>=1)&&(2<=4)) group.long 0x8++0x03 line.long 0x00 "PORTE_PCR_2,PORTE Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(2==5)) group.long 0x8++0x03 line.long 0x00 "PORTE_PCR_2,PORTE Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(2==0)) group.long 0x8++0x03 line.long 0x00 "PORTE_PCR_2,PORTE Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x8++0x03 line.long 0x00 "PORTE_PCR_2,PORTE Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x8++0x03 line.long 0x00 "PORTE_PCR_2,PORTE Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x8++0x03 line.long 0x00 "PORTE_PCR_2,PORTE Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x8++0x03 line.long 0x00 "PORTE_PCR_2,PORTE Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B endif sif cpuis("MK8?FN256V*") ; 0xC - adres ; E - litera portu (A,B,C,...) ; 3 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(3>=1)&&(3<=5)) group.long 0xC++0x03 line.long 0x00 "PORTE_PCR_3,PORTE Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(3==0)) group.long 0xC++0x03 line.long 0x00 "PORTE_PCR_3,PORTE Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0xC++0x03 line.long 0x00 "PORTE_PCR_3,PORTE Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(3>=1)&&(3<=4)) group.long 0xC++0x03 line.long 0x00 "PORTE_PCR_3,PORTE Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(3==5)) group.long 0xC++0x03 line.long 0x00 "PORTE_PCR_3,PORTE Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(3==0)) group.long 0xC++0x03 line.long 0x00 "PORTE_PCR_3,PORTE Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0xC++0x03 line.long 0x00 "PORTE_PCR_3,PORTE Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0xC++0x03 line.long 0x00 "PORTE_PCR_3,PORTE Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0xC++0x03 line.long 0x00 "PORTE_PCR_3,PORTE Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0xC++0x03 line.long 0x00 "PORTE_PCR_3,PORTE Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B else ; 0xC - adres ; E - litera portu (A,B,C,...) ; 3 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(3>=1)&&(3<=5)) group.long 0xC++0x03 line.long 0x00 "PORTE_PCR_3,PORTE Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(3==0)) group.long 0xC++0x03 line.long 0x00 "PORTE_PCR_3,PORTE Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0xC++0x03 line.long 0x00 "PORTE_PCR_3,PORTE Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(3>=1)&&(3<=4)) group.long 0xC++0x03 line.long 0x00 "PORTE_PCR_3,PORTE Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(3==5)) group.long 0xC++0x03 line.long 0x00 "PORTE_PCR_3,PORTE Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(3==0)) group.long 0xC++0x03 line.long 0x00 "PORTE_PCR_3,PORTE Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0xC++0x03 line.long 0x00 "PORTE_PCR_3,PORTE Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0xC++0x03 line.long 0x00 "PORTE_PCR_3,PORTE Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0xC++0x03 line.long 0x00 "PORTE_PCR_3,PORTE Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0xC++0x03 line.long 0x00 "PORTE_PCR_3,PORTE Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B endif sif cpuis("MK8?FN256V*") ; 0x10 - adres ; E - litera portu (A,B,C,...) ; 4 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(4>=1)&&(4<=5)) group.long 0x10++0x03 line.long 0x00 "PORTE_PCR_4,PORTE Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(4==0)) group.long 0x10++0x03 line.long 0x00 "PORTE_PCR_4,PORTE Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x10++0x03 line.long 0x00 "PORTE_PCR_4,PORTE Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(4>=1)&&(4<=4)) group.long 0x10++0x03 line.long 0x00 "PORTE_PCR_4,PORTE Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(4==5)) group.long 0x10++0x03 line.long 0x00 "PORTE_PCR_4,PORTE Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(4==0)) group.long 0x10++0x03 line.long 0x00 "PORTE_PCR_4,PORTE Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x10++0x03 line.long 0x00 "PORTE_PCR_4,PORTE Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x10++0x03 line.long 0x00 "PORTE_PCR_4,PORTE Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x10++0x03 line.long 0x00 "PORTE_PCR_4,PORTE Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x10++0x03 line.long 0x00 "PORTE_PCR_4,PORTE Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B else ; 0x10 - adres ; E - litera portu (A,B,C,...) ; 4 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(4>=1)&&(4<=5)) group.long 0x10++0x03 line.long 0x00 "PORTE_PCR_4,PORTE Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(4==0)) group.long 0x10++0x03 line.long 0x00 "PORTE_PCR_4,PORTE Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x10++0x03 line.long 0x00 "PORTE_PCR_4,PORTE Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(4>=1)&&(4<=4)) group.long 0x10++0x03 line.long 0x00 "PORTE_PCR_4,PORTE Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(4==5)) group.long 0x10++0x03 line.long 0x00 "PORTE_PCR_4,PORTE Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(4==0)) group.long 0x10++0x03 line.long 0x00 "PORTE_PCR_4,PORTE Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x10++0x03 line.long 0x00 "PORTE_PCR_4,PORTE Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x10++0x03 line.long 0x00 "PORTE_PCR_4,PORTE Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x10++0x03 line.long 0x00 "PORTE_PCR_4,PORTE Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x10++0x03 line.long 0x00 "PORTE_PCR_4,PORTE Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B endif sif cpuis("MK8?FN256V*") ; 0x14 - adres ; E - litera portu (A,B,C,...) ; 5 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(5>=1)&&(5<=5)) group.long 0x14++0x03 line.long 0x00 "PORTE_PCR_5,PORTE Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(5==0)) group.long 0x14++0x03 line.long 0x00 "PORTE_PCR_5,PORTE Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x14++0x03 line.long 0x00 "PORTE_PCR_5,PORTE Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(5>=1)&&(5<=4)) group.long 0x14++0x03 line.long 0x00 "PORTE_PCR_5,PORTE Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(5==5)) group.long 0x14++0x03 line.long 0x00 "PORTE_PCR_5,PORTE Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(5==0)) group.long 0x14++0x03 line.long 0x00 "PORTE_PCR_5,PORTE Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x14++0x03 line.long 0x00 "PORTE_PCR_5,PORTE Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x14++0x03 line.long 0x00 "PORTE_PCR_5,PORTE Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x14++0x03 line.long 0x00 "PORTE_PCR_5,PORTE Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x14++0x03 line.long 0x00 "PORTE_PCR_5,PORTE Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B else ; 0x14 - adres ; E - litera portu (A,B,C,...) ; 5 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(5>=1)&&(5<=5)) group.long 0x14++0x03 line.long 0x00 "PORTE_PCR_5,PORTE Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(5==0)) group.long 0x14++0x03 line.long 0x00 "PORTE_PCR_5,PORTE Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x14++0x03 line.long 0x00 "PORTE_PCR_5,PORTE Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(5>=1)&&(5<=4)) group.long 0x14++0x03 line.long 0x00 "PORTE_PCR_5,PORTE Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(5==5)) group.long 0x14++0x03 line.long 0x00 "PORTE_PCR_5,PORTE Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(5==0)) group.long 0x14++0x03 line.long 0x00 "PORTE_PCR_5,PORTE Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x14++0x03 line.long 0x00 "PORTE_PCR_5,PORTE Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x14++0x03 line.long 0x00 "PORTE_PCR_5,PORTE Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x14++0x03 line.long 0x00 "PORTE_PCR_5,PORTE Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x14++0x03 line.long 0x00 "PORTE_PCR_5,PORTE Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B endif sif cpuis("MK8?FN256V*") ; 0x18 - adres ; E - litera portu (A,B,C,...) ; 6 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(6>=1)&&(6<=5)) group.long 0x18++0x03 line.long 0x00 "PORTE_PCR_6,PORTE Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(6==0)) group.long 0x18++0x03 line.long 0x00 "PORTE_PCR_6,PORTE Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x18++0x03 line.long 0x00 "PORTE_PCR_6,PORTE Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(6>=1)&&(6<=4)) group.long 0x18++0x03 line.long 0x00 "PORTE_PCR_6,PORTE Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(6==5)) group.long 0x18++0x03 line.long 0x00 "PORTE_PCR_6,PORTE Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(6==0)) group.long 0x18++0x03 line.long 0x00 "PORTE_PCR_6,PORTE Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x18++0x03 line.long 0x00 "PORTE_PCR_6,PORTE Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x18++0x03 line.long 0x00 "PORTE_PCR_6,PORTE Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x18++0x03 line.long 0x00 "PORTE_PCR_6,PORTE Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x18++0x03 line.long 0x00 "PORTE_PCR_6,PORTE Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B else ; 0x18 - adres ; E - litera portu (A,B,C,...) ; 6 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(6>=1)&&(6<=5)) group.long 0x18++0x03 line.long 0x00 "PORTE_PCR_6,PORTE Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(6==0)) group.long 0x18++0x03 line.long 0x00 "PORTE_PCR_6,PORTE Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x18++0x03 line.long 0x00 "PORTE_PCR_6,PORTE Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(6>=1)&&(6<=4)) group.long 0x18++0x03 line.long 0x00 "PORTE_PCR_6,PORTE Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(6==5)) group.long 0x18++0x03 line.long 0x00 "PORTE_PCR_6,PORTE Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(6==0)) group.long 0x18++0x03 line.long 0x00 "PORTE_PCR_6,PORTE Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x18++0x03 line.long 0x00 "PORTE_PCR_6,PORTE Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x18++0x03 line.long 0x00 "PORTE_PCR_6,PORTE Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x18++0x03 line.long 0x00 "PORTE_PCR_6,PORTE Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x18++0x03 line.long 0x00 "PORTE_PCR_6,PORTE Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B endif sif cpuis("MK8?FN256V*") ; 0x1C - adres ; E - litera portu (A,B,C,...) ; 7 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(7>=1)&&(7<=5)) group.long 0x1C++0x03 line.long 0x00 "PORTE_PCR_7,PORTE Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(7==0)) group.long 0x1C++0x03 line.long 0x00 "PORTE_PCR_7,PORTE Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x1C++0x03 line.long 0x00 "PORTE_PCR_7,PORTE Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(7>=1)&&(7<=4)) group.long 0x1C++0x03 line.long 0x00 "PORTE_PCR_7,PORTE Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(7==5)) group.long 0x1C++0x03 line.long 0x00 "PORTE_PCR_7,PORTE Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(7==0)) group.long 0x1C++0x03 line.long 0x00 "PORTE_PCR_7,PORTE Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x1C++0x03 line.long 0x00 "PORTE_PCR_7,PORTE Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x1C++0x03 line.long 0x00 "PORTE_PCR_7,PORTE Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x1C++0x03 line.long 0x00 "PORTE_PCR_7,PORTE Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x1C++0x03 line.long 0x00 "PORTE_PCR_7,PORTE Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B else ; 0x1C - adres ; E - litera portu (A,B,C,...) ; 7 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(7>=1)&&(7<=5)) group.long 0x1C++0x03 line.long 0x00 "PORTE_PCR_7,PORTE Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(7==0)) group.long 0x1C++0x03 line.long 0x00 "PORTE_PCR_7,PORTE Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x1C++0x03 line.long 0x00 "PORTE_PCR_7,PORTE Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(7>=1)&&(7<=4)) group.long 0x1C++0x03 line.long 0x00 "PORTE_PCR_7,PORTE Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(7==5)) group.long 0x1C++0x03 line.long 0x00 "PORTE_PCR_7,PORTE Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(7==0)) group.long 0x1C++0x03 line.long 0x00 "PORTE_PCR_7,PORTE Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x1C++0x03 line.long 0x00 "PORTE_PCR_7,PORTE Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x1C++0x03 line.long 0x00 "PORTE_PCR_7,PORTE Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x1C++0x03 line.long 0x00 "PORTE_PCR_7,PORTE Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x1C++0x03 line.long 0x00 "PORTE_PCR_7,PORTE Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B endif sif cpuis("MK8?FN256V*") ; 0x20 - adres ; E - litera portu (A,B,C,...) ; 8 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(8>=1)&&(8<=5)) group.long 0x20++0x03 line.long 0x00 "PORTE_PCR_8,PORTE Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(8==0)) group.long 0x20++0x03 line.long 0x00 "PORTE_PCR_8,PORTE Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x20++0x03 line.long 0x00 "PORTE_PCR_8,PORTE Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(8>=1)&&(8<=4)) group.long 0x20++0x03 line.long 0x00 "PORTE_PCR_8,PORTE Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(8==5)) group.long 0x20++0x03 line.long 0x00 "PORTE_PCR_8,PORTE Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(8==0)) group.long 0x20++0x03 line.long 0x00 "PORTE_PCR_8,PORTE Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x20++0x03 line.long 0x00 "PORTE_PCR_8,PORTE Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x20++0x03 line.long 0x00 "PORTE_PCR_8,PORTE Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x20++0x03 line.long 0x00 "PORTE_PCR_8,PORTE Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x20++0x03 line.long 0x00 "PORTE_PCR_8,PORTE Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B else ; 0x20 - adres ; E - litera portu (A,B,C,...) ; 8 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(8>=1)&&(8<=5)) group.long 0x20++0x03 line.long 0x00 "PORTE_PCR_8,PORTE Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(8==0)) group.long 0x20++0x03 line.long 0x00 "PORTE_PCR_8,PORTE Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x20++0x03 line.long 0x00 "PORTE_PCR_8,PORTE Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(8>=1)&&(8<=4)) group.long 0x20++0x03 line.long 0x00 "PORTE_PCR_8,PORTE Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(8==5)) group.long 0x20++0x03 line.long 0x00 "PORTE_PCR_8,PORTE Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(8==0)) group.long 0x20++0x03 line.long 0x00 "PORTE_PCR_8,PORTE Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x20++0x03 line.long 0x00 "PORTE_PCR_8,PORTE Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x20++0x03 line.long 0x00 "PORTE_PCR_8,PORTE Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x20++0x03 line.long 0x00 "PORTE_PCR_8,PORTE Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x20++0x03 line.long 0x00 "PORTE_PCR_8,PORTE Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B endif sif cpuis("MK8?FN256V*") ; 0x24 - adres ; E - litera portu (A,B,C,...) ; 9 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(9>=1)&&(9<=5)) group.long 0x24++0x03 line.long 0x00 "PORTE_PCR_9,PORTE Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(9==0)) group.long 0x24++0x03 line.long 0x00 "PORTE_PCR_9,PORTE Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x24++0x03 line.long 0x00 "PORTE_PCR_9,PORTE Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(9>=1)&&(9<=4)) group.long 0x24++0x03 line.long 0x00 "PORTE_PCR_9,PORTE Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(9==5)) group.long 0x24++0x03 line.long 0x00 "PORTE_PCR_9,PORTE Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(9==0)) group.long 0x24++0x03 line.long 0x00 "PORTE_PCR_9,PORTE Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x24++0x03 line.long 0x00 "PORTE_PCR_9,PORTE Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x24++0x03 line.long 0x00 "PORTE_PCR_9,PORTE Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x24++0x03 line.long 0x00 "PORTE_PCR_9,PORTE Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x24++0x03 line.long 0x00 "PORTE_PCR_9,PORTE Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B else ; 0x24 - adres ; E - litera portu (A,B,C,...) ; 9 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(9>=1)&&(9<=5)) group.long 0x24++0x03 line.long 0x00 "PORTE_PCR_9,PORTE Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(9==0)) group.long 0x24++0x03 line.long 0x00 "PORTE_PCR_9,PORTE Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x24++0x03 line.long 0x00 "PORTE_PCR_9,PORTE Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(9>=1)&&(9<=4)) group.long 0x24++0x03 line.long 0x00 "PORTE_PCR_9,PORTE Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(9==5)) group.long 0x24++0x03 line.long 0x00 "PORTE_PCR_9,PORTE Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(9==0)) group.long 0x24++0x03 line.long 0x00 "PORTE_PCR_9,PORTE Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x24++0x03 line.long 0x00 "PORTE_PCR_9,PORTE Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x24++0x03 line.long 0x00 "PORTE_PCR_9,PORTE Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x24++0x03 line.long 0x00 "PORTE_PCR_9,PORTE Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x24++0x03 line.long 0x00 "PORTE_PCR_9,PORTE Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B endif sif cpuis("MK8?FN256V*") ; 0x28 - adres ; E - litera portu (A,B,C,...) ; 10 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(10>=1)&&(10<=5)) group.long 0x28++0x03 line.long 0x00 "PORTE_PCR_10,PORTE Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(10==0)) group.long 0x28++0x03 line.long 0x00 "PORTE_PCR_10,PORTE Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x28++0x03 line.long 0x00 "PORTE_PCR_10,PORTE Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(10>=1)&&(10<=4)) group.long 0x28++0x03 line.long 0x00 "PORTE_PCR_10,PORTE Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(10==5)) group.long 0x28++0x03 line.long 0x00 "PORTE_PCR_10,PORTE Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(10==0)) group.long 0x28++0x03 line.long 0x00 "PORTE_PCR_10,PORTE Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x28++0x03 line.long 0x00 "PORTE_PCR_10,PORTE Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x28++0x03 line.long 0x00 "PORTE_PCR_10,PORTE Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x28++0x03 line.long 0x00 "PORTE_PCR_10,PORTE Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x28++0x03 line.long 0x00 "PORTE_PCR_10,PORTE Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B else ; 0x28 - adres ; E - litera portu (A,B,C,...) ; 10 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(10>=1)&&(10<=5)) group.long 0x28++0x03 line.long 0x00 "PORTE_PCR_10,PORTE Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(10==0)) group.long 0x28++0x03 line.long 0x00 "PORTE_PCR_10,PORTE Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x28++0x03 line.long 0x00 "PORTE_PCR_10,PORTE Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(10>=1)&&(10<=4)) group.long 0x28++0x03 line.long 0x00 "PORTE_PCR_10,PORTE Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(10==5)) group.long 0x28++0x03 line.long 0x00 "PORTE_PCR_10,PORTE Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(10==0)) group.long 0x28++0x03 line.long 0x00 "PORTE_PCR_10,PORTE Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x28++0x03 line.long 0x00 "PORTE_PCR_10,PORTE Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x28++0x03 line.long 0x00 "PORTE_PCR_10,PORTE Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x28++0x03 line.long 0x00 "PORTE_PCR_10,PORTE Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x28++0x03 line.long 0x00 "PORTE_PCR_10,PORTE Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B endif sif cpuis("MK8?FN256V*") ; 0x2C - adres ; E - litera portu (A,B,C,...) ; 11 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(11>=1)&&(11<=5)) group.long 0x2C++0x03 line.long 0x00 "PORTE_PCR_11,PORTE Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(11==0)) group.long 0x2C++0x03 line.long 0x00 "PORTE_PCR_11,PORTE Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x2C++0x03 line.long 0x00 "PORTE_PCR_11,PORTE Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(11>=1)&&(11<=4)) group.long 0x2C++0x03 line.long 0x00 "PORTE_PCR_11,PORTE Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(11==5)) group.long 0x2C++0x03 line.long 0x00 "PORTE_PCR_11,PORTE Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(11==0)) group.long 0x2C++0x03 line.long 0x00 "PORTE_PCR_11,PORTE Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x2C++0x03 line.long 0x00 "PORTE_PCR_11,PORTE Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x2C++0x03 line.long 0x00 "PORTE_PCR_11,PORTE Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x2C++0x03 line.long 0x00 "PORTE_PCR_11,PORTE Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x2C++0x03 line.long 0x00 "PORTE_PCR_11,PORTE Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B else ; 0x2C - adres ; E - litera portu (A,B,C,...) ; 11 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(11>=1)&&(11<=5)) group.long 0x2C++0x03 line.long 0x00 "PORTE_PCR_11,PORTE Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(11==0)) group.long 0x2C++0x03 line.long 0x00 "PORTE_PCR_11,PORTE Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x2C++0x03 line.long 0x00 "PORTE_PCR_11,PORTE Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(11>=1)&&(11<=4)) group.long 0x2C++0x03 line.long 0x00 "PORTE_PCR_11,PORTE Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(11==5)) group.long 0x2C++0x03 line.long 0x00 "PORTE_PCR_11,PORTE Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(11==0)) group.long 0x2C++0x03 line.long 0x00 "PORTE_PCR_11,PORTE Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x2C++0x03 line.long 0x00 "PORTE_PCR_11,PORTE Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x2C++0x03 line.long 0x00 "PORTE_PCR_11,PORTE Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x2C++0x03 line.long 0x00 "PORTE_PCR_11,PORTE Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x2C++0x03 line.long 0x00 "PORTE_PCR_11,PORTE Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B endif sif cpuis("MK8?FN256V*") ; 0x30 - adres ; E - litera portu (A,B,C,...) ; 12 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(12>=1)&&(12<=5)) group.long 0x30++0x03 line.long 0x00 "PORTE_PCR_12,PORTE Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(12==0)) group.long 0x30++0x03 line.long 0x00 "PORTE_PCR_12,PORTE Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x30++0x03 line.long 0x00 "PORTE_PCR_12,PORTE Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(12>=1)&&(12<=4)) group.long 0x30++0x03 line.long 0x00 "PORTE_PCR_12,PORTE Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(12==5)) group.long 0x30++0x03 line.long 0x00 "PORTE_PCR_12,PORTE Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(12==0)) group.long 0x30++0x03 line.long 0x00 "PORTE_PCR_12,PORTE Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x30++0x03 line.long 0x00 "PORTE_PCR_12,PORTE Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x30++0x03 line.long 0x00 "PORTE_PCR_12,PORTE Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x30++0x03 line.long 0x00 "PORTE_PCR_12,PORTE Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x30++0x03 line.long 0x00 "PORTE_PCR_12,PORTE Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B else ; 0x30 - adres ; E - litera portu (A,B,C,...) ; 12 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(12>=1)&&(12<=5)) group.long 0x30++0x03 line.long 0x00 "PORTE_PCR_12,PORTE Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(12==0)) group.long 0x30++0x03 line.long 0x00 "PORTE_PCR_12,PORTE Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x30++0x03 line.long 0x00 "PORTE_PCR_12,PORTE Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(12>=1)&&(12<=4)) group.long 0x30++0x03 line.long 0x00 "PORTE_PCR_12,PORTE Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(12==5)) group.long 0x30++0x03 line.long 0x00 "PORTE_PCR_12,PORTE Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(12==0)) group.long 0x30++0x03 line.long 0x00 "PORTE_PCR_12,PORTE Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x30++0x03 line.long 0x00 "PORTE_PCR_12,PORTE Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x30++0x03 line.long 0x00 "PORTE_PCR_12,PORTE Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x30++0x03 line.long 0x00 "PORTE_PCR_12,PORTE Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x30++0x03 line.long 0x00 "PORTE_PCR_12,PORTE Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B endif sif cpuis("MK8?FN256V*") else ; 0x34 - adres ; E - litera portu (A,B,C,...) ; 13 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(13>=1)&&(13<=5)) group.long 0x34++0x03 line.long 0x00 "PORTE_PCR_13,PORTE Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(13==0)) group.long 0x34++0x03 line.long 0x00 "PORTE_PCR_13,PORTE Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x34++0x03 line.long 0x00 "PORTE_PCR_13,PORTE Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(13>=1)&&(13<=4)) group.long 0x34++0x03 line.long 0x00 "PORTE_PCR_13,PORTE Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(13==5)) group.long 0x34++0x03 line.long 0x00 "PORTE_PCR_13,PORTE Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(13==0)) group.long 0x34++0x03 line.long 0x00 "PORTE_PCR_13,PORTE Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x34++0x03 line.long 0x00 "PORTE_PCR_13,PORTE Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x34++0x03 line.long 0x00 "PORTE_PCR_13,PORTE Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x34++0x03 line.long 0x00 "PORTE_PCR_13,PORTE Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x34++0x03 line.long 0x00 "PORTE_PCR_13,PORTE Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B endif sif cpuis("MK8?FN256V*") else endif sif cpuis("MK8?FN256V*") else endif sif cpuis("MK8?FN256V*") else ; 0x40 - adres ; E - litera portu (A,B,C,...) ; 16 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(16>=1)&&(16<=5)) group.long 0x40++0x03 line.long 0x00 "PORTE_PCR_16,PORTE Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(16==0)) group.long 0x40++0x03 line.long 0x00 "PORTE_PCR_16,PORTE Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x40++0x03 line.long 0x00 "PORTE_PCR_16,PORTE Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(16>=1)&&(16<=4)) group.long 0x40++0x03 line.long 0x00 "PORTE_PCR_16,PORTE Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(16==5)) group.long 0x40++0x03 line.long 0x00 "PORTE_PCR_16,PORTE Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(16==0)) group.long 0x40++0x03 line.long 0x00 "PORTE_PCR_16,PORTE Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x40++0x03 line.long 0x00 "PORTE_PCR_16,PORTE Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x40++0x03 line.long 0x00 "PORTE_PCR_16,PORTE Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x40++0x03 line.long 0x00 "PORTE_PCR_16,PORTE Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x40++0x03 line.long 0x00 "PORTE_PCR_16,PORTE Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B endif sif cpuis("MK8?FN256V*") else ; 0x44 - adres ; E - litera portu (A,B,C,...) ; 17 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(17>=1)&&(17<=5)) group.long 0x44++0x03 line.long 0x00 "PORTE_PCR_17,PORTE Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(17==0)) group.long 0x44++0x03 line.long 0x00 "PORTE_PCR_17,PORTE Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x44++0x03 line.long 0x00 "PORTE_PCR_17,PORTE Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(17>=1)&&(17<=4)) group.long 0x44++0x03 line.long 0x00 "PORTE_PCR_17,PORTE Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(17==5)) group.long 0x44++0x03 line.long 0x00 "PORTE_PCR_17,PORTE Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(17==0)) group.long 0x44++0x03 line.long 0x00 "PORTE_PCR_17,PORTE Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x44++0x03 line.long 0x00 "PORTE_PCR_17,PORTE Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x44++0x03 line.long 0x00 "PORTE_PCR_17,PORTE Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x44++0x03 line.long 0x00 "PORTE_PCR_17,PORTE Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x44++0x03 line.long 0x00 "PORTE_PCR_17,PORTE Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B endif sif cpuis("MK8?FN256V*") else ; 0x48 - adres ; E - litera portu (A,B,C,...) ; 18 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(18>=1)&&(18<=5)) group.long 0x48++0x03 line.long 0x00 "PORTE_PCR_18,PORTE Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(18==0)) group.long 0x48++0x03 line.long 0x00 "PORTE_PCR_18,PORTE Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x48++0x03 line.long 0x00 "PORTE_PCR_18,PORTE Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(18>=1)&&(18<=4)) group.long 0x48++0x03 line.long 0x00 "PORTE_PCR_18,PORTE Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(18==5)) group.long 0x48++0x03 line.long 0x00 "PORTE_PCR_18,PORTE Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(18==0)) group.long 0x48++0x03 line.long 0x00 "PORTE_PCR_18,PORTE Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x48++0x03 line.long 0x00 "PORTE_PCR_18,PORTE Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x48++0x03 line.long 0x00 "PORTE_PCR_18,PORTE Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x48++0x03 line.long 0x00 "PORTE_PCR_18,PORTE Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x48++0x03 line.long 0x00 "PORTE_PCR_18,PORTE Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B endif sif cpuis("MK8?FN256V*") else ; 0x4C - adres ; E - litera portu (A,B,C,...) ; 19 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(19>=1)&&(19<=5)) group.long 0x4C++0x03 line.long 0x00 "PORTE_PCR_19,PORTE Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(19==0)) group.long 0x4C++0x03 line.long 0x00 "PORTE_PCR_19,PORTE Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4C++0x03 line.long 0x00 "PORTE_PCR_19,PORTE Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(19>=1)&&(19<=4)) group.long 0x4C++0x03 line.long 0x00 "PORTE_PCR_19,PORTE Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(19==5)) group.long 0x4C++0x03 line.long 0x00 "PORTE_PCR_19,PORTE Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(19==0)) group.long 0x4C++0x03 line.long 0x00 "PORTE_PCR_19,PORTE Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4C++0x03 line.long 0x00 "PORTE_PCR_19,PORTE Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x4C++0x03 line.long 0x00 "PORTE_PCR_19,PORTE Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x4C++0x03 line.long 0x00 "PORTE_PCR_19,PORTE Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4C++0x03 line.long 0x00 "PORTE_PCR_19,PORTE Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B endif sif cpuis("MK8?FN256V*") else endif sif cpuis("MK8?FN256V*") else endif sif cpuis("MK8?FN256V*") else endif sif cpuis("MK8?FN256V*") else endif sif cpuis("MK8?FN256V*") else endif sif cpuis("MK8?FN256V*") else endif sif cpuis("MK8?FN256V*") else endif sif cpuis("MK8?FN256V*") else endif sif cpuis("MK8?FN256V*") else endif sif cpuis("MK8?FN256V*") else endif sif cpuis("MK8?FN256V*") else endif sif cpuis("MK8?FN256V*") else endif tree.end newline width 13. wgroup.long 0x80++0x03 line.long 0x00 "PORTE_GPCLR,PORTE Global Pin Control Low Register" sif !cpuis("MK8?FN256V*") bitfld.long 0x00 29. " GPWE_13 ,Global Pin 13 Write Enable" "Disable,Enable" endif bitfld.long 0x00 28. " GPWE_12 ,Global Pin 12 Write Enable" "Disable,Enable" bitfld.long 0x00 27. " GPWE_11 ,Global Pin 11 Write Enable" "Disable,Enable" bitfld.long 0x00 26. " GPWE_10 ,Global Pin 10 Write Enable" "Disable,Enable" newline bitfld.long 0x00 25. " GPWE_9 ,Global Pin 9 Write Enable" "Disable,Enable" bitfld.long 0x00 24. " GPWE_8 ,Global Pin 8 Write Enable" "Disable,Enable" bitfld.long 0x00 23. " GPWE_7 ,Global Pin 7 Write Enable" "Disable,Enable" bitfld.long 0x00 22. " GPWE_6 ,Global Pin 6 Write Enable" "Disable,Enable" newline bitfld.long 0x00 21. " GPWE_5 ,Global Pin 5 Write Enable" "Disable,Enable" bitfld.long 0x00 20. " GPWE_4 ,Global Pin 4 Write Enable" "Disable,Enable" bitfld.long 0x00 19. " GPWE_3 ,Global Pin 3 Write Enable" "Disable,Enable" bitfld.long 0x00 18. " GPWE_2 ,Global Pin 2 Write Enable" "Disable,Enable" newline bitfld.long 0x00 17. " GPWE_1 ,Global Pin 1 Write Enable" "Disable,Enable" bitfld.long 0x00 16. " GPWE_0 ,Global Pin 0 Write Enable" "Disable,Enable" newline hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global Pin Write Data" sif !cpuis("MK8?FN256V*") wgroup.long 0x84++0x03 line.long 0x00 "PORTE_GPCHR,PORTE Global Pin Control High Register" bitfld.long 0x00 19. " GPWE_19 ,Global Pin 19 Write Enable" "Disable,Enable" bitfld.long 0x00 18. " GPWE_18 ,Global Pin 18 Write Enable" "Disable,Enable" bitfld.long 0x00 17. " GPWE_17 ,Global Pin 17 Write Enable" "Disable,Enable" bitfld.long 0x00 16. " GPWE_16 ,Global Pin 16 Write Enable" "Disable,Enable" newline hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global Pin Write Data" endif group.long 0xA0++0x03 line.long 0x00 "PORTE_ISFR,PORTE Interrupt Status Flag Register" sif !cpuis("MK8?FN256V*") eventfld.long 0x00 19. " ISF_19 ,Interrupt Status Flag 19 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 18. " ISF_18 ,Interrupt Status Flag 18 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 17. " ISF_17 ,Interrupt Status Flag 17 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 16. " ISF_16 ,Interrupt Status Flag 16 (In Digital Modes only)" "No interrupt,Interrupt" newline eventfld.long 0x00 13. " ISF_13 ,Interrupt Status Flag 13 (In Digital Modes only)" "No interrupt,Interrupt" endif eventfld.long 0x00 12. " ISF_12 ,Interrupt Status Flag 12 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 11. " ISF_11 ,Interrupt Status Flag 11 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 10. " ISF_10 ,Interrupt Status Flag 10 (In Digital Modes only)" "No interrupt,Interrupt" newline eventfld.long 0x00 9. " ISF_9 ,Interrupt Status Flag 9 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 8. " ISF_8 ,Interrupt Status Flag 8 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 7. " ISF_7 ,Interrupt Status Flag 7 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 6. " ISF_6 ,Interrupt Status Flag 6 (In Digital Modes only)" "No interrupt,Interrupt" newline eventfld.long 0x00 5. " ISF_5 ,Interrupt Status Flag 5 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 4. " ISF_4 ,Interrupt Status Flag 4 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 3. " ISF_3 ,Interrupt Status Flag 3 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 2. " ISF_2 ,Interrupt Status Flag 2 (In Digital Modes only)" "No interrupt,Interrupt" newline eventfld.long 0x00 1. " ISF_1 ,Interrupt Status Flag 1 (In Digital Modes only)" "No interrupt,Interrupt" eventfld.long 0x00 0. " ISF_0 ,Interrupt Status Flag 0 (In Digital Modes only)" "No interrupt,Interrupt" group.long 0xC0++0x0B line.long 0x00 "PORTE_DFER,Digital Filter Enable Register" sif !cpuis("MK8?FN256V*") bitfld.long 0x00 19. " DFE_19 ,Pin 19 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 18. " DFE_18 ,Pin 18 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 17. " DFE_17 ,Pin 17 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 16. " DFE_16 ,Pin 16 digital filter enable" "Disabled,Enabled" newline bitfld.long 0x00 13. " DFE_13 ,Pin 13 digital filter enable" "Disabled,Enabled" endif bitfld.long 0x00 12. " DFE_12 ,Pin 12 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 11. " DFE_11 ,Pin 11 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 10. " DFE_10 ,Pin 10 digital filter enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " DFE_9 ,Pin 9 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 8. " DFE_8 ,Pin 8 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DFE_7 ,Pin 7 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " DFE_6 ,Pin 6 digital filter enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " DFE_5 ,Pin 5 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 4. " DFE_4 ,Pin 4 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 3. " DFE_3 ,Pin 3 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " DFE_2 ,Pin 2 digital filter enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " DFE_1 ,Pin 1 digital filter enable" "Disabled,Enabled" bitfld.long 0x00 0. " DFE_0 ,Pin 0 digital filter enable" "Disabled,Enabled" line.long 0x04 "PORTE_DFCR,Digital Filter Clock Register" bitfld.long 0x04 0. " CS ,Clock source" "Bus clock,LPO clock" line.long 0x08 "PORTE_DFWR,Digital Filter Width Register" bitfld.long 0x08 0.--4. " FILT ,Filter length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree.end tree "SIM (System Integration Module)" base ad:0x40047000 width 10. sif cpuis("MK8?FN256V*") if (((per.l(ad:0x40047000+0x04))&0x7000000)==0x7000000) group.long 0x00++0x03 line.long 0x00 "SOPT1,System Options Register 1" bitfld.long 0x00 31. " USBREGEN ,USB voltage regulator enable" "Disabled,Enabled" bitfld.long 0x00 30. " USBSSTBY ,USB voltage regulator in standby mode during Stop & VLPS & LLS and VLLS modes" "Not in standby,In standby" bitfld.long 0x00 29. " USBVSTBY ,USB voltage regulator in standby mode during VLPR and VLPW modes" "Not in standby,In standby" newline bitfld.long 0x00 18.--19. " OSC32KSEL ,32K oscillator clock select" "OSC32KCLK,,RTC,LPO" rbitfld.long 0x00 12.--15. " RAMSIZE ,RAM size" ",8 KB,16 KB,24 KB,32 KB,48 KB,64 KB,96 KB,128 KB,256 KB,?..." elif (((per.l(ad:0x40047000+0x04))&0x7000000)==0x6000000) group.long 0x00++0x03 line.long 0x00 "SOPT1,System Options Register 1" rbitfld.long 0x00 31. " USBREGEN ,USB voltage regulator enable" "Disabled,Enabled" bitfld.long 0x00 30. " USBSSTBY ,USB voltage regulator in standby mode during Stop & VLPS & LLS and VLLS modes" "Not in standby,In standby" bitfld.long 0x00 29. " USBVSTBY ,USB voltage regulator in standby mode during VLPR and VLPW modes" "Not in standby,In standby" newline bitfld.long 0x00 18.--19. " OSC32KSEL ,32K oscillator clock select" "OSC32KCLK,,RTC,LPO" rbitfld.long 0x00 12.--15. " RAMSIZE ,RAM size" "8 KB,16 KB,24 KB,32 KB,48 KB,64 KB,96 KB,128 KB,256 KB,?..." elif (((per.l(ad:0x40047000+0x04))&0x7000000)==0x5000000) group.long 0x00++0x03 line.long 0x00 "SOPT1,System Options Register 1" bitfld.long 0x00 31. " USBREGEN ,USB voltage regulator enable" "Disabled,Enabled" bitfld.long 0x00 30. " USBSSTBY ,USB voltage regulator in standby mode during Stop & VLPS & LLS and VLLS modes" "Not in standby,In standby" rbitfld.long 0x00 29. " USBVSTBY ,USB voltage regulator in standby mode during VLPR and VLPW modes" "Not in standby,In standby" newline bitfld.long 0x00 18.--19. " OSC32KSEL ,32K oscillator clock select" "OSC32KCLK,,RTC,LPO" rbitfld.long 0x00 12.--15. " RAMSIZE ,RAM size" "8 KB,16 KB,24 KB,32 KB,48 KB,64 KB,96 KB,128 KB,256 KB,?..." elif (((per.l(ad:0x40047000+0x04))&0x7000000)==0x4000000) group.long 0x00++0x03 line.long 0x00 "SOPT1,System Options Register 1" rbitfld.long 0x00 31. " USBREGEN ,USB voltage regulator enable" "Disabled,Enabled" bitfld.long 0x00 30. " USBSSTBY ,USB voltage regulator in standby mode during Stop & VLPS & LLS and VLLS modes" "Not in standby,In standby" rbitfld.long 0x00 29. " USBVSTBY ,USB voltage regulator in standby mode during VLPR and VLPW modes" "Not in standby,In standby" newline bitfld.long 0x00 18.--19. " OSC32KSEL ,32K oscillator clock select" "OSC32KCLK,,RTC,LPO" rbitfld.long 0x00 12.--15. " RAMSIZE ,RAM size" "8 KB,16 KB,24 KB,32 KB,48 KB,64 KB,96 KB,128 KB,256 KB,?..." elif (((per.l(ad:0x40047000+0x04))&0x7000000)==0x3000000) group.long 0x00++0x03 line.long 0x00 "SOPT1,System Options Register 1" bitfld.long 0x00 31. " USBREGEN ,USB voltage regulator enable" "Disabled,Enabled" rbitfld.long 0x00 30. " USBSSTBY ,USB voltage regulator in standby mode during Stop & VLPS & LLS and VLLS modes" "Not in standby,In standby" bitfld.long 0x00 29. " USBVSTBY ,USB voltage regulator in standby mode during VLPR and VLPW modes" "Not in standby,In standby" newline bitfld.long 0x00 18.--19. " OSC32KSEL ,32K oscillator clock select" "OSC32KCLK,,RTC,LPO" rbitfld.long 0x00 12.--15. " RAMSIZE ,RAM size" "8 KB,16 KB,24 KB,32 KB,48 KB,64 KB,96 KB,128 KB,256 KB,?..." elif (((per.l(ad:0x40047000+0x04))&0x7000000)==0x2000000) group.long 0x00++0x03 line.long 0x00 "SOPT1,System Options Register 1" rbitfld.long 0x00 31. " USBREGEN ,USB voltage regulator enable" "Disabled,Enabled" rbitfld.long 0x00 30. " USBSSTBY ,USB voltage regulator in standby mode during Stop & VLPS & LLS and VLLS modes" "Not in standby,In standby" bitfld.long 0x00 29. " USBVSTBY ,USB voltage regulator in standby mode during VLPR and VLPW modes" "Not in standby,In standby" newline bitfld.long 0x00 18.--19. " OSC32KSEL ,32K oscillator clock select" "OSC32KCLK,,RTC,LPO" rbitfld.long 0x00 12.--15. " RAMSIZE ,RAM size" "8 KB,16 KB,24 KB,32 KB,48 KB,64 KB,96 KB,128 KB,256 KB,?..." elif (((per.l(ad:0x40047000+0x04))&0x7000000)==0x1000000) group.long 0x00++0x03 line.long 0x00 "SOPT1,System Options Register 1" bitfld.long 0x00 31. " USBREGEN ,USB voltage regulator enable" "Disabled,Enabled" rbitfld.long 0x00 30. " USBSSTBY ,USB voltage regulator in standby mode during Stop & VLPS & LLS and VLLS modes" "Not in standby,In standby" rbitfld.long 0x00 29. " USBVSTBY ,USB voltage regulator in standby mode during VLPR and VLPW modes" "Not in standby,In standby" newline bitfld.long 0x00 18.--19. " OSC32KSEL ,32K oscillator clock select" "OSC32KCLK,,RTC,LPO" rbitfld.long 0x00 12.--15. " RAMSIZE ,RAM size" "8 KB,16 KB,24 KB,32 KB,48 KB,64 KB,96 KB,128 KB,256 KB,?..." else group.long 0x00++0x03 line.long 0x00 "SOPT1,System Options Register 1" rbitfld.long 0x00 31. " USBREGEN ,USB voltage regulator enable" "Disabled,Enabled" rbitfld.long 0x00 30. " USBSSTBY ,USB voltage regulator in standby mode during Stop & VLPS & LLS and VLLS modes" "Not in standby,In standby" rbitfld.long 0x00 29. " USBVSTBY ,USB voltage regulator in standby mode during VLPR and VLPW modes" "Not in standby,In standby" newline bitfld.long 0x00 18.--19. " OSC32KSEL ,32K oscillator clock select" "OSC32KCLK,,RTC,LPO" rbitfld.long 0x00 12.--15. " RAMSIZE ,RAM size" "8 KB,16 KB,24 KB,32 KB,48 KB,64 KB,96 KB,128 KB,256 KB,?..." endif group.long 0x04++0x03 line.long 0x00 "SOPT1CFG,SOPT1 Configuration Register" bitfld.long 0x00 26. " USSWE ,USB voltage regulator stop standby write enable" "Disabled,Enabled" bitfld.long 0x00 25. " UVSWE ,UUSB voltage regulator VLP standby write enable" "Disabled,Enabled" bitfld.long 0x00 24. " URWE ,USB voltage regulator enable write enable" "Disabled,Enabled" if (((per.l(ad:0x40047000+0x1004))&0x30000)==0x00) group.long 0x1004++0x03 line.long 0x00 "SOPT2,System Options Register 2" bitfld.long 0x00 30.--31. " EMVSIMSRC ,EMVSIM Module Clock Source Select" "Disabled,MCGFLLCLK,OSCERCLK,MCGIRCLK" bitfld.long 0x00 28.--29. " SDHCSRC ,SDHC clock source select" "Core/system clock,MCGFLLCLK,OSCERCLK,SDHC0_CLKIN" bitfld.long 0x00 26.--27. " LPUARTSRC ,LPUART clock source select" "Disabled,MCGFLLCLK,OSCERCLK,MCGIRCLK" newline bitfld.long 0x00 24.--25. " TPMSRC ,TPM clock source select" "Disabled,MCGFLLCLK,OSCERCLK,MCGIRCLK" bitfld.long 0x00 22.--23. " FLEXIOSRC ,FlexIO Module Clock Source Select" "System clock,MCGFLLCLK,OSCERCLK,MCGIRCLK" bitfld.long 0x00 18. " USBSRC ,USB clock source select" "USB_CLKIN,MCGFLLCLK" newline bitfld.long 0x00 16.--17. " PLLFLLSEL ,PLL/FLL clock select" "MCGFLLCLK,MCGPLLCLK,,IRC48" bitfld.long 0x00 12. " TRACECLKSEL ,Debug trace clock select" "MCGOUTCLK,Core/system clock" bitfld.long 0x00 8.--9. " FBSL ,Flexbus security level. Off-chip accesses via FlexBus or SDRAM instruction/data" "Not allowed/Not allowed,Not allowed/Not allowed,Not allowed/Allowed,Allowed/Allowed" newline bitfld.long 0x00 5.--7. " CLKOUTSEL ,Clock out select" "FlexBus CLKOUT,,Flash clock,LPO clock,MCGIRCLK,RTC clock,OSCERCLK0,IRC48M" bitfld.long 0x00 4. " RTCCLKOUTSEL ,RTC clock out select" "1 Hz,32 kHz" elif (((per.l(ad:0x40047000+0x1004))&0x30000)==0x10000) group.long 0x1004++0x03 line.long 0x00 "SOPT2,System Options Register 2" bitfld.long 0x00 30.--31. " EMVSIMSRC ,EMVSIM Module Clock Source Select" "Disabled,MCGPLLCLK,OSCERCLK,MCGIRCLK" bitfld.long 0x00 28.--29. " SDHCSRC ,SDHC clock source select" "Core/system clock,MCGPLLCLK,OSCERCLK,SDHC0_CLKIN" bitfld.long 0x00 26.--27. " LPUARTSRC ,LPUART clock source select" "Disabled,MCGPLLCLK,OSCERCLK,MCGIRCLK" newline bitfld.long 0x00 24.--25. " TPMSRC ,TPM clock source select" "Disabled,MCGPLLCLK,OSCERCLK,MCGIRCLK" bitfld.long 0x00 22.--23. " FLEXIOSRC ,FlexIO Module Clock Source Select" "System clock,MCGPLLCLK,OSCERCLK,MCGIRCLK" bitfld.long 0x00 18. " USBSRC ,USB clock source select" "USB_CLKIN,MCGPLLCLK" newline bitfld.long 0x00 16.--17. " PLLFLLSEL ,PLL/FLL clock select" "MCGFLLCLK,MCGPLLCLK,,IRC48" bitfld.long 0x00 12. " TRACECLKSEL ,Debug trace clock select" "MCGOUTCLK,Core/system clock" bitfld.long 0x00 8.--9. " FBSL ,Flexbus security level. Off-chip accesses via FlexBus or SDRAM instruction/data" "Not allowed/Not allowed,Not allowed/Not allowed,Not allowed/Allowed,Allowed/Allowed" newline bitfld.long 0x00 5.--7. " CLKOUTSEL ,Clock out select" "FlexBus CLKOUT,,Flash clock,LPO clock,MCGIRCLK,RTC clock,OSCERCLK0,IRC48M" bitfld.long 0x00 4. " RTCCLKOUTSEL ,RTC clock out select" "1 Hz,32 kHz" elif (((per.l(ad:0x40047000+0x1004))&0x30000)==0x30000) group.long 0x1004++0x03 line.long 0x00 "SOPT2,System Options Register 2" bitfld.long 0x00 30.--31. " EMVSIMSRC ,EMVSIM Module Clock Source Select" "Disabled,IRC48M,OSCERCLK,MCGIRCLK" bitfld.long 0x00 28.--29. " SDHCSRC ,SDHC clock source select" "Core/system clock,IRC48M,OSCERCLK,SDHC0_CLKIN" bitfld.long 0x00 26.--27. " LPUARTSRC ,LPUART clock source select" "Disabled,IRC48M,OSCERCLK,MCGIRCLK" newline bitfld.long 0x00 24.--25. " TPMSRC ,TPM clock source select" "Disabled,IRC48M,OSCERCLK,MCGIRCLK" bitfld.long 0x00 22.--23. " FLEXIOSRC ,FlexIO Module Clock Source Select" "System clock,IRC48M,OSCERCLK,MCGIRCLK" bitfld.long 0x00 18. " USBSRC ,USB clock source select" "USB_CLKIN,IRC48M" newline bitfld.long 0x00 16.--17. " PLLFLLSEL ,PLL/FLL clock select" "MCGFLLCLK,MCGPLLCLK,,IRC48" bitfld.long 0x00 12. " TRACECLKSEL ,Debug trace clock select" "MCGOUTCLK,Core/system clock" bitfld.long 0x00 8.--9. " FBSL ,Flexbus security level. Off-chip accesses via FlexBus or SDRAM instruction/data" "Not allowed/Not allowed,Not allowed/Not allowed,Not allowed/Allowed,Allowed/Allowed" newline newline bitfld.long 0x00 5.--7. " CLKOUTSEL ,Clock out select" "FlexBus CLKOUT,,Flash clock,LPO clock,MCGIRCLK,RTC clock,OSCERCLK0,IRC48M" bitfld.long 0x00 4. " RTCCLKOUTSEL ,RTC clock out select" "1 Hz,32 kHz" else group.long 0x1004++0x03 line.long 0x00 "SOPT2,System Options Register 2" bitfld.long 0x00 30.--31. " EMVSIMSRC ,EMVSIM Module Clock Source Select" "Disabled,,OSCERCLK,MCGIRCLK" bitfld.long 0x00 28.--29. " SDHCSRC ,SDHC clock source select" "Core/system clock,,OSCERCLK,SDHC0_CLKIN" bitfld.long 0x00 26.--27. " LPUARTSRC ,LPUART clock source select" "Disabled,,OSCERCLK,MCGIRCLK" newline bitfld.long 0x00 24.--25. " TPMSRC ,TPM clock source select" "Disabled,,OSCERCLK,MCGIRCLK" bitfld.long 0x00 22.--23. " FLEXIOSRC ,FlexIO Module Clock Source Select" "System clock,,OSCERCLK,MCGIRCLK" bitfld.long 0x00 18. " USBSRC ,USB clock source select" "USB_CLKIN,?..." newline bitfld.long 0x00 16.--17. " PLLFLLSEL ,PLL/FLL clock select" "MCGFLLCLK,MCGPLLCLK,,IRC48" bitfld.long 0x00 12. " TRACECLKSEL ,Debug trace clock select" "MCGOUTCLK,Core/system clock" bitfld.long 0x00 8.--9. " FBSL ,Flexbus security level. Off-chip accesses via FlexBus or SDRAM instruction/data" "Not allowed/Not allowed,Not allowed/Not allowed,Not allowed/Allowed,Allowed/Allowed" newline newline bitfld.long 0x00 5.--7. " CLKOUTSEL ,Clock out select" "FlexBus CLKOUT,,Flash clock,LPO clock,MCGIRCLK,RTC clock,OSCERCLK0,IRC48M" bitfld.long 0x00 4. " RTCCLKOUTSEL ,RTC clock out select" "1 Hz,32 kHz" endif else if (((per.l(ad:0x40047000+0x04))&0x7000000)==0x7000000) group.long 0x00++0x03 line.long 0x00 "SOPT1,System Options Register 1" bitfld.long 0x00 31. " USBREGEN ,USB voltage regulator enable" "Disabled,Enabled" bitfld.long 0x00 30. " USBSSTBY ,USB voltage regulator in standby mode during Stop & VLPS & LLS and VLLS modes" "Not in standby,In standby" bitfld.long 0x00 29. " USBVSTBY ,USB voltage regulator in standby mode during VLPR and VLPW modes" "Not in standby,In standby" bitfld.long 0x00 18.--19. " OSC32KSEL ,32K oscillator clock select" "OSC32KCLK,,RTC,LPO" newline rbitfld.long 0x00 12.--15. " RAMSIZE ,RAM size" "8 KB,16 KB,24 KB,32 KB,48 KB,64 KB,96 KB,128 KB,256 KB,512 KB,1024 KB,?..." elif (((per.l(ad:0x40047000+0x04))&0x7000000)==0x6000000) group.long 0x00++0x03 line.long 0x00 "SOPT1,System Options Register 1" rbitfld.long 0x00 31. " USBREGEN ,USB voltage regulator enable" "Disabled,Enabled" bitfld.long 0x00 30. " USBSSTBY ,USB voltage regulator in standby mode during Stop & VLPS & LLS and VLLS modes" "Not in standby,In standby" bitfld.long 0x00 29. " USBVSTBY ,USB voltage regulator in standby mode during VLPR and VLPW modes" "Not in standby,In standby" bitfld.long 0x00 18.--19. " OSC32KSEL ,32K oscillator clock select" "OSC32KCLK,,RTC,LPO" newline rbitfld.long 0x00 12.--15. " RAMSIZE ,RAM size" "8 KB,16 KB,24 KB,32 KB,48 KB,64 KB,96 KB,128 KB,256 KB,512 KB,1024 KB,?..." elif (((per.l(ad:0x40047000+0x04))&0x7000000)==0x5000000) group.long 0x00++0x03 line.long 0x00 "SOPT1,System Options Register 1" bitfld.long 0x00 31. " USBREGEN ,USB voltage regulator enable" "Disabled,Enabled" bitfld.long 0x00 30. " USBSSTBY ,USB voltage regulator in standby mode during Stop & VLPS & LLS and VLLS modes" "Not in standby,In standby" rbitfld.long 0x00 29. " USBVSTBY ,USB voltage regulator in standby mode during VLPR and VLPW modes" "Not in standby,In standby" bitfld.long 0x00 18.--19. " OSC32KSEL ,32K oscillator clock select" "OSC32KCLK,,RTC,LPO" newline rbitfld.long 0x00 12.--15. " RAMSIZE ,RAM size" "8 KB,16 KB,24 KB,32 KB,48 KB,64 KB,96 KB,128 KB,256 KB,512 KB,1024 KB,?..." elif (((per.l(ad:0x40047000+0x04))&0x7000000)==0x4000000) group.long 0x00++0x03 line.long 0x00 "SOPT1,System Options Register 1" rbitfld.long 0x00 31. " USBREGEN ,USB voltage regulator enable" "Disabled,Enabled" bitfld.long 0x00 30. " USBSSTBY ,USB voltage regulator in standby mode during Stop & VLPS & LLS and VLLS modes" "Not in standby,In standby" rbitfld.long 0x00 29. " USBVSTBY ,USB voltage regulator in standby mode during VLPR and VLPW modes" "Not in standby,In standby" bitfld.long 0x00 18.--19. " OSC32KSEL ,32K oscillator clock select" "OSC32KCLK,,RTC,LPO" newline rbitfld.long 0x00 12.--15. " RAMSIZE ,RAM size" "8 KB,16 KB,24 KB,32 KB,48 KB,64 KB,96 KB,128 KB,256 KB,512 KB,1024 KB,?..." elif (((per.l(ad:0x40047000+0x04))&0x7000000)==0x3000000) group.long 0x00++0x03 line.long 0x00 "SOPT1,System Options Register 1" bitfld.long 0x00 31. " USBREGEN ,USB voltage regulator enable" "Disabled,Enabled" rbitfld.long 0x00 30. " USBSSTBY ,USB voltage regulator in standby mode during Stop & VLPS & LLS and VLLS modes" "Not in standby,In standby" bitfld.long 0x00 29. " USBVSTBY ,USB voltage regulator in standby mode during VLPR and VLPW modes" "Not in standby,In standby" bitfld.long 0x00 18.--19. " OSC32KSEL ,32K oscillator clock select" "OSC32KCLK,,RTC,LPO" newline rbitfld.long 0x00 12.--15. " RAMSIZE ,RAM size" "8 KB,16 KB,24 KB,32 KB,48 KB,64 KB,96 KB,128 KB,256 KB,512 KB,1024 KB,?..." elif (((per.l(ad:0x40047000+0x04))&0x7000000)==0x2000000) group.long 0x00++0x03 line.long 0x00 "SOPT1,System Options Register 1" rbitfld.long 0x00 31. " USBREGEN ,USB voltage regulator enable" "Disabled,Enabled" rbitfld.long 0x00 30. " USBSSTBY ,USB voltage regulator in standby mode during Stop & VLPS & LLS and VLLS modes" "Not in standby,In standby" bitfld.long 0x00 29. " USBVSTBY ,USB voltage regulator in standby mode during VLPR and VLPW modes" "Not in standby,In standby" bitfld.long 0x00 18.--19. " OSC32KSEL ,32K oscillator clock select" "OSC32KCLK,,RTC,LPO" newline rbitfld.long 0x00 12.--15. " RAMSIZE ,RAM size" "8 KB,16 KB,24 KB,32 KB,48 KB,64 KB,96 KB,128 KB,256 KB,512 KB,1024 KB,?..." elif (((per.l(ad:0x40047000+0x04))&0x7000000)==0x1000000) group.long 0x00++0x03 line.long 0x00 "SOPT1,System Options Register 1" bitfld.long 0x00 31. " USBREGEN ,USB voltage regulator enable" "Disabled,Enabled" rbitfld.long 0x00 30. " USBSSTBY ,USB voltage regulator in standby mode during Stop & VLPS & LLS and VLLS modes" "Not in standby,In standby" rbitfld.long 0x00 29. " USBVSTBY ,USB voltage regulator in standby mode during VLPR and VLPW modes" "Not in standby,In standby" bitfld.long 0x00 18.--19. " OSC32KSEL ,32K oscillator clock select" "OSC32KCLK,,RTC,LPO" newline rbitfld.long 0x00 12.--15. " RAMSIZE ,RAM size" "8 KB,16 KB,24 KB,32 KB,48 KB,64 KB,96 KB,128 KB,256 KB,512 KB,1024 KB,?..." else group.long 0x00++0x03 line.long 0x00 "SOPT1,System Options Register 1" rbitfld.long 0x00 31. " USBREGEN ,USB voltage regulator enable" "Disabled,Enabled" rbitfld.long 0x00 30. " USBSSTBY ,USB voltage regulator in standby mode during Stop & VLPS & LLS and VLLS modes" "Not in standby,In standby" rbitfld.long 0x00 29. " USBVSTBY ,USB voltage regulator in standby mode during VLPR and VLPW modes" "Not in standby,In standby" bitfld.long 0x00 18.--19. " OSC32KSEL ,32K oscillator clock select" "OSC32KCLK,,RTC,LPO" newline rbitfld.long 0x00 12.--15. " RAMSIZE ,RAM size" "8 KB,16 KB,24 KB,32 KB,48 KB,64 KB,96 KB,128 KB,256 KB,512 KB,1024 KB,?..." endif group.long 0x04++0x03 line.long 0x00 "SOPT1CFG,SOPT1 Configuration Register" bitfld.long 0x00 26. " USSWE ,USB voltage regulator stop standby write enable" "Disabled,Enabled" bitfld.long 0x00 25. " UVSWE ,UUSB voltage regulator VLP standby write enable" "Disabled,Enabled" bitfld.long 0x00 24. " URWE ,USB voltage regulator enable write enable" "Disabled,Enabled" if (((per.l(ad:0x40047000+0x1004))&0x30000)==0x00) group.long 0x1004++0x03 line.long 0x00 "SOPT2,System Options Register 2" bitfld.long 0x00 28.--29. " SDHCSRC ,SDHC clock source select" "Core/system clock,MCGFLLCLK,OSCERCLK,SDHC0_CLKIN" bitfld.long 0x00 26.--27. " LPUARTSRC ,LPUART clock source select" "Disabled,MCGFLLCLK,OSCERCLK,MCGIRCLK" bitfld.long 0x00 24.--25. " TPMSRC ,TPM clock source select" "Disabled,MCGFLLCLK,OSCERCLK,MCGIRCLK" newline bitfld.long 0x00 22.--23. " FLEXIOSRC ,FlexIO Module Clock Source Select" "System clock,MCGFLLCLK,OSCERCLK,MCGIRCLK" bitfld.long 0x00 18. " USBSRC ,USB clock source select" "USB_CLKIN,MCGFLLCLK" bitfld.long 0x00 16.--17. " PLLFLLSEL ,PLL/FLL clock select" "MCGFLLCLK,MCGPLLCLK,,IRC48" newline bitfld.long 0x00 12. " TRACECLKSEL ,Debug trace clock select" "MCGOUTCLK,Core/system clock" bitfld.long 0x00 8.--9. " FBSL ,Flexbus security level. Off-chip accesses via FlexBus or SDRAM instruction/data" "Not allowed/Not allowed,Not allowed/Not allowed,Not allowed/Allowed,Allowed/Allowed" newline bitfld.long 0x00 5.--7. " CLKOUTSEL ,Clock out select" "FlexBus CLKOUT,,Flash clock,LPO clock,MCGIRCLK,RTC clock,OSCERCLK0,IRC48M" newline bitfld.long 0x00 4. " RTCCLKOUTSEL ,RTC clock out select" "1 Hz,32 kHz" elif (((per.l(ad:0x40047000+0x1004))&0x30000)==0x10000) group.long 0x1004++0x03 line.long 0x00 "SOPT2,System Options Register 2" bitfld.long 0x00 28.--29. " SDHCSRC ,SDHC clock source select" "Core/system clock,MCGPLLCLK,OSCERCLK,SDHC0_CLKIN" bitfld.long 0x00 26.--27. " LPUARTSRC ,LPUART clock source select" "Disabled,MCGPLLCLK,OSCERCLK,MCGIRCLK" bitfld.long 0x00 24.--25. " TPMSRC ,TPM clock source select" "Disabled,MCGPLLCLK,OSCERCLK,MCGIRCLK" newline bitfld.long 0x00 22.--23. " FLEXIOSRC ,FlexIO Module Clock Source Select" "System clock,MCGPLLCLK,OSCERCLK,MCGIRCLK" bitfld.long 0x00 18. " USBSRC ,USB clock source select" "USB_CLKIN,MCGPLLCLK" bitfld.long 0x00 16.--17. " PLLFLLSEL ,PLL/FLL clock select" "MCGFLLCLK,MCGPLLCLK,,IRC48" newline bitfld.long 0x00 12. " TRACECLKSEL ,Debug trace clock select" "MCGOUTCLK,Core/system clock" bitfld.long 0x00 8.--9. " FBSL ,Flexbus security level. Off-chip accesses via FlexBus or SDRAM instruction/data" "Not allowed/Not allowed,Not allowed/Not allowed,Not allowed/Allowed,Allowed/Allowed" newline bitfld.long 0x00 5.--7. " CLKOUTSEL ,Clock out select" "FlexBus CLKOUT,,Flash clock,LPO clock,MCGIRCLK,RTC clock,OSCERCLK0,IRC48M" newline bitfld.long 0x00 4. " RTCCLKOUTSEL ,RTC clock out select" "1 Hz,32 kHz" elif (((per.l(ad:0x40047000+0x1004))&0x30000)==0x30000) group.long 0x1004++0x03 line.long 0x00 "SOPT2,System Options Register 2" bitfld.long 0x00 28.--29. " SDHCSRC ,SDHC clock source select" "Core/system clock,IRC48M,OSCERCLK,SDHC0_CLKIN" bitfld.long 0x00 26.--27. " LPUARTSRC ,LPUART clock source select" "Disabled,IRC48M,OSCERCLK,MCGIRCLK" bitfld.long 0x00 24.--25. " TPMSRC ,TPM clock source select" "Disabled,IRC48M,OSCERCLK,MCGIRCLK" newline bitfld.long 0x00 22.--23. " FLEXIOSRC ,FlexIO Module Clock Source Select" "System clock,IRC48M,OSCERCLK,MCGIRCLK" bitfld.long 0x00 18. " USBSRC ,USB clock source select" "USB_CLKIN,IRC48M" bitfld.long 0x00 16.--17. " PLLFLLSEL ,PLL/FLL clock select" "MCGFLLCLK,MCGPLLCLK,,IRC48" newline bitfld.long 0x00 12. " TRACECLKSEL ,Debug trace clock select" "MCGOUTCLK,Core/system clock" bitfld.long 0x00 8.--9. " FBSL ,Flexbus security level. Off-chip accesses via FlexBus or SDRAM instruction/data" "Not allowed/Not allowed,Not allowed/Not allowed,Not allowed/Allowed,Allowed/Allowed" newline bitfld.long 0x00 5.--7. " CLKOUTSEL ,Clock out select" "FlexBus CLKOUT,,Flash clock,LPO clock,MCGIRCLK,RTC clock,OSCERCLK0,IRC48M" newline bitfld.long 0x00 4. " RTCCLKOUTSEL ,RTC clock out select" "1 Hz,32 kHz" else group.long 0x1004++0x03 line.long 0x00 "SOPT2,System Options Register 2" bitfld.long 0x00 28.--29. " SDHCSRC ,SDHC clock source select" "Core/system clock,,OSCERCLK,SDHC0_CLKIN" bitfld.long 0x00 26.--27. " LPUARTSRC ,LPUART clock source select" "Disabled,,OSCERCLK,MCGIRCLK" bitfld.long 0x00 24.--25. " TPMSRC ,TPM clock source select" "Disabled,,OSCERCLK,MCGIRCLK" newline bitfld.long 0x00 22.--23. " FLEXIOSRC ,FlexIO Module Clock Source Select" "System clock,,OSCERCLK,MCGIRCLK" bitfld.long 0x00 18. " USBSRC ,USB clock source select" "USB_CLKIN,?..." bitfld.long 0x00 16.--17. " PLLFLLSEL ,PLL/FLL clock select" "MCGFLLCLK,MCGPLLCLK,,IRC48" newline bitfld.long 0x00 12. " TRACECLKSEL ,Debug trace clock select" "MCGOUTCLK,Core/system clock" bitfld.long 0x00 8.--9. " FBSL ,Flexbus security level. Off-chip accesses via FlexBus or SDRAM instruction/data" "Not allowed/Not allowed,Not allowed/Not allowed,Not allowed/Allowed,Allowed/Allowed" newline bitfld.long 0x00 5.--7. " CLKOUTSEL ,Clock out select" "FlexBus CLKOUT,,Flash clock,LPO clock,MCGIRCLK,RTC clock,OSCERCLK0,IRC48M" newline bitfld.long 0x00 4. " RTCCLKOUTSEL ,RTC clock out select" "1 Hz,32 kHz" endif endif newline group.long 0x100C++0x07 line.long 0x00 "SOPT4,System Options Register 4" bitfld.long 0x00 31. " FTM3TRG1SRC ,FlexTimer 3 Hardware Trigger 1 Source Select" ",FTM2" bitfld.long 0x00 30. " FTM3TRG0SRC ,FlexTimer 3 Hardware Trigger 0 Source Select" ",FTM1" bitfld.long 0x00 29. " FTM0TRG1SRC ,FlexTimer 0 Hardware Trigger 1 Source Select" "PDB,FTM2" newline bitfld.long 0x00 28. " FTM0TRG0SRC ,FlexTimer 0 Hardware Trigger 0 Source Select" "HSCMP0,FTM1" bitfld.long 0x00 27. " FTM3CLKSEL ,FlexTimer 3 external clock pin select" "FTM_CLK0,FTM_CLK1" bitfld.long 0x00 26. " FTM2CLKSEL ,FlexTimer 2 External Clock Pin Select" "FTM_CLK0,FTM_CLK1" newline bitfld.long 0x00 25. " FTM1CLKSEL ,FlexTimer 1 External Clock Pin Select" "FTM_CLK0,FTM_CLK1" bitfld.long 0x00 24. " FTM0CLKSEL ,FlexTimer 0 External Clock Pin Select" "FTM_CLK0,FTM_CLK1" bitfld.long 0x00 22. " FTM2CH1SRC ,FlexTimer 2 channel 1 input capture source select" "FTM_CLK0,FTM_CLK1" newline bitfld.long 0x00 20.--21. " FTM2CH0SRC ,FlexTimer 2 channel 0 input capture source select" "FTM2_CH0,CMP0 output,CMP1 output,?..." bitfld.long 0x00 18.--19. " FTM1CH0SRC ,FlexTimer 1 channel 0 input capture source select" "FTM1_CH0,CMP0 output,CMP1 output,USB start of frame" bitfld.long 0x00 12. " FTM3FLT0 ,Flextimer 3 Fault 0 Select" "FTM3_FLT0,CMP0 output" newline bitfld.long 0x00 8. " FTM2FLT0 ,Flextimer 2 Fault 0 Select" "FTM2_FLT0,CMP0 output" bitfld.long 0x00 4. " FTM1FLT0 ,FlexTimer 1 Fault 0 Select" "FTM1_FLT0,CMP0 output" bitfld.long 0x00 1. " FTM0FLT1 ,FlexTimer 0 Fault 1 Select" "FTM0_FLT1,CMP1 output" newline bitfld.long 0x00 0. " FTM0FLT0 ,FlexTimer 0 Fault 0 Select" "FTM0_FLT0,CMP0 output" line.long 0x04 "SOPT5,System Options Register 5" bitfld.long 0x04 22.--23. " LPUART1RXSRC ,LPUART 1 receive data source select" "LPUART1_RX,CMP0 output,CMP1 output,?..." bitfld.long 0x04 20.--21. " LPUART1TXSRC ,LPUART 1 transmit data source selec" "LPUART1_TX,TPM1 Ch.0 output,TPM2 Ch.0 output,?..." bitfld.long 0x04 18.--19. " LPUART0RXSRC ,LPUART 0 receive data source select" "LPUART0_RX,CMP0 output,CMP1 output,?..." newline bitfld.long 0x04 16.--17. " LPUART0TXSRC ,LPUART 0 transmit data source select" "LPUART0_TX,TPM1 Ch.0 output,TPM2 Ch.0 output,?..." group.long 0x1018++0x0B line.long 0x00 "SOPT7,System Options Register 7" bitfld.long 0x00 7. " ADC0ALTTRGEN ,ADC0 alternate trigger enable" "Disabled,Enabled" bitfld.long 0x00 4. " ADC0PRETRGSEL ,ADC0 pretrigger select" "Pre-trigger A,Pre-trigger B" bitfld.long 0x00 0.--3. " ADC0TRGSEL ,ADC0 trigger select" "PDB0_EXTRG,HS comparator 0 output,HS comparator 1 output,,PIT0,PIT1,PIT2,PIT3,FTM0,FTM1,FTM2,FTM3,RTC alarm,RTC seconds,LPTMR,TPM1 Ch.0 and Ch.1" line.long 0x04 "SOPT8,System Options Register 8" bitfld.long 0x04 31. " FTM3OCH7SRC ,FlexTimer 3 channel 7 output source" "FTM3 Ch.7 output,FTM2 Ch.1 output" bitfld.long 0x04 30. " FTM3OCH6SRC ,FlexTimer 3 channel 6 output source" "FTM3 Ch.6 output,FTM2 Ch.1 output" bitfld.long 0x04 29. " FTM3OCH5SRC ,FlexTimer 3 channel 5 output source" "FTM3 Ch.5 output,FTM2 Ch.1 output" newline bitfld.long 0x04 28. " FTM3OCH4SRC ,FlexTimer 3 channel 4 output source" "FTM3 Ch.4 output,FTM2 Ch.1 output" bitfld.long 0x04 27. " FTM3OCH3SRC ,FlexTimer 3 channel 3 output source" "FTM3 Ch.3 output,FTM2 Ch.1 output" bitfld.long 0x04 26. " FTM3OCH2SRC ,FlexTimer 3 channel 2 output source" "FTM3 Ch.2 output,FTM2 Ch.1 output" newline bitfld.long 0x04 25. " FTM3OCH1SRC ,FlexTimer 3 channel 1 output source" "FTM3 Ch.1 output,FTM2 Ch.1 output" bitfld.long 0x04 24. " FTM3OCH0SRC ,FlexTimer 3 channel 0 output source" "FTM3 Ch.0 output,FTM2 Ch.1 output" newline bitfld.long 0x04 23. " FTM0OCH7SRC ,FlexTimer 0 channel 7 output source" "FTM0 Ch.7 output,FTM1 Ch.1 output" bitfld.long 0x04 22. " FTM0OCH6SRC ,FlexTimer 0 channel 6 output source" "FTM0 Ch.6 output,FTM1 Ch.1 output" bitfld.long 0x04 21. " FTM0OCH5SRC ,FlexTimer 0 channel 5 output source" "FTM0 Ch.5 output,FTM1 Ch.1 output" newline bitfld.long 0x04 20. " FTM0OCH4SRC ,FlexTimer 0 channel 4 output source" "FTM0 Ch.4 output,FTM1 Ch.1 output" bitfld.long 0x04 19. " FTM0OCH3SRC ,FlexTimer 0 channel 3 output source" "FTM0 Ch.3 output,FTM1 Ch.1 output" bitfld.long 0x04 18. " FTM0OCH2SRC ,FlexTimer 0 channel 2 output source" "FTM0 Ch.2 output,FTM1 Ch.1 output" newline bitfld.long 0x04 17. " FTM0OCH1SRC ,FlexTimer 0 channel 1 output source" "FTM0 Ch.1 output,FTM1 Ch.1 output" bitfld.long 0x04 16. " FTM0OCH0SRC ,FlexTimer 0 channel 0 output source" "FTM0 Ch.0 output,FTM1 Ch.1 output" bitfld.long 0x04 3. " FTM3SYNCBIT ,FlexTimer 3 Hardware Trigger 0 Software Synchronization" "No effect,FTM3" newline bitfld.long 0x04 2. " FTM2SYNCBIT ,FlexTimer 2 Hardware Trigger 0 Software Synchronization" "No effect,FTM2" bitfld.long 0x04 1. " FTM1SYNCBIT ,FlexTimer 1 Hardware Trigger 0 Software Synchronization" "No effect,FTM1" bitfld.long 0x04 0. " FTM0SYNCBIT ,FlexTimer 0 Hardware Trigger 0 Software Synchronization" "No effect,FTM0" line.long 0x08 "SOPT9,System Options Register 9" bitfld.long 0x08 26. " TPM2CLKSEL ,TPM2 External Clock Pin Select" "TPM_CLKIN0,TPM_CLKIN1" bitfld.long 0x08 25. " TPM1CLKSEL ,TPM1 External Clock Pin Select" "TPM_CLKIN0,TPM_CLKIN1" bitfld.long 0x08 20.--21. " TPM2CH0SRC ,TPM2 channel 0 input capture source select" "TPM2_CH0,CMP0 output,CMP1 output,?..." newline bitfld.long 0x08 18.--19. " TPM1CH0SRC ,TPM1 channel 0 input capture source select" "TPM1_CH0,CMP0 output,CMP1 output,?..." rgroup.long 0x1024++0x03 line.long 0x00 "SDID,System Device Identification Register" bitfld.long 0x00 28.--31. " FAMILYID ,Kinetis Family ID" "K0x,K1x,K2x,K3x,K4x,,K6x,K7x,K8x,?..." bitfld.long 0x00 24.--27. " SUBFAMID ,Kinetis Sub-Family ID" "Kx0,Kx1 (tamper detected),Kx2,Kx3 (tamper detected),Kx4,Kx5 (tamper detected),Kx6,?..." bitfld.long 0x00 20.--23. " SERIESID ,Kinetis Series ID" "K,L,,,,W,V,?..." newline bitfld.long 0x00 12.--15. " REVID ,Device Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7.--11. " DIEID ,Device Die ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--6. " FAMID ,Kinetis family identification" "K1x (w/o tamper),K2x (w/o tamper),K3x or K1x/K6x (w/ tamper),K4x or K2x (w/ tamper),K6x (w/o tamper),K7x,?..." newline bitfld.long 0x00 0.--3. " PINID ,Pincount identification" ",,32-pin,,48-pin,64-pin,80-pin,81-pin or 121-pin,100-pin,121-pin,144-pin,WLCSP,169-pin,,256-pin,?..." newline group.long 0x1028++0x03 line.long 0x00 "SCGC1,System Clock Gating Control Register 1" bitfld.long 0x00 7. " I2C3 ,I2C3 Clock Enable" "Disabled,Enabled" bitfld.long 0x00 6. " I2C2 ,I2C2 Clock Enable" "Disabled,Enabled" sif cpuis("MK80FN256V*") group.long 0x102C++0x03 line.long 0x00 "SCGC2,System Clock Gating Control Register 2" bitfld.long 0x00 31. " FLEXIO ,FlexIO Clock Enable" "Disabled,Enabled" bitfld.long 0x00 26. " QSPI ,QSPI Clock Enable" "Disabled,Enabled" bitfld.long 0x00 22. " LPUART4 ,LPUART4 Clock Enable" "Disabled,Enabled" bitfld.long 0x00 21. " EMVSIM1 ,EMVSIM1 Clock Gate Control" "Disabled,Enabled" newline bitfld.long 0x00 20. " EMVSIM0 ,EMVSIM0 Clock Gate Control" "Disabled,Enabled" bitfld.long 0x00 12. " DAC0 ,DAC0 Clock Enable" "Disabled,Enabled" bitfld.long 0x00 10. " TPM2 ,TPM2 Clock Enable" "Disabled,Enabled" bitfld.long 0x00 9. " TPM1 ,TPM1 Clock Enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " LPUART3 ,LPUART3 Clock Enable" "Disabled,Enabled" bitfld.long 0x00 6. " LPUART2 ,LPUART2 Clock Enable" "Disabled,Enabled" bitfld.long 0x00 5. " LPUART1 ,LPUART1 Clock Enable" "Disabled,Enabled" bitfld.long 0x00 4. " LPUART0 ,LPUART0 Clock Enable" "Disabled,Enabled" elif cpuis("MK8?FN256V*") group.long 0x102C++0x03 line.long 0x00 "SCGC2,System Clock Gating Control Register 2" bitfld.long 0x00 31. " FLEXIO ,FlexIO Clock Enable" "Disabled,Enabled" bitfld.long 0x00 26. " QSPI ,QSPI Clock Enable" "Disabled,Enabled" bitfld.long 0x00 22. " LPUART4 ,LPUART4 Clock Enable" "Disabled,Enabled" bitfld.long 0x00 21. " EMVSIM1 ,EMVSIM1 Clock Gate Control" "Disabled,Enabled" newline bitfld.long 0x00 20. " EMVSIM0 ,EMVSIM0 Clock Gate Control" "Disabled,Enabled" bitfld.long 0x00 17. " LTC ,LTC Clock Gate Control" "Disabled,Enabled" bitfld.long 0x00 12. " DAC0 ,DAC0 Clock Enable" "Disabled,Enabled" bitfld.long 0x00 10. " TPM2 ,TPM2 Clock Enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " TPM1 ,TPM1 Clock Enable" "Disabled,Enabled" bitfld.long 0x00 7. " LPUART3 ,LPUART3 Clock Enable" "Disabled,Enabled" bitfld.long 0x00 6. " LPUART2 ,LPUART2 Clock Enable" "Disabled,Enabled" bitfld.long 0x00 5. " LPUART1 ,LPUART1 Clock Enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " LPUART0 ,LPUART0 Clock Enable" "Disabled,Enabled" else group.long 0x102C++0x03 line.long 0x00 "SCGC2,System Clock Gating Control Register 2" bitfld.long 0x00 31. " FLEXIO ,FlexIO Clock Enable" "Disabled,Enabled" bitfld.long 0x00 26. " QSPI ,QSPI Clock Enable" "Disabled,Enabled" bitfld.long 0x00 22. " LPUART4 ,LPUART4 Clock Enable" "Disabled,Enabled" bitfld.long 0x00 12. " DAC0 ,DAC0 Clock Enable" "Disabled,Enabled" newline bitfld.long 0x00 10. " TPM2 ,TPM2 Clock Enable" "Disabled,Enabled" bitfld.long 0x00 9. " TPM1 ,TPM1 Clock Enable" "Disabled,Enabled" bitfld.long 0x00 7. " LPUART3 ,LPUART3 Clock Enable" "Disabled,Enabled" bitfld.long 0x00 6. " LPUART2 ,LPUART2 Clock Enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " LPUART1 ,LPUART1 Clock Enable" "Disabled,Enabled" bitfld.long 0x00 4. " LPUART0 ,LPUART0 Clock Enable" "Disabled,Enabled" endif group.long 0x1030++0x1B line.long 0x00 "SCGC3,System Clock Gating Control Register 3" bitfld.long 0x00 25. " FTM3 ,FTM3 Clock Enable" "Disabled,Enabled" bitfld.long 0x00 24. " FTM2 ,FTM2 Clock Enable" "Disabled,Enabled" bitfld.long 0x00 17. " SDHC ,SDHC Clock Enable" "Disabled,Enabled" bitfld.long 0x00 12. " SPI2 ,SPI2 Clock Enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " TRNG ,TRNG Clock Enable" "Disabled,Enabled" line.long 0x04 "SCGC4,System Clock Gating Control Register 4" bitfld.long 0x04 20. " VREF ,VREF Clock Enable" "Disabled,Enabled" bitfld.long 0x04 19. " CMP ,Comparator Clock Enable" "Disabled,Enabled" bitfld.long 0x04 18. " USBOTG ,USB Clock Enable" "Disabled,Enabled" bitfld.long 0x04 7. " I2C1 ,I2C1 Clock Enable" "Disabled,Enabled" newline bitfld.long 0x04 6. " I2C0 ,I2C0 Clock Enable" "Disabled,Enabled" bitfld.long 0x04 2. " CMT ,CMT Clock Enable" "Disabled,Enabled" bitfld.long 0x04 1. " EWM ,EWM Clock Enable" "Disabled,Enabled" line.long 0x08 "SCGC5,System Clock Gating Control Register 5" bitfld.long 0x08 13. " PORTE ,Port E Clock Enable" "Disabled,Enabled" bitfld.long 0x08 12. " PORTD ,Port D Clock Enable" "Disabled,Enabled" bitfld.long 0x08 11. " PORTC ,Port C Clock Enable" "Disabled,Enabled" bitfld.long 0x08 10. " PORTB ,Port B Clock Enable" "Disabled,Enabled" newline bitfld.long 0x08 9. " PORTA ,Port A Clock Enable" "Disabled,Enabled" bitfld.long 0x08 5. " TSI ,TSI Clock Enable" "Disabled,Enabled" bitfld.long 0x08 4. " LPTMR1 ,LPTMR1 Clock Gate Control" "Disabled,Enabled" bitfld.long 0x08 0. " LPTMR ,Low Power Timer Access Enable" "Disabled,Enabled" line.long 0x0C "SCGC6,System Clock Gating Control Register 6" bitfld.long 0x0C 31. " DAC0 ,DAC0 Clock Enable" "Disabled,Enabled" bitfld.long 0x0C 29. " RTC ,RTC Access and interrupts Enable" "Disabled,Enabled" bitfld.long 0x0C 27. " ADC0 ,ADC0 Clock Enable" "Disabled,Enabled" bitfld.long 0x0C 26. " FTM2 ,FTM2 Clock Enable" "Disabled,Enabled" newline bitfld.long 0x0C 25. " FTM1 ,FTM1 Clock Enable" "Disabled,Enabled" bitfld.long 0x0C 24. " FTM0 ,FTM0 Clock Enable" "Disabled,Enabled" bitfld.long 0x0C 23. " PIT ,PIT Clock Enable" "Disabled,Enabled" bitfld.long 0x0C 22. " PDB ,PDB Clock Enable" "Disabled,Enabled" newline bitfld.long 0x0C 21. " USBDCD ,USB DCD Clock Enable" "Disabled,Enabled" bitfld.long 0x0C 18. " CRC ,CRC Clock Enable" "Disabled,Enabled" bitfld.long 0x0C 15. " I2S ,I2S Clock Enable" "Disabled,Enabled" bitfld.long 0x0C 13. " SPI1 ,SPI1 Clock Enable" "Disabled,Enabled" newline bitfld.long 0x0C 12. " SPI0 ,SPI0 Clock Enable" "Disabled,Enabled" bitfld.long 0x0C 1. " DMAMUX ,DMA Mux Clock Enable" "Disabled,Enabled" bitfld.long 0x0C 0. " FTF ,Flash Memory Clock Enable" "Disabled,Enabled" line.long 0x10 "SCGC7,System Clock Gating Control Register 7" bitfld.long 0x10 3. " SDRAMC ,SDRAMC Clock Enable" "Disabled,Enabled" bitfld.long 0x10 2. " MPU ,MPU Clock Enable" "Disabled,Enabled" bitfld.long 0x10 1. " DMA ,DMA Clock Enable" "Disabled,Enabled" bitfld.long 0x10 0. " FLEXBUS ,FlexBus Clock Enable" "Disabled,Enabled" line.long 0x14 "CLKDIV1,System Clock Divider Register 1" bitfld.long 0x14 28.--31. " OUTDIV1 ,Clock 1 output Divider value" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x14 24.--27. " OUTDIV2 ,Clock 2 output Divider value" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x14 20.--23. " OUTDIV3 ,Clock 3 output Divider value" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x14 16.--19. " OUTDIV4 ,Clock 4 output divider value" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" line.long 0x18 "CLKDIV2,System Clock Divider Register 2" bitfld.long 0x18 1.--3. " USBDIV ,USB clock divider divisor" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0. " USBFRAC ,USB clock divider fraction" "0,1" sif cpuis("MK8?FN256V*") group.long 0x104C++0x03 line.long 0x00 "FCFG1,Flash Configuration Register 1" rbitfld.long 0x00 24.--27. " PFSIZE ,Program flash size" ",,,32 KB,,64 KB,,128 KB,,256 KB,,512 KB,,1024 KB,,256 KB" bitfld.long 0x00 1. " FLASHDOZE ,Disable Flash memory for the duration of Wait mode" "No,Yes" bitfld.long 0x00 0. " FLASHDIS ,Disable Flash" "No,Yes" rgroup.long 0x1050++0x03 line.long 0x00 "FCFG2,Flash Configuration Register 2" hexmask.long.byte 0x00 24.--29. 0x01 " MAXADDR0 ,Max address block 0" hexmask.long.byte 0x00 16.--22. 0x01 " MAXADDR1 ,Max address block 1" else group.long 0x104C++0x03 line.long 0x00 "FCFG1,Flash Configuration Register 1" rbitfld.long 0x00 28.--31. " NVMSIZE ,FlexNVM memory size" "0 KB,,,32 KB,,64 KB,,128 KB,,256 KB,,512 KB,?..." rbitfld.long 0x00 24.--27. " PFSIZE ,Program flash size" ",,,32 KB,,64 KB,,128 KB,,256 KB,,512 KB,,1024 KB,,2048 KB" rbitfld.long 0x00 16.--19. " EESIZE ,EEPROM size" "16 KB,8 KB,4 KB,2 KB,1 KB,512 B,256 B,128 B,64 B,32 B,,,,,,0 bytes" bitfld.long 0x00 1. " FLASHDOZE ,Disable Flash memory for the duration of Wait mode" "No,Yes" newline bitfld.long 0x00 0. " FLASHDIS ,Disable Flash" "No,Yes" rgroup.long 0x1050++0x03 line.long 0x00 "FCFG2,Flash Configuration Register 2" bitfld.long 0x00 31. " SWAPPFLSH ,Swap program flash" "Not swapped,Swapped" hexmask.long.byte 0x00 24.--29. 0x01 " MAXADDR0 ,Max address block 0" bitfld.long 0x00 23. " PFLSH ,Device supports FlexNVM/Program Flash only" "FlexNVM,Program Flash" hexmask.long.byte 0x00 16.--22. 0x01 " MAXADDR1 ,Max address block 1" endif rgroup.long 0x1054++0x0F line.long 0x00 "UIDH,Unique Identification Register High" line.long 0x04 "UIDMH,Unique Identification Register Mid-High" line.long 0x08 "UIDML,Unique Identification Register Mid Low" line.long 0x0C "UIDL,Unique Identification Register Low" group.long 0x1064++0x07 line.long 0x00 "CLKDIV3,System Clock Divider Register 3" bitfld.long 0x00 1.--3. " PLLFLLDIV ,PLLFLL clock divider divisor" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " PLLFLLFRAC ,PLLFLL clock divider fraction" "0,1" line.long 0x04 "CLKDIV4,System Clock Divider Register 4" bitfld.long 0x04 1.--3. " TRACEDIV ,Trace clock divider divisor" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0. " TRACEFRAC ,Trace clock divider fraction" "0,1" width 0x0B tree.end tree "EMVSIM (Euro/Mastercard/Visa/SIM Serial Interface Module)" base ad:0x400D4000 width 12. tree "EMVSIM0" rgroup.long (0x0+0x00)++0x07 line.long 0x00 "VER_ID,Version ID Register" line.long 0x04 "PARAM,Parameter Register" hexmask.long.byte 0x04 8.--15. 1. " TX_FIFO_DEPTH ,Transmit FIFO Depth" hexmask.long.byte 0x04 0.--7. 1. " RX_FIFO_DEPTH ,Receive FIFO Depth" group.long (0x0+0x08)++0x23 line.long 0x00 "CLKCFG,Clock Configuration Register" bitfld.long 0x00 10.--11. " GPCNT0_CLK_SEL ,General Purpose Counter 0 Clock Select" "Disabled/Reset,Card Clock,Receive Clock,ETU Clock" bitfld.long 0x00 8.--9. " GPCNT1_CLK_SEL ,General Purpose Counter 1 Clock Select" "Disabled/Reset,Card Clock,Receive Clock,ETU Clock" hexmask.long.byte 0x00 0.--7. 1. " CLK_PRSC ,Clock Prescaler Value" line.long 0x04 "DIVISOR,Baud Rate Divisor Register" hexmask.long.word 0x04 0.--8. 1. " DIVISOR_VALUE ,Divisor (F/D) Value" line.long 0x08 "CTRL,Control Register" bitfld.long 0x08 31. " BWT_EN ,Block Wait Time Counter Enable" "Disabled,Enabled" bitfld.long 0x08 30. " XMT_CRC_LRC ,Transmit CRC or LRC Enable" "Disabled,Enabled" bitfld.long 0x08 29. " CRC_EN ,CRC Enable" "Disabled,Enabled" newline bitfld.long 0x08 28. " LRC_EN ,LRC Enable" "Disabled,Enabled" bitfld.long 0x08 27. " CWT_EN ,Character Wait Time Counter Enable" "Disabled,Enabled" bitfld.long 0x08 26. " CRC_IN_FLIP ,CRC Input Byte's Bit Reversal or Flip Control" "Not Reversed,Reversed" newline bitfld.long 0x08 25. " CRC_OUT_FLIP ,CRC Output Value Bit Reversal or Flip" "Not Reversed,Reversed" bitfld.long 0x08 24. " INV_CRC_VAL ,Invert bits in the CRC Output Value" "Not Inverted,Inverted" bitfld.long 0x08 20. " TX_DMA_EN ,Transmit DMA Enable" "No Request,Request" newline bitfld.long 0x08 19. " RX_DMA_EN ,Receive DMA Enable" "No Request,Request" bitfld.long 0x08 18. " RCVR_11 ,Receiver 11 ETU Mode Enable" "12 ETU,11 ETU" bitfld.long 0x08 17. " XMT_EN ,Transmitter Enable" "Disabled,Enabled" newline bitfld.long 0x08 16. " RCV_EN ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x08 13. " STOP_EN ,STOP Enable" "Stoped all EMV SIM clocks,Stoped all clocks except for the SCK" bitfld.long 0x08 12. " DOZE_EN ,Doze Enable" "All internal EMV SIM,No effect" newline bitfld.long 0x08 11. " KILL_CLOCKS ,Kill all internal clocks" "Enabled,Disabled" bitfld.long 0x08 10. " SW_RST ,Software Reset Bit" "Normal,Reset" bitfld.long 0x08 9. " FLSH_TX ,Flush Transmitter Bit" "Normal,Reset" newline bitfld.long 0x08 8. " FLSH_RX ,Flush Receiver Bit" "Normal,Reset" bitfld.long 0x08 3. " ONACK ,Overrun NACK Enable" "Disabled,Enabled" bitfld.long 0x08 2. " ANACK ,Auto NACK Enable" "Disabled,Enabled" newline bitfld.long 0x08 1. " ICM ,Initial Character Mode" "Disabled,Enabled" bitfld.long 0x08 0. " IC ,Inverse Convention" "Direction,Inverse" line.long 0x0C "INT_MASK,Interrupt Mask Register" bitfld.long 0x0C 15. " PEF_IM ,Parity Error Interrupt Mask" "Not masked,Masked" bitfld.long 0x0C 14. " RX_DATA_IM ,Receive Data Interrupt Mask" "Not masked,Masked" bitfld.long 0x0C 13. " GPCNT1_IM ,General Purpose Counter 1 Timeout Interrupt Mask" "Not masked,Masked" newline bitfld.long 0x0C 12. " BGT_ERR_IM ,Block Guard Time Error Interrupt" "Not masked,Masked" bitfld.long 0x0C 11. " BWT_ERR_IM ,Block Wait Time Error Interrupt Mask" "Not masked,Masked" bitfld.long 0x0C 10. " RNACK_IM ,Receiver NACK Threshold Interrupt Mask" "Not masked,Masked" newline bitfld.long 0x0C 9. " CWT_ERR_IM ,Character Wait Time Error Interrupt Mask" "Not masked,Masked" bitfld.long 0x0C 8. " GPCNT0_IM ,General Purpose Timer 0 Timeout Interrupt Mask" "Not masked,Masked" bitfld.long 0x0C 7. " TDT_IM ,Transmit Data Threshold Interrupt Mask" "Not masked,Masked" newline bitfld.long 0x0C 6. " TFF_IM ,Transmit FIFO Full Interrupt Mask" "Not masked,Masked" bitfld.long 0x0C 5. " TNACK_IM ,Transmit NACK Threshold Interrupt Mask" "Not masked,Masked" bitfld.long 0x0C 4. " TFE_IM ,Transmit FIFO Empty Interrupt Mask" "Not masked,Masked" newline bitfld.long 0x0C 3. " ETC_IM ,Early Transmit Complete Interrupt Mask" "Not masked,Masked" bitfld.long 0x0C 2. " RFO_IM ,Receive FIFO Overflow Interrupt Mask" "Not masked,Masked" bitfld.long 0x0C 1. " TC_IM ,Transmit Complete Interrupt Mask" "Not masked,Masked" newline bitfld.long 0x0C 0. " RDT_IM ,Receive Data Threshold Interrupt Mask" "Not masked,Masked" line.long 0x10 "RX_THD,Receiver Threshold Register" bitfld.long 0x10 8.--11. " RNCK_THD ,Receiver NACK Threshold Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 0.--3. " RDT ,Receiver Data Threshold Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x14 "TX_THD,Transmitter Threshold Register" bitfld.long 0x14 8.--11. " TNCK_THD ,Transmitter NACK Threshold Value" "TNTE will never be set,After 1 nack,After 2 nacks,After 3 nacks,After 4 nacks,After 5 nacks,After 6 nacks,After 7 nacks,After 8 nacks,After 9 nack,After 10 nacks,After 11 nacks,After 12 nacks,After 13 nacks,After 14 nacks,After 15 nacks" bitfld.long 0x14 0.--3. " TDT ,Transmitter Data Threshold Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x18 "RX_STATUS,Receive Status Register" rbitfld.long 0x18 24.--28. " RX_CNT ,Receive FIFO Byte Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x18 16.--19. " RX_WPTR ,Receive FIFO Write Pointer Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" eventfld.long 0x18 13. " FEF ,Frame Error Flag" "No error,Error" newline eventfld.long 0x18 12. " PEF ,Parity Error Flag" "No error,Error" eventfld.long 0x18 11. " BGT_ERR ,Block Guard Time Error Flag" "Sufficient,Too Small" eventfld.long 0x18 10. " BWT_ERR ,Block Wait Time Error Flag" "Not Exceeded,Exeeded" newline eventfld.long 0x18 9. " RTE ,Received NACK Threshold Error Flag" "Less then programmed value,Equal to programmed value" eventfld.long 0x18 8. " CWT_ERR ,Character Wait Time Error Flag" "No Occurred,Occurred" rbitfld.long 0x18 7. " CRC_OK ,CRC Check OK Flag" "Not Match,Match" newline rbitfld.long 0x18 6. " LRC_OK ,LRC Check OK Flag" "Not Match,Match" rbitfld.long 0x18 5. " RDTF ,Receive Data Threshold Interrupt Flag" "Less then value set by RDT,Greater or than equal to value set by RDT" eventfld.long 0x18 4. " RX_DATA ,Receive Data Interrupt Flag" "No received,Received" newline eventfld.long 0x18 0. " RFO ,Receive FIFO Overflow Flag" "No occurred,Occurred" line.long 0x1C "TX_STATUS,Transmitter Status Register" rbitfld.long 0x1C 24.--28. " TX_CNT ,Transmit FIFO Byte Count" "Empty,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x1C 16.--19. " TX_RPTR ,Transmit FIFO Read Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" eventfld.long 0x1C 9. " GPCNT1_TO ,General Purpose Counter 1 Timeout Flag" "Not reached,Reached" newline eventfld.long 0x1C 8. " GPCNT0_TO ,General Purpose Counter 0 Timeout Flag" "Not reached,Reached" rbitfld.long 0x1C 7. " TDTF ,Transmit Data Threshold Flag" "Greater,Less or Equal" eventfld.long 0x1C 6. " TFF ,Transmit FIFO Full Flag" "Not Occurred,Occurred" newline eventfld.long 0x1C 5. " TCF ,Transmit Complete Flag" "In Progress,Completed" eventfld.long 0x1C 4. " ETCF ,Early Transmit Complete Flag" "In Progress,Completed" eventfld.long 0x1C 3. " TFE ,Transmit FIFO Empty Flag" "Not Empty,Empty" newline eventfld.long 0x1C 0. " TNTE ,Transmit NACK Threshold Error Flag" "Not Reached,Reached" line.long 0x20 "PCSR,Port Control and Status Register" bitfld.long 0x20 27. " SPDES ,SIM Presence Detect Edge Select" "Falling Edge,Rising Edge" rbitfld.long 0x20 26. " SPDP ,Smart Card Presence Detect Pin Status" "Low,High" eventfld.long 0x20 25. " SPDIF ,Smart Card Presence Detect Interrupt Flag" "No insertion or removal,Insertion or removal" newline bitfld.long 0x20 24. " SPDIM ,Smart Card Presence Detect Interrupt Mask" "Enabled,Masked" bitfld.long 0x20 7. " SPD ,Auto Power Down Control" "No effect,Started" bitfld.long 0x20 5. " SCSP ,Smart Card Clock Stop Polarity" "Logic 0,Logic 1" newline bitfld.long 0x20 4. " SCEN ,Clock Enable for Smart Card" "Disabled,Enabled" bitfld.long 0x20 3. " SRST ,Reset to Smart Card" "Asserted,De-asserted" bitfld.long 0x20 2. " VCCENP ,VCC Enable Polarity Control" "Unchanged,Inverted" newline bitfld.long 0x20 1. " SVCC_EN ,Vcc Enable for Smart Card" "Disabled,Enabled" bitfld.long 0x20 0. " SAPD ,Auto Power Down Enable" "Disabled,Enabled" hgroup.long (0x0+0x2C)++0x03 hide.long 0x00 "RX_BUF,Receive Data Read Buffer" in wgroup.long (0x0+0x30)++0x03 line.long 0x00 "TX_BUF,Transmit Data Buffer" hexmask.long.byte 0x00 0.--7. 1. " TX_BYTE ,Transmit Data Byte" group.long (0x0+0x34)++0x17 line.long 0x00 "TX_GETU,Transmitter Guard ETU Value Register" hexmask.long.byte 0x00 0.--7. 1. " GETU ,Transmitter Guard Time Value in ETU" line.long 0x04 "CWT_VAL,Character Wait Time Value Register" hexmask.long.word 0x04 0.--15. 1. " CWT ,Character Wait Time Value" line.long 0x08 "BWT_VAL,Block Wait Time Value Register" line.long 0x0C "BGT_VAL,Block Guard Time Value Register" hexmask.long.word 0x0C 0.--15. 1. " BGT ,Block Guard Time Value" line.long 0x10 "GPCNT0_VAL,General Purpose Counter 0 Timeout Value Register" hexmask.long.word 0x10 0.--15. 1. " GPCNT0 ,General Purpose Counter 0 Timeout Value" line.long 0x14 "GPCNT1_VAL,General Purpose Counter 1 Timeout Value" hexmask.long.word 0x14 0.--15. 1. " GPCNT1 ,General Purpose Counter 1 Timeout Value" tree.end tree "EMVSIM1" rgroup.long (0x1000+0x00)++0x07 line.long 0x00 "VER_ID,Version ID Register" line.long 0x04 "PARAM,Parameter Register" hexmask.long.byte 0x04 8.--15. 1. " TX_FIFO_DEPTH ,Transmit FIFO Depth" hexmask.long.byte 0x04 0.--7. 1. " RX_FIFO_DEPTH ,Receive FIFO Depth" group.long (0x1000+0x08)++0x23 line.long 0x00 "CLKCFG,Clock Configuration Register" bitfld.long 0x00 10.--11. " GPCNT0_CLK_SEL ,General Purpose Counter 0 Clock Select" "Disabled/Reset,Card Clock,Receive Clock,ETU Clock" bitfld.long 0x00 8.--9. " GPCNT1_CLK_SEL ,General Purpose Counter 1 Clock Select" "Disabled/Reset,Card Clock,Receive Clock,ETU Clock" hexmask.long.byte 0x00 0.--7. 1. " CLK_PRSC ,Clock Prescaler Value" line.long 0x04 "DIVISOR,Baud Rate Divisor Register" hexmask.long.word 0x04 0.--8. 1. " DIVISOR_VALUE ,Divisor (F/D) Value" line.long 0x08 "CTRL,Control Register" bitfld.long 0x08 31. " BWT_EN ,Block Wait Time Counter Enable" "Disabled,Enabled" bitfld.long 0x08 30. " XMT_CRC_LRC ,Transmit CRC or LRC Enable" "Disabled,Enabled" bitfld.long 0x08 29. " CRC_EN ,CRC Enable" "Disabled,Enabled" newline bitfld.long 0x08 28. " LRC_EN ,LRC Enable" "Disabled,Enabled" bitfld.long 0x08 27. " CWT_EN ,Character Wait Time Counter Enable" "Disabled,Enabled" bitfld.long 0x08 26. " CRC_IN_FLIP ,CRC Input Byte's Bit Reversal or Flip Control" "Not Reversed,Reversed" newline bitfld.long 0x08 25. " CRC_OUT_FLIP ,CRC Output Value Bit Reversal or Flip" "Not Reversed,Reversed" bitfld.long 0x08 24. " INV_CRC_VAL ,Invert bits in the CRC Output Value" "Not Inverted,Inverted" bitfld.long 0x08 20. " TX_DMA_EN ,Transmit DMA Enable" "No Request,Request" newline bitfld.long 0x08 19. " RX_DMA_EN ,Receive DMA Enable" "No Request,Request" bitfld.long 0x08 18. " RCVR_11 ,Receiver 11 ETU Mode Enable" "12 ETU,11 ETU" bitfld.long 0x08 17. " XMT_EN ,Transmitter Enable" "Disabled,Enabled" newline bitfld.long 0x08 16. " RCV_EN ,Receiver Enable" "Disabled,Enabled" bitfld.long 0x08 13. " STOP_EN ,STOP Enable" "Stoped all EMV SIM clocks,Stoped all clocks except for the SCK" bitfld.long 0x08 12. " DOZE_EN ,Doze Enable" "All internal EMV SIM,No effect" newline bitfld.long 0x08 11. " KILL_CLOCKS ,Kill all internal clocks" "Enabled,Disabled" bitfld.long 0x08 10. " SW_RST ,Software Reset Bit" "Normal,Reset" bitfld.long 0x08 9. " FLSH_TX ,Flush Transmitter Bit" "Normal,Reset" newline bitfld.long 0x08 8. " FLSH_RX ,Flush Receiver Bit" "Normal,Reset" bitfld.long 0x08 3. " ONACK ,Overrun NACK Enable" "Disabled,Enabled" bitfld.long 0x08 2. " ANACK ,Auto NACK Enable" "Disabled,Enabled" newline bitfld.long 0x08 1. " ICM ,Initial Character Mode" "Disabled,Enabled" bitfld.long 0x08 0. " IC ,Inverse Convention" "Direction,Inverse" line.long 0x0C "INT_MASK,Interrupt Mask Register" bitfld.long 0x0C 15. " PEF_IM ,Parity Error Interrupt Mask" "Not masked,Masked" bitfld.long 0x0C 14. " RX_DATA_IM ,Receive Data Interrupt Mask" "Not masked,Masked" bitfld.long 0x0C 13. " GPCNT1_IM ,General Purpose Counter 1 Timeout Interrupt Mask" "Not masked,Masked" newline bitfld.long 0x0C 12. " BGT_ERR_IM ,Block Guard Time Error Interrupt" "Not masked,Masked" bitfld.long 0x0C 11. " BWT_ERR_IM ,Block Wait Time Error Interrupt Mask" "Not masked,Masked" bitfld.long 0x0C 10. " RNACK_IM ,Receiver NACK Threshold Interrupt Mask" "Not masked,Masked" newline bitfld.long 0x0C 9. " CWT_ERR_IM ,Character Wait Time Error Interrupt Mask" "Not masked,Masked" bitfld.long 0x0C 8. " GPCNT0_IM ,General Purpose Timer 0 Timeout Interrupt Mask" "Not masked,Masked" bitfld.long 0x0C 7. " TDT_IM ,Transmit Data Threshold Interrupt Mask" "Not masked,Masked" newline bitfld.long 0x0C 6. " TFF_IM ,Transmit FIFO Full Interrupt Mask" "Not masked,Masked" bitfld.long 0x0C 5. " TNACK_IM ,Transmit NACK Threshold Interrupt Mask" "Not masked,Masked" bitfld.long 0x0C 4. " TFE_IM ,Transmit FIFO Empty Interrupt Mask" "Not masked,Masked" newline bitfld.long 0x0C 3. " ETC_IM ,Early Transmit Complete Interrupt Mask" "Not masked,Masked" bitfld.long 0x0C 2. " RFO_IM ,Receive FIFO Overflow Interrupt Mask" "Not masked,Masked" bitfld.long 0x0C 1. " TC_IM ,Transmit Complete Interrupt Mask" "Not masked,Masked" newline bitfld.long 0x0C 0. " RDT_IM ,Receive Data Threshold Interrupt Mask" "Not masked,Masked" line.long 0x10 "RX_THD,Receiver Threshold Register" bitfld.long 0x10 8.--11. " RNCK_THD ,Receiver NACK Threshold Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 0.--3. " RDT ,Receiver Data Threshold Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x14 "TX_THD,Transmitter Threshold Register" bitfld.long 0x14 8.--11. " TNCK_THD ,Transmitter NACK Threshold Value" "TNTE will never be set,After 1 nack,After 2 nacks,After 3 nacks,After 4 nacks,After 5 nacks,After 6 nacks,After 7 nacks,After 8 nacks,After 9 nack,After 10 nacks,After 11 nacks,After 12 nacks,After 13 nacks,After 14 nacks,After 15 nacks" bitfld.long 0x14 0.--3. " TDT ,Transmitter Data Threshold Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x18 "RX_STATUS,Receive Status Register" rbitfld.long 0x18 24.--28. " RX_CNT ,Receive FIFO Byte Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x18 16.--19. " RX_WPTR ,Receive FIFO Write Pointer Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" eventfld.long 0x18 13. " FEF ,Frame Error Flag" "No error,Error" newline eventfld.long 0x18 12. " PEF ,Parity Error Flag" "No error,Error" eventfld.long 0x18 11. " BGT_ERR ,Block Guard Time Error Flag" "Sufficient,Too Small" eventfld.long 0x18 10. " BWT_ERR ,Block Wait Time Error Flag" "Not Exceeded,Exeeded" newline eventfld.long 0x18 9. " RTE ,Received NACK Threshold Error Flag" "Less then programmed value,Equal to programmed value" eventfld.long 0x18 8. " CWT_ERR ,Character Wait Time Error Flag" "No Occurred,Occurred" rbitfld.long 0x18 7. " CRC_OK ,CRC Check OK Flag" "Not Match,Match" newline rbitfld.long 0x18 6. " LRC_OK ,LRC Check OK Flag" "Not Match,Match" rbitfld.long 0x18 5. " RDTF ,Receive Data Threshold Interrupt Flag" "Less then value set by RDT,Greater or than equal to value set by RDT" eventfld.long 0x18 4. " RX_DATA ,Receive Data Interrupt Flag" "No received,Received" newline eventfld.long 0x18 0. " RFO ,Receive FIFO Overflow Flag" "No occurred,Occurred" line.long 0x1C "TX_STATUS,Transmitter Status Register" rbitfld.long 0x1C 24.--28. " TX_CNT ,Transmit FIFO Byte Count" "Empty,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x1C 16.--19. " TX_RPTR ,Transmit FIFO Read Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" eventfld.long 0x1C 9. " GPCNT1_TO ,General Purpose Counter 1 Timeout Flag" "Not reached,Reached" newline eventfld.long 0x1C 8. " GPCNT0_TO ,General Purpose Counter 0 Timeout Flag" "Not reached,Reached" rbitfld.long 0x1C 7. " TDTF ,Transmit Data Threshold Flag" "Greater,Less or Equal" eventfld.long 0x1C 6. " TFF ,Transmit FIFO Full Flag" "Not Occurred,Occurred" newline eventfld.long 0x1C 5. " TCF ,Transmit Complete Flag" "In Progress,Completed" eventfld.long 0x1C 4. " ETCF ,Early Transmit Complete Flag" "In Progress,Completed" eventfld.long 0x1C 3. " TFE ,Transmit FIFO Empty Flag" "Not Empty,Empty" newline eventfld.long 0x1C 0. " TNTE ,Transmit NACK Threshold Error Flag" "Not Reached,Reached" line.long 0x20 "PCSR,Port Control and Status Register" bitfld.long 0x20 27. " SPDES ,SIM Presence Detect Edge Select" "Falling Edge,Rising Edge" rbitfld.long 0x20 26. " SPDP ,Smart Card Presence Detect Pin Status" "Low,High" eventfld.long 0x20 25. " SPDIF ,Smart Card Presence Detect Interrupt Flag" "No insertion or removal,Insertion or removal" newline bitfld.long 0x20 24. " SPDIM ,Smart Card Presence Detect Interrupt Mask" "Enabled,Masked" bitfld.long 0x20 7. " SPD ,Auto Power Down Control" "No effect,Started" bitfld.long 0x20 5. " SCSP ,Smart Card Clock Stop Polarity" "Logic 0,Logic 1" newline bitfld.long 0x20 4. " SCEN ,Clock Enable for Smart Card" "Disabled,Enabled" bitfld.long 0x20 3. " SRST ,Reset to Smart Card" "Asserted,De-asserted" bitfld.long 0x20 2. " VCCENP ,VCC Enable Polarity Control" "Unchanged,Inverted" newline bitfld.long 0x20 1. " SVCC_EN ,Vcc Enable for Smart Card" "Disabled,Enabled" bitfld.long 0x20 0. " SAPD ,Auto Power Down Enable" "Disabled,Enabled" hgroup.long (0x1000+0x2C)++0x03 hide.long 0x00 "RX_BUF,Receive Data Read Buffer" in wgroup.long (0x1000+0x30)++0x03 line.long 0x00 "TX_BUF,Transmit Data Buffer" hexmask.long.byte 0x00 0.--7. 1. " TX_BYTE ,Transmit Data Byte" group.long (0x1000+0x34)++0x17 line.long 0x00 "TX_GETU,Transmitter Guard ETU Value Register" hexmask.long.byte 0x00 0.--7. 1. " GETU ,Transmitter Guard Time Value in ETU" line.long 0x04 "CWT_VAL,Character Wait Time Value Register" hexmask.long.word 0x04 0.--15. 1. " CWT ,Character Wait Time Value" line.long 0x08 "BWT_VAL,Block Wait Time Value Register" line.long 0x0C "BGT_VAL,Block Guard Time Value Register" hexmask.long.word 0x0C 0.--15. 1. " BGT ,Block Guard Time Value" line.long 0x10 "GPCNT0_VAL,General Purpose Counter 0 Timeout Value Register" hexmask.long.word 0x10 0.--15. 1. " GPCNT0 ,General Purpose Counter 0 Timeout Value" line.long 0x14 "GPCNT1_VAL,General Purpose Counter 1 Timeout Value" hexmask.long.word 0x14 0.--15. 1. " GPCNT1 ,General Purpose Counter 1 Timeout Value" tree.end width 0x0B tree.end tree "RCM (Reset Control Module)" base ad:0x4007F000 width 7. rgroup.byte 0x00++0x01 line.byte 0x00 "SRS0,System Reset Status Register 0" bitfld.byte 0x00 7. " POR ,Power-on reset" "Not caused,Caused" bitfld.byte 0x00 6. " PIN ,External reset pin" "Not caused,Caused" bitfld.byte 0x00 5. " WDOG ,Watchdog" "Not caused,Caused" sif cpuis("MK02*")||cpuis("MK22FN128*")||cpuis("MK60F*") newline bitfld.byte 0x00 2. " LOC ,Loss-of-clock reset" "Not caused,Caused" bitfld.byte 0x00 1. " LVD ,Low-voltage detect reset" "Not caused,Caused" bitfld.byte 0x00 0. " WAKEUP ,Low-leakage wakeup reset" "Not caused,Caused" else newline bitfld.byte 0x00 3. " LOL ,Loss-of-lock reset" "Not caused,Caused" bitfld.byte 0x00 2. " LOC ,Loss-of-clock reset" "Not caused,Caused" bitfld.byte 0x00 1. " LVD ,Low-voltage detect reset" "Not caused,Caused" newline bitfld.byte 0x00 0. " WAKEUP ,Low-leakage wakeup reset" "Not caused,Caused" endif line.byte 0x01 "SRS1,System Reset Status Register 1" sif !cpuis("MK26FN*")&&!cpuis("MK24FN*")&&!cpuis("MK22F*")&&!cpuis("MK22D*")&&!cpuis("MK20*")&&!cpuis("MK10F*")&&!cpuis("MK10D*")&&!cpuis("MK12D*")&&!cpuis("MK30D*")&&!cpuis("MK40D*")&&!cpuis("MK5?D*")&&!cpuis("MK60*")&&!cpuis("MK64F*")&&!cpuis("MK65F*")&&!cpuis("MK66F*")&&!cpuis("MK02*")&&(!cpuis("MK84FN2M0CAU15R"))&&!cpuis("MK8?FN256V*")&&!cpuis("KK22FN256CAP12R")&&!cpuis("KK22FN512CBP12R")&&!cpuis("KK22FN128CAH12R")&&!cpuis("KK22FN256CAH12R")&&!cpuis("KK26FN2M0CAC18R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MKS2?FN???V??12")&&!cpuis("KK60FN1M0VLQ15")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("KK65FN2M0CAC18R") bitfld.byte 0x01 7. " TAMPER ,Tamper detect" "Not caused,Caused" newline endif sif cpuis("MK02*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12") bitfld.byte 0x01 5. " SACKERR ,Stop mode acknowledge error reset" "Not caused,Caused" bitfld.byte 0x01 3. " MDM_AP ,MDM-AP system reset request" "Not caused,Caused" bitfld.byte 0x01 2. " SW ,Software reset" "Not caused,Caused" newline bitfld.byte 0x01 1. " LOCKUP ,Core lockup" "Not caused,Caused" bitfld.byte 0x01 0. " JTAG ,JTAG generated reset" "Not caused,Caused" else bitfld.byte 0x01 5. " SACKERR ,Stop mode acknowledge error reset" "Not caused,Caused" bitfld.byte 0x01 4. " EZPT ,EzPort reset" "Not caused,Caused" bitfld.byte 0x01 3. " MDM_AP ,MDM-AP system reset request" "Not caused,Caused" newline bitfld.byte 0x01 2. " SW ,Software reset" "Not caused,Caused" bitfld.byte 0x01 1. " LOCKUP ,Core lockup" "Not caused,Caused" bitfld.byte 0x01 0. " JTAG ,JTAG generated reset" "Not caused,Caused" endif group.byte 0x04++0x01 line.byte 0x00 "RPFC,Reset Pin Filter Control Register" bitfld.byte 0x00 2. " RSTFLTSS ,Reset pin filter select in stop mode" "All filtering disabled,LPO clock filter enabled" newline bitfld.byte 0x00 0.--1. " RSTFLTSRW ,Reset pin filter select in run and wait modes" "All filtering disabled,Bus clock filter enabled,LPO clock filter enabled,?..." line.byte 0x01 "RPFW,Reset Pin Filter Width Register" bitfld.byte 0x01 0.--4. " RSTFLTSEL ,Selects the reset pin bus clock filter width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") group.byte 0x06++0x00 line.byte 0x00 "FM,Force Mode Register" bitfld.byte 0x00 1.--2. " FORCEROM ,Force ROM Boot" "No effect,Force w/ RCM_MR[1] set,Force w/ RCM_MR[2] set,Force w/ RCM_MR[2:1] set" endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") group.byte 0x07++0x00 line.byte 0x00 "MR,Mode Register" bitfld.byte 0x00 1.--2. " BOOTROM ,Boot ROM Configuration" "Flash,BOOTCFG0,FOPT[7],BOOTCFG0 and FOPT[7]" elif !cpuis("MK02*")&&!cpuis("MKS2?FN???V??12") rgroup.byte 0x07++0x00 line.byte 0x00 "MR,Mode Register" bitfld.byte 0x00 1. " EZP_MS ,EZP_MS_B pin state" "Deasserted,Asserted" endif newline sif cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK02*")||cpuis("MK26FN*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R") group.byte 0x08++0x01 line.byte 0x00 "SSRS0,Sticky System Reset Status Register 0" eventfld.byte 0x00 7. " SPOR ,Sticky power-on reset" "Not caused,Caused" eventfld.byte 0x00 6. " SPIN ,Sticky external reset pin" "Not caused,Caused" eventfld.byte 0x00 5. " SWDOG ,Sticky watchdog" "Not caused,Caused" sif cpuis("MK02*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN128VLH10R") newline eventfld.byte 0x00 2. " SLOC ,Sticky loss-of-clock reset" "Not caused,Caused" eventfld.byte 0x00 1. " SLVD ,Sticky low-voltage detect reset" "Not caused,Caused" eventfld.byte 0x00 0. " SWAKEUP ,Sticky low leakage wakeup reset" "Not caused,Caused" else newline eventfld.byte 0x00 3. " SLOL ,Sticky loss-of-lock reset" "Not caused,Caused" eventfld.byte 0x00 2. " SLOC ,Sticky loss-of-clock reset" "Not caused,Caused" eventfld.byte 0x00 1. " SLVD ,Sticky low-voltage detect reset" "Not caused,Caused" newline eventfld.byte 0x00 0. " SWAKEUP ,Sticky low leakage wakeup reset" "Not caused,Caused" endif line.byte 0x01 "SSRS1,Sticky System Reset Status Register 1" eventfld.byte 0x01 5. " SSACKERR ,Sticky stop mode acknowledge error reset" "Not caused,Caused" sif !cpuis("MK02*")&&!cpuis("MK84FN2M0CAU15R")&&!cpuis("MK8?FN256V*")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MKS2?FN???V??12") eventfld.byte 0x01 4. " SEZPT ,Sticky EzPort reset" "Not caused,Caused" endif eventfld.byte 0x01 3. " SMDM_AP ,Sticky MDM-AP system reset request" "Not caused,Caused" eventfld.byte 0x01 2. " SSW ,Sticky software" "Not caused,Caused" newline eventfld.byte 0x01 1. " SLOCKUP ,Sticky core lockup" "Not caused,Caused" eventfld.byte 0x01 0. " SJTAG ,Sticky JTAG generated reset" "Not caused,Caused" endif width 0x0B tree.end tree "SMC (System Mode Controller)" base ad:0x4007E000 sif (cpuis("MK60D*AB10")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK40*Z*10")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("KK60DN512ZCAB10R")) width 8. rgroup.byte 0x00++0x01 line.byte 0x00 "SRSH,System Reset Status Register High" bitfld.byte 0x00 2. " SW ,Software reset" "Not caused,Caused" bitfld.byte 0x00 1. " LOCKUP ,Core-lockup reset" "Not caused,Caused" bitfld.byte 0x00 0. " JTAG ,JTAG generated reset" "Not caused,Caused" line.byte 0x01 "SRSL,System Reset Status Register Low" bitfld.byte 0x01 7. " POR ,Power-on reset" "Not caused,Caused" bitfld.byte 0x01 6. " PIN ,External reset pin" "Not caused,Caused" bitfld.byte 0x01 5. " COP ,Computer operating properly (Cop) watchdog" "Not caused,Caused" newline bitfld.byte 0x01 2. " LOC ,Loss-of-clock reset" "Not caused,Caused" bitfld.byte 0x01 1. " LVD ,Low-voltage detect reset" "Not caused,Caused" bitfld.byte 0x01 0. " WAKEUP ,Low-leakage wakeup reset" "Not caused,Caused" group.byte 0x02++0x01 line.byte 0x00 "PMPROT,Power Mode Protection Register" bitfld.byte 0x00 5. " AVLP ,Allow very low power modes" "Not allowed,Allowed" bitfld.byte 0x00 4. " ALLS ,Allow low leakage stop mode" "Not allowed,Allowed" bitfld.byte 0x00 2. " AVLLS3 ,Allow very low leakage stop 3 mode" "Not allowed,Allowed" newline bitfld.byte 0x00 1. " AVLLS2 ,Allow very low leakage stop 2 mode" "Not allowed,Allowed" bitfld.byte 0x00 0. " AVLLS1 ,Allow very low leakage stop 1 mode" "Not allowed,Allowed" line.byte 0x01 "PMCTRL,Power Mode Control Register" hexmask.byte 0x01 0.--7. 1. "PMCTRL,Power mode control" newline else width 10. group.byte 0x00++0x01 line.byte 0x00 "PMPROT,Power Mode Protection Register" sif cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK02*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("KK65FN2M0CAC18R") bitfld.byte 0x00 7. " AHSRUN ,Allow high speed run mode" "Not allowed,Allowed" newline endif bitfld.byte 0x00 5. " AVLP ,Allow very low power modes" "Not allowed,Allowed" bitfld.byte 0x00 3. " ALLS ,Allow low leakage stop mode" "Not allowed,Allowed" bitfld.byte 0x00 1. " AVLLS ,Allow very low leakage stop mode" "Not allowed,Allowed" line.byte 0x01 "PMCTRL,Power Mode Control Register" sif !cpuis("MK?0D*7")&&!cpuis("MK65F*")&&!cpuis("MK66F*")&&!cpuis("MK02*")&&!cpuis("MK84FN2M0CAU15R")&&!cpuis("MK8?FN256V*")&&!cpuis("MK30DX256VLL7R") bitfld.byte 0x01 7. " LPWUI ,Low power wake up on interrupt" "Remain,Exit" newline endif sif cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK02*")||cpuis("MK8?FN256V*")||cpuis("KK65FN2M0CAC18R") bitfld.byte 0x01 5.--6. " RUNM ,Run mode control" "Normal,,Very low power,High speed run mode" newline elif cpuis("MK84FN2M0CAU15R") bitfld.byte 0x01 5.--6. " RUNM ,Run mode control" "Normal,,Very low power,High speed" newline else bitfld.byte 0x01 5.--6. " RUNM ,Run mode control" "Normal,,Very low power,?..." newline endif rbitfld.byte 0x01 3. " STOPA ,Stop aborted" "Not aborted,Aborted" bitfld.byte 0x01 0.--2. " STOPM ,Stop mode control" "Normal stop,,VLPS,LLS,VLLSX,?..." sif cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK02*")||cpuis("KK65FN2M0CAC18R") if (((per.b(ad:0x4007E000+0x01))&0x07)==0x04) sif cpuis("MK02*") group.byte 0x02++0x00 line.byte 0x00 "STOPCTRL,VLLS Control Register" bitfld.byte 0x00 6.--7. " PSTOPO ,Partial stop option" "STOP,PSTOP1,PSTOP2,?..." bitfld.byte 0x00 5. " PORPO ,POR power option" "Enabled,Disabled" bitfld.byte 0x00 0.--2. " LLSM ,VLLS mode control" "VLLS0,VLLS1,VLLS2,VLLS3,?..." else group.byte 0x02++0x00 line.byte 0x00 "STOPCTRL,VLLS Control Register" bitfld.byte 0x00 6.--7. " PSTOPO ,Partial stop option" "STOP,PSTOP1,PSTOP2,?..." bitfld.byte 0x00 5. " PORPO ,POR power option" "Enabled,Disabled" bitfld.byte 0x00 4. " RAM2PO ,RAM2 power option" "Not powered,Powered" newline bitfld.byte 0x00 0.--2. " LLSM ,VLLS mode control" "VLLS0,VLLS1,VLLS2,VLLS3,?..." endif elif (((per.b(ad:0x4007E000+0x01))&0x07)==0x03) sif cpuis("MK02*") group.byte 0x02++0x00 line.byte 0x00 "STOPCTRL,VLLS Control Register" bitfld.byte 0x00 6.--7. " PSTOPO ,Partial stop option" "STOP,PSTOP1,PSTOP2,?..." bitfld.byte 0x00 5. " PORPO ,POR power option" "Enabled,Disabled" bitfld.byte 0x00 0.--2. " LLSM ,LLS mode control" ",,LLS2,LLS3,?..." else group.byte 0x02++0x00 line.byte 0x00 "STOPCTRL,VLLS Control Register" bitfld.byte 0x00 6.--7. " PSTOPO ,Partial stop option" "STOP,PSTOP1,PSTOP2,?..." bitfld.byte 0x00 5. " PORPO ,POR power option" "Enabled,Disabled" bitfld.byte 0x00 4. " RAM2PO ,RAM2 power option" "Not powered,Powered" newline bitfld.byte 0x00 0.--2. " LLSM ,LLS mode control" ",,LLS2,LLS3,?..." endif else sif cpuis("MK02*") group.byte 0x02++0x00 line.byte 0x00 "STOPCTRL,VLLS Control Register" bitfld.byte 0x00 6.--7. " PSTOPO ,Partial stop option" "STOP,PSTOP1,PSTOP2,?..." bitfld.byte 0x00 5. " PORPO ,POR power option" "Enabled,Disabled" else group.byte 0x02++0x00 line.byte 0x00 "STOPCTRL,VLLS Control Register" bitfld.byte 0x00 6.--7. " PSTOPO ,Partial stop option" "STOP,PSTOP1,PSTOP2,?..." bitfld.byte 0x00 5. " PORPO ,POR power option" "Enabled,Disabled" bitfld.byte 0x00 4. " RAM2PO ,RAM2 power option" "Not powered,Powered" endif endif elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*") if (((per.b(ad:0x4007E000+0x01))&0x07)==0x04) group.byte 0x02++0x00 line.byte 0x00 "STOPCTRL,VLLS Control Register" bitfld.byte 0x00 6.--7. " PSTOPO ,Partial stop option" "STOP,PSTOP1,PSTOP2,?..." bitfld.byte 0x00 5. " PORPO ,Disable POR detect circuit in VLLS0 mode" "No,Yes" bitfld.byte 0x00 4. " RAM2PO ,Powering of RAM partition 2 in LLS2 or VLLS2 mode" "Not powered,Powered" bitfld.byte 0x00 3. " LPOPO ,Disable 1 kHz LPO clock in LLS/VLLSX modes" "No,Yes" newline bitfld.byte 0x00 0.--2. " LLSM ,VLLS mode control" "VLLS0,VLLS1,VLLS2,VLLS3,?..." elif (((per.b(ad:0x4007E000+0x01))&0x07)==0x03) group.byte 0x02++0x00 line.byte 0x00 "STOPCTRL,VLLS Control Register" bitfld.byte 0x00 6.--7. " PSTOPO ,Partial stop option" "STOP,PSTOP1,PSTOP2,?..." bitfld.byte 0x00 5. " PORPO ,Disable POR detect circuit in VLLS0 mode" "No,Yes" bitfld.byte 0x00 4. " RAM2PO ,Powering of RAM partition 2 in LLS2 or VLLS2 mode" "Not powered,Powered" bitfld.byte 0x00 3. " LPOPO ,Disable 1 kHz LPO clock in LLS/VLLSX modes" "No,Yes" newline bitfld.byte 0x00 0.--2. " LLSM ,VLLS mode control" ",,LLS2,LLS3,?..." else group.byte 0x02++0x00 line.byte 0x00 "STOPCTRL,VLLS Control Register" bitfld.byte 0x00 6.--7. " PSTOPO ,Partial stop option" "STOP,PSTOP1,PSTOP2,?..." bitfld.byte 0x00 5. " PORPO ,Disable POR detect circuit in VLLS0 mode" "No,Yes" bitfld.byte 0x00 4. " RAM2PO ,Powering of RAM partition 2 in LLS2 or VLLS2 mode" "Not powered,Powered" bitfld.byte 0x00 3. " LPOPO ,Disable 1 kHz LPO clock in LLS/VLLSX modes" "No,Yes" endif elif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*") if (((per.b(ad:0x4007E000+0x01))&0x07)==0x04) if (((per.b(ad:0x4007E000+0x02))&0x07)==0x00) group.byte 0x02++0x00 line.byte 0x00 "VLLSCTRL,Stop Control Register" bitfld.byte 0x00 5. " PORPO ,POR power option" "Enabled,Disabled" bitfld.byte 0x00 0.--2. " VLLSM ,VLLS mode control" "VLLS0,VLLS1,VLLS2,VLLS3,?..." elif (((per.b(ad:0x4007E000+0x02))&0x07)==0x02) group.byte 0x02++0x00 line.byte 0x00 "VLLSCTRL,Stop Control Register" bitfld.byte 0x00 4. " RAM2PO ,RAM2 power option" "Not powered,Powered" bitfld.byte 0x00 0.--2. " VLLSM ,VLLS mode control" "VLLS0,VLLS1,VLLS2,VLLS3,?..." else group.byte 0x02++0x00 line.byte 0x00 "VLLSCTRL,Stop Control Register" bitfld.byte 0x00 0.--2. " VLLSM ,VLLS mode control" "VLLS0,VLLS1,VLLS2,VLLS3,?..." endif else hgroup.byte 0x02++0x00 hide.byte 0x00 "VLLSCTRL,VLLS Control Register" endif else if (((per.b(ad:0x4007E000+0x01))&0x07)==0x04) group.byte 0x02++0x00 line.byte 0x00 "VLLSCTRL,Stop Control Register" sif cpuis("MK10D*5")||cpuis("MK11D*")||cpuis("MK12D*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK63F*") bitfld.byte 0x00 5. " PORPO ,POR power option" "Enabled,Disabled" newline endif sif cpuis("MK?0D*10")||cpuis("MK11D*")||cpuis("MK12D*")||cpuis("MK5?D*10")||cpuis("MK60D*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*") bitfld.byte 0x00 4. " RAM2PO ,RAM2 power option" "Not powered,Powered" newline endif sif cpuis("MK63FN1M0VLQ12R") bitfld.byte 0x00 0.--2. " VLLSM ,VLLS mode control" "VLLS0,VLLS1,VLLS2,VLLS3,?..." elif cpuis("MK?0D*7")||cpuis("MK?0D*10")||cpuis("MK10F*12")||cpuis("MK5?D*")||cpuis("MK6?*")||cpuis("MK70*")||cpuis("MK30DX256VLL7R")||cpuis("KK60FN1M0VLQ15") bitfld.byte 0x00 0.--2. " VLLSM ,VLLS mode control" ",VLLS1,VLLS2,VLLS3,?..." else bitfld.byte 0x00 0.--2. " VLLSM ,VLLS mode control" "VLLS0,VLLS1,VLLS2,VLLS3,?..." endif else hgroup.byte 0x02++0x00 hide.byte 0x00 "VLLSCTRL,VLLS Control Register" endif endif rgroup.byte 0x03++0x00 line.byte 0x00 "PMSTAT,Power Mode Status Register" sif !cpuis("MK65F*")&&!cpuis("MK66F*")&&!cpuis("MK02*")&&!cpuis("MK84FN2M0CAU15R")&&!cpuis("MK8?FN256V*")&&!cpuis("MK63F*")&&!cpuis("MK60F*")&&!cpuis("KK60FN1M0VLQ15")&&!cpuis("KK65FN2M0CAC18R") hexmask.byte 0x00 0.--6. 1. "PMSTAT ,PMSTAT" endif endif width 0x0B tree.end tree "PMC (Power Management Controller)" base ad:0x4007D000 width 8. group.byte 0x00++0x02 line.byte 0x00 "LVDSC1,Low Voltage Detect Status and Control 1 Register" rbitfld.byte 0x00 7. " LVDF ,Low-voltage detect flag" "Not detected,Detected" bitfld.byte 0x00 6. " LVDACK ,Low-voltage detect acknowledge" "NACK,ACK" bitfld.byte 0x00 5. " LVDIE ,Low-voltage detect interrupt enable" "Disabled,Enabled" newline bitfld.byte 0x00 4. " LVDRE ,Low-voltage detect reset enable" "Disabled,Enabled" bitfld.byte 0x00 0.--1. " LVDV ,Low-voltage detect voltage select" "Low trip,High trip,?..." line.byte 0x01 "LVDSC2,Low Voltage Detect Status and Control 2 Register" rbitfld.byte 0x01 7. " LVWF ,Low-voltage warning flag" "Not detected,Detected" bitfld.byte 0x01 6. " LVWACK ,Low-voltage warning acknowledge" "NACK,ACK" bitfld.byte 0x01 5. " LVWIE ,Low-voltage warning interrupt enable" "Disabled,Enabled" newline bitfld.byte 0x01 0.--1. " LVWV ,Low-voltage warning voltage select" "Low trip point,Mid 1 trip point,Mid 2 trip point,High trip point" line.byte 0x02 "REGSC,Regulator Status and Control Register" sif cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK40DX*Z*10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DX256ZCMC10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZCAB10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60DN512ZCAB10R") bitfld.byte 0x02 4. " TRAMPO ,Traditional RAM power option" "Not powered,Powered" newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK02*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK30DX256ZVLQ10")||cpuis("KK60DN512ZCAB10R") bitfld.byte 0x02 4. " BGEN ,Bandgap Enable In VLPx/LLS/VLLSx modes" "Disabled,Enabled" newline elif !cpuis("MK10F*12*")&&!cpuis("MK10DN512ZV??10*")&&!cpuis("MK10DX256ZV??10*")&&!cpuis("MK60FN1M0VLQ15")&&!cpuis("MK70FN1M0VMJ1*")&&!cpuis("KK60FN1M0VLQ15") bitfld.byte 0x02 4. " BGEN ,Bandgap enable" "Enabled,Disabled" newline elif cpuis("MK10DX256ZV??10*") bitfld.byte 0x02 4. " TRAMPO ,Traditional RAM power option" "Not powered,Powered" newline endif sif (cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*"))||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK40D*Z*10")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("KK60DN512ZCAB10R") rbitfld.byte 0x02 3. " VLPRS ,Very low power run status" "Off,On" newline else eventfld.byte 0x02 3. " ACKISO ,Acknowledge isolation" "Disabled,Enabled" newline endif rbitfld.byte 0x02 2. " REGONS ,Regulator in run regulation status" "Stop,Run" sif cpuis("MK?0D*7") newline bitfld.byte 0x02 1. " BGBE ,Bandgap buffer enable" "Disabled,Enabled" else newline bitfld.byte 0x02 0. " BGBE ,Bandgap buffer enable" "Disabled,Enabled" endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*") group.byte 0x0B++0x00 line.byte 0x00 "HVDSC1,High Voltage Detect Status And Control 1 Register" rbitfld.byte 0x00 7. " HVDF ,High-voltage detect flag" "Not detected,Detected" bitfld.byte 0x00 6. " HVDACK ,High-voltage detect acknowledge" "NACK,ACK" bitfld.byte 0x00 5. " HVDIE ,High-voltage detect interrupt enable" "Disabled,Enabled" newline bitfld.byte 0x00 4. " HVDRE ,High-voltage detect reset enable" "Disabled,Enabled" bitfld.byte 0x00 0. " HVDV ,High-voltage detect voltage select" "Low trip,High trip" endif width 0x0B tree.end tree "LLWU (Low-Leakage Wake-up Unit)" base ad:0x4007C000 width 7. sif cpuis("MK8?FN256V*") group.byte 0x00++0x0C line.byte 0x00 "PE1,LLWU Pin Enable 1 Register" bitfld.byte 0x00 6.--7. " WUPE_3 ,Wakeup pin enable for LLWU_P3" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" bitfld.byte 0x00 4.--5. " WUPE_2 ,Wakeup pin enable for LLWU_P2" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" bitfld.byte 0x00 2.--3. " WUPE_1 ,Wakeup pin enable for LLWU_P1" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" bitfld.byte 0x00 0.--1. " WUPE_0 ,Wakeup pin enable for LLWU_P0" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" line.byte 0x01 "PE2,LLWU Pin Enable 2 Register" bitfld.byte 0x01 6.--7. " WUPE_7 ,Wakeup pin enable for LLWU_P7" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" bitfld.byte 0x01 4.--5. " WUPE_6 ,Wakeup pin enable for LLWU_P6" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" bitfld.byte 0x01 2.--3. " WUPE_5 ,Wakeup pin enable for LLWU_P5" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" bitfld.byte 0x01 0.--1. " WUPE_4 ,Wakeup pin enable for LLWU_P4" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" line.byte 0x02 "PE3,LLWU Pin Enable 3 Register" bitfld.byte 0x02 6.--7. " WUPE_11 ,Wakeup pin enable for LLWU_P11" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" bitfld.byte 0x02 4.--5. " WUPE_10 ,Wakeup pin enable for LLWU_P10" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" bitfld.byte 0x02 2.--3. " WUPE_9 ,Wakeup pin enable for LLWU_P9" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" bitfld.byte 0x02 0.--1. " WUPE_8 ,Wakeup pin enable for LLWU_P8" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" line.byte 0x03 "PE4,LLWU Pin Enable 4 Register" bitfld.byte 0x03 6.--7. " WUPE_15 ,Wakeup pin enable for LLWU_P15" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" bitfld.byte 0x03 4.--5. " WUPE_14 ,Wakeup pin enable for LLWU_P14" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" bitfld.byte 0x03 2.--3. " WUPE_13 ,Wakeup pin enable for LLWU_P13" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" bitfld.byte 0x03 0.--1. " WUPE_12 ,Wakeup pin enable for LLWU_P12" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" line.byte 0x04 "PE5,LLWU Pin Enable 5 Register" bitfld.byte 0x04 6.--7. " WUPE_19 ,Wakeup pin enable for LLWU_P19" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" bitfld.byte 0x04 4.--5. " WUPE_18 ,Wakeup pin enable for LLWU_P18" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" bitfld.byte 0x04 2.--3. " WUPE_17 ,Wakeup pin enable for LLWU_P17" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" bitfld.byte 0x04 0.--1. " WUPE_16 ,Wakeup pin enable for LLWU_P16" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" line.byte 0x05 "PE6,LLWU Pin Enable 6 Register" bitfld.byte 0x05 6.--7. " WUPE_23 ,Wakeup pin enable for LLWU_P23" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" bitfld.byte 0x05 4.--5. " WUPE_22 ,Wakeup pin enable for LLWU_P22" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" bitfld.byte 0x05 2.--3. " WUPE_21 ,Wakeup pin enable for LLWU_P21" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" bitfld.byte 0x05 0.--1. " WUPE_20 ,Wakeup pin enable for LLWU_P20" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" line.byte 0x06 "PE7,LLWU Pin Enable 7 Register" bitfld.byte 0x06 6.--7. " WUPE_27 ,Wakeup pin enable for LLWU_P27" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" bitfld.byte 0x06 4.--5. " WUPE_26 ,Wakeup pin enable for LLWU_P26" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" bitfld.byte 0x06 2.--3. " WUPE_25 ,Wakeup pin enable for LLWU_P25" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" bitfld.byte 0x06 0.--1. " WUPE_24 ,Wakeup pin enable for LLWU_P24" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" line.byte 0x07 "PE8,LLWU Pin Enable 8 Register" bitfld.byte 0x07 6.--7. " WUPE_31 ,Wakeup pin enable for LLWU_P31" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" bitfld.byte 0x07 4.--5. " WUPE_30 ,Wakeup pin enable for LLWU_P30" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" bitfld.byte 0x07 2.--3. " WUPE_29 ,Wakeup pin enable for LLWU_P29" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" bitfld.byte 0x07 0.--1. " WUPE_28 ,Wakeup pin enable for LLWU_P28" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" line.byte 0x08 "ME,LLWU Module Enable Register" bitfld.byte 0x08 7. " WUME_7 ,Wakeup module enable for module 7" "Disabled,Enabled" bitfld.byte 0x08 6. " WUME_6 ,Wakeup module enable for module 6" "Disabled,Enabled" bitfld.byte 0x08 5. " WUME_5 ,Wakeup module enable for module 5" "Disabled,Enabled" bitfld.byte 0x08 4. " WUME_4 ,Wakeup module enable for module 4" "Disabled,Enabled" newline bitfld.byte 0x08 3. " WUME_3 ,Wakeup module enable for module 3" "Disabled,Enabled" bitfld.byte 0x08 2. " WUME_2 ,Wakeup module enable for module 2" "Disabled,Enabled" bitfld.byte 0x08 1. " WUME_1 ,Wakeup module enable for module 1" "Disabled,Enabled" bitfld.byte 0x08 0. " WUME_0 ,Wakeup module enable for module 0" "Disabled,Enabled" line.byte 0x09 "F1,LLWU Pin Flag 1 Register" eventfld.byte 0x09 7. " WUF_7 ,Wakeup flag for LLWU_P7" "No wakeup,Wakeup" eventfld.byte 0x09 6. " WUF_6 ,Wakeup flag for LLWU_P6" "No wakeup,Wakeup" eventfld.byte 0x09 5. " WUF_5 ,Wakeup flag for LLWU_P5" "No wakeup,Wakeup" eventfld.byte 0x09 4. " WUF_4 ,Wakeup flag for LLWU_P4" "No wakeup,Wakeup" newline eventfld.byte 0x09 3. " WUF_3 ,Wakeup flag for LLWU_P3" "No wakeup,Wakeup" eventfld.byte 0x09 2. " WUF_2 ,Wakeup flag for LLWU_P2" "No wakeup,Wakeup" eventfld.byte 0x09 1. " WUF_1 ,Wakeup flag for LLWU_P1" "No wakeup,Wakeup" eventfld.byte 0x09 0. " WUF_0 ,Wakeup flag for LLWU_P0" "No wakeup,Wakeup" line.byte 0x0A "F2,LLWU Pin Flag 2 Register" eventfld.byte 0x0A 7. " WUF_15 ,Wakeup flag for LLWU_P15" "No wakeup,Wakeup" eventfld.byte 0x0A 6. " WUF_14 ,Wakeup flag for LLWU_P14" "No wakeup,Wakeup" eventfld.byte 0x0A 5. " WUF_13 ,Wakeup flag for LLWU_P13" "No wakeup,Wakeup" eventfld.byte 0x0A 4. " WUF_12 ,Wakeup flag for LLWU_P12" "No wakeup,Wakeup" newline eventfld.byte 0x0A 3. " WUF_11 ,Wakeup flag for LLWU_P11" "No wakeup,Wakeup" eventfld.byte 0x0A 2. " WUF_10 ,Wakeup flag for LLWU_P10" "No wakeup,Wakeup" eventfld.byte 0x0A 1. " WUF_9 ,Wakeup flag for LLWU_P9" "No wakeup,Wakeup" eventfld.byte 0x0A 0. " WUF_8 ,Wakeup flag for LLWU_P8" "No wakeup,Wakeup" line.byte 0x0B "F3,LLWU Pin Flag 3 Register" eventfld.byte 0x0B 7. " WUF_23 ,Wakeup flag for LLWU_P23" "No wakeup,Wakeup" eventfld.byte 0x0B 6. " WUF_22 ,Wakeup flag for LLWU_P22" "No wakeup,Wakeup" eventfld.byte 0x0B 5. " WUF_21 ,Wakeup flag for LLWU_P21" "No wakeup,Wakeup" eventfld.byte 0x0B 4. " WUF_20 ,Wakeup flag for LLWU_P20" "No wakeup,Wakeup" newline eventfld.byte 0x0B 3. " WUF_19 ,Wakeup flag for LLWU_P19" "No wakeup,Wakeup" eventfld.byte 0x0B 2. " WUF_18 ,Wakeup flag for LLWU_P18" "No wakeup,Wakeup" eventfld.byte 0x0B 1. " WUF_17 ,Wakeup flag for LLWU_P17" "No wakeup,Wakeup" eventfld.byte 0x0B 0. " WUF_16 ,Wakeup flag for LLWU_P16" "No wakeup,Wakeup" line.byte 0x0C "F4,LLWU Pin Flag 4 Register" eventfld.byte 0x0C 7. " WUF_31 ,Wakeup flag for LLWU_P31" "No wakeup,Wakeup" eventfld.byte 0x0C 6. " WUF_30 ,Wakeup flag for LLWU_P30" "No wakeup,Wakeup" eventfld.byte 0x0C 5. " WUF_29 ,Wakeup flag for LLWU_P29" "No wakeup,Wakeup" eventfld.byte 0x0C 4. " WUF_28 ,Wakeup flag for LLWU_P28" "No wakeup,Wakeup" newline eventfld.byte 0x0C 3. " WUF_27 ,Wakeup flag for LLWU_P27" "No wakeup,Wakeup" eventfld.byte 0x0C 2. " WUF_26 ,Wakeup flag for LLWU_P26" "No wakeup,Wakeup" eventfld.byte 0x0C 1. " WUF_25 ,Wakeup flag for LLWU_P25" "No wakeup,Wakeup" eventfld.byte 0x0C 0. " WUF_24 ,Wakeup flag for LLWU_P24" "No wakeup,Wakeup" else group.byte 0x00++0x06 line.byte 0x00 "PE1,LLWU Pin Enable 1 Register" bitfld.byte 0x00 6.--7. " WUPE_3 ,Wakeup pin enable for LLWU_P3" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" bitfld.byte 0x00 4.--5. " WUPE_2 ,Wakeup pin enable for LLWU_P2" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" bitfld.byte 0x00 2.--3. " WUPE_1 ,Wakeup pin enable for LLWU_P1" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" bitfld.byte 0x00 0.--1. " WUPE_0 ,Wakeup pin enable for LLWU_P0" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" line.byte 0x01 "PE2,LLWU Pin Enable 2 Register" bitfld.byte 0x01 6.--7. " WUPE_7 ,Wakeup pin enable for LLWU_P7" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" bitfld.byte 0x01 4.--5. " WUPE_6 ,Wakeup pin enable for LLWU_P6" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" bitfld.byte 0x01 2.--3. " WUPE_5 ,Wakeup pin enable for LLWU_P5" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" bitfld.byte 0x01 0.--1. " WUPE_4 ,Wakeup pin enable for LLWU_P4" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" line.byte 0x02 "PE3,LLWU Pin Enable 3 Register" bitfld.byte 0x02 6.--7. " WUPE_11 ,Wakeup pin enable for LLWU_P11" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" bitfld.byte 0x02 4.--5. " WUPE_10 ,Wakeup pin enable for LLWU_P10" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" bitfld.byte 0x02 2.--3. " WUPE_9 ,Wakeup pin enable for LLWU_P9" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" bitfld.byte 0x02 0.--1. " WUPE_8 ,Wakeup pin enable for LLWU_P8" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" line.byte 0x03 "PE4,LLWU Pin Enable 4 Register" bitfld.byte 0x03 6.--7. " WUPE_15 ,Wakeup pin enable for LLWU_P15" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" bitfld.byte 0x03 4.--5. " WUPE_14 ,Wakeup pin enable for LLWU_P14" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" bitfld.byte 0x03 2.--3. " WUPE_13 ,Wakeup pin enable for LLWU_P13" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" bitfld.byte 0x03 0.--1. " WUPE_12 ,Wakeup pin enable for LLWU_P12" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" line.byte 0x04 "PE5,LLWU Pin Enable 5 Register" bitfld.byte 0x04 6.--7. " WUPE_19 ,Wakeup pin enable for LLWU_P19" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" bitfld.byte 0x04 4.--5. " WUPE_18 ,Wakeup pin enable for LLWU_P18" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" bitfld.byte 0x04 2.--3. " WUPE_17 ,Wakeup pin enable for LLWU_P17" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" bitfld.byte 0x04 0.--1. " WUPE_16 ,Wakeup pin enable for LLWU_P16" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" line.byte 0x05 "PE6,LLWU Pin Enable 6 Register" bitfld.byte 0x05 6.--7. " WUPE_23 ,Wakeup pin enable for LLWU_P23" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" bitfld.byte 0x05 4.--5. " WUPE_22 ,Wakeup pin enable for LLWU_P22" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" bitfld.byte 0x05 2.--3. " WUPE_21 ,Wakeup pin enable for LLWU_P21" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" bitfld.byte 0x05 0.--1. " WUPE_20 ,Wakeup pin enable for LLWU_P20" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" line.byte 0x06 "PE7,LLWU Pin Enable 7 Register" bitfld.byte 0x06 2.--3. " WUPE_25 ,Wakeup pin enable for LLWU_P25" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" bitfld.byte 0x06 0.--1. " WUPE_24 ,Wakeup pin enable for LLWU_P24" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" group.byte 0x08++0x04 line.byte 0x00 "ME,LLWU Module Enable Register" bitfld.byte 0x00 7. " WUME_7 ,Wakeup module enable for module 7" "Disabled,Enabled" bitfld.byte 0x00 6. " WUME_6 ,Wakeup module enable for module 6" "Disabled,Enabled" bitfld.byte 0x00 5. " WUME_5 ,Wakeup module enable for module 5" "Disabled,Enabled" bitfld.byte 0x00 4. " WUME_4 ,Wakeup module enable for module 4" "Disabled,Enabled" newline bitfld.byte 0x00 3. " WUME_3 ,Wakeup module enable for module 3" "Disabled,Enabled" bitfld.byte 0x00 2. " WUME_2 ,Wakeup module enable for module 2" "Disabled,Enabled" bitfld.byte 0x00 1. " WUME_1 ,Wakeup module enable for module 1" "Disabled,Enabled" bitfld.byte 0x00 0. " WUME_0 ,Wakeup module enable for module 0" "Disabled,Enabled" line.byte 0x01 "F1,LLWU Pin Flag 1 Register" eventfld.byte 0x01 7. " WUF_7 ,Wakeup flag for LLWU_P7" "No wakeup,Wakeup" eventfld.byte 0x01 6. " WUF_6 ,Wakeup flag for LLWU_P6" "No wakeup,Wakeup" eventfld.byte 0x01 5. " WUF_5 ,Wakeup flag for LLWU_P5" "No wakeup,Wakeup" eventfld.byte 0x01 4. " WUF_4 ,Wakeup flag for LLWU_P4" "No wakeup,Wakeup" newline eventfld.byte 0x01 3. " WUF_3 ,Wakeup flag for LLWU_P3" "No wakeup,Wakeup" eventfld.byte 0x01 2. " WUF_2 ,Wakeup flag for LLWU_P2" "No wakeup,Wakeup" eventfld.byte 0x01 1. " WUF_1 ,Wakeup flag for LLWU_P1" "No wakeup,Wakeup" eventfld.byte 0x01 0. " WUF_0 ,Wakeup flag for LLWU_P0" "No wakeup,Wakeup" line.byte 0x02 "F2,LLWU Pin Flag 2 Register" eventfld.byte 0x02 7. " WUF_15 ,Wakeup flag for LLWU_P15" "No wakeup,Wakeup" eventfld.byte 0x02 6. " WUF_14 ,Wakeup flag for LLWU_P14" "No wakeup,Wakeup" eventfld.byte 0x02 5. " WUF_13 ,Wakeup flag for LLWU_P13" "No wakeup,Wakeup" eventfld.byte 0x02 4. " WUF_12 ,Wakeup flag for LLWU_P12" "No wakeup,Wakeup" newline eventfld.byte 0x02 3. " WUF_11 ,Wakeup flag for LLWU_P11" "No wakeup,Wakeup" eventfld.byte 0x02 2. " WUF_10 ,Wakeup flag for LLWU_P10" "No wakeup,Wakeup" eventfld.byte 0x02 1. " WUF_9 ,Wakeup flag for LLWU_P9" "No wakeup,Wakeup" eventfld.byte 0x02 0. " WUF_8 ,Wakeup flag for LLWU_P8" "No wakeup,Wakeup" line.byte 0x03 "F3,LLWU Pin Flag 3 Register" eventfld.byte 0x03 7. " WUF_23 ,Wakeup flag for LLWU_P23" "No wakeup,Wakeup" eventfld.byte 0x03 6. " WUF_22 ,Wakeup flag for LLWU_P22" "No wakeup,Wakeup" eventfld.byte 0x03 5. " WUF_21 ,Wakeup flag for LLWU_P21" "No wakeup,Wakeup" eventfld.byte 0x03 4. " WUF_20 ,Wakeup flag for LLWU_P20" "No wakeup,Wakeup" newline eventfld.byte 0x03 3. " WUF_19 ,Wakeup flag for LLWU_P19" "No wakeup,Wakeup" eventfld.byte 0x03 2. " WUF_18 ,Wakeup flag for LLWU_P18" "No wakeup,Wakeup" eventfld.byte 0x03 1. " WUF_17 ,Wakeup flag for LLWU_P17" "No wakeup,Wakeup" eventfld.byte 0x03 0. " WUF_16 ,Wakeup flag for LLWU_P16" "No wakeup,Wakeup" line.byte 0x04 "F4,LLWU Pin Flag 4 Register" eventfld.byte 0x04 1. " WUF_25 ,Wakeup flag for LLWU_P25" "No wakeup,Wakeup" eventfld.byte 0x04 0. " WUF_24 ,Wakeup flag for LLWU_P24" "No wakeup,Wakeup" endif rgroup.byte 0x0D++0x00 line.byte 0x00 "MF5,LLWU Module Flag 5 Register" bitfld.byte 0x00 7. " MWUF_7 ,Wakeup flag for module 7" "No wakeup,Wakeup" bitfld.byte 0x00 6. " MWUF_6 ,Wakeup flag for module 6" "No wakeup,Wakeup" bitfld.byte 0x00 5. " MWUF_5 ,Wakeup flag for module 5" "No wakeup,Wakeup" bitfld.byte 0x00 4. " MWUF_4 ,Wakeup flag for module 4" "No wakeup,Wakeup" newline bitfld.byte 0x00 3. " MWUF_3 ,Wakeup flag for module 3" "No wakeup,Wakeup" bitfld.byte 0x00 2. " MWUF_2 ,Wakeup flag for module 2" "No wakeup,Wakeup" bitfld.byte 0x00 1. " MWUF_1 ,Wakeup flag for module 1" "No wakeup,Wakeup" bitfld.byte 0x00 0. " MWUF_0 ,Wakeup flag for module 0" "No wakeup,Wakeup" sif cpuis("MK8?FN256V*") group.byte 0xE++0x00 line.byte 0x00 "FILT1,LLWU Pin Filter 1 Register" eventfld.byte 0x00 7. " FILTF ,Filter detect flag" "No wakeup,Wakeup" bitfld.byte 0x00 5.--6. " FILTE ,Digital filter on external pin" "Disabled,Filter posedge,Filter negedge,Filter any edge" bitfld.byte 0x00 0.--4. " FILTSEL ,Filter pin select" "LLWU_P0,LLWU_P1,LLWU_P2,LLWU_P3,LLWU_P4,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,LLWU_P11,LLWU_P12,LLWU_P13,LLWU_P14,LLWU_P15,LLWU_P16,LLWU_P17,LLWU_P18,LLWU_P19,LLWU_P20,LLWU_P21,LLWU_P22,LLWU_P23,LLWU_P24,LLWU_P25,LLWU_P26,LLWU_P27,LLWU_P28,LLWU_P29,LLWU_P30,LLWU_P31" group.byte 0xF++0x00 line.byte 0x00 "FILT2,LLWU Pin Filter 2 Register" eventfld.byte 0x00 7. " FILTF ,Filter detect flag" "No wakeup,Wakeup" bitfld.byte 0x00 5.--6. " FILTE ,Digital filter on external pin" "Disabled,Filter posedge,Filter negedge,Filter any edge" bitfld.byte 0x00 0.--4. " FILTSEL ,Filter pin select" "LLWU_P0,LLWU_P1,LLWU_P2,LLWU_P3,LLWU_P4,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,LLWU_P11,LLWU_P12,LLWU_P13,LLWU_P14,LLWU_P15,LLWU_P16,LLWU_P17,LLWU_P18,LLWU_P19,LLWU_P20,LLWU_P21,LLWU_P22,LLWU_P23,LLWU_P24,LLWU_P25,LLWU_P26,LLWU_P27,LLWU_P28,LLWU_P29,LLWU_P30,LLWU_P31" group.byte 0x10++0x00 line.byte 0x00 "FILT3,LLWU Pin Filter 3 Register" eventfld.byte 0x00 7. " FILTF ,Filter detect flag" "No wakeup,Wakeup" bitfld.byte 0x00 5.--6. " FILTE ,Digital filter on external pin" "Disabled,Filter posedge,Filter negedge,Filter any edge" bitfld.byte 0x00 0.--4. " FILTSEL ,Filter pin select" "LLWU_P0,LLWU_P1,LLWU_P2,LLWU_P3,LLWU_P4,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,LLWU_P11,LLWU_P12,LLWU_P13,LLWU_P14,LLWU_P15,LLWU_P16,LLWU_P17,LLWU_P18,LLWU_P19,LLWU_P20,LLWU_P21,LLWU_P22,LLWU_P23,LLWU_P24,LLWU_P25,LLWU_P26,LLWU_P27,LLWU_P28,LLWU_P29,LLWU_P30,LLWU_P31" group.byte 0x11++0x00 line.byte 0x00 "FILT4,LLWU Pin Filter 4 Register" eventfld.byte 0x00 7. " FILTF ,Filter detect flag" "No wakeup,Wakeup" bitfld.byte 0x00 5.--6. " FILTE ,Digital filter on external pin" "Disabled,Filter posedge,Filter negedge,Filter any edge" bitfld.byte 0x00 0.--4. " FILTSEL ,Filter pin select" "LLWU_P0,LLWU_P1,LLWU_P2,LLWU_P3,LLWU_P4,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,LLWU_P11,LLWU_P12,LLWU_P13,LLWU_P14,LLWU_P15,LLWU_P16,LLWU_P17,LLWU_P18,LLWU_P19,LLWU_P20,LLWU_P21,LLWU_P22,LLWU_P23,LLWU_P24,LLWU_P25,LLWU_P26,LLWU_P27,LLWU_P28,LLWU_P29,LLWU_P30,LLWU_P31" else group.byte 0xE++0x00 line.byte 0x00 "FILT1,LLWU Pin Filter 1 Register" eventfld.byte 0x00 7. " FILTF ,Filter detect flag" "No wakeup,Wakeup" bitfld.byte 0x00 5.--6. " FILTE ,Digital filter on external pin" "Disabled,Filter posedge,Filter negedge,Filter any edge" bitfld.byte 0x00 0.--4. " FILTSEL ,Filter pin select" "LLWU_P0,LLWU_P1,LLWU_P2,LLWU_P3,LLWU_P4,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,LLWU_P11,LLWU_P12,LLWU_P13,LLWU_P14,LLWU_P15,LLWU_P16,LLWU_P17,LLWU_P18,LLWU_P19,LLWU_P20,LLWU_P21,LLWU_P22,LLWU_P23,LLWU_P24,LLWU_P25,?..." group.byte 0xF++0x00 line.byte 0x00 "FILT2,LLWU Pin Filter 2 Register" eventfld.byte 0x00 7. " FILTF ,Filter detect flag" "No wakeup,Wakeup" bitfld.byte 0x00 5.--6. " FILTE ,Digital filter on external pin" "Disabled,Filter posedge,Filter negedge,Filter any edge" bitfld.byte 0x00 0.--4. " FILTSEL ,Filter pin select" "LLWU_P0,LLWU_P1,LLWU_P2,LLWU_P3,LLWU_P4,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,LLWU_P11,LLWU_P12,LLWU_P13,LLWU_P14,LLWU_P15,LLWU_P16,LLWU_P17,LLWU_P18,LLWU_P19,LLWU_P20,LLWU_P21,LLWU_P22,LLWU_P23,LLWU_P24,LLWU_P25,?..." group.byte 0x10++0x00 line.byte 0x00 "FILT3,LLWU Pin Filter 3 Register" eventfld.byte 0x00 7. " FILTF ,Filter detect flag" "No wakeup,Wakeup" bitfld.byte 0x00 5.--6. " FILTE ,Digital filter on external pin" "Disabled,Filter posedge,Filter negedge,Filter any edge" bitfld.byte 0x00 0.--4. " FILTSEL ,Filter pin select" "LLWU_P0,LLWU_P1,LLWU_P2,LLWU_P3,LLWU_P4,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,LLWU_P11,LLWU_P12,LLWU_P13,LLWU_P14,LLWU_P15,LLWU_P16,LLWU_P17,LLWU_P18,LLWU_P19,LLWU_P20,LLWU_P21,LLWU_P22,LLWU_P23,LLWU_P24,LLWU_P25,?..." group.byte 0x11++0x00 line.byte 0x00 "FILT4,LLWU Pin Filter 4 Register" eventfld.byte 0x00 7. " FILTF ,Filter detect flag" "No wakeup,Wakeup" bitfld.byte 0x00 5.--6. " FILTE ,Digital filter on external pin" "Disabled,Filter posedge,Filter negedge,Filter any edge" bitfld.byte 0x00 0.--4. " FILTSEL ,Filter pin select" "LLWU_P0,LLWU_P1,LLWU_P2,LLWU_P3,LLWU_P4,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,LLWU_P11,LLWU_P12,LLWU_P13,LLWU_P14,LLWU_P15,LLWU_P16,LLWU_P17,LLWU_P18,LLWU_P19,LLWU_P20,LLWU_P21,LLWU_P22,LLWU_P23,LLWU_P24,LLWU_P25,?..." endif width 0x0B tree.end tree "MCM (Miscellaneous Control Module)" base ad:0xE0080000 width 8. rgroup.word 0x08++0x03 line.word 0x00 "PLASC,Crossbar Switch (AXBS) Slave Configuration" bitfld.word 0x00 7. " ASC[7] ,Connection to the crossbar switch's slave input port 7" "Not connected,Connected" bitfld.word 0x00 6. " [6] ,Connection to the crossbar switch's slave input port 6" "Not connected,Connected" bitfld.word 0x00 5. " [5] ,Connection to the crossbar switch's slave input port 5" "Not connected,Connected" bitfld.word 0x00 4. " [4] ,Connection to the crossbar switch's slave input port 4" "Not connected,Connected" newline bitfld.word 0x00 3. " [3] ,Connection to the crossbar switch's slave input port 3" "Not connected,Connected" bitfld.word 0x00 2. " [2] ,Connection to the crossbar switch's slave input port 2" "Not connected,Connected" bitfld.word 0x00 1. " [1] ,Connection to the crossbar switch's slave input port 1" "Not connected,Connected" bitfld.word 0x00 0. " [0] ,Connection to the crossbar switch's slave input port 0" "Not connected,Connected" line.word 0x02 "PLAMC,Crossbar Switch (AXBS) Master Configuration" bitfld.word 0x02 7. " AMC[7] ,Connection to the AXBS master input port 7" "Not connected,Connected" bitfld.word 0x02 6. " [6] ,Connection to the AXBS master input port 6" "Not connected,Connected" bitfld.word 0x02 5. " [5] ,Connection to the AXBS master input port 5" "Not connected,Connected" bitfld.word 0x02 4. " [4] ,Connection to the AXBS master input port 4" "Not connected,Connected" newline bitfld.word 0x02 3. " [3] ,Connection to the AXBS master input port 3" "Not connected,Connected" bitfld.word 0x02 2. " [2] ,Connection to the AXBS master input port 2" "Not connected,Connected" bitfld.word 0x02 1. " [1] ,Connection to the AXBS master input port 1" "Not connected,Connected" bitfld.word 0x02 0. " [0] ,Connection to the AXBS master input port 0" "Not connected,Connected" newline sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK30DX256VLL7R") group.long 0x0C++0x03 line.long 0x00 "CR,Control Register" bitfld.long 0x00 30. " SRAMLWP ,SRAM_L write protect" "Not protected,Protected" bitfld.long 0x00 28.--29. " SRAMLAP ,SRAM_L arbitration priority" "Round robin,Special round robin,Processor highest,Backdoor highest" bitfld.long 0x00 26. " SRAMUWP ,SRAM_U write protect" "Not protected,Protected" newline bitfld.long 0x00 24.--25. " SRAMUAP ,SRAM_U arbitration priority" "Round robin,Special round robin,Processor highest,Backdoor highest" elif (cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R"))||cpuis("MK40D*Z*10")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60FN1M0VLQ15")||cpuis("MK60DN512ZCAB10R") group.long 0x0C++0x03 line.long 0x00 "SRAMAP,SRAM Arbitration And Protection Register" bitfld.long 0x00 30. " SRAMLWP ,SRAM_L write protect" "Not protected,Protected" bitfld.long 0x00 28.--29. " SRAMLAP ,SRAM_L arbitration priority" "Round robin,Special round robin,Processor highest,Backdoor highest" bitfld.long 0x00 26. " SRAMUWP ,SRAM_U write protect" "Not protected,Protected" newline bitfld.long 0x00 24.--25. " SRAMUAP ,SRAM_U arbitration priority" "Round robin,Special round robin,Processor highest,Backdoor highest" elif cpuis("MK10D*7")||cpuis("MK10D*10")||cpuis("MK10F*12")||cpuis("MK30D*")||cpuis("MK40D*")||cpuis("MK5?D*")||cpuis("MK6*")||cpuis("MK70*") group.long 0x0C++0x03 line.long 0x00 "PLACR,Platform Control Register" bitfld.long 0x00 30. " SRAMLWP ,SRAM_L write protect" "Disabled,Enabled" bitfld.long 0x00 28.--29. " SRAMLAP ,SRAM_L arbitration priority" "Round robin,Special round robin,Fixed priority (Hi),Fixed priority (Low)" bitfld.long 0x00 26. " SRAMUWP ,SRAM_U write protect" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " SRAMUAP ,SRAM_U arbitration priority" "Round robin,Special round robin,Fixed priority (Hi),Fixed priority (Low)" sif cpuis("MK61*VMJ*")||cpuis("MK70*") newline bitfld.long 0x00 20.--21. " DDRSIZE ,DDR address size translation" "Disabled,128MB,256MB,512MB" endif else group.long 0x0C++0x03 line.long 0x00 "PLACR,Platform Control Register" bitfld.long 0x00 9. " ARB ,Arbitration select" "Fixed-priority,Round-robin" endif sif cpuis("MK02*") group.long 0x10++0x03 line.long 0x00 "ISCR,Interrupt Status And Control Register" bitfld.long 0x00 31. " FIDCE ,FPU input denormal interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " FIXCE ,FPU inexact interrupt enable" "Disabled,Enabled" bitfld.long 0x00 27. " FUFCE ,FPU underflow interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 26. " FOFCE ,FPU overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 25. " FDZCE ,FPU divide-by-zero interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " FIOCE ,FPU invalid operation interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 15. " FIDC ,FPU input denormal interrupt status" "Not occurred,Occurred" rbitfld.long 0x00 12. " FIXC ,FPU inexact interrupt status" "Not occurred,Occurred" rbitfld.long 0x00 11. " FUFC ,FPU underflow interrupt status" "Not occurred,Occurred" newline rbitfld.long 0x00 10. " FOFC ,FPU overflow interrupt status" "Not occurred,Occurred" rbitfld.long 0x00 9. " FDZC ,FPU divide-by-zero interrupt status" "Not occurred,Occurred" rbitfld.long 0x00 8. " FIOC ,FPU invalid operation interrupt status" "Not occurred,Occurred" group.long 0x40++0x03 line.long 0x00 "CPO,Compute Operation Control Register" bitfld.long 0x00 2. " CPOWOI ,Compute operation wakeup on interrupt" "No effect,Clr CPOREQ on int." rbitfld.long 0x00 1. " CPOACK ,Compute operation acknowledge" "Completed,Not completed" bitfld.long 0x00 0. " CPOREQ ,Compute operation request" "Not requested,Requested" elif cpuis("MK?0D*10")||cpuis("MK10F*12")||cpuis("MK5?D*10")||cpuis("MK6*")||cpuis("MK70*")||cpuis("MK10DN512ZVLK10R")||cpuis("MK10DN512ZVLL10R")||cpuis("MK10DX256ZVLQ10R")||cpuis("MK30DN512ZVLQ10R") group.long 0x10++0x0B line.long 0x00 "ISR,Interrupt Status Register" sif cpuis("MK10F*12")||cpuis("MK6?F*")||cpuis("MK70*") bitfld.long 0x00 31. " FIDCE ,FPU input denormal interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " FIXCE ,FPU inexact interrupt enable" "Disabled,Enabled" bitfld.long 0x00 27. " FUFCE ,FPU underflow interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 26. " FOFCE ,FPU overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 25. " FDZCE ,FPU divide-by-zero interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " FIOCE ,FPU invalid operation interrupt enable" "Disabled,Enabled" newline sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK65F*")&&!cpuis("MK66F*") bitfld.long 0x00 20. " CWBEE ,Cache write buffer error enable" "Disabled,Enabled" newline endif rbitfld.long 0x00 15. " FIDC ,FPU input denormal interrupt status" "Not occurred,Occurred" rbitfld.long 0x00 12. " FIXC ,FPU inexact interrupt status" "Not occurred,Occurred" rbitfld.long 0x00 11. " FUFC ,FPU underflow interrupt status" "Not occurred,Occurred" newline rbitfld.long 0x00 10. " FOFC ,FPU overflow interrupt status" "Not occurred,Occurred" rbitfld.long 0x00 9. " FDZC ,FPU divide-by-zero interrupt status" "Not occurred,Occurred" rbitfld.long 0x00 8. " FIOC ,FPU invalid operation interrupt status" "Not occurred,Occurred" newline sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK65F*")&&!cpuis("MK66F*") eventfld.long 0x00 4. " CWBER ,Cache write buffer error status" "Not occurred,Occurred" newline endif endif sif !cpuis("MK10DN512ZV??10*")&&!cpuis("MK10DX256ZV??10*")&&!cpuis("MK60*AB10")&&!cpuis("MK30DN512ZVLK10")&&!cpuis("MK30DN512ZVLQ10")&&!cpuis("MK30DX256ZVLQ10")&&!cpuis("MK30DN512ZVLQ10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZCAB10R")&&cpu()!=("MK50DN512ZCLL10")&&cpu()!=("MK50DX256ZCLL10")&&cpu()!=("MK50DN512ZCLQ10")&&cpu()!=("MK50DX256ZCLQ10")&&cpu()!=("MK51DN512ZCLL10")&&cpu()!=("MK51DN512ZCMC10")&&cpu()!=("MK51DX256ZCMC10")&&cpu()!=("MK51DN256ZCMD10")&&cpu()!=("MK51DN512ZCLQ10")&&cpu()!=("MK52DN512ZCLQ10")&&cpu()!=("MK52DN512ZCMD10")&&cpu()!=("MK53DN512ZCLQ10")&&cpu()!=("MK53DN512ZCMD10")&&cpu()!=("MK53DX256ZCLQ10")&&!cpuis("MK40D*Z*10") rbitfld.long 0x00 3. " DHREQ ,Debug halt request indicator" "Not occurred,Occurred" newline endif eventfld.long 0x00 2. " NMI ,Non-maskable interrupt pending" "Not pending,Pending" eventfld.long 0x00 1. " IRQ ,Normal interrupt pending" "Not pending,Pending" line.long 0x04 "ETBCC,ETB Counter Control Register" bitfld.long 0x04 5. " ITDIS ,ITM-to-TPIU disable" "No,Yes" bitfld.long 0x04 4. " ETDIS ,ETM-to-TPIU disable" "No,Yes" bitfld.long 0x04 3. " RLRQ ,Reload request clear" "No effect,Cleared" newline bitfld.long 0x04 1.--2. " RSPT ,Response type when the ETB count expires" "No response,Normal interrupt,NMI,Debug" bitfld.long 0x04 0. " CNTEN ,Counter enable" "Disabled,Enabled" line.long 0x08 "ETBRL,ETB Reload Register" hexmask.long.word 0x08 0.--10. 1. " RELOAD ,Byte count reload value" rgroup.long 0x1C++0x03 line.long 0x00 "ETBCNT,ETB Counter Value Register" hexmask.long.word 0x00 0.--10. 1. " COUNTER ,Byte count counter value" sif !cpuis("MK63FN1M0VLQ12R") sif cpuis("MK10F*12")||cpuis("MK6?F*")||cpuis("MK70*") rgroup.long 0x20++0x0B line.long 0x00 "FADR,Fault Address Register" line.long 0x04 "FATR,Fault Attributes Register" bitfld.long 0x04 31. " BEOVR ,Bus error overrun" "Not occurred,Occurred" bitfld.long 0x04 8.--11. " BEMN ,Bus error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 7. " BEWT ,Bus error write" "Read,Write" newline bitfld.long 0x04 4.--5. " BESZ ,Bus error size" "8-bit,16-bit,32-bit,?..." bitfld.long 0x04 1. " BEMD ,Bus error privilege level" "User mode,Supervisor mode" bitfld.long 0x04 0. " BEDA ,Bus error access type" "Instruction,Data" line.long 0x08 "FDR,Fault Data Register" endif endif sif !cpuis("MK10DN512ZV??10*")&&!cpuis("MK10DX256ZV??10*")&&!cpuis("MK60*AB10")&&!cpuis("MK30DN512ZVLK10")&&!cpuis("MK30DN512ZVLQ10")&&!cpuis("MK30DX256ZVLQ10")&&!cpuis("MK30DN512ZVLQ10R")&&cpu()!=("MK50DN512ZCLL10")&&cpu()!=("MK50DX256ZCLL10")&&cpu()!=("MK50DN512ZCLQ10")&&cpu()!=("MK50DX256ZCLQ10")&&cpu()!=("MK51DN512ZCLL10")&&cpu()!=("MK51DN512ZCMC10")&&cpu()!=("MK51DX256ZCMC10")&&cpu()!=("MK51DN256ZCMD10")&&cpu()!=("MK51DN512ZCLQ10")&&cpu()!=("MK52DN512ZCLQ10")&&cpu()!=("MK52DN512ZCMD10")&&cpu()!=("MK53DN512ZCLQ10")&&cpu()!=("MK53DN512ZCMD10")&&cpu()!=("MK53DX256ZCLQ10")&&!cpuis("MK40D*Z*10")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DX256ZVLL10") group.long 0x30++0x03 line.long 0x00 "PID,Process ID Register" hexmask.long.byte 0x00 0.--7. 1. " PID ,M0_PID and M1_PID for MPU" endif sif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0CAC18R") group.long 0x40++0x03 line.long 0x00 "CPO,Compute Operation Control Register" bitfld.long 0x00 2. " CPOWOI ,Compute operation wakeup on interrupt" "No effect,Clr CPOREQ on int." rbitfld.long 0x00 1. " CPOACK ,Compute operation acknowledge" "Completed,Not completed" bitfld.long 0x00 0. " CPOREQ ,Compute operation request" "Not requested,Requested" endif elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK60FN1M0VLQ15") group.long 0x10++0x03 line.long 0x00 "ISCR,Interrupt Status Register" bitfld.long 0x00 31. " FIDCE ,FPU input denormal interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " FIXCE ,FPU inexact interrupt enable" "Disabled,Enabled" bitfld.long 0x00 27. " FUFCE ,FPU underflow interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 26. " FOFCE ,FPU overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 25. " FDZCE ,FPU divide-by-zero interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " FIOCE ,FPU invalid operation interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 15. " FIDC ,FPU input denormal interrupt status" "Not occurred,Occurred" rbitfld.long 0x00 12. " FIXC ,FPU inexact interrupt status" "Not occurred,Occurred" rbitfld.long 0x00 11. " FUFC ,FPU underflow interrupt status" "Not occurred,Occurred" newline rbitfld.long 0x00 10. " FOFC ,FPU overflow interrupt status" "Not occurred,Occurred" rbitfld.long 0x00 9. " FDZC ,FPU divide-by-zero interrupt status" "Not occurred,Occurred" rbitfld.long 0x00 8. " FIOC ,FPU invalid operation interrupt status" "Not occurred,Occurred" sif !cpuis("MK60FN1M0VLQ15") newline rbitfld.long 0x00 6. " WABORTS_OVERRUN ,WABORTS assertion overrun" "No overrun,Overrun" rbitfld.long 0x00 5. " WABORTS ,WABORTS imprecise write fault from the TCM backdoor" "Not occurred,Occurred" else newline eventfld.long 0x00 4. " CWBER ,Cache write buffer error status" "Not occurred,Occurred" rbitfld.long 0x00 3. " DHREQ ,Debug halt request indicator" "Not requested,Initiated request" eventfld.long 0x00 2. " NMI ,Not maskable interrupt pending" "No pending,Pending" newline eventfld.long 0x00 1. " IRQ ,Normal interrupt pending" "No pending,Pending" endif sif cpuis("MK60FN1M0VLQ15") group.long 0x14++0x0B line.long 0x00 "ETBCC,ETB Counter Control Register" bitfld.long 0x00 5. " ITDIS ,ITM-to-TPIU disable" "No,Yes" bitfld.long 0x00 4. " ETDIS ,ETM-to-TPIU disable" "No,Yes" bitfld.long 0x00 3. " RLRQ ,Reload request clear" "No effect,Cleared" newline bitfld.long 0x00 1.--2. " RSPT ,Response type when the ETB count expires" "No response,Normal interrupt,NMI,Debug" bitfld.long 0x00 0. " CNTEN ,Counter enable" "Disabled,Enabled" line.long 0x04 "ETBRL,ETB Reload Register" hexmask.long.word 0x04 0.--10. 1. " RELOAD ,Byte count reload value" line.long 0x08 "ETBCNT,ETB Counter Value Register" hexmask.long.word 0x08 0.--10. 1. " COUNTER ,Byte count counter value" endif rgroup.long 0x20++0x0B line.long 0x00 "FADR,Fault Address Register" line.long 0x04 "FATR,Fault Attributes Register" bitfld.long 0x04 31. " BEOVR ,Bus error overrun" "Not occurred,Occurred" bitfld.long 0x04 8.--11. " BEMN ,Bus error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 7. " BEWT ,Bus error write" "Read,Write" newline bitfld.long 0x04 4.--5. " BESZ ,Bus error size" "8-bit,16-bit,32-bit,?..." bitfld.long 0x04 1. " BEMD ,Bus error privilege level" "User mode,Supervisor mode" bitfld.long 0x04 0. " BEDA ,Bus error access type" "Instruction,Data" line.long 0x08 "FDR,Fault Data Register" group.long 0x30++0x03 line.long 0x00 "PID,Process ID Register" hexmask.long.byte 0x00 0.--7. 1. " PID ,M0_PID and M1_PID for MPU" sif !cpuis("MK60FN1M0VLQ15") group.long 0x40++0x03 line.long 0x00 "CPO,Compute Operation Control Register" bitfld.long 0x00 2. " CPOWOI ,Compute operation wakeup on interrupt" "No effect,Clr CPOREQ on int." rbitfld.long 0x00 1. " CPOACK ,Compute operation acknowledge" "Completed,Not completed" bitfld.long 0x00 0. " CPOREQ ,Compute operation request" "Not requested,Requested" endif endif width 0x0B tree.end tree "AXBS (Crossbar Switch)" base ad:0x40004000 width 9. sif cpuis("MK26F*") group.long 0x0++0x03 line.long 0x00 "PRS0,Priority Register Slave" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,Lowest,?..." newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,Lowest,?..." group.long (0x0+0x10)++0x03 line.long 0x00 "CRS0,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,?..." group.long 0x100++0x03 line.long 0x00 "PRS1,Priority Register Slave" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,Lowest,?..." newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,Lowest,?..." group.long (0x100+0x10)++0x03 line.long 0x00 "CRS1,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,?..." group.long 0x200++0x03 line.long 0x00 "PRS2,Priority Register Slave" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,Lowest,?..." newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,Lowest,?..." group.long (0x200+0x10)++0x03 line.long 0x00 "CRS2,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,?..." group.long 0x300++0x03 line.long 0x00 "PRS3,Priority Register Slave" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,Lowest,?..." newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,Lowest,?..." group.long (0x300+0x10)++0x03 line.long 0x00 "CRS3,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,?..." group.long 0x400++0x03 line.long 0x00 "PRS4,Priority Register Slave" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,Lowest,?..." newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,Lowest,?..." group.long (0x400+0x10)++0x03 line.long 0x00 "CRS4,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,?..." group.long 0x800++0x03 line.long 0x00 "MGPCR0,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0x900++0x03 line.long 0x00 "MGPCR1,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xA00++0x03 line.long 0x00 "MGPCR2,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xB00++0x03 line.long 0x00 "MGPCR3,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xC00++0x03 line.long 0x00 "MGPCR4,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." elif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60FN1M0VLQ15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK60DN512ZVLQ10") sif !cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10") if (((per.l(ad:0x40004000+0x0+0x10))&0x80000000)==0x80000000) rgroup.long 0x0++0x03 line.long 0x00 "PRS0,Priority Register Slave" sif cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 28.--30. " ETH ,Ethernet priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 24.--26. " USB_HS ,USB_HS priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " SDHC/NFC/USB_FS ,SDHC/NFC/USB_FS priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " DMA/EzPort ,DMA/EzPort priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 4.--6. " ARM_CSB ,ARM core system bus priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " ARM_CCB ,ARM core code bus priority" "Highest,2,3,4,5,6,7,Lowest" else sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R")&&!cpuis("MK60DN512ZVLQ10") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK60DN512ZVLQ10") bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" endif rgroup.long (0x0+0x10)++0x03 sif !cpuis("KK60FN1M0VLQ15") line.long 0x00 "CRS0,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read Only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" elif cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,?..." else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif endif else group.long 0x0++0x03 line.long 0x00 "PRS0,Priority Register Slave" sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x0+0x10)++0x03 line.long 0x00 "CRS0,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif endif if (((per.l(ad:0x40004000+0x100+0x10))&0x80000000)==0x80000000) rgroup.long 0x100++0x03 line.long 0x00 "PRS1,Priority Register Slave" sif cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 28.--30. " ETH ,Ethernet priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 24.--26. " USB_HS ,USB_HS priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " SDHC/NFC/USB_FS ,SDHC/NFC/USB_FS priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " DMA/EzPort ,DMA/EzPort priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 4.--6. " ARM_CSB ,ARM core system bus priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " ARM_CCB ,ARM core code bus priority" "Highest,2,3,4,5,6,7,Lowest" else sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R")&&!cpuis("MK60DN512ZVLQ10") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK60DN512ZVLQ10") bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" endif rgroup.long (0x100+0x10)++0x03 sif !cpuis("KK60FN1M0VLQ15") line.long 0x00 "CRS1,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read Only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" elif cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,?..." else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif endif else group.long 0x100++0x03 line.long 0x00 "PRS1,Priority Register Slave" sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x100+0x10)++0x03 line.long 0x00 "CRS1,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif endif if (((per.l(ad:0x40004000+0x200+0x10))&0x80000000)==0x80000000) rgroup.long 0x200++0x03 line.long 0x00 "PRS2,Priority Register Slave" sif cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 28.--30. " ETH ,Ethernet priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 24.--26. " USB_HS ,USB_HS priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " SDHC/NFC/USB_FS ,SDHC/NFC/USB_FS priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " DMA/EzPort ,DMA/EzPort priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 4.--6. " ARM_CSB ,ARM core system bus priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " ARM_CCB ,ARM core code bus priority" "Highest,2,3,4,5,6,7,Lowest" else sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R")&&!cpuis("MK60DN512ZVLQ10") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK60DN512ZVLQ10") bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" endif rgroup.long (0x200+0x10)++0x03 sif !cpuis("KK60FN1M0VLQ15") line.long 0x00 "CRS2,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read Only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" elif cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,?..." else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif endif else group.long 0x200++0x03 line.long 0x00 "PRS2,Priority Register Slave" sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x200+0x10)++0x03 line.long 0x00 "CRS2,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif endif if (((per.l(ad:0x40004000+0x300+0x10))&0x80000000)==0x80000000) rgroup.long 0x300++0x03 line.long 0x00 "PRS3,Priority Register Slave" sif cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 28.--30. " ETH ,Ethernet priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 24.--26. " USB_HS ,USB_HS priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " SDHC/NFC/USB_FS ,SDHC/NFC/USB_FS priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " DMA/EzPort ,DMA/EzPort priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 4.--6. " ARM_CSB ,ARM core system bus priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " ARM_CCB ,ARM core code bus priority" "Highest,2,3,4,5,6,7,Lowest" else sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R")&&!cpuis("MK60DN512ZVLQ10") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK60DN512ZVLQ10") bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" endif rgroup.long (0x300+0x10)++0x03 sif !cpuis("KK60FN1M0VLQ15") line.long 0x00 "CRS3,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read Only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" elif cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,?..." else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif endif else group.long 0x300++0x03 line.long 0x00 "PRS3,Priority Register Slave" sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x300+0x10)++0x03 line.long 0x00 "CRS3,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif endif if (((per.l(ad:0x40004000+0x400+0x10))&0x80000000)==0x80000000) rgroup.long 0x400++0x03 line.long 0x00 "PRS4,Priority Register Slave" sif cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 28.--30. " ETH ,Ethernet priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 24.--26. " USB_HS ,USB_HS priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " SDHC/NFC/USB_FS ,SDHC/NFC/USB_FS priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " DMA/EzPort ,DMA/EzPort priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 4.--6. " ARM_CSB ,ARM core system bus priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " ARM_CCB ,ARM core code bus priority" "Highest,2,3,4,5,6,7,Lowest" else sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R")&&!cpuis("MK60DN512ZVLQ10") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK60DN512ZVLQ10") bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" endif rgroup.long (0x400+0x10)++0x03 sif !cpuis("KK60FN1M0VLQ15") line.long 0x00 "CRS4,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read Only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" elif cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,?..." else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif endif else group.long 0x400++0x03 line.long 0x00 "PRS4,Priority Register Slave" sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x400+0x10)++0x03 line.long 0x00 "CRS4,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif endif if (((per.l(ad:0x40004000+0x500+0x10))&0x80000000)==0x80000000) rgroup.long 0x500++0x03 line.long 0x00 "PRS5,Priority Register Slave" sif cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 28.--30. " ETH ,Ethernet priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 24.--26. " USB_HS ,USB_HS priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " SDHC/NFC/USB_FS ,SDHC/NFC/USB_FS priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " DMA/EzPort ,DMA/EzPort priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 4.--6. " ARM_CSB ,ARM core system bus priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " ARM_CCB ,ARM core code bus priority" "Highest,2,3,4,5,6,7,Lowest" else sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R")&&!cpuis("MK60DN512ZVLQ10") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK60DN512ZVLQ10") bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" endif rgroup.long (0x500+0x10)++0x03 sif !cpuis("KK60FN1M0VLQ15") line.long 0x00 "CRS5,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read Only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" elif cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,?..." else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif endif else group.long 0x500++0x03 line.long 0x00 "PRS5,Priority Register Slave" sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x500+0x10)++0x03 line.long 0x00 "CRS5,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif endif else if (((per.l(ad:0x40004000+0x0+0x10))&0x80000000)==0x80000000) rgroup.long 0x0++0x03 line.long 0x00 "PRS0,Priority Register Slave" sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R")&&!cpuis("MK60DN512ZVLQ10") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK60DN512ZVLQ10") bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" rgroup.long (0x0+0x10)++0x03 line.long 0x00 "CRS0,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read Only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif else group.long 0x0++0x03 line.long 0x00 "PRS0,Priority Register Slave" sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x0+0x10)++0x03 line.long 0x00 "CRS0,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif endif if (((per.l(ad:0x40004000+0x100+0x10))&0x80000000)==0x80000000) rgroup.long 0x100++0x03 line.long 0x00 "PRS1,Priority Register Slave" sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R")&&!cpuis("MK60DN512ZVLQ10") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK60DN512ZVLQ10") bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" rgroup.long (0x100+0x10)++0x03 line.long 0x00 "CRS1,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read Only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif else group.long 0x100++0x03 line.long 0x00 "PRS1,Priority Register Slave" sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x100+0x10)++0x03 line.long 0x00 "CRS1,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif endif if (((per.l(ad:0x40004000+0x200+0x10))&0x80000000)==0x80000000) rgroup.long 0x200++0x03 line.long 0x00 "PRS2,Priority Register Slave" sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R")&&!cpuis("MK60DN512ZVLQ10") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK60DN512ZVLQ10") bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" rgroup.long (0x200+0x10)++0x03 line.long 0x00 "CRS2,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read Only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif else group.long 0x200++0x03 line.long 0x00 "PRS2,Priority Register Slave" sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x200+0x10)++0x03 line.long 0x00 "CRS2,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif endif if (((per.l(ad:0x40004000+0x300+0x10))&0x80000000)==0x80000000) rgroup.long 0x300++0x03 line.long 0x00 "PRS3,Priority Register Slave" sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R")&&!cpuis("MK60DN512ZVLQ10") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK60DN512ZVLQ10") bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" rgroup.long (0x300+0x10)++0x03 line.long 0x00 "CRS3,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read Only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif else group.long 0x300++0x03 line.long 0x00 "PRS3,Priority Register Slave" sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x300+0x10)++0x03 line.long 0x00 "CRS3,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif endif if (((per.l(ad:0x40004000+0x400+0x10))&0x80000000)==0x80000000) rgroup.long 0x400++0x03 line.long 0x00 "PRS4,Priority Register Slave" sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R")&&!cpuis("MK60DN512ZVLQ10") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK60DN512ZVLQ10") bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" rgroup.long (0x400+0x10)++0x03 line.long 0x00 "CRS4,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read Only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif else group.long 0x400++0x03 line.long 0x00 "PRS4,Priority Register Slave" sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x400+0x10)++0x03 line.long 0x00 "CRS4,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif endif if (((per.l(ad:0x40004000+0x500+0x10))&0x80000000)==0x80000000) rgroup.long 0x500++0x03 line.long 0x00 "PRS5,Priority Register Slave" sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R")&&!cpuis("MK60DN512ZVLQ10") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK60DN512ZVLQ10") bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" rgroup.long (0x500+0x10)++0x03 line.long 0x00 "CRS5,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read Only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif else group.long 0x500++0x03 line.long 0x00 "PRS5,Priority Register Slave" sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x500+0x10)++0x03 line.long 0x00 "CRS5,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif endif endif group.long 0x800++0x03 line.long 0x00 "MGPCR0,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0x900++0x03 line.long 0x00 "MGPCR1,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xA00++0x03 line.long 0x00 "MGPCR2,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xB00++0x03 line.long 0x00 "MGPCR3,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xC00++0x03 line.long 0x00 "MGPCR4,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xD00++0x03 line.long 0x00 "MGPCR5,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xE00++0x03 line.long 0x00 "MGPCR6,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xF00++0x03 line.long 0x00 "MGPCR7,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." elif cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7") if (((per.l(ad:0x40004000+0x10+0x0))&0x80000000)==0x80000000) rgroup.long 0x0++0x03 line.long 0x00 "PRS0,Priority Register 0 Slave" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,Lowest,?..." rgroup.long (0x0+0x10)++0x03 line.long 0x00 "CRS0,Control Register 0" bitfld.long 0x00 31. " RO ,Read only" "Read/write,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Highest,Lowest" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin/rotating,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,?..." else group.long 0x0++0x03 line.long 0x00 "PRS0,Priority Register 0 Slave" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,Lowest,?..." group.long (0x0+0x10)++0x03 line.long 0x00 "CRS0,Control Register 0" bitfld.long 0x00 31. " RO ,Read only" "Read/write,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Highest,Lowest" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin/rotating,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,?..." endif if (((per.l(ad:0x40004000+0x10+0x100))&0x80000000)==0x80000000) rgroup.long 0x100++0x03 line.long 0x00 "PRS1,Priority Register 1 Slave" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,Lowest,?..." rgroup.long (0x100+0x10)++0x03 line.long 0x00 "CRS1,Control Register 1" bitfld.long 0x00 31. " RO ,Read only" "Read/write,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Highest,Lowest" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin/rotating,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,?..." else group.long 0x100++0x03 line.long 0x00 "PRS1,Priority Register 1 Slave" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,Lowest,?..." group.long (0x100+0x10)++0x03 line.long 0x00 "CRS1,Control Register 1" bitfld.long 0x00 31. " RO ,Read only" "Read/write,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Highest,Lowest" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin/rotating,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,?..." endif if (((per.l(ad:0x40004000+0x10+0x200))&0x80000000)==0x80000000) rgroup.long 0x200++0x03 line.long 0x00 "PRS2,Priority Register 2 Slave" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,Lowest,?..." rgroup.long (0x200+0x10)++0x03 line.long 0x00 "CRS2,Control Register 2" bitfld.long 0x00 31. " RO ,Read only" "Read/write,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Highest,Lowest" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin/rotating,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,?..." else group.long 0x200++0x03 line.long 0x00 "PRS2,Priority Register 2 Slave" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,Lowest,?..." group.long (0x200+0x10)++0x03 line.long 0x00 "CRS2,Control Register 2" bitfld.long 0x00 31. " RO ,Read only" "Read/write,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Highest,Lowest" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin/rotating,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,?..." endif if (((per.l(ad:0x40004000+0x10+0x300))&0x80000000)==0x80000000) rgroup.long 0x300++0x03 line.long 0x00 "PRS3,Priority Register 3 Slave" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,Lowest,?..." rgroup.long (0x300+0x10)++0x03 line.long 0x00 "CRS3,Control Register 3" bitfld.long 0x00 31. " RO ,Read only" "Read/write,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Highest,Lowest" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin/rotating,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,?..." else group.long 0x300++0x03 line.long 0x00 "PRS3,Priority Register 3 Slave" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,Lowest,?..." group.long (0x300+0x10)++0x03 line.long 0x00 "CRS3,Control Register 3" bitfld.long 0x00 31. " RO ,Read only" "Read/write,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Highest,Lowest" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin/rotating,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,?..." endif group.long 0x800++0x03 line.long 0x00 "MGPCR0,Master General Purpose Control Register 0" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0x900++0x03 line.long 0x00 "MGPCR1,Master General Purpose Control Register 1" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xA00++0x03 line.long 0x00 "MGPCR2,Master General Purpose Control Register 2" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xB00++0x03 line.long 0x00 "MGPCR3,Master General Purpose Control Register 3" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." elif cpuis("MK20DX256VLK7R")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7") if (((per.l(ad:0x40004000+0x10+0x0))&0x80000000)==0x80000000) rgroup.long 0x0++0x03 line.long 0x00 "PRS0,Priority Register 0 Slave" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,Lowest,?..." rgroup.long (0x0+0x10)++0x03 line.long 0x00 "CRS0,Control Register 0" bitfld.long 0x00 31. " RO ,Read only" "Read/write,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Highest,Lowest" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin/rotating,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,?..." else group.long 0x0++0x03 line.long 0x00 "PRS0,Priority Register 0 Slave" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,Lowest,?..." group.long (0x0+0x10)++0x03 line.long 0x00 "CRS0,Control Register 0" bitfld.long 0x00 31. " RO ,Read only" "Read/Write,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Highest,Lowest" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin/rotating,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,?..." endif if (((per.l(ad:0x40004000+0x10+0x100))&0x80000000)==0x80000000) rgroup.long 0x100++0x03 line.long 0x00 "PRS1,Priority Register 1 Slave" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,Lowest,?..." rgroup.long (0x100+0x10)++0x03 line.long 0x00 "CRS1,Control Register 1" bitfld.long 0x00 31. " RO ,Read only" "Read/write,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Highest,Lowest" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin/rotating,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,?..." else group.long 0x100++0x03 line.long 0x00 "PRS1,Priority Register 1 Slave" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,Lowest,?..." group.long (0x100+0x10)++0x03 line.long 0x00 "CRS1,Control Register 1" bitfld.long 0x00 31. " RO ,Read only" "Read/Write,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Highest,Lowest" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin/rotating,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,?..." endif if (((per.l(ad:0x40004000+0x10+0x200))&0x80000000)==0x80000000) rgroup.long 0x200++0x03 line.long 0x00 "PRS2,Priority Register 2 Slave" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,Lowest,?..." rgroup.long (0x200+0x10)++0x03 line.long 0x00 "CRS2,Control Register 2" bitfld.long 0x00 31. " RO ,Read only" "Read/write,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Highest,Lowest" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin/rotating,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,?..." else group.long 0x200++0x03 line.long 0x00 "PRS2,Priority Register 2 Slave" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,Lowest,?..." group.long (0x200+0x10)++0x03 line.long 0x00 "CRS2,Control Register 2" bitfld.long 0x00 31. " RO ,Read only" "Read/Write,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Highest,Lowest" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin/rotating,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,?..." endif if (((per.l(ad:0x40004000+0x10+0x300))&0x80000000)==0x80000000) rgroup.long 0x300++0x03 line.long 0x00 "PRS3,Priority Register 3 Slave" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,Lowest,?..." rgroup.long (0x300+0x10)++0x03 line.long 0x00 "CRS3,Control Register 3" bitfld.long 0x00 31. " RO ,Read only" "Read/write,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Highest,Lowest" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin/rotating,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,?..." else group.long 0x300++0x03 line.long 0x00 "PRS3,Priority Register 3 Slave" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,Lowest,?..." group.long (0x300+0x10)++0x03 line.long 0x00 "CRS3,Control Register 3" bitfld.long 0x00 31. " RO ,Read only" "Read/Write,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Highest,Lowest" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin/rotating,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,?..." endif if (((per.l(ad:0x40004000+0x10+0x400))&0x80000000)==0x80000000) rgroup.long 0x400++0x03 line.long 0x00 "PRS4,Priority Register 4 Slave" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,Lowest,?..." rgroup.long (0x400+0x10)++0x03 line.long 0x00 "CRS4,Control Register 4" bitfld.long 0x00 31. " RO ,Read only" "Read/write,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Highest,Lowest" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin/rotating,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,?..." else group.long 0x400++0x03 line.long 0x00 "PRS4,Priority Register 4 Slave" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,Lowest,?..." group.long (0x400+0x10)++0x03 line.long 0x00 "CRS4,Control Register 4" bitfld.long 0x00 31. " RO ,Read only" "Read/Write,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Highest,Lowest" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin/rotating,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,?..." endif group.long 0x800++0x03 line.long 0x00 "MGPCR0,Master General Purpose Control Register 0" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0x900++0x03 line.long 0x00 "MGPCR1,Master General Purpose Control Register 1" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xA00++0x03 line.long 0x00 "MGPCR2,Master General Purpose Control Register 2" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xB00++0x03 line.long 0x00 "MGPCR3,Master General Purpose Control Register 3" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." elif cpuis("MK24F*DC12")||cpuis("MK24F*LQ12") group.long 0x0++0x03 line.long 0x00 "PRS0,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,Lowest,?..." bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,Lowest,?..." newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,Lowest,?..." group.long (0x0+0x10)++0x03 line.long 0x00 "CRS0,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." group.long 0x100++0x03 line.long 0x00 "PRS1,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,Lowest,?..." bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,Lowest,?..." newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,Lowest,?..." group.long (0x100+0x10)++0x03 line.long 0x00 "CRS1,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." group.long 0x200++0x03 line.long 0x00 "PRS2,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,Lowest,?..." bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,Lowest,?..." newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,Lowest,?..." group.long (0x200+0x10)++0x03 line.long 0x00 "CRS2,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." group.long 0x300++0x03 line.long 0x00 "PRS3,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,Lowest,?..." bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,Lowest,?..." newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,Lowest,?..." group.long (0x300+0x10)++0x03 line.long 0x00 "CRS3,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." group.long 0x400++0x03 line.long 0x00 "PRS4,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,Lowest,?..." bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,Lowest,?..." newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,Lowest,?..." group.long (0x400+0x10)++0x03 line.long 0x00 "CRS4,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." group.long 0x800++0x03 line.long 0x00 "MGPCR0,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0x900++0x03 line.long 0x00 "MGPCR1,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xA00++0x03 line.long 0x00 "MGPCR2,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xB00++0x03 line.long 0x00 "MGPCR3,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xC00++0x03 line.long 0x00 "MGPCR4,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." elif (cpuis("MK22F*LQ12")&&!cpuis("MK22FX512AVLQ12"))||cpuis("MK21F*MC12")||cpuis("MK21F*MD")||cpuis("MK21F*LQ") if (((per.l(ad:0x40004000+0x10+0x0))&0x80000000)==0x80000000) rgroup.long 0x0++0x03 line.long 0x00 "PRS0,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." rgroup.long (0x0+0x10)++0x03 line.long 0x00 "CRS0,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,,Port M4,Port M5,?..." else group.long 0x0++0x03 line.long 0x00 "PRS0,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." group.long (0x0+0x10)++0x03 line.long 0x00 "CRS0,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,,Port M4,Port M5,?..." endif if (((per.l(ad:0x40004000+0x10+0x100))&0x80000000)==0x80000000) rgroup.long 0x100++0x03 line.long 0x00 "PRS1,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." rgroup.long (0x100+0x10)++0x03 line.long 0x00 "CRS1,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,,Port M4,Port M5,?..." else group.long 0x100++0x03 line.long 0x00 "PRS1,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." group.long (0x100+0x10)++0x03 line.long 0x00 "CRS1,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,,Port M4,Port M5,?..." endif if (((per.l(ad:0x40004000+0x10+0x200))&0x80000000)==0x80000000) rgroup.long 0x200++0x03 line.long 0x00 "PRS2,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." rgroup.long (0x200+0x10)++0x03 line.long 0x00 "CRS2,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,,Port M4,Port M5,?..." else group.long 0x200++0x03 line.long 0x00 "PRS2,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." group.long (0x200+0x10)++0x03 line.long 0x00 "CRS2,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,,Port M4,Port M5,?..." endif if (((per.l(ad:0x40004000+0x10+0x300))&0x80000000)==0x80000000) rgroup.long 0x300++0x03 line.long 0x00 "PRS3,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." rgroup.long (0x300+0x10)++0x03 line.long 0x00 "CRS3,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,,Port M4,Port M5,?..." else group.long 0x300++0x03 line.long 0x00 "PRS3,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." group.long (0x300+0x10)++0x03 line.long 0x00 "CRS3,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,,Port M4,Port M5,?..." endif if (((per.l(ad:0x40004000+0x10+0x400))&0x80000000)==0x80000000) rgroup.long 0x400++0x03 line.long 0x00 "PRS4,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." rgroup.long (0x400+0x10)++0x03 line.long 0x00 "CRS4,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,,Port M4,Port M5,?..." else group.long 0x400++0x03 line.long 0x00 "PRS4,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." group.long (0x400+0x10)++0x03 line.long 0x00 "CRS4,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,,Port M4,Port M5,?..." endif group.long 0x800++0x03 line.long 0x00 "MGPCR0,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0x900++0x03 line.long 0x00 "MGPCR1,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xA00++0x03 line.long 0x00 "MGPCR2,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xB00++0x03 line.long 0x00 "MGPCR3,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xC00++0x03 line.long 0x00 "MGPCR4,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." elif cpuis("MK22FN1M0VLH10")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN1M0AVLH12") if (((per.l(ad:0x40004000+0x10+0x0))&0x80000000)==0x80000000) rgroup.long 0x0++0x03 line.long 0x00 "PRS0,Priority Register Slave" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,Lowest,?..." rgroup.long (0x0+0x10)++0x03 line.long 0x00 "CRS0,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,,Port M4,?..." else group.long 0x0++0x03 line.long 0x00 "PRS0,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,Lowest,?..." group.long (0x0+0x10)++0x03 line.long 0x00 "CRS0,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,,Port M4,?..." endif if (((per.l(ad:0x40004000+0x10+0x100))&0x80000000)==0x80000000) rgroup.long 0x100++0x03 line.long 0x00 "PRS1,Priority Register Slave" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,Lowest,?..." rgroup.long (0x100+0x10)++0x03 line.long 0x00 "CRS1,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,,Port M4,?..." else group.long 0x100++0x03 line.long 0x00 "PRS1,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,Lowest,?..." group.long (0x100+0x10)++0x03 line.long 0x00 "CRS1,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,,Port M4,?..." endif if (((per.l(ad:0x40004000+0x10+0x200))&0x80000000)==0x80000000) rgroup.long 0x200++0x03 line.long 0x00 "PRS2,Priority Register Slave" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,Lowest,?..." rgroup.long (0x200+0x10)++0x03 line.long 0x00 "CRS2,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,,Port M4,?..." else group.long 0x200++0x03 line.long 0x00 "PRS2,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,Lowest,?..." group.long (0x200+0x10)++0x03 line.long 0x00 "CRS2,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,,Port M4,?..." endif if (((per.l(ad:0x40004000+0x10+0x300))&0x80000000)==0x80000000) rgroup.long 0x300++0x03 line.long 0x00 "PRS3,Priority Register Slave" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,Lowest,?..." rgroup.long (0x300+0x10)++0x03 line.long 0x00 "CRS3,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,,Port M4,?..." else group.long 0x300++0x03 line.long 0x00 "PRS3,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,Lowest,?..." group.long (0x300+0x10)++0x03 line.long 0x00 "CRS3,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,,Port M4,?..." endif if (((per.l(ad:0x40004000+0x10+0x400))&0x80000000)==0x80000000) rgroup.long 0x400++0x03 line.long 0x00 "PRS4,Priority Register Slave" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,Lowest,?..." rgroup.long (0x400+0x10)++0x03 line.long 0x00 "CRS4,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,,Port M4,?..." else group.long 0x400++0x03 line.long 0x00 "PRS4,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,Lowest,?..." group.long (0x400+0x10)++0x03 line.long 0x00 "CRS4,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,,Port M4,?..." endif group.long 0x800++0x03 line.long 0x00 "MGPCR0,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0x900++0x03 line.long 0x00 "MGPCR1,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xA00++0x03 line.long 0x00 "MGPCR2,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xC00++0x03 line.long 0x00 "MGPCR4,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." elif cpuis("MK22FN1M0VMC10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLK10")||cpuis("MK21FX512VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK20DX256VLQ10R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DN512ZCAB10R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R") if (((per.l(ad:0x40004000+0x10+0x0))&0x80000000)==0x80000000) rgroup.long 0x0++0x03 line.long 0x00 "PRS0,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." rgroup.long (0x0+0x10)++0x03 line.long 0x00 "CRS0,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read Only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,,Port M4,Port M5,?..." else group.long 0x0++0x03 line.long 0x00 "PRS0,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." group.long (0x0+0x10)++0x03 line.long 0x00 "CRS0,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,,Port M4,Port M5,?..." endif if (((per.l(ad:0x40004000+0x10+0x100))&0x80000000)==0x80000000) rgroup.long 0x100++0x03 line.long 0x00 "PRS1,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." rgroup.long (0x100+0x10)++0x03 line.long 0x00 "CRS1,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read Only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,,Port M4,Port M5,?..." else group.long 0x100++0x03 line.long 0x00 "PRS1,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." group.long (0x100+0x10)++0x03 line.long 0x00 "CRS1,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,,Port M4,Port M5,?..." endif if (((per.l(ad:0x40004000+0x10+0x200))&0x80000000)==0x80000000) rgroup.long 0x200++0x03 line.long 0x00 "PRS2,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." rgroup.long (0x200+0x10)++0x03 line.long 0x00 "CRS2,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read Only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,,Port M4,Port M5,?..." else group.long 0x200++0x03 line.long 0x00 "PRS2,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." group.long (0x200+0x10)++0x03 line.long 0x00 "CRS2,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,,Port M4,Port M5,?..." endif if (((per.l(ad:0x40004000+0x10+0x300))&0x80000000)==0x80000000) rgroup.long 0x300++0x03 line.long 0x00 "PRS3,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." rgroup.long (0x300+0x10)++0x03 line.long 0x00 "CRS3,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read Only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,,Port M4,Port M5,?..." else group.long 0x300++0x03 line.long 0x00 "PRS3,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." group.long (0x300+0x10)++0x03 line.long 0x00 "CRS3,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,,Port M4,Port M5,?..." endif if (((per.l(ad:0x40004000+0x10+0x400))&0x80000000)==0x80000000) rgroup.long 0x400++0x03 line.long 0x00 "PRS4,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." rgroup.long (0x400+0x10)++0x03 line.long 0x00 "CRS4,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read Only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,,Port M4,Port M5,?..." else group.long 0x400++0x03 line.long 0x00 "PRS4,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." group.long (0x400+0x10)++0x03 line.long 0x00 "CRS4,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,,Port M4,Port M5,?..." endif group.long 0x800++0x03 line.long 0x00 "MGPCR0,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0x900++0x03 line.long 0x00 "MGPCR1,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xA00++0x03 line.long 0x00 "MGPCR2,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xC00++0x03 line.long 0x00 "MGPCR4,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xD00++0x03 line.long 0x00 "MGPCR5,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." elif cpuis("MK20FN1M0VLQ12R") if (((per.l(ad:0x40004000+0x10+0x0))&0x80000000)==0x80000000) rgroup.long 0x0++0x03 line.long 0x00 "PRS0,Priority Register Slave" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." rgroup.long (0x0+0x10)++0x03 line.long 0x00 "CRS0,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,,,Port M6,?..." else group.long 0x0++0x03 line.long 0x00 "PRS0,Priority Register Slave" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." group.long (0x0+0x10)++0x03 line.long 0x00 "CRS0,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,,,Port M6,?..." endif if (((per.l(ad:0x40004000+0x10+0x100))&0x80000000)==0x80000000) rgroup.long 0x100++0x03 line.long 0x00 "PRS1,Priority Register Slave" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." rgroup.long (0x100+0x10)++0x03 line.long 0x00 "CRS1,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,,,Port M6,?..." else group.long 0x100++0x03 line.long 0x00 "PRS1,Priority Register Slave" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." group.long (0x100+0x10)++0x03 line.long 0x00 "CRS1,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,,,Port M6,?..." endif if (((per.l(ad:0x40004000+0x10+0x200))&0x80000000)==0x80000000) rgroup.long 0x200++0x03 line.long 0x00 "PRS2,Priority Register Slave" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." rgroup.long (0x200+0x10)++0x03 line.long 0x00 "CRS2,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,,,Port M6,?..." else group.long 0x200++0x03 line.long 0x00 "PRS2,Priority Register Slave" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." group.long (0x200+0x10)++0x03 line.long 0x00 "CRS2,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,,,Port M6,?..." endif if (((per.l(ad:0x40004000+0x10+0x300))&0x80000000)==0x80000000) rgroup.long 0x300++0x03 line.long 0x00 "PRS3,Priority Register Slave" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." rgroup.long (0x300+0x10)++0x03 line.long 0x00 "CRS3,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,,,Port M6,?..." else group.long 0x300++0x03 line.long 0x00 "PRS3,Priority Register Slave" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." group.long (0x300+0x10)++0x03 line.long 0x00 "CRS3,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,,,Port M6,?..." endif if (((per.l(ad:0x40004000+0x10+0x400))&0x80000000)==0x80000000) rgroup.long 0x400++0x03 line.long 0x00 "PRS4,Priority Register Slave" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." rgroup.long (0x400+0x10)++0x03 line.long 0x00 "CRS4,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,,,Port M6,?..." else group.long 0x400++0x03 line.long 0x00 "PRS4,Priority Register Slave" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." group.long (0x400+0x10)++0x03 line.long 0x00 "CRS4,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,,,Port M6,?..." endif group.long 0x800++0x03 line.long 0x00 "MGPCR0,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0x900++0x03 line.long 0x00 "MGPCR1,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xA00++0x03 line.long 0x00 "MGPCR2,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xB00++0x03 line.long 0x00 "MGPCR3,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xE00++0x03 line.long 0x00 "MGPCR6,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*") group.long 0x0++0x03 line.long 0x00 "PRS0,Priority Register 0 Slave" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x0+0x10)++0x03 line.long 0x00 "CRS0,Control Register 0" bitfld.long 0x00 31. " RO ,Read only" "Read/write,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Highest,Lowest" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin/rotating,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" group.long 0x100++0x03 line.long 0x00 "PRS1,Priority Register 1 Slave" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x100+0x10)++0x03 line.long 0x00 "CRS1,Control Register 1" bitfld.long 0x00 31. " RO ,Read only" "Read/write,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Highest,Lowest" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin/rotating,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" group.long 0x200++0x03 line.long 0x00 "PRS2,Priority Register 2 Slave" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x200+0x10)++0x03 line.long 0x00 "CRS2,Control Register 2" bitfld.long 0x00 31. " RO ,Read only" "Read/write,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Highest,Lowest" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin/rotating,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" group.long 0x300++0x03 line.long 0x00 "PRS3,Priority Register 3 Slave" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x300+0x10)++0x03 line.long 0x00 "CRS3,Control Register 3" bitfld.long 0x00 31. " RO ,Read only" "Read/write,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Highest,Lowest" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin/rotating,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" group.long 0x400++0x03 line.long 0x00 "PRS4,Priority Register 4 Slave" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x400+0x10)++0x03 line.long 0x00 "CRS4,Control Register 4" bitfld.long 0x00 31. " RO ,Read only" "Read/write,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Highest,Lowest" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin/rotating,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" group.long 0x500++0x03 line.long 0x00 "PRS5,Priority Register 5 Slave" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x500+0x10)++0x03 line.long 0x00 "CRS5,Control Register 5" bitfld.long 0x00 31. " RO ,Read only" "Read/write,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Highest,Lowest" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin/rotating,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" group.long 0x600++0x03 line.long 0x00 "PRS6,Priority Register 6 Slave" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x600+0x10)++0x03 line.long 0x00 "CRS6,Control Register 6" bitfld.long 0x00 31. " RO ,Read only" "Read/write,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Highest,Lowest" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin/rotating,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" group.long 0x700++0x03 line.long 0x00 "PRS7,Priority Register 7 Slave" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x700+0x10)++0x03 line.long 0x00 "CRS7,Control Register 7" bitfld.long 0x00 31. " RO ,Read only" "Read/write,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Highest,Lowest" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin/rotating,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" group.long 0x800++0x03 line.long 0x00 "MGPCR0,Master General Purpose Control Register 0" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0x900++0x03 line.long 0x00 "MGPCR1,Master General Purpose Control Register 1" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xA00++0x03 line.long 0x00 "MGPCR2,Master General Purpose Control Register 2" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xB00++0x03 line.long 0x00 "MGPCR3,Master General Purpose Control Register 3" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xC00++0x03 line.long 0x00 "MGPCR4,Master General Purpose Control Register 4" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xD00++0x03 line.long 0x00 "MGPCR5,Master General Purpose Control Register 5" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xE00++0x03 line.long 0x00 "MGPCR6,Master General Purpose Control Register 6" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xF00++0x03 line.long 0x00 "MGPCR7,Master General Purpose Control Register 7" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10") if (((per.l(ad:0x40004000+0x10+0x0))&0x80000000)==0x80000000) rgroup.long 0x0++0x03 line.long 0x00 "PRS0,Priority Register Slave" bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" rgroup.long (0x0+0x10)++0x03 line.long 0x00 "CRS0,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else group.long 0x0++0x03 line.long 0x00 "PRS0,Priority Register Slave" bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x0+0x10)++0x03 line.long 0x00 "CRS0,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" endif if (((per.l(ad:0x40004000+0x10+0x100))&0x80000000)==0x80000000) rgroup.long 0x100++0x03 line.long 0x00 "PRS1,Priority Register Slave" bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" rgroup.long (0x100+0x10)++0x03 line.long 0x00 "CRS1,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else group.long 0x100++0x03 line.long 0x00 "PRS1,Priority Register Slave" bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x100+0x10)++0x03 line.long 0x00 "CRS1,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" endif if (((per.l(ad:0x40004000+0x10+0x200))&0x80000000)==0x80000000) rgroup.long 0x200++0x03 line.long 0x00 "PRS2,Priority Register Slave" bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" rgroup.long (0x200+0x10)++0x03 line.long 0x00 "CRS2,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else group.long 0x200++0x03 line.long 0x00 "PRS2,Priority Register Slave" bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x200+0x10)++0x03 line.long 0x00 "CRS2,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" endif if (((per.l(ad:0x40004000+0x10+0x300))&0x80000000)==0x80000000) rgroup.long 0x300++0x03 line.long 0x00 "PRS3,Priority Register Slave" bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" rgroup.long (0x300+0x10)++0x03 line.long 0x00 "CRS3,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else group.long 0x300++0x03 line.long 0x00 "PRS3,Priority Register Slave" bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x300+0x10)++0x03 line.long 0x00 "CRS3,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" endif if (((per.l(ad:0x40004000+0x10+0x400))&0x80000000)==0x80000000) rgroup.long 0x400++0x03 line.long 0x00 "PRS4,Priority Register Slave" bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" rgroup.long (0x400+0x10)++0x03 line.long 0x00 "CRS4,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else group.long 0x400++0x03 line.long 0x00 "PRS4,Priority Register Slave" bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x400+0x10)++0x03 line.long 0x00 "CRS4,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" endif if (((per.l(ad:0x40004000+0x10+0x500))&0x80000000)==0x80000000) rgroup.long 0x500++0x03 line.long 0x00 "PRS5,Priority Register Slave" bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" rgroup.long (0x500+0x10)++0x03 line.long 0x00 "CRS5,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else group.long 0x500++0x03 line.long 0x00 "PRS5,Priority Register Slave" bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x500+0x10)++0x03 line.long 0x00 "CRS5,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" endif group.long 0x800++0x03 line.long 0x00 "MGPCR0,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0x900++0x03 line.long 0x00 "MGPCR1,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xA00++0x03 line.long 0x00 "MGPCR2,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xB00++0x03 line.long 0x00 "MGPCR3,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xC00++0x03 line.long 0x00 "MGPCR4,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xD00++0x03 line.long 0x00 "MGPCR5,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xE00++0x03 line.long 0x00 "MGPCR6,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xF00++0x03 line.long 0x00 "MGPCR7,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." else sif cpuis("MK40D*Z*")||cpuis("MK20D????ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20D????ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0*12R")||cpuis("MK22FX512*12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") if (((per.l(ad:0x40004000+0x10+0x0))&0x80000000)==0x80000000) rgroup.long 0x0++0x03 line.long 0x00 "PRS0,Priority Register Slave" sif !cpuis("KK20DN512ZCAB10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0*12R")&&!cpuis("MK22FX512*12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15") sif !cpuis("KK26FN2M0CAC18R") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" sif !cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0*12R")&&!cpuis("MK22FX512*12R") bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" rgroup.long (0x0+0x10)++0x03 line.long 0x00 "CRS0,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0*12R")||cpuis("MK22FX512*12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif else group.long 0x0++0x03 line.long 0x00 "PRS0,Priority Register Slave" sif !cpuis("KK20DN512ZCAB10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0*12R")&&!cpuis("MK22FX512*12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15") sif !cpuis("KK26FN2M0CAC18R") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" sif !cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0*12R")&&!cpuis("MK22FX512*12R") bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x0+0x10)++0x03 line.long 0x00 "CRS0,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0*12R")||cpuis("MK22FX512*12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif endif else group.long 0x0++0x03 line.long 0x00 "PRS0,Priority Register Slave" sif cpuis("MK?0F*")||cpuis("MK?0D*7")||cpuis("MK?0D*10")||cpuis("MK5?D*10")||cpuis("MK6?*")||cpuis("MK70*")||cpuis("MK30DN512ZVLQ10R") sif cpuis("MK65F*")||cpuis("MK66F*") bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,Lowest,?..." newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,Lowest,?..." elif !cpuis("MK20D*AB10")&&!cpuis("MK21F*")&&!cpuis("MK60D*AB10")&&!cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" elif cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." endif elif cpuis("MK60DN512ZCAB10R") bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" else bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." endif group.long (0x0+0x10)++0x03 line.long 0x00 "CRS0,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" endif sif cpuis("MK40D*Z*")||cpuis("MK20D????ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20D????ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0*12R")||cpuis("MK22FX512*12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") if (((per.l(ad:0x40004000+0x10+0x100))&0x80000000)==0x80000000) rgroup.long 0x100++0x03 line.long 0x00 "PRS1,Priority Register Slave" sif !cpuis("KK20DN512ZCAB10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0*12R")&&!cpuis("MK22FX512*12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15") sif !cpuis("KK26FN2M0CAC18R") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" sif !cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0*12R")&&!cpuis("MK22FX512*12R") bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" rgroup.long (0x100+0x10)++0x03 line.long 0x00 "CRS1,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0*12R")||cpuis("MK22FX512*12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif else group.long 0x100++0x03 line.long 0x00 "PRS1,Priority Register Slave" sif !cpuis("KK20DN512ZCAB10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0*12R")&&!cpuis("MK22FX512*12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15") sif !cpuis("KK26FN2M0CAC18R") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" sif !cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0*12R")&&!cpuis("MK22FX512*12R") bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x100+0x10)++0x03 line.long 0x00 "CRS1,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0*12R")||cpuis("MK22FX512*12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif endif else group.long 0x100++0x03 line.long 0x00 "PRS1,Priority Register Slave" sif cpuis("MK?0F*")||cpuis("MK?0D*7")||cpuis("MK?0D*10")||cpuis("MK5?D*10")||cpuis("MK6?*")||cpuis("MK70*")||cpuis("MK30DN512ZVLQ10R") sif cpuis("MK65F*")||cpuis("MK66F*") bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,Lowest,?..." newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,Lowest,?..." elif !cpuis("MK20D*AB10")&&!cpuis("MK21F*")&&!cpuis("MK60D*AB10")&&!cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" elif cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." endif elif cpuis("MK60DN512ZCAB10R") bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" else bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." endif group.long (0x100+0x10)++0x03 line.long 0x00 "CRS1,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" endif sif cpuis("MK40D*Z*")||cpuis("MK20D????ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20D????ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0*12R")||cpuis("MK22FX512*12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") if (((per.l(ad:0x40004000+0x10+0x200))&0x80000000)==0x80000000) rgroup.long 0x200++0x03 line.long 0x00 "PRS2,Priority Register Slave" sif !cpuis("KK20DN512ZCAB10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0*12R")&&!cpuis("MK22FX512*12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15") sif !cpuis("KK26FN2M0CAC18R") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" sif !cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0*12R")&&!cpuis("MK22FX512*12R") bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" rgroup.long (0x200+0x10)++0x03 line.long 0x00 "CRS2,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0*12R")||cpuis("MK22FX512*12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif else group.long 0x200++0x03 line.long 0x00 "PRS2,Priority Register Slave" sif !cpuis("KK20DN512ZCAB10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0*12R")&&!cpuis("MK22FX512*12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15") sif !cpuis("KK26FN2M0CAC18R") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" sif !cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0*12R")&&!cpuis("MK22FX512*12R") bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x200+0x10)++0x03 line.long 0x00 "CRS2,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0*12R")||cpuis("MK22FX512*12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif endif else group.long 0x200++0x03 line.long 0x00 "PRS2,Priority Register Slave" sif cpuis("MK?0F*")||cpuis("MK?0D*7")||cpuis("MK?0D*10")||cpuis("MK5?D*10")||cpuis("MK6?*")||cpuis("MK70*")||cpuis("MK30DN512ZVLQ10R") sif cpuis("MK65F*")||cpuis("MK66F*") bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,Lowest,?..." newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,Lowest,?..." elif !cpuis("MK20D*AB10")&&!cpuis("MK21F*")&&!cpuis("MK60D*AB10")&&!cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" elif cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." endif elif cpuis("MK60DN512ZCAB10R") bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" else bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." endif group.long (0x200+0x10)++0x03 line.long 0x00 "CRS2,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" endif sif cpuis("MK40D*Z*")||cpuis("MK20D????ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20D????ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0*12R")||cpuis("MK22FX512*12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") if (((per.l(ad:0x40004000+0x10+0x300))&0x80000000)==0x80000000) rgroup.long 0x300++0x03 line.long 0x00 "PRS3,Priority Register Slave" sif !cpuis("KK20DN512ZCAB10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0*12R")&&!cpuis("MK22FX512*12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15") sif !cpuis("KK26FN2M0CAC18R") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" sif !cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0*12R")&&!cpuis("MK22FX512*12R") bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" rgroup.long (0x300+0x10)++0x03 line.long 0x00 "CRS3,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0*12R")||cpuis("MK22FX512*12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif else group.long 0x300++0x03 line.long 0x00 "PRS3,Priority Register Slave" sif !cpuis("KK20DN512ZCAB10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0*12R")&&!cpuis("MK22FX512*12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15") sif !cpuis("KK26FN2M0CAC18R") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" sif !cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0*12R")&&!cpuis("MK22FX512*12R") bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x300+0x10)++0x03 line.long 0x00 "CRS3,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0*12R")||cpuis("MK22FX512*12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif endif else group.long 0x300++0x03 line.long 0x00 "PRS3,Priority Register Slave" sif cpuis("MK?0F*")||cpuis("MK?0D*7")||cpuis("MK?0D*10")||cpuis("MK5?D*10")||cpuis("MK6?*")||cpuis("MK70*")||cpuis("MK30DN512ZVLQ10R") sif cpuis("MK65F*")||cpuis("MK66F*") bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,Lowest,?..." newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,Lowest,?..." elif !cpuis("MK20D*AB10")&&!cpuis("MK21F*")&&!cpuis("MK60D*AB10")&&!cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" elif cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." endif elif cpuis("MK60DN512ZCAB10R") bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" else bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." endif group.long (0x300+0x10)++0x03 line.long 0x00 "CRS3,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" endif sif cpuis("MK40D*Z*")||cpuis("MK20D????ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20D????ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0*12R")||cpuis("MK22FX512*12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") if (((per.l(ad:0x40004000+0x10+0x400))&0x80000000)==0x80000000) rgroup.long 0x400++0x03 line.long 0x00 "PRS4,Priority Register Slave" sif !cpuis("KK20DN512ZCAB10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0*12R")&&!cpuis("MK22FX512*12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15") sif !cpuis("KK26FN2M0CAC18R") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" sif !cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0*12R")&&!cpuis("MK22FX512*12R") bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" rgroup.long (0x400+0x10)++0x03 line.long 0x00 "CRS4,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0*12R")||cpuis("MK22FX512*12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif else group.long 0x400++0x03 line.long 0x00 "PRS4,Priority Register Slave" sif !cpuis("KK20DN512ZCAB10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0*12R")&&!cpuis("MK22FX512*12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15") sif !cpuis("KK26FN2M0CAC18R") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" sif !cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0*12R")&&!cpuis("MK22FX512*12R") bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x400+0x10)++0x03 line.long 0x00 "CRS4,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0*12R")||cpuis("MK22FX512*12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif endif else group.long 0x400++0x03 line.long 0x00 "PRS4,Priority Register Slave" sif cpuis("MK?0F*")||cpuis("MK?0D*7")||cpuis("MK?0D*10")||cpuis("MK5?D*10")||cpuis("MK6?*")||cpuis("MK70*")||cpuis("MK30DN512ZVLQ10R") sif cpuis("MK65F*")||cpuis("MK66F*") bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,Lowest,?..." newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,Lowest,?..." elif !cpuis("MK20D*AB10")&&!cpuis("MK21F*")&&!cpuis("MK60D*AB10")&&!cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" elif cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." endif elif cpuis("MK60DN512ZCAB10R") bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" else bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." endif group.long (0x400+0x10)++0x03 line.long 0x00 "CRS4,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" endif sif cpuis("MK40D*Z*")||cpuis("MK20D????ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20D????ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0*12R")||cpuis("MK22FX512*12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") if (((per.l(ad:0x40004000+0x10+0x500))&0x80000000)==0x80000000) rgroup.long 0x500++0x03 line.long 0x00 "PRS5,Priority Register Slave" sif !cpuis("KK20DN512ZCAB10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0*12R")&&!cpuis("MK22FX512*12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15") sif !cpuis("KK26FN2M0CAC18R") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" sif !cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0*12R")&&!cpuis("MK22FX512*12R") bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" rgroup.long (0x500+0x10)++0x03 line.long 0x00 "CRS5,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0*12R")||cpuis("MK22FX512*12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif else group.long 0x500++0x03 line.long 0x00 "PRS5,Priority Register Slave" sif !cpuis("KK20DN512ZCAB10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0*12R")&&!cpuis("MK22FX512*12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15") sif !cpuis("KK26FN2M0CAC18R") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" sif !cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0*12R")&&!cpuis("MK22FX512*12R") bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x500+0x10)++0x03 line.long 0x00 "CRS5,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0*12R")||cpuis("MK22FX512*12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif endif else group.long 0x500++0x03 line.long 0x00 "PRS5,Priority Register Slave" sif cpuis("MK?0F*")||cpuis("MK?0D*7")||cpuis("MK?0D*10")||cpuis("MK5?D*10")||cpuis("MK6?*")||cpuis("MK70*")||cpuis("MK30DN512ZVLQ10R") sif cpuis("MK65F*")||cpuis("MK66F*") bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,Lowest,?..." newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,Lowest,?..." elif !cpuis("MK20D*AB10")&&!cpuis("MK21F*")&&!cpuis("MK60D*AB10")&&!cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" elif cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." endif elif cpuis("MK60DN512ZCAB10R") bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" else bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." endif group.long (0x500+0x10)++0x03 line.long 0x00 "CRS5,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" endif sif cpuis("MK40D*Z*")||cpuis("MK20D????ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20D????ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0*12R")||cpuis("MK22FX512*12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") if (((per.l(ad:0x40004000+0x10+0x600))&0x80000000)==0x80000000) rgroup.long 0x600++0x03 line.long 0x00 "PRS6,Priority Register Slave" sif !cpuis("KK20DN512ZCAB10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0*12R")&&!cpuis("MK22FX512*12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15") sif !cpuis("KK26FN2M0CAC18R") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" sif !cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0*12R")&&!cpuis("MK22FX512*12R") bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" rgroup.long (0x600+0x10)++0x03 line.long 0x00 "CRS6,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0*12R")||cpuis("MK22FX512*12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif else group.long 0x600++0x03 line.long 0x00 "PRS6,Priority Register Slave" sif !cpuis("KK20DN512ZCAB10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0*12R")&&!cpuis("MK22FX512*12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15") sif !cpuis("KK26FN2M0CAC18R") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" sif !cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0*12R")&&!cpuis("MK22FX512*12R") bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x600+0x10)++0x03 line.long 0x00 "CRS6,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0*12R")||cpuis("MK22FX512*12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif endif else group.long 0x600++0x03 line.long 0x00 "PRS6,Priority Register Slave" sif cpuis("MK?0F*")||cpuis("MK?0D*7")||cpuis("MK?0D*10")||cpuis("MK5?D*10")||cpuis("MK6?*")||cpuis("MK70*")||cpuis("MK30DN512ZVLQ10R") sif cpuis("MK65F*")||cpuis("MK66F*") bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,Lowest,?..." newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,Lowest,?..." elif !cpuis("MK20D*AB10")&&!cpuis("MK21F*")&&!cpuis("MK60D*AB10")&&!cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" elif cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." endif elif cpuis("MK60DN512ZCAB10R") bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" else bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." endif group.long (0x600+0x10)++0x03 line.long 0x00 "CRS6,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" endif sif cpuis("MK40D*Z*")||cpuis("MK20D????ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20D????ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0*12R")||cpuis("MK22FX512*12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") if (((per.l(ad:0x40004000+0x10+0x700))&0x80000000)==0x80000000) rgroup.long 0x700++0x03 line.long 0x00 "PRS7,Priority Register Slave" sif !cpuis("KK20DN512ZCAB10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0*12R")&&!cpuis("MK22FX512*12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15") sif !cpuis("KK26FN2M0CAC18R") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" sif !cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0*12R")&&!cpuis("MK22FX512*12R") bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" rgroup.long (0x700+0x10)++0x03 line.long 0x00 "CRS7,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0*12R")||cpuis("MK22FX512*12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif else group.long 0x700++0x03 line.long 0x00 "PRS7,Priority Register Slave" sif !cpuis("KK20DN512ZCAB10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0*12R")&&!cpuis("MK22FX512*12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15") sif !cpuis("KK26FN2M0CAC18R") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" sif !cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0*12R")&&!cpuis("MK22FX512*12R") bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x700+0x10)++0x03 line.long 0x00 "CRS7,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0*12R")||cpuis("MK22FX512*12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif endif else group.long 0x700++0x03 line.long 0x00 "PRS7,Priority Register Slave" sif cpuis("MK?0F*")||cpuis("MK?0D*7")||cpuis("MK?0D*10")||cpuis("MK5?D*10")||cpuis("MK6?*")||cpuis("MK70*")||cpuis("MK30DN512ZVLQ10R") sif cpuis("MK65F*")||cpuis("MK66F*") bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,Lowest,?..." newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,Lowest,?..." elif !cpuis("MK20D*AB10")&&!cpuis("MK21F*")&&!cpuis("MK60D*AB10")&&!cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" elif cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." endif elif cpuis("MK60DN512ZCAB10R") bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" else bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." endif group.long (0x700+0x10)++0x03 line.long 0x00 "CRS7,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" endif group.long 0x800++0x03 line.long 0x00 "MGPCR0,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0x900++0x03 line.long 0x00 "MGPCR1,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xA00++0x03 line.long 0x00 "MGPCR2,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xB00++0x03 line.long 0x00 "MGPCR3,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xC00++0x03 line.long 0x00 "MGPCR4,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xD00++0x03 line.long 0x00 "MGPCR5,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xE00++0x03 line.long 0x00 "MGPCR6,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xF00++0x03 line.long 0x00 "MGPCR7,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." endif width 0x0B tree.end tree.open "AIPS-Lite (Peripheral Bridge)" tree "AIPS_0" base ad:0x40000000 width 7. group.long 0x00++0x03 line.long 0x00 "MPRA,Master Privilege Register A" bitfld.long 0x00 30. " MTR0 ,Master trusted for read" "Not trusted,Trusted" bitfld.long 0x00 29. " MTW0 ,Master trusted for writes" "Not trusted,Trusted" bitfld.long 0x00 28. " MPL0 ,Master privilege level" "Not forced,Forced" newline bitfld.long 0x00 26. " MTR1 ,Master trusted for read" "Not trusted,Trusted" bitfld.long 0x00 25. " MTW1 ,Master trusted for writes" "Not trusted,Trusted" bitfld.long 0x00 24. " MPL1 ,Master privilege level" "Not forced,Forced" newline bitfld.long 0x00 22. " MTR2 ,Master trusted for read" "Not trusted,Trusted" bitfld.long 0x00 21. " MTW2 ,Master trusted for writes" "Not trusted,Trusted" bitfld.long 0x00 20. " MPL2 ,Master privilege level" "Not forced,Forced" newline bitfld.long 0x00 18. " MTR3 ,Master trusted for read" "Not trusted,Trusted" bitfld.long 0x00 17. " MTW3 ,Master trusted for writes" "Not trusted,Trusted" bitfld.long 0x00 16. " MPL3 ,Master privilege level" "Not forced,Forced" newline bitfld.long 0x00 14. " MTR4 ,Master trusted for read" "Not trusted,Trusted" bitfld.long 0x00 13. " MTW4 ,Master trusted for writes" "Not trusted,Trusted" bitfld.long 0x00 12. " MPL4 ,Master privilege level" "Not forced,Forced" group.long 0x20++0x03 line.long 0x00 "PACRA,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 29. " WP0 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 25. " WP1 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 21. " WP2 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 17. " WP3 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 13. " WP4 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 9. " WP5 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 5. " WP6 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 1. " WP7 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Disabled,Enabled" group.long 0x24++0x03 line.long 0x00 "PACRB,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 29. " WP0 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 25. " WP1 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 21. " WP2 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 17. " WP3 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 13. " WP4 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 9. " WP5 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 5. " WP6 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 1. " WP7 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Disabled,Enabled" group.long 0x28++0x03 line.long 0x00 "PACRC,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 29. " WP0 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 25. " WP1 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 21. " WP2 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 17. " WP3 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 13. " WP4 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 9. " WP5 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 5. " WP6 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 1. " WP7 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Disabled,Enabled" group.long 0x2C++0x03 line.long 0x00 "PACRD,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 29. " WP0 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 25. " WP1 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 21. " WP2 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 17. " WP3 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 13. " WP4 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 9. " WP5 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 5. " WP6 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 1. " WP7 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Disabled,Enabled" group.long 0x40++0x03 line.long 0x00 "PACRE,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 29. " WP0 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 25. " WP1 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 21. " WP2 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 17. " WP3 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 13. " WP4 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 9. " WP5 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 5. " WP6 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 1. " WP7 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Disabled,Enabled" group.long 0x44++0x03 line.long 0x00 "PACRF,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 29. " WP0 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 25. " WP1 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 21. " WP2 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 17. " WP3 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 13. " WP4 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 9. " WP5 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 5. " WP6 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 1. " WP7 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Disabled,Enabled" group.long 0x48++0x03 line.long 0x00 "PACRG,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 29. " WP0 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 25. " WP1 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 21. " WP2 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 17. " WP3 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 13. " WP4 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 9. " WP5 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 5. " WP6 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 1. " WP7 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Disabled,Enabled" group.long 0x4C++0x03 line.long 0x00 "PACRH,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 29. " WP0 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 25. " WP1 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 21. " WP2 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 17. " WP3 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 13. " WP4 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 9. " WP5 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 5. " WP6 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 1. " WP7 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Disabled,Enabled" group.long 0x50++0x03 line.long 0x00 "PACRI,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 29. " WP0 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 25. " WP1 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 21. " WP2 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 17. " WP3 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 13. " WP4 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 9. " WP5 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 5. " WP6 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 1. " WP7 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Disabled,Enabled" group.long 0x54++0x03 line.long 0x00 "PACRJ,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 29. " WP0 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 25. " WP1 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 21. " WP2 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 17. " WP3 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 13. " WP4 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 9. " WP5 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 5. " WP6 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 1. " WP7 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Disabled,Enabled" group.long 0x58++0x03 line.long 0x00 "PACRK,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 29. " WP0 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 25. " WP1 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 21. " WP2 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 17. " WP3 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 13. " WP4 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 9. " WP5 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 5. " WP6 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 1. " WP7 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Disabled,Enabled" group.long 0x5C++0x03 line.long 0x00 "PACRL,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 29. " WP0 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 25. " WP1 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 21. " WP2 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 17. " WP3 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 13. " WP4 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 9. " WP5 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 5. " WP6 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 1. " WP7 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Disabled,Enabled" group.long 0x60++0x03 line.long 0x00 "PACRM,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 29. " WP0 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 25. " WP1 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 21. " WP2 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 17. " WP3 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 13. " WP4 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 9. " WP5 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 5. " WP6 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 1. " WP7 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Disabled,Enabled" group.long 0x64++0x03 line.long 0x00 "PACRN,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 29. " WP0 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 25. " WP1 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 21. " WP2 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 17. " WP3 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 13. " WP4 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 9. " WP5 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 5. " WP6 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 1. " WP7 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Disabled,Enabled" group.long 0x68++0x03 line.long 0x00 "PACRO,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 29. " WP0 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 25. " WP1 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 21. " WP2 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 17. " WP3 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 13. " WP4 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 9. " WP5 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 5. " WP6 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 1. " WP7 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Disabled,Enabled" group.long 0x6C++0x03 line.long 0x00 "PACRP,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 29. " WP0 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 25. " WP1 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 21. " WP2 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 17. " WP3 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 13. " WP4 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 9. " WP5 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 5. " WP6 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 1. " WP7 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Disabled,Enabled" width 0x0B tree.end tree "AIPS_1" base ad:0x40080000 width 7. group.long 0x00++0x03 line.long 0x00 "MPRA,Master Privilege Register A" bitfld.long 0x00 30. " MTR0 ,Master trusted for read" "Not trusted,Trusted" bitfld.long 0x00 29. " MTW0 ,Master trusted for writes" "Not trusted,Trusted" bitfld.long 0x00 28. " MPL0 ,Master privilege level" "Not forced,Forced" newline bitfld.long 0x00 26. " MTR1 ,Master trusted for read" "Not trusted,Trusted" bitfld.long 0x00 25. " MTW1 ,Master trusted for writes" "Not trusted,Trusted" bitfld.long 0x00 24. " MPL1 ,Master privilege level" "Not forced,Forced" newline bitfld.long 0x00 22. " MTR2 ,Master trusted for read" "Not trusted,Trusted" bitfld.long 0x00 21. " MTW2 ,Master trusted for writes" "Not trusted,Trusted" bitfld.long 0x00 20. " MPL2 ,Master privilege level" "Not forced,Forced" newline bitfld.long 0x00 18. " MTR3 ,Master trusted for read" "Not trusted,Trusted" bitfld.long 0x00 17. " MTW3 ,Master trusted for writes" "Not trusted,Trusted" bitfld.long 0x00 16. " MPL3 ,Master privilege level" "Not forced,Forced" newline bitfld.long 0x00 14. " MTR4 ,Master trusted for read" "Not trusted,Trusted" bitfld.long 0x00 13. " MTW4 ,Master trusted for writes" "Not trusted,Trusted" bitfld.long 0x00 12. " MPL4 ,Master privilege level" "Not forced,Forced" group.long 0x20++0x03 line.long 0x00 "PACRA,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 29. " WP0 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 25. " WP1 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 21. " WP2 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 17. " WP3 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 13. " WP4 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 9. " WP5 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 5. " WP6 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 1. " WP7 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Disabled,Enabled" group.long 0x24++0x03 line.long 0x00 "PACRB,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 29. " WP0 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 25. " WP1 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 21. " WP2 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 17. " WP3 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 13. " WP4 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 9. " WP5 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 5. " WP6 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 1. " WP7 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Disabled,Enabled" group.long 0x28++0x03 line.long 0x00 "PACRC,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 29. " WP0 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 25. " WP1 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 21. " WP2 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 17. " WP3 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 13. " WP4 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 9. " WP5 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 5. " WP6 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 1. " WP7 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Disabled,Enabled" group.long 0x2C++0x03 line.long 0x00 "PACRD,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 29. " WP0 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 25. " WP1 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 21. " WP2 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 17. " WP3 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 13. " WP4 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 9. " WP5 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 5. " WP6 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 1. " WP7 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Disabled,Enabled" group.long 0x40++0x03 line.long 0x00 "PACRE,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 29. " WP0 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 25. " WP1 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 21. " WP2 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 17. " WP3 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 13. " WP4 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 9. " WP5 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 5. " WP6 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 1. " WP7 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Disabled,Enabled" group.long 0x44++0x03 line.long 0x00 "PACRF,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 29. " WP0 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 25. " WP1 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 21. " WP2 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 17. " WP3 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 13. " WP4 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 9. " WP5 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 5. " WP6 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 1. " WP7 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Disabled,Enabled" group.long 0x48++0x03 line.long 0x00 "PACRG,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 29. " WP0 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 25. " WP1 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 21. " WP2 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 17. " WP3 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 13. " WP4 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 9. " WP5 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 5. " WP6 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 1. " WP7 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Disabled,Enabled" group.long 0x4C++0x03 line.long 0x00 "PACRH,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 29. " WP0 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 25. " WP1 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 21. " WP2 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 17. " WP3 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 13. " WP4 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 9. " WP5 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 5. " WP6 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 1. " WP7 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Disabled,Enabled" group.long 0x50++0x03 line.long 0x00 "PACRI,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 29. " WP0 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 25. " WP1 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 21. " WP2 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 17. " WP3 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 13. " WP4 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 9. " WP5 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 5. " WP6 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 1. " WP7 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Disabled,Enabled" group.long 0x54++0x03 line.long 0x00 "PACRJ,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 29. " WP0 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 25. " WP1 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 21. " WP2 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 17. " WP3 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 13. " WP4 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 9. " WP5 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 5. " WP6 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 1. " WP7 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Disabled,Enabled" group.long 0x58++0x03 line.long 0x00 "PACRK,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 29. " WP0 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 25. " WP1 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 21. " WP2 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 17. " WP3 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 13. " WP4 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 9. " WP5 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 5. " WP6 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 1. " WP7 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Disabled,Enabled" group.long 0x5C++0x03 line.long 0x00 "PACRL,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 29. " WP0 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 25. " WP1 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 21. " WP2 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 17. " WP3 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 13. " WP4 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 9. " WP5 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 5. " WP6 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 1. " WP7 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Disabled,Enabled" group.long 0x60++0x03 line.long 0x00 "PACRM,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 29. " WP0 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 25. " WP1 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 21. " WP2 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 17. " WP3 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 13. " WP4 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 9. " WP5 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 5. " WP6 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 1. " WP7 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Disabled,Enabled" group.long 0x64++0x03 line.long 0x00 "PACRN,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 29. " WP0 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 25. " WP1 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 21. " WP2 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 17. " WP3 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 13. " WP4 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 9. " WP5 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 5. " WP6 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 1. " WP7 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Disabled,Enabled" group.long 0x68++0x03 line.long 0x00 "PACRO,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 29. " WP0 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 25. " WP1 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 21. " WP2 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 17. " WP3 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 13. " WP4 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 9. " WP5 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 5. " WP6 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 1. " WP7 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Disabled,Enabled" group.long 0x6C++0x03 line.long 0x00 "PACRP,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 29. " WP0 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 25. " WP1 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 21. " WP2 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 17. " WP3 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 13. " WP4 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 9. " WP5 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 5. " WP6 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Disabled,Enabled" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Disabled,Enabled" bitfld.long 0x00 1. " WP7 ,Write protect" "Disabled,Enabled" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Disabled,Enabled" width 0x0B tree.end tree.end tree "MPU (Memory Protection Unit)" base ad:0x4000D000 width 13. group.long 0x00++0x03 line.long 0x00 "CESR,Control/Error Status Register" eventfld.long 0x00 31. " SPERR[0] ,Slave port 0 error" "No error,Error" eventfld.long 0x00 30. " SPERR[1] ,Slave port 1 error" "No error,Error" newline eventfld.long 0x00 29. " SPERR[2] ,Slave port 2 error" "No error,Error" eventfld.long 0x00 28. " SPERR[3] ,Slave port 3 error" "No error,Error" newline sif !cpuis("MK51DN512ZCLL10")&&!cpuis("MK51DN512ZCMC10")&&!cpuis("MK51DX256ZCMC10") eventfld.long 0x00 27. " SPERR[4] ,Slave port 4 error" "No error,Error" newline endif sif cpuis("MK??F*")||cpuis("KK28FN2M0CAU15R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK20DN512*AB10R")&&!cpuis("MK21F*")&&!cpuis("MK22FX512*")&&!cpuis("MK24FN*")&&!cpuis("MK26FN*")&&!cpuis("MK10F*")&&!cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK65F*")&&!cpuis("MK66F*")&&!cpuis("MK84FN2M0CAU15R")&&!cpuis("MK8?FN256V*")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60FN1M0VLQ15")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK65FN2M0CAC18R") eventfld.long 0x00 26. " SPERR[5] ,Slave port 5 error" "No error,Error" eventfld.long 0x00 25. " SPERR[6] ,Slave port 6 error" "No error,Error" newline sif !cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15") eventfld.long 0x00 24. " SPERR[7] ,Slave port 7 error" "No error,Error" newline endif elif cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") eventfld.long 0x00 26. " SPERR[5] ,Slave port 5 error" "No error,Error" sif !cpuis("MK63FN1M0VLQ12R") eventfld.long 0x00 25. " SPERR[6] ,Slave port 6 error" "No error,Error" newline eventfld.long 0x00 24. " SPERR[7] ,Slave port 7 error" "No error,Error" endif endif endif rbitfld.long 0x00 16.--19. " HRL ,Hardware revision level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif cpuis("MK70F*")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") newline rbitfld.long 0x00 12.--15. " NSP ,Number of slave ports" "0,1,2,3,4,5,6,7,?..." elif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12*")||cpuis("MK60DN512ZCAB10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60FN1M0VLQ15") newline rbitfld.long 0x00 12.--15. " NSP ,Number of slave ports" "0,1,2,3,4,?..." elif cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10") newline rbitfld.long 0x00 12.--15. " NSP ,Number of slave ports" "0,1,2,3,?..." elif cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18*")||cpuis("MK66FN2M0VLQ18*") rbitfld.long 0x00 12.--15. " NSP ,Number of slave ports" "0,1,2,3,4,Three MPU slave ports,?..." else newline rbitfld.long 0x00 12.--15. " NSP ,Number of slave ports" "0,1,2,3,4,5,?..." endif newline rbitfld.long 0x00 8.--11. " NRGD ,Number of region descriptors" "8,12,16,?..." bitfld.long 0x00 0. " VLD ,Valid (global enable/disable for the MPU)" "Disabled,Enabled" newline sif cpuis("MK70*") rgroup.long 0x10++0x07 line.long 0x00 "EAR0,Error Address Register" line.long 0x04 "EDR0,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." rgroup.long 0x18++0x07 line.long 0x00 "EAR1,Error Address Register" line.long 0x04 "EDR1,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." rgroup.long 0x20++0x07 line.long 0x00 "EAR2,Error Address Register" line.long 0x04 "EDR2,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." rgroup.long 0x28++0x07 line.long 0x00 "EAR3,Error Address Register" line.long 0x04 "EDR3,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." rgroup.long 0x30++0x07 line.long 0x00 "EAR4,Error Address Register" line.long 0x04 "EDR4,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." rgroup.long 0x38++0x07 line.long 0x00 "EAR5,Error Address Register" line.long 0x04 "EDR5,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." rgroup.long 0x40++0x07 line.long 0x00 "EAR6,Error Address Register" line.long 0x04 "EDR6,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." rgroup.long 0x48++0x07 line.long 0x00 "EAR7,Error Address Register" line.long 0x04 "EDR7,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." elif cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10") rgroup.long 0x10++0x07 line.long 0x00 "EAR0,Error Address Register" line.long 0x04 "EDR0,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" rgroup.long 0x18++0x07 line.long 0x00 "EAR1,Error Address Register" line.long 0x04 "EDR1,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" rgroup.long 0x20++0x07 line.long 0x00 "EAR2,Error Address Register" line.long 0x04 "EDR2,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" rgroup.long 0x28++0x07 line.long 0x00 "EAR3,Error Address Register" line.long 0x04 "EDR3,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" elif cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") rgroup.long 0x10++0x07 line.long 0x00 "EAR0,Error Address Register" line.long 0x04 "EDR0,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" rgroup.long 0x18++0x07 line.long 0x00 "EAR1,Error Address Register" line.long 0x04 "EDR1,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" rgroup.long 0x20++0x07 line.long 0x00 "EAR2,Error Address Register" line.long 0x04 "EDR2,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" rgroup.long 0x28++0x07 line.long 0x00 "EAR3,Error Address Register" line.long 0x04 "EDR3,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" rgroup.long 0x30++0x07 line.long 0x00 "EAR4,Error Address Register" line.long 0x04 "EDR4,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" rgroup.long 0x38++0x07 line.long 0x00 "EAR5,Error Address Register" line.long 0x04 "EDR5,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" rgroup.long 0x40++0x07 line.long 0x00 "EAR6,Error Address Register" line.long 0x04 "EDR6,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" elif cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") rgroup.long 0x10++0x07 line.long 0x00 "EAR0,Error Address Register" line.long 0x04 "EDR0,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" sif !cpuis("MK65FN2M0VMI18R") hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" endif bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" rgroup.long 0x18++0x07 line.long 0x00 "EAR1,Error Address Register" line.long 0x04 "EDR1,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" sif !cpuis("MK65FN2M0VMI18R") hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" endif bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" rgroup.long 0x20++0x07 line.long 0x00 "EAR2,Error Address Register" line.long 0x04 "EDR2,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" sif !cpuis("MK65FN2M0VMI18R") hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" endif bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" rgroup.long 0x28++0x07 line.long 0x00 "EAR3,Error Address Register" line.long 0x04 "EDR3,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" sif !cpuis("MK65FN2M0VMI18R") hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" endif bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" rgroup.long 0x30++0x07 line.long 0x00 "EAR4,Error Address Register" line.long 0x04 "EDR4,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" sif !cpuis("MK65FN2M0VMI18R") hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" endif bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" rgroup.long 0x38++0x07 line.long 0x00 "EAR5,Error Address Register" line.long 0x04 "EDR5,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" sif !cpuis("MK65FN2M0VMI18R") hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" endif bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" else rgroup.long 0x10++0x07 line.long 0x00 "EAR0,Error Address Register" line.long 0x04 "EDR0,Error Detail Register" sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK60FN1M0VLQ15") hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" sif !cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("KK60FN1M0VLQ15")&&!cpuis("KK60DN512ZCAB10R") hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" endif newline bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline else hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline endif bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" rgroup.long 0x18++0x07 line.long 0x00 "EAR1,Error Address Register" line.long 0x04 "EDR1,Error Detail Register" sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK60FN1M0VLQ15") hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" sif !cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("KK60FN1M0VLQ15")&&!cpuis("KK60DN512ZCAB10R") hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" endif newline bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline else hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline endif bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" rgroup.long 0x20++0x07 line.long 0x00 "EAR2,Error Address Register" line.long 0x04 "EDR2,Error Detail Register" sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK60FN1M0VLQ15") hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" sif !cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("KK60FN1M0VLQ15")&&!cpuis("KK60DN512ZCAB10R") hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" endif newline bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline else hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline endif bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" rgroup.long 0x28++0x07 line.long 0x00 "EAR3,Error Address Register" line.long 0x04 "EDR3,Error Detail Register" sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK60FN1M0VLQ15") hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" sif !cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("KK60FN1M0VLQ15")&&!cpuis("KK60DN512ZCAB10R") hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" endif newline bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline else hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline endif bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" rgroup.long 0x30++0x07 line.long 0x00 "EAR4,Error Address Register" line.long 0x04 "EDR4,Error Detail Register" sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK60FN1M0VLQ15") hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" sif !cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("KK60FN1M0VLQ15")&&!cpuis("KK60DN512ZCAB10R") hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" endif newline bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline else hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline endif bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" endif newline group.long 0x400++0x0F line.long 0x00 "RGD0_WORD0,Region Descriptor 0 Word 0" hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address" line.long 0x04 "RGD0_WORD1,Region Descriptor 0 Word 1" hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address" line.long 0x08 "RGD0_WORD2,Region Descriptor 0 Word 2" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FX512VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x08 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x08 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x08 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x08 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x08 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x08 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 17. " M2PE ,DMA process identifier enable" "Disabled,Enabled" bitfld.long 0x08 15.--16. " M2SM ,DMA supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,DMA user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,DMA user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,DMA user mode execute access control" "No access,Access" newline else bitfld.long 0x08 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x08 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x08 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif line.long 0x0C "RGD0_WORD3,Region Descriptor 0 Word 3" sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") hexmask.long.byte 0x0C 24.--31. 1. " PID ,Process identifier" hexmask.long.byte 0x0C 16.--23. 1. " PIDMASK ,Process identifier mask" newline endif bitfld.long 0x0C 0. " VLD ,Signals the region descriptor" "Not valid,Valid" newline group.long 0x410++0x0F line.long 0x00 "RGD1_WORD0,Region Descriptor 1 Word 0" hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address" line.long 0x04 "RGD1_WORD1,Region Descriptor 1 Word 1" hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address" line.long 0x08 "RGD1_WORD2,Region Descriptor 1 Word 2" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FX512VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x08 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x08 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x08 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x08 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x08 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x08 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 17. " M2PE ,DMA process identifier enable" "Disabled,Enabled" bitfld.long 0x08 15.--16. " M2SM ,DMA supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,DMA user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,DMA user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,DMA user mode execute access control" "No access,Access" newline else bitfld.long 0x08 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x08 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x08 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif line.long 0x0C "RGD1_WORD3,Region Descriptor 1 Word 3" sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") hexmask.long.byte 0x0C 24.--31. 1. " PID ,Process identifier" hexmask.long.byte 0x0C 16.--23. 1. " PIDMASK ,Process identifier mask" newline endif bitfld.long 0x0C 0. " VLD ,Signals the region descriptor" "Not valid,Valid" newline group.long 0x420++0x0F line.long 0x00 "RGD2_WORD0,Region Descriptor 2 Word 0" hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address" line.long 0x04 "RGD2_WORD1,Region Descriptor 2 Word 1" hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address" line.long 0x08 "RGD2_WORD2,Region Descriptor 2 Word 2" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FX512VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x08 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x08 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x08 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x08 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x08 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x08 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 17. " M2PE ,DMA process identifier enable" "Disabled,Enabled" bitfld.long 0x08 15.--16. " M2SM ,DMA supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,DMA user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,DMA user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,DMA user mode execute access control" "No access,Access" newline else bitfld.long 0x08 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x08 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x08 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif line.long 0x0C "RGD2_WORD3,Region Descriptor 2 Word 3" sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") hexmask.long.byte 0x0C 24.--31. 1. " PID ,Process identifier" hexmask.long.byte 0x0C 16.--23. 1. " PIDMASK ,Process identifier mask" newline endif bitfld.long 0x0C 0. " VLD ,Signals the region descriptor" "Not valid,Valid" newline group.long 0x430++0x0F line.long 0x00 "RGD3_WORD0,Region Descriptor 3 Word 0" hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address" line.long 0x04 "RGD3_WORD1,Region Descriptor 3 Word 1" hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address" line.long 0x08 "RGD3_WORD2,Region Descriptor 3 Word 2" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FX512VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x08 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x08 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x08 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x08 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x08 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x08 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 17. " M2PE ,DMA process identifier enable" "Disabled,Enabled" bitfld.long 0x08 15.--16. " M2SM ,DMA supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,DMA user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,DMA user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,DMA user mode execute access control" "No access,Access" newline else bitfld.long 0x08 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x08 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x08 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif line.long 0x0C "RGD3_WORD3,Region Descriptor 3 Word 3" sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") hexmask.long.byte 0x0C 24.--31. 1. " PID ,Process identifier" hexmask.long.byte 0x0C 16.--23. 1. " PIDMASK ,Process identifier mask" newline endif bitfld.long 0x0C 0. " VLD ,Signals the region descriptor" "Not valid,Valid" newline group.long 0x440++0x0F line.long 0x00 "RGD4_WORD0,Region Descriptor 4 Word 0" hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address" line.long 0x04 "RGD4_WORD1,Region Descriptor 4 Word 1" hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address" line.long 0x08 "RGD4_WORD2,Region Descriptor 4 Word 2" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FX512VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x08 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x08 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x08 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x08 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x08 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x08 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 17. " M2PE ,DMA process identifier enable" "Disabled,Enabled" bitfld.long 0x08 15.--16. " M2SM ,DMA supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,DMA user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,DMA user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,DMA user mode execute access control" "No access,Access" newline else bitfld.long 0x08 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x08 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x08 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif line.long 0x0C "RGD4_WORD3,Region Descriptor 4 Word 3" sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") hexmask.long.byte 0x0C 24.--31. 1. " PID ,Process identifier" hexmask.long.byte 0x0C 16.--23. 1. " PIDMASK ,Process identifier mask" newline endif bitfld.long 0x0C 0. " VLD ,Signals the region descriptor" "Not valid,Valid" newline group.long 0x450++0x0F line.long 0x00 "RGD5_WORD0,Region Descriptor 5 Word 0" hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address" line.long 0x04 "RGD5_WORD1,Region Descriptor 5 Word 1" hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address" line.long 0x08 "RGD5_WORD2,Region Descriptor 5 Word 2" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FX512VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x08 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x08 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x08 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x08 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x08 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x08 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 17. " M2PE ,DMA process identifier enable" "Disabled,Enabled" bitfld.long 0x08 15.--16. " M2SM ,DMA supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,DMA user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,DMA user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,DMA user mode execute access control" "No access,Access" newline else bitfld.long 0x08 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x08 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x08 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif line.long 0x0C "RGD5_WORD3,Region Descriptor 5 Word 3" sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") hexmask.long.byte 0x0C 24.--31. 1. " PID ,Process identifier" hexmask.long.byte 0x0C 16.--23. 1. " PIDMASK ,Process identifier mask" newline endif bitfld.long 0x0C 0. " VLD ,Signals the region descriptor" "Not valid,Valid" newline group.long 0x460++0x0F line.long 0x00 "RGD6_WORD0,Region Descriptor 6 Word 0" hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address" line.long 0x04 "RGD6_WORD1,Region Descriptor 6 Word 1" hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address" line.long 0x08 "RGD6_WORD2,Region Descriptor 6 Word 2" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FX512VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x08 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x08 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x08 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x08 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x08 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x08 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 17. " M2PE ,DMA process identifier enable" "Disabled,Enabled" bitfld.long 0x08 15.--16. " M2SM ,DMA supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,DMA user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,DMA user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,DMA user mode execute access control" "No access,Access" newline else bitfld.long 0x08 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x08 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x08 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif line.long 0x0C "RGD6_WORD3,Region Descriptor 6 Word 3" sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") hexmask.long.byte 0x0C 24.--31. 1. " PID ,Process identifier" hexmask.long.byte 0x0C 16.--23. 1. " PIDMASK ,Process identifier mask" newline endif bitfld.long 0x0C 0. " VLD ,Signals the region descriptor" "Not valid,Valid" newline group.long 0x470++0x0F line.long 0x00 "RGD7_WORD0,Region Descriptor 7 Word 0" hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address" line.long 0x04 "RGD7_WORD1,Region Descriptor 7 Word 1" hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address" line.long 0x08 "RGD7_WORD2,Region Descriptor 7 Word 2" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FX512VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x08 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x08 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x08 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x08 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x08 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x08 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 17. " M2PE ,DMA process identifier enable" "Disabled,Enabled" bitfld.long 0x08 15.--16. " M2SM ,DMA supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,DMA user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,DMA user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,DMA user mode execute access control" "No access,Access" newline else bitfld.long 0x08 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x08 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x08 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif line.long 0x0C "RGD7_WORD3,Region Descriptor 7 Word 3" sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") hexmask.long.byte 0x0C 24.--31. 1. " PID ,Process identifier" hexmask.long.byte 0x0C 16.--23. 1. " PIDMASK ,Process identifier mask" newline endif bitfld.long 0x0C 0. " VLD ,Signals the region descriptor" "Not valid,Valid" newline group.long 0x480++0x0F line.long 0x00 "RGD8_WORD0,Region Descriptor 8 Word 0" hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address" line.long 0x04 "RGD8_WORD1,Region Descriptor 8 Word 1" hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address" line.long 0x08 "RGD8_WORD2,Region Descriptor 8 Word 2" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FX512VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x08 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x08 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x08 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x08 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x08 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x08 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 17. " M2PE ,DMA process identifier enable" "Disabled,Enabled" bitfld.long 0x08 15.--16. " M2SM ,DMA supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,DMA user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,DMA user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,DMA user mode execute access control" "No access,Access" newline else bitfld.long 0x08 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x08 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x08 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif line.long 0x0C "RGD8_WORD3,Region Descriptor 8 Word 3" sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") hexmask.long.byte 0x0C 24.--31. 1. " PID ,Process identifier" hexmask.long.byte 0x0C 16.--23. 1. " PIDMASK ,Process identifier mask" newline endif bitfld.long 0x0C 0. " VLD ,Signals the region descriptor" "Not valid,Valid" newline group.long 0x490++0x0F line.long 0x00 "RGD9_WORD0,Region Descriptor 9 Word 0" hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address" line.long 0x04 "RGD9_WORD1,Region Descriptor 9 Word 1" hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address" line.long 0x08 "RGD9_WORD2,Region Descriptor 9 Word 2" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FX512VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x08 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x08 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x08 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x08 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x08 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x08 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 17. " M2PE ,DMA process identifier enable" "Disabled,Enabled" bitfld.long 0x08 15.--16. " M2SM ,DMA supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,DMA user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,DMA user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,DMA user mode execute access control" "No access,Access" newline else bitfld.long 0x08 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x08 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x08 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif line.long 0x0C "RGD9_WORD3,Region Descriptor 9 Word 3" sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") hexmask.long.byte 0x0C 24.--31. 1. " PID ,Process identifier" hexmask.long.byte 0x0C 16.--23. 1. " PIDMASK ,Process identifier mask" newline endif bitfld.long 0x0C 0. " VLD ,Signals the region descriptor" "Not valid,Valid" newline group.long 0x4A0++0x0F line.long 0x00 "RGD10_WORD0,Region Descriptor 10 Word 0" hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address" line.long 0x04 "RGD10_WORD1,Region Descriptor 10 Word 1" hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address" line.long 0x08 "RGD10_WORD2,Region Descriptor 10 Word 2" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FX512VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x08 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x08 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x08 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x08 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x08 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x08 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 17. " M2PE ,DMA process identifier enable" "Disabled,Enabled" bitfld.long 0x08 15.--16. " M2SM ,DMA supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,DMA user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,DMA user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,DMA user mode execute access control" "No access,Access" newline else bitfld.long 0x08 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x08 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x08 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif line.long 0x0C "RGD10_WORD3,Region Descriptor 10 Word 3" sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") hexmask.long.byte 0x0C 24.--31. 1. " PID ,Process identifier" hexmask.long.byte 0x0C 16.--23. 1. " PIDMASK ,Process identifier mask" newline endif bitfld.long 0x0C 0. " VLD ,Signals the region descriptor" "Not valid,Valid" newline group.long 0x4B0++0x0F line.long 0x00 "RGD11_WORD0,Region Descriptor 11 Word 0" hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address" line.long 0x04 "RGD11_WORD1,Region Descriptor 11 Word 1" hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address" line.long 0x08 "RGD11_WORD2,Region Descriptor 11 Word 2" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FX512VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x08 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x08 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x08 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x08 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x08 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x08 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 17. " M2PE ,DMA process identifier enable" "Disabled,Enabled" bitfld.long 0x08 15.--16. " M2SM ,DMA supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,DMA user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,DMA user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,DMA user mode execute access control" "No access,Access" newline else bitfld.long 0x08 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x08 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x08 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif line.long 0x0C "RGD11_WORD3,Region Descriptor 11 Word 3" sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") hexmask.long.byte 0x0C 24.--31. 1. " PID ,Process identifier" hexmask.long.byte 0x0C 16.--23. 1. " PIDMASK ,Process identifier mask" newline endif bitfld.long 0x0C 0. " VLD ,Signals the region descriptor" "Not valid,Valid" newline group.long 0x800++0x03 line.long 0x00 "RGDAAC0,Region Descriptor Alternate Access Control 0" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x00 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M2PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M2SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M2UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M2UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M2UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x00 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x00 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x00 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif group.long 0x804++0x03 line.long 0x00 "RGDAAC1,Region Descriptor Alternate Access Control 1" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x00 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M2PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M2SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M2UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M2UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M2UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x00 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x00 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x00 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif group.long 0x808++0x03 line.long 0x00 "RGDAAC2,Region Descriptor Alternate Access Control 2" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x00 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M2PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M2SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M2UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M2UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M2UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x00 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x00 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x00 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif group.long 0x80C++0x03 line.long 0x00 "RGDAAC3,Region Descriptor Alternate Access Control 3" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x00 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M2PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M2SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M2UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M2UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M2UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x00 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x00 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x00 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif group.long 0x810++0x03 line.long 0x00 "RGDAAC4,Region Descriptor Alternate Access Control 4" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x00 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M2PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M2SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M2UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M2UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M2UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x00 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x00 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x00 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif group.long 0x814++0x03 line.long 0x00 "RGDAAC5,Region Descriptor Alternate Access Control 5" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x00 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M2PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M2SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M2UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M2UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M2UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x00 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x00 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x00 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif group.long 0x818++0x03 line.long 0x00 "RGDAAC6,Region Descriptor Alternate Access Control 6" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x00 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M2PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M2SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M2UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M2UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M2UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x00 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x00 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x00 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif group.long 0x81C++0x03 line.long 0x00 "RGDAAC7,Region Descriptor Alternate Access Control 7" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x00 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M2PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M2SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M2UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M2UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M2UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x00 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x00 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x00 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif group.long 0x820++0x03 line.long 0x00 "RGDAAC8,Region Descriptor Alternate Access Control 8" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x00 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M2PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M2SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M2UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M2UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M2UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x00 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x00 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x00 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif group.long 0x824++0x03 line.long 0x00 "RGDAAC9,Region Descriptor Alternate Access Control 9" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x00 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M2PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M2SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M2UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M2UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M2UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x00 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x00 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x00 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif group.long 0x828++0x03 line.long 0x00 "RGDAAC10,Region Descriptor Alternate Access Control 10" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x00 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M2PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M2SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M2UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M2UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M2UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x00 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x00 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x00 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif group.long 0x82C++0x03 line.long 0x00 "RGDAAC11,Region Descriptor Alternate Access Control 11" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x00 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M2PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M2SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M2UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M2UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M2UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x00 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x00 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x00 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif width 0x0B tree.end tree "DMAMUX (Direct Memory Access Multiplexer)" base ad:0x40021000 width 10. group.byte 0x0++0x00 line.byte 0x00 "CHCFG_0,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 0 Enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA Channel 0 Trigger Enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 0 Source" "Disabled,TSI0,LPUART0_Rx,LPUART0_Tx,LPUART1_Rx,LPUART1_Tx,LPUART2_Rx,LPUART2_Tx,LPUART3_Rx,LPUART3_Tx,LPUART4_Rx,LPUART4_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,I2C0/I2C3,I2C1/I2C2,FTM0 Ch.0,FTM0 Ch.1,FTM0 Ch.2,FTM0 Ch.3,FTM0 Ch.4,FTM0 Ch.5,FTM0 Ch.6,FTM0 Ch.7,FTM1 Ch.0,FTM1 Ch.1,FTM2 Ch.0,FTM2 Ch.1,FTM3 Ch.0,FTM3 Ch.1,FTM3 Ch.2,FTM3 Ch.3,FTM3 Ch.4,FTM3 Ch.5,FTM3 Ch.6,FTM3 Ch.7,ADC0,,CMP0,CMP1,,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,,,,,SPI2_Rx,SPI2_Tx,DMA MUX,DMA MUX,DMA MUX,DMA MUX" group.byte 0x1++0x00 line.byte 0x00 "CHCFG_1,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 1 Enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA Channel 1 Trigger Enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 1 Source" "Disabled,TSI0,LPUART0_Rx,LPUART0_Tx,LPUART1_Rx,LPUART1_Tx,LPUART2_Rx,LPUART2_Tx,LPUART3_Rx,LPUART3_Tx,LPUART4_Rx,LPUART4_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,I2C0/I2C3,I2C1/I2C2,FTM0 Ch.0,FTM0 Ch.1,FTM0 Ch.2,FTM0 Ch.3,FTM0 Ch.4,FTM0 Ch.5,FTM0 Ch.6,FTM0 Ch.7,FTM1 Ch.0,FTM1 Ch.1,FTM2 Ch.0,FTM2 Ch.1,FTM3 Ch.0,FTM3 Ch.1,FTM3 Ch.2,FTM3 Ch.3,FTM3 Ch.4,FTM3 Ch.5,FTM3 Ch.6,FTM3 Ch.7,ADC0,,CMP0,CMP1,,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,,,,,SPI2_Rx,SPI2_Tx,DMA MUX,DMA MUX,DMA MUX,DMA MUX" group.byte 0x2++0x00 line.byte 0x00 "CHCFG_2,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 2 Enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA Channel 2 Trigger Enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 2 Source" "Disabled,TSI0,LPUART0_Rx,LPUART0_Tx,LPUART1_Rx,LPUART1_Tx,LPUART2_Rx,LPUART2_Tx,LPUART3_Rx,LPUART3_Tx,LPUART4_Rx,LPUART4_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,I2C0/I2C3,I2C1/I2C2,FTM0 Ch.0,FTM0 Ch.1,FTM0 Ch.2,FTM0 Ch.3,FTM0 Ch.4,FTM0 Ch.5,FTM0 Ch.6,FTM0 Ch.7,FTM1 Ch.0,FTM1 Ch.1,FTM2 Ch.0,FTM2 Ch.1,FTM3 Ch.0,FTM3 Ch.1,FTM3 Ch.2,FTM3 Ch.3,FTM3 Ch.4,FTM3 Ch.5,FTM3 Ch.6,FTM3 Ch.7,ADC0,,CMP0,CMP1,,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,,,,,SPI2_Rx,SPI2_Tx,DMA MUX,DMA MUX,DMA MUX,DMA MUX" group.byte 0x3++0x00 line.byte 0x00 "CHCFG_3,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 3 Enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA Channel 3 Trigger Enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 3 Source" "Disabled,TSI0,LPUART0_Rx,LPUART0_Tx,LPUART1_Rx,LPUART1_Tx,LPUART2_Rx,LPUART2_Tx,LPUART3_Rx,LPUART3_Tx,LPUART4_Rx,LPUART4_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,I2C0/I2C3,I2C1/I2C2,FTM0 Ch.0,FTM0 Ch.1,FTM0 Ch.2,FTM0 Ch.3,FTM0 Ch.4,FTM0 Ch.5,FTM0 Ch.6,FTM0 Ch.7,FTM1 Ch.0,FTM1 Ch.1,FTM2 Ch.0,FTM2 Ch.1,FTM3 Ch.0,FTM3 Ch.1,FTM3 Ch.2,FTM3 Ch.3,FTM3 Ch.4,FTM3 Ch.5,FTM3 Ch.6,FTM3 Ch.7,ADC0,,CMP0,CMP1,,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,,,,,SPI2_Rx,SPI2_Tx,DMA MUX,DMA MUX,DMA MUX,DMA MUX" group.byte 0x4++0x00 line.byte 0x00 "CHCFG_4,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 4 Enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 4 Source" "Disabled,TSI0,LPUART0_Rx,LPUART0_Tx,LPUART1_Rx,LPUART1_Tx,LPUART2_Rx,LPUART2_Tx,LPUART3_Rx,LPUART3_Tx,LPUART4_Rx,LPUART4_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,I2C0/I2C3,I2C1/I2C2,FTM0 Ch.0,FTM0 Ch.1,FTM0 Ch.2,FTM0 Ch.3,FTM0 Ch.4,FTM0 Ch.5,FTM0 Ch.6,FTM0 Ch.7,FTM1 Ch.0,FTM1 Ch.1,FTM2 Ch.0,FTM2 Ch.1,FTM3 Ch.0,FTM3 Ch.1,FTM3 Ch.2,FTM3 Ch.3,FTM3 Ch.4,FTM3 Ch.5,FTM3 Ch.6,FTM3 Ch.7,ADC0,,CMP0,CMP1,,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,,,,,SPI2_Rx,SPI2_Tx,DMA MUX,DMA MUX,DMA MUX,DMA MUX" group.byte 0x5++0x00 line.byte 0x00 "CHCFG_5,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 5 Enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 5 Source" "Disabled,TSI0,LPUART0_Rx,LPUART0_Tx,LPUART1_Rx,LPUART1_Tx,LPUART2_Rx,LPUART2_Tx,LPUART3_Rx,LPUART3_Tx,LPUART4_Rx,LPUART4_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,I2C0/I2C3,I2C1/I2C2,FTM0 Ch.0,FTM0 Ch.1,FTM0 Ch.2,FTM0 Ch.3,FTM0 Ch.4,FTM0 Ch.5,FTM0 Ch.6,FTM0 Ch.7,FTM1 Ch.0,FTM1 Ch.1,FTM2 Ch.0,FTM2 Ch.1,FTM3 Ch.0,FTM3 Ch.1,FTM3 Ch.2,FTM3 Ch.3,FTM3 Ch.4,FTM3 Ch.5,FTM3 Ch.6,FTM3 Ch.7,ADC0,,CMP0,CMP1,,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,,,,,SPI2_Rx,SPI2_Tx,DMA MUX,DMA MUX,DMA MUX,DMA MUX" group.byte 0x6++0x00 line.byte 0x00 "CHCFG_6,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 6 Enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 6 Source" "Disabled,TSI0,LPUART0_Rx,LPUART0_Tx,LPUART1_Rx,LPUART1_Tx,LPUART2_Rx,LPUART2_Tx,LPUART3_Rx,LPUART3_Tx,LPUART4_Rx,LPUART4_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,I2C0/I2C3,I2C1/I2C2,FTM0 Ch.0,FTM0 Ch.1,FTM0 Ch.2,FTM0 Ch.3,FTM0 Ch.4,FTM0 Ch.5,FTM0 Ch.6,FTM0 Ch.7,FTM1 Ch.0,FTM1 Ch.1,FTM2 Ch.0,FTM2 Ch.1,FTM3 Ch.0,FTM3 Ch.1,FTM3 Ch.2,FTM3 Ch.3,FTM3 Ch.4,FTM3 Ch.5,FTM3 Ch.6,FTM3 Ch.7,ADC0,,CMP0,CMP1,,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,,,,,SPI2_Rx,SPI2_Tx,DMA MUX,DMA MUX,DMA MUX,DMA MUX" group.byte 0x7++0x00 line.byte 0x00 "CHCFG_7,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 7 Enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 7 Source" "Disabled,TSI0,LPUART0_Rx,LPUART0_Tx,LPUART1_Rx,LPUART1_Tx,LPUART2_Rx,LPUART2_Tx,LPUART3_Rx,LPUART3_Tx,LPUART4_Rx,LPUART4_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,I2C0/I2C3,I2C1/I2C2,FTM0 Ch.0,FTM0 Ch.1,FTM0 Ch.2,FTM0 Ch.3,FTM0 Ch.4,FTM0 Ch.5,FTM0 Ch.6,FTM0 Ch.7,FTM1 Ch.0,FTM1 Ch.1,FTM2 Ch.0,FTM2 Ch.1,FTM3 Ch.0,FTM3 Ch.1,FTM3 Ch.2,FTM3 Ch.3,FTM3 Ch.4,FTM3 Ch.5,FTM3 Ch.6,FTM3 Ch.7,ADC0,,CMP0,CMP1,,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,,,,,SPI2_Rx,SPI2_Tx,DMA MUX,DMA MUX,DMA MUX,DMA MUX" group.byte 0x8++0x00 line.byte 0x00 "CHCFG_8,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 8 Enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 8 Source" "Disabled,TSI0,LPUART0_Rx,LPUART0_Tx,LPUART1_Rx,LPUART1_Tx,LPUART2_Rx,LPUART2_Tx,LPUART3_Rx,LPUART3_Tx,LPUART4_Rx,LPUART4_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,I2C0/I2C3,I2C1/I2C2,FTM0 Ch.0,FTM0 Ch.1,FTM0 Ch.2,FTM0 Ch.3,FTM0 Ch.4,FTM0 Ch.5,FTM0 Ch.6,FTM0 Ch.7,FTM1 Ch.0,FTM1 Ch.1,FTM2 Ch.0,FTM2 Ch.1,FTM3 Ch.0,FTM3 Ch.1,FTM3 Ch.2,FTM3 Ch.3,FTM3 Ch.4,FTM3 Ch.5,FTM3 Ch.6,FTM3 Ch.7,ADC0,,CMP0,CMP1,,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,,,,,SPI2_Rx,SPI2_Tx,DMA MUX,DMA MUX,DMA MUX,DMA MUX" group.byte 0x9++0x00 line.byte 0x00 "CHCFG_9,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 9 Enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 9 Source" "Disabled,TSI0,LPUART0_Rx,LPUART0_Tx,LPUART1_Rx,LPUART1_Tx,LPUART2_Rx,LPUART2_Tx,LPUART3_Rx,LPUART3_Tx,LPUART4_Rx,LPUART4_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,I2C0/I2C3,I2C1/I2C2,FTM0 Ch.0,FTM0 Ch.1,FTM0 Ch.2,FTM0 Ch.3,FTM0 Ch.4,FTM0 Ch.5,FTM0 Ch.6,FTM0 Ch.7,FTM1 Ch.0,FTM1 Ch.1,FTM2 Ch.0,FTM2 Ch.1,FTM3 Ch.0,FTM3 Ch.1,FTM3 Ch.2,FTM3 Ch.3,FTM3 Ch.4,FTM3 Ch.5,FTM3 Ch.6,FTM3 Ch.7,ADC0,,CMP0,CMP1,,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,,,,,SPI2_Rx,SPI2_Tx,DMA MUX,DMA MUX,DMA MUX,DMA MUX" group.byte 0xA++0x00 line.byte 0x00 "CHCFG_10,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 10 Enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 10 Source" "Disabled,TSI0,LPUART0_Rx,LPUART0_Tx,LPUART1_Rx,LPUART1_Tx,LPUART2_Rx,LPUART2_Tx,LPUART3_Rx,LPUART3_Tx,LPUART4_Rx,LPUART4_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,I2C0/I2C3,I2C1/I2C2,FTM0 Ch.0,FTM0 Ch.1,FTM0 Ch.2,FTM0 Ch.3,FTM0 Ch.4,FTM0 Ch.5,FTM0 Ch.6,FTM0 Ch.7,FTM1 Ch.0,FTM1 Ch.1,FTM2 Ch.0,FTM2 Ch.1,FTM3 Ch.0,FTM3 Ch.1,FTM3 Ch.2,FTM3 Ch.3,FTM3 Ch.4,FTM3 Ch.5,FTM3 Ch.6,FTM3 Ch.7,ADC0,,CMP0,CMP1,,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,,,,,SPI2_Rx,SPI2_Tx,DMA MUX,DMA MUX,DMA MUX,DMA MUX" group.byte 0xB++0x00 line.byte 0x00 "CHCFG_11,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 11 Enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 11 Source" "Disabled,TSI0,LPUART0_Rx,LPUART0_Tx,LPUART1_Rx,LPUART1_Tx,LPUART2_Rx,LPUART2_Tx,LPUART3_Rx,LPUART3_Tx,LPUART4_Rx,LPUART4_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,I2C0/I2C3,I2C1/I2C2,FTM0 Ch.0,FTM0 Ch.1,FTM0 Ch.2,FTM0 Ch.3,FTM0 Ch.4,FTM0 Ch.5,FTM0 Ch.6,FTM0 Ch.7,FTM1 Ch.0,FTM1 Ch.1,FTM2 Ch.0,FTM2 Ch.1,FTM3 Ch.0,FTM3 Ch.1,FTM3 Ch.2,FTM3 Ch.3,FTM3 Ch.4,FTM3 Ch.5,FTM3 Ch.6,FTM3 Ch.7,ADC0,,CMP0,CMP1,,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,,,,,SPI2_Rx,SPI2_Tx,DMA MUX,DMA MUX,DMA MUX,DMA MUX" group.byte 0xC++0x00 line.byte 0x00 "CHCFG_12,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 12 Enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 12 Source" "Disabled,TSI0,LPUART0_Rx,LPUART0_Tx,LPUART1_Rx,LPUART1_Tx,LPUART2_Rx,LPUART2_Tx,LPUART3_Rx,LPUART3_Tx,LPUART4_Rx,LPUART4_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,I2C0/I2C3,I2C1/I2C2,FTM0 Ch.0,FTM0 Ch.1,FTM0 Ch.2,FTM0 Ch.3,FTM0 Ch.4,FTM0 Ch.5,FTM0 Ch.6,FTM0 Ch.7,FTM1 Ch.0,FTM1 Ch.1,FTM2 Ch.0,FTM2 Ch.1,FTM3 Ch.0,FTM3 Ch.1,FTM3 Ch.2,FTM3 Ch.3,FTM3 Ch.4,FTM3 Ch.5,FTM3 Ch.6,FTM3 Ch.7,ADC0,,CMP0,CMP1,,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,,,,,SPI2_Rx,SPI2_Tx,DMA MUX,DMA MUX,DMA MUX,DMA MUX" group.byte 0xD++0x00 line.byte 0x00 "CHCFG_13,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 13 Enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 13 Source" "Disabled,TSI0,LPUART0_Rx,LPUART0_Tx,LPUART1_Rx,LPUART1_Tx,LPUART2_Rx,LPUART2_Tx,LPUART3_Rx,LPUART3_Tx,LPUART4_Rx,LPUART4_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,I2C0/I2C3,I2C1/I2C2,FTM0 Ch.0,FTM0 Ch.1,FTM0 Ch.2,FTM0 Ch.3,FTM0 Ch.4,FTM0 Ch.5,FTM0 Ch.6,FTM0 Ch.7,FTM1 Ch.0,FTM1 Ch.1,FTM2 Ch.0,FTM2 Ch.1,FTM3 Ch.0,FTM3 Ch.1,FTM3 Ch.2,FTM3 Ch.3,FTM3 Ch.4,FTM3 Ch.5,FTM3 Ch.6,FTM3 Ch.7,ADC0,,CMP0,CMP1,,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,,,,,SPI2_Rx,SPI2_Tx,DMA MUX,DMA MUX,DMA MUX,DMA MUX" group.byte 0xE++0x00 line.byte 0x00 "CHCFG_14,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 14 Enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 14 Source" "Disabled,TSI0,LPUART0_Rx,LPUART0_Tx,LPUART1_Rx,LPUART1_Tx,LPUART2_Rx,LPUART2_Tx,LPUART3_Rx,LPUART3_Tx,LPUART4_Rx,LPUART4_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,I2C0/I2C3,I2C1/I2C2,FTM0 Ch.0,FTM0 Ch.1,FTM0 Ch.2,FTM0 Ch.3,FTM0 Ch.4,FTM0 Ch.5,FTM0 Ch.6,FTM0 Ch.7,FTM1 Ch.0,FTM1 Ch.1,FTM2 Ch.0,FTM2 Ch.1,FTM3 Ch.0,FTM3 Ch.1,FTM3 Ch.2,FTM3 Ch.3,FTM3 Ch.4,FTM3 Ch.5,FTM3 Ch.6,FTM3 Ch.7,ADC0,,CMP0,CMP1,,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,,,,,SPI2_Rx,SPI2_Tx,DMA MUX,DMA MUX,DMA MUX,DMA MUX" group.byte 0xF++0x00 line.byte 0x00 "CHCFG_15,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 15 Enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 15 Source" "Disabled,TSI0,LPUART0_Rx,LPUART0_Tx,LPUART1_Rx,LPUART1_Tx,LPUART2_Rx,LPUART2_Tx,LPUART3_Rx,LPUART3_Tx,LPUART4_Rx,LPUART4_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,I2C0/I2C3,I2C1/I2C2,FTM0 Ch.0,FTM0 Ch.1,FTM0 Ch.2,FTM0 Ch.3,FTM0 Ch.4,FTM0 Ch.5,FTM0 Ch.6,FTM0 Ch.7,FTM1 Ch.0,FTM1 Ch.1,FTM2 Ch.0,FTM2 Ch.1,FTM3 Ch.0,FTM3 Ch.1,FTM3 Ch.2,FTM3 Ch.3,FTM3 Ch.4,FTM3 Ch.5,FTM3 Ch.6,FTM3 Ch.7,ADC0,,CMP0,CMP1,,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,,,,,SPI2_Rx,SPI2_Tx,DMA MUX,DMA MUX,DMA MUX,DMA MUX" group.byte 0x10++0x00 line.byte 0x00 "CHCFG_16,Channel 16 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 16 Enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 16 Source" "Disabled,FlexIO0 (Shifter 0),FlexIO0 (Shifter 1),DMA MUX (Shifter 2),FlexIO0 (Shifter 3),FlexIO0 (Shifter 4),FlexIO0 (Shifter 5),FlexIO0 (Shifter 6),FlexIO0 (Shifter 7),,,,,,,,,,,,,,,,QSPI0_Rx,QSPI0_Tx,,,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,,,,,,,,,TPM1 Ch.0,TPM1 Ch.1,TPM2 Ch.0,TPM2 Ch.1,,,,,,,,,,TPM1 Overflow,TPM2 Overflow,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX" group.byte 0x11++0x00 line.byte 0x00 "CHCFG_17,Channel 17 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 17 Enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 17 Source" "Disabled,FlexIO0 (Shifter 0),FlexIO0 (Shifter 1),DMA MUX (Shifter 2),FlexIO0 (Shifter 3),FlexIO0 (Shifter 4),FlexIO0 (Shifter 5),FlexIO0 (Shifter 6),FlexIO0 (Shifter 7),,,,,,,,,,,,,,,,QSPI0_Rx,QSPI0_Tx,,,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,,,,,,,,,TPM1 Ch.0,TPM1 Ch.1,TPM2 Ch.0,TPM2 Ch.1,,,,,,,,,,TPM1 Overflow,TPM2 Overflow,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX" group.byte 0x12++0x00 line.byte 0x00 "CHCFG_18,Channel 18 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 18 Enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 18 Source" "Disabled,FlexIO0 (Shifter 0),FlexIO0 (Shifter 1),DMA MUX (Shifter 2),FlexIO0 (Shifter 3),FlexIO0 (Shifter 4),FlexIO0 (Shifter 5),FlexIO0 (Shifter 6),FlexIO0 (Shifter 7),,,,,,,,,,,,,,,,QSPI0_Rx,QSPI0_Tx,,,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,,,,,,,,,TPM1 Ch.0,TPM1 Ch.1,TPM2 Ch.0,TPM2 Ch.1,,,,,,,,,,TPM1 Overflow,TPM2 Overflow,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX" group.byte 0x13++0x00 line.byte 0x00 "CHCFG_19,Channel 19 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 19 Enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 19 Source" "Disabled,FlexIO0 (Shifter 0),FlexIO0 (Shifter 1),DMA MUX (Shifter 2),FlexIO0 (Shifter 3),FlexIO0 (Shifter 4),FlexIO0 (Shifter 5),FlexIO0 (Shifter 6),FlexIO0 (Shifter 7),,,,,,,,,,,,,,,,QSPI0_Rx,QSPI0_Tx,,,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,,,,,,,,,TPM1 Ch.0,TPM1 Ch.1,TPM2 Ch.0,TPM2 Ch.1,,,,,,,,,,TPM1 Overflow,TPM2 Overflow,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX" group.byte 0x14++0x00 line.byte 0x00 "CHCFG_20,Channel 20 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 20 Enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 20 Source" "Disabled,FlexIO0 (Shifter 0),FlexIO0 (Shifter 1),DMA MUX (Shifter 2),FlexIO0 (Shifter 3),FlexIO0 (Shifter 4),FlexIO0 (Shifter 5),FlexIO0 (Shifter 6),FlexIO0 (Shifter 7),,,,,,,,,,,,,,,,QSPI0_Rx,QSPI0_Tx,,,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,,,,,,,,,TPM1 Ch.0,TPM1 Ch.1,TPM2 Ch.0,TPM2 Ch.1,,,,,,,,,,TPM1 Overflow,TPM2 Overflow,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX" group.byte 0x15++0x00 line.byte 0x00 "CHCFG_21,Channel 21 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 21 Enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 21 Source" "Disabled,FlexIO0 (Shifter 0),FlexIO0 (Shifter 1),DMA MUX (Shifter 2),FlexIO0 (Shifter 3),FlexIO0 (Shifter 4),FlexIO0 (Shifter 5),FlexIO0 (Shifter 6),FlexIO0 (Shifter 7),,,,,,,,,,,,,,,,QSPI0_Rx,QSPI0_Tx,,,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,,,,,,,,,TPM1 Ch.0,TPM1 Ch.1,TPM2 Ch.0,TPM2 Ch.1,,,,,,,,,,TPM1 Overflow,TPM2 Overflow,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX" group.byte 0x16++0x00 line.byte 0x00 "CHCFG_22,Channel 22 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 22 Enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 22 Source" "Disabled,FlexIO0 (Shifter 0),FlexIO0 (Shifter 1),DMA MUX (Shifter 2),FlexIO0 (Shifter 3),FlexIO0 (Shifter 4),FlexIO0 (Shifter 5),FlexIO0 (Shifter 6),FlexIO0 (Shifter 7),,,,,,,,,,,,,,,,QSPI0_Rx,QSPI0_Tx,,,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,,,,,,,,,TPM1 Ch.0,TPM1 Ch.1,TPM2 Ch.0,TPM2 Ch.1,,,,,,,,,,TPM1 Overflow,TPM2 Overflow,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX" group.byte 0x17++0x00 line.byte 0x00 "CHCFG_23,Channel 23 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 23 Enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 23 Source" "Disabled,FlexIO0 (Shifter 0),FlexIO0 (Shifter 1),DMA MUX (Shifter 2),FlexIO0 (Shifter 3),FlexIO0 (Shifter 4),FlexIO0 (Shifter 5),FlexIO0 (Shifter 6),FlexIO0 (Shifter 7),,,,,,,,,,,,,,,,QSPI0_Rx,QSPI0_Tx,,,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,,,,,,,,,TPM1 Ch.0,TPM1 Ch.1,TPM2 Ch.0,TPM2 Ch.1,,,,,,,,,,TPM1 Overflow,TPM2 Overflow,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX" group.byte 0x18++0x00 line.byte 0x00 "CHCFG_24,Channel 24 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 24 Enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 24 Source" "Disabled,FlexIO0 (Shifter 0),FlexIO0 (Shifter 1),DMA MUX (Shifter 2),FlexIO0 (Shifter 3),FlexIO0 (Shifter 4),FlexIO0 (Shifter 5),FlexIO0 (Shifter 6),FlexIO0 (Shifter 7),,,,,,,,,,,,,,,,QSPI0_Rx,QSPI0_Tx,,,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,,,,,,,,,TPM1 Ch.0,TPM1 Ch.1,TPM2 Ch.0,TPM2 Ch.1,,,,,,,,,,TPM1 Overflow,TPM2 Overflow,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX" group.byte 0x19++0x00 line.byte 0x00 "CHCFG_25,Channel 25 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 25 Enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 25 Source" "Disabled,FlexIO0 (Shifter 0),FlexIO0 (Shifter 1),DMA MUX (Shifter 2),FlexIO0 (Shifter 3),FlexIO0 (Shifter 4),FlexIO0 (Shifter 5),FlexIO0 (Shifter 6),FlexIO0 (Shifter 7),,,,,,,,,,,,,,,,QSPI0_Rx,QSPI0_Tx,,,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,,,,,,,,,TPM1 Ch.0,TPM1 Ch.1,TPM2 Ch.0,TPM2 Ch.1,,,,,,,,,,TPM1 Overflow,TPM2 Overflow,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX" group.byte 0x1A++0x00 line.byte 0x00 "CHCFG_26,Channel 26 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 26 Enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 26 Source" "Disabled,FlexIO0 (Shifter 0),FlexIO0 (Shifter 1),DMA MUX (Shifter 2),FlexIO0 (Shifter 3),FlexIO0 (Shifter 4),FlexIO0 (Shifter 5),FlexIO0 (Shifter 6),FlexIO0 (Shifter 7),,,,,,,,,,,,,,,,QSPI0_Rx,QSPI0_Tx,,,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,,,,,,,,,TPM1 Ch.0,TPM1 Ch.1,TPM2 Ch.0,TPM2 Ch.1,,,,,,,,,,TPM1 Overflow,TPM2 Overflow,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX" group.byte 0x1B++0x00 line.byte 0x00 "CHCFG_27,Channel 27 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 27 Enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 27 Source" "Disabled,FlexIO0 (Shifter 0),FlexIO0 (Shifter 1),DMA MUX (Shifter 2),FlexIO0 (Shifter 3),FlexIO0 (Shifter 4),FlexIO0 (Shifter 5),FlexIO0 (Shifter 6),FlexIO0 (Shifter 7),,,,,,,,,,,,,,,,QSPI0_Rx,QSPI0_Tx,,,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,,,,,,,,,TPM1 Ch.0,TPM1 Ch.1,TPM2 Ch.0,TPM2 Ch.1,,,,,,,,,,TPM1 Overflow,TPM2 Overflow,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX" group.byte 0x1C++0x00 line.byte 0x00 "CHCFG_28,Channel 28 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 28 Enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 28 Source" "Disabled,FlexIO0 (Shifter 0),FlexIO0 (Shifter 1),DMA MUX (Shifter 2),FlexIO0 (Shifter 3),FlexIO0 (Shifter 4),FlexIO0 (Shifter 5),FlexIO0 (Shifter 6),FlexIO0 (Shifter 7),,,,,,,,,,,,,,,,QSPI0_Rx,QSPI0_Tx,,,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,,,,,,,,,TPM1 Ch.0,TPM1 Ch.1,TPM2 Ch.0,TPM2 Ch.1,,,,,,,,,,TPM1 Overflow,TPM2 Overflow,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX" group.byte 0x1D++0x00 line.byte 0x00 "CHCFG_29,Channel 29 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 29 Enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 29 Source" "Disabled,FlexIO0 (Shifter 0),FlexIO0 (Shifter 1),DMA MUX (Shifter 2),FlexIO0 (Shifter 3),FlexIO0 (Shifter 4),FlexIO0 (Shifter 5),FlexIO0 (Shifter 6),FlexIO0 (Shifter 7),,,,,,,,,,,,,,,,QSPI0_Rx,QSPI0_Tx,,,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,,,,,,,,,TPM1 Ch.0,TPM1 Ch.1,TPM2 Ch.0,TPM2 Ch.1,,,,,,,,,,TPM1 Overflow,TPM2 Overflow,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX" group.byte 0x1E++0x00 line.byte 0x00 "CHCFG_30,Channel 30 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 30 Enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 30 Source" "Disabled,FlexIO0 (Shifter 0),FlexIO0 (Shifter 1),DMA MUX (Shifter 2),FlexIO0 (Shifter 3),FlexIO0 (Shifter 4),FlexIO0 (Shifter 5),FlexIO0 (Shifter 6),FlexIO0 (Shifter 7),,,,,,,,,,,,,,,,QSPI0_Rx,QSPI0_Tx,,,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,,,,,,,,,TPM1 Ch.0,TPM1 Ch.1,TPM2 Ch.0,TPM2 Ch.1,,,,,,,,,,TPM1 Overflow,TPM2 Overflow,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX" group.byte 0x1F++0x00 line.byte 0x00 "CHCFG_31,Channel 31 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 31 Enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 31 Source" "Disabled,FlexIO0 (Shifter 0),FlexIO0 (Shifter 1),DMA MUX (Shifter 2),FlexIO0 (Shifter 3),FlexIO0 (Shifter 4),FlexIO0 (Shifter 5),FlexIO0 (Shifter 6),FlexIO0 (Shifter 7),,,,,,,,,,,,,,,,QSPI0_Rx,QSPI0_Tx,,,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,,,,,,,,,TPM1 Ch.0,TPM1 Ch.1,TPM2 Ch.0,TPM2 Ch.1,,,,,,,,,,TPM1 Overflow,TPM2 Overflow,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX" width 0x0B tree.end tree "eDMA (Enhanced Direct Memory Access)" base ad:0x40008000 width 6. tree "eDMA Control and Status Registers" group.long 0x00++0x03 line.long 0x00 "CR,Control Register" sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") sif cpuis("MK22FN128VLH10R") rbitfld.long 0x00 31. " ACTIVE ,DMA active status" "Idle,Executing" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.long 0x00 31. " ACTIVE ,DMA active status" "Idle,Executing" newline endif endif bitfld.long 0x00 17. " CX ,Cancel transfer" "Not canceled,Canceled" bitfld.long 0x00 16. " ECX ,Error cancel transfer" "No error,Error" sif cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") newline bitfld.long 0x00 10. " GRP1PRI ,Channel group 1 priority" "0,1" bitfld.long 0x00 8. " GRP0PRI ,Channel group 0 priority" "0,1" elif cpuis("MK?0F*")||cpuis("MK6?F*")||cpuis("MK60FN1M0VLQ15") sif !cpuis("MK63FN1M0VLQ12R") newline bitfld.long 0x00 10.--11. " GRP1PRI ,Channel group 1 priority" "0,1,2,3" bitfld.long 0x00 8.--9. " GRP0PRI ,Channel group 0 priority" "0,1,2,3" endif endif newline bitfld.long 0x00 7. " EMLM ,Enable minor loop mapping" "Disabled,Enabled" bitfld.long 0x00 6. " CLM ,Continuous link mode" "Through channel arbitration,Not through channel arbitration" newline bitfld.long 0x00 5. " HALT ,Halt DMA operations" "Not halted,Halted" bitfld.long 0x00 4. " HOE ,Halt on error" "Not halted,Halted" newline sif cpuis("MK?0F*")||cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK60FN1M0VLQ15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 3. " ERGA ,Enable round robin group arbitration" "Disabled,Enabled" newline endif endif bitfld.long 0x00 2. " ERCA ,Enable round robin channel arbitration" "Disabled,Enabled" bitfld.long 0x00 1. " EDBG ,Enable debug" "Disabled,Enabled" rgroup.long 0x04++0x03 line.long 0x00 "ES,Error Status Register" bitfld.long 0x00 31. " VLD ,Logical OR of all ERR status bits" "Cleared,Not cleared" bitfld.long 0x00 16. " ECX ,Transfer canceled" "Not canceled,Canceled" sif cpuis("MK?0F*")||cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK60FN1M0VLQ15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") newline bitfld.long 0x00 15. " GPE ,Group priority error" "No error,Error" endif endif sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60FN1M0VLQ15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") newline bitfld.long 0x00 14. " CPE ,Channel priority error" "No error,Error" bitfld.long 0x00 8.--12. " ERRCHN ,Error channel number or canceled channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.long 0x00 14. " CPE ,Channel priority error" "No error,Error" bitfld.long 0x00 8.--11. " ERRCHN ,Error channel number or canceled channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") newline bitfld.long 0x00 14. " CPE ,Channel priority error" "No error,Error" bitfld.long 0x00 8.--9. " ERRCHN ,Error channel number or canceled channel number" "0,1,2,3" else newline bitfld.long 0x00 14. " CPE ,Channel priority error" "No error,Error" bitfld.long 0x00 8.--11. " ERRCHN ,Error channel number or canceled channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else newline bitfld.long 0x00 14. " CPE ,Channel priority error" "No error,Error" bitfld.long 0x00 8.--11. " ERRCHN ,Error channel number or canceled channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.long 0x00 7. " SAE ,Source address error" "No error,Error" bitfld.long 0x00 6. " SOE ,Source offset error" "No error,Error" newline bitfld.long 0x00 5. " DAE ,Destination address error" "No error,Error" bitfld.long 0x00 4. " DOE ,Destination offset error" "No error,Error" bitfld.long 0x00 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" newline bitfld.long 0x00 2. " SGE ,Scatter/gather configuration error" "No error,Error" bitfld.long 0x00 1. " SBE ,Source bus error" "No error,Error" bitfld.long 0x00 0. " DBE ,Destination bus error" "No error,Error" group.long 0x0C++0x03 line.long 0x00 "ERQ,Enable Request Register" sif cpuis("MK6?F*")||cpuis("MK?0F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK60FN1M0VLQ15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.long 0x00 31. " ERQ[31] ,Enable DMA request 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Enable DMA request 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Enable DMA request 29" "Disabled,Enabled" newline bitfld.long 0x00 28. " [28] ,Enable DMA request 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Enable DMA request 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Enable DMA request 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,Enable DMA request 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Enable DMA request 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,Enable DMA request 23" "Disabled,Enabled" newline bitfld.long 0x00 22. " [22] ,Enable DMA request 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Enable DMA request 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Enable DMA request 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,Enable DMA request 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Enable DMA request 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Enable DMA request 17" "Disabled,Enabled" newline bitfld.long 0x00 16. " [16] ,Enable DMA request 16" "Disabled,Enabled" newline endif endif sif cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0VLL10")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK70FN1M0VMJ12")||cpuis("MK70FN1M0VMJ15")||cpuis("MK20FX256VLH7")||cpuis("MK20FX128VLH7")||cpuis("MK20FX64VLH7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7") sif cpuis("MK?0F*")||cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK60FN1M0VLQ15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.long 0x00 15. " [15] ,Enable DMA request 15" "Disabled,Enabled" endif else bitfld.long 0x00 15. " ERQ[15] ,Enable DMA request 15" "Disabled,Enabled" endif newline bitfld.long 0x00 14. " [14] ,Enable DMA request 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Enable DMA request 13" "Disabled,Enabled" newline bitfld.long 0x00 12. " [12] ,Enable DMA request 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Enable DMA request 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Enable DMA request 10" "Disabled,Enabled" newline bitfld.long 0x00 9. " [9] ,Enable DMA request 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Enable DMA request 8" "Disabled,Enabled" bitfld.long 0x00 7. " [7] ,Enable DMA request 7" "Disabled,Enabled" newline bitfld.long 0x00 6. " [6] ,Enable DMA request 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable DMA request 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable DMA request 4" "Disabled,Enabled" newline elif !cpuis("MK?0D*5")&&!cpuis("MK22*DC10")&&!cpuis("MK22*LL10")&&!cpuis("MK22*MP10")&&!cpuis("MK22*LH10")&&!cpuis("MK22FN128VLH10R") sif cpuis("MK?0F*")||cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK60FN1M0VLQ15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.long 0x00 15. " [15] ,Enable DMA request 15" "Disabled,Enabled" endif else bitfld.long 0x00 15. " ERQ[15] ,Enable DMA request 15" "Disabled,Enabled" endif newline bitfld.long 0x00 14. " [14] ,Enable DMA request 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Enable DMA request 13" "Disabled,Enabled" newline bitfld.long 0x00 12. " [12] ,Enable DMA request 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Enable DMA request 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Enable DMA request 10" "Disabled,Enabled" newline bitfld.long 0x00 9. " [9] ,Enable DMA request 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Enable DMA request 8" "Disabled,Enabled" bitfld.long 0x00 7. " [7] ,Enable DMA request 7" "Disabled,Enabled" newline bitfld.long 0x00 6. " [6] ,Enable DMA request 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable DMA request 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable DMA request 4" "Disabled,Enabled" newline endif bitfld.long 0x00 3. " [3] ,Enable DMA request 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable DMA request 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable DMA request 1" "Disabled,Enabled" newline bitfld.long 0x00 0. " [0] ,Enable DMA request 0" "Disabled,Enabled" group.long 0x14++0x03 line.long 0x00 "EEI,Enable Error Interrupt Register" sif cpuis("MK?0F*")||cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK60FN1M0VLQ15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.long 0x00 31. " EEI[31] ,Enable error interrupt 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Enable error interrupt 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Enable error interrupt 29" "Disabled,Enabled" newline bitfld.long 0x00 28. " [28] ,Enable error interrupt 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Enable error interrupt 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Enable error interrupt 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,Enable error interrupt 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Enable error interrupt 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,Enable error interrupt 23" "Disabled,Enabled" newline bitfld.long 0x00 22. " [22] ,Enable error interrupt 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Enable error interrupt 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Enable error interrupt 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,Enable error interrupt 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Enable error interrupt 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Enable error interrupt 17" "Disabled,Enabled" newline bitfld.long 0x00 16. " [16] ,Enable error interrupt 16" "Disabled,Enabled" newline endif endif sif cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0VLL10")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK70FN1M0VMJ12")||cpuis("MK70FN1M0VMJ15")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R") sif cpuis("MK?0F*")||cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK60FN1M0VLQ15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.long 0x00 15. " [15] ,Enable error interrupt 15" "Disabled,Enabled" endif else bitfld.long 0x00 15. " EEI[15] ,Enable error interrupt 15" "Disabled,Enabled" endif newline bitfld.long 0x00 14. " [14] ,Enable error interrupt 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Enable error interrupt 13" "Disabled,Enabled" newline bitfld.long 0x00 12. " [12] ,Enable error interrupt 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Enable error interrupt 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Enable error interrupt 10" "Disabled,Enabled" newline bitfld.long 0x00 9. " [9] ,Enable error interrupt 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Enable error interrupt 8" "Disabled,Enabled" bitfld.long 0x00 7. " [7] ,Enable error interrupt 7" "Disabled,Enabled" newline bitfld.long 0x00 6. " [6] ,Enable error interrupt 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable error interrupt 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable error interrupt 4" "Disabled,Enabled" newline elif !cpuis("MK?0D*5")&&!cpuis("MK22*DC10")&&!cpuis("MK22*LL10")&&!cpuis("MK22*MP10")&&!cpuis("MK22*LH10")&&!cpuis("MK22FN128VLH10R") sif cpuis("MK?0F*")||cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK60FN1M0VLQ15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.long 0x00 15. " [15] ,Enable error interrupt 15" "Disabled,Enabled" endif else bitfld.long 0x00 15. " EEI[15] ,Enable error interrupt 15" "Disabled,Enabled" endif newline bitfld.long 0x00 14. " [14] ,Enable error interrupt 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Enable error interrupt 13" "Disabled,Enabled" newline bitfld.long 0x00 12. " [12] ,Enable error interrupt 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Enable error interrupt 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Enable error interrupt 10" "Disabled,Enabled" newline bitfld.long 0x00 9. " [9] ,Enable error interrupt 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Enable error interrupt 8" "Disabled,Enabled" bitfld.long 0x00 7. " [7] ,Enable error interrupt 7" "Disabled,Enabled" newline bitfld.long 0x00 6. " [6] ,Enable error interrupt 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable error interrupt 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable error interrupt 4" "Disabled,Enabled" newline endif bitfld.long 0x00 3. " [3] ,Enable error interrupt 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable error interrupt 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable error interrupt 1" "Disabled,Enabled" newline bitfld.long 0x00 0. " [0] ,Enable error interrupt 0" "Disabled,Enabled" newline wgroup.byte 0x18++0x27 line.byte 0x00 "CEEI,Clear Enable Error Interrupt Register" bitfld.byte 0x00 7. " NOP ,No operation bit" "Disable,Enable" bitfld.byte 0x00 6. " CAEE ,Clear all enable error interrupts" "CEEI only,All EEI" newline sif cpuis("MK20FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK60FN1M0VLQ15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.byte 0x00 0.--4. " CEEI ,Clear enable error interrupt for DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline elif cpuis("MK20DX64VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN32VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK22FN128VLH10R") bitfld.byte 0x00 0.--1. " CEEI ,Clear enable error interrupt for DMA channel" "0,1,2,3" newline elif cpuis("MK24FN256VDC12")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN128CAH12R")||cpuis("MK21FX512VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10")||cpuis("MK20DX64VMB7")||cpuis("MK20DX64VEX7")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VMB7")||cpuis("MK20DX256VLQ10R")||cpuis("MK20DX256VLK7R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VEX7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK60DN512ZCAB10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12")||cpuis("MK60DN512ZVLL10")||cpuis("KK60DN512ZCAB10R") bitfld.byte 0x00 0.--3. " CEEI ,Clear enable error interrupt for DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline else sif cpuis("MK6?F*")||cpuis("MK10F*12")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK70*")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.byte 0x00 4. " CEEI[4] ,Clear enable error interrupt 4 in EEI" "No effect,Clear" newline endif endif sif !cpuis("MK?0D*5")&&!cpuis("MK22*DC10")&&!cpuis("MK22*LL10")&&!cpuis("MK22*MP10")&&!cpuis("MK22*LH10") bitfld.byte 0x00 3. " CEEI[3] ,Clear enable error interrupt 3 in EEI" "No effect,Clear" bitfld.byte 0x00 2. " CEEI[2] ,Clear enable error interrupt 2 in EEI" "No effect,Clear" newline endif bitfld.byte 0x00 1. " CEEI[1] ,Clear enable error interrupt 1 in EEI" "No effect,Clear" bitfld.byte 0x00 0. " CEEI[0] ,Clear enable error interrupt 0 in EEI" "No effect,Clear" endif line.byte 0x01 "SEEI,Set Enable Error Interrupt Register" bitfld.byte 0x01 7. " NOP ,No operation bit" "Disable,Enable" bitfld.byte 0x01 6. " SAEE ,Sets all enable error interrupts" "SEEI only,All EEI" newline sif cpuis("MK20FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK60FN1M0VLQ15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.byte 0x01 0.--4. " SEEI ,Set enable error interrupt for DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline elif cpuis("MK20DX64VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN32VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK22FN128VLH10R") bitfld.byte 0x01 0.--1. " SEEI ,Set enable error interrupt for DMA channel" "0,1,2,3" newline elif cpuis("MK24FN256VDC12")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN128CAH12R")||cpuis("MK21FX512VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10")||cpuis("MK20DX64VMB7")||cpuis("MK20DX64VEX7")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VMB7")||cpuis("MK20DX256VLQ10R")||cpuis("MK20DX256VLK7R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VEX7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK60DN512ZCAB10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12")||cpuis("MK60DN512ZVLL10")||cpuis("KK60DN512ZCAB10R") bitfld.byte 0x01 0.--3. " SEEI ,Set enable error interrupt for DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline else sif cpuis("MK6?F*")||cpuis("MK10F*12")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.byte 0x01 4. " SEEI[4] ,Set enable error interrupt 4 in EEI" "No effect,Set" newline endif endif sif !cpuis("MK?0D*5")&&!cpuis("MK22*DC10")&&!cpuis("MK22*LL10")&&!cpuis("MK22*MP10")&&!cpuis("MK22*LH10") bitfld.byte 0x01 3. " SEEI[3] ,Set enable error interrupt 3 in EEI" "No effect,Set" bitfld.byte 0x01 2. " SEEI[2] ,Set enable error interrupt 2 in EEI" "No effect,Set" newline endif bitfld.byte 0x01 1. " SEEI[1] ,Set enable error interrupt 1 in EEI" "No effect,Set" bitfld.byte 0x01 0. " SEEI[0] ,Set enable error interrupt 0 in EEI" "No effect,Set" endif line.byte 0x02 "CERQ,Clear Enable Request Register" bitfld.byte 0x02 7. " NOP ,No operation bit" "Disable,Enable" bitfld.byte 0x02 6. " CAER ,Clear all enable requests" "CER only,ALL ER" newline sif cpuis("MK20FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK60FN1M0VLQ15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.byte 0x02 0.--4. " CERQ ,Clear enable request for DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline elif cpuis("MK20DX64VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN32VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK22FN128VLH10R") bitfld.byte 0x02 0.--1. " CERQ ,Clear enable request for DMA channel" "0,1,2,3" newline elif cpuis("MK24FN256VDC12")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN128CAH12R")||cpuis("MK21FX512VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10")||cpuis("MK20DX64VMB7")||cpuis("MK20DX64VEX7")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VMB7")||cpuis("MK20DX256VLQ10R")||cpuis("MK20DX256VLK7R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VEX7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK60DN512ZCAB10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12")||cpuis("MK60DN512ZVLL10")||cpuis("KK60DN512ZCAB10R") bitfld.byte 0x02 0.--3. " CERQ ,Clear enable request for DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline else sif cpuis("MK6?F*")||cpuis("MK10F*12")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.byte 0x02 4. " CERQ[4] ,Clear enable request" "No effect,Clear" newline endif endif sif !cpuis("MK?0D*5")&&!cpuis("MK22*DC10")&&!cpuis("MK22*LL10")&&!cpuis("MK22*MP10")&&!cpuis("MK22*LH10") bitfld.byte 0x02 3. " CERQ[3] ,Clear enable request" "No effect,Clear" bitfld.byte 0x02 2. " CERQ[2] ,Clear enable request" "No effect,Clear" newline endif bitfld.byte 0x02 1. " CERQ[1] ,Clear enable request" "No effect,Clear" bitfld.byte 0x02 0. " CERQ[0] ,Clear enable request" "No effect,Clear" endif line.byte 0x03 "SERQ,Set Enable Request Register" bitfld.byte 0x03 7. " NOP ,No operation bit" "Disable,Enable" bitfld.byte 0x03 6. " SAER ,Set all enable requests" "SAER only,All ER" newline sif cpuis("MK20FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK60FN1M0VLQ15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.byte 0x03 0.--4. " SERQ ,Set enable request for DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline elif cpuis("MK20DX64VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN32VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK22FN128VLH10R") bitfld.byte 0x03 0.--1. " SERQ ,Set enable request for DMA channel" "0,1,2,3" newline elif cpuis("MK24FN256VDC12")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN128CAH12R")||cpuis("MK21FX512VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10")||cpuis("MK20DX64VMB7")||cpuis("MK20DX64VEX7")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VMB7")||cpuis("MK20DX256VLQ10R")||cpuis("MK20DX256VLK7R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VEX7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK60DN512ZCAB10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12")||cpuis("MK60DN512ZVLL10")||cpuis("KK60DN512ZCAB10R") bitfld.byte 0x03 0.--3. " SERQ ,Set enable request for DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline else sif cpuis("MK6?F*")||cpuis("MK10F*12")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.byte 0x03 4. " SERQ[4] ,Set enable request" "No effect,Set" newline endif endif sif !cpuis("MK?0D*5")&&!cpuis("MK22*DC10")&&!cpuis("MK22*LL10")&&!cpuis("MK22*MP10")&&!cpuis("MK22*LH10") bitfld.byte 0x03 3. " SERQ[3] ,Set enable request" "No effect,Set" bitfld.byte 0x03 2. " SERQ[2] ,Set enable request" "No effect,Set" newline endif bitfld.byte 0x03 1. " SERQ[1] ,Set enable request" "No effect,Set" bitfld.byte 0x03 0. " SERQ[0] ,Set enable request" "No effect,Set" endif line.byte 0x04 "CDNE,Clear DONE Status Bit Register" bitfld.byte 0x04 7. " NOP ,No operation bit" "Disabled,Enabled" bitfld.byte 0x04 6. " CADN ,Clear all done bits" "CADB only,All DB" newline sif cpuis("MK20FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK60FN1M0VLQ15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.byte 0x04 0.--4. " CDNE ,Clear done bit for DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline elif cpuis("MK20DX64VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN32VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK22FN128VLH10R") bitfld.byte 0x04 0.--1. " CDNE ,Clear done bit for DMA channel" "0,1,2,3" newline elif cpuis("MK24FN256VDC12")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN128CAH12R")||cpuis("MK21FX512VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10")||cpuis("MK20DX64VMB7")||cpuis("MK20DX64VEX7")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VMB7")||cpuis("MK20DX256VLQ10R")||cpuis("MK20DX256VLK7R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VEX7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK60DN512ZCAB10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12")||cpuis("MK60DN512ZVLL10")||cpuis("KK60DN512ZCAB10R") bitfld.byte 0x04 0.--3. " CDNE ,Clear done bit for DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline else sif cpuis("MK6?F*")||cpuis("MK10F*12")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK70*") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.byte 0x04 4. " CDNE[4] ,Clear done bit" "No effect,Clear" newline endif endif sif !cpuis("MK?0D*5")&&!cpuis("MK22*DC10")&&!cpuis("MK22*LL10")&&!cpuis("MK22*MP10")&&!cpuis("MK22*LH10") bitfld.byte 0x04 3. " CDNE[3] ,Clear done bit" "No effect,Clear" bitfld.byte 0x04 2. " CDNE[2] ,Clear done bit" "No effect,Clear" newline endif bitfld.byte 0x04 1. " CDNE[1] ,Clear done bit" "No effect,Clear" bitfld.byte 0x04 0. " CDNE[0] ,Clear done bit" "No effect,Clear" endif line.byte 0x05 "SSRT,Set START Bit Register" bitfld.byte 0x05 7. " NOP ,No operation bit" "Disabled,Enabled" bitfld.byte 0x05 6. " SAST ,Set all start bits" "SASB only,All SB" newline sif cpuis("MK20FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK60FN1M0VLQ15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.byte 0x05 0.--4. " SSRT ,Set start bit for DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline elif cpuis("MK20DX64VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN32VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK22FN128VLH10R") bitfld.byte 0x05 0.--1. " SSRT ,Set start bit for DMA channel" "0,1,2,3" newline elif cpuis("MK24FN256VDC12")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN128CAH12R")||cpuis("MK21FX512VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10")||cpuis("MK20DX64VMB7")||cpuis("MK20DX64VEX7")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VMB7")||cpuis("MK20DX256VLQ10R")||cpuis("MK20DX256VLK7R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VEX7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK60DN512ZCAB10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12")||cpuis("MK60DN512ZVLL10")||cpuis("KK60DN512ZCAB10R") bitfld.byte 0x05 0.--3. " SSRT ,Set start bit for DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline else sif cpuis("MK6?F*")||cpuis("MK10F*12")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.byte 0x05 4. " SSRT[4] ,Set start bit" "No effect,Clear" newline endif endif sif !cpuis("MK?0D*5")&&!cpuis("MK22*DC10")&&!cpuis("MK22*LL10")&&!cpuis("MK22*MP10")&&!cpuis("MK22*LH10") bitfld.byte 0x05 3. " SSRT[3] ,Set start bit" "No effect,Clear" bitfld.byte 0x05 2. " SSRT[2] ,Set start bit" "No effect,Clear" newline endif bitfld.byte 0x05 1. " SSRT[1] ,Set start bit" "No effect,Clear" bitfld.byte 0x05 0. " SSRT[0] ,Set start bit" "No effect,Clear" endif line.byte 0x06 "CERR,Clear Error Register" bitfld.byte 0x06 7. " NOP ,No operation bit" "Disable,Enable" bitfld.byte 0x06 6. " CAEI ,Clear all error indicators" "CAEI only,ALL EI" newline sif cpuis("MK20FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK60FN1M0VLQ15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.byte 0x06 0.--4. " CERR ,Clear error indicator for DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline elif cpuis("MK20DX64VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN32VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK22FN128VLH10R") bitfld.byte 0x06 0.--1. " CERR ,Clear error indicator for DMA channel" "0,1,2,3" newline elif cpuis("MK24FN256VDC12")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN128CAH12R")||cpuis("MK21FX512VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10")||cpuis("MK20DX64VMB7")||cpuis("MK20DX64VEX7")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VMB7")||cpuis("MK20DX256VLQ10R")||cpuis("MK20DX256VLK7R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VEX7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK60DN512ZCAB10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12")||cpuis("MK60DN512ZVLL10")||cpuis("KK60DN512ZCAB10R") bitfld.byte 0x06 0.--3. " CERR ,Clear error indicator for DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline else sif cpuis("MK6?F*")||cpuis("MK10F*12")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.byte 0x06 4. " CERR[4] ,Clear error indicator" "No effect,Clear" newline endif endif sif !cpuis("MK?0D*5")&&!cpuis("MK22*DC10")&&!cpuis("MK22*LL10")&&!cpuis("MK22*MP10")&&!cpuis("MK22*LH10") bitfld.byte 0x06 3. " CERR[3] ,Clear error indicator" "No effect,Clear" bitfld.byte 0x06 2. " CERR[2] ,Clear error indicator" "No effect,Clear" newline endif bitfld.byte 0x06 1. " CERR[1] ,Clear error indicator" "No effect,Clear" bitfld.byte 0x06 0. " CERR[0] ,Clear error indicator" "No effect,Clear" endif line.byte 0x07 "CINT,Clear Interrupt Request Register" bitfld.byte 0x07 7. " NOP ,No operation bit" "Disable,Enable" bitfld.byte 0x07 6. " CAIR ,Clear all interrupt request" "CAIR only,All IR" newline sif cpuis("MK20FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK60FN1M0VLQ15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.byte 0x07 0.--4. " CINT ,Clear interrupt request for DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline elif cpuis("MK20DX64VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN32VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK22FN128VLH10R") bitfld.byte 0x07 0.--1. " CINT ,Clear interrupt request for DMA channel" "0,1,2,3" newline elif cpuis("MK24FN256VDC12")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN128CAH12R")||cpuis("MK21FX512VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10")||cpuis("MK20DX64VMB7")||cpuis("MK20DX64VEX7")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VMB7")||cpuis("MK20DX256VLQ10R")||cpuis("MK20DX256VLK7R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VEX7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK60DN512ZCAB10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12")||cpuis("MK60DN512ZVLL10")||cpuis("KK60DN512ZCAB10R") bitfld.byte 0x07 0.--3. " CINT ,Clear interrupt request for DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline else sif cpuis("MK6?F*")||cpuis("MK10F*12")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.byte 0x07 4. " CINT[4] ,Clear interrupt request" "No effect,Clear" newline endif endif sif !cpuis("MK?0D*5")&&!cpuis("MK22*DC10")&&!cpuis("MK22*LL10")&&!cpuis("MK22*MP10")&&!cpuis("MK22*LH10") bitfld.byte 0x07 3. " CINT[3] ,Clear interrupt request" "No effect,Clear" bitfld.byte 0x07 2. " CINT[2] ,Clear interrupt request" "No effect,Clear" newline endif bitfld.byte 0x07 1. " CINT[1] ,Clear interrupt request" "No effect,Clear" bitfld.byte 0x07 0. " CINT[0] ,Clear interrupt request" "No effect,Clear" endif group.long 0x24++0x03 line.long 0x00 "INT,Interrupt Request Register" sif cpuis("MK6?F*")||cpuis("MK?0F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK60FN1M0VLQ15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") eventfld.long 0x00 31. " INT[31] ,Interrupt request 31" "No interrupt,Interrupt" eventfld.long 0x00 30. " [30] ,Interrupt request 30" "No interrupt,Interrupt" eventfld.long 0x00 29. " [29] ,Interrupt request 29" "No interrupt,Interrupt" newline eventfld.long 0x00 28. " [28] ,Interrupt request 28" "No interrupt,Interrupt" eventfld.long 0x00 27. " [27] ,Interrupt request 27" "No interrupt,Interrupt" eventfld.long 0x00 26. " [26] ,Interrupt request 26" "No interrupt,Interrupt" newline eventfld.long 0x00 25. " [25] ,Interrupt request 25" "No interrupt,Interrupt" eventfld.long 0x00 24. " [24] ,Interrupt request 24" "No interrupt,Interrupt" eventfld.long 0x00 23. " [23] ,Interrupt request 23" "No interrupt,Interrupt" newline eventfld.long 0x00 22. " [22] ,Interrupt request 22" "No interrupt,Interrupt" eventfld.long 0x00 21. " [21] ,Interrupt request 21" "No interrupt,Interrupt" eventfld.long 0x00 20. " [20] ,Interrupt request 20" "No interrupt,Interrupt" newline eventfld.long 0x00 19. " [19] ,Interrupt request 19" "No interrupt,Interrupt" eventfld.long 0x00 18. " [18] ,Interrupt request 18" "No interrupt,Interrupt" eventfld.long 0x00 17. " [17] ,Interrupt request 17" "No interrupt,Interrupt" newline eventfld.long 0x00 16. " [16] ,Interrupt request 16" "No interrupt,Interrupt" newline endif endif sif cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0VLL10")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK70FN1M0VMJ12")||cpuis("MK70FN1M0VMJ15")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7") sif cpuis("MK6?F*")||cpuis("MK?0F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK60FN1M0VLQ15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.long 0x00 15. " [15] ,Interrupt request 15" "No interrupt,Interrupt" endif else bitfld.long 0x00 15. " INT[15] ,Interrupt request 15" "No interrupt,Interrupt" endif newline eventfld.long 0x00 14. " [14] ,Interrupt request 14" "No interrupt,Interrupt" eventfld.long 0x00 13. " [13] ,Interrupt request 13" "No interrupt,Interrupt" newline eventfld.long 0x00 12. " [12] ,Interrupt request 12" "No interrupt,Interrupt" eventfld.long 0x00 11. " [11] ,Interrupt request 11" "No interrupt,Interrupt" eventfld.long 0x00 10. " [10] ,Interrupt request 10" "No interrupt,Interrupt" newline eventfld.long 0x00 9. " [9] ,Interrupt request 9" "No interrupt,Interrupt" eventfld.long 0x00 8. " [8] ,Interrupt request 8" "No interrupt,Interrupt" eventfld.long 0x00 7. " [7] ,Interrupt request 7" "No interrupt,Interrupt" newline eventfld.long 0x00 6. " [6] ,Interrupt request 6" "No interrupt,Interrupt" eventfld.long 0x00 5. " [5] ,Interrupt request 5" "No interrupt,Interrupt" eventfld.long 0x00 4. " [4] ,Interrupt request 4" "No interrupt,Interrupt" newline elif !cpuis("MK?0D*5")&&!cpuis("MK22*DC10")&&!cpuis("MK22*LL10")&&!cpuis("MK22*MP10")&&!cpuis("MK22*LH10")&&!cpuis("MK22FN128VLH10R") sif cpuis("MK6?F*")||cpuis("MK?0F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK60FN1M0VLQ15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.long 0x00 15. " [15] ,Interrupt request 15" "No interrupt,Interrupt" endif else bitfld.long 0x00 15. " INT[15] ,Interrupt request 15" "No interrupt,Interrupt" endif newline eventfld.long 0x00 14. " [14] ,Interrupt request 14" "No interrupt,Interrupt" eventfld.long 0x00 13. " [13] ,Interrupt request 13" "No interrupt,Interrupt" newline eventfld.long 0x00 12. " [12] ,Interrupt request 12" "No interrupt,Interrupt" eventfld.long 0x00 11. " [11] ,Interrupt request 11" "No interrupt,Interrupt" eventfld.long 0x00 10. " [10] ,Interrupt request 10" "No interrupt,Interrupt" newline eventfld.long 0x00 9. " [9] ,Interrupt request 9" "No interrupt,Interrupt" eventfld.long 0x00 8. " [8] ,Interrupt request 8" "No interrupt,Interrupt" eventfld.long 0x00 7. " [7] ,Interrupt request 7" "No interrupt,Interrupt" newline eventfld.long 0x00 6. " [6] ,Interrupt request 6" "No interrupt,Interrupt" eventfld.long 0x00 5. " [5] ,Interrupt request 5" "No interrupt,Interrupt" eventfld.long 0x00 4. " [4] ,Interrupt request 4" "No interrupt,Interrupt" newline endif eventfld.long 0x00 3. " [3] ,Interrupt request 3" "No interrupt,Interrupt" eventfld.long 0x00 2. " [2] ,Interrupt request 2" "No interrupt,Interrupt" eventfld.long 0x00 1. " [1] ,Interrupt request 1" "No interrupt,Interrupt" newline eventfld.long 0x00 0. " [0] ,Interrupt request 0" "No interrupt,Interrupt" group.long 0x2C++0x03 line.long 0x00 "ERR,Error Register" sif cpuis("MK6?F*")||cpuis("MK?0F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK60FN1M0VLQ15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") eventfld.long 0x00 31. " ERR[31] ,Error in channel 31" "No error,Error" eventfld.long 0x00 30. " [30] ,Error in channel 30" "No error,Error" eventfld.long 0x00 29. " [29] ,Error in channel 29" "No error,Error" newline eventfld.long 0x00 28. " [28] ,Error in channel 28" "No error,Error" eventfld.long 0x00 27. " [27] ,Error in channel 27" "No error,Error" eventfld.long 0x00 26. " [26] ,Error in channel 26" "No error,Error" newline eventfld.long 0x00 25. " [25] ,Error in channel 25" "No error,Error" eventfld.long 0x00 24. " [24] ,Error in channel 24" "No error,Error" eventfld.long 0x00 23. " [23] ,Error in channel 23" "No error,Error" newline eventfld.long 0x00 22. " [22] ,Error in channel 22" "No error,Error" eventfld.long 0x00 21. " [21] ,Error in channel 21" "No error,Error" eventfld.long 0x00 20. " [20] ,Error in channel 20" "No error,Error" newline eventfld.long 0x00 19. " [19] ,Error in channel 19" "No error,Error" eventfld.long 0x00 18. " [18] ,Error in channel 18" "No error,Error" eventfld.long 0x00 17. " [17] ,Error in channel 17" "No error,Error" newline eventfld.long 0x00 16. " [16] ,Error in channel 16" "No error,Error" newline endif endif sif cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0VLL10")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK70FN1M0VMJ12")||cpuis("MK70FN1M0VMJ15")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7") sif cpuis("MK6?F*")||cpuis("MK?0F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK60FN1M0VLQ15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.long 0x00 15. " [15] ,Error in channel 15" "No error,Error" endif else bitfld.long 0x00 15. " ERR[15] ,Error in channel 15" "No error,Error" endif newline eventfld.long 0x00 14. " [14] ,Error in channel 14" "No error,Error" eventfld.long 0x00 13. " [13] ,Error in channel 13" "No error,Error" newline eventfld.long 0x00 12. " [12] ,Error in channel 12" "No error,Error" eventfld.long 0x00 11. " [11] ,Error in channel 11" "No error,Error" eventfld.long 0x00 10. " [10] ,Error in channel 10" "No error,Error" newline eventfld.long 0x00 9. " [9] ,Error in channel 9" "No error,Error" eventfld.long 0x00 8. " [8] ,Error in channel 8" "No error,Error" eventfld.long 0x00 7. " [7] ,Error in channel 7" "No error,Error" newline eventfld.long 0x00 6. " [6] ,Error in channel 6" "No error,Error" eventfld.long 0x00 5. " [5] ,Error in channel 5" "No error,Error" eventfld.long 0x00 4. " [4] ,Error in channel 4" "No error,Error" newline elif !cpuis("MK?0D*5")&&!cpuis("MK22*DC10")&&!cpuis("MK22*LL10")&&!cpuis("MK22*MP10")&&!cpuis("MK22*LH10")&&!cpuis("MK22FN128VLH10R") sif cpuis("MK6?F*")||cpuis("MK?0F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK60FN1M0VLQ15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.long 0x00 15. " [15] ,Error in channel 15" "No error,Error" endif else bitfld.long 0x00 15. " ERR[15] ,Error in channel 15" "No error,Error" endif newline eventfld.long 0x00 14. " [14] ,Error in channel 14" "No error,Error" eventfld.long 0x00 13. " [13] ,Error in channel 13" "No error,Error" newline eventfld.long 0x00 12. " [12] ,Error in channel 12" "No error,Error" eventfld.long 0x00 11. " [11] ,Error in channel 11" "No error,Error" eventfld.long 0x00 10. " [10] ,Error in channel 10" "No error,Error" newline eventfld.long 0x00 9. " [9] ,Error in channel 9" "No error,Error" eventfld.long 0x00 8. " [8] ,Error in channel 8" "No error,Error" eventfld.long 0x00 7. " [7] ,Error in channel 7" "No error,Error" newline eventfld.long 0x00 6. " [6] ,Error in channel 6" "No error,Error" eventfld.long 0x00 5. " [5] ,Error in channel 5" "No error,Error" eventfld.long 0x00 4. " [4] ,Error in channel 4" "No error,Error" newline endif eventfld.long 0x00 3. " [3] ,Error in channel 3" "No error,Error" eventfld.long 0x00 2. " [2] ,Error in channel 2" "No error,Error" eventfld.long 0x00 1. " [1] ,Error in channel 1" "No error,Error" newline eventfld.long 0x00 0. " [0] ,Error in channel 0" "No error,Error" sif cpuis("MK11*")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") rgroup.long 0x34++0x03 line.long 0x00 "HRS,Hardware Request Status Register" bitfld.long 0x00 15. " HRS[15] ,Hardware request status for channel 15" "Not present,Present" bitfld.long 0x00 14. " [14] ,Hardware request status for channel 14" "Not present,Present" bitfld.long 0x00 13. " [13] ,Hardware request status for channel 13" "Not present,Present" newline bitfld.long 0x00 12. " [12] ,Hardware request status for channel 12" "Not present,Present" bitfld.long 0x00 11. " [11] ,Hardware request status for channel 11" "Not present,Present" bitfld.long 0x00 10. " [10] ,Hardware request status for channel 10" "Not present,Present" newline bitfld.long 0x00 9. " [9] ,Hardware request status for channel 9" "Not present,Present" bitfld.long 0x00 8. " [8] ,Hardware request status for channel 8" "Not present,Present" bitfld.long 0x00 7. " [7] ,Hardware request status for channel 7" "Not present,Present" newline bitfld.long 0x00 6. " [6] ,Hardware request status for channel 6" "Not present,Present" bitfld.long 0x00 5. " [5] ,Hardware request status for channel 5" "Not present,Present" bitfld.long 0x00 4. " [4] ,Hardware request status for channel 4" "Not present,Present" newline bitfld.long 0x00 3. " [3] ,Hardware request status for channel 3" "Not present,Present" bitfld.long 0x00 2. " [2] ,Hardware request status for channel 2" "Not present,Present" bitfld.long 0x00 1. " [1] ,Hardware request status for channel 1" "Not present,Present" newline bitfld.long 0x00 0. " [0] ,Hardware request status for channel 0" "Not present,Present" elif cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK26*")||cpuis("MK24*")||cpuis("MK21D*LK5")||cpuis("MK21D*AVMC5")||cpuis("MK21F*AVLQ12")||cpuis("MK21F*AVMD12")||cpuis("MK21F*AVMC12")||cpuis("MK22F*DC12")||cpuis("MK22F*LL12")||cpuis("MK22F*MP12")||cpuis("MK22F*LH12")||cpuis("MK22F*DC10")||(cpuis("MK22F*LL10")&&!cpuis("MK22FN1M0VLL10"))||cpuis("MK22F*MP10")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK24FN256VDC12")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK70*")||cpuis("MK22FN128VLH10R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") rgroup.long 0x34++0x03 line.long 0x00 "HRS,Hardware Request Status Register" sif cpuis("MK6?F*")||cpuis("MK?0F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK60FN1M0VLQ15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.long 0x00 31. " HRS[31] ,Hardware request status for channel 31" "Not present,Present" bitfld.long 0x00 30. " [30] ,Hardware request status for channel 30" "Not present,Present" bitfld.long 0x00 29. " [29] ,Hardware request status for channel 29" "Not present,Present" newline bitfld.long 0x00 28. " [28] ,Hardware request status for channel 28" "Not present,Present" bitfld.long 0x00 27. " [27] ,Hardware request status for channel 27" "Not present,Present" bitfld.long 0x00 26. " [26] ,Hardware request status for channel 26" "Not present,Present" newline bitfld.long 0x00 25. " [25] ,Hardware request status for channel 25" "Not present,Present" bitfld.long 0x00 24. " [24] ,Hardware request status for channel 24" "Not present,Present" bitfld.long 0x00 23. " [23] ,Hardware request status for channel 23" "Not present,Present" newline bitfld.long 0x00 22. " [22] ,Hardware request status for channel 22" "Not present,Present" bitfld.long 0x00 21. " [21] ,Hardware request status for channel 21" "Not present,Present" bitfld.long 0x00 20. " [20] ,Hardware request status for channel 20" "Not present,Present" newline bitfld.long 0x00 19. " [19] ,Hardware request status for channel 19" "Not present,Present" bitfld.long 0x00 18. " [18] ,Hardware request status for channel 18" "Not present,Present" bitfld.long 0x00 17. " [17] ,Hardware request status for channel 17" "Not present,Present" newline bitfld.long 0x00 16. " [16] ,Hardware request status for channel 16" "Not present,Present" newline endif endif sif cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0VLL10")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK70FN1M0VMJ12")||cpuis("MK70FN1M0VMJ15")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7") sif cpuis("MK6?F*")||cpuis("MK?0F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK60FN1M0VLQ15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.long 0x00 15. " [15] ,Hardware request status for channel 15" "Not present,Present" endif else bitfld.long 0x00 15. " HRS[15] ,Hardware request status for channel 15" "Not present,Present" endif newline bitfld.long 0x00 14. " [14] ,Hardware request status for channel 14" "Not present,Present" bitfld.long 0x00 13. " [13] ,Hardware request status for channel 13" "Not present,Present" newline bitfld.long 0x00 12. " [12] ,Hardware request status for channel 12" "Not present,Present" bitfld.long 0x00 11. " [11] ,Hardware request status for channel 11" "Not present,Present" bitfld.long 0x00 10. " [10] ,Hardware request status for channel 10" "Not present,Present" newline bitfld.long 0x00 9. " [9] ,Hardware request status for channel 9" "Not present,Present" bitfld.long 0x00 8. " [8] ,Hardware request status for channel 8" "Not present,Present" bitfld.long 0x00 7. " [7] ,Hardware request status for channel 7" "Not present,Present" newline bitfld.long 0x00 6. " [6] ,Hardware request status for channel 6" "Not present,Present" bitfld.long 0x00 5. " [5] ,Hardware request status for channel 5" "Not present,Present" bitfld.long 0x00 4. " [4] ,Hardware request status for channel 4" "Not present,Present" newline elif !cpuis("MK?0D*5")&&!cpuis("MK22*DC10")&&!cpuis("MK22*LL10")&&!cpuis("MK22*MP10")&&!cpuis("MK22*LH10")&&!cpuis("MK22FN128VLH10R") sif cpuis("MK6?F*")||cpuis("MK?0F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK60FN1M0VLQ15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.long 0x00 15. " [15] ,Hardware request status for channel 15" "Not present,Present" endif else bitfld.long 0x00 15. " HRS[15] ,Hardware request status for channel 15" "Not present,Present" endif newline bitfld.long 0x00 14. " [14] ,Hardware request status for channel 14" "Not present,Present" bitfld.long 0x00 13. " [13] ,Hardware request status for channel 13" "Not present,Present" newline bitfld.long 0x00 12. " [12] ,Hardware request status for channel 12" "Not present,Present" bitfld.long 0x00 11. " [11] ,Hardware request status for channel 11" "Not present,Present" bitfld.long 0x00 10. " [10] ,Hardware request status for channel 10" "Not present,Present" newline bitfld.long 0x00 9. " [9] ,Hardware request status for channel 9" "Not present,Present" bitfld.long 0x00 8. " [8] ,Hardware request status for channel 8" "Not present,Present" bitfld.long 0x00 7. " [7] ,Hardware request status for channel 7" "Not present,Present" newline bitfld.long 0x00 6. " [6] ,Hardware request status for channel 6" "Not present,Present" bitfld.long 0x00 5. " [5] ,Hardware request status for channel 5" "Not present,Present" bitfld.long 0x00 4. " [4] ,Hardware request status for channel 4" "Not present,Present" newline endif bitfld.long 0x00 3. " [3] ,Hardware request status for channel 3" "Not present,Present" bitfld.long 0x00 2. " [2] ,Hardware request status for channel 2" "Not present,Present" bitfld.long 0x00 1. " [1] ,Hardware request status for channel 1" "Not present,Present" newline bitfld.long 0x00 0. " [0] ,Hardware request status for channel 0" "Not present,Present" else group.long 0x34++0x03 line.long 0x00 "HRS,Hardware Request Status Register" sif cpuis("MK6?F*")||cpuis("MK?0F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.long 0x00 31. " HRS[31] ,Hardware request status for channel 31" "Not present,Present" bitfld.long 0x00 30. " [30] ,Hardware request status for channel 30" "Not present,Present" bitfld.long 0x00 29. " [29] ,Hardware request status for channel 29" "Not present,Present" newline bitfld.long 0x00 28. " [28] ,Hardware request status for channel 28" "Not present,Present" bitfld.long 0x00 27. " [27] ,Hardware request status for channel 27" "Not present,Present" bitfld.long 0x00 26. " [26] ,Hardware request status for channel 26" "Not present,Present" newline bitfld.long 0x00 25. " [25] ,Hardware request status for channel 25" "Not present,Present" bitfld.long 0x00 24. " [24] ,Hardware request status for channel 24" "Not present,Present" bitfld.long 0x00 23. " [23] ,Hardware request status for channel 23" "Not present,Present" newline bitfld.long 0x00 22. " [22] ,Hardware request status for channel 22" "Not present,Present" bitfld.long 0x00 21. " [21] ,Hardware request status for channel 21" "Not present,Present" bitfld.long 0x00 20. " [20] ,Hardware request status for channel 20" "Not present,Present" newline bitfld.long 0x00 19. " [19] ,Hardware request status for channel 19" "Not present,Present" bitfld.long 0x00 18. " [18] ,Hardware request status for channel 18" "Not present,Present" bitfld.long 0x00 17. " [17] ,Hardware request status for channel 17" "Not present,Present" newline bitfld.long 0x00 16. " [16] ,Hardware request status for channel 16" "Not present,Present" newline endif endif sif cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0VLL10")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK70FN1M0VMJ12")||cpuis("MK70FN1M0VMJ15")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7") sif cpuis("MK6?F*")||cpuis("MK?0F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.long 0x00 15. " [15] ,Hardware request status for channel 15" "Not present,Present" endif else bitfld.long 0x00 15. " HRS[15] ,Hardware request status for channel 15" "Not present,Present" endif newline bitfld.long 0x00 14. " [14] ,Hardware request status for channel 14" "Not present,Present" bitfld.long 0x00 13. " [13] ,Hardware request status for channel 13" "Not present,Present" newline bitfld.long 0x00 12. " [12] ,Hardware request status for channel 12" "Not present,Present" bitfld.long 0x00 11. " [11] ,Hardware request status for channel 11" "Not present,Present" bitfld.long 0x00 10. " [10] ,Hardware request status for channel 10" "Not present,Present" newline bitfld.long 0x00 9. " [9] ,Hardware request status for channel 9" "Not present,Present" bitfld.long 0x00 8. " [8] ,Hardware request status for channel 8" "Not present,Present" bitfld.long 0x00 7. " [7] ,Hardware request status for channel 7" "Not present,Present" newline bitfld.long 0x00 6. " [6] ,Hardware request status for channel 6" "Not present,Present" bitfld.long 0x00 5. " [5] ,Hardware request status for channel 5" "Not present,Present" bitfld.long 0x00 4. " [4] ,Hardware request status for channel 4" "Not present,Present" newline elif !cpuis("MK?0D*5")&&!cpuis("MK22*DC10")&&!cpuis("MK22*LL10")&&!cpuis("MK22*MP10")&&!cpuis("MK22*LH10")&&!cpuis("MK22FN128VLH10R") sif cpuis("MK6?F*")||cpuis("MK?0F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.long 0x00 15. " [15] ,Hardware request status for channel 15" "Not present,Present" endif else bitfld.long 0x00 15. " HRS[15] ,Hardware request status for channel 15" "Not present,Present" endif newline bitfld.long 0x00 14. " [14] ,Hardware request status for channel 14" "Not present,Present" bitfld.long 0x00 13. " [13] ,Hardware request status for channel 13" "Not present,Present" newline bitfld.long 0x00 12. " [12] ,Hardware request status for channel 12" "Not present,Present" bitfld.long 0x00 11. " [11] ,Hardware request status for channel 11" "Not present,Present" bitfld.long 0x00 10. " [10] ,Hardware request status for channel 10" "Not present,Present" newline bitfld.long 0x00 9. " [9] ,Hardware request status for channel 9" "Not present,Present" bitfld.long 0x00 8. " [8] ,Hardware request status for channel 8" "Not present,Present" bitfld.long 0x00 7. " [7] ,Hardware request status for channel 7" "Not present,Present" newline bitfld.long 0x00 6. " [6] ,Hardware request status for channel 6" "Not present,Present" bitfld.long 0x00 5. " [5] ,Hardware request status for channel 5" "Not present,Present" bitfld.long 0x00 4. " [4] ,Hardware request status for channel 4" "Not present,Present" newline endif bitfld.long 0x00 3. " [3] ,Hardware request status for channel 3" "Not present,Present" bitfld.long 0x00 2. " [2] ,Hardware request status for channel 2" "Not present,Present" bitfld.long 0x00 1. " [1] ,Hardware request status for channel 1" "Not present,Present" newline bitfld.long 0x00 0. " [0] ,Hardware request status for channel 0" "Not present,Present" endif sif cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK26F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN128CAH12R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK70*")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") group.long 0x44++0x03 line.long 0x00 "EARS,Enable Asynchronous Request In Stop Register" sif cpuis("MK26F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 31. " EDREQ[31] ,Enable asynchronous DMA request in stop for channel 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Enable asynchronous DMA request in stop for channel 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Enable asynchronous DMA request in stop for channel 29" "Disabled,Enabled" newline bitfld.long 0x00 28. " [28] ,Enable asynchronous DMA request in stop for channel 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Enable asynchronous DMA request in stop for channel 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Enable asynchronous DMA request in stop for channel 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,Enable asynchronous DMA request in stop for channel 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Enable asynchronous DMA request in stop for channel 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,Enable asynchronous DMA request in stop for channel 23" "Disabled,Enabled" newline bitfld.long 0x00 22. " [22] ,Enable asynchronous DMA request in stop for channel 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Enable asynchronous DMA request in stop for channel 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Enable asynchronous DMA request in stop for channel 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,Enable asynchronous DMA request in stop for channel 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Enable asynchronous DMA request in stop for channel 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Enable asynchronous DMA request in stop for channel 17" "Disabled,Enabled" newline bitfld.long 0x00 16. " [16] ,Enable asynchronous DMA request in stop for channel 16" "Disabled,Enabled" newline endif sif cpuis("MK26F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 15. " [15] ,Enable asynchronous DMA request in stop for channel 15" "Disabled,Enabled" else bitfld.long 0x00 15. " EDREQ[15] ,Enable asynchronous DMA request in stop for channel 15" "Disabled,Enabled" endif newline bitfld.long 0x00 14. " [14] ,Enable asynchronous DMA request in stop for channel 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Enable asynchronous DMA request in stop for channel 13" "Disabled,Enabled" newline bitfld.long 0x00 12. " [12] ,Enable asynchronous DMA request in stop for channel 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Enable asynchronous DMA request in stop for channel 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Enable asynchronous DMA request in stop for channel 10" "Disabled,Enabled" newline bitfld.long 0x00 9. " [9] ,Enable asynchronous DMA request in stop for channel 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Enable asynchronous DMA request in stop for channel 8" "Disabled,Enabled" bitfld.long 0x00 7. " [7] ,Enable asynchronous DMA request in stop for channel 7" "Disabled,Enabled" newline bitfld.long 0x00 6. " [6] ,Enable asynchronous DMA request in stop for channel 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable asynchronous DMA request in stop for channel 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable asynchronous DMA request in stop for channel 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Enable asynchronous DMA request in stop for channel 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable asynchronous DMA request in stop for channel 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable asynchronous DMA request in stop for channel 1" "Disabled,Enabled" newline bitfld.long 0x00 0. " [0] ,Enable asynchronous DMA request in stop for channel 0" "Disabled,Enabled" elif cpuis("MK26F*MD18")||cpuis("MK22F*DC10")||cpuis("MK22F*LL10")||cpuis("MK22F*MP10")||cpuis("MK22F*LH10")||cpuis("MK22F*DC12")||cpuis("MK22F*LL12")||cpuis("MK22F*MP12")||cpuis("MK22F*LH12")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0AVLL12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0VLH10") group.long 0x44++0x03 line.long 0x00 "EARS,Enable Asynchronous Request In Stop Register" bitfld.long 0x00 3. " EDREQ[3] ,Enable asynchronous DMA request in stop for channel 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable asynchronous DMA request in stop for channel 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable asynchronous DMA request in stop for channel 1" "Disabled,Enabled" newline bitfld.long 0x00 0. " [0] ,Enable asynchronous DMA request in stop for channel 0" "Disabled,Enabled" endif endif tree.end width 11. tree "DMA Channel Priority Registers" sif cpuis("MK20D*5")||cpuis("MK10D*5")||cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") group.byte (0x100+0x0)++0x00 line.byte 0x00 "DCHPRI_3,Channel 3 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 3 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 3 preempt ability" "No,Yes" bitfld.byte 0x00 0.--1. " CHPRI ,Channel 3 arbitration priority" "Lowest,1,2,Highest" group.byte (0x100+0x1)++0x00 line.byte 0x00 "DCHPRI_2,Channel 2 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 2 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 2 preempt ability" "No,Yes" bitfld.byte 0x00 0.--1. " CHPRI ,Channel 2 arbitration priority" "Lowest,1,2,Highest" group.byte (0x100+0x2)++0x00 line.byte 0x00 "DCHPRI_1,Channel 1 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 1 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 1 preempt ability" "No,Yes" bitfld.byte 0x00 0.--1. " CHPRI ,Channel 1 arbitration priority" "Lowest,1,2,Highest" group.byte (0x100+0x3)++0x00 line.byte 0x00 "DCHPRI_0,Channel 0 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 0 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 0 preempt ability" "No,Yes" bitfld.byte 0x00 0.--1. " CHPRI ,Channel 0 arbitration priority" "Lowest,1,2,Highest" else group.byte (0x100+0x0)++0x00 line.byte 0x00 "DCHPRI_3,Channel 3 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 3 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 3 preempt ability" "No,Yes" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 3 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x1)++0x00 line.byte 0x00 "DCHPRI_2,Channel 2 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 2 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 2 preempt ability" "No,Yes" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 2 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x2)++0x00 line.byte 0x00 "DCHPRI_1,Channel 1 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 1 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 1 preempt ability" "No,Yes" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 1 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x3)++0x00 line.byte 0x00 "DCHPRI_0,Channel 0 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 0 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 0 preempt ability" "No,Yes" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 0 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x4)++0x00 line.byte 0x00 "DCHPRI_7,Channel 7 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 7 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 7 preempt ability" "No,Yes" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 7 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x5)++0x00 line.byte 0x00 "DCHPRI_6,Channel 6 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 6 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 6 preempt ability" "No,Yes" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 6 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x6)++0x00 line.byte 0x00 "DCHPRI_5,Channel 5 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 5 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 5 preempt ability" "No,Yes" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 5 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x7)++0x00 line.byte 0x00 "DCHPRI_4,Channel 4 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 4 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 4 preempt ability" "No,Yes" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 4 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x8)++0x00 line.byte 0x00 "DCHPRI_11,Channel 11 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 11 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 11 preempt ability" "No,Yes" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 11 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x9)++0x00 line.byte 0x00 "DCHPRI_10,Channel 10 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 10 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 10 preempt ability" "No,Yes" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 10 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0xA)++0x00 line.byte 0x00 "DCHPRI_9,Channel 9 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 9 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 9 preempt ability" "No,Yes" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 9 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0xB)++0x00 line.byte 0x00 "DCHPRI_8,Channel 8 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 8 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 8 preempt ability" "No,Yes" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 8 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0xC)++0x00 line.byte 0x00 "DCHPRI_15,Channel 15 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 15 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 15 preempt ability" "No,Yes" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 15 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0xD)++0x00 line.byte 0x00 "DCHPRI_14,Channel 14 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 14 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 14 preempt ability" "No,Yes" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 14 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0xE)++0x00 line.byte 0x00 "DCHPRI_13,Channel 13 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 13 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 13 preempt ability" "No,Yes" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 13 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0xF)++0x00 line.byte 0x00 "DCHPRI_12,Channel 12 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 12 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 12 preempt ability" "No,Yes" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 12 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" endif elif cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") group.byte (0x100+0x0)++0x00 line.byte 0x00 "DCHPRI_3,Channel 3 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 3 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 3 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 3 current group priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 3 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x1)++0x00 line.byte 0x00 "DCHPRI_2,Channel 2 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 2 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 2 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 2 current group priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 2 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x2)++0x00 line.byte 0x00 "DCHPRI_1,Channel 1 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 1 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 1 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 1 current group priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 1 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x3)++0x00 line.byte 0x00 "DCHPRI_0,Channel 0 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 0 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 0 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 0 current group priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 0 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x4)++0x00 line.byte 0x00 "DCHPRI_7,Channel 7 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 7 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 7 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 7 current group priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 7 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x5)++0x00 line.byte 0x00 "DCHPRI_6,Channel 6 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 6 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 6 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 6 current group priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 6 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x6)++0x00 line.byte 0x00 "DCHPRI_5,Channel 5 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 5 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 5 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 5 current group priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 5 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x7)++0x00 line.byte 0x00 "DCHPRI_4,Channel 4 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 4 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 4 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 4 current group priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 4 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x8)++0x00 line.byte 0x00 "DCHPRI_11,Channel 11 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 11 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 11 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 11 current group priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 11 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x9)++0x00 line.byte 0x00 "DCHPRI_10,Channel 10 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 10 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 10 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 10 current group priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 10 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0xA)++0x00 line.byte 0x00 "DCHPRI_9,Channel 9 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 9 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 9 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 9 current group priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 9 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0xB)++0x00 line.byte 0x00 "DCHPRI_8,Channel 8 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 8 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 8 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 8 current group priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 8 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0xC)++0x00 line.byte 0x00 "DCHPRI_15,Channel 15 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 15 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 15 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 15 current group priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 15 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0xD)++0x00 line.byte 0x00 "DCHPRI_14,Channel 14 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 14 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 14 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 14 current group priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 14 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0xE)++0x00 line.byte 0x00 "DCHPRI_13,Channel 13 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 13 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 13 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 13 current group priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 13 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0xF)++0x00 line.byte 0x00 "DCHPRI_12,Channel 12 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 12 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 12 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 12 current group priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 12 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x10)++0x00 line.byte 0x00 "DCHPRI_19,Channel 19 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 19 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 19 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 19 current group priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 19 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x11)++0x00 line.byte 0x00 "DCHPRI_18,Channel 18 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 18 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 18 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 18 current group priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 18 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x12)++0x00 line.byte 0x00 "DCHPRI_17,Channel 17 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 17 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 17 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 17 current group priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 17 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x13)++0x00 line.byte 0x00 "DCHPRI_16,Channel 16 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 16 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 16 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 16 current group priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 16 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x14)++0x00 line.byte 0x00 "DCHPRI_23,Channel 23 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 23 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 23 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 23 current group priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 23 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x15)++0x00 line.byte 0x00 "DCHPRI_22,Channel 22 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 22 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 22 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 22 current group priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 22 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x16)++0x00 line.byte 0x00 "DCHPRI_21,Channel 21 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 21 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 21 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 21 current group priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 21 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x17)++0x00 line.byte 0x00 "DCHPRI_20,Channel 20 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 20 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 20 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 20 current group priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 20 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x18)++0x00 line.byte 0x00 "DCHPRI_27,Channel 27 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 27 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 27 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 27 current group priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 27 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x19)++0x00 line.byte 0x00 "DCHPRI_26,Channel 26 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 26 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 26 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 26 current group priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 26 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x1A)++0x00 line.byte 0x00 "DCHPRI_25,Channel 25 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 25 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 25 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 25 current group priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 25 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x1B)++0x00 line.byte 0x00 "DCHPRI_24,Channel 24 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 24 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 24 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 24 current group priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 24 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x1C)++0x00 line.byte 0x00 "DCHPRI_31,Channel 31 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 31 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 31 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 31 current group priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 31 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x1D)++0x00 line.byte 0x00 "DCHPRI_30,Channel 30 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 30 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 30 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 30 current group priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 30 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x1E)++0x00 line.byte 0x00 "DCHPRI_29,Channel 29 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 29 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 29 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 29 current group priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 29 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x1F)++0x00 line.byte 0x00 "DCHPRI_28,Channel 28 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 28 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 28 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 28 current group priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 28 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" else group.byte (0x100+0x0)++0x00 line.byte 0x00 "DCHPRI_3,Channel 3 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 3 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 3 preempt ability" "No,Yes" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK20FN1M0VLQ12R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 3 current group priority" "0,1,2,3" newline endif endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 3 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x1)++0x00 line.byte 0x00 "DCHPRI_2,Channel 2 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 2 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 2 preempt ability" "No,Yes" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK20FN1M0VLQ12R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 2 current group priority" "0,1,2,3" newline endif endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 2 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x2)++0x00 line.byte 0x00 "DCHPRI_1,Channel 1 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 1 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 1 preempt ability" "No,Yes" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK20FN1M0VLQ12R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 1 current group priority" "0,1,2,3" newline endif endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 1 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x3)++0x00 line.byte 0x00 "DCHPRI_0,Channel 0 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 0 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 0 preempt ability" "No,Yes" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK20FN1M0VLQ12R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 0 current group priority" "0,1,2,3" newline endif endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 0 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x4)++0x00 line.byte 0x00 "DCHPRI_7,Channel 7 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 7 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 7 preempt ability" "No,Yes" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK20FN1M0VLQ12R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 7 current group priority" "0,1,2,3" newline endif endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 7 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x5)++0x00 line.byte 0x00 "DCHPRI_6,Channel 6 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 6 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 6 preempt ability" "No,Yes" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK20FN1M0VLQ12R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 6 current group priority" "0,1,2,3" newline endif endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 6 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x6)++0x00 line.byte 0x00 "DCHPRI_5,Channel 5 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 5 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 5 preempt ability" "No,Yes" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK20FN1M0VLQ12R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 5 current group priority" "0,1,2,3" newline endif endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 5 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x7)++0x00 line.byte 0x00 "DCHPRI_4,Channel 4 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 4 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 4 preempt ability" "No,Yes" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK20FN1M0VLQ12R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 4 current group priority" "0,1,2,3" newline endif endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 4 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x8)++0x00 line.byte 0x00 "DCHPRI_11,Channel 11 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 11 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 11 preempt ability" "No,Yes" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK20FN1M0VLQ12R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 11 current group priority" "0,1,2,3" newline endif endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 11 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x9)++0x00 line.byte 0x00 "DCHPRI_10,Channel 10 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 10 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 10 preempt ability" "No,Yes" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK20FN1M0VLQ12R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 10 current group priority" "0,1,2,3" newline endif endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 10 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0xA)++0x00 line.byte 0x00 "DCHPRI_9,Channel 9 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 9 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 9 preempt ability" "No,Yes" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK20FN1M0VLQ12R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 9 current group priority" "0,1,2,3" newline endif endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 9 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0xB)++0x00 line.byte 0x00 "DCHPRI_8,Channel 8 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 8 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 8 preempt ability" "No,Yes" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK20FN1M0VLQ12R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 8 current group priority" "0,1,2,3" newline endif endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 8 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0xC)++0x00 line.byte 0x00 "DCHPRI_15,Channel 15 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 15 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 15 preempt ability" "No,Yes" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK20FN1M0VLQ12R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 15 current group priority" "0,1,2,3" newline endif endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 15 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0xD)++0x00 line.byte 0x00 "DCHPRI_14,Channel 14 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 14 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 14 preempt ability" "No,Yes" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK20FN1M0VLQ12R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 14 current group priority" "0,1,2,3" newline endif endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 14 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0xE)++0x00 line.byte 0x00 "DCHPRI_13,Channel 13 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 13 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 13 preempt ability" "No,Yes" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK20FN1M0VLQ12R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 13 current group priority" "0,1,2,3" newline endif endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 13 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0xF)++0x00 line.byte 0x00 "DCHPRI_12,Channel 12 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 12 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 12 preempt ability" "No,Yes" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK20FN1M0VLQ12R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 12 current group priority" "0,1,2,3" newline endif endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 12 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" endif sif cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4") group.byte (0x140+0x0)++0x00 line.byte 0x00 "DCHMID_3,Channel 3 Master ID Register" bitfld.byte 0x00 7. " EMI ,Enable master ID replication" "Disabled,Enabled" sif cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4") rbitfld.byte 0x00 6. " PAL ,Privileged access level" "Not privileged,Privileged" rbitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.byte 0x00 6. " PAL ,Privileged access level" "Not privileged,Privileged" bitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.byte (0x140+0x1)++0x00 line.byte 0x00 "DCHMID_2,Channel 2 Master ID Register" bitfld.byte 0x00 7. " EMI ,Enable master ID replication" "Disabled,Enabled" sif cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4") rbitfld.byte 0x00 6. " PAL ,Privileged access level" "Not privileged,Privileged" rbitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.byte 0x00 6. " PAL ,Privileged access level" "Not privileged,Privileged" bitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.byte (0x140+0x2)++0x00 line.byte 0x00 "DCHMID_1,Channel 1 Master ID Register" bitfld.byte 0x00 7. " EMI ,Enable master ID replication" "Disabled,Enabled" sif cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4") rbitfld.byte 0x00 6. " PAL ,Privileged access level" "Not privileged,Privileged" rbitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.byte 0x00 6. " PAL ,Privileged access level" "Not privileged,Privileged" bitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.byte (0x140+0x3)++0x00 line.byte 0x00 "DCHMID_0,Channel 0 Master ID Register" bitfld.byte 0x00 7. " EMI ,Enable master ID replication" "Disabled,Enabled" sif cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4") rbitfld.byte 0x00 6. " PAL ,Privileged access level" "Not privileged,Privileged" rbitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.byte 0x00 6. " PAL ,Privileged access level" "Not privileged,Privileged" bitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.byte (0x140+0x4)++0x00 line.byte 0x00 "DCHMID_7,Channel 7 Master ID Register" bitfld.byte 0x00 7. " EMI ,Enable master ID replication" "Disabled,Enabled" sif cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4") rbitfld.byte 0x00 6. " PAL ,Privileged access level" "Not privileged,Privileged" rbitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.byte 0x00 6. " PAL ,Privileged access level" "Not privileged,Privileged" bitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.byte (0x140+0x5)++0x00 line.byte 0x00 "DCHMID_6,Channel 6 Master ID Register" bitfld.byte 0x00 7. " EMI ,Enable master ID replication" "Disabled,Enabled" sif cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4") rbitfld.byte 0x00 6. " PAL ,Privileged access level" "Not privileged,Privileged" rbitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.byte 0x00 6. " PAL ,Privileged access level" "Not privileged,Privileged" bitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.byte (0x140+0x6)++0x00 line.byte 0x00 "DCHMID_5,Channel 5 Master ID Register" bitfld.byte 0x00 7. " EMI ,Enable master ID replication" "Disabled,Enabled" sif cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4") rbitfld.byte 0x00 6. " PAL ,Privileged access level" "Not privileged,Privileged" rbitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.byte 0x00 6. " PAL ,Privileged access level" "Not privileged,Privileged" bitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.byte (0x140+0x7)++0x00 line.byte 0x00 "DCHMID_4,Channel 4 Master ID Register" bitfld.byte 0x00 7. " EMI ,Enable master ID replication" "Disabled,Enabled" sif cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4") rbitfld.byte 0x00 6. " PAL ,Privileged access level" "Not privileged,Privileged" rbitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.byte 0x00 6. " PAL ,Privileged access level" "Not privileged,Privileged" bitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.byte (0x140+0x8)++0x00 line.byte 0x00 "DCHMID_11,Channel 11 Master ID Register" bitfld.byte 0x00 7. " EMI ,Enable master ID replication" "Disabled,Enabled" sif cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4") rbitfld.byte 0x00 6. " PAL ,Privileged access level" "Not privileged,Privileged" rbitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.byte 0x00 6. " PAL ,Privileged access level" "Not privileged,Privileged" bitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.byte (0x140+0x9)++0x00 line.byte 0x00 "DCHMID_10,Channel 10 Master ID Register" bitfld.byte 0x00 7. " EMI ,Enable master ID replication" "Disabled,Enabled" sif cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4") rbitfld.byte 0x00 6. " PAL ,Privileged access level" "Not privileged,Privileged" rbitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.byte 0x00 6. " PAL ,Privileged access level" "Not privileged,Privileged" bitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.byte (0x140+0xA)++0x00 line.byte 0x00 "DCHMID_9,Channel 9 Master ID Register" bitfld.byte 0x00 7. " EMI ,Enable master ID replication" "Disabled,Enabled" sif cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4") rbitfld.byte 0x00 6. " PAL ,Privileged access level" "Not privileged,Privileged" rbitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.byte 0x00 6. " PAL ,Privileged access level" "Not privileged,Privileged" bitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.byte (0x140+0xB)++0x00 line.byte 0x00 "DCHMID_8,Channel 8 Master ID Register" bitfld.byte 0x00 7. " EMI ,Enable master ID replication" "Disabled,Enabled" sif cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4") rbitfld.byte 0x00 6. " PAL ,Privileged access level" "Not privileged,Privileged" rbitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.byte 0x00 6. " PAL ,Privileged access level" "Not privileged,Privileged" bitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.byte (0x140+0xC)++0x00 line.byte 0x00 "DCHMID_15,Channel 15 Master ID Register" bitfld.byte 0x00 7. " EMI ,Enable master ID replication" "Disabled,Enabled" sif cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4") rbitfld.byte 0x00 6. " PAL ,Privileged access level" "Not privileged,Privileged" rbitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.byte 0x00 6. " PAL ,Privileged access level" "Not privileged,Privileged" bitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.byte (0x140+0xD)++0x00 line.byte 0x00 "DCHMID_14,Channel 14 Master ID Register" bitfld.byte 0x00 7. " EMI ,Enable master ID replication" "Disabled,Enabled" sif cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4") rbitfld.byte 0x00 6. " PAL ,Privileged access level" "Not privileged,Privileged" rbitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.byte 0x00 6. " PAL ,Privileged access level" "Not privileged,Privileged" bitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.byte (0x140+0xE)++0x00 line.byte 0x00 "DCHMID_13,Channel 13 Master ID Register" bitfld.byte 0x00 7. " EMI ,Enable master ID replication" "Disabled,Enabled" sif cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4") rbitfld.byte 0x00 6. " PAL ,Privileged access level" "Not privileged,Privileged" rbitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.byte 0x00 6. " PAL ,Privileged access level" "Not privileged,Privileged" bitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.byte (0x140+0xF)++0x00 line.byte 0x00 "DCHMID_12,Channel 12 Master ID Register" bitfld.byte 0x00 7. " EMI ,Enable master ID replication" "Disabled,Enabled" sif cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4") rbitfld.byte 0x00 6. " PAL ,Privileged access level" "Not privileged,Privileged" rbitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.byte 0x00 6. " PAL ,Privileged access level" "Not privileged,Privileged" bitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline endif tree.end base ad:0x40009000 tree "Transfer Control Descriptor Registers" tree "Channel 0" width 23. group.long 0x0++0x03 line.long 0x00 "SADDR,TCD Source Address" newline group.word (0x0+0x04)++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK60DX256ZVMD10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,?..." newline else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif newline if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x0+0x08)++0x03 line.long 0x00 "NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x0+0x08))&0xC0000000)==0x00) group.long (0x0+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x0+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x0+0x0C)++0x07 line.long 0x00 "SLAST,TCD Last Source Address Adjustment" line.long 0x04 "DADDR,TCD Destination Address" newline group.word (0x0+0x14)++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if (((per.w(ad:0x40009000+0x0+0x16))&0x8000)==0x00) group.word (0x0+0x16)++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x0+0x16)++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif newline group.long (0x0+0x18)++0x03 line.long 0x00 "DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" newline if ((((per.w(ad:0x40009000+0x0+0x1E))&0x8000)==0x00)&&(((per.w(ad:0x40009000+0x0+0x1E))&0x7FFF)==0x01))||((((per.w(ad:0x40009000+0x0+0x1E))&0x8000)==0x8000)&&(((per.w(ad:0x40009000+0x0+0x1E))&0x1FF)==0x01)) if (((per.w(ad:0x40009000+0x0+0x1C))&0x80)==0x00) group.word (0x0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif else if (((per.w(ad:0x40009000+0x0+0x1C))&0x80)==0x00) group.word (0x0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" endif newline bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif endif if (((per.w(ad:0x40009000+0x0+0x1E))&0x8000)==0x00) group.word (0x0+0x1E)++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x0+0x1E)++0x01 line.word 0x00 "BITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK60D*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif endif tree.end tree "Channel 1" width 23. group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" newline group.word (0x20+0x04)++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK60DX256ZVMD10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,?..." newline else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif newline if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x20+0x08)++0x03 line.long 0x00 "NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x20+0x08))&0xC0000000)==0x00) group.long (0x20+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x20+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x20+0x0C)++0x07 line.long 0x00 "SLAST,TCD Last Source Address Adjustment" line.long 0x04 "DADDR,TCD Destination Address" newline group.word (0x20+0x14)++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if (((per.w(ad:0x40009000+0x20+0x16))&0x8000)==0x00) group.word (0x20+0x16)++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x20+0x16)++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif newline group.long (0x20+0x18)++0x03 line.long 0x00 "DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" newline if ((((per.w(ad:0x40009000+0x20+0x1E))&0x8000)==0x00)&&(((per.w(ad:0x40009000+0x20+0x1E))&0x7FFF)==0x01))||((((per.w(ad:0x40009000+0x20+0x1E))&0x8000)==0x8000)&&(((per.w(ad:0x40009000+0x20+0x1E))&0x1FF)==0x01)) if (((per.w(ad:0x40009000+0x20+0x1C))&0x80)==0x00) group.word (0x20+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x20+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif else if (((per.w(ad:0x40009000+0x20+0x1C))&0x80)==0x00) group.word (0x20+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x20+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" endif newline bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif endif if (((per.w(ad:0x40009000+0x20+0x1E))&0x8000)==0x00) group.word (0x20+0x1E)++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x20+0x1E)++0x01 line.word 0x00 "BITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK60D*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif endif tree.end tree "Channel 2" width 23. group.long 0x40++0x03 line.long 0x00 "SADDR,TCD Source Address" newline group.word (0x40+0x04)++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK60DX256ZVMD10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,?..." newline else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif newline if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x40+0x08)++0x03 line.long 0x00 "NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x40+0x08))&0xC0000000)==0x00) group.long (0x40+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x40+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x40+0x0C)++0x07 line.long 0x00 "SLAST,TCD Last Source Address Adjustment" line.long 0x04 "DADDR,TCD Destination Address" newline group.word (0x40+0x14)++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if (((per.w(ad:0x40009000+0x40+0x16))&0x8000)==0x00) group.word (0x40+0x16)++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x40+0x16)++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif newline group.long (0x40+0x18)++0x03 line.long 0x00 "DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" newline if ((((per.w(ad:0x40009000+0x40+0x1E))&0x8000)==0x00)&&(((per.w(ad:0x40009000+0x40+0x1E))&0x7FFF)==0x01))||((((per.w(ad:0x40009000+0x40+0x1E))&0x8000)==0x8000)&&(((per.w(ad:0x40009000+0x40+0x1E))&0x1FF)==0x01)) if (((per.w(ad:0x40009000+0x40+0x1C))&0x80)==0x00) group.word (0x40+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x40+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif else if (((per.w(ad:0x40009000+0x40+0x1C))&0x80)==0x00) group.word (0x40+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x40+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" endif newline bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif endif if (((per.w(ad:0x40009000+0x40+0x1E))&0x8000)==0x00) group.word (0x40+0x1E)++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x40+0x1E)++0x01 line.word 0x00 "BITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK60D*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif endif tree.end tree "Channel 3" width 23. group.long 0x60++0x03 line.long 0x00 "SADDR,TCD Source Address" newline group.word (0x60+0x04)++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK60DX256ZVMD10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,?..." newline else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif newline if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x60+0x08)++0x03 line.long 0x00 "NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x60+0x08))&0xC0000000)==0x00) group.long (0x60+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x60+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x60+0x0C)++0x07 line.long 0x00 "SLAST,TCD Last Source Address Adjustment" line.long 0x04 "DADDR,TCD Destination Address" newline group.word (0x60+0x14)++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if (((per.w(ad:0x40009000+0x60+0x16))&0x8000)==0x00) group.word (0x60+0x16)++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x60+0x16)++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif newline group.long (0x60+0x18)++0x03 line.long 0x00 "DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" newline if ((((per.w(ad:0x40009000+0x60+0x1E))&0x8000)==0x00)&&(((per.w(ad:0x40009000+0x60+0x1E))&0x7FFF)==0x01))||((((per.w(ad:0x40009000+0x60+0x1E))&0x8000)==0x8000)&&(((per.w(ad:0x40009000+0x60+0x1E))&0x1FF)==0x01)) if (((per.w(ad:0x40009000+0x60+0x1C))&0x80)==0x00) group.word (0x60+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x60+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif else if (((per.w(ad:0x40009000+0x60+0x1C))&0x80)==0x00) group.word (0x60+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x60+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" endif newline bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif endif if (((per.w(ad:0x40009000+0x60+0x1E))&0x8000)==0x00) group.word (0x60+0x1E)++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x60+0x1E)++0x01 line.word 0x00 "BITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK60D*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif endif tree.end tree "Channel 4" width 23. group.long 0x80++0x03 line.long 0x00 "SADDR,TCD Source Address" newline group.word (0x80+0x04)++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK60DX256ZVMD10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,?..." newline else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif newline if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x80+0x08)++0x03 line.long 0x00 "NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x80+0x08))&0xC0000000)==0x00) group.long (0x80+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x80+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x80+0x0C)++0x07 line.long 0x00 "SLAST,TCD Last Source Address Adjustment" line.long 0x04 "DADDR,TCD Destination Address" newline group.word (0x80+0x14)++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if (((per.w(ad:0x40009000+0x80+0x16))&0x8000)==0x00) group.word (0x80+0x16)++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x80+0x16)++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif newline group.long (0x80+0x18)++0x03 line.long 0x00 "DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" newline if ((((per.w(ad:0x40009000+0x80+0x1E))&0x8000)==0x00)&&(((per.w(ad:0x40009000+0x80+0x1E))&0x7FFF)==0x01))||((((per.w(ad:0x40009000+0x80+0x1E))&0x8000)==0x8000)&&(((per.w(ad:0x40009000+0x80+0x1E))&0x1FF)==0x01)) if (((per.w(ad:0x40009000+0x80+0x1C))&0x80)==0x00) group.word (0x80+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x80+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif else if (((per.w(ad:0x40009000+0x80+0x1C))&0x80)==0x00) group.word (0x80+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x80+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" endif newline bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif endif if (((per.w(ad:0x40009000+0x80+0x1E))&0x8000)==0x00) group.word (0x80+0x1E)++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x80+0x1E)++0x01 line.word 0x00 "BITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK60D*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif endif tree.end tree "Channel 5" width 23. group.long 0xA0++0x03 line.long 0x00 "SADDR,TCD Source Address" newline group.word (0xA0+0x04)++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK60DX256ZVMD10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,?..." newline else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif newline if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0xA0+0x08)++0x03 line.long 0x00 "NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0xA0+0x08))&0xC0000000)==0x00) group.long (0xA0+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0xA0+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0xA0+0x0C)++0x07 line.long 0x00 "SLAST,TCD Last Source Address Adjustment" line.long 0x04 "DADDR,TCD Destination Address" newline group.word (0xA0+0x14)++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if (((per.w(ad:0x40009000+0xA0+0x16))&0x8000)==0x00) group.word (0xA0+0x16)++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0xA0+0x16)++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif newline group.long (0xA0+0x18)++0x03 line.long 0x00 "DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" newline if ((((per.w(ad:0x40009000+0xA0+0x1E))&0x8000)==0x00)&&(((per.w(ad:0x40009000+0xA0+0x1E))&0x7FFF)==0x01))||((((per.w(ad:0x40009000+0xA0+0x1E))&0x8000)==0x8000)&&(((per.w(ad:0x40009000+0xA0+0x1E))&0x1FF)==0x01)) if (((per.w(ad:0x40009000+0xA0+0x1C))&0x80)==0x00) group.word (0xA0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0xA0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif else if (((per.w(ad:0x40009000+0xA0+0x1C))&0x80)==0x00) group.word (0xA0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0xA0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" endif newline bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif endif if (((per.w(ad:0x40009000+0xA0+0x1E))&0x8000)==0x00) group.word (0xA0+0x1E)++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0xA0+0x1E)++0x01 line.word 0x00 "BITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK60D*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif endif tree.end tree "Channel 6" width 23. group.long 0xC0++0x03 line.long 0x00 "SADDR,TCD Source Address" newline group.word (0xC0+0x04)++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK60DX256ZVMD10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,?..." newline else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif newline if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0xC0+0x08)++0x03 line.long 0x00 "NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0xC0+0x08))&0xC0000000)==0x00) group.long (0xC0+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0xC0+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0xC0+0x0C)++0x07 line.long 0x00 "SLAST,TCD Last Source Address Adjustment" line.long 0x04 "DADDR,TCD Destination Address" newline group.word (0xC0+0x14)++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if (((per.w(ad:0x40009000+0xC0+0x16))&0x8000)==0x00) group.word (0xC0+0x16)++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0xC0+0x16)++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif newline group.long (0xC0+0x18)++0x03 line.long 0x00 "DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" newline if ((((per.w(ad:0x40009000+0xC0+0x1E))&0x8000)==0x00)&&(((per.w(ad:0x40009000+0xC0+0x1E))&0x7FFF)==0x01))||((((per.w(ad:0x40009000+0xC0+0x1E))&0x8000)==0x8000)&&(((per.w(ad:0x40009000+0xC0+0x1E))&0x1FF)==0x01)) if (((per.w(ad:0x40009000+0xC0+0x1C))&0x80)==0x00) group.word (0xC0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0xC0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif else if (((per.w(ad:0x40009000+0xC0+0x1C))&0x80)==0x00) group.word (0xC0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0xC0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" endif newline bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif endif if (((per.w(ad:0x40009000+0xC0+0x1E))&0x8000)==0x00) group.word (0xC0+0x1E)++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0xC0+0x1E)++0x01 line.word 0x00 "BITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK60D*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif endif tree.end tree "Channel 7" width 23. group.long 0xE0++0x03 line.long 0x00 "SADDR,TCD Source Address" newline group.word (0xE0+0x04)++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK60DX256ZVMD10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,?..." newline else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif newline if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0xE0+0x08)++0x03 line.long 0x00 "NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0xE0+0x08))&0xC0000000)==0x00) group.long (0xE0+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0xE0+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0xE0+0x0C)++0x07 line.long 0x00 "SLAST,TCD Last Source Address Adjustment" line.long 0x04 "DADDR,TCD Destination Address" newline group.word (0xE0+0x14)++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if (((per.w(ad:0x40009000+0xE0+0x16))&0x8000)==0x00) group.word (0xE0+0x16)++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0xE0+0x16)++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif newline group.long (0xE0+0x18)++0x03 line.long 0x00 "DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" newline if ((((per.w(ad:0x40009000+0xE0+0x1E))&0x8000)==0x00)&&(((per.w(ad:0x40009000+0xE0+0x1E))&0x7FFF)==0x01))||((((per.w(ad:0x40009000+0xE0+0x1E))&0x8000)==0x8000)&&(((per.w(ad:0x40009000+0xE0+0x1E))&0x1FF)==0x01)) if (((per.w(ad:0x40009000+0xE0+0x1C))&0x80)==0x00) group.word (0xE0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0xE0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif else if (((per.w(ad:0x40009000+0xE0+0x1C))&0x80)==0x00) group.word (0xE0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0xE0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" endif newline bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif endif if (((per.w(ad:0x40009000+0xE0+0x1E))&0x8000)==0x00) group.word (0xE0+0x1E)++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0xE0+0x1E)++0x01 line.word 0x00 "BITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK60D*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif endif tree.end tree "Channel 8" width 23. group.long 0x100++0x03 line.long 0x00 "SADDR,TCD Source Address" newline group.word (0x100+0x04)++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK60DX256ZVMD10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,?..." newline else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif newline if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x100+0x08)++0x03 line.long 0x00 "NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x100+0x08))&0xC0000000)==0x00) group.long (0x100+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x100+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x100+0x0C)++0x07 line.long 0x00 "SLAST,TCD Last Source Address Adjustment" line.long 0x04 "DADDR,TCD Destination Address" newline group.word (0x100+0x14)++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if (((per.w(ad:0x40009000+0x100+0x16))&0x8000)==0x00) group.word (0x100+0x16)++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x100+0x16)++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif newline group.long (0x100+0x18)++0x03 line.long 0x00 "DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" newline if ((((per.w(ad:0x40009000+0x100+0x1E))&0x8000)==0x00)&&(((per.w(ad:0x40009000+0x100+0x1E))&0x7FFF)==0x01))||((((per.w(ad:0x40009000+0x100+0x1E))&0x8000)==0x8000)&&(((per.w(ad:0x40009000+0x100+0x1E))&0x1FF)==0x01)) if (((per.w(ad:0x40009000+0x100+0x1C))&0x80)==0x00) group.word (0x100+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x100+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif else if (((per.w(ad:0x40009000+0x100+0x1C))&0x80)==0x00) group.word (0x100+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x100+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" endif newline bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif endif if (((per.w(ad:0x40009000+0x100+0x1E))&0x8000)==0x00) group.word (0x100+0x1E)++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x100+0x1E)++0x01 line.word 0x00 "BITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK60D*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif endif tree.end tree "Channel 9" width 23. group.long 0x120++0x03 line.long 0x00 "SADDR,TCD Source Address" newline group.word (0x120+0x04)++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK60DX256ZVMD10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,?..." newline else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif newline if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x120+0x08)++0x03 line.long 0x00 "NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x120+0x08))&0xC0000000)==0x00) group.long (0x120+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x120+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x120+0x0C)++0x07 line.long 0x00 "SLAST,TCD Last Source Address Adjustment" line.long 0x04 "DADDR,TCD Destination Address" newline group.word (0x120+0x14)++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if (((per.w(ad:0x40009000+0x120+0x16))&0x8000)==0x00) group.word (0x120+0x16)++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x120+0x16)++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif newline group.long (0x120+0x18)++0x03 line.long 0x00 "DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" newline if ((((per.w(ad:0x40009000+0x120+0x1E))&0x8000)==0x00)&&(((per.w(ad:0x40009000+0x120+0x1E))&0x7FFF)==0x01))||((((per.w(ad:0x40009000+0x120+0x1E))&0x8000)==0x8000)&&(((per.w(ad:0x40009000+0x120+0x1E))&0x1FF)==0x01)) if (((per.w(ad:0x40009000+0x120+0x1C))&0x80)==0x00) group.word (0x120+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x120+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif else if (((per.w(ad:0x40009000+0x120+0x1C))&0x80)==0x00) group.word (0x120+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x120+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" endif newline bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif endif if (((per.w(ad:0x40009000+0x120+0x1E))&0x8000)==0x00) group.word (0x120+0x1E)++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x120+0x1E)++0x01 line.word 0x00 "BITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK60D*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif endif tree.end tree "Channel 10" width 23. group.long 0x140++0x03 line.long 0x00 "SADDR,TCD Source Address" newline group.word (0x140+0x04)++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK60DX256ZVMD10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,?..." newline else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif newline if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x140+0x08)++0x03 line.long 0x00 "NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x140+0x08))&0xC0000000)==0x00) group.long (0x140+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x140+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x140+0x0C)++0x07 line.long 0x00 "SLAST,TCD Last Source Address Adjustment" line.long 0x04 "DADDR,TCD Destination Address" newline group.word (0x140+0x14)++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if (((per.w(ad:0x40009000+0x140+0x16))&0x8000)==0x00) group.word (0x140+0x16)++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x140+0x16)++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif newline group.long (0x140+0x18)++0x03 line.long 0x00 "DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" newline if ((((per.w(ad:0x40009000+0x140+0x1E))&0x8000)==0x00)&&(((per.w(ad:0x40009000+0x140+0x1E))&0x7FFF)==0x01))||((((per.w(ad:0x40009000+0x140+0x1E))&0x8000)==0x8000)&&(((per.w(ad:0x40009000+0x140+0x1E))&0x1FF)==0x01)) if (((per.w(ad:0x40009000+0x140+0x1C))&0x80)==0x00) group.word (0x140+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x140+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif else if (((per.w(ad:0x40009000+0x140+0x1C))&0x80)==0x00) group.word (0x140+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x140+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" endif newline bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif endif if (((per.w(ad:0x40009000+0x140+0x1E))&0x8000)==0x00) group.word (0x140+0x1E)++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x140+0x1E)++0x01 line.word 0x00 "BITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK60D*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif endif tree.end tree "Channel 11" width 23. group.long 0x160++0x03 line.long 0x00 "SADDR,TCD Source Address" newline group.word (0x160+0x04)++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK60DX256ZVMD10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,?..." newline else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif newline if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x160+0x08)++0x03 line.long 0x00 "NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x160+0x08))&0xC0000000)==0x00) group.long (0x160+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x160+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x160+0x0C)++0x07 line.long 0x00 "SLAST,TCD Last Source Address Adjustment" line.long 0x04 "DADDR,TCD Destination Address" newline group.word (0x160+0x14)++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if (((per.w(ad:0x40009000+0x160+0x16))&0x8000)==0x00) group.word (0x160+0x16)++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x160+0x16)++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif newline group.long (0x160+0x18)++0x03 line.long 0x00 "DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" newline if ((((per.w(ad:0x40009000+0x160+0x1E))&0x8000)==0x00)&&(((per.w(ad:0x40009000+0x160+0x1E))&0x7FFF)==0x01))||((((per.w(ad:0x40009000+0x160+0x1E))&0x8000)==0x8000)&&(((per.w(ad:0x40009000+0x160+0x1E))&0x1FF)==0x01)) if (((per.w(ad:0x40009000+0x160+0x1C))&0x80)==0x00) group.word (0x160+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x160+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif else if (((per.w(ad:0x40009000+0x160+0x1C))&0x80)==0x00) group.word (0x160+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x160+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" endif newline bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif endif if (((per.w(ad:0x40009000+0x160+0x1E))&0x8000)==0x00) group.word (0x160+0x1E)++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x160+0x1E)++0x01 line.word 0x00 "BITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK60D*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif endif tree.end tree "Channel 12" width 23. group.long 0x180++0x03 line.long 0x00 "SADDR,TCD Source Address" newline group.word (0x180+0x04)++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK60DX256ZVMD10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,?..." newline else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif newline if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x180+0x08)++0x03 line.long 0x00 "NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x180+0x08))&0xC0000000)==0x00) group.long (0x180+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x180+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x180+0x0C)++0x07 line.long 0x00 "SLAST,TCD Last Source Address Adjustment" line.long 0x04 "DADDR,TCD Destination Address" newline group.word (0x180+0x14)++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if (((per.w(ad:0x40009000+0x180+0x16))&0x8000)==0x00) group.word (0x180+0x16)++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x180+0x16)++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif newline group.long (0x180+0x18)++0x03 line.long 0x00 "DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" newline if ((((per.w(ad:0x40009000+0x180+0x1E))&0x8000)==0x00)&&(((per.w(ad:0x40009000+0x180+0x1E))&0x7FFF)==0x01))||((((per.w(ad:0x40009000+0x180+0x1E))&0x8000)==0x8000)&&(((per.w(ad:0x40009000+0x180+0x1E))&0x1FF)==0x01)) if (((per.w(ad:0x40009000+0x180+0x1C))&0x80)==0x00) group.word (0x180+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x180+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif else if (((per.w(ad:0x40009000+0x180+0x1C))&0x80)==0x00) group.word (0x180+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x180+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" endif newline bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif endif if (((per.w(ad:0x40009000+0x180+0x1E))&0x8000)==0x00) group.word (0x180+0x1E)++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x180+0x1E)++0x01 line.word 0x00 "BITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK60D*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif endif tree.end tree "Channel 13" width 23. group.long 0x1A0++0x03 line.long 0x00 "SADDR,TCD Source Address" newline group.word (0x1A0+0x04)++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK60DX256ZVMD10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,?..." newline else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif newline if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x1A0+0x08)++0x03 line.long 0x00 "NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x1A0+0x08))&0xC0000000)==0x00) group.long (0x1A0+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x1A0+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x1A0+0x0C)++0x07 line.long 0x00 "SLAST,TCD Last Source Address Adjustment" line.long 0x04 "DADDR,TCD Destination Address" newline group.word (0x1A0+0x14)++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if (((per.w(ad:0x40009000+0x1A0+0x16))&0x8000)==0x00) group.word (0x1A0+0x16)++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x1A0+0x16)++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif newline group.long (0x1A0+0x18)++0x03 line.long 0x00 "DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" newline if ((((per.w(ad:0x40009000+0x1A0+0x1E))&0x8000)==0x00)&&(((per.w(ad:0x40009000+0x1A0+0x1E))&0x7FFF)==0x01))||((((per.w(ad:0x40009000+0x1A0+0x1E))&0x8000)==0x8000)&&(((per.w(ad:0x40009000+0x1A0+0x1E))&0x1FF)==0x01)) if (((per.w(ad:0x40009000+0x1A0+0x1C))&0x80)==0x00) group.word (0x1A0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x1A0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif else if (((per.w(ad:0x40009000+0x1A0+0x1C))&0x80)==0x00) group.word (0x1A0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x1A0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" endif newline bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif endif if (((per.w(ad:0x40009000+0x1A0+0x1E))&0x8000)==0x00) group.word (0x1A0+0x1E)++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x1A0+0x1E)++0x01 line.word 0x00 "BITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK60D*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif endif tree.end tree "Channel 14" width 23. group.long 0x1C0++0x03 line.long 0x00 "SADDR,TCD Source Address" newline group.word (0x1C0+0x04)++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK60DX256ZVMD10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,?..." newline else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif newline if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x1C0+0x08)++0x03 line.long 0x00 "NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x1C0+0x08))&0xC0000000)==0x00) group.long (0x1C0+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x1C0+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x1C0+0x0C)++0x07 line.long 0x00 "SLAST,TCD Last Source Address Adjustment" line.long 0x04 "DADDR,TCD Destination Address" newline group.word (0x1C0+0x14)++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if (((per.w(ad:0x40009000+0x1C0+0x16))&0x8000)==0x00) group.word (0x1C0+0x16)++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x1C0+0x16)++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif newline group.long (0x1C0+0x18)++0x03 line.long 0x00 "DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" newline if ((((per.w(ad:0x40009000+0x1C0+0x1E))&0x8000)==0x00)&&(((per.w(ad:0x40009000+0x1C0+0x1E))&0x7FFF)==0x01))||((((per.w(ad:0x40009000+0x1C0+0x1E))&0x8000)==0x8000)&&(((per.w(ad:0x40009000+0x1C0+0x1E))&0x1FF)==0x01)) if (((per.w(ad:0x40009000+0x1C0+0x1C))&0x80)==0x00) group.word (0x1C0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x1C0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif else if (((per.w(ad:0x40009000+0x1C0+0x1C))&0x80)==0x00) group.word (0x1C0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x1C0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" endif newline bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif endif if (((per.w(ad:0x40009000+0x1C0+0x1E))&0x8000)==0x00) group.word (0x1C0+0x1E)++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x1C0+0x1E)++0x01 line.word 0x00 "BITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK60D*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif endif tree.end tree "Channel 15" width 23. group.long 0x1E0++0x03 line.long 0x00 "SADDR,TCD Source Address" newline group.word (0x1E0+0x04)++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK60DX256ZVMD10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,?..." newline else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif newline if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x1E0+0x08)++0x03 line.long 0x00 "NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x1E0+0x08))&0xC0000000)==0x00) group.long (0x1E0+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x1E0+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x1E0+0x0C)++0x07 line.long 0x00 "SLAST,TCD Last Source Address Adjustment" line.long 0x04 "DADDR,TCD Destination Address" newline group.word (0x1E0+0x14)++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if (((per.w(ad:0x40009000+0x1E0+0x16))&0x8000)==0x00) group.word (0x1E0+0x16)++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x1E0+0x16)++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif newline group.long (0x1E0+0x18)++0x03 line.long 0x00 "DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" newline if ((((per.w(ad:0x40009000+0x1E0+0x1E))&0x8000)==0x00)&&(((per.w(ad:0x40009000+0x1E0+0x1E))&0x7FFF)==0x01))||((((per.w(ad:0x40009000+0x1E0+0x1E))&0x8000)==0x8000)&&(((per.w(ad:0x40009000+0x1E0+0x1E))&0x1FF)==0x01)) if (((per.w(ad:0x40009000+0x1E0+0x1C))&0x80)==0x00) group.word (0x1E0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x1E0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif else if (((per.w(ad:0x40009000+0x1E0+0x1C))&0x80)==0x00) group.word (0x1E0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x1E0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" endif newline bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif endif if (((per.w(ad:0x40009000+0x1E0+0x1E))&0x8000)==0x00) group.word (0x1E0+0x1E)++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x1E0+0x1E)++0x01 line.word 0x00 "BITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK60D*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif endif tree.end tree "Channel 16" width 23. group.long 0x200++0x03 line.long 0x00 "SADDR,TCD Source Address" newline group.word (0x200+0x04)++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK60DX256ZVMD10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,?..." newline else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif newline if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x200+0x08)++0x03 line.long 0x00 "NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x200+0x08))&0xC0000000)==0x00) group.long (0x200+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x200+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x200+0x0C)++0x07 line.long 0x00 "SLAST,TCD Last Source Address Adjustment" line.long 0x04 "DADDR,TCD Destination Address" newline group.word (0x200+0x14)++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if (((per.w(ad:0x40009000+0x200+0x16))&0x8000)==0x00) group.word (0x200+0x16)++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x200+0x16)++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif newline group.long (0x200+0x18)++0x03 line.long 0x00 "DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" newline if ((((per.w(ad:0x40009000+0x200+0x1E))&0x8000)==0x00)&&(((per.w(ad:0x40009000+0x200+0x1E))&0x7FFF)==0x01))||((((per.w(ad:0x40009000+0x200+0x1E))&0x8000)==0x8000)&&(((per.w(ad:0x40009000+0x200+0x1E))&0x1FF)==0x01)) if (((per.w(ad:0x40009000+0x200+0x1C))&0x80)==0x00) group.word (0x200+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x200+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif else if (((per.w(ad:0x40009000+0x200+0x1C))&0x80)==0x00) group.word (0x200+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x200+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" endif newline bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif endif if (((per.w(ad:0x40009000+0x200+0x1E))&0x8000)==0x00) group.word (0x200+0x1E)++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x200+0x1E)++0x01 line.word 0x00 "BITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK60D*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif endif tree.end tree "Channel 17" width 23. group.long 0x220++0x03 line.long 0x00 "SADDR,TCD Source Address" newline group.word (0x220+0x04)++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK60DX256ZVMD10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,?..." newline else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif newline if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x220+0x08)++0x03 line.long 0x00 "NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x220+0x08))&0xC0000000)==0x00) group.long (0x220+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x220+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x220+0x0C)++0x07 line.long 0x00 "SLAST,TCD Last Source Address Adjustment" line.long 0x04 "DADDR,TCD Destination Address" newline group.word (0x220+0x14)++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if (((per.w(ad:0x40009000+0x220+0x16))&0x8000)==0x00) group.word (0x220+0x16)++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x220+0x16)++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif newline group.long (0x220+0x18)++0x03 line.long 0x00 "DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" newline if ((((per.w(ad:0x40009000+0x220+0x1E))&0x8000)==0x00)&&(((per.w(ad:0x40009000+0x220+0x1E))&0x7FFF)==0x01))||((((per.w(ad:0x40009000+0x220+0x1E))&0x8000)==0x8000)&&(((per.w(ad:0x40009000+0x220+0x1E))&0x1FF)==0x01)) if (((per.w(ad:0x40009000+0x220+0x1C))&0x80)==0x00) group.word (0x220+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x220+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif else if (((per.w(ad:0x40009000+0x220+0x1C))&0x80)==0x00) group.word (0x220+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x220+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" endif newline bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif endif if (((per.w(ad:0x40009000+0x220+0x1E))&0x8000)==0x00) group.word (0x220+0x1E)++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x220+0x1E)++0x01 line.word 0x00 "BITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK60D*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif endif tree.end tree "Channel 18" width 23. group.long 0x240++0x03 line.long 0x00 "SADDR,TCD Source Address" newline group.word (0x240+0x04)++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK60DX256ZVMD10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,?..." newline else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif newline if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x240+0x08)++0x03 line.long 0x00 "NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x240+0x08))&0xC0000000)==0x00) group.long (0x240+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x240+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x240+0x0C)++0x07 line.long 0x00 "SLAST,TCD Last Source Address Adjustment" line.long 0x04 "DADDR,TCD Destination Address" newline group.word (0x240+0x14)++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if (((per.w(ad:0x40009000+0x240+0x16))&0x8000)==0x00) group.word (0x240+0x16)++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x240+0x16)++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif newline group.long (0x240+0x18)++0x03 line.long 0x00 "DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" newline if ((((per.w(ad:0x40009000+0x240+0x1E))&0x8000)==0x00)&&(((per.w(ad:0x40009000+0x240+0x1E))&0x7FFF)==0x01))||((((per.w(ad:0x40009000+0x240+0x1E))&0x8000)==0x8000)&&(((per.w(ad:0x40009000+0x240+0x1E))&0x1FF)==0x01)) if (((per.w(ad:0x40009000+0x240+0x1C))&0x80)==0x00) group.word (0x240+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x240+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif else if (((per.w(ad:0x40009000+0x240+0x1C))&0x80)==0x00) group.word (0x240+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x240+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" endif newline bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif endif if (((per.w(ad:0x40009000+0x240+0x1E))&0x8000)==0x00) group.word (0x240+0x1E)++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x240+0x1E)++0x01 line.word 0x00 "BITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK60D*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif endif tree.end tree "Channel 19" width 23. group.long 0x260++0x03 line.long 0x00 "SADDR,TCD Source Address" newline group.word (0x260+0x04)++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK60DX256ZVMD10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,?..." newline else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif newline if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x260+0x08)++0x03 line.long 0x00 "NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x260+0x08))&0xC0000000)==0x00) group.long (0x260+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x260+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x260+0x0C)++0x07 line.long 0x00 "SLAST,TCD Last Source Address Adjustment" line.long 0x04 "DADDR,TCD Destination Address" newline group.word (0x260+0x14)++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if (((per.w(ad:0x40009000+0x260+0x16))&0x8000)==0x00) group.word (0x260+0x16)++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x260+0x16)++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif newline group.long (0x260+0x18)++0x03 line.long 0x00 "DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" newline if ((((per.w(ad:0x40009000+0x260+0x1E))&0x8000)==0x00)&&(((per.w(ad:0x40009000+0x260+0x1E))&0x7FFF)==0x01))||((((per.w(ad:0x40009000+0x260+0x1E))&0x8000)==0x8000)&&(((per.w(ad:0x40009000+0x260+0x1E))&0x1FF)==0x01)) if (((per.w(ad:0x40009000+0x260+0x1C))&0x80)==0x00) group.word (0x260+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x260+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif else if (((per.w(ad:0x40009000+0x260+0x1C))&0x80)==0x00) group.word (0x260+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x260+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" endif newline bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif endif if (((per.w(ad:0x40009000+0x260+0x1E))&0x8000)==0x00) group.word (0x260+0x1E)++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x260+0x1E)++0x01 line.word 0x00 "BITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK60D*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif endif tree.end tree "Channel 20" width 23. group.long 0x280++0x03 line.long 0x00 "SADDR,TCD Source Address" newline group.word (0x280+0x04)++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK60DX256ZVMD10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,?..." newline else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif newline if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x280+0x08)++0x03 line.long 0x00 "NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x280+0x08))&0xC0000000)==0x00) group.long (0x280+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x280+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x280+0x0C)++0x07 line.long 0x00 "SLAST,TCD Last Source Address Adjustment" line.long 0x04 "DADDR,TCD Destination Address" newline group.word (0x280+0x14)++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if (((per.w(ad:0x40009000+0x280+0x16))&0x8000)==0x00) group.word (0x280+0x16)++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x280+0x16)++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif newline group.long (0x280+0x18)++0x03 line.long 0x00 "DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" newline if ((((per.w(ad:0x40009000+0x280+0x1E))&0x8000)==0x00)&&(((per.w(ad:0x40009000+0x280+0x1E))&0x7FFF)==0x01))||((((per.w(ad:0x40009000+0x280+0x1E))&0x8000)==0x8000)&&(((per.w(ad:0x40009000+0x280+0x1E))&0x1FF)==0x01)) if (((per.w(ad:0x40009000+0x280+0x1C))&0x80)==0x00) group.word (0x280+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x280+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif else if (((per.w(ad:0x40009000+0x280+0x1C))&0x80)==0x00) group.word (0x280+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x280+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" endif newline bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif endif if (((per.w(ad:0x40009000+0x280+0x1E))&0x8000)==0x00) group.word (0x280+0x1E)++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x280+0x1E)++0x01 line.word 0x00 "BITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK60D*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif endif tree.end tree "Channel 21" width 23. group.long 0x2A0++0x03 line.long 0x00 "SADDR,TCD Source Address" newline group.word (0x2A0+0x04)++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK60DX256ZVMD10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,?..." newline else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif newline if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x2A0+0x08)++0x03 line.long 0x00 "NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x2A0+0x08))&0xC0000000)==0x00) group.long (0x2A0+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x2A0+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x2A0+0x0C)++0x07 line.long 0x00 "SLAST,TCD Last Source Address Adjustment" line.long 0x04 "DADDR,TCD Destination Address" newline group.word (0x2A0+0x14)++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if (((per.w(ad:0x40009000+0x2A0+0x16))&0x8000)==0x00) group.word (0x2A0+0x16)++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x2A0+0x16)++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif newline group.long (0x2A0+0x18)++0x03 line.long 0x00 "DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" newline if ((((per.w(ad:0x40009000+0x2A0+0x1E))&0x8000)==0x00)&&(((per.w(ad:0x40009000+0x2A0+0x1E))&0x7FFF)==0x01))||((((per.w(ad:0x40009000+0x2A0+0x1E))&0x8000)==0x8000)&&(((per.w(ad:0x40009000+0x2A0+0x1E))&0x1FF)==0x01)) if (((per.w(ad:0x40009000+0x2A0+0x1C))&0x80)==0x00) group.word (0x2A0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x2A0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif else if (((per.w(ad:0x40009000+0x2A0+0x1C))&0x80)==0x00) group.word (0x2A0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x2A0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" endif newline bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif endif if (((per.w(ad:0x40009000+0x2A0+0x1E))&0x8000)==0x00) group.word (0x2A0+0x1E)++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x2A0+0x1E)++0x01 line.word 0x00 "BITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK60D*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif endif tree.end tree "Channel 22" width 23. group.long 0x2C0++0x03 line.long 0x00 "SADDR,TCD Source Address" newline group.word (0x2C0+0x04)++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK60DX256ZVMD10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,?..." newline else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif newline if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x2C0+0x08)++0x03 line.long 0x00 "NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x2C0+0x08))&0xC0000000)==0x00) group.long (0x2C0+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x2C0+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x2C0+0x0C)++0x07 line.long 0x00 "SLAST,TCD Last Source Address Adjustment" line.long 0x04 "DADDR,TCD Destination Address" newline group.word (0x2C0+0x14)++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if (((per.w(ad:0x40009000+0x2C0+0x16))&0x8000)==0x00) group.word (0x2C0+0x16)++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x2C0+0x16)++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif newline group.long (0x2C0+0x18)++0x03 line.long 0x00 "DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" newline if ((((per.w(ad:0x40009000+0x2C0+0x1E))&0x8000)==0x00)&&(((per.w(ad:0x40009000+0x2C0+0x1E))&0x7FFF)==0x01))||((((per.w(ad:0x40009000+0x2C0+0x1E))&0x8000)==0x8000)&&(((per.w(ad:0x40009000+0x2C0+0x1E))&0x1FF)==0x01)) if (((per.w(ad:0x40009000+0x2C0+0x1C))&0x80)==0x00) group.word (0x2C0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x2C0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif else if (((per.w(ad:0x40009000+0x2C0+0x1C))&0x80)==0x00) group.word (0x2C0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x2C0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" endif newline bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif endif if (((per.w(ad:0x40009000+0x2C0+0x1E))&0x8000)==0x00) group.word (0x2C0+0x1E)++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x2C0+0x1E)++0x01 line.word 0x00 "BITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK60D*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif endif tree.end tree "Channel 23" width 23. group.long 0x2E0++0x03 line.long 0x00 "SADDR,TCD Source Address" newline group.word (0x2E0+0x04)++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK60DX256ZVMD10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,?..." newline else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif newline if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x2E0+0x08)++0x03 line.long 0x00 "NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x2E0+0x08))&0xC0000000)==0x00) group.long (0x2E0+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x2E0+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x2E0+0x0C)++0x07 line.long 0x00 "SLAST,TCD Last Source Address Adjustment" line.long 0x04 "DADDR,TCD Destination Address" newline group.word (0x2E0+0x14)++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if (((per.w(ad:0x40009000+0x2E0+0x16))&0x8000)==0x00) group.word (0x2E0+0x16)++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x2E0+0x16)++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif newline group.long (0x2E0+0x18)++0x03 line.long 0x00 "DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" newline if ((((per.w(ad:0x40009000+0x2E0+0x1E))&0x8000)==0x00)&&(((per.w(ad:0x40009000+0x2E0+0x1E))&0x7FFF)==0x01))||((((per.w(ad:0x40009000+0x2E0+0x1E))&0x8000)==0x8000)&&(((per.w(ad:0x40009000+0x2E0+0x1E))&0x1FF)==0x01)) if (((per.w(ad:0x40009000+0x2E0+0x1C))&0x80)==0x00) group.word (0x2E0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x2E0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif else if (((per.w(ad:0x40009000+0x2E0+0x1C))&0x80)==0x00) group.word (0x2E0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x2E0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" endif newline bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif endif if (((per.w(ad:0x40009000+0x2E0+0x1E))&0x8000)==0x00) group.word (0x2E0+0x1E)++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x2E0+0x1E)++0x01 line.word 0x00 "BITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK60D*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif endif tree.end tree "Channel 24" width 23. group.long 0x300++0x03 line.long 0x00 "SADDR,TCD Source Address" newline group.word (0x300+0x04)++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK60DX256ZVMD10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,?..." newline else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif newline if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x300+0x08)++0x03 line.long 0x00 "NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x300+0x08))&0xC0000000)==0x00) group.long (0x300+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x300+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x300+0x0C)++0x07 line.long 0x00 "SLAST,TCD Last Source Address Adjustment" line.long 0x04 "DADDR,TCD Destination Address" newline group.word (0x300+0x14)++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if (((per.w(ad:0x40009000+0x300+0x16))&0x8000)==0x00) group.word (0x300+0x16)++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x300+0x16)++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif newline group.long (0x300+0x18)++0x03 line.long 0x00 "DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" newline if ((((per.w(ad:0x40009000+0x300+0x1E))&0x8000)==0x00)&&(((per.w(ad:0x40009000+0x300+0x1E))&0x7FFF)==0x01))||((((per.w(ad:0x40009000+0x300+0x1E))&0x8000)==0x8000)&&(((per.w(ad:0x40009000+0x300+0x1E))&0x1FF)==0x01)) if (((per.w(ad:0x40009000+0x300+0x1C))&0x80)==0x00) group.word (0x300+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x300+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif else if (((per.w(ad:0x40009000+0x300+0x1C))&0x80)==0x00) group.word (0x300+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x300+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" endif newline bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif endif if (((per.w(ad:0x40009000+0x300+0x1E))&0x8000)==0x00) group.word (0x300+0x1E)++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x300+0x1E)++0x01 line.word 0x00 "BITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK60D*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif endif tree.end tree "Channel 25" width 23. group.long 0x320++0x03 line.long 0x00 "SADDR,TCD Source Address" newline group.word (0x320+0x04)++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK60DX256ZVMD10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,?..." newline else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif newline if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x320+0x08)++0x03 line.long 0x00 "NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x320+0x08))&0xC0000000)==0x00) group.long (0x320+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x320+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x320+0x0C)++0x07 line.long 0x00 "SLAST,TCD Last Source Address Adjustment" line.long 0x04 "DADDR,TCD Destination Address" newline group.word (0x320+0x14)++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if (((per.w(ad:0x40009000+0x320+0x16))&0x8000)==0x00) group.word (0x320+0x16)++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x320+0x16)++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif newline group.long (0x320+0x18)++0x03 line.long 0x00 "DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" newline if ((((per.w(ad:0x40009000+0x320+0x1E))&0x8000)==0x00)&&(((per.w(ad:0x40009000+0x320+0x1E))&0x7FFF)==0x01))||((((per.w(ad:0x40009000+0x320+0x1E))&0x8000)==0x8000)&&(((per.w(ad:0x40009000+0x320+0x1E))&0x1FF)==0x01)) if (((per.w(ad:0x40009000+0x320+0x1C))&0x80)==0x00) group.word (0x320+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x320+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif else if (((per.w(ad:0x40009000+0x320+0x1C))&0x80)==0x00) group.word (0x320+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x320+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" endif newline bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif endif if (((per.w(ad:0x40009000+0x320+0x1E))&0x8000)==0x00) group.word (0x320+0x1E)++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x320+0x1E)++0x01 line.word 0x00 "BITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK60D*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif endif tree.end tree "Channel 26" width 23. group.long 0x340++0x03 line.long 0x00 "SADDR,TCD Source Address" newline group.word (0x340+0x04)++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK60DX256ZVMD10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,?..." newline else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif newline if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x340+0x08)++0x03 line.long 0x00 "NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x340+0x08))&0xC0000000)==0x00) group.long (0x340+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x340+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x340+0x0C)++0x07 line.long 0x00 "SLAST,TCD Last Source Address Adjustment" line.long 0x04 "DADDR,TCD Destination Address" newline group.word (0x340+0x14)++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if (((per.w(ad:0x40009000+0x340+0x16))&0x8000)==0x00) group.word (0x340+0x16)++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x340+0x16)++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif newline group.long (0x340+0x18)++0x03 line.long 0x00 "DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" newline if ((((per.w(ad:0x40009000+0x340+0x1E))&0x8000)==0x00)&&(((per.w(ad:0x40009000+0x340+0x1E))&0x7FFF)==0x01))||((((per.w(ad:0x40009000+0x340+0x1E))&0x8000)==0x8000)&&(((per.w(ad:0x40009000+0x340+0x1E))&0x1FF)==0x01)) if (((per.w(ad:0x40009000+0x340+0x1C))&0x80)==0x00) group.word (0x340+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x340+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif else if (((per.w(ad:0x40009000+0x340+0x1C))&0x80)==0x00) group.word (0x340+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x340+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" endif newline bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif endif if (((per.w(ad:0x40009000+0x340+0x1E))&0x8000)==0x00) group.word (0x340+0x1E)++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x340+0x1E)++0x01 line.word 0x00 "BITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK60D*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif endif tree.end tree "Channel 27" width 23. group.long 0x360++0x03 line.long 0x00 "SADDR,TCD Source Address" newline group.word (0x360+0x04)++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK60DX256ZVMD10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,?..." newline else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif newline if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x360+0x08)++0x03 line.long 0x00 "NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x360+0x08))&0xC0000000)==0x00) group.long (0x360+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x360+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x360+0x0C)++0x07 line.long 0x00 "SLAST,TCD Last Source Address Adjustment" line.long 0x04 "DADDR,TCD Destination Address" newline group.word (0x360+0x14)++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if (((per.w(ad:0x40009000+0x360+0x16))&0x8000)==0x00) group.word (0x360+0x16)++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x360+0x16)++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif newline group.long (0x360+0x18)++0x03 line.long 0x00 "DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" newline if ((((per.w(ad:0x40009000+0x360+0x1E))&0x8000)==0x00)&&(((per.w(ad:0x40009000+0x360+0x1E))&0x7FFF)==0x01))||((((per.w(ad:0x40009000+0x360+0x1E))&0x8000)==0x8000)&&(((per.w(ad:0x40009000+0x360+0x1E))&0x1FF)==0x01)) if (((per.w(ad:0x40009000+0x360+0x1C))&0x80)==0x00) group.word (0x360+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x360+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif else if (((per.w(ad:0x40009000+0x360+0x1C))&0x80)==0x00) group.word (0x360+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x360+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" endif newline bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif endif if (((per.w(ad:0x40009000+0x360+0x1E))&0x8000)==0x00) group.word (0x360+0x1E)++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x360+0x1E)++0x01 line.word 0x00 "BITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK60D*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif endif tree.end tree "Channel 28" width 23. group.long 0x380++0x03 line.long 0x00 "SADDR,TCD Source Address" newline group.word (0x380+0x04)++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK60DX256ZVMD10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,?..." newline else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif newline if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x380+0x08)++0x03 line.long 0x00 "NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x380+0x08))&0xC0000000)==0x00) group.long (0x380+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x380+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x380+0x0C)++0x07 line.long 0x00 "SLAST,TCD Last Source Address Adjustment" line.long 0x04 "DADDR,TCD Destination Address" newline group.word (0x380+0x14)++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if (((per.w(ad:0x40009000+0x380+0x16))&0x8000)==0x00) group.word (0x380+0x16)++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x380+0x16)++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif newline group.long (0x380+0x18)++0x03 line.long 0x00 "DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" newline if ((((per.w(ad:0x40009000+0x380+0x1E))&0x8000)==0x00)&&(((per.w(ad:0x40009000+0x380+0x1E))&0x7FFF)==0x01))||((((per.w(ad:0x40009000+0x380+0x1E))&0x8000)==0x8000)&&(((per.w(ad:0x40009000+0x380+0x1E))&0x1FF)==0x01)) if (((per.w(ad:0x40009000+0x380+0x1C))&0x80)==0x00) group.word (0x380+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x380+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif else if (((per.w(ad:0x40009000+0x380+0x1C))&0x80)==0x00) group.word (0x380+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x380+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" endif newline bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif endif if (((per.w(ad:0x40009000+0x380+0x1E))&0x8000)==0x00) group.word (0x380+0x1E)++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x380+0x1E)++0x01 line.word 0x00 "BITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK60D*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif endif tree.end tree "Channel 29" width 23. group.long 0x3A0++0x03 line.long 0x00 "SADDR,TCD Source Address" newline group.word (0x3A0+0x04)++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK60DX256ZVMD10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,?..." newline else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif newline if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x3A0+0x08)++0x03 line.long 0x00 "NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x3A0+0x08))&0xC0000000)==0x00) group.long (0x3A0+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x3A0+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x3A0+0x0C)++0x07 line.long 0x00 "SLAST,TCD Last Source Address Adjustment" line.long 0x04 "DADDR,TCD Destination Address" newline group.word (0x3A0+0x14)++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if (((per.w(ad:0x40009000+0x3A0+0x16))&0x8000)==0x00) group.word (0x3A0+0x16)++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x3A0+0x16)++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif newline group.long (0x3A0+0x18)++0x03 line.long 0x00 "DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" newline if ((((per.w(ad:0x40009000+0x3A0+0x1E))&0x8000)==0x00)&&(((per.w(ad:0x40009000+0x3A0+0x1E))&0x7FFF)==0x01))||((((per.w(ad:0x40009000+0x3A0+0x1E))&0x8000)==0x8000)&&(((per.w(ad:0x40009000+0x3A0+0x1E))&0x1FF)==0x01)) if (((per.w(ad:0x40009000+0x3A0+0x1C))&0x80)==0x00) group.word (0x3A0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x3A0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif else if (((per.w(ad:0x40009000+0x3A0+0x1C))&0x80)==0x00) group.word (0x3A0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x3A0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" endif newline bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif endif if (((per.w(ad:0x40009000+0x3A0+0x1E))&0x8000)==0x00) group.word (0x3A0+0x1E)++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x3A0+0x1E)++0x01 line.word 0x00 "BITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK60D*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif endif tree.end tree "Channel 30" width 23. group.long 0x3C0++0x03 line.long 0x00 "SADDR,TCD Source Address" newline group.word (0x3C0+0x04)++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK60DX256ZVMD10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,?..." newline else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif newline if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x3C0+0x08)++0x03 line.long 0x00 "NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x3C0+0x08))&0xC0000000)==0x00) group.long (0x3C0+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x3C0+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x3C0+0x0C)++0x07 line.long 0x00 "SLAST,TCD Last Source Address Adjustment" line.long 0x04 "DADDR,TCD Destination Address" newline group.word (0x3C0+0x14)++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if (((per.w(ad:0x40009000+0x3C0+0x16))&0x8000)==0x00) group.word (0x3C0+0x16)++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x3C0+0x16)++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif newline group.long (0x3C0+0x18)++0x03 line.long 0x00 "DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" newline if ((((per.w(ad:0x40009000+0x3C0+0x1E))&0x8000)==0x00)&&(((per.w(ad:0x40009000+0x3C0+0x1E))&0x7FFF)==0x01))||((((per.w(ad:0x40009000+0x3C0+0x1E))&0x8000)==0x8000)&&(((per.w(ad:0x40009000+0x3C0+0x1E))&0x1FF)==0x01)) if (((per.w(ad:0x40009000+0x3C0+0x1C))&0x80)==0x00) group.word (0x3C0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x3C0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif else if (((per.w(ad:0x40009000+0x3C0+0x1C))&0x80)==0x00) group.word (0x3C0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x3C0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" endif newline bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif endif if (((per.w(ad:0x40009000+0x3C0+0x1E))&0x8000)==0x00) group.word (0x3C0+0x1E)++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x3C0+0x1E)++0x01 line.word 0x00 "BITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK60D*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif endif tree.end tree "Channel 31" width 23. group.long 0x3E0++0x03 line.long 0x00 "SADDR,TCD Source Address" newline group.word (0x3E0+0x04)++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK60DX256ZVMD10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,?..." newline else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif newline if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x3E0+0x08)++0x03 line.long 0x00 "NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x3E0+0x08))&0xC0000000)==0x00) group.long (0x3E0+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x3E0+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x3E0+0x0C)++0x07 line.long 0x00 "SLAST,TCD Last Source Address Adjustment" line.long 0x04 "DADDR,TCD Destination Address" newline group.word (0x3E0+0x14)++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if (((per.w(ad:0x40009000+0x3E0+0x16))&0x8000)==0x00) group.word (0x3E0+0x16)++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x3E0+0x16)++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif newline group.long (0x3E0+0x18)++0x03 line.long 0x00 "DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" newline if ((((per.w(ad:0x40009000+0x3E0+0x1E))&0x8000)==0x00)&&(((per.w(ad:0x40009000+0x3E0+0x1E))&0x7FFF)==0x01))||((((per.w(ad:0x40009000+0x3E0+0x1E))&0x8000)==0x8000)&&(((per.w(ad:0x40009000+0x3E0+0x1E))&0x1FF)==0x01)) if (((per.w(ad:0x40009000+0x3E0+0x1C))&0x80)==0x00) group.word (0x3E0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x3E0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif else if (((per.w(ad:0x40009000+0x3E0+0x1C))&0x80)==0x00) group.word (0x3E0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x3E0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" endif newline bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif endif if (((per.w(ad:0x40009000+0x3E0+0x1E))&0x8000)==0x00) group.word (0x3E0+0x1E)++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x3E0+0x1E)++0x01 line.word 0x00 "BITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK60D*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif endif tree.end tree.end width 0x0B tree.end tree "EWM (External Watchdog Monitor)" base ad:0x40061000 width 14. group.byte 0x00++0x00 line.byte 0x00 "CTRL,Control Register" sif !cpuis("MK60*AB10")&&!cpuis("MK20DN512*AB10R")&&!cpuis("MK10DN512ZV??10*")&&!cpuis("MK10DX256ZV??10*")&&!cpuis("MK30DN512ZVLK10")&&!cpuis("MK30DN512ZVLQ10")&&!cpuis("MK30DN512ZVLQ10R")&&!cpuis("MK30DX256ZVLQ10")&&!cpuis("MK40D*Z*10")&&!cpuis("MK50DN512ZCLL10")&&!cpuis("MK50DX256ZCLL10")&&!cpuis("MK50DN512ZCLQ10")&&!cpuis("MK50DX256ZCLQ10")&&!cpuis("MK51DN512ZCLL10")&&!cpuis("MK51DN512ZCMC10")&&!cpuis("MK51DX256ZCMC10")&&!cpuis("MK51DN256ZCMD10")&&!cpuis("MK51DN512ZCLQ10")&&!cpuis("MK52DN512ZCLQ10")&&!cpuis("MK52DN512ZCMD10")&&!cpuis("MK53DN512ZCLQ10")&&!cpuis("MK53DN512ZCMD10")&&!cpuis("MK53DX256ZCLQ10")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZCAB10R")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVLQ10R")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("KK60DN512ZCAB10R") bitfld.byte 0x00 3. " INTEN ,Interrupt enable" "Disabled,Enabled" endif bitfld.byte 0x00 2. " INEN ,Enables the EWM_in port" "Disabled,Enabled" bitfld.byte 0x00 1. " ASSIN ,Inverts the assert state to a logic one" "Not inverted,Inverted" bitfld.byte 0x00 0. " EWMEN ,EWM module enable" "Disabled,Enabled" wgroup.byte 0x01++0x00 line.byte 0x00 "SERV,Service Register" group.byte 0x02++0x01 line.byte 0x00 "CMPL,Compare Low Register" line.byte 0x01 "CMPH,Compare High Register" sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK27FN2M0VMI15") group.byte 0x04++0x00 line.byte 0x00 "CLKCTRL,Clock Control Register" bitfld.byte 0x00 0.--1. " CLKSEL ,Low power clock source select" "lpo_clk[0],lpo_clk[1],lpo_clk[2],lpo_clk[3]" endif sif !cpuis("MK40D*Z*10")&&!cpuis("KK60FN1M0VLQ15")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") sif cpuis("MK40D*10")||cpuis("MK5?D*10")||cpuis("MK60D*10")||cpuis("MK02*")||cpuis("MK22FN256*")||cpuis("MK22FN128*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20DX256VLQ10R")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK20DN512VLK10R")||cpuis("MK22FN128VLH10R")||cpuis("MK27FN2M0VMI15")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK20DX256VLK10R") group.byte 0x05++0x00 line.byte 0x00 "CLKPRESCALER,Clock Prescaler Register" endif endif width 0x0B tree.end tree "WDOG (Watchdog Timer)" base ad:0x40052000 width 9. group.word 0x00++0x17 line.word 0x00 "STCTRLH,Watchdog Status And Control Register High" bitfld.word 0x00 14. " DISTESTWDOG ,WDOG functional test mode disable" "No,Yes" bitfld.word 0x00 12.--13. " BYTESEL ,Select the byte to be tested" "Byte 0,Byte 1,Byte 2,Byte 3" bitfld.word 0x00 11. " TESTSEL ,Selects the test to be run on the watchdog timer" "Quick test,Byte test" newline bitfld.word 0x00 10. " TESTWDOG ,Functional test mode enable" "Disabled,Enabled" sif cpuis("MK20DN512*AB10R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK40D*Z*10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK60DX256ZVMC10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10")||cpuis("MK20DX256ZVLQ10R")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("KK60DN512ZCAB10R") newline bitfld.word 0x00 8. " STNDBYEN ,Enables WDOG in standby mode" "Disabled,Enabled" endif newline bitfld.word 0x00 7. " WAIT_EN ,Enables WDOG in wait mode" "Disabled,Enabled" bitfld.word 0x00 6. " STOPEN ,Enables WDOG in stop mode" "Disabled,Enabled" bitfld.word 0x00 5. " DBGEN ,Enables WDOG in debug mode" "Disabled,Enabled" newline bitfld.word 0x00 4. " ALLOWUPDATE ,Enables updates to watchdog write once registers" "Disabled,Enabled" bitfld.word 0x00 3. " WINEN ,Enable windowing mode" "Disabled,Enabled" bitfld.word 0x00 2. " IRQRSTEN ,Enable the debug breadcrumbs feature" "Disabled,Enabled" newline bitfld.word 0x00 1. " CLKSRC ,Selects clock source for the WDOG timer and other internal timing operations" "LPO Osc,Alternate" bitfld.word 0x00 0. " WDOGEN ,Enables the WDOG operation" "Disabled,Enabled" line.word 0x02 "STCTRLL,Watchdog Status And Control Register Low" eventfld.word 0x02 15. " INTFLG ,Interrupt flag" "No interrupt,Interrupt" line.word 0x04 "TOVALH,Watchdog Time-out Value Register High" line.word 0x06 "TOVALL,Watchdog Time-out Value Register Low" line.word 0x08 "WINH,Watchdog Window Register High" line.word 0x0A "WINL,Watchdog Window Register Low" line.word 0x0C "REFRESH,Watchdog Refresh Register" line.word 0x0E "UNLOCK,Watchdog Unlock Register" line.word 0x10 "TMROUTH,Watchdog Timer Output Register High" line.word 0x12 "TMROUTL,Watchdog Timer Output Register Low" line.word 0x14 "RSTCNT,Watchdog Reset Count Register" line.word 0x16 "PRESC,Watchdog Prescaler Register" bitfld.word 0x16 8.--10. " PRESCVAL ,3-bit prescaler for the watchdog clock source" "/1,/2,/3,/4,/5,/6,/7,/8" width 0x0B tree.end tree "MCG (Multipurpose Clock Generator)" base ad:0x40064000 width 7. if (((per.b(ad:0x40064000+0x001))&0x30)==0x00||((per.b(ad:0x40064000+0x00C))&0x01)==0x01) group.byte 0x00++0x00 line.byte 0x00 "C1,MCG Control 1 Register" sif cpuis("MK11DN512AVLK5*") bitfld.byte 0x00 6.--7. " CLKS ,Clock source select" ",Internal ref clk,External ref clk,?..." newline else bitfld.byte 0x00 6.--7. " CLKS ,Clock source select" "Out FLL/PLL,Internal ref clk,External ref clk,?..." newline endif bitfld.byte 0x00 3.--5. " FRDIV ,FLL external reference divider" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.byte 0x00 2. " IREFS ,Internal reference select" "External,Internal" bitfld.byte 0x00 1. " IRCLKEN ,Internal reference clock enable" "Disabled,Enabled" newline bitfld.byte 0x00 0. " IREFSTEN ,Internal reference stop enable" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "C1,MCG Control 1 Register" bitfld.byte 0x00 6.--7. " CLKS ,Clock source select" "Out FLL/PLL,Internal ref clk,External ref clk,?..." sif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK63FN1M0VLQ12")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0VMI18")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK66FN2M0VLQ18") bitfld.byte 0x00 3.--5. " FRDIV ,FLL external reference divider" "/32,/64,/128,/256,/512,/1024,/1280,/1536" elif cpuis("MK40D*Z*10")||cpuis("MK10DN512ZVLK10*")||cpuis("MK10DN512ZVLL10*")||cpuis("MK10DN512ZVLQ10")||cpuis("MK10DN512ZVMD10")||cpuis("MK10DN512ZVMC10")||cpuis("MK10DX256ZVLQ10*")||cpuis("MK10DX256ZVMD10")||cpuis("MK??F*")||cpuis("KK60DN512ZCAB10R") bitfld.byte 0x00 3.--5. " FRDIV ,FLL external reference divider" "/32,/64,/128,/256,/512,/1024,?..." else bitfld.byte 0x00 3.--5. " FRDIV ,FLL external reference divider" "/32,/64,/128,/256,/512,/1024,/1280,/1536" endif newline bitfld.byte 0x00 2. " IREFS ,Internal reference select" "External,Internal" bitfld.byte 0x00 1. " IRCLKEN ,Internal reference clock enable" "Disabled,Enabled" bitfld.byte 0x00 0. " IREFSTEN ,Internal reference stop enable" "Disabled,Enabled" endif group.byte 0x01++0x01 line.byte 0x00 "C2,MCG Control 2 Register" sif !cpuis("MK20D*AB10")&&!cpuis("MK10DN512ZV??10*")&&!cpuis("MK10DX256ZV??10*")&&!cpuis("MK30DN512ZVLK10")&&!cpuis("MK30DN512ZVLQ10")&&!cpuis("MK30DN512ZVLQ10R")&&!cpuis("MK30DX256ZVLQ10")&&!cpuis("MK40D*Z*10")&&!cpuis("MK50DN512ZCLQ10")&&!cpuis("MK50DX256ZCLQ10")&&!cpuis("MK50DN512ZCLL10")&&!cpuis("MK50DX256ZCLL10")&&!cpuis("MK51DN512ZCLL10")&&!cpuis("MK51DN512ZCMC10")&&!cpuis("MK51DX256ZCMC10")&&!cpuis("MK51DN256ZCMD10")&&!cpuis("MK51DN512ZCLQ10")&&!cpuis("MK52DN512ZCLQ10")&&!cpuis("MK52DN512ZCMD10")&&!cpuis("MK53DN512ZCLQ10")&&!cpuis("MK53DN512ZCMD10")&&!cpuis("MK53DX256ZCLQ10")&&!cpuis("KK65FN2M0CAC18R") bitfld.byte 0x00 7. " LOCRE0 ,Loss of clock reset enable" "Interrupt,Reset" newline endif sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z64CLH5")||cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5"))||cpuis("MK02*")||cpuis("MK63*")||cpuis("MK64*")||cpuis("MK65*")||cpuis("MK66*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK30DX256ZVLQ10")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60DN512ZCAB10R")||cpuis("KK60FN1M0VLQ15")||cpuis("MK60D*") sif !cpuis("MK60D*")&&!cpuis("KK60FN1M0VLQ15")&&!cpuis("KK60DN512ZCAB10R") bitfld.byte 0x00 6. " FCFTRIM ,Fast internal reference clock fine trim" "Increased,Decreased" endif bitfld.byte 0x00 4.--5. " RANGE ,Frequency range select" "Encoding 0,Encoding 1,Encoding 2,Encoding 2" bitfld.byte 0x00 3. " HGO ,High gain oscillator select" "Low-power,High-gain" newline else sif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*") bitfld.byte 0x00 4.--5. " RANGE ,Frequency range select" "32kHz-39kHz,1MHz-8MHz,8MHz-32MHz,8MHz-32MHz" newline elif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") bitfld.byte 0x00 4.--5. " RANGE ,Frequency range select" "32kHz-40kHz,3MHz-8MHz,8MHz-32MHz,8MHz-32MHz" newline else bitfld.byte 0x00 4.--5. " RANGE ,Frequency range select" "1kHz-32kHz,1MHz-8MHz,8MHz-32MHz,8MHz-32MHz" newline endif bitfld.byte 0x00 3. " HGO ,High gain oscillator select" "Low-power,High-gain" newline endif bitfld.byte 0x00 2. " EREFS ,External reference select" "Ext ref,Osc" bitfld.byte 0x00 1. " LP ,Low power select" "FLL||PLL enabled,FLL||PLL disabled" bitfld.byte 0x00 0. " IRCS ,Internal reference clock select" "Slow,Fast" line.byte 0x01 "C3,MCG Control 3 Register" if (((per.b(ad:0x40064000+0x003))&0x60)==0x00) group.byte 0x03++0x00 line.byte 0x00 "C4,MCG Control 4 Register" bitfld.byte 0x00 7. " DMX32 ,DCO maximum frequency with 32.768 kHz reference" "20 - 25 MHz,24 MHz" bitfld.byte 0x00 5.--6. " DRST_DRS ,DCO range select" "Low range,Mid range,Mid-high range,High range" bitfld.byte 0x00 1.--4. " FCTRIM ,Fast internal reference clock trim setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.byte 0x00 0. " SCFTRIM ,Slow internal reference clock fine trim" "Decrease the period,Increase th period" elif (((per.b(ad:0x40064000+0x03))&0x60)==0x20) group.byte 0x03++0x00 line.byte 0x00 "C4,MCG Control 4 Register" bitfld.byte 0x00 7. " DMX32 ,Dco maximum frequency with 32.768 kHz reference" "40 - 50 MHz,48 MHz" bitfld.byte 0x00 5.--6. " DRST_DRS ,DCO range select" "Low range,Mid range,Mid-high range,High range" bitfld.byte 0x00 1.--4. " FCTRIM ,Fast internal reference clock trim setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.byte 0x00 0. " SCFTRIM ,Slow internal reference clock fine trim" "Decrease the period,Increase th period" elif (((per.b(ad:0x40064000+0x03))&0x60)==0x40) group.byte 0x03++0x00 line.byte 0x00 "C4,MCG Control 4 Register" bitfld.byte 0x00 7. " DMX32 ,DCO maximum frequency with 32.768 kHz reference" "60 - 75 MHz,72 MHz" bitfld.byte 0x00 5.--6. " DRST_DRS ,DCO range select" "Low range,Mid range,Mid-high range,High range" bitfld.byte 0x00 1.--4. " FCTRIM ,Fast internal reference clock trim setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.byte 0x00 0. " SCFTRIM ,Slow internal reference clock fine trim" "Decrease the period,Increase th period" else group.byte 0x03++0x00 line.byte 0x00 "C4,MCG Control 4 Register" bitfld.byte 0x00 7. " DMX32 ,DCO maximum frequency with 32.768 kHz reference" "80 - 100 MHz,96 MHz" bitfld.byte 0x00 5.--6. " DRST_DRS ,DCO range select" "Low range,Mid range,Mid-high range,High range" bitfld.byte 0x00 1.--4. " FCTRIM ,Fast internal reference clock trim setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.byte 0x00 0. " SCFTRIM ,Slow internal reference clock fine trim" "Decrease the period,Increase th period" endif sif !cpuis("MK02*") sif cpuis("MK??F*")||cpuis("MK60D*")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK66*")||cpuis("MK65*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*") group.byte 0x04++0x00 line.byte 0x00 "C5,MCG Control 5 Register" sif cpuis("KK60FN1M0VLQ15") bitfld.byte 0x00 7. "PLLREFSEL0,PLL0 external reference select" "OSC0,OSC1" endif bitfld.byte 0x00 6. " PLLCLKEN ,PLL clock enable" "Disabled,Enabled" bitfld.byte 0x00 5. " PLLSTEN ,PLL stop enable" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " PRDIV ,PLL external reference divider" "/1,/2,/3,/4,/5,/6,/7,/8" elif !cpuis("MK21F*") group.byte 0x04++0x00 line.byte 0x00 "C5,MCG Control 5 Register" sif !cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK63FN1M0VLQ12R") newline sif cpuis("MK20FN1M0VLQ12R")||cpuis("MK60FN1M0VLQ15")||cpuis("MK70*") bitfld.byte 0x00 7. " PLLREFSEL ,PLL0 external reference select" "OSC0,OSC1" else bitfld.byte 0x00 7. " PLLREFSEL ,PLL0 external reference select" "Disabled,Enabled" endif endif bitfld.byte 0x00 6. " PLLCLKEN ,PLL clock enable" "Disabled,Enabled" bitfld.byte 0x00 5. " PLLSTEN ,PLL stop enable" "Disabled,Enabled" sif CPUIS("MK20FN1M0VLQ12R") newline bitfld.byte 0x00 0.--2. " PRDIV ,PLL external reference divider" "/1,/2,/3,/4,/5,/6,/7,/8" elif cpuis("MK20F*")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK63FN1M0VLQ12R") newline bitfld.byte 0x00 0.--4. " PRDIV ,PLL external reference divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/18,/19,/20,/21,/22,/23,/24,/25,?..." else newline bitfld.byte 0x00 0.--2. " PRDIV ,PLL external reference divider" "/1,/2,/3,/4,/5,/6,/7,/8" endif else group.byte 0x04++0x00 line.byte 0x00 "C5,MCG Control 5 Register" bitfld.byte 0x00 6. " PLLCLKEN ,PLL clock enable" "Disabled,Enabled" bitfld.byte 0x00 5. " PLLSTEN ,PLL stop enable" "Disabled,Enabled" bitfld.byte 0x00 0.--4. " PRDIV ,PLL external reference divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/18,/19,/20,/21,/22,/23,/24,/25,?..." endif elif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z128CLH5*")||cpuis("MKM33Z64CLH5")||cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) group.byte 0x04++0x00 line.byte 0x00 "C5,MCG Control 5 Register" bitfld.byte 0x00 6. " PLLCLKEN ,PLL clock enable" "Disabled,Enabled" bitfld.byte 0x00 5. " PLLSTEN ,PLL stop enable" "Disabled,Enabled" else group.byte 0x04++0x00 line.byte 0x00 "C5,MCG Control 5 Register" bitfld.byte 0x00 6. " PLLCLKEN ,PLL clock enable" "Disabled,Enabled" bitfld.byte 0x00 5. " PLLSTEN ,PLL stop enable" "Disabled,Enabled" bitfld.byte 0x00 0.--4. " PRDIV ,PLL external reference divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,?..." endif group.byte 0x05++0x00 line.byte 0x00 "C6,MCG Control 6 Register" bitfld.byte 0x00 7. " LOLIE ,Loss of lock interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 6. " PLLS ,PLL select" "FLL,PLL" bitfld.byte 0x00 5. " CME ,Clock monitor enable" "Disabled,Enabled" sif !cpuis("MKM33Z128CLL5")&&!cpuis("MKM33Z64CLL5*")&&!cpuis("MKM34Z128CLL5")&&!cpuis("MKM33Z128CLH5*")&&!cpuis("MKM33Z64CLH5")&&!cpuis("MKM14Z128CHH5*")&&!cpuis("MKM14Z64CHH5")&&!cpuis("MKM14Z128ACHH5*")&&!cpuis("MKM14Z64ACHH5")&&!cpuis("MKM33Z128ACLH5*")&&!cpuis("MKM33Z64ACLH5*")&&!cpuis("MKM33Z64ACLL5*")&&!cpuis("MKM33Z128ACLL5")&&!cpuis("MKM34Z128ACLL5*") sif !cpuis("MK20F*")&&!cpuis("MK84FN2M0CAU15R")&&!cpuis("MK21F*")&&!cpuis("MK10F*")&&!cpuis("MK70F*")&&!cpuis("MK8?FN256V*")&&!cpuis("MK66FN2M0VLQ18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("MK65FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R")&&!cpuis("KK60FN1M0VLQ15") newline bitfld.byte 0x00 0.--4. " VDIV ,VCO divider" "/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55" elif cpuis("MK21FX512VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10") newline bitfld.byte 0x00 0.--4. " VDIV ,VCO divider" "/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55" elif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") newline bitfld.byte 0x00 0.--4. " CHGPMP_BIAS ,PLL charge pump current" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.byte 0x00 0.--4. " VDIV ,VCO divider" "/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47" endif endif else group.byte 0x05++0x00 line.byte 0x00 "C6,MCG Control 6 Register" bitfld.byte 0x00 5. " CME ,Clock monitor enable" "Disabled,Enabled" endif rgroup.byte 0x06++0x00 line.byte 0x00 "S,MCG Status Register" sif !cpuis("MK02*") bitfld.byte 0x00 7. " LOLS ,Loss of lock status" "Not lost,Lost" bitfld.byte 0x00 6. " LOCK ,Lock status" "Not locked,Locked" bitfld.byte 0x00 5. " PLLST ,PLL select status" "FLL,PLL" newline bitfld.byte 0x00 4. " IREFST ,Internal reference status" "External,Internal" bitfld.byte 0x00 2.--3. " CLKST ,Clock mode status" "Out FLL,Internal ref,External ref,Out PLL" bitfld.byte 0x00 1. " OSCINIT ,OSC initialization" "Not completed,Completed" newline else bitfld.byte 0x00 4. " IREFST ,Internal reference status" "External,Internal" bitfld.byte 0x00 2.--3. " CLKST ,Clock mode status" "Out FLL,Internal ref,External ref,?..." bitfld.byte 0x00 1. " OSCINIT ,OSC initialization" "Not completed,Completed" newline endif bitfld.byte 0x00 0. " IRCST ,Internal reference clock status" "Slow clock,Fast clock" sif cpuis("MK20D*AB10")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK40D*Z*10")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60DN512ZCAB10R") group.byte 0x08++0x00 line.byte 0x00 "ATC,MCG Auto Trim Control Register" bitfld.byte 0x00 7. " ATME ,Automatic trim machine enable" "Disabled,Enabled" bitfld.byte 0x00 6. " ATMS ,Automatic trim machine select" "32kHz,4MHz" rbitfld.byte 0x00 5. " ATMF ,Automatic trim machine fail flag" "Not occurred,Occurred" elif cpuis("KK60DN512ZCAB10R") group.byte 0x08++0x00 line.byte 0x00 "ATC,MCG Auto Trim Control Register" bitfld.byte 0x00 7. " ATME ,Automatic trim machine enable" "Disabled,Enabled" bitfld.byte 0x00 6. " ATMS ,Automatic trim machine select" "32kHz,4MHz" eventfld.byte 0x00 5. " ATMF ,Automatic trim machine fail flag" "Not occurred,Occurred" else group.byte 0x08++0x00 line.byte 0x00 "SC,MCG Status And Control Register" bitfld.byte 0x00 7. " ATME ,Automatic trim machine enable" "Disabled,Enabled" bitfld.byte 0x00 6. " ATMS ,Automatic trim machine select" "32kHz,4MHz" sif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15") rbitfld.byte 0x00 5. " ATMF ,Automatic trim machine fail flag" "Not occurred,Occurred" else eventfld.byte 0x00 5. " ATMF ,Automatic trim machine fail flag" "Not occurred,Occurred" endif newline bitfld.byte 0x00 4. " FLTPRSRV ,FLL filter preserve enable" "Disabled,Enabled" bitfld.byte 0x00 1.--3. " FCIRDIV ,Fast clock internal reference divider" "/1,/2,/4,/8,/16,/32,/64,/128" sif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15") rbitfld.byte 0x00 0. " LOCS ,OSC0 loss of clock status" "Not occurred,Occurred" else eventfld.byte 0x00 0. " LOCS ,OSC0 loss of clock status" "Not occurred,Occurred" endif endif group.byte 0x0A++0x01 line.byte 0x00 "ATCVH,MCG Auto Trim Compare Value High Register" line.byte 0x01 "ATCVL,MCG Auto Trim Compare Value Low Register" sif !cpuis("MK10DN512ZV??10*")&&!cpuis("MK10DX256ZV??10*")&&!cpuis("MK30DN512ZVLK10")&&!cpuis("MK30DN512ZVLQ10")&&!cpuis("MK30DN512ZVLQ10R")&&!cpuis("MK30DX256ZVLQ10")&&!cpuis("MK40D*Z*10")&&!cpuis("MK50DN512ZCLL10")&&!cpuis("MK50DX256ZCLL10")&&!cpuis("MK50DN512ZCLQ10")&&!cpuis("MK50DX256ZCLQ10")&&!cpuis("MK51DN512ZCLL10")&&!cpuis("MK51DN512ZCMC10")&&!cpuis("MK51DX256ZCMC10")&&!cpuis("MK51DN256ZCMD10")&&!cpuis("MK51DN512ZCLQ10")&&!cpuis("MK52DN512ZCLQ10")&&!cpuis("MK52DN512ZCMD10")&&!cpuis("MK53DN512ZCLQ10")&&!cpuis("MK53DN512ZCMD10")&&!cpuis("MK53DX256ZCLQ10") sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5*")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z128CLH5*")||cpuis("MKM33Z64CLH5")||cpuis("MKM14Z128CHH5*")||cpuis("MKM14Z64CHH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) group.byte 0x0C++0x00 line.byte 0x00 "C7,MCG Control 7 Register" bitfld.byte 0x00 6.--7. " PLL32KREFSEL ,MCG PLL 32kHz reference clock select" "32kHz RTC,32kHz IRC,FLL FRDIV,?..." sif cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")||cpuis("MKM33Z128CLH5*") newline bitfld.byte 0x00 0. " OSCSEL ,MCG OSC clock select" "OSCCLK,32kHz RTC" else newline bitfld.byte 0x00 0.--1. " OSCSEL ,MCG OSC clock select" "OSCCLK0,32kHz RTC,OSCCLK1,?..." endif elif cpuis("MK02*")||cpuis("MK63*")||cpuis("MK64*")||cpuis("MK65*")||cpuis("MK66*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK22FN512CAP12R")||cpuis("MK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") group.byte 0x0C++0x00 line.byte 0x00 "C7,MCG Control 7 Register" bitfld.byte 0x00 0.--1. " OSCSEL ,MCG OSC clock select" "OSCCLK0,32kHz RTC,OSCCLK1,?..." else group.byte 0x0C++0x00 line.byte 0x00 "C7,MCG Control 7 Register" bitfld.byte 0x00 0. " OSCSEL ,MCG OSC clock select" "OSCCLK,32kHz RTC" endif sif !cpuis("MK70*")&&!cpuis("MK02*")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK60FN1M0VLQ15") group.byte 0x0D++0x00 line.byte 0x00 "C8,MCG Control 8 Register" bitfld.byte 0x00 7. " LOCRE1 ,Loss of clock reset enable" "Interrupt,Reset" sif !cpuis("KK60FN1M0VLQ15") bitfld.byte 0x00 6. " LOLRE ,PLL loss of lock reset enable" "Interrupt,Reset" endif bitfld.byte 0x00 5. " CME1 ,Clock monitor enable" "Disabled,Enabled" newline sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z128CLH5*")||cpuis("MKM33Z64CLH5")||cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) bitfld.byte 0x00 4. " COARSE_LOLIE ,Loss of coarse lock interrupt enable" "No interrupt,Interrupt" newline endif eventfld.byte 0x00 0. " LOCS1 ,RTC loss of clock status" "Not occurred,Occurred" else group.byte 0x0D++0x00 line.byte 0x00 "C8,MCG Control 8 Register" bitfld.byte 0x00 7. " LOCRE1 ,Loss of clock reset enable" "Interrupt,Reset" bitfld.byte 0x00 5. " CME1 ,Clock monitor enable" "Disabled,Enabled" newline sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z128CLH5*")||cpuis("MKM33Z64CLH5")||cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) bitfld.byte 0x00 4. " COARSE_LOLIE ,Loss of coarse lock interrupt enable" "No interrupt,Interrupt" newline endif eventfld.byte 0x00 0. " LOCS1 ,RTC loss of clock status" "Not occurred,Occurred" endif sif !cpuis("MK84FN2M0CAU15R")&&!cpuis("MK8?FN256V*")&&!cpuis("MK20DX256VMC7R")&&!cpuis("MK20DX256VLK7R")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FX512VMD10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK30DX256VLL7R")&&!cpuis("MK02F*")&&!cpuis("MK63FN1M0VLQ12R") sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z128CLH5*")||cpuis("MKM33Z64CLH5")||cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) rgroup.byte 0x0E++0x00 line.byte 0x00 "C9,MCG Control 9 Register" bitfld.byte 0x00 7. " COARSE_LOLS ,Coarse loss of lock status" "Not occurred,Occurred" bitfld.byte 0x00 6. " COARSE_LOCK ,Coarse lock status" "Unlocked,Locked" elif cpuis("MK66*")||cpuis("MK65*")||cpuis("KK65FN2M0CAC18R")||cpuis("MK63FN1M0VLQ12R") group.byte 0x0E++0x00 line.byte 0x00 "C9,MCG Control 9 Register" bitfld.byte 0x00 5. " PLL_CME ,MCG external PLL clock monitor enable" "Disabled,Enabled" bitfld.byte 0x00 4. " PLL_LOCRE ,MCG external PLL loss of clock reset enable" "Interrupt,Sys. reset" eventfld.byte 0x00 0. " EXT_PLL_LOCS ,External PLL loss of clock status" "Not occurred,Occurred" elif !cpuis("MK63*")&&!cpuis("MK64*")&&!cpuis("MK20F*")&&!cpuis("MK21F*")&&!cpuis("MK10F*")&&!cpuis("MK10D*5")&&!cpuis("MK70*")&&!cpuis("MK11*")&&!cpuis("MK11DN512AVLK5")&&!cpuis("MK11DN512VLK5*")&&!cpuis("MK60FN1M0VLQ15")&&!cpuis("KK60FN1M0VLQ15")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R") hgroup.byte 0x0E++0x00 hide.byte 0x00 "C9,MCG Control 9 Register" endif sif !cpuis("MKM14Z128ACHH5*")&&!cpuis("MKM14Z64ACHH5")&&!cpuis("MKM33Z128ACLH5*")&&!cpuis("MKM33Z64ACLH5*")&&!cpuis("MKM33Z64ACLL5*")&&!cpuis("MKM33Z128ACLL5")&&!cpuis("MKM34Z128ACLL5*")&&!cpuis("MKM33Z64CLL5*")&&!cpuis("MKM14Z128CHH5*")&&!cpuis("MKM33Z128CLH5*")&&!cpuis("MKM34Z256VLL7*")&&!cpuis("MKM34Z256VLQ7")&&!cpuis("MK11DN512AVLK5")&&!cpuis("MK11DN512VLK5*") sif cpuis("MK??F*")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63*")&&!cpuis("MK64*")&&!cpuis("MK65*")&&!cpuis("MK66*")&&!cpuis("KK65FN2M0CAC18R") group.byte 0x0F++0x02 line.byte 0x00 "C10,MCG Control 10 Register" bitfld.byte 0x00 7. " LOCRE2 ,Loss of clock reset enable" "Interrupt,Reset" bitfld.byte 0x00 4.--5. " RANGE1 ,Frequency range select" "Encoding 0,Encoding 1,Encoding 2,Encoding 2" bitfld.byte 0x00 3. " HGO1 ,High gain oscillator select" "Low-power,High-gain" newline bitfld.byte 0x00 2. " EREFS1 ,External reference select" "Ext ref,Osc" line.byte 0x01 "C11,MCG Control 11 Register" sif cpuis("MK70*")||cpuis("KK60FN1M0VLQ15") bitfld.byte 0x01 7. " PLLREFSEL1 ,PLL1 external reference select" "OSC0,OSC1" else bitfld.byte 0x01 7. " PLLREFSEL1 ,PLL1 external reference select" "Disabled,Enabled" endif newline bitfld.byte 0x01 6. " PLLCLKEN1 ,PLL clock enable" "Disabled,Enabled" bitfld.byte 0x01 5. " PLLSTEN1 ,PLL stop enable" "Disabled,Enabled" newline bitfld.byte 0x01 4. " PLLCS ,PLL clock select" "PLL0,PLL1" bitfld.byte 0x01 0.--2. " PRDIV1 ,PLL external reference divider" "/1,/2,/3,/4,/5,/6,/7,/8" line.byte 0x02 "C12,MCG Control 12 Register" bitfld.byte 0x02 7. " LOLIE1 ,Loss of lock interrupt enable" "Disabled,Enabled" bitfld.byte 0x02 5. " CME2 ,Clock monitor enable" "Disabled,Enabled" newline sif !cpuis("MK20F*")&&!cpuis("MK21F*")&&!cpuis("KK60FN1M0VLQ15") bitfld.byte 0x02 0.--4. " VDIV1 ,VCO divider" "/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55" else bitfld.byte 0x02 0.--4. " VDIV1 ,VCO divider" "/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47" endif rgroup.byte 0x12++0x00 line.byte 0x00 "S2,MCG Status Register" sif !cpuis("KK60FN1M0VLQ15") bitfld.byte 0x00 7. " LOLS1 ,Loss of lock status" "Not lost,Lost" else eventfld.byte 0x00 7. " LOLS1 ,Loss of lock status" "Not lost,Lost" endif bitfld.byte 0x00 6. " LOCK1 ,Lock status" "Not locked,Locked" bitfld.byte 0x00 4. " PLLCST ,PLL clock select status" "PLL0,PLL1" newline bitfld.byte 0x00 1. " OSCINIT1 ,OSC initialization" "Not completed,Completed" bitfld.byte 0x00 0. " LOCS2 ,OSC1 loss of clock status" "No loss of OSC1,Loss of OSC1" elif cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.byte 0x10++0x00 line.byte 0x00 "C11,MCG Control 11 Register" bitfld.byte 0x00 4. " PLLCS ,PLL clock select" "PLL0,PLL_EXT" hgroup.byte 0x11++0x00 hide.byte 0x00 "C12,MCG Control 12 Register" rgroup.byte 0x12++0x00 line.byte 0x00 "S2,MCG Status 2 Register" bitfld.byte 0x00 4. " PLLCST ,PLL clock select status" "PLL0,PLL_EXT" elif !cpuis("MK10D*5")&&!cpuis("MK64*")&&!cpuis("MK63*") hgroup.byte 0x0F++0x00 hide.byte 0x00 "C10,MCG Control 10 Register" endif elif cpuis("MK66*")||cpuis("MK65*") group.byte 0x10++0x00 line.byte 0x00 "C11,MCG Control 11 Register" bitfld.byte 0x00 4. " PLLCS ,PLL clock select" "PLL0,PLL_EXT" hgroup.byte 0x11++0x00 hide.byte 0x00 "C12,MCG Control 12 Register" rgroup.byte 0x12++0x00 line.byte 0x00 "S2,MCG Status 2 Register" bitfld.byte 0x00 4. " PLLCST ,PLL clock select status" "PLL0,PLL_EXT" hgroup.byte 0x13++0x00 hide.byte 0x00 "T3,MCG Test 3 Register" elif !cpuis("MK10D*5")&&!cpuis("MK64*")&&!cpuis("MK63*") hgroup.byte 0x0F++0x00 hide.byte 0x00 "C10,MCG Control 10 Register" elif cpuis("MK63FN1M0VLQ12R") hgroup.byte 0x11++0x00 hide.byte 0x00 "C12,MCG Control 12 Register" endif endif endif endif width 0x0B tree.end tree "OSC (Oscillator)" base ad:0x40065000 width 4. group.byte 0x00++0x00 line.byte 0x00 "CR,OSC Control Register" bitfld.byte 0x00 7. " ERCLKEN ,External reference enable" "Disabled,Enabled" bitfld.byte 0x00 5. " EREFSTEN ,External reference stop enable" "Disabled,Enabled" bitfld.byte 0x00 3. " SC2P ,Oscillator 2 pF capacitor load configure" "Disabled,Enabled" newline bitfld.byte 0x00 2. " SC4P ,Oscillator 4 pF capacitor load configure" "Disabled,Enabled" bitfld.byte 0x00 1. " SC8P ,Oscillator 8 pF capacitor load configure" "Disabled,Enabled" bitfld.byte 0x00 0. " SC16P ,Oscillator 16 pF capacitor load configure" "Disabled,Enabled" sif cpuis("MK02*")||cpuis("MK66*")||cpuis("MK65*")||cpuis("MK22FN256*")||cpuis("MK22FN128*")||cpuis("MK26FN*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MKV5*")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK22FN128VLH10R")||cpuis("MK27FN2M0VMI15")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK65FN2M0CAC18*") width 9. newline group.byte 0x02++0x00 line.byte 0x00 "OSC_DIV,OSC Clock Divider Register" bitfld.byte 0x00 6.--7. " ERPS ,ERCLK prescaler" "/1,/2,/4,/8" endif width 0x0B tree.end tree "LMEM (Local Memory Controller)" base ad:0xE0082000 width 8. group.long 0x00++0x03 line.long 0x00 "PCCCR,Cache Control Register" bitfld.long 0x00 31. " GO ,Initiate cache command" "Disabled,Enabled" bitfld.long 0x00 27. " PUSHW1 ,Push way 1" "Disabled,Enabled" bitfld.long 0x00 26. " INVW1 ,Invalidate way 1" "Disabled,Enabled" newline bitfld.long 0x00 25. " PUSHW0 ,Push way 0" "Disabled,Enabled" bitfld.long 0x00 24. " INVW0 ,Invalidate way 0" "Disabled,Enabled" newline sif cpuis("MK65*")||cpuis("MK66*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK65FN2M0CAC18*") bitfld.long 0x00 3. " PCCR3 ,Forces no allocation on cache misses (must also have PCCR2 asserted)" "Not forced,Forced" bitfld.long 0x00 2. " PCCR2 ,Forces all cacheable spaces to write through" "Not forced,Forced" newline endif bitfld.long 0x00 1. " ENWRBUF ,Enable write buffer" "Disabled,Enabled" bitfld.long 0x00 0. " ENCACHE ,Cache enable" "Disabled,Enabled" sif cpuis("MK65*")||cpuis("MK66*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK65FN2M0CAC18*")||cpuis("KK60FN1M0VLQ15") if (((per.l(ad:0xE0082000+0x04))&0x10000)==0x00) group.long 0x04++0x07 line.long 0x00 "PCCLCR,Cache Line Control Register" bitfld.long 0x00 27. " LACC ,Line access type" "Read,Write" bitfld.long 0x00 26. " LADSEL ,Line address select" "Cache address,Physical address" bitfld.long 0x00 24.--25. " LCMD ,Line command" "Search and R/W,Invalidate,Push,Clear" newline rbitfld.long 0x00 22. " LCWAY ,Line command way" "Way 0,Way 1" rbitfld.long 0x00 21. " LCIMB ,Line command initial modified bit" "Way 0,Way 1" rbitfld.long 0x00 20. " LCIVB ,Line command initial valid bit" "0,1" newline bitfld.long 0x00 16. " TDSEL ,Tag/Data select" "Data,Tag" bitfld.long 0x00 14. " WSEL ,Way select" "Way 0,Way 1" newline hexmask.long.word 0x00 2.--11. 0x04 " CACHEADDR ,Cache address" bitfld.long 0x00 0. " LGO ,Initiate cache line command" "Not initiated,Initiated" line.long 0x04 "PCCSAR,Cache Search Address Register" hexmask.long.tbyte 0x04 12.--31. 0x10 " CSAR ,CSAR bits are used for tag compare" hexmask.long.word 0x04 2.--11. 0x04 " CSAR ,CCSAR bits are used to access the data arrays" bitfld.long 0x04 0. " LGO ,Initiate cache line command" "Not initiated,Initiated" else group.long 0x04++0x07 line.long 0x00 "PCCLCR,Cache Line Control Register" bitfld.long 0x00 27. " LACC ,Line access type" "Read,Write" bitfld.long 0x00 26. " LADSEL ,Line address select" "Cache address,Physical address" bitfld.long 0x00 24.--25. " LCMD ,Line command" "Search and R/W,Invalidate,Push,Clear" newline rbitfld.long 0x00 22. " LCWAY ,Line command way" "Way 0,Way 1" rbitfld.long 0x00 21. " LCIMB ,Line command initial modified bit" "Way 0,Way 1" rbitfld.long 0x00 20. " LCIVB ,Line command initial valid bit" "0,1" newline bitfld.long 0x00 16. " TDSEL ,Tag/Data select" "Data,Tag" bitfld.long 0x00 14. " WSEL ,Way select" "Way 0,Way 1" newline hexmask.long.byte 0x00 4.--11. 0x10 " CACHEADDR ,Cache address" bitfld.long 0x00 0. " LGO ,Initiate cache line command" "No effect/Not active,Initiated/Active" line.long 0x04 "PCCSAR,Cache Search Address Register" hexmask.long.tbyte 0x04 12.--31. 0x10 " CSAR ,CSAR bits are used for tag compare" hexmask.long.byte 0x04 4.--11. 0x10 " CSAR ,CSAR bits are used to access the tag arrays" bitfld.long 0x04 0. " LGO ,Initiate cache line command" "Not initiated,Initiated" endif if (((per.l(ad:0xE0082000+0x04))&0x10000)==0x00) group.long 0x0C++0x03 line.long 0x00 "PCCCVR,Cache Read/Write Value Register" elif (((per.l(ad:0xE0082000+0x04))&0x8010000)==0x0010000) group.long 0x0C++0x03 line.long 0x00 "PCCCVR,Cache Read/Write Value Register" hexmask.long.tbyte 0x00 12.--31. 1. " CCVR ,Tag array R/W value" hexmask.long.byte 0x00 4.--11. 0x10 " CCVR ,CCVR bits are used for tag set address on reads" newline bitfld.long 0x00 1. " CCVR[1] ,Tag modify bit" "0,1" bitfld.long 0x00 0. " CCVR[0] ,Tag valid bit" "0,1" elif (((per.l(ad:0xE0082000+0x04))&0x8010000)==0x8010000) group.long 0x0C++0x03 line.long 0x00 "PCCCVR,Cache Read/Write Value Register" hexmask.long.tbyte 0x00 12.--31. 1. " CCVR ,Tag array R/W value" newline bitfld.long 0x00 1. " CCVR[1] ,Tag modify bit" "0,1" bitfld.long 0x00 0. " CCVR[0] ,Tag valid bit" "0,1" endif else group.long 0x04++0x07 line.long 0x00 "PCCLCR,Cache Line Control Register" bitfld.long 0x00 27. " LACC ,Line access type" "Read,Write" bitfld.long 0x00 26. " LADSEL ,Line address select" "Cache address,Physical address" bitfld.long 0x00 24.--25. " LCMD ,Line command" "Search and R/W,Invalidate,Push,Clear" newline rbitfld.long 0x00 22. " LCWAY ,Line command way" "0,1" rbitfld.long 0x00 21. " LCIMB ,Line command initial modified bit" "Way 0,Way 1" rbitfld.long 0x00 20. " LCIVB ,Line command initial valid bit" "0,1" newline bitfld.long 0x00 16. " TDSEL ,Tag/Data select" "Data,Tag" bitfld.long 0x00 14. " WSEL ,Way select" "Way 0,Way 1" newline hexmask.long.word 0x00 2.--11. 0x04 " CACHEADDR[11:2] ,Cache address" bitfld.long 0x00 0. " LGO ,Initiate cache line command" "0,1" line.long 0x04 "PCCSAR,Cache Search Address Register" hexmask.long 0x04 2.--31. 0x04 " PHYADDR ,Physical address" bitfld.long 0x04 0. " LGO ,Initiate cache line command" "0,1" group.long 0x0C++0x03 line.long 0x00 "PCCCVR,Cache Read/Write Value Register" endif sif cpuis("MK65*")||cpuis("MK66*")||cpuis("KK65FN2M0CAC18*")||cpuis("KK60FN1M0VLQ15") group.long 0x20++0x03 line.long 0x00 "PCCRMR,Cache Regions Mode Register" sif cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 30.--31. " R0 ,Program flash and read-only data" ",,Write-through,?..." bitfld.long 0x00 28.--29. " R1 ,DRAM Controller (aliased Area)" ",,Write-through,?..." bitfld.long 0x00 26.--27. " R2 ,FlexNVM" ",,Write-through,?..." newline bitfld.long 0x00 24.--25. " R3 ,FlexBus (aliased Area)" ",,Write-through,?..." bitfld.long 0x00 18.--19. " R6 ,FlexBus (external memory - write-back)" ",,Write-through,Write-back" bitfld.long 0x00 12.--13. " R9 ,FlexBus (external memory - write-through)" ",,Write-through,?..." elif cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 30.--31. " R0 ,Program flash and read-only data" ",,Write-through,?..." bitfld.long 0x00 28.--29. " R1 ,DRAM Controller (aliased Area)" ",,Write-through,?..." bitfld.long 0x00 26.--27. " R2 ,FlexNVM" ",,Write-through,?..." newline bitfld.long 0x00 24.--25. " R3 ,FlexBus (aliased Area)" ",,Write-through,?..." bitfld.long 0x00 18.--19. " R6 ,FlexBus (external memory - write-back)" ",,Write-through,Write-back" bitfld.long 0x00 16.--17. " R7 ,DRAM Controller" ",,Write-through,Write-back" endif elif cpuis("MK20FN1M0VLQ12R") group.long 0x20++0x03 line.long 0x00 "PCCRMR,Cache Regions Mode Register" bitfld.long 0x00 30.--31. " R0 ,Program flash and read-only data" "Non-cacheable,Non-cacheable,Write-through,?..." bitfld.long 0x00 28.--29. " R1 ,DRAM Controller (Aliased Area)" "Non-cacheable,Non-cacheable,Write-through,?..." bitfld.long 0x00 26.--27. " R2 ,FlexNVM" "Non-cacheable,Non-cacheable,Write-through,?..." bitfld.long 0x00 24.--25. " R3 ,FlexBus (Aliased Area)" "Non-cacheable,Non-cacheable,Write-through,?..." newline bitfld.long 0x00 22.--23. " R4 ,SRAM_L: Lower SRAM (ICODE/DCODE)" "Non-cacheable,Non-cacheable,?..." bitfld.long 0x00 20.--21. " R5 ,SRAM_U: Upper SRAM" "Non-cacheable,Non-cacheable,?..." bitfld.long 0x00 18.--19. " R6 ,Flexbus (External memory - Write-back)" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 12.--13. " R9 ,FlexBus (External memory - Write-through)" "Non-cacheable,Non-cacheable,Write-through,?..." newline bitfld.long 0x00 10.--11. " R10 ,FlexBus (external peripheral)" "Non-cacheable,Non-cacheable,?..." bitfld.long 0x00 8.--9. " R11 ,FlexBus (External memory - Write-through)" "Non-cacheable,Non-cacheable,?..." bitfld.long 0x00 6.--7. " R12 ,FlexBus (External memory - Write-through)" "Non-cacheable,Non-cacheable,?..." bitfld.long 0x00 4.--5. " R13 ,FlexBus (External memory - Write-through)" "Non-cacheable,Non-cacheable,?..." else group.long 0x20++0x03 line.long 0x00 "PCCRMR,Cache Regions Mode Register" bitfld.long 0x00 30.--31. " R0 ,Region 0 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 28.--29. " R1 ,Region 1 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 26.--27. " R2 ,Region 2 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 24.--25. " R3 ,Region 3 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" newline bitfld.long 0x00 22.--23. " R4 ,Region 4 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 20.--21. " R5 ,Region 5 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 18.--19. " R6 ,Region 6 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 16.--17. " R7 ,Region 7 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" newline bitfld.long 0x00 14.--15. " R8 ,Region 8 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 12.--13. " R9 ,Region 9 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 10.--11. " R10 ,Region 10 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 8.--9. " R11 ,Region 11 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" newline bitfld.long 0x00 6.--7. " R12 ,Region 12 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 4.--5. " R13 ,Region 13 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 2.--3. " R14 ,Region 14 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 0.--1. " R15 ,Region 15 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" endif sif !cpuis("MK65*")&&!cpuis("MK66*")&&!cpuis("MK26*")&&!cpuis("KK26FN2M0CAC18R")&&!cpuis("KK65FN2M0CAC18*") group.long 0x800++0x03 line.long 0x00 "PSCCR,Cache Control Register" bitfld.long 0x00 31. " GO ,Initiate cache command" "Disabled,Enabled" bitfld.long 0x00 27. " PUSHW1 ,Push way 1" "Disabled,Enabled" bitfld.long 0x00 26. " INVW1 ,Invalidate way 1" "Disabled,Enabled" newline bitfld.long 0x00 25. " PUSHW0 ,Push way 0" "Disabled,Enabled" bitfld.long 0x00 24. " INVW0 ,Invalidate way 0" "Disabled,Enabled" bitfld.long 0x00 1. " ENWRBUF ,Enable write buffer" "Disabled,Enabled" newline bitfld.long 0x00 0. " ENCACHE ,Cache enable" "Disabled,Enabled" if (((per.l(ad:0xE0082000+0x804))&0x10000)==0x00) group.long 0x804++0x07 line.long 0x00 "PSCLCR,Cache Line Control Register" bitfld.long 0x00 27. " LACC ,Line access type" "Read,Write" bitfld.long 0x00 26. " LADSEL ,Line address select" "Cache address,Physical address" bitfld.long 0x00 24.--25. " LCMD ,Line command" "Search and R/W,Invalidate,Push,Clear" newline rbitfld.long 0x00 22. " LCWAY ,Line command way" "0,1" rbitfld.long 0x00 21. " LCIMB ,Line command initial modified bit" "0,1" rbitfld.long 0x00 20. " LCIVB ,Line command initial valid bit" "0,1" newline bitfld.long 0x00 16. " TDSEL ,Tag/Data select" "Data,Tag" bitfld.long 0x00 14. " WSEL ,Way select" "Way 0,Way 1" hexmask.long.word 0x00 2.--11. 0x04 " CACHEADDR ,Cache address" bitfld.long 0x00 0. " LGO ,Initiate cache line command" "Not initiated,Initiated" line.long 0x04 "PSCSAR,Cache Search Address Register" hexmask.long.tbyte 0x04 12.--31. 0x10 " CSAR ,CSAR bits are used for tag compare" hexmask.long.word 0x04 2.--11. 0x04 " CSAR ,CCSAR bits are used to access the data arrays" bitfld.long 0x04 0. " LGO ,Initiate cache line command" "Not initiated,Initiated" group.long 0x80C++0x03 line.long 0x00 "PSCCVR,Cache Read/Write Value Register" else group.long 0x804++0x07 line.long 0x00 "PSCLCR,Cache Line Control Register" bitfld.long 0x00 27. " LACC ,Line access type" "Read,Write" bitfld.long 0x00 26. " LADSEL ,Line address select" "Cache address,Physical address" bitfld.long 0x00 24.--25. " LCMD ,Line command" "Search and R/W,Invalidate,Push,Clear" newline rbitfld.long 0x00 22. " LCWAY ,Line command way" "0,1" rbitfld.long 0x00 21. " LCIMB ,Line command initial modified bit" "0,1" rbitfld.long 0x00 20. " LCIVB ,Line command initial valid bit" "0,1" newline bitfld.long 0x00 16. " TDSEL ,Tag/Data select" "Data,Tag" bitfld.long 0x00 14. " WSEL ,Way select" "Way 0,Way 1" hexmask.long.byte 0x00 4.--11. 0x10 " CACHEADDR ,Cache address" bitfld.long 0x00 0. " LGO ,Initiate cache line command" "Not initiated,Initiated" line.long 0x04 "PSCSAR,Cache Search Address Register" hexmask.long.tbyte 0x04 12.--31. 0x10 " CSAR ,CSAR bits are used for tag compare" hexmask.long.byte 0x04 4.--11. 0x10 " CSAR ,CCSAR bits are used to access the tag arrays" bitfld.long 0x04 0. " LGO ,Initiate cache line command" "Not initiated,Initiated" sif cpuis("KK60FN1M0VLQ15") if (((per.l(ad:0xE0082000+0x804))&0x8000000)==0x00) group.long 0x80C++0x03 line.long 0x00 "PSCCVR,Cache Read/Write Value Register" hexmask.long.tbyte 0x00 12.--31. 1. " TAG_VALUE ,Tag array R/W value" hexmask.long.byte 0x00 4.--11. 0x10 " TAG_ADDR ,Tag set address" else group.long 0x80C++0x03 line.long 0x00 "PSCCVR,Cache Read/Write Value Register" hexmask.long.tbyte 0x00 12.--31. 1. " TAG_VALUE ,Tag array R/W value" endif else group.long 0x80C++0x03 line.long 0x00 "PSCCVR,Cache Read/Write Value Register" hexmask.long.tbyte 0x00 12.--31. 1. " TAG_VALUE ,Tag array R/W value" hexmask.long.byte 0x00 4.--11. 0x10 " TAG_ADDR ,Tag set address" endif endif group.long 0x820++0x03 line.long 0x00 "PSCRMR,Cache Regions Mode Register" sif cpuis("MK20FN1M0VLQ12R") bitfld.long 0x00 30.--31. " R0 ,Program flash and read-only data" "Non-cacheable,Non-cacheable,Write-through,?..." bitfld.long 0x00 28.--29. " R1 ,DRAM Controller (Aliased Area)" "Non-cacheable,Non-cacheable,Write-through,?..." bitfld.long 0x00 26.--27. " R2 ,FlexNVM" "Non-cacheable,Non-cacheable,Write-through,?..." bitfld.long 0x00 24.--25. " R3 ,FlexBus (Aliased Area)" "Non-cacheable,Non-cacheable,Write-through,?..." newline bitfld.long 0x00 22.--23. " R4 ,SRAM_L: Lower SRAM (ICODE/DCODE)" "Non-cacheable,Non-cacheable,?..." bitfld.long 0x00 20.--21. " R5 ,SRAM_U: Upper SRAM" "Non-cacheable,Non-cacheable,?..." bitfld.long 0x00 18.--19. " R6 ,Flexbus (External memory - Write-back)" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 12.--13. " R9 ,FlexBus (External memory - Write-through)" "Non-cacheable,Non-cacheable,Write-through,?..." newline bitfld.long 0x00 10.--11. " R10 ,FlexBus (external peripheral)" "Non-cacheable,Non-cacheable,?..." bitfld.long 0x00 8.--9. " R11 ,FlexBus (External memory - Write-through)" "Non-cacheable,Non-cacheable,?..." bitfld.long 0x00 6.--7. " R12 ,FlexBus (External memory - Write-through)" "Non-cacheable,Non-cacheable,?..." bitfld.long 0x00 4.--5. " R13 ,FlexBus (External memory - Write-through)" "Non-cacheable,Non-cacheable,?..." elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 30.--31. " R0 ,Program flash and read-only data" "Non-cacheable,Non-cacheable,Write-through,?..." bitfld.long 0x00 28.--29. " R1 ,DRAM Controller (aliased Area)" "Non-cacheable,Non-cacheable,Write-through,?..." bitfld.long 0x00 26.--27. " R2 ,FlexNVM" "Non-cacheable,Non-cacheable,Write-through,?..." bitfld.long 0x00 24.--25. " R3 ,FlexBus (aliased Area)" "Non-cacheable,Non-cacheable,Write-through,?..." newline bitfld.long 0x00 22.--23. " R4 ,SRAM_L: Lower SRAM (ICODE/DCODE)" "Non-cacheable,Non-cacheable,?..." bitfld.long 0x00 20.--21. " R5 ,SRAM_U: Upper SRAM" "Non-cacheable,Non-cacheable,?..." bitfld.long 0x00 18.--19. " R6 ,FlexBus (extermal memory - write-back)" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 12.--13. " R9 ,FlexBus (external memory - write-through)" "Non-cacheable,Non-cacheable,Write-through,?..." else bitfld.long 0x00 30.--31. " R0 ,Region 0 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 28.--29. " R1 ,Region 1 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 26.--27. " R2 ,Region 2 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 24.--25. " R3 ,Region 3 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" newline bitfld.long 0x00 22.--23. " R4 ,Region 4 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 20.--21. " R5 ,Region 5 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 18.--19. " R6 ,Region 6 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 16.--17. " R7 ,Region 7 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" newline bitfld.long 0x00 14.--15. " R8 ,Region 8 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 12.--13. " R9 ,Region 9 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 10.--11. " R10 ,Region 10 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 8.--9. " R11 ,Region 11 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" newline bitfld.long 0x00 6.--7. " R12 ,Region 12 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 4.--5. " R13 ,Region 13 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 2.--3. " R14 ,Region 14 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 0.--1. " R15 ,Region 15 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" endif endif width 0x0B tree.end tree "FMC (Flash Memory Controller)" base ad:0x4001f000 width 12. group.long 0x00++0x03 line.long 0x00 "PFAPR,Flash Access Protection Register" bitfld.long 0x00 20. " M4PFD ,Master 4 prefetch disable" "No,Yes" bitfld.long 0x00 19. " M3PFD ,Master 3 prefetch disable" "No,Yes" bitfld.long 0x00 18. " M2PFD ,Master 2 prefetch disable" "No,Yes" bitfld.long 0x00 17. " M1PFD ,Master 1 prefetch disable" "No,Yes" newline bitfld.long 0x00 16. " M0PFD ,Master 0 prefetch disable" "No,Yes" bitfld.long 0x00 8.--9. " M4AP ,Master 4 access protection" "No access,RO accesses,WO accesses,RW accesses" bitfld.long 0x00 6.--7. " M3AP ,Master 3 access protection" "No access,RO accesses,WO accesses,RW accesses" bitfld.long 0x00 4.--5. " M2AP ,Master 2 access protection" "No access,RO accesses,WO accesses,RW accesses" newline bitfld.long 0x00 2.--3. " M1AP ,Master 1 access protection" "No access,RO accesses,WO accesses,RW accesses" bitfld.long 0x00 0.--1. " M0AP ,Master 0 access protection" "No access,RO accesses,WO accesses,RW accesses" group.long 0x04++0x03 line.long 0x00 "PFB0CR,Flash Bank 0 Control Register" rbitfld.long 0x00 28.--31. " B0RWSC ,Bank 0 read wait state control" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 27. " CLCK_WAY[3] ,Cache lock way 3" "Not locked,Locked" bitfld.long 0x00 26. " CLCK_WAY[2] ,Cache lock way 2" "Not locked,Locked" newline bitfld.long 0x00 25. " CLCK_WAY[1] ,Cache lock way 1" "Not locked,Locked" bitfld.long 0x00 24. " CLCK_WAY[0] ,Cache lock way 0" "Not locked,Locked" bitfld.long 0x00 23. " CINV_WAY[3] ,Cache invalidate way 3" "Not invalidated,Invalidated" newline bitfld.long 0x00 22. " CINV_WAY[2] ,Cache invalidate way 2" "Not invalidated,Invalidated" bitfld.long 0x00 21. " CINV_WAY[1] ,Cache invalidate way 1" "Not invalidated,Invalidated" bitfld.long 0x00 20. " CINV_WAY[0] ,Cache invalidate way 0" "Not invalidated,Invalidated" newline bitfld.long 0x00 19. " S_B_INV ,Invalidate prefetch speculation buffer" "Not invalidated,Invalidated" rbitfld.long 0x00 17.--18. " B0MW ,Bank 0 memory width" "32 bits,64 bits,128 bits,?..." bitfld.long 0x00 5.--7. " CRC ,Cache replacement control" "LRU per 4 ways,,LRU with 0-1 ways,LRU with 0-2 ways,?..." newline bitfld.long 0x00 4. " B0DCE ,Bank 0 data cache enable" "Disabled,Enabled" bitfld.long 0x00 3. " B0ICE ,Bank 0 instruction cache enable" "Disabled,Enabled" bitfld.long 0x00 2. " B0DPE ,Bank 0 data prefetch enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " B0IPE ,Bank 0 instruction prefetch enable" "Disabled,Enabled" bitfld.long 0x00 0. " B0SEBE ,Bank 0 single entry buffer enable" "Disabled,Enabled" group.long 0x100++0x03 line.long 0x00 "TAGVDW0S0,Cache Tag Storage Way 0 Set 0" hexmask.long.word 0x00 6.--19. 1. " CACHE_TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x104++0x03 line.long 0x00 "TAGVDW0S1,Cache Tag Storage Way 0 Set 1" hexmask.long.word 0x00 6.--19. 1. " CACHE_TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x108++0x03 line.long 0x00 "TAGVDW0S2,Cache Tag Storage Way 0 Set 2" hexmask.long.word 0x00 6.--19. 1. " CACHE_TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x10C++0x03 line.long 0x00 "TAGVDW0S3,Cache Tag Storage Way 0 Set 3" hexmask.long.word 0x00 6.--19. 1. " CACHE_TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x110++0x03 line.long 0x00 "TAGVDW1S0,Cache Tag Storage Way 1 Set 0" hexmask.long.word 0x00 6.--19. 1. " CACHE_TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x114++0x03 line.long 0x00 "TAGVDW1S1,Cache Tag Storage Way 1 Set 1" hexmask.long.word 0x00 6.--19. 1. " CACHE_TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x118++0x03 line.long 0x00 "TAGVDW1S2,Cache Tag Storage Way 1 Set 2" hexmask.long.word 0x00 6.--19. 1. " CACHE_TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x11C++0x03 line.long 0x00 "TAGVDW1S3,Cache Tag Storage Way 1 Set 3" hexmask.long.word 0x00 6.--19. 1. " CACHE_TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x120++0x03 line.long 0x00 "TAGVDW2S0,Cache Tag Storage Way 2 Set 0" hexmask.long.word 0x00 6.--19. 1. " CACHE_TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x124++0x03 line.long 0x00 "TAGVDW2S1,Cache Tag Storage Way 2 Set 1" hexmask.long.word 0x00 6.--19. 1. " CACHE_TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x128++0x03 line.long 0x00 "TAGVDW2S2,Cache Tag Storage Way 2 Set 2" hexmask.long.word 0x00 6.--19. 1. " CACHE_TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x12C++0x03 line.long 0x00 "TAGVDW2S3,Cache Tag Storage Way 2 Set 3" hexmask.long.word 0x00 6.--19. 1. " CACHE_TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x130++0x03 line.long 0x00 "TAGVDW3S0,Cache Tag Storage Way 3 Set 0" hexmask.long.word 0x00 6.--19. 1. " CACHE_TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x134++0x03 line.long 0x00 "TAGVDW3S1,Cache Tag Storage Way 3 Set 1" hexmask.long.word 0x00 6.--19. 1. " CACHE_TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x138++0x03 line.long 0x00 "TAGVDW3S2,Cache Tag Storage Way 3 Set 2" hexmask.long.word 0x00 6.--19. 1. " CACHE_TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x13C++0x03 line.long 0x00 "TAGVDW3S3,Cache Tag Storage Way 3 Set 3" hexmask.long.word 0x00 6.--19. 1. " CACHE_TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x200++0x0F line.long 0x00 "DATAW0S0UM,Cache Data Storage Way 0 Set 0 (Uppermost word)" line.long 0x04 "DATAW0S0MU,Cache Data Storage Way 0 Set 0 (Mid-upper word)" line.long 0x08 "DATAW0S0ML,Cache Data Storage Way 0 Set 0 (Mid-lower word)" line.long 0x0C "DATAW0S0LM,Cache Data Storage Way 0 Set 0 (Lowermost word)" group.long 0x210++0x0F line.long 0x00 "DATAW0S1UM,Cache Data Storage Way 0 Set 1 (Uppermost word)" line.long 0x04 "DATAW0S1MU,Cache Data Storage Way 0 Set 1 (Mid-upper word)" line.long 0x08 "DATAW0S1ML,Cache Data Storage Way 0 Set 1 (Mid-lower word)" line.long 0x0C "DATAW0S1LM,Cache Data Storage Way 0 Set 1 (Lowermost word)" group.long 0x220++0x0F line.long 0x00 "DATAW0S2UM,Cache Data Storage Way 0 Set 2 (Uppermost word)" line.long 0x04 "DATAW0S2MU,Cache Data Storage Way 0 Set 2 (Mid-upper word)" line.long 0x08 "DATAW0S2ML,Cache Data Storage Way 0 Set 2 (Mid-lower word)" line.long 0x0C "DATAW0S2LM,Cache Data Storage Way 0 Set 2 (Lowermost word)" group.long 0x230++0x0F line.long 0x00 "DATAW0S3UM,Cache Data Storage Way 0 Set 3 (Uppermost word)" line.long 0x04 "DATAW0S3MU,Cache Data Storage Way 0 Set 3 (Mid-upper word)" line.long 0x08 "DATAW0S3ML,Cache Data Storage Way 0 Set 3 (Mid-lower word)" line.long 0x0C "DATAW0S3LM,Cache Data Storage Way 0 Set 3 (Lowermost word)" group.long 0x240++0x0F line.long 0x00 "DATAW1S0UM,Cache Data Storage Way 1 Set 0 (Uppermost word)" line.long 0x04 "DATAW1S0MU,Cache Data Storage Way 1 Set 0 (Mid-upper word)" line.long 0x08 "DATAW1S0ML,Cache Data Storage Way 1 Set 0 (Mid-lower word)" line.long 0x0C "DATAW1S0LM,Cache Data Storage Way 1 Set 0 (Lowermost word)" group.long 0x250++0x0F line.long 0x00 "DATAW1S1UM,Cache Data Storage Way 1 Set 1 (Uppermost word)" line.long 0x04 "DATAW1S1MU,Cache Data Storage Way 1 Set 1 (Mid-upper word)" line.long 0x08 "DATAW1S1ML,Cache Data Storage Way 1 Set 1 (Mid-lower word)" line.long 0x0C "DATAW1S1LM,Cache Data Storage Way 1 Set 1 (Lowermost word)" group.long 0x260++0x0F line.long 0x00 "DATAW1S2UM,Cache Data Storage Way 1 Set 2 (Uppermost word)" line.long 0x04 "DATAW1S2MU,Cache Data Storage Way 1 Set 2 (Mid-upper word)" line.long 0x08 "DATAW1S2ML,Cache Data Storage Way 1 Set 2 (Mid-lower word)" line.long 0x0C "DATAW1S2LM,Cache Data Storage Way 1 Set 2 (Lowermost word)" group.long 0x270++0x0F line.long 0x00 "DATAW1S3UM,Cache Data Storage Way 1 Set 3 (Uppermost word)" line.long 0x04 "DATAW1S3MU,Cache Data Storage Way 1 Set 3 (Mid-upper word)" line.long 0x08 "DATAW1S3ML,Cache Data Storage Way 1 Set 3 (Mid-lower word)" line.long 0x0C "DATAW1S3LM,Cache Data Storage Way 1 Set 3 (Lowermost word)" group.long 0x280++0x0F line.long 0x00 "DATAW2S0UM,Cache Data Storage Way 2 Set 0 (Uppermost word)" line.long 0x04 "DATAW2S0MU,Cache Data Storage Way 2 Set 0 (Mid-upper word)" line.long 0x08 "DATAW2S0ML,Cache Data Storage Way 2 Set 0 (Mid-lower word)" line.long 0x0C "DATAW2S0LM,Cache Data Storage Way 2 Set 0 (Lowermost word)" group.long 0x290++0x0F line.long 0x00 "DATAW2S1UM,Cache Data Storage Way 2 Set 1 (Uppermost word)" line.long 0x04 "DATAW2S1MU,Cache Data Storage Way 2 Set 1 (Mid-upper word)" line.long 0x08 "DATAW2S1ML,Cache Data Storage Way 2 Set 1 (Mid-lower word)" line.long 0x0C "DATAW2S1LM,Cache Data Storage Way 2 Set 1 (Lowermost word)" group.long 0x2A0++0x0F line.long 0x00 "DATAW2S2UM,Cache Data Storage Way 2 Set 2 (Uppermost word)" line.long 0x04 "DATAW2S2MU,Cache Data Storage Way 2 Set 2 (Mid-upper word)" line.long 0x08 "DATAW2S2ML,Cache Data Storage Way 2 Set 2 (Mid-lower word)" line.long 0x0C "DATAW2S2LM,Cache Data Storage Way 2 Set 2 (Lowermost word)" group.long 0x2B0++0x0F line.long 0x00 "DATAW2S3UM,Cache Data Storage Way 2 Set 3 (Uppermost word)" line.long 0x04 "DATAW2S3MU,Cache Data Storage Way 2 Set 3 (Mid-upper word)" line.long 0x08 "DATAW2S3ML,Cache Data Storage Way 2 Set 3 (Mid-lower word)" line.long 0x0C "DATAW2S3LM,Cache Data Storage Way 2 Set 3 (Lowermost word)" group.long 0x2C0++0x0F line.long 0x00 "DATAW3S0UM,Cache Data Storage Way 3 Set 0 (Uppermost word)" line.long 0x04 "DATAW3S0MU,Cache Data Storage Way 3 Set 0 (Mid-upper word)" line.long 0x08 "DATAW3S0ML,Cache Data Storage Way 3 Set 0 (Mid-lower word)" line.long 0x0C "DATAW3S0LM,Cache Data Storage Way 3 Set 0 (Lowermost word)" group.long 0x2D0++0x0F line.long 0x00 "DATAW3S1UM,Cache Data Storage Way 3 Set 1 (Uppermost word)" line.long 0x04 "DATAW3S1MU,Cache Data Storage Way 3 Set 1 (Mid-upper word)" line.long 0x08 "DATAW3S1ML,Cache Data Storage Way 3 Set 1 (Mid-lower word)" line.long 0x0C "DATAW3S1LM,Cache Data Storage Way 3 Set 1 (Lowermost word)" group.long 0x2E0++0x0F line.long 0x00 "DATAW3S2UM,Cache Data Storage Way 3 Set 2 (Uppermost word)" line.long 0x04 "DATAW3S2MU,Cache Data Storage Way 3 Set 2 (Mid-upper word)" line.long 0x08 "DATAW3S2ML,Cache Data Storage Way 3 Set 2 (Mid-lower word)" line.long 0x0C "DATAW3S2LM,Cache Data Storage Way 3 Set 2 (Lowermost word)" group.long 0x2F0++0x0F line.long 0x00 "DATAW3S3UM,Cache Data Storage Way 3 Set 3 (Uppermost word)" line.long 0x04 "DATAW3S3MU,Cache Data Storage Way 3 Set 3 (Mid-upper word)" line.long 0x08 "DATAW3S3ML,Cache Data Storage Way 3 Set 3 (Mid-lower word)" line.long 0x0C "DATAW3S3LM,Cache Data Storage Way 3 Set 3 (Lowermost word)" width 0x0B tree.end tree "FTFE (Flash Memory Module)" base ad:0x40020000 width 7. group.byte 0x00++0x01 line.byte 0x00 "FSTAT,Flash Status Register" eventfld.byte 0x00 7. " CCIF ,Command complete interrupt flag" "Not completed,Completed" eventfld.byte 0x00 6. " RDCOLERR ,Flash read collision error flag" "No error,Error" newline eventfld.byte 0x00 5. " ACCERR ,Flash access error flag" "No error,Error" eventfld.byte 0x00 4. " FPVIOL ,Flash protection violation flag" "Not detected,Detected" newline rbitfld.byte 0x00 0. " MGSTAT0 ,Memory controller command completion status flag" "No error,Error" line.byte 0x01 "FCNFG,Flash Configuration Register" bitfld.byte 0x01 7. " CCIE ,Command complete interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 6. " RDCOLLIE ,Read collision error interrupt enable" "Disabled,Enabled" newline rbitfld.byte 0x01 5. " ERSAREQ ,Erase all request" "Not erased,Erased" bitfld.byte 0x01 4. " ERSSUSP ,Erase suspend" "Not suspended,Suspended" sif cpuis("MK10DN512ZVLK10*")||cpuis("MK10DN512ZVMD10")||cpuis("MK10DN512ZVLQ10")||cpuis("MK10DX256ZVLQ10*")||cpuis("MK10DN512ZVLL10*")||cpuis("MK10DN512ZVMC10")||cpuis("MK11DN512VLK5R")||cpuis("MK11DN512AVLK5R")||cpuis("MK20D????ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R") sif !cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMC10R") newline rbitfld.byte 0x01 3. " SWAP ,Swap" "0 block at 0x0000,1 block at 0x0000" rbitfld.byte 0x01 2. " PFLSH ,Flash configuration" ",Program flash only" newline rbitfld.byte 0x01 1. " RAMRDY ,RAM ready" "Not available,Available" else newline rbitfld.byte 0x01 3. " SWAP ,Swap" "0 block at 0x0000,1 block at 0x0000" rbitfld.byte 0x01 2. " PFLSH ,Flash configuration" ",Program flash only" newline rbitfld.byte 0x01 1. " RAMRDY ,RAM ready" "Not available,Available" rbitfld.byte 0x01 0. " EEERDY ,EEPROM ready" "Not available,Available" endif elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK21D*AVMC5R") newline rbitfld.byte 0x01 3. " SWAP ,Swap" "0 block at 0x0000,1 block at 0x0000" rbitfld.byte 0x01 2. " PFLSH ,Flash configuration" ",Program flash only" newline rbitfld.byte 0x01 1. " RAMRDY ,RAM ready" "Not available,Available" rbitfld.byte 0x01 0. " EEERDY ,EEPROM ready" "Not available,Available" elif cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R") newline rbitfld.byte 0x01 3. " SWAP ,Swap" "0 block at 0x0000,1 block at 0x0000" rbitfld.byte 0x01 2. " PFLSH ,Flash configuration" ",4 flash blocks" newline rbitfld.byte 0x01 1. " RAMRDY ,RAM ready" "Not available,Available" rbitfld.byte 0x01 0. " EEERDY ,EEPROM ready" "Not available,Available" elif cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5") newline rbitfld.byte 0x01 3. " SWAP ,Swap" "0 block at 0x0000,?..." rbitfld.byte 0x01 2. " PFLSH ,Flash configuration" "2 flash and 2 FlexNVM blocks,?..." newline rbitfld.byte 0x01 1. " RAMRDY ,RAM ready" "Not available,Available" rbitfld.byte 0x01 0. " EEERDY ,EEPROM ready" "Not available,Available" elif cpuis("MK27FN2M0VMI15")||cpuis("?K28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") newline rbitfld.byte 0x01 3. " SWAP ,Indicates which half of program flash space is located at relative address 0x0000" "0/1 blocks,2/3 blocks" rbitfld.byte 0x01 1. " RAMRDY ,RAM ready" "Not available,Available" elif cpuis("MK84FN2M0CAU15R")||cpuis("KK60DN512ZCAB10R") newline rbitfld.byte 0x01 3. " SWAP ,Indicates which half of program flash space is located at relative address 0x0000" "0/1 blocks,2/3 blocks" rbitfld.byte 0x01 2. " PFLSH ,FTFE configuration (number of supported blocks)" ",4 flash blocks" newline rbitfld.byte 0x01 1. " RAMRDY ,RAM ready" "Not ready,Ready" elif cpuis("MK???X*")||cpuis("MK22FN1M0VMC10")||cpuis("MK53DN512ZCMD10")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DN512ZVMC10*") sif !cpuis("MK02*") sif cpuis("MK21D*AVLK5")||cpuis("MK21D*AVMC5")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7") newline rbitfld.byte 0x01 2. " PFLSH ,Flash configuration" "Flash and/or EEPROM,?..." elif cpuis("MK20DN512ZVMC10*")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VLQ10R")||cpuis("MK10DX256ZVLQ10")||cpuis("MK10DX256ZVLQ10R")||cpuis("MK10DX256ZVMD10")||cpuis("MK40D*Z*10")||cpuis("MK50DX256ZCLL10")||cpuis("MK51DX256ZCMC10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DX256ZVLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DX256ZCMC10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20D????ZVLL10") newline rbitfld.byte 0x01 3. " SWAP ,Swap" "0 block at 0x0000,1 block at 0x0000" rbitfld.byte 0x01 2. " PFLSH ,Flash configuration" "Flash and/or EEPROM,?..." elif cpuis("MK21F*AVLQ12")||cpuis("MK21F*AVMD12")||cpuis("MK21F*AVMC12")||cpuis("MK22FX512*")||cpuis("MK21FX512VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVLH12") newline rbitfld.byte 0x01 3. " SWAP ,Swap" "0 block at 0x0000,?..." rbitfld.byte 0x01 2. " PFLSH ,Flash configuration" "2 flash and 2 FlexNVM blocks,?..." elif !cpuis("MK10D?128V??5")&&!cpuis("MK10D?64V??5")&&!cpuis("MK10D?32V??5")&&!cpuis("MK10*7")&&!cpuis("MK30DX256VLL7R") newline rbitfld.byte 0x01 3. " SWAP ,Swap" "0 block at 0x0000,1 block at 0x0000" rbitfld.byte 0x01 2. " PFLSH ,Flash configuration" "2 flash and 2 FlexNVM blocks,?..." else newline rbitfld.byte 0x01 2. " PFLSH ,Flash configuration" "2 flash and 2 FlexNVM blocks,?..." endif newline rbitfld.byte 0x01 1. " RAMRDY ,RAM ready" "FlexRAM not available,FlexRAM available" sif !cpuis("MK20DX256VLK10R") newline rbitfld.byte 0x01 0. " EEERDY ,EEPROM ready" "Not available,Available" endif endif elif cpuis("MK???N*")||cpuis("KK26FN2M0CAC18R") sif !cpuis("MK02*")&&!cpuis("MK22FN256*")&&!cpuis("MK22FN128*")&&!cpuis("MK8?FN256V*")&&!cpuis("MK22FN512VMP12")&&!cpuis("MK22FN512VLL12")&&!cpuis("MK22FN512VLH12")&&!cpuis("MK22FN512VDC12")&&!cpuis("MK22FN512CBP12R")&&!cpuis("MK22FN512CAP12R")&&!cpuis("MK24FN256VDC12")&&!cpuis("MK22FN512VDC12R")&&!cpuis("MK22FN512VFX12*")&&!cpuis("MK22FN512VLH12R") sif (cpuis("MK21F*AVLQ12")||cpuis("MK21F*AVMD12"))||cpuis("MK21D*AVMC5")||cpuis("MK21F*AVMC12")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK40D*Z*10")||cpuis("MK21FN1M0VMD10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VMC10")||cpuis("MK21FN1M0VMC10")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLH12")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZCAB10R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10") newline rbitfld.byte 0x01 3. " SWAP ,Swap" "0 block at 0x0000,1 block at 0x0000" elif cpuis("MK20FN1M0VLQ12R")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK60FN1M0VLQ15")||cpuis("MK70FN1M0VMJ12R")||cpuis("MK70FN1M0VMJ15R")||cpuis("KK26FN2M0CAC18R") newline rbitfld.byte 0x01 3. " SWAP ,Swap" "0/1 block at 0x0000,2/3 block at 0x0000" elif !cpuis("MK10D?128V??5")&&!cpuis("MK10D?64V??5")&&!cpuis("MK10D?32V??5")&&!cpuis("MK10DN512ZVLK10")&&!cpuis("MK10DN512ZVLK10R")&&!cpuis("MK10DN512ZVLL10")&&!cpuis("MK10DN512ZVLL10R")&&!cpuis("MK10DN512ZVMC10")&&!cpuis("MK11DN512VLK5R")&&!cpuis("MK11DN512AVLK5R")&&!cpuis("MK10*7")&&!cpuis("MK70FN1M0VMJ12R")&&!cpuis("MK70FN1M0VMJ15R") newline rbitfld.byte 0x01 3. " SWAP ,Swap" "0 block at 0x0000,?..." endif sif cpuis("MK21D*AVLK5")||cpuis("MK21D*AVMC5")||cpuis("MK20DX256VLK10R")||cpuis("MK60DN512ZCAB10R") newline bitfld.byte 0x01 2. " PFLSH ,Flash configuration" ",Program flash only" rbitfld.byte 0x01 1. " RAMRDY ,RAM ready" "Not available,Available" elif cpuis("MK50DN512ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10") newline rbitfld.byte 0x01 2. " PFLSH ,Flash configuration" ",Program flash only" rbitfld.byte 0x01 1. " RAMRDY ,RAM ready" "Not available,Available" elif cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R") newline rbitfld.byte 0x01 2. " PFLSH ,Flash configuration" ",2 flash blocks" rbitfld.byte 0x01 1. " RAMRDY ,RAM ready" "Not available,Available" else newline rbitfld.byte 0x01 2. " PFLSH ,Flash configuration" ",4 flash blocks" rbitfld.byte 0x01 1. " RAMRDY ,RAM ready" "Not available,Available" endif sif (cpuis("MK10F????VLQ12")||cpuis("MK10F????VMD12"))||(cpuis("MK10D?128V??5")||cpuis("MK10D?64V??5")||cpuis("MK10D?32V??5"))||cpuis("MK10DN512VLQ10")||cpuis("MK10DN512VMD10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK60FN1M0VLQ15")||cpuis("KK26FN2M0CAC18R") newline rbitfld.byte 0x01 0. " EEERDY ,EEPROM ready" "Not available,Available" endif endif endif rgroup.byte 0x02++0x01 line.byte 0x00 "FSEC,Flash Security Register" bitfld.byte 0x00 6.--7. " KEYEN ,Backdoor key security enable" "Disabled,Disabled,Enabled,Disabled" bitfld.byte 0x00 4.--5. " MEEN ,Mass erase enable bits" "Enabled,Enabled,Disabled,Enabled" newline bitfld.byte 0x00 2.--3. " FSLACC ,Freescale failure analysis access code" "Granted,Denied,Denied,Granted" bitfld.byte 0x00 0.--1. " SEC ,Flash security" "Secure,Secure,Unsecure,Secure" line.byte 0x01 "FOPT,Flash Option Register" sif cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.byte 0x01 6.--7. " BOOTSRC_SEL ,Boot source selection" "Internal flash,,ROM/QSPI0,ROM/boot loader mode" newline endif sif cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12*")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.byte 0x01 5. " FAST_INIT ,Select initialization speed on POR\VLLSx and any system reset" "Slower initialization,Fast initialization" newline endif sif cpuis("MK22FN1M0VMC10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLK10")||cpuis("MK21FX512VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN128CAH12R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK20DX256VLQ10R")||cpuis("MK20DX256VLK7R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VMC7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK70*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVLQ10*")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12*")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK63FN1M0VLQ12")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18")||cpuis("MK66FN2M0VLQ18") sif !cpuis("MK50DN512ZCLL10")&&!cpuis("MK50DX256ZCLL10")&&!cpuis("MK50DN512ZCLQ10")&&!cpuis("MK50DX256ZCLQ10")&&!cpuis("MK51DN512ZCLL10")&&!cpuis("MK51DN512ZCMC10")&&!cpuis("MK51DX256ZCMC10")&&!cpuis("MK51DN256ZCMD10")&&!cpuis("MK51DN512ZCLQ10")&&!cpuis("MK52DN512ZCLQ10")&&!cpuis("MK52DN512ZCMD10")&&!cpuis("MK53DN512ZCLQ10")&&!cpuis("MK53DN512ZCMD10")&&!cpuis("MK53DX256ZCLQ10")&&!cpuis("MK70*")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("MK20DN512ZVLQ10*")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10*")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVMC10*")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.byte 0x01 2. " NMI_DIS ,Enable/disable control for the NMI function" "Disabled,Enabled" newline endif sif !cpuis("MKS20FN128VFT12")&&!cpuis("MKS20FN128VLH12")&&!cpuis("MKS20FN128VLL12")&&!cpuis("MKS20FN256VFT12")&&!cpuis("MKS20FN256VLH12")&&!cpuis("MKS20FN256VLL12")&&!cpuis("MKS22FN128VFT12")&&!cpuis("MKS22FN128VLH12")&&!cpuis("MKS22FN128VLL12")&&!cpuis("MKS22FN256VFT12")&&!cpuis("MKS22FN256VLH12")&&!cpuis("MKS22FN256VLL12") bitfld.byte 0x01 1. " EZPORT_DIS ,Enable/disable EzPort function" "Disabled,Enabled" newline endif bitfld.byte 0x01 0. " LPBOOT ,Control the reset value of OUTDIVx values in SIM_CLKDIV1 register" "Low-power boot,Normal boot" endif width 9. newline sif cpuis("MK22FN1M0VMC10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLH10")||cpuis("MK21FX512VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN128CAH12R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK20DX256VLQ10R")||cpuis("MK20DX256VLK7R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VMC7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") if (((per.b(ad:0x40020000))&0x80)==0x0)||(((per.b(ad:0x40020000+0x01))&0x10)==0x10) rgroup.byte (0x04+0x0)++0x00 line.byte 0x00 "FCCOB3,Flash Common Command Object Register" rgroup.byte (0x04+0x1)++0x00 line.byte 0x00 "FCCOB2,Flash Common Command Object Register" rgroup.byte (0x04+0x2)++0x00 line.byte 0x00 "FCCOB1,Flash Common Command Object Register" rgroup.byte (0x04+0x3)++0x00 line.byte 0x00 "FCCOB0,Flash Common Command Object Register" rgroup.byte (0x04+0x4)++0x00 line.byte 0x00 "FCCOB7,Flash Common Command Object Register" rgroup.byte (0x04+0x5)++0x00 line.byte 0x00 "FCCOB6,Flash Common Command Object Register" rgroup.byte (0x04+0x6)++0x00 line.byte 0x00 "FCCOB5,Flash Common Command Object Register" rgroup.byte (0x04+0x7)++0x00 line.byte 0x00 "FCCOB4,Flash Common Command Object Register" rgroup.byte (0x04+0x8)++0x00 line.byte 0x00 "FCCOBB,Flash Common Command Object Register" rgroup.byte (0x04+0x9)++0x00 line.byte 0x00 "FCCOBA,Flash Common Command Object Register" rgroup.byte (0x04+0xA)++0x00 line.byte 0x00 "FCCOB9,Flash Common Command Object Register" rgroup.byte (0x04+0xB)++0x00 line.byte 0x00 "FCCOB8,Flash Common Command Object Register" rgroup.byte 0x10++0x03 line.byte 0x00 "FPROT_3,Program Flash Protection Register 3" bitfld.byte 0x00 7. " PROT_[7] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 6. " [6] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 5. " [5] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 4. " [4] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x00 3. " [3] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 2. " [2] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 1. " [1] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 0. " [0] ,Program flash region protect" "Protected,Not protected" line.byte 0x01 "FPROT_2,Program Flash Protection Register 2" bitfld.byte 0x01 7. " [15] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 6. " [14] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 5. " [13] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 4. " [12] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x01 3. " [11] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 2. " [10] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 1. " [9] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 0. " [8] ,Program flash region protect" "Protected,Not protected" line.byte 0x02 "FPROT_1,Program Flash Protection Register 1" bitfld.byte 0x02 7. " [23] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 6. " [22] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 5. " [21] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 4. " [20] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x02 3. " [19] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 2. " [18] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 1. " [17] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 0. " [16] ,Program flash region protect" "Protected,Not protected" line.byte 0x03 "FPROT_0,Program Flash Protection Register 0" bitfld.byte 0x03 7. " [31] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 6. " [30] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 5. " [29] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 4. " [28] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x03 3. " [27] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 2. " [26] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 1. " [25] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 0. " [24] ,Program flash region protect" "Protected,Not protected" newline else group.byte (0x04+0x0)++0x00 line.byte 0x00 "FCCOB3,Flash Common Command Object Register" group.byte (0x04+0x1)++0x00 line.byte 0x00 "FCCOB2,Flash Common Command Object Register" group.byte (0x04+0x2)++0x00 line.byte 0x00 "FCCOB1,Flash Common Command Object Register" group.byte (0x04+0x3)++0x00 line.byte 0x00 "FCCOB0,Flash Common Command Object Register" group.byte (0x04+0x4)++0x00 line.byte 0x00 "FCCOB7,Flash Common Command Object Register" group.byte (0x04+0x5)++0x00 line.byte 0x00 "FCCOB6,Flash Common Command Object Register" group.byte (0x04+0x6)++0x00 line.byte 0x00 "FCCOB5,Flash Common Command Object Register" group.byte (0x04+0x7)++0x00 line.byte 0x00 "FCCOB4,Flash Common Command Object Register" group.byte (0x04+0x8)++0x00 line.byte 0x00 "FCCOBB,Flash Common Command Object Register" group.byte (0x04+0x9)++0x00 line.byte 0x00 "FCCOBA,Flash Common Command Object Register" group.byte (0x04+0xA)++0x00 line.byte 0x00 "FCCOB9,Flash Common Command Object Register" group.byte (0x04+0xB)++0x00 line.byte 0x00 "FCCOB8,Flash Common Command Object Register" group.byte 0x10++0x03 line.byte 0x00 "FPROT_3,Program Flash Protection Register 3" bitfld.byte 0x00 7. " PROT_[7] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 6. " [6] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 5. " [5] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 4. " [4] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x00 3. " [3] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 2. " [2] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 1. " [1] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 0. " [0] ,Program flash region protect" "Protected,Not protected" line.byte 0x01 "FPROT_2,Program Flash Protection Register 2" bitfld.byte 0x01 7. " [15] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 6. " [14] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 5. " [13] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 4. " [12] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x01 3. " [11] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 2. " [10] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 1. " [9] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 0. " [8] ,Program flash region protect" "Protected,Not protected" line.byte 0x02 "FPROT_1,Program Flash Protection Register 1" bitfld.byte 0x02 7. " [23] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 6. " [22] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 5. " [21] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 4. " [20] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x02 3. " [19] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 2. " [18] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 1. " [17] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 0. " [16] ,Program flash region protect" "Protected,Not protected" line.byte 0x03 "FPROT_0,Program Flash Protection Register 0" bitfld.byte 0x03 7. " [31] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 6. " [30] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 5. " [29] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 4. " [28] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x03 3. " [27] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 2. " [26] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 1. " [25] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 0. " [24] ,Program flash region protect" "Protected,Not protected" newline endif else if (((per.b(ad:0x40020000))&0x80)==0x0)||(((per.b(ad:0x40020000+0x01))&0x10)==0x10) rgroup.byte (0x04+0x0)++0x00 line.byte 0x00 "FCCOB3,Flash Common Command Object Register" rgroup.byte (0x04+0x1)++0x00 line.byte 0x00 "FCCOB2,Flash Common Command Object Register" rgroup.byte (0x04+0x2)++0x00 line.byte 0x00 "FCCOB1,Flash Common Command Object Register" rgroup.byte (0x04+0x3)++0x00 line.byte 0x00 "FCCOB0,Flash Common Command Object Register" rgroup.byte (0x04+0x4)++0x00 line.byte 0x00 "FCCOB7,Flash Common Command Object Register" rgroup.byte (0x04+0x5)++0x00 line.byte 0x00 "FCCOB6,Flash Common Command Object Register" rgroup.byte (0x04+0x6)++0x00 line.byte 0x00 "FCCOB5,Flash Common Command Object Register" rgroup.byte (0x04+0x7)++0x00 line.byte 0x00 "FCCOB4,Flash Common Command Object Register" rgroup.byte (0x04+0x8)++0x00 line.byte 0x00 "FCCOBB,Flash Common Command Object Register" rgroup.byte (0x04+0x9)++0x00 line.byte 0x00 "FCCOBA,Flash Common Command Object Register" rgroup.byte (0x04+0xA)++0x00 line.byte 0x00 "FCCOB9,Flash Common Command Object Register" rgroup.byte (0x04+0xB)++0x00 line.byte 0x00 "FCCOB8,Flash Common Command Object Register" rgroup.byte 0x10++0x03 line.byte 0x00 "FPROT_3,Program Flash Protection Register 3" bitfld.byte 0x00 7. " PROT_[31] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 6. " [30] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 5. " [29] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 4. " [28] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x00 3. " [27] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 2. " [26] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 1. " [25] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 0. " [24] ,Program flash region protect" "Protected,Not protected" line.byte 0x01 "FPROT_2,Program Flash Protection Register 2" bitfld.byte 0x01 7. " [23] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 6. " [22] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 5. " [21] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 4. " [20] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x01 3. " [19] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 2. " [18] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 1. " [17] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 0. " [16] ,Program flash region protect" "Protected,Not protected" line.byte 0x02 "FPROT_1,Program Flash Protection Register 1" bitfld.byte 0x02 7. " [15] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 6. " [14] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 5. " [13] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 4. " [12] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x02 3. " [11] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 2. " [10] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 1. " [9] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 0. " [8] ,Program flash region protect" "Protected,Not protected" line.byte 0x03 "FPROT_0,Program Flash Protection Register 0" bitfld.byte 0x03 7. " [7] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 6. " [6] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 5. " [5] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 4. " [4] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x03 3. " [3] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 2. " [2] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 1. " [1] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 0. " [0] ,Program flash region protect" "Protected,Not protected" newline else group.byte (0x04+0x0)++0x00 line.byte 0x00 "FCCOB3,Flash Common Command Object Register" group.byte (0x04+0x1)++0x00 line.byte 0x00 "FCCOB2,Flash Common Command Object Register" group.byte (0x04+0x2)++0x00 line.byte 0x00 "FCCOB1,Flash Common Command Object Register" group.byte (0x04+0x3)++0x00 line.byte 0x00 "FCCOB0,Flash Common Command Object Register" group.byte (0x04+0x4)++0x00 line.byte 0x00 "FCCOB7,Flash Common Command Object Register" group.byte (0x04+0x5)++0x00 line.byte 0x00 "FCCOB6,Flash Common Command Object Register" group.byte (0x04+0x6)++0x00 line.byte 0x00 "FCCOB5,Flash Common Command Object Register" group.byte (0x04+0x7)++0x00 line.byte 0x00 "FCCOB4,Flash Common Command Object Register" group.byte (0x04+0x8)++0x00 line.byte 0x00 "FCCOBB,Flash Common Command Object Register" group.byte (0x04+0x9)++0x00 line.byte 0x00 "FCCOBA,Flash Common Command Object Register" group.byte (0x04+0xA)++0x00 line.byte 0x00 "FCCOB9,Flash Common Command Object Register" group.byte (0x04+0xB)++0x00 line.byte 0x00 "FCCOB8,Flash Common Command Object Register" group.byte 0x10++0x03 line.byte 0x00 "FPROT_3,Program Flash Protection Register 3" bitfld.byte 0x00 7. " PROT_[31] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 6. " [30] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 5. " [29] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 4. " [28] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x00 3. " [27] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 2. " [26] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 1. " [25] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 0. " [24] ,Program flash region protect" "Protected,Not protected" line.byte 0x01 "FPROT_2,Program Flash Protection Register 2" bitfld.byte 0x01 7. " [23] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 6. " [22] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 5. " [21] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 4. " [20] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x01 3. " [19] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 2. " [18] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 1. " [17] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 0. " [16] ,Program flash region protect" "Protected,Not protected" line.byte 0x02 "FPROT_1,Program Flash Protection Register 1" bitfld.byte 0x02 7. " [15] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 6. " [14] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 5. " [13] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 4. " [12] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x02 3. " [11] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 2. " [10] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 1. " [9] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 0. " [8] ,Program flash region protect" "Protected,Not protected" line.byte 0x03 "FPROT_0,Program Flash Protection Register 0" bitfld.byte 0x03 7. " [7] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 6. " [6] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 5. " [5] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 4. " [4] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x03 3. " [3] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 2. " [2] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 1. " [1] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 0. " [0] ,Program flash region protect" "Protected,Not protected" newline endif endif sif !cpuis("MK8?FN256V*")&&!cpuis("MK02*")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK50DX256ZCLQ10")&&!cpuis("MK50DN512ZCLQ10")&&!cpuis("MK51DN256ZCMD10")&&!cpuis("MK51DN512ZCLQ10")&&!cpuis("MK52DN512ZCLQ10")&&!cpuis("MK52DN512ZCMD10")&&!cpuis("MK40D*ZVLL10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DN512ZCAB10R")&&!cpuis("MKS20FN128V??12")&&!cpuis("MKS22FN128V??12")&&!cpuis("MKS20FN256V??12")&&!cpuis("MKS22FN256V??12")&&!cpuis("MK20D????ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("KK22FN???CAH12R")&&!cpuis("MK22FN256VLL12R")&&!cpuis("KK22FN???C?P12R")&&!cpuis("MK22FN512VDC12*")&&!cpuis("MK22FN512VFX12*")&&!cpuis("MK22FN512VLH12R")&&!cpuis("MK22FN128VLH10R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("?K28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK10DN512ZV??10*")&&!cpuis("MK10DX256ZV??10*")&&!cpuis("MK11DN512AVLK5*")&&!cpuis("MK11DN512VLK5*")&&!cpuis("MK20DN512VLK10")&&!cpuis("MK22FN128VLH10")&&!cpuis("MK22FN512VLH12")&&!cpuis("MK22FN256VLL12")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") if (((per.l(ad:0x40020000))&0x80)==0x0)||(((per.l(ad:0x40020000+0x01))&0x10)==0x10) sif cpuis("MK???X*") rgroup.byte 0x16++0x01 line.byte 0x00 "FEPROT,EEPROM Protection Register" bitfld.byte 0x00 7. " EPROT_[7] ,EEPROM region protect" "Protected,Not protected" bitfld.byte 0x00 6. " [6] ,EEPROM region protect" "Protected,Not protected" bitfld.byte 0x00 5. " [5] ,EEPROM region protect" "Protected,Not protected" bitfld.byte 0x00 4. " [4] ,EEPROM region protect" "Protected,Not protected" newline bitfld.byte 0x00 3. " [3] ,EEPROM region protect" "Protected,Not protected" bitfld.byte 0x00 2. " [2] ,EEPROM region protect" "Protected,Not protected" bitfld.byte 0x00 1. " [1] ,EEPROM region protect" "Protected,Not protected" bitfld.byte 0x00 0. " [0] ,EEPROM region protect" "Protected,Not protected" line.byte 0x01 "FDPROT,Data Flash Protection Register" bitfld.byte 0x01 7. " DPROT_[7] ,Data flash region protect" "Protected,Not protected" bitfld.byte 0x01 6. " [6] ,Data flash region protect" "Protected,Not protected" bitfld.byte 0x01 5. " [5] ,Data flash region protect" "Protected,Not protected" bitfld.byte 0x01 4. " [4] ,Data flash region protect" "Protected,Not protected" newline bitfld.byte 0x01 3. " [3] ,Data flash region protect" "Protected,Not protected" bitfld.byte 0x01 2. " [2] ,Data flash region protect" "Protected,Not protected" bitfld.byte 0x01 1. " [1] ,Data flash region protect" "Protected,Not protected" bitfld.byte 0x01 0. " [0] ,Data flash region protect" "Protected,Not protected" else hgroup.byte 0x16++0x0 hide.byte 0x00 "FEPROT,EEPROM Protection Register" rgroup.byte 0x17++0x00 line.byte 0x00 "FDPROT,Data Flash Protection Register" bitfld.byte 0x00 7. " DPROT_[7] ,Data flash region protect" "Protected,Not protected" bitfld.byte 0x00 6. " [6] ,Data flash region protect" "Protected,Not protected" bitfld.byte 0x00 5. " [5] ,Data flash region protect" "Protected,Not protected" bitfld.byte 0x00 4. " [4] ,Data flash region protect" "Protected,Not protected" newline bitfld.byte 0x00 3. " [3] ,Data flash region protect" "Protected,Not protected" bitfld.byte 0x00 2. " [2] ,Data flash region protect" "Protected,Not protected" bitfld.byte 0x00 1. " [1] ,Data flash region protect" "Protected,Not protected" bitfld.byte 0x00 0. " [0] ,Data flash region protect" "Protected,Not protected" endif else sif cpuis("MK???X*") group.byte 0x16++0x01 line.byte 0x00 "FEPROT,EEPROM Protection Register" bitfld.byte 0x00 7. " EPROT_[7] ,EEPROM region protect" "Protected,Not protected" bitfld.byte 0x00 6. " [6] ,EEPROM region protect" "Protected,Not protected" bitfld.byte 0x00 5. " [5] ,EEPROM region protect" "Protected,Not protected" bitfld.byte 0x00 4. " [4] ,EEPROM region protect" "Protected,Not protected" newline bitfld.byte 0x00 3. " [3] ,EEPROM region protect" "Protected,Not protected" bitfld.byte 0x00 2. " [2] ,EEPROM region protect" "Protected,Not protected" bitfld.byte 0x00 1. " [1] ,EEPROM region protect" "Protected,Not protected" bitfld.byte 0x00 0. " [0] ,EEPROM region protect" "Protected,Not protected" line.byte 0x01 "FDPROT,Data Flash Protection Register" bitfld.byte 0x01 7. " DPROT_[7] ,Data flash region protect" "Protected,Not protected" bitfld.byte 0x01 6. " [6] ,Data flash region protect" "Protected,Not protected" bitfld.byte 0x01 5. " [5] ,Data flash region protect" "Protected,Not protected" bitfld.byte 0x01 4. " [4] ,Data flash region protect" "Protected,Not protected" newline bitfld.byte 0x01 3. " [3] ,Data flash region protect" "Protected,Not protected" bitfld.byte 0x01 2. " [2] ,Data flash region protect" "Protected,Not protected" bitfld.byte 0x01 1. " [1] ,Data flash region protect" "Protected,Not protected" bitfld.byte 0x01 0. " [0] ,Data flash region protect" "Protected,Not protected" else hgroup.byte 0x16++0x0 hide.byte 0x00 "FEPROT,EEPROM Protection Register" group.byte 0x17++0x00 line.byte 0x00 "FDPROT,Data Flash Protection Register" bitfld.byte 0x00 7. " DPROT_[7] ,Data flash region protect" "Protected,Not protected" bitfld.byte 0x00 6. " [6] ,Data flash region protect" "Protected,Not protected" bitfld.byte 0x00 5. " [5] ,Data flash region protect" "Protected,Not protected" bitfld.byte 0x00 4. " [4] ,Data flash region protect" "Protected,Not protected" newline bitfld.byte 0x00 3. " [3] ,Data flash region protect" "Protected,Not protected" bitfld.byte 0x00 2. " [2] ,Data flash region protect" "Protected,Not protected" bitfld.byte 0x00 1. " [1] ,Data flash region protect" "Protected,Not protected" bitfld.byte 0x00 0. " [0] ,Data flash region protect" "Protected,Not protected" endif endif newline endif sif cpuis("MK02*")||cpuis("MK66*")||cpuis("MK65*")||cpuis("MK22FN256*")||cpuis("MK22FN128*")||cpuis("MK26FN*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MKS20FN128V??12")||cpuis("MKS22FN128V??12")||cpuis("MKS20FN256V??12")||cpuis("MKS22FN256V??12")||cpuis("KK22FN???C?P12R")||cpuis("MK22FN512VFX12*")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN???CAH12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("?K28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK22FN128CAH12R") rgroup.byte 0x18++0x03 line.byte 0x00 "XACCH3,Execute-only Access Register 3" bitfld.byte 0x00 7. " XA_[39] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x00 6. " [38] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x00 5. " [37] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x00 4. " [36] ,Execute-only access control" "Execute-only,Execute/Data" newline bitfld.byte 0x00 3. " [35] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x00 2. " [34] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x00 1. " [33] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x00 0. " [32] ,Execute-only access control" "Execute-only,Execute/Data" line.byte 0x01 "XACCH2,Execute-only Access Register 2" bitfld.byte 0x01 7. " [47] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x01 6. " [46] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x01 5. " [45] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x01 4. " [44] ,Execute-only access control" "Execute-only,Execute/Data" newline bitfld.byte 0x01 3. " [43] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x01 2. " [42] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x01 1. " [41] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x01 0. " [40] ,Execute-only access control" "Execute-only,Execute/Data" line.byte 0x02 "XACCH1,Execute-only Access Register 1" bitfld.byte 0x02 7. " [55] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x02 6. " [54] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x02 5. " [53] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x02 4. " [52] ,Execute-only access control" "Execute-only,Execute/Data" newline bitfld.byte 0x02 3. " [51] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x02 2. " [50] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x02 1. " [49] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x02 0. " [48] ,Execute-only access control" "Execute-only,Execute/Data" line.byte 0x03 "XACCH0,Execute-only Access Register 0" bitfld.byte 0x03 7. " [63] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x03 6. " [62] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x03 5. " [61] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x03 4. " [60] ,Execute-only access control" "Execute-only,Execute/Data" newline bitfld.byte 0x03 3. " [59] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x03 2. " [58] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x03 1. " [57] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x03 0. " [56] ,Execute-only access control" "Execute-only,Execute/Data" endif rgroup.byte 0x1C++0x03 line.byte 0x00 "XACCL3,Execute-only Access Register 3" sif cpuis("MK22FN128CAH12R") bitfld.byte 0x00 7. " XA_[7] ,Execute-only access control" "Execute-only,Execute/Data" else bitfld.byte 0x00 7. " [7] ,Execute-only access control" "Execute-only,Execute/Data" endif bitfld.byte 0x00 6. " [6] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x00 5. " [5] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x00 4. " [4] ,Execute-only access control" "Execute-only,Execute/Data" newline bitfld.byte 0x00 3. " [3] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x00 2. " [2] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x00 1. " [1] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x00 0. " [0] ,Execute-only access control" "Execute-only,Execute/Data" line.byte 0x01 "XACCL2,Execute-only Access Register 2" bitfld.byte 0x01 7. " [15] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x01 6. " [14] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x01 5. " [13] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x01 4. " [12] ,Execute-only access control" "Execute-only,Execute/Data" newline bitfld.byte 0x01 3. " [11] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x01 2. " [10] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x01 1. " [9] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x01 0. " [8] ,Execute-only access control" "Execute-only,Execute/Data" line.byte 0x02 "XACCL1,Execute-only Access Register 1" bitfld.byte 0x02 7. " [23] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x02 6. " [22] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x02 5. " [21] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x02 4. " [20] ,Execute-only access control" "Execute-only,Execute/Data" newline bitfld.byte 0x02 3. " [19] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x02 2. " [18] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x02 1. " [17] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x02 0. " [16] ,Execute-only access control" "Execute-only,Execute/Data" line.byte 0x03 "XACCL0,Execute-only Access Register 0" bitfld.byte 0x03 7. " [31] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x03 6. " [30] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x03 5. " [29] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x03 4. " [28] ,Execute-only access control" "Execute-only,Execute/Data" newline bitfld.byte 0x03 3. " [27] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x03 2. " [26] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x03 1. " [25] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x03 0. " [24] ,Execute-only access control" "Execute-only,Execute/Data" newline sif !cpuis("MK22FN128CAH12R") rgroup.byte 0x20++0x03 line.byte 0x00 "SACCH3,Supervisor-only Access Register 3" bitfld.byte 0x00 7. " SA_[39] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x00 6. " [38] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x00 5. " [37] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x00 4. " [36] ,Supervisor-only access control" "Supervisor,User/Supervisor" newline bitfld.byte 0x00 3. " [35] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x00 2. " [34] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x00 1. " [33] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x00 0. " [32] ,Supervisor-only access control" "Supervisor,User/Supervisor" line.byte 0x01 "SACCH2,Supervisor-only Access Register 2" bitfld.byte 0x01 7. " [47] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x01 6. " [46] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x01 5. " [45] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x01 4. " [44] ,Supervisor-only access control" "Supervisor,User/Supervisor" newline bitfld.byte 0x01 3. " [43] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x01 2. " [42] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x01 1. " [41] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x01 0. " [40] ,Supervisor-only access control" "Supervisor,User/Supervisor" line.byte 0x02 "SACCH1,Supervisor-only Access Register 1" bitfld.byte 0x02 7. " [55] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x02 6. " [54] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x02 5. " [53] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x02 4. " [52] ,Supervisor-only access control" "Supervisor,User/Supervisor" newline bitfld.byte 0x02 3. " [51] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x02 2. " [50] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x02 1. " [49] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x02 0. " [48] ,Supervisor-only access control" "Supervisor,User/Supervisor" line.byte 0x03 "SACCH0,Supervisor-only Access Register 0" bitfld.byte 0x03 7. " [63] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x03 6. " [62] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x03 5. " [61] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x03 4. " [60] ,Supervisor-only access control" "Supervisor,User/Supervisor" newline bitfld.byte 0x03 3. " [59] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x03 2. " [58] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x03 1. " [57] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x03 0. " [56] ,Supervisor-only access control" "Supervisor,User/Supervisor" endif rgroup.byte 0x24++0x03 line.byte 0x00 "SACCL3,Supervisor-only Access Register 3" sif cpuis("MK22FN128CAH12R") bitfld.byte 0x00 7. " SA_[7] ,Supervisor-only access control" "Supervisor,User/Supervisor" else bitfld.byte 0x00 7. " [7] ,Supervisor-only access control" "Supervisor,User/Supervisor" endif bitfld.byte 0x00 6. " [6] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x00 5. " [5] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x00 4. " [4] ,Supervisor-only access control" "Supervisor,User/Supervisor" newline bitfld.byte 0x00 3. " [3] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x00 2. " [2] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x00 1. " [1] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x00 0. " [0] ,Supervisor-only access control" "Supervisor,User/Supervisor" line.byte 0x01 "SACCL2,Supervisor-only Access Register 2" bitfld.byte 0x01 7. " [15] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x01 6. " [14] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x01 5. " [13] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x01 4. " [12] ,Supervisor-only access control" "Supervisor,User/Supervisor" newline bitfld.byte 0x01 3. " [11] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x01 2. " [10] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x01 1. " [9] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x01 0. " [8] ,Supervisor-only access control" "Supervisor,User/Supervisor" line.byte 0x02 "SACCL1,Supervisor-only Access Register 1" bitfld.byte 0x02 7. " [23] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x02 6. " [22] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x02 5. " [21] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x02 4. " [20] ,Supervisor-only access control" "Supervisor,User/Supervisor" newline bitfld.byte 0x02 3. " [19] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x02 2. " [18] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x02 1. " [17] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x02 0. " [16] ,Supervisor-only access control" "Supervisor,User/Supervisor" line.byte 0x03 "SACCL0,Supervisor-only Access Register 0" bitfld.byte 0x03 7. " [31] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x03 6. " [30] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x03 5. " [29] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x03 4. " [28] ,Supervisor-only access control" "Supervisor,User/Supervisor" newline bitfld.byte 0x03 3. " [27] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x03 2. " [26] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x03 1. " [25] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x03 0. " [24] ,Supervisor-only access control" "Supervisor,User/Supervisor" rgroup.byte 0x28++0x00 line.byte 0x00 "FACSS,Flash Access Segment Size Register" rgroup.byte 0x2B++0x00 line.byte 0x00 "FACSN,Flash Access Segment Number Register" endif width 0x0B tree.end tree "SDRAM (Synchronous DRAM Controller Module)" base ad:0x4000F000 width 6. group.word 0x42++0x01 line.word 0x00 "CTRL,Control Register" bitfld.word 0x00 11. " IS ,Initiate self-refresh command" "No action,Self-refresh" bitfld.word 0x00 9.--10. " RTIM ,Refresh timing" "3 clocks,6 clocks,9 clocks,9 clocks" hexmask.word 0x00 0.--8. 1. " RC ,Refresh count" if (((per.l(ad:0x4000F000+(0x48)))&0x30)==0x10) group.long 0x48++0x03 line.long 0x00 "AC0,Address and Control Register 0" hexmask.long.word 0x00 18.--31. 0x04 " BA ,Base address register" bitfld.long 0x00 15. " RE ,Refresh enable" "Disabled,Enabled" bitfld.long 0x00 12.--13. " CASL ,CAS latency [TRCD/TCASL/TRAS/TRP/TRWL&TRDL/TEP]" "1/1/2/1/1/1,2/2/4/2/1/1,3/3/6/3/1/1,3/3/6/3/1/1" newline bitfld.long 0x00 8.--10. " CBM ,Command and bank MUX" ",18,19,20,21,22,23,?..." bitfld.long 0x00 6. " IMRS ,Initiate mode register set command" "No action,Mrs command" bitfld.long 0x00 4.--5. " PS ,Port size" "32bit,8bit,16bit,16bit" newline bitfld.long 0x00 3. " IP ,Initiate precharge all" "No action,Enabled" else group.long 0x48++0x03 line.long 0x00 "AC0,Address and Control Register 0" hexmask.long.word 0x00 18.--31. 0x04 " BA ,Base address register" bitfld.long 0x00 15. " RE ,Refresh enable" "Disabled,Enabled" bitfld.long 0x00 12.--13. " CASL ,CAS latency [TRCD/TCASL/TRAS/TRP/TRWL&TRDL/TEP]" "1/1/2/1/1/1,2/2/4/2/1/1,3/3/6/3/1/1,3/3/6/3/1/1" newline bitfld.long 0x00 8.--10. " CBM ,Command and bank MUX" "17,18,19,20,21,22,23,?..." bitfld.long 0x00 6. " IMRS ,Initiate mode register set command" "No action,Mrs command" bitfld.long 0x00 4.--5. " PS ,Port size" "32bit,8bit,16bit,16bit" newline bitfld.long 0x00 3. " IP ,Initiate precharge all" "No action,Enabled" endif group.long (0x48+0x04)++0x03 line.long 0x00 "CM0,Control Mask 0" bitfld.long 0x00 31. " BAM ,Base address bit 13 mask" "0,1" bitfld.long 0x00 30. ",Base address bit 12 mask" "0,1" bitfld.long 0x00 29. ",Base address bit 11 mask" "0,1" bitfld.long 0x00 28. ",Base address bit 10 mask" "0,1" bitfld.long 0x00 27. ",Base address bit 9 mask" "0,1" bitfld.long 0x00 26. ",Base address bit 8 mask" "0,1" bitfld.long 0x00 25. ",Base address bit 7 mask" "0,1" bitfld.long 0x00 24. ",Base address bit 6 mask" "0,1" bitfld.long 0x00 23. ",Base address bit 5 mask" "0,1" bitfld.long 0x00 22. ",Base address bit 4 mask" "0,1" bitfld.long 0x00 21. ",Base address bit 3 mask" "0,1" bitfld.long 0x00 20. ",Base address bit 2 mask" "0,1" bitfld.long 0x00 19. ",Base address bit 1 mask" "0,1" bitfld.long 0x00 18. ",Base address bit 0 mask" "0,1" bitfld.long 0x00 8. " WP ,Write protect" "Not protected,Protected" bitfld.long 0x00 0. " V ,Valid" "Not decodable,Decodable" if (((per.l(ad:0x4000F000+(0x50)))&0x30)==0x10) group.long 0x50++0x03 line.long 0x00 "AC1,Address and Control Register 1" hexmask.long.word 0x00 18.--31. 0x04 " BA ,Base address register" bitfld.long 0x00 15. " RE ,Refresh enable" "Disabled,Enabled" bitfld.long 0x00 12.--13. " CASL ,CAS latency [TRCD/TCASL/TRAS/TRP/TRWL&TRDL/TEP]" "1/1/2/1/1/1,2/2/4/2/1/1,3/3/6/3/1/1,3/3/6/3/1/1" newline bitfld.long 0x00 8.--10. " CBM ,Command and bank MUX" ",18,19,20,21,22,23,?..." bitfld.long 0x00 6. " IMRS ,Initiate mode register set command" "No action,Mrs command" bitfld.long 0x00 4.--5. " PS ,Port size" "32bit,8bit,16bit,16bit" newline bitfld.long 0x00 3. " IP ,Initiate precharge all" "No action,Enabled" else group.long 0x50++0x03 line.long 0x00 "AC1,Address and Control Register 1" hexmask.long.word 0x00 18.--31. 0x04 " BA ,Base address register" bitfld.long 0x00 15. " RE ,Refresh enable" "Disabled,Enabled" bitfld.long 0x00 12.--13. " CASL ,CAS latency [TRCD/TCASL/TRAS/TRP/TRWL&TRDL/TEP]" "1/1/2/1/1/1,2/2/4/2/1/1,3/3/6/3/1/1,3/3/6/3/1/1" newline bitfld.long 0x00 8.--10. " CBM ,Command and bank MUX" "17,18,19,20,21,22,23,?..." bitfld.long 0x00 6. " IMRS ,Initiate mode register set command" "No action,Mrs command" bitfld.long 0x00 4.--5. " PS ,Port size" "32bit,8bit,16bit,16bit" newline bitfld.long 0x00 3. " IP ,Initiate precharge all" "No action,Enabled" endif group.long (0x50+0x04)++0x03 line.long 0x00 "CM1,Control Mask 1" bitfld.long 0x00 31. " BAM ,Base address bit 13 mask" "0,1" bitfld.long 0x00 30. ",Base address bit 12 mask" "0,1" bitfld.long 0x00 29. ",Base address bit 11 mask" "0,1" bitfld.long 0x00 28. ",Base address bit 10 mask" "0,1" bitfld.long 0x00 27. ",Base address bit 9 mask" "0,1" bitfld.long 0x00 26. ",Base address bit 8 mask" "0,1" bitfld.long 0x00 25. ",Base address bit 7 mask" "0,1" bitfld.long 0x00 24. ",Base address bit 6 mask" "0,1" bitfld.long 0x00 23. ",Base address bit 5 mask" "0,1" bitfld.long 0x00 22. ",Base address bit 4 mask" "0,1" bitfld.long 0x00 21. ",Base address bit 3 mask" "0,1" bitfld.long 0x00 20. ",Base address bit 2 mask" "0,1" bitfld.long 0x00 19. ",Base address bit 1 mask" "0,1" bitfld.long 0x00 18. ",Base address bit 0 mask" "0,1" bitfld.long 0x00 8. " WP ,Write protect" "Not protected,Protected" bitfld.long 0x00 0. " V ,Valid" "Not decodable,Decodable" width 0x0B tree.end tree "QuadSPI (Quad Serial Peripheral Interface)" base ad:0x400DA000 width 9. sif cpuis("MK27FN2M0VMI15")||cpuis("MK28FN2M0VMI15")||cpuis("?K28FN2M0CAU15?") if (((per.l(ad:0x400DA000+0x00)&0x4000)==0x00)) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" hexmask.long.byte 0x00 24.--31. 1. " SCLKCFG ,Serial clock configuration" newline rbitfld.long 0x00 19. " ISD3FB ,Idle signal drive flash B" "Low,High" rbitfld.long 0x00 18. " ISD2FB ,Idle signal drive flash B" "Low,High" rbitfld.long 0x00 17. " ISD3FA ,Idle signal drive flash A" "Low,High" rbitfld.long 0x00 16. " ISD2FA ,Idle signal drive flash A" "Low,High" newline bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO/Buffer" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO/Buffer" "No effect,Clear" newline bitfld.long 0x00 7. " DDR_EN ,DDR mode (2x and 4x clocks)" "Disabled,Enabled" bitfld.long 0x00 6. " DQS_EN ,DQS enable" "Disabled,Enabled" bitfld.long 0x00 5. " DQS_LAT_EN ,DQS Latency Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " END_CFG ,Endianness of the QSPI" "64 bit BE,32 bit LE,32 bit BE,64 bit LE" newline bitfld.long 0x00 1. " SWRSTHD ,Software reset for AHB domain" "No reset,Reset" bitfld.long 0x00 0. " SWRSTSD ,Software reset for Serial Flash domain" "No reset,Reset" else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" hexmask.long.byte 0x00 24.--31. 1. " SCLKCFG ,Serial clock configuration" newline bitfld.long 0x00 19. " ISD3FB ,Idle signal drive flash B" "Low,High" bitfld.long 0x00 18. " ISD2FB ,Idle signal drive flash B" "Low,High" bitfld.long 0x00 17. " ISD3FA ,Idle signal drive flash A" "Low,High" bitfld.long 0x00 16. " ISD2FA ,Idle signal drive flash A" "Low,High" newline bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO/Buffer" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO/Buffer" "No effect,Clear" newline bitfld.long 0x00 7. " DDR_EN ,DDR mode (2x and 4x clocks)" "Disabled,Enabled" bitfld.long 0x00 6. " DQS_EN ,DQS enable" "Disabled,Enabled" bitfld.long 0x00 5. " DQS_LAT_EN ,DQS Latency Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " END_CFG ,Endianness of the QSPI" "64 bit BE,32 bit LE,32 bit BE,64 bit LE" newline bitfld.long 0x00 1. " SWRSTHD ,Software reset for AHB domain" "No reset,Reset" bitfld.long 0x00 0. " SWRSTSD ,Software reset for Serial Flash domain" "No reset,Reset" endif else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" hexmask.long.byte 0x00 24.--31. 1. " SCLKCFG ,Serial Clock Configuration" bitfld.long 0x00 14. " MDIS ,Module disable" "Enabled,Disabled" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO/Buffer" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO/Buffer" "No effect,Clear" newline bitfld.long 0x00 7. " DDR_EN ,DDR mode (2x and 4x clocks)" "Disabled,Enabled" bitfld.long 0x00 6. " DQS_EN ,DQS enable" "Disabled,Enabled" bitfld.long 0x00 5. " DQS_LAT_EN ,DQS Latency Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " END_CFG ,Endianness of the QSPI" "64 bit big endian,32 bit little endian,32 bit big endian,64 bit little endian" newline bitfld.long 0x00 1. " SWRSTHD ,Software reset for AHB domain" "No reset,Reset" bitfld.long 0x00 0. " SWRSTSD ,Software reset for Serial Flash domain" "No reset,Reset" endif if (((per.l(ad:0x400DA000+0x15C)&0x02)==0x00)) group.long 0x08++0x03 line.long 0x00 "IPCR,IP Configuration Register" bitfld.long 0x00 24.--27. " SEQID ,Sequence in the Look-up-table" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16. " PAR_EN ,Parallel mode for triggering a transaction to two serial flash devices" "Disabled,Enabled" hexmask.long.word 0x00 0.--15. 1. " IDATSZ ,Data transfer size (in bytes) of the IP command" else rgroup.long 0x08++0x03 line.long 0x00 "IPCR,IP Configuration Register" bitfld.long 0x00 24.--27. " SEQID ,Sequence in the Look-up-table" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16. " PAR_EN ,Parallel mode for triggering a transaction to two serial flash devices" "Disabled,Enabled" hexmask.long.word 0x00 0.--15. 1. " IDATSZ ,Data transfer size (in bytes) of the IP command" endif sif cpuis("MK27FN2M0VMI15")||cpuis("MK28FN2M0VMI15")||cpuis("?K28FN2M0CAU15?") if (((per.l(ad:0x400DA000+0x15C)&0x06)==0x00)) group.long 0x0C++0x03 line.long 0x00 "FLSHCR,Flash Configuration Register" bitfld.long 0x00 16.--17. " TDH ,Serial flash data in hold time" "Posedge of int. ref. clk.,2x serial flash half clk.,4x serial flash half clk.,?..." newline bitfld.long 0x00 8.--11. " TCSH ,Serial flash CS hold time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " TCSS ,Serial flash CS setup time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.long 0x0C++0x03 line.long 0x00 "FLSHCR,Flash Configuration Register" bitfld.long 0x00 16.--17. " TDH ,Serial flash data in hold time" "Posedge of int. ref. clk.,2x serial flash half clk.,4x serial flash half clk.,?..." newline bitfld.long 0x00 8.--11. " TCSH ,Serial flash CS hold time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " TCSS ,Serial flash CS setup time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else if (((per.l(ad:0x400DA000+0x15C)&0x06)==0x00)) if (((per.l(ad:0x400DA000)&0x80)==0x80)) group.long 0x0C++0x03 line.long 0x00 "FLSHCR,Flash Configuration Register" bitfld.long 0x00 16.--17. " TDH ,Serial flash data in hold time" "Posedge of int. ref. clk.,2x serial flash half clk.,4x serial flash half clk.,?..." newline bitfld.long 0x00 8.--11. " TCSH ,Serial flash CS hold time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " TCSS ,Serial flash CS setup time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x0C++0x03 line.long 0x00 "FLSHCR,Flash Configuration Register" sif cpuis("MK8?FN256V*") bitfld.long 0x00 16.--17. " TDH ,Serial flash data in hold time" "Posedge of int. ref. clk.,?..." newline endif bitfld.long 0x00 8.--11. " TCSH ,Serial flash CS hold time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " TCSS ,Serial flash CS setup time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else if (((per.l(ad:0x400DA000)&0x80)==0x80)) rgroup.long 0x0C++0x03 line.long 0x00 "FLSHCR,Flash Configuration Register" bitfld.long 0x00 16.--17. " TDH ,Serial flash data in hold time" "Posedge of int. ref. clk.,2x serial flash half clk.,4x serial flash half clk.,?..." newline bitfld.long 0x00 8.--11. " TCSH ,Serial flash CS hold time in terms of serial flash clock cycles" "1,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " TCSS ,Serial flash CS setup time in terms of serial flash clock cycles" "0.5,0.5,2.5,3.5,4.5,5.5,6.5,7.5,8.5,9.5,10.5,11.5,12.5,13.5,14.5,15.5" else rgroup.long 0x0C++0x03 line.long 0x00 "FLSHCR,Flash Configuration Register" bitfld.long 0x00 8.--11. " TCSH ,Serial flash CS hold time in terms of serial flash clock cycles" "1,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " TCSS ,Serial flash CS setup time in terms of serial flash clock cycles" "0.5,0.5,2.5,3.5,4.5,5.5,6.5,7.5,8.5,9.5,10.5,11.5,12.5,13.5,14.5,15.5" endif endif endif if (((per.l(ad:0x400DA000+0x15C)&0x04)==0x00)) group.long 0x10++0x17 line.long 0x00 "BUF0CR,Buffer0 Configuration Register" bitfld.long 0x00 31. " HP_EN ,High Priority Enable" "Disabled,Enabled" hexmask.long.byte 0x00 8.--14. 1. " ADATSZ ,AHB data transfer size" bitfld.long 0x00 0.--3. " MSTRID ,The ID of the AHB master associated with BUFFER0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "BUF1CR,Buffer1 Configuration Register" hexmask.long.byte 0x04 8.--14. 1. " ADATSZ ,AHB data transfer size" bitfld.long 0x04 0.--3. " MSTRID ,The ID of the AHB master associated with BUFFER1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "BUF2CR,Buffer2 Configuration Register" hexmask.long.byte 0x08 8.--14. 1. " ADATSZ ,AHB data transfer size" bitfld.long 0x08 0.--3. " MSTRID ,The ID of the AHB master associated with BUFFER2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "BUF3CR,Buffer3 Configuration Register" bitfld.long 0x0C 31. " ALLMST ,All master enable" "Disabled,Enabled" hexmask.long.byte 0x0C 8.--14. 1. " ADATSZ ,AHB data transfer size" bitfld.long 0x0C 0.--3. " MSTRID ,The ID of the AHB master associated with BUFFER0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "BFGENCR,Buffer0 Configuration Register" bitfld.long 0x10 16. " PAR_EN ,Parallel mode for triggering a transaction to two serial flash devices" "Disabled,Enabled" bitfld.long 0x10 12.--15. " SEQID ,Sequence in the Look-up-table" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x14 "SOCCR,SOC Configuration Register" group.long 0x30++0x0B line.long 0x00 "BUF0IND,Buffer0 Top Index Register" hexmask.long 0x00 3.--31. 1. " TPINDX0 ,Top index of buffer 0" line.long 0x04 "BUF1IND,Buffer1 Top Index Register" hexmask.long 0x04 3.--31. 1. " TPINDX1 ,Top index of buffer 1" line.long 0x08 "BUF2IND,Buffer2 Top Index Register" hexmask.long 0x08 3.--31. 1. " TPINDX2 ,Top index of buffer 2" else rgroup.long 0x10++0x17 line.long 0x00 "BUF0CR,Buffer0 Configuration Register" bitfld.long 0x00 31. " HP_EN ,High Priority Enable" "Disabled,Enabled" hexmask.long.byte 0x00 8.--14. 1. " ADATSZ ,AHB data transfer size" bitfld.long 0x00 0.--3. " MSTRID ,The ID of the AHB master associated with BUFFER0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "BUF1CR,Buffer1 Configuration Register" hexmask.long.byte 0x04 8.--14. 1. " ADATSZ ,AHB data transfer size" bitfld.long 0x04 0.--3. " MSTRID ,The ID of the AHB master associated with BUFFER1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "BUF2CR,Buffer2 Configuration Register" hexmask.long.byte 0x08 8.--14. 1. " ADATSZ ,AHB data transfer size" bitfld.long 0x08 0.--3. " MSTRID ,The ID of the AHB master associated with BUFFER2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "BUF3CR,Buffer3 Configuration Register" bitfld.long 0x0C 31. " ALLMST ,All master enable" "Disabled,Enabled" hexmask.long.byte 0x0C 8.--14. 1. " ADATSZ ,AHB data transfer size" bitfld.long 0x0C 0.--3. " MSTRID ,The ID of the AHB master associated with BUFFER0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "BFGENCR,Buffer0 Configuration Register" bitfld.long 0x10 16. " PAR_EN ,Parallel mode for triggering a transaction to two serial flash devices" "Disabled,Enabled" bitfld.long 0x10 12.--15. " SEQID ,Sequence in the Look-up-table" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x14 "SOCCR,SOC Configuration Register" rgroup.long 0x30++0x0B line.long 0x00 "BUF0IND,Buffer0 Top Index Register" hexmask.long 0x00 3.--31. 1. " TPINDX0 ,Top index of buffer 0" line.long 0x04 "BUF1IND,Buffer1 Top Index Register" hexmask.long 0x04 3.--31. 1. " TPINDX1 ,Top index of buffer 1" line.long 0x08 "BUF2IND,Buffer2 Top Index Register" hexmask.long 0x08 3.--31. 1. " TPINDX2 ,Top index of buffer 2" endif if (((per.l(ad:0x400DA000+0x15C)&0x02)==0x00)) group.long 0x100++0x03 line.long 0x00 "SFAR,Serial Flash Address Register" else rgroup.long 0x100++0x03 line.long 0x00 "SFAR,Serial Flash Address Register" endif if (((per.l(ad:0x400DA000+0x15C)&0x06)==0x00)) group.long 0x104++0x03 line.long 0x00 "SFACR,Serial Flash Address Configuration Register" bitfld.long 0x00 16. " WA ,Serial flash is byte or word addressable flash" "Byte,Word" bitfld.long 0x00 0.--3. " CAS ,Column address space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.long 0x104++0x03 line.long 0x00 "SFACR,Serial Flash Address Configuration Register" bitfld.long 0x00 16. " WA ,Serial flash is byte or word addressable flash" "Byte,Word" bitfld.long 0x00 0.--3. " CAS ,Column address space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x400DA000)&0x4000)==0x4000)) group.long 0x108++0x03 line.long 0x00 "SMPR,Sampling Register" bitfld.long 0x00 16.--18. " DDRSMP ,DDR Sampling point" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6. " FSDLY ,Full speed delay selection for SDR instructions" "1 clock cycle,2 clock cycles" bitfld.long 0x00 5. " FSPHS ,Full speed phase selection for SDR instructions (edge of the sampling clock)" "Non-inverted,Inverted" bitfld.long 0x00 2. " HSDLY ,Half speed delay selection for SDR instructions" "1 clock cycle,2 clock cycles" newline bitfld.long 0x00 1. " HSPHS ,Half Speed Phase selection for SDR instructions (edge of the sampling clock)" "Non-inverted,Inverted" bitfld.long 0x00 0. " HSENA ,Half speed serial flash clock enable" "Disabled,Enabled" else rgroup.long 0x108++0x03 line.long 0x00 "SMPR,Sampling Register" bitfld.long 0x00 16.--18. " DDRSMP ,DDR Sampling point" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6. " FSDLY ,Full speed delay selection for SDR instructions" "1 clock cycle,2 clock cycles" bitfld.long 0x00 5. " FSPHS ,Full speed phase selection for SDR instructions (edge of the sampling clock)" "Non-inverted,Inverted" bitfld.long 0x00 2. " HSDLY ,Half speed delay selection for SDR instructions" "1 clock cycle,2 clock cycles" newline bitfld.long 0x00 1. " HSPHS ,Half speed Phase selection for SDR instructions (edge of the sampling clock)" "Non-inverted,Inverted" bitfld.long 0x00 0. " HSENA ,Half speed serial flash clock enable" "Disabled,Enabled" endif rgroup.long 0x10C++0x03 line.long 0x00 "RBSR,RX Buffer Status Register" hexmask.long.word 0x00 16.--31. 1. " RDCTR ,Indicates how many entries of 4 bytes have been removed from the RX Buffer" bitfld.long 0x00 8.--12. " RDBFL ,Indicates how many entries of 4 bytes are still available in the RX Buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x400DA000+0x15C)&0x02)==0x00)) group.long 0x110++0x03 line.long 0x00 "RBCT,RX Buffer Control Register" bitfld.long 0x00 8. " RXBRD ,Access scheme for the RX Buffer readout" "AHB Bus,IP Bus" bitfld.long 0x00 0.--3. " WMRK ,RX buffer watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.long 0x110++0x03 line.long 0x00 "RBCT,RX Buffer Control Register" bitfld.long 0x00 8. " RXBRD ,Access scheme for the RX buffer readout" "AHB Bus,IP Bus" bitfld.long 0x00 0.--3. " WMRK ,RX buffer watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif rgroup.long 0x150++0x03 line.long 0x00 "TBSR,TX Buffer Status Register" hexmask.long.word 0x00 16.--31. 1. " TRCTR ,Indicates how many entries of 4 bytes have been written into the TX Buffer by host accesses" bitfld.long 0x00 8.--12. " TRBFL ,Number of entries of 4 bytes each available in the TX buffer for the QuadSPI module to transmit to the serial flash device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x400DA000+0x15C)&0x8000000)==0x00)) group.long 0x154++0x03 line.long 0x00 "TBDR,TX Buffer Data Register" else rgroup.long 0x154++0x03 line.long 0x00 "TBDR,TX Buffer Data Register" endif group.long 0x158++0x03 line.long 0x00 "TBCT,TX Buffer Control Register" bitfld.long 0x00 0.--3. " WMRK ,TX buffer watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x15C++0x03 line.long 0x00 "SR,Status register" bitfld.long 0x00 29.--31. " DLPSMP ,Data learning pattern sampling point" "0,1,2,3,4,5,6,7" bitfld.long 0x00 27. " TXFULL ,TX buffer full" "Not full,Full" bitfld.long 0x00 26. " TXDMA ,TX buffer fill via DMA" "Not active,Active" bitfld.long 0x00 25. " TXWA ,TX buffer watermark available" "Not available,Available" newline bitfld.long 0x00 24. " TXEDA ,TX buffer enough data available" "Not available,Available" bitfld.long 0x00 23. " RXDMA ,RX buffer read out via DMA" "Not active,Active" bitfld.long 0x00 19. " RXFULL ,RX buffer full" "Not full,Full" bitfld.long 0x00 16. " RXWE ,RX buffer watermark exceeded" "Not exceeded,Exceeded" newline bitfld.long 0x00 14. " AHB3FUL ,AHB 3 buffer full" "Not full,Full" bitfld.long 0x00 13. " AHB2FUL ,AHB 2 buffer full" "Not full,Full" bitfld.long 0x00 12. " AHB1FUL ,AHB 1 buffer full" "Not full,Full" bitfld.long 0x00 11. " AHB0FUL ,AHB 0 buffer full" "Not full,Full" newline bitfld.long 0x00 10. " AHB3NE ,AHB 3 buffer not empty" "Empty,Not empty" bitfld.long 0x00 9. " AHB2NE ,AHB 2 buffer not empty" "Empty,Not empty" bitfld.long 0x00 8. " AHB1NE ,AHB 1 buffer not empty" "Empty,Not empty" bitfld.long 0x00 7. " AHB0NE ,AHB 0 buffer not empty" "Empty,Not empty" newline bitfld.long 0x00 6. " AHBTRN ,AHB access transaction pending" "Not pending,Pending" bitfld.long 0x00 5. " AHBGNT ,AHB command priority granted" "Not granted,Granted" bitfld.long 0x00 2. " AHB_ACC ,AHB access" "Not AHB initiated,AHB initiated" bitfld.long 0x00 1. " IP_ACC ,IP access" "Not IP bus initiated,IP bus initiated" newline bitfld.long 0x00 0. " BUSY ,Indicates whether module is currently busy handling a transaction to an external flash device" "Not busy,Busy" if (((per.l(ad:0x400DA000+0x00)&0x4000)==0x00)) group.long 0x160++0x03 line.long 0x00 "FR,Flag register" eventfld.long 0x00 31. " DLPFF ,Data learning pattern failure flag" "Not failed,Failed" eventfld.long 0x00 27. " TBFF ,TX buffer fulfilment flag" "Full,Not full" eventfld.long 0x00 26. " TBUF ,TX buffer underrun flag" "No underrun,Underrun" eventfld.long 0x00 23. " ILLINE ,Illegal instruction error flag" "No error,Error" newline eventfld.long 0x00 17. " RBOF ,RX buffer overflow flag" "No overflow,Overflow" eventfld.long 0x00 16. " RBDF ,RX buffer drain flag" "Not occurred,Occurred" eventfld.long 0x00 15. " ABSEF ,AHB sequence error flag" "No error,Error" eventfld.long 0x00 14. " AITEF ,AHB illegal transaction error flag" "No error,Error" newline eventfld.long 0x00 13. " AIBSEF ,AHB illegal burst size error flag" "No error,Error" eventfld.long 0x00 12. " ABOF ,AHB buffer overflow flag" "No overflow,Overflow" eventfld.long 0x00 11. " IUEF ,IP command usage error flag" "Not occurred,Occurred" eventfld.long 0x00 7. " IPAEF ,IP command trigger during AHB access error flag" "No error,Error" newline eventfld.long 0x00 6. " IPIEF ,IP command trigger could not be executed error flag" "No error,Error" eventfld.long 0x00 4. " IPGEF ,IP command trigger during AHB grant error flag" "No error,Error" eventfld.long 0x00 0. " TFF ,IP command transaction finished flag" "Not finished,Finished" else rgroup.long 0x160++0x03 line.long 0x00 "FR,Flag register" bitfld.long 0x00 31. " DLPFF ,Data learning pattern failure flag" "Not failed,Failed" bitfld.long 0x00 27. " TBFF ,TX buffer fulfilment flag" "Full,Not full" bitfld.long 0x00 26. " TBUF ,TX buffer underrun flag" "No underrun,Underrun" bitfld.long 0x00 23. " ILLINE ,Illegal instruction error flag" "No error,Error" newline bitfld.long 0x00 17. " RBOF ,RX buffer overflow flag" "No overflow,Overflow" bitfld.long 0x00 16. " RBDF ,RX buffer drain flag" "Not occurred,Occurred" bitfld.long 0x00 15. " ABSEF ,AHB sequence error flag" "No error,Error" bitfld.long 0x00 14. " AITEF ,AHB illegal transaction error flag" "No error,Error" newline bitfld.long 0x00 13. " AIBSEF ,AHB illegal burst size error flag" "No error,Error" bitfld.long 0x00 12. " ABOF ,AHB buffer overflow flag" "No overflow,Overflow" bitfld.long 0x00 11. " IUEF ,IP command usage error flag" "Not occurred,Occurred" bitfld.long 0x00 7. " IPAEF ,IP command trigger during AHB access error flag" "No error,Error" newline bitfld.long 0x00 6. " IPIEF ,IP command trigger could not be executed error flag" "No error,Error" bitfld.long 0x00 4. " IPGEF ,IP command trigger during AHB grant error flag" "No error,Error" bitfld.long 0x00 0. " TFF ,IP command transaction finished flag" "Not finished,Finished" endif group.long 0x164++0x03 line.long 0x00 "RSER,Interrupt and DMA Request Select and Enable Register" bitfld.long 0x00 31. " DLPFIE ,Data learning pattern failure interrupt enable" "Disabled,Enabled" bitfld.long 0x00 27. " TBFIE ,TX buffer fill interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " TBUIE ,TX buffer underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 25. " TBFDE ,TX buffer fill DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 23. " ILLINIE ,Illegal instruction error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " RBDDE ,RX buffer drain DMA enable" "Disabled,Enabled" bitfld.long 0x00 17. " RBOIE ,RX buffer overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 16. " RBDIE ,RX buffer drain interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 15. " ABSEIE ,AHB sequence error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " AITIE ,AHB illegal transaction interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " AIBSIE ,AHB illegal burst size interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " ABOIE ,AHB buffer overflow interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " IUEIE ,AIP command usage error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " IPAEIE ,IP command trigger during AHB access error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " IPIEIE ,IP command trigger during IP access error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " IPGEIE ,IP command trigger during AHB grant error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " TFIE ,Transaction finished interrupt enable" "Disabled,Enabled" if (((per.l(ad:0x400DA000+0x168)&0x01)==0x01)) rgroup.long 0x168++0x03 line.long 0x00 "SPNDST,Sequence Suspend Status Register" hexmask.long.byte 0x00 9.--14. 1. " DATLFT ,Data left" bitfld.long 0x00 6.--7. " SPDBUF ,Suspended buffer number" "0,1,2,3" newline bitfld.long 0x00 0. " SUSPND ,Sequence is in suspended state" "Disabled,Enabled" else rgroup.long 0x168++0x03 line.long 0x00 "SPNDST,Sequence Suspend Status Register" bitfld.long 0x00 0. " SUSPND ,Sequence is in suspended state" "Disabled,Enabled" endif sif cpuis("MK8?FN256V*")||cpuis("MK27FN2M0VMI15")||cpuis("MK28FN2M0VMI15")||cpuis("?K28FN2M0CAU15?") wgroup.long 0x16C++0x03 line.long 0x00 "SPTRCLR,Sequence Pointer Clear Register" bitfld.long 0x00 8. " IPPTRC ,IP pointer clear" "No effect,Clear" bitfld.long 0x00 0. " BFPTRC ,Buffer pointer clear" "No effect,Clear" else group.long 0x16C++0x03 line.long 0x00 "SPTRCLR,Sequence Pointer Clear Register" bitfld.long 0x00 8. " IPPTRC ,IP pointer Clear" "No effect,Clear" bitfld.long 0x00 0. " BFPTRC ,Buffer pointer clear" "No effect,Clear" endif if (((per.l(ad:0x400DA000+0x15C)&0x06)==0x00)) group.long 0x180++0x13 line.long 0x00 "SFA1AD,serial flash A1 Top Address" hexmask.long.tbyte 0x00 10.--31. 0x04 " TPADA1 ,Top address for serial flash A1" line.long 0x04 "SFA2AD,serial flash A2 Top Address" hexmask.long.tbyte 0x04 10.--31. 0x04 " TPADA2 ,Top address for serial flash A2" line.long 0x08 "SFB1AD,serial flash B1 Top Address" hexmask.long.tbyte 0x08 10.--31. 0x04 " TPADB1 ,Top address for serial flash B1" line.long 0x0C "SFB2AD,serial flash B2 Top Address" hexmask.long.tbyte 0x0C 10.--31. 0x04 " TPADB2 ,Top address for serial flash B2" line.long 0x10 "DLPR,Data Learn Pattern Register" else rgroup.long 0x180++0x13 line.long 0x00 "SFA1AD,serial flash A1 Top Address" hexmask.long.tbyte 0x00 10.--31. 0x04 " TPADA1 ,Top address for serial flash A1" line.long 0x04 "SFA2AD,serial flash A2 Top Address" hexmask.long.tbyte 0x04 10.--31. 0x04 " TPADA2 ,Top address for serial flash A2" line.long 0x08 "SFB1AD,serial flash B1 Top Address" hexmask.long.tbyte 0x08 10.--31. 0x04 " TPADB1 ,Top address for serial flash B1" line.long 0x0C "SFB2AD,serial flash B2 Top Address" hexmask.long.tbyte 0x0C 10.--31. 0x04 " TPADB2 ,Top address for serial flash B2" line.long 0x10 "DLPR,Data Learn Pattern Register" endif sif cpuis("MK8?FN256V*")||cpuis("MK27FN2M0VMI15")||cpuis("MK28FN2M0VMI15")||cpuis("KK28FN2M0CAU15R") rgroup.long 0x200++0x03 line.long 0x00 "RBDR0,RX Buffer Data Register 0" rgroup.long 0x204++0x03 line.long 0x00 "RBDR1,RX Buffer Data Register 1" rgroup.long 0x208++0x03 line.long 0x00 "RBDR2,RX Buffer Data Register 2" rgroup.long 0x20C++0x03 line.long 0x00 "RBDR3,RX Buffer Data Register 3" rgroup.long 0x210++0x03 line.long 0x00 "RBDR4,RX Buffer Data Register 4" rgroup.long 0x214++0x03 line.long 0x00 "RBDR5,RX Buffer Data Register 5" rgroup.long 0x218++0x03 line.long 0x00 "RBDR6,RX Buffer Data Register 6" rgroup.long 0x21C++0x03 line.long 0x00 "RBDR7,RX Buffer Data Register 7" rgroup.long 0x220++0x03 line.long 0x00 "RBDR8,RX Buffer Data Register 8" rgroup.long 0x224++0x03 line.long 0x00 "RBDR9,RX Buffer Data Register 9" rgroup.long 0x228++0x03 line.long 0x00 "RBDR10,RX Buffer Data Register 10" rgroup.long 0x22C++0x03 line.long 0x00 "RBDR11,RX Buffer Data Register 11" rgroup.long 0x230++0x03 line.long 0x00 "RBDR12,RX Buffer Data Register 12" rgroup.long 0x234++0x03 line.long 0x00 "RBDR13,RX Buffer Data Register 13" rgroup.long 0x238++0x03 line.long 0x00 "RBDR14,RX Buffer Data Register 14" rgroup.long 0x23C++0x03 line.long 0x00 "RBDR15,RX Buffer Data Register 15" else group.long 0x200++0x03 line.long 0x00 "RBDR0,RX Buffer Data Register 0" group.long 0x204++0x03 line.long 0x00 "RBDR1,RX Buffer Data Register 1" group.long 0x208++0x03 line.long 0x00 "RBDR2,RX Buffer Data Register 2" group.long 0x20C++0x03 line.long 0x00 "RBDR3,RX Buffer Data Register 3" group.long 0x210++0x03 line.long 0x00 "RBDR4,RX Buffer Data Register 4" group.long 0x214++0x03 line.long 0x00 "RBDR5,RX Buffer Data Register 5" group.long 0x218++0x03 line.long 0x00 "RBDR6,RX Buffer Data Register 6" group.long 0x21C++0x03 line.long 0x00 "RBDR7,RX Buffer Data Register 7" group.long 0x220++0x03 line.long 0x00 "RBDR8,RX Buffer Data Register 8" group.long 0x224++0x03 line.long 0x00 "RBDR9,RX Buffer Data Register 9" group.long 0x228++0x03 line.long 0x00 "RBDR10,RX Buffer Data Register 10" group.long 0x22C++0x03 line.long 0x00 "RBDR11,RX Buffer Data Register 11" group.long 0x230++0x03 line.long 0x00 "RBDR12,RX Buffer Data Register 12" group.long 0x234++0x03 line.long 0x00 "RBDR13,RX Buffer Data Register 13" group.long 0x238++0x03 line.long 0x00 "RBDR14,RX Buffer Data Register 14" group.long 0x23C++0x03 line.long 0x00 "RBDR15,RX Buffer Data Register 15" endif group.long 0x300++0x07 line.long 0x00 "LUTKEY,LUT Key Register" line.long 0x04 "LCKCR,LUT Lock Configuration Register" bitfld.long 0x04 1. " UNLOCK ,LUT unlock" "Locked,Unlocked" bitfld.long 0x04 0. " LOCK ,LUT lock" "Unlocked,Locked" tree "Look-up Tables" group.long 0x310++0x03 line.long 0x00 "LUT0,Look-up Table register 0" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x314++0x03 line.long 0x00 "LUT1,Look-up Table register 1" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x318++0x03 line.long 0x00 "LUT2,Look-up Table register 2" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x31C++0x03 line.long 0x00 "LUT3,Look-up Table register 3" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x320++0x03 line.long 0x00 "LUT4,Look-up Table register 4" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x324++0x03 line.long 0x00 "LUT5,Look-up Table register 5" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x328++0x03 line.long 0x00 "LUT6,Look-up Table register 6" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x32C++0x03 line.long 0x00 "LUT7,Look-up Table register 7" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x330++0x03 line.long 0x00 "LUT8,Look-up Table register 8" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x334++0x03 line.long 0x00 "LUT9,Look-up Table register 9" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x338++0x03 line.long 0x00 "LUT10,Look-up Table register 10" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x33C++0x03 line.long 0x00 "LUT11,Look-up Table register 11" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x340++0x03 line.long 0x00 "LUT12,Look-up Table register 12" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x344++0x03 line.long 0x00 "LUT13,Look-up Table register 13" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x348++0x03 line.long 0x00 "LUT14,Look-up Table register 14" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x34C++0x03 line.long 0x00 "LUT15,Look-up Table register 15" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x350++0x03 line.long 0x00 "LUT16,Look-up Table register 16" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x354++0x03 line.long 0x00 "LUT17,Look-up Table register 17" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x358++0x03 line.long 0x00 "LUT18,Look-up Table register 18" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x35C++0x03 line.long 0x00 "LUT19,Look-up Table register 19" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x360++0x03 line.long 0x00 "LUT20,Look-up Table register 20" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x364++0x03 line.long 0x00 "LUT21,Look-up Table register 21" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x368++0x03 line.long 0x00 "LUT22,Look-up Table register 22" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x36C++0x03 line.long 0x00 "LUT23,Look-up Table register 23" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x370++0x03 line.long 0x00 "LUT24,Look-up Table register 24" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x374++0x03 line.long 0x00 "LUT25,Look-up Table register 25" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x378++0x03 line.long 0x00 "LUT26,Look-up Table register 26" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x37C++0x03 line.long 0x00 "LUT27,Look-up Table register 27" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x380++0x03 line.long 0x00 "LUT28,Look-up Table register 28" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x384++0x03 line.long 0x00 "LUT29,Look-up Table register 29" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x388++0x03 line.long 0x00 "LUT30,Look-up Table register 30" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x38C++0x03 line.long 0x00 "LUT31,Look-up Table register 31" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x390++0x03 line.long 0x00 "LUT32,Look-up Table register 32" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x394++0x03 line.long 0x00 "LUT33,Look-up Table register 33" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x398++0x03 line.long 0x00 "LUT34,Look-up Table register 34" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x39C++0x03 line.long 0x00 "LUT35,Look-up Table register 35" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3A0++0x03 line.long 0x00 "LUT36,Look-up Table register 36" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3A4++0x03 line.long 0x00 "LUT37,Look-up Table register 37" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3A8++0x03 line.long 0x00 "LUT38,Look-up Table register 38" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3AC++0x03 line.long 0x00 "LUT39,Look-up Table register 39" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3B0++0x03 line.long 0x00 "LUT40,Look-up Table register 40" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3B4++0x03 line.long 0x00 "LUT41,Look-up Table register 41" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3B8++0x03 line.long 0x00 "LUT42,Look-up Table register 42" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3BC++0x03 line.long 0x00 "LUT43,Look-up Table register 43" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3C0++0x03 line.long 0x00 "LUT44,Look-up Table register 44" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3C4++0x03 line.long 0x00 "LUT45,Look-up Table register 45" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3C8++0x03 line.long 0x00 "LUT46,Look-up Table register 46" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3CC++0x03 line.long 0x00 "LUT47,Look-up Table register 47" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3D0++0x03 line.long 0x00 "LUT48,Look-up Table register 48" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3D4++0x03 line.long 0x00 "LUT49,Look-up Table register 49" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3D8++0x03 line.long 0x00 "LUT50,Look-up Table register 50" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3DC++0x03 line.long 0x00 "LUT51,Look-up Table register 51" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3E0++0x03 line.long 0x00 "LUT52,Look-up Table register 52" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3E4++0x03 line.long 0x00 "LUT53,Look-up Table register 53" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3E8++0x03 line.long 0x00 "LUT54,Look-up Table register 54" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3EC++0x03 line.long 0x00 "LUT55,Look-up Table register 55" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3F0++0x03 line.long 0x00 "LUT56,Look-up Table register 56" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3F4++0x03 line.long 0x00 "LUT57,Look-up Table register 57" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3F8++0x03 line.long 0x00 "LUT58,Look-up Table register 58" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x3FC++0x03 line.long 0x00 "LUT59,Look-up Table register 59" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x400++0x03 line.long 0x00 "LUT60,Look-up Table register 60" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x404++0x03 line.long 0x00 "LUT61,Look-up Table register 61" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x408++0x03 line.long 0x00 "LUT62,Look-up Table register 62" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" group.long 0x40C++0x03 line.long 0x00 "LUT63,Look-up Table register 63" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 Pad,2 Pads,4 Pads,8 Pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" tree.end width 0x0B tree "QuadSPI AHB RX Buffer" base ad:0x67000000 width 8. group.long 0x0++0x03 line.long 0x00 "ARDB0,AHB RX Data Buffer Register 0" group.long 0x4++0x03 line.long 0x00 "ARDB1,AHB RX Data Buffer Register 1" group.long 0x8++0x03 line.long 0x00 "ARDB2,AHB RX Data Buffer Register 2" group.long 0xC++0x03 line.long 0x00 "ARDB3,AHB RX Data Buffer Register 3" group.long 0x10++0x03 line.long 0x00 "ARDB4,AHB RX Data Buffer Register 4" group.long 0x14++0x03 line.long 0x00 "ARDB5,AHB RX Data Buffer Register 5" group.long 0x18++0x03 line.long 0x00 "ARDB6,AHB RX Data Buffer Register 6" group.long 0x1C++0x03 line.long 0x00 "ARDB7,AHB RX Data Buffer Register 7" group.long 0x20++0x03 line.long 0x00 "ARDB8,AHB RX Data Buffer Register 8" group.long 0x24++0x03 line.long 0x00 "ARDB9,AHB RX Data Buffer Register 9" group.long 0x28++0x03 line.long 0x00 "ARDB10,AHB RX Data Buffer Register 10" group.long 0x2C++0x03 line.long 0x00 "ARDB11,AHB RX Data Buffer Register 11" group.long 0x30++0x03 line.long 0x00 "ARDB12,AHB RX Data Buffer Register 12" group.long 0x34++0x03 line.long 0x00 "ARDB13,AHB RX Data Buffer Register 13" group.long 0x38++0x03 line.long 0x00 "ARDB14,AHB RX Data Buffer Register 14" group.long 0x3C++0x03 line.long 0x00 "ARDB15,AHB RX Data Buffer Register 15" width 0x0B tree.end tree.end sif cpuis("MK82FN256VDC15")||cpuis("MK82FN256VLL15") tree "OTFAD (On-the-Fly AES Decryption Module)" base ad:0x400DAC00 width 13. group.long 0xC00++0x03 line.long 0x00 "CR,Control Register" bitfld.long 0x00 31. " GE ,Global OTFAD Enable" "Disabled,Enabled" bitfld.long 0x00 21. " CRCI ,CRC Initialization" "Not initialized,Initialized" bitfld.long 0x00 20. " CRCE ,CRC Enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " CCTX ,CRC Context" "CTX0,CTX1,CTX2,CTX3" newline bitfld.long 0x00 7. " RRAE ,Restricted Register Access Enable" "Disabled,Enabled" bitfld.long 0x00 3. " FLDM ,Force Logically Disabled Mode" "Not forced,Forced" bitfld.long 0x00 2. " FSVM ,Force Security Violation Mode" "Not forced,Forced" rgroup.long 0xC04++0x03 line.long 0x00 "SR,Status Register" bitfld.long 0x00 29. " GEM ,Global Enable Mode" "Disabled,Enabled" bitfld.long 0x00 28. " RRAM ,Restricted Register Access Mode" "Normal,RAZ/WI" bitfld.long 0x00 2.--3. " MODE ,Operating Mode" "NRM,,SVM,LDM" group.long 0xC08++0x03 line.long 0x00 "CRC,Cyclic Redundancy Check Register" if (((per.l(ad:0x400DAC00+0xC00))&0x80)==0x08) hgroup.long (0xD00+0x0)++0x1F hide.long 0x00 "CTX0_KEY_W0,AES Key Word0" hide.long 0x04 "CTX0_KEY_W1,AES Key Word1" hide.long 0x08 "CTX0_KEY_W2,AES Key Word2" hide.long 0x0C "CTX0_KEY_W3,AES Key Word3" hide.long 0x10 "CTX0_CTR_W0,AES Counter Word0" hide.long 0x14 "CTX0_CTR_W1,AES Counter Word1" hide.long 0x18 "CTX0_RGD_W0,AES Region Descriptor Word0" hide.long 0x1C "CTX0_RGD_W1,AES Region Descriptor Word1" hgroup.long (0xD00+0x40)++0x1F hide.long 0x00 "CTX1_KEY_W0,AES Key Word0" hide.long 0x04 "CTX1_KEY_W1,AES Key Word1" hide.long 0x08 "CTX1_KEY_W2,AES Key Word2" hide.long 0x0C "CTX1_KEY_W3,AES Key Word3" hide.long 0x10 "CTX1_CTR_W0,AES Counter Word0" hide.long 0x14 "CTX1_CTR_W1,AES Counter Word1" hide.long 0x18 "CTX1_RGD_W0,AES Region Descriptor Word0" hide.long 0x1C "CTX1_RGD_W1,AES Region Descriptor Word1" hgroup.long (0xD00+0x80)++0x1F hide.long 0x00 "CTX2_KEY_W0,AES Key Word0" hide.long 0x04 "CTX2_KEY_W1,AES Key Word1" hide.long 0x08 "CTX2_KEY_W2,AES Key Word2" hide.long 0x0C "CTX2_KEY_W3,AES Key Word3" hide.long 0x10 "CTX2_CTR_W0,AES Counter Word0" hide.long 0x14 "CTX2_CTR_W1,AES Counter Word1" hide.long 0x18 "CTX2_RGD_W0,AES Region Descriptor Word0" hide.long 0x1C "CTX2_RGD_W1,AES Region Descriptor Word1" hgroup.long (0xD00+0xC0)++0x1F hide.long 0x00 "CTX3_KEY_W0,AES Key Word0" hide.long 0x04 "CTX3_KEY_W1,AES Key Word1" hide.long 0x08 "CTX3_KEY_W2,AES Key Word2" hide.long 0x0C "CTX3_KEY_W3,AES Key Word3" hide.long 0x10 "CTX3_CTR_W0,AES Counter Word0" hide.long 0x14 "CTX3_CTR_W1,AES Counter Word1" hide.long 0x18 "CTX3_RGD_W0,AES Region Descriptor Word0" hide.long 0x1C "CTX3_RGD_W1,AES Region Descriptor Word1" else if (((per.l(ad:0x400DAC00+0xD1C+0x0))&0x04)==0x04) rgroup.long (0xD00+0x0)++0x1F line.long 0x00 "CTX0_KEY_W0,AES Key Word0" line.long 0x04 "CTX0_KEY_W1,AES Key Word1" line.long 0x08 "CTX0_KEY_W2,AES Key Word2" line.long 0x0C "CTX0_KEY_W3,AES Key Word3" line.long 0x10 "CTX0_CTR_W0,AES Counter Word0" line.long 0x14 "CTX0_CTR_W1,AES Counter Word1" line.long 0x18 "CTX0_RGD_W0,AES Region Descriptor Word0" hexmask.long.tbyte 0x18 10.--31. 1. " SRTADDR ,Start Address" line.long 0x1C "CTX0_RGD_W1,AES Region Descriptor Word1" hexmask.long.word 0x1C 16.--31. 1. " ENDADDR ,End Address" bitfld.long 0x1C 2. " RO ,Read-Only" "Normal,RO" bitfld.long 0x1C 1. " ADE ,Aes Decryption Enable" "Disabled,Enabled" bitfld.long 0x1C 0. " VLD ,Valid" "invalid,Valid" else group.long (0xD00+0x0)++0x1F line.long 0x00 "CTX0_KEY_W0,AES Key Word0" line.long 0x04 "CTX0_KEY_W1,AES Key Word1" line.long 0x08 "CTX0_KEY_W2,AES Key Word2" line.long 0x0C "CTX0_KEY_W3,AES Key Word3" line.long 0x10 "CTX0_CTR_W0,AES Counter Word0" line.long 0x14 "CTX0_CTR_W1,AES Counter Word1" line.long 0x18 "CTX0_RGD_W0,AES Region Descriptor Word0" hexmask.long.tbyte 0x18 10.--31. 1. " SRTADDR ,Start Address" line.long 0x1C "CTX0_RGD_W1,AES Region Descriptor Word1" hexmask.long.word 0x1C 16.--31. 1. " ENDADDR ,End Address" bitfld.long 0x1C 2. " RO ,Read-Only" "Normal,RO" bitfld.long 0x1C 1. " ADE ,Aes Decryption Enable" "Disabled,Enabled" bitfld.long 0x1C 0. " VLD ,Valid" "invalid,Valid" endif if (((per.l(ad:0x400DAC00+0xD1C+0x40))&0x04)==0x04) rgroup.long (0xD00+0x40)++0x1F line.long 0x00 "CTX1_KEY_W0,AES Key Word0" line.long 0x04 "CTX1_KEY_W1,AES Key Word1" line.long 0x08 "CTX1_KEY_W2,AES Key Word2" line.long 0x0C "CTX1_KEY_W3,AES Key Word3" line.long 0x10 "CTX1_CTR_W0,AES Counter Word0" line.long 0x14 "CTX1_CTR_W1,AES Counter Word1" line.long 0x18 "CTX1_RGD_W0,AES Region Descriptor Word0" hexmask.long.tbyte 0x18 10.--31. 1. " SRTADDR ,Start Address" line.long 0x1C "CTX1_RGD_W1,AES Region Descriptor Word1" hexmask.long.word 0x1C 16.--31. 1. " ENDADDR ,End Address" bitfld.long 0x1C 2. " RO ,Read-Only" "Normal,RO" bitfld.long 0x1C 1. " ADE ,Aes Decryption Enable" "Disabled,Enabled" bitfld.long 0x1C 0. " VLD ,Valid" "invalid,Valid" else group.long (0xD00+0x40)++0x1F line.long 0x00 "CTX1_KEY_W0,AES Key Word0" line.long 0x04 "CTX1_KEY_W1,AES Key Word1" line.long 0x08 "CTX1_KEY_W2,AES Key Word2" line.long 0x0C "CTX1_KEY_W3,AES Key Word3" line.long 0x10 "CTX1_CTR_W0,AES Counter Word0" line.long 0x14 "CTX1_CTR_W1,AES Counter Word1" line.long 0x18 "CTX1_RGD_W0,AES Region Descriptor Word0" hexmask.long.tbyte 0x18 10.--31. 1. " SRTADDR ,Start Address" line.long 0x1C "CTX1_RGD_W1,AES Region Descriptor Word1" hexmask.long.word 0x1C 16.--31. 1. " ENDADDR ,End Address" bitfld.long 0x1C 2. " RO ,Read-Only" "Normal,RO" bitfld.long 0x1C 1. " ADE ,Aes Decryption Enable" "Disabled,Enabled" bitfld.long 0x1C 0. " VLD ,Valid" "invalid,Valid" endif if (((per.l(ad:0x400DAC00+0xD1C+0x80))&0x04)==0x04) rgroup.long (0xD00+0x80)++0x1F line.long 0x00 "CTX2_KEY_W0,AES Key Word0" line.long 0x04 "CTX2_KEY_W1,AES Key Word1" line.long 0x08 "CTX2_KEY_W2,AES Key Word2" line.long 0x0C "CTX2_KEY_W3,AES Key Word3" line.long 0x10 "CTX2_CTR_W0,AES Counter Word0" line.long 0x14 "CTX2_CTR_W1,AES Counter Word1" line.long 0x18 "CTX2_RGD_W0,AES Region Descriptor Word0" hexmask.long.tbyte 0x18 10.--31. 1. " SRTADDR ,Start Address" line.long 0x1C "CTX2_RGD_W1,AES Region Descriptor Word1" hexmask.long.word 0x1C 16.--31. 1. " ENDADDR ,End Address" bitfld.long 0x1C 2. " RO ,Read-Only" "Normal,RO" bitfld.long 0x1C 1. " ADE ,Aes Decryption Enable" "Disabled,Enabled" bitfld.long 0x1C 0. " VLD ,Valid" "invalid,Valid" else group.long (0xD00+0x80)++0x1F line.long 0x00 "CTX2_KEY_W0,AES Key Word0" line.long 0x04 "CTX2_KEY_W1,AES Key Word1" line.long 0x08 "CTX2_KEY_W2,AES Key Word2" line.long 0x0C "CTX2_KEY_W3,AES Key Word3" line.long 0x10 "CTX2_CTR_W0,AES Counter Word0" line.long 0x14 "CTX2_CTR_W1,AES Counter Word1" line.long 0x18 "CTX2_RGD_W0,AES Region Descriptor Word0" hexmask.long.tbyte 0x18 10.--31. 1. " SRTADDR ,Start Address" line.long 0x1C "CTX2_RGD_W1,AES Region Descriptor Word1" hexmask.long.word 0x1C 16.--31. 1. " ENDADDR ,End Address" bitfld.long 0x1C 2. " RO ,Read-Only" "Normal,RO" bitfld.long 0x1C 1. " ADE ,Aes Decryption Enable" "Disabled,Enabled" bitfld.long 0x1C 0. " VLD ,Valid" "invalid,Valid" endif if (((per.l(ad:0x400DAC00+0xD1C+0xC0))&0x04)==0x04) rgroup.long (0xD00+0xC0)++0x1F line.long 0x00 "CTX3_KEY_W0,AES Key Word0" line.long 0x04 "CTX3_KEY_W1,AES Key Word1" line.long 0x08 "CTX3_KEY_W2,AES Key Word2" line.long 0x0C "CTX3_KEY_W3,AES Key Word3" line.long 0x10 "CTX3_CTR_W0,AES Counter Word0" line.long 0x14 "CTX3_CTR_W1,AES Counter Word1" line.long 0x18 "CTX3_RGD_W0,AES Region Descriptor Word0" hexmask.long.tbyte 0x18 10.--31. 1. " SRTADDR ,Start Address" line.long 0x1C "CTX3_RGD_W1,AES Region Descriptor Word1" hexmask.long.word 0x1C 16.--31. 1. " ENDADDR ,End Address" bitfld.long 0x1C 2. " RO ,Read-Only" "Normal,RO" bitfld.long 0x1C 1. " ADE ,Aes Decryption Enable" "Disabled,Enabled" bitfld.long 0x1C 0. " VLD ,Valid" "invalid,Valid" else group.long (0xD00+0xC0)++0x1F line.long 0x00 "CTX3_KEY_W0,AES Key Word0" line.long 0x04 "CTX3_KEY_W1,AES Key Word1" line.long 0x08 "CTX3_KEY_W2,AES Key Word2" line.long 0x0C "CTX3_KEY_W3,AES Key Word3" line.long 0x10 "CTX3_CTR_W0,AES Counter Word0" line.long 0x14 "CTX3_CTR_W1,AES Counter Word1" line.long 0x18 "CTX3_RGD_W0,AES Region Descriptor Word0" hexmask.long.tbyte 0x18 10.--31. 1. " SRTADDR ,Start Address" line.long 0x1C "CTX3_RGD_W1,AES Region Descriptor Word1" hexmask.long.word 0x1C 16.--31. 1. " ENDADDR ,End Address" bitfld.long 0x1C 2. " RO ,Read-Only" "Normal,RO" bitfld.long 0x1C 1. " ADE ,Aes Decryption Enable" "Disabled,Enabled" bitfld.long 0x1C 0. " VLD ,Valid" "invalid,Valid" endif endif width 0x0B tree.end endif tree "FlexBus (External Bus Interface)" base ad:0x4000C000 width 8. tree "Chip Select 0" group.long 0x0++0x07 line.long 0x00 "CSAR0,Chip Select Address Register" hexmask.long.word 0x00 16.--31. 0x01 " BA ,Base address" line.long 0x04 "CSMR0,Chip Select Mask Register" bitfld.long 0x04 31. " BAM_[15] ,Base address bit 15 mask" "Not masked,Masked" bitfld.long 0x04 30. " [14] ,Base address bit 14 mask" "Not masked,Masked" bitfld.long 0x04 29. " [13] ,Base address bit 13 mask" "Not masked,Masked" bitfld.long 0x04 28. " [12] ,Base address bit 12 mask" "Not masked,Masked" newline bitfld.long 0x04 27. " [11] ,Base address bit 11 mask" "Not masked,Masked" bitfld.long 0x04 26. " [10] ,Base address bit 10 mask" "Not masked,Masked" bitfld.long 0x04 25. " [9] ,Base address bit 9 mask" "Not masked,Masked" bitfld.long 0x04 24. " [8] ,Base address bit 8 mask" "Not masked,Masked" newline bitfld.long 0x04 23. " [7] ,Base address bit 7 mask" "Not masked,Masked" bitfld.long 0x04 22. " [6] ,Base address bit 6 mask" "Not masked,Masked" bitfld.long 0x04 21. " [5] ,Base address bit 5 mask" "Not masked,Masked" bitfld.long 0x04 20. " [4] ,Base address bit 4 mask" "Not masked,Masked" newline bitfld.long 0x04 19. " [3] ,Base address bit 3 mask" "Not masked,Masked" bitfld.long 0x04 18. " [2] ,Base address bit 2 mask" "Not masked,Masked" bitfld.long 0x04 17. " [1] ,Base address bit 1 mask" "Not masked,Masked" bitfld.long 0x04 16. " [0] ,Base address bit 0 mask" "Not masked,Masked" newline bitfld.long 0x04 8. " WP ,Write protect" "Allowed,Not allowed" bitfld.long 0x04 0. " V ,Valid bit" "Invalid,Valid" if ((per.l(ad:0x4000C000+0x0+0x08)&0x800000)==0x800000) if ((per.l(ad:0x4000C000+0x0+0x08)&0x100)==0x00) group.long (0x0+0x08)++0x03 line.long 0x00 "CSCR0,Chip Select Control Register" bitfld.long 0x00 26.--31. " SWS ,Secondary wait state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" newline sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK70FN1M0VMJ12")||cpuis("MK70FN1M0VMJ15")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN1M0AVMD12")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "0 cycles,1 cycle,2 cycles,3 cycles" newline else bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" newline endif bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" newline bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Write only,Read/write" bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" else group.long (0x0+0x08)++0x03 line.long 0x00 "CSCR0,Chip Select Control Register" bitfld.long 0x00 26.--31. " SWS ,Secondary wait state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" newline sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK70FN1M0VMJ12")||cpuis("MK70FN1M0VMJ15")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN1M0AVMD12")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" newline else bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "0 cycles,1 cycle,2 cycles,3 cycles" newline endif bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" newline bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Write only,Read/write" bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" endif else if ((per.l(ad:0x4000C000+0x0+0x08)&0x100)==0x00) group.long (0x0+0x08)++0x03 line.long 0x00 "CSCR0,Chip Select Control Register" newline bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" newline sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK70FN1M0VMJ12")||cpuis("MK70FN1M0VMJ15")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN1M0AVMD12")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "0 cycles,1 cycle,2 cycles,3 cycles" newline else bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" newline endif bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" newline bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Write only,Read/write" bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" else group.long (0x0+0x08)++0x03 line.long 0x00 "CSCR0,Chip Select Control Register" newline bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" newline sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK70FN1M0VMJ12")||cpuis("MK70FN1M0VMJ15")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN1M0AVMD12")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" newline else bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "0 cycles,1 cycle,2 cycles,3 cycles" newline endif bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" newline bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Write only,Read/write" bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" endif endif tree.end tree "Chip Select 1" group.long 0xC++0x07 line.long 0x00 "CSAR1,Chip Select Address Register" hexmask.long.word 0x00 16.--31. 0x01 " BA ,Base address" line.long 0x04 "CSMR1,Chip Select Mask Register" bitfld.long 0x04 31. " BAM_[15] ,Base address bit 15 mask" "Not masked,Masked" bitfld.long 0x04 30. " [14] ,Base address bit 14 mask" "Not masked,Masked" bitfld.long 0x04 29. " [13] ,Base address bit 13 mask" "Not masked,Masked" bitfld.long 0x04 28. " [12] ,Base address bit 12 mask" "Not masked,Masked" newline bitfld.long 0x04 27. " [11] ,Base address bit 11 mask" "Not masked,Masked" bitfld.long 0x04 26. " [10] ,Base address bit 10 mask" "Not masked,Masked" bitfld.long 0x04 25. " [9] ,Base address bit 9 mask" "Not masked,Masked" bitfld.long 0x04 24. " [8] ,Base address bit 8 mask" "Not masked,Masked" newline bitfld.long 0x04 23. " [7] ,Base address bit 7 mask" "Not masked,Masked" bitfld.long 0x04 22. " [6] ,Base address bit 6 mask" "Not masked,Masked" bitfld.long 0x04 21. " [5] ,Base address bit 5 mask" "Not masked,Masked" bitfld.long 0x04 20. " [4] ,Base address bit 4 mask" "Not masked,Masked" newline bitfld.long 0x04 19. " [3] ,Base address bit 3 mask" "Not masked,Masked" bitfld.long 0x04 18. " [2] ,Base address bit 2 mask" "Not masked,Masked" bitfld.long 0x04 17. " [1] ,Base address bit 1 mask" "Not masked,Masked" bitfld.long 0x04 16. " [0] ,Base address bit 0 mask" "Not masked,Masked" newline bitfld.long 0x04 8. " WP ,Write protect" "Allowed,Not allowed" bitfld.long 0x04 0. " V ,Valid bit" "Invalid,Valid" if ((per.l(ad:0x4000C000+0xC+0x08)&0x800000)==0x800000) if ((per.l(ad:0x4000C000+0xC+0x08)&0x100)==0x00) group.long (0xC+0x08)++0x03 line.long 0x00 "CSCR1,Chip Select Control Register" bitfld.long 0x00 26.--31. " SWS ,Secondary wait state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" newline sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK70FN1M0VMJ12")||cpuis("MK70FN1M0VMJ15")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN1M0AVMD12")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "0 cycles,1 cycle,2 cycles,3 cycles" newline else bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" newline endif bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" newline bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Write only,Read/write" bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" else group.long (0xC+0x08)++0x03 line.long 0x00 "CSCR1,Chip Select Control Register" bitfld.long 0x00 26.--31. " SWS ,Secondary wait state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" newline sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK70FN1M0VMJ12")||cpuis("MK70FN1M0VMJ15")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN1M0AVMD12")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" newline else bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "0 cycles,1 cycle,2 cycles,3 cycles" newline endif bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" newline bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Write only,Read/write" bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" endif else if ((per.l(ad:0x4000C000+0xC+0x08)&0x100)==0x00) group.long (0xC+0x08)++0x03 line.long 0x00 "CSCR1,Chip Select Control Register" newline bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" newline sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK70FN1M0VMJ12")||cpuis("MK70FN1M0VMJ15")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN1M0AVMD12")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "0 cycles,1 cycle,2 cycles,3 cycles" newline else bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" newline endif bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" newline bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Write only,Read/write" bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" else group.long (0xC+0x08)++0x03 line.long 0x00 "CSCR1,Chip Select Control Register" newline bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" newline sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK70FN1M0VMJ12")||cpuis("MK70FN1M0VMJ15")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN1M0AVMD12")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" newline else bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "0 cycles,1 cycle,2 cycles,3 cycles" newline endif bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" newline bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Write only,Read/write" bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" endif endif tree.end tree "Chip Select 2" group.long 0x18++0x07 line.long 0x00 "CSAR2,Chip Select Address Register" hexmask.long.word 0x00 16.--31. 0x01 " BA ,Base address" line.long 0x04 "CSMR2,Chip Select Mask Register" bitfld.long 0x04 31. " BAM_[15] ,Base address bit 15 mask" "Not masked,Masked" bitfld.long 0x04 30. " [14] ,Base address bit 14 mask" "Not masked,Masked" bitfld.long 0x04 29. " [13] ,Base address bit 13 mask" "Not masked,Masked" bitfld.long 0x04 28. " [12] ,Base address bit 12 mask" "Not masked,Masked" newline bitfld.long 0x04 27. " [11] ,Base address bit 11 mask" "Not masked,Masked" bitfld.long 0x04 26. " [10] ,Base address bit 10 mask" "Not masked,Masked" bitfld.long 0x04 25. " [9] ,Base address bit 9 mask" "Not masked,Masked" bitfld.long 0x04 24. " [8] ,Base address bit 8 mask" "Not masked,Masked" newline bitfld.long 0x04 23. " [7] ,Base address bit 7 mask" "Not masked,Masked" bitfld.long 0x04 22. " [6] ,Base address bit 6 mask" "Not masked,Masked" bitfld.long 0x04 21. " [5] ,Base address bit 5 mask" "Not masked,Masked" bitfld.long 0x04 20. " [4] ,Base address bit 4 mask" "Not masked,Masked" newline bitfld.long 0x04 19. " [3] ,Base address bit 3 mask" "Not masked,Masked" bitfld.long 0x04 18. " [2] ,Base address bit 2 mask" "Not masked,Masked" bitfld.long 0x04 17. " [1] ,Base address bit 1 mask" "Not masked,Masked" bitfld.long 0x04 16. " [0] ,Base address bit 0 mask" "Not masked,Masked" newline bitfld.long 0x04 8. " WP ,Write protect" "Allowed,Not allowed" bitfld.long 0x04 0. " V ,Valid bit" "Invalid,Valid" if ((per.l(ad:0x4000C000+0x18+0x08)&0x800000)==0x800000) if ((per.l(ad:0x4000C000+0x18+0x08)&0x100)==0x00) group.long (0x18+0x08)++0x03 line.long 0x00 "CSCR2,Chip Select Control Register" bitfld.long 0x00 26.--31. " SWS ,Secondary wait state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" newline sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK70FN1M0VMJ12")||cpuis("MK70FN1M0VMJ15")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN1M0AVMD12")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "0 cycles,1 cycle,2 cycles,3 cycles" newline else bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" newline endif bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" newline bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Write only,Read/write" bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" else group.long (0x18+0x08)++0x03 line.long 0x00 "CSCR2,Chip Select Control Register" bitfld.long 0x00 26.--31. " SWS ,Secondary wait state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" newline sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK70FN1M0VMJ12")||cpuis("MK70FN1M0VMJ15")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN1M0AVMD12")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" newline else bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "0 cycles,1 cycle,2 cycles,3 cycles" newline endif bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" newline bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Write only,Read/write" bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" endif else if ((per.l(ad:0x4000C000+0x18+0x08)&0x100)==0x00) group.long (0x18+0x08)++0x03 line.long 0x00 "CSCR2,Chip Select Control Register" newline bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" newline sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK70FN1M0VMJ12")||cpuis("MK70FN1M0VMJ15")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN1M0AVMD12")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "0 cycles,1 cycle,2 cycles,3 cycles" newline else bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" newline endif bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" newline bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Write only,Read/write" bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" else group.long (0x18+0x08)++0x03 line.long 0x00 "CSCR2,Chip Select Control Register" newline bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" newline sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK70FN1M0VMJ12")||cpuis("MK70FN1M0VMJ15")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN1M0AVMD12")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" newline else bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "0 cycles,1 cycle,2 cycles,3 cycles" newline endif bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" newline bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Write only,Read/write" bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" endif endif tree.end tree "Chip Select 3" group.long 0x24++0x07 line.long 0x00 "CSAR3,Chip Select Address Register" hexmask.long.word 0x00 16.--31. 0x01 " BA ,Base address" line.long 0x04 "CSMR3,Chip Select Mask Register" bitfld.long 0x04 31. " BAM_[15] ,Base address bit 15 mask" "Not masked,Masked" bitfld.long 0x04 30. " [14] ,Base address bit 14 mask" "Not masked,Masked" bitfld.long 0x04 29. " [13] ,Base address bit 13 mask" "Not masked,Masked" bitfld.long 0x04 28. " [12] ,Base address bit 12 mask" "Not masked,Masked" newline bitfld.long 0x04 27. " [11] ,Base address bit 11 mask" "Not masked,Masked" bitfld.long 0x04 26. " [10] ,Base address bit 10 mask" "Not masked,Masked" bitfld.long 0x04 25. " [9] ,Base address bit 9 mask" "Not masked,Masked" bitfld.long 0x04 24. " [8] ,Base address bit 8 mask" "Not masked,Masked" newline bitfld.long 0x04 23. " [7] ,Base address bit 7 mask" "Not masked,Masked" bitfld.long 0x04 22. " [6] ,Base address bit 6 mask" "Not masked,Masked" bitfld.long 0x04 21. " [5] ,Base address bit 5 mask" "Not masked,Masked" bitfld.long 0x04 20. " [4] ,Base address bit 4 mask" "Not masked,Masked" newline bitfld.long 0x04 19. " [3] ,Base address bit 3 mask" "Not masked,Masked" bitfld.long 0x04 18. " [2] ,Base address bit 2 mask" "Not masked,Masked" bitfld.long 0x04 17. " [1] ,Base address bit 1 mask" "Not masked,Masked" bitfld.long 0x04 16. " [0] ,Base address bit 0 mask" "Not masked,Masked" newline bitfld.long 0x04 8. " WP ,Write protect" "Allowed,Not allowed" bitfld.long 0x04 0. " V ,Valid bit" "Invalid,Valid" if ((per.l(ad:0x4000C000+0x24+0x08)&0x800000)==0x800000) if ((per.l(ad:0x4000C000+0x24+0x08)&0x100)==0x00) group.long (0x24+0x08)++0x03 line.long 0x00 "CSCR3,Chip Select Control Register" bitfld.long 0x00 26.--31. " SWS ,Secondary wait state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" newline sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK70FN1M0VMJ12")||cpuis("MK70FN1M0VMJ15")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN1M0AVMD12")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "0 cycles,1 cycle,2 cycles,3 cycles" newline else bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" newline endif bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" newline bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Write only,Read/write" bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" else group.long (0x24+0x08)++0x03 line.long 0x00 "CSCR3,Chip Select Control Register" bitfld.long 0x00 26.--31. " SWS ,Secondary wait state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" newline sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK70FN1M0VMJ12")||cpuis("MK70FN1M0VMJ15")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN1M0AVMD12")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" newline else bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "0 cycles,1 cycle,2 cycles,3 cycles" newline endif bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" newline bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Write only,Read/write" bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" endif else if ((per.l(ad:0x4000C000+0x24+0x08)&0x100)==0x00) group.long (0x24+0x08)++0x03 line.long 0x00 "CSCR3,Chip Select Control Register" newline bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" newline sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK70FN1M0VMJ12")||cpuis("MK70FN1M0VMJ15")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN1M0AVMD12")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "0 cycles,1 cycle,2 cycles,3 cycles" newline else bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" newline endif bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" newline bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Write only,Read/write" bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" else group.long (0x24+0x08)++0x03 line.long 0x00 "CSCR3,Chip Select Control Register" newline bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" newline sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK70FN1M0VMJ12")||cpuis("MK70FN1M0VMJ15")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN1M0AVMD12")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" newline else bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "0 cycles,1 cycle,2 cycles,3 cycles" newline endif bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" newline bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Write only,Read/write" bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" endif endif tree.end tree "Chip Select 4" group.long 0x30++0x07 line.long 0x00 "CSAR4,Chip Select Address Register" hexmask.long.word 0x00 16.--31. 0x01 " BA ,Base address" line.long 0x04 "CSMR4,Chip Select Mask Register" bitfld.long 0x04 31. " BAM_[15] ,Base address bit 15 mask" "Not masked,Masked" bitfld.long 0x04 30. " [14] ,Base address bit 14 mask" "Not masked,Masked" bitfld.long 0x04 29. " [13] ,Base address bit 13 mask" "Not masked,Masked" bitfld.long 0x04 28. " [12] ,Base address bit 12 mask" "Not masked,Masked" newline bitfld.long 0x04 27. " [11] ,Base address bit 11 mask" "Not masked,Masked" bitfld.long 0x04 26. " [10] ,Base address bit 10 mask" "Not masked,Masked" bitfld.long 0x04 25. " [9] ,Base address bit 9 mask" "Not masked,Masked" bitfld.long 0x04 24. " [8] ,Base address bit 8 mask" "Not masked,Masked" newline bitfld.long 0x04 23. " [7] ,Base address bit 7 mask" "Not masked,Masked" bitfld.long 0x04 22. " [6] ,Base address bit 6 mask" "Not masked,Masked" bitfld.long 0x04 21. " [5] ,Base address bit 5 mask" "Not masked,Masked" bitfld.long 0x04 20. " [4] ,Base address bit 4 mask" "Not masked,Masked" newline bitfld.long 0x04 19. " [3] ,Base address bit 3 mask" "Not masked,Masked" bitfld.long 0x04 18. " [2] ,Base address bit 2 mask" "Not masked,Masked" bitfld.long 0x04 17. " [1] ,Base address bit 1 mask" "Not masked,Masked" bitfld.long 0x04 16. " [0] ,Base address bit 0 mask" "Not masked,Masked" newline bitfld.long 0x04 8. " WP ,Write protect" "Allowed,Not allowed" bitfld.long 0x04 0. " V ,Valid bit" "Invalid,Valid" if ((per.l(ad:0x4000C000+0x30+0x08)&0x800000)==0x800000) if ((per.l(ad:0x4000C000+0x30+0x08)&0x100)==0x00) group.long (0x30+0x08)++0x03 line.long 0x00 "CSCR4,Chip Select Control Register" bitfld.long 0x00 26.--31. " SWS ,Secondary wait state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" newline sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK70FN1M0VMJ12")||cpuis("MK70FN1M0VMJ15")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN1M0AVMD12")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "0 cycles,1 cycle,2 cycles,3 cycles" newline else bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" newline endif bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" newline bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Write only,Read/write" bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" else group.long (0x30+0x08)++0x03 line.long 0x00 "CSCR4,Chip Select Control Register" bitfld.long 0x00 26.--31. " SWS ,Secondary wait state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" newline sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK70FN1M0VMJ12")||cpuis("MK70FN1M0VMJ15")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN1M0AVMD12")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" newline else bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "0 cycles,1 cycle,2 cycles,3 cycles" newline endif bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" newline bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Write only,Read/write" bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" endif else if ((per.l(ad:0x4000C000+0x30+0x08)&0x100)==0x00) group.long (0x30+0x08)++0x03 line.long 0x00 "CSCR4,Chip Select Control Register" newline bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" newline sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK70FN1M0VMJ12")||cpuis("MK70FN1M0VMJ15")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN1M0AVMD12")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "0 cycles,1 cycle,2 cycles,3 cycles" newline else bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" newline endif bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" newline bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Write only,Read/write" bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" else group.long (0x30+0x08)++0x03 line.long 0x00 "CSCR4,Chip Select Control Register" newline bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" newline sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK70FN1M0VMJ12")||cpuis("MK70FN1M0VMJ15")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN1M0AVMD12")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" newline else bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "0 cycles,1 cycle,2 cycles,3 cycles" newline endif bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" newline bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Write only,Read/write" bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" endif endif tree.end tree "Chip Select 5" group.long 0x3C++0x07 line.long 0x00 "CSAR5,Chip Select Address Register" hexmask.long.word 0x00 16.--31. 0x01 " BA ,Base address" line.long 0x04 "CSMR5,Chip Select Mask Register" bitfld.long 0x04 31. " BAM_[15] ,Base address bit 15 mask" "Not masked,Masked" bitfld.long 0x04 30. " [14] ,Base address bit 14 mask" "Not masked,Masked" bitfld.long 0x04 29. " [13] ,Base address bit 13 mask" "Not masked,Masked" bitfld.long 0x04 28. " [12] ,Base address bit 12 mask" "Not masked,Masked" newline bitfld.long 0x04 27. " [11] ,Base address bit 11 mask" "Not masked,Masked" bitfld.long 0x04 26. " [10] ,Base address bit 10 mask" "Not masked,Masked" bitfld.long 0x04 25. " [9] ,Base address bit 9 mask" "Not masked,Masked" bitfld.long 0x04 24. " [8] ,Base address bit 8 mask" "Not masked,Masked" newline bitfld.long 0x04 23. " [7] ,Base address bit 7 mask" "Not masked,Masked" bitfld.long 0x04 22. " [6] ,Base address bit 6 mask" "Not masked,Masked" bitfld.long 0x04 21. " [5] ,Base address bit 5 mask" "Not masked,Masked" bitfld.long 0x04 20. " [4] ,Base address bit 4 mask" "Not masked,Masked" newline bitfld.long 0x04 19. " [3] ,Base address bit 3 mask" "Not masked,Masked" bitfld.long 0x04 18. " [2] ,Base address bit 2 mask" "Not masked,Masked" bitfld.long 0x04 17. " [1] ,Base address bit 1 mask" "Not masked,Masked" bitfld.long 0x04 16. " [0] ,Base address bit 0 mask" "Not masked,Masked" newline bitfld.long 0x04 8. " WP ,Write protect" "Allowed,Not allowed" bitfld.long 0x04 0. " V ,Valid bit" "Invalid,Valid" if ((per.l(ad:0x4000C000+0x3C+0x08)&0x800000)==0x800000) if ((per.l(ad:0x4000C000+0x3C+0x08)&0x100)==0x00) group.long (0x3C+0x08)++0x03 line.long 0x00 "CSCR5,Chip Select Control Register" bitfld.long 0x00 26.--31. " SWS ,Secondary wait state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" newline sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK70FN1M0VMJ12")||cpuis("MK70FN1M0VMJ15")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN1M0AVMD12")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "0 cycles,1 cycle,2 cycles,3 cycles" newline else bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" newline endif bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" newline bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Write only,Read/write" bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" else group.long (0x3C+0x08)++0x03 line.long 0x00 "CSCR5,Chip Select Control Register" bitfld.long 0x00 26.--31. " SWS ,Secondary wait state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" newline sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK70FN1M0VMJ12")||cpuis("MK70FN1M0VMJ15")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN1M0AVMD12")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" newline else bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "0 cycles,1 cycle,2 cycles,3 cycles" newline endif bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" newline bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Write only,Read/write" bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" endif else if ((per.l(ad:0x4000C000+0x3C+0x08)&0x100)==0x00) group.long (0x3C+0x08)++0x03 line.long 0x00 "CSCR5,Chip Select Control Register" newline bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" newline sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK70FN1M0VMJ12")||cpuis("MK70FN1M0VMJ15")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN1M0AVMD12")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "0 cycles,1 cycle,2 cycles,3 cycles" newline else bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" newline endif bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" newline bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Write only,Read/write" bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" else group.long (0x3C+0x08)++0x03 line.long 0x00 "CSCR5,Chip Select Control Register" newline bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" newline sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK70FN1M0VMJ12")||cpuis("MK70FN1M0VMJ15")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN1M0AVMD12")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" newline else bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "0 cycles,1 cycle,2 cycles,3 cycles" newline endif bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" newline bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Write only,Read/write" bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" endif endif tree.end newline sif cpuis("MK30D????ZVLQ*")||cpuis("MK40D*Z*10")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLL10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK60FN1M0VLQ15")||cpuis("MK60DN512ZCAB10R")||cpuis("MK20D????ZVLL10")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK22FN???C?P12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VFX12*")||cpuis("MK22FN512VLH12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("?K28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") if ((per.l(ad:0x4000C000+0x44)&0x100)==0x0) group.long 0x60++0x03 line.long 0x00 "CSPMCR,Chip Select Port Multiplexing Control Register" bitfld.long 0x00 28.--31. " GROUP_1 ,FlexBus signal group 1 multiplex control" "FB_ALE,/FB_CS1,/FB_TS,?..." bitfld.long 0x00 24.--27. " GROUP_2 ,FlexBus signal group 2 multiplex control" "/FB_CS4,FB_TSIZ0,/FB_BE_31_24,?..." bitfld.long 0x00 20.--23. " GROUP_3 ,FlexBus signal group 3 multiplex control" "/FB_CS5,FB_TSIZ1,/FB_BE_23_16,?..." bitfld.long 0x00 16.--19. " GROUP_4 ,FlexBus signal group 4 multiplex control" "/FB_TBST,/FB_CS2,/FB_BE_15_8,?..." newline bitfld.long 0x00 12.--15. " GROUP_5 ,FlexBus signal group 5 multiplex control" "/FB_TA,?..." else group.long 0x60++0x03 line.long 0x00 "CSPMCR,Chip Select Port Multiplexing Control Register" bitfld.long 0x00 28.--31. " GROUP_1 ,FlexBus signal group 1 multiplex control" "FB_ALE,/FB_CS1,/FB_TS,?..." bitfld.long 0x00 24.--27. " GROUP_2 ,FlexBus signal group 2 multiplex control" "/FB_CS4,FB_TSIZ0,/FB_BE_31_24,?..." bitfld.long 0x00 20.--23. " GROUP_3 ,FlexBus signal group 3 multiplex control" "/FB_CS5,FB_TSIZ1,/FB_BE_23_16,?..." bitfld.long 0x00 16.--19. " GROUP_4 ,FlexBus signal group 4 multiplex control" "/FB_TBST,/FB_CS2,/FB_BE_15_8,?..." newline bitfld.long 0x00 12.--15. " GROUP_5 ,FlexBus signal group 5 multiplex control" "/FB_TA,/FB_CS3,/FB_BE_7_0,?..." endif else group.long 0x60++0x03 line.long 0x00 "CSPMCR,Chip Select Port Multiplexing Control Register" bitfld.long 0x00 28.--31. " GROUP_1 ,FlexBus signal group 1 multiplex control" "FB_ALE,/FB_CS1,/FB_TS,?..." bitfld.long 0x00 24.--27. " GROUP_2 ,FlexBus signal group 2 multiplex control" "/FB_CS4,FB_TSIZ0,/FB_BE_31_24,?..." bitfld.long 0x00 20.--23. " GROUP_3 ,FlexBus signal group 3 multiplex control" "/FB_CS5,FB_TSIZ1,/FB_BE_23_16,?..." bitfld.long 0x00 16.--19. " GROUP_4 ,FlexBus signal group 4 multiplex control" "/FB_TBST,/FB_CS2,/FB_BE_15_8,?..." newline bitfld.long 0x00 12.--15. " GROUP_5 ,FlexBus signal group 5 multiplex control" "/FB_TA,/FB_CS3,/FB_BE_7_0,?..." endif width 0x0B tree.end sif !cpuis("MK81FN256VDC15")&&!cpuis("MK81FN256VLL15")&&!cpuis("MK81FN256VDC15R") tree "CRC (Cyclic Redundancy Check)" base ad:0x40032000 width 7. if (((per.l(ad:0x40032000+0x08)&0x1000000)==0x1000000)) group.long 0x00++0x03 line.long 0x00 "CRC,CRC Data Register" hexmask.long.byte 0x00 24.--31. 1. " HU ,CRC high upper byte" hexmask.long.byte 0x00 16.--23. 1. " HL ,CRC high lower byte" newline hexmask.long.byte 0x00 8.--15. 1. " LU ,CRC low upper byte" hexmask.long.byte 0x00 0.--7. 1. " LL ,CRC low lower byte" else group.long 0x00++0x03 line.long 0x00 "CRC,CRC Data Register" hexmask.long.byte 0x00 8.--15. 1. " LU ,CRC low upper byte" hexmask.long.byte 0x00 0.--7. 1. " LL ,CRC low lower byte" endif group.long 0x04++0x07 line.long 0x00 "GPOLY,CRC Polynomial Register" hexmask.long.word 0x00 16.--31. 1. " HIGH ,High polynomial half-word" hexmask.long.word 0x00 0.--15. 1. " LOW ,Low polynomial half-word" line.long 0x04 "CTRL,CRC Control Register" bitfld.long 0x04 30.--31. " TOT ,Type of transpose for writes" "No transposition,Bits,Bits and bytes,Bytes" bitfld.long 0x04 28.--29. " TOTR ,Type of transpose for read" "No transposition,Bits,Bits and bytes,Bytes" newline bitfld.long 0x04 26. " FXOR ,Complement read of CRC data register" "No XOR,Inverted/Complemented" bitfld.long 0x04 25. " WAS ,Write CRC data register as seed" "Data values,Seed values" newline bitfld.long 0x04 24. " TCRC ,Width of CRC protocol" "16-bit,32-bit" width 0x0B tree.end tree "MMCAU (Memory-Mapped Cryptographic Acceleration Unit)" base ad:0xE0081000 width 6. group.long 0x00++0x03 line.long 0x00 "CASR,Status Register" rbitfld.long 0x00 28.--31. " VER ,CAU version" ",Initial CAU version,Second version(with SHA-256 algorithm),?..." bitfld.long 0x00 1. " DPE ,DES parity error" "No error,Error" bitfld.long 0x00 0. " IC ,Illegal command" "Not issued,Issued" group.long 0x01++0x03 line.long 0x00 "CAA,Accumulator" sif cpuis("MK24FN*") group.long 0x2++0x03 line.long 0x00 "CA0,General Purpose Register" group.long 0x3++0x03 line.long 0x00 "CA1,General Purpose Register" group.long 0x4++0x03 line.long 0x00 "CA2,General Purpose Register" group.long 0x5++0x03 line.long 0x00 "CA3,General Purpose Register" group.long 0x6++0x03 line.long 0x00 "CA4,General Purpose Register" group.long 0x7++0x03 line.long 0x00 "CA5,General Purpose Register" else group.long 0x2++0x03 line.long 0x00 "CA0,General Purpose Register" group.long 0x3++0x03 line.long 0x00 "CA1,General Purpose Register" group.long 0x4++0x03 line.long 0x00 "CA2,General Purpose Register" group.long 0x5++0x03 line.long 0x00 "CA3,General Purpose Register" group.long 0x6++0x03 line.long 0x00 "CA4,General Purpose Register" group.long 0x7++0x03 line.long 0x00 "CA5,General Purpose Register" group.long 0x8++0x03 line.long 0x00 "CA6,General Purpose Register" group.long 0x9++0x03 line.long 0x00 "CA7,General Purpose Register" group.long 0xA++0x03 line.long 0x00 "CA8,General Purpose Register" endif width 0x0B tree.end tree "SA-TRNG (Standalone True Random Number Generator)" base ad:0x400A0000 width 12. if (((per.l(ad:0x400A0000))&0x10000)==0x00) group.long 0x00++0x03 line.long 0x00 "MCTL,TRNG Miscellaneous Control Register" bitfld.long 0x00 16. " PRGM ,Programming mode select" "Run mode,Program mode" rbitfld.long 0x00 13. " TSTOP_OK ,RNG ring oscillator (used for entropy generation) is not running" "Running,Not running" eventfld.long 0x00 12. " ERR ,Read: error status (read/write)" "No error/No effect,Error/Clear" newline rbitfld.long 0x00 11. " TST_OUT ,Test point inside ring oscillator" "0,1" rbitfld.long 0x00 10. " ENT_VAL ,Entropy valid" "Not valid,Valid" rbitfld.long 0x00 9. " FCT_VAL ,Frequency count valid" "Not valid,Valid" newline rbitfld.long 0x00 8. " FCT_FAIL ,Frequency count fail" "Not failed,Failed" rbitfld.long 0x00 7. " FOR_SCLK ,Force system clock" "Ring oscillator,System clock" rbitfld.long 0x00 6. " RST_DEF ,Reset defaults" "No effect,Clear" newline bitfld.long 0x00 5. " TRNG_ACC ,TRNG access mode" "No effect,Generate entropy value" rbitfld.long 0x00 2.--3. " OSC_DIV ,Oscillator divide" "/1,/2,/4,/8" rbitfld.long 0x00 0.--1. " SAMP_MODE ,Sample mode (data into: entropy shifter / statistical checker)" "Von Neumann both,Raw data both,Von Neumann/Raw data,?..." else group.long 0x00++0x03 line.long 0x00 "MCTL,RNG TRNG Miscellaneous Control Register" bitfld.long 0x00 16. " PRGM ,Programming mode select" "Run mode,Program mode" rbitfld.long 0x00 13. " TSTOP_OK ,RNG ring oscillator (used for entropy generation) is not running" "Running,Not running" eventfld.long 0x00 12. " ERR ,Read: error status (read/write)" "No error/No effect,Error/Clear" newline rbitfld.long 0x00 11. " TST_OUT ,Test point inside ring oscillator" "0,1" rbitfld.long 0x00 10. " ENT_VAL ,Entropy valid" "Not valid,Valid" rbitfld.long 0x00 9. " FCT_VAL ,Frequency count valid" "Not valid,Valid" newline rbitfld.long 0x00 8. " FCT_FAIL ,Frequency count fail" "Not failed,Failed" bitfld.long 0x00 7. " FOR_SCLK ,Force system clock" "Ring oscillator,System clock" bitfld.long 0x00 6. " RST_DEF ,Reset defaults" "No effect,Clear" newline bitfld.long 0x00 5. " TRNG_ACC ,TRNG access mode" "No effect,Generate entropy value" bitfld.long 0x00 2.--3. " OSC_DIV ,Ring oscillator divide" "/1,/2,/4,/8" bitfld.long 0x00 0.--1. " SAMP_MODE ,Sample mode (data into: entropy shifter / statistical checker)" "Von Neumann both,Raw data both,Von Neumann/Raw data,?..." endif if (((per.l(ad:0x400A0000))&0x10000)==0x00) hgroup.long 0x04++0x03 hide.long 0x00 "SCMISC,TRNG Statistical Check Miscellaneous Register" hgroup.long 0x08++0x03 hide.long 0x00 "PKRRNG,TRNG Poker Range Register" rgroup.long 0x0C++0x03 line.long 0x00 "PKRSQ,TRNG Poker Square Calculation Result Register" hexmask.long.tbyte 0x00 0.--23. 1. " PKR_SQ ,Poker square calculation result" hgroup.long 0x10++0x03 hide.long 0x00 "SDCTL,TRNG Seed Control Register" rgroup.long 0x14++0x03 line.long 0x00 "TOTSAM,Total Samples Register" hexmask.long.tbyte 0x00 0.--19. 1. " TOT_SAM ,Total samples" hgroup.long 0x18++0x03 hide.long 0x00 "FRQMIN,TRNG Frequency Count Minimum Limit Register" if (((per.l(ad:0x400A0000))&0x20)==0x20) rgroup.long 0x1C++0x03 line.long 0x00 "FRQCNT,TRNG Frequency Count Register" hexmask.long.tbyte 0x00 0.--21. 1. " FRQ_CNT ,Frequency count" else hgroup.long 0x1C++0x03 hide.long 0x00 "FRQCNT,TRNG Frequency Count Register" endif rgroup.long 0x20++0x1B line.long 0x00 "SCMC,TRNG Statistical Check Monobit Count Register" hexmask.long.word 0x00 0.--15. 1. " MONO_CNT ,Monobit count" line.long 0x04 "SCR1C,TRNG Statistical Check Run Length 1 Count Register" hexmask.long.word 0x04 16.--30. 1. " R1_1_COUNT ,Runs of one (length 1 count)" hexmask.long.word 0x04 0.--14. 1. " R1_0_COUNT ,Runs of zero (length 1 count)" line.long 0x08 "SCR2C,TRNG Statistical Check Run Length 2 Count Register" hexmask.long.word 0x08 16.--29. 1. " R2_1_COUNT ,Runs of one (length 2 count)" hexmask.long.word 0x08 0.--13. 1. " R2_0_COUNT ,Runs of zero (length 2 count)" line.long 0x0C "SCR3C,TRNG Statistical Check Run Length 3 Count Register" hexmask.long.word 0x0C 16.--28. 1. " R3_1_COUNT ,Runs of ones (length 3 count)" hexmask.long.word 0x0C 0.--12. 1. " R3_0_COUNT ,Runs of zeroes (length 3 count)" line.long 0x10 "SCR4C,TRNG Statistical Check Run Length 4 Count Register" hexmask.long.word 0x10 16.--27. 1. " R4_1_COUNT ,Runs of one (length 4 count)" hexmask.long.word 0x10 0.--11. 1. " R4_0_COUNT ,Runs of zero (length 4 count)" line.long 0x14 "SCR5C,TRNG Statistical Check Run Length 5 Count Register" hexmask.long.word 0x14 16.--26. 1. " R5_1_COUNT ,Runs of one (length 5 count)" hexmask.long.word 0x14 0.--10. 1. " R5_0_COUNT ,Runs of zero (length 5 count)" line.long 0x18 "SCR6PC,TRNG Statistical Check Run Length 6+ Count Register" hexmask.long.word 0x18 16.--26. 1. " R6P_1_COUNT ,Runs of one (length 6+ count)" hexmask.long.word 0x18 0.--10. 1. " R6P_0_COUNT ,Runs of zero (length 6+ count)" else group.long 0x04++0x37 line.long 0x00 "SCMISC,TRNG Statistical Check Miscellaneous Register" bitfld.long 0x00 16.--19. " RTY_CNT ,Retry count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " LRUN_MAX ,Long run max limit" line.long 0x04 "PKRRNG,TRNG Poker Range Register" hexmask.long.word 0x04 0.--15. 1. " PKR_RNG ,Poker range" line.long 0x08 "PKRMAX,TRNG Poker Maximum Limit Register" hexmask.long.tbyte 0x08 0.--23. 1. " PKR_MAX ,Poker maximum limit" line.long 0x0C "SDCTL,TRNG Seed Control Register" hexmask.long.word 0x0C 16.--31. 1. " ENT_DLY ,Entropy delay" hexmask.long.word 0x0C 0.--15. 1. " SAMP_SIZE ,Sample size" line.long 0x10 "SBLIM,TRNG Sparse Bit Limit Register" hexmask.long.word 0x10 0.--9. 1. " SB_LIM ,Sparse bit limit" line.long 0x14 "FRQMIN,TRNG Frequency Count Minimum Limit Register" hexmask.long.tbyte 0x14 0.--21. 1. " FRQ_MIN ,Frequency Count minimum limit" line.long 0x18 "FRQMAX,TRNG Frequency Count Maximum Limit Register" hexmask.long.tbyte 0x18 0.--21. 1. " FRQ_MAX ,Frequency Counter maximum limit" line.long 0x1C "SCML,TRNG Statistical Check Monobit Limit Register" hexmask.long.word 0x1C 16.--31. 1. " MONO_RNG ,Monobit range" hexmask.long.word 0x1C 0.--15. 1. " MONO_MAX ,Monobit maximum limit" line.long 0x20 "SCR1L,TRNG Statistical Check Run Length 1 Limit Register" hexmask.long.word 0x20 16.--30. 1. " RUN1_RNG ,Run length 1 range" hexmask.long.word 0x20 0.--14. 1. " RUN1_MAX ,Run length 1 maximum limit" line.long 0x24 "SCR2L,TRNG Statistical Check Run Length 2 Limit Register" hexmask.long.word 0x24 16.--29. 1. " RUN2_RNG ,Run length 2 range" hexmask.long.word 0x24 0.--13. 1. " RUN2_MAX ,Run length 2 maximum limit" line.long 0x28 "SCR3L,TRNG Statistical Check Run Length 3 Limit Register" hexmask.long.word 0x28 16.--28. 1. " RUN3_RNG ,Run length 3 range" hexmask.long.word 0x28 0.--12. 1. " RUN3_MAX ,Run length 3 maximum limit" line.long 0x2C "SCR4L,TRNG Statistical Check Run Length 4 Limit Register" hexmask.long.word 0x2C 16.--27. 1. " RUN4_RNG ,Run length 4 range" hexmask.long.word 0x2C 0.--11. 1. " RUN4_MAX ,Run length 4 maximum limit" line.long 0x30 "SCR5L,TRNG Statistical Check Run Length 5 Limit Register" hexmask.long.word 0x30 16.--26. 1. " RUN5_RNG ,Run length 5 range" hexmask.long.word 0x30 0.--10. 1. " RUN5_MAX ,Run length 5 maximum limit" line.long 0x34 "SCR6PL,TRNG Statistical Check Run Length 6+ Limit Register" hexmask.long.word 0x34 16.--26. 1. " RUN6P_RNG ,Run length 6+ range" hexmask.long.word 0x34 0.--10. 1. " RUN6P_MAX ,Run length 6+ maximum limit" endif if (((per.l(ad:0x400A0000))&0x10000)==0x10000) hgroup.long 0x3C++0x03 hide.long 0x00 "STATUS,TRNG Status Register" else rgroup.long 0x3C++0x03 line.long 0x00 "STATUS,TRNG Status Register" bitfld.long 0x00 16.--19. " RETRY_COUNT ,Retry count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " TFMB ,Mono bit test fail" "Not failed,Failed" bitfld.long 0x00 14. " TFP ,Poker test fail" "Not failed,Failed" newline bitfld.long 0x00 13. " TFLR ,Long run test fail" "Not failed,Failed" bitfld.long 0x00 12. " TFSB ,Sparse bit test fail" "Not failed,Failed" bitfld.long 0x00 11. " TF6PBR1 ,6 Plus bit run (sampling 1s) test fail" "Not failed,Failed" newline bitfld.long 0x00 10. " TF6PBR0 ,6 Plus bit run (sampling 0s) test fail" "Not failed,Failed" bitfld.long 0x00 9. " TF5BR1 ,5-bit run (sampling 1s) test fail" "Not failed,Failed" bitfld.long 0x00 8. " TF5BR0 ,5-bit run (sampling 0s) test fail" "Not failed,Failed" newline bitfld.long 0x00 7. " TF4BR1 ,4-bit run (sampling 1s) test fail" "Not failed,Failed" bitfld.long 0x00 6. " TF4BR0 ,4-bit run (sampling 0s) test fail" "Not failed,Failed" bitfld.long 0x00 5. " TF3BR1 ,3-bit run (sampling 1s) test fail" "Not failed,Failed" newline bitfld.long 0x00 4. " TF3BR0 ,3-bit run (sampling 0s) test fail" "Not failed,Failed" bitfld.long 0x00 3. " TF2BR1 ,2-bit run (sampling 1s) test fail" "Not failed,Failed" bitfld.long 0x00 2. " TF2BR0 ,2-bit run (sampling 0s) test fail" "Not failed,Failed" newline bitfld.long 0x00 1. " TF1BR1 ,1-bit run (sampling 1s) test fail" "Not failed,Failed" bitfld.long 0x00 0. " TF1BR0 ,1-bit run (sampling 0s) test fail" "Not failed,Failed" endif sif (cpuis("IMX7ULP-CM4")||cpuis("IMX7ULP-CM4")) if (((per.l(ad:0x400A0000))&0x10420)==0x420) rgroup.long 0x40++0x03 line.long 0x00 "ENT0,TRNG Entropy Read Register 0" else hgroup.long 0x40++0x03 hide.long 0x00 "ENT0,TRNG Entropy Read Register 0" endif if (((per.l(ad:0x400A0000))&0x10420)==0x420) rgroup.long 0x44++0x03 line.long 0x00 "ENT1,TRNG Entropy Read Register 1" else hgroup.long 0x44++0x03 hide.long 0x00 "ENT1,TRNG Entropy Read Register 1" endif if (((per.l(ad:0x400A0000))&0x10420)==0x420) rgroup.long 0x48++0x03 line.long 0x00 "ENT2,TRNG Entropy Read Register 2" else hgroup.long 0x48++0x03 hide.long 0x00 "ENT2,TRNG Entropy Read Register 2" endif if (((per.l(ad:0x400A0000))&0x10420)==0x420) rgroup.long 0x4C++0x03 line.long 0x00 "ENT3,TRNG Entropy Read Register 3" else hgroup.long 0x4C++0x03 hide.long 0x00 "ENT3,TRNG Entropy Read Register 3" endif if (((per.l(ad:0x400A0000))&0x10420)==0x420) rgroup.long 0x50++0x03 line.long 0x00 "ENT4,TRNG Entropy Read Register 4" else hgroup.long 0x50++0x03 hide.long 0x00 "ENT4,TRNG Entropy Read Register 4" endif if (((per.l(ad:0x400A0000))&0x10420)==0x420) rgroup.long 0x54++0x03 line.long 0x00 "ENT5,TRNG Entropy Read Register 5" else hgroup.long 0x54++0x03 hide.long 0x00 "ENT5,TRNG Entropy Read Register 5" endif if (((per.l(ad:0x400A0000))&0x10420)==0x420) rgroup.long 0x58++0x03 line.long 0x00 "ENT6,TRNG Entropy Read Register 6" else hgroup.long 0x58++0x03 hide.long 0x00 "ENT6,TRNG Entropy Read Register 6" endif if (((per.l(ad:0x400A0000))&0x10420)==0x420) rgroup.long 0x5C++0x03 line.long 0x00 "ENT7,TRNG Entropy Read Register 7" else hgroup.long 0x5C++0x03 hide.long 0x00 "ENT7,TRNG Entropy Read Register 7" endif if (((per.l(ad:0x400A0000))&0x10420)==0x420) rgroup.long 0x60++0x03 line.long 0x00 "ENT8,TRNG Entropy Read Register 8" else hgroup.long 0x60++0x03 hide.long 0x00 "ENT8,TRNG Entropy Read Register 8" endif if (((per.l(ad:0x400A0000))&0x10420)==0x420) rgroup.long 0x64++0x03 line.long 0x00 "ENT9,TRNG Entropy Read Register 9" else hgroup.long 0x64++0x03 hide.long 0x00 "ENT9,TRNG Entropy Read Register 9" endif if (((per.l(ad:0x400A0000))&0x10420)==0x420) rgroup.long 0x68++0x03 line.long 0x00 "ENT10,TRNG Entropy Read Register 10" else hgroup.long 0x68++0x03 hide.long 0x00 "ENT10,TRNG Entropy Read Register 10" endif if (((per.l(ad:0x400A0000))&0x10420)==0x420) rgroup.long 0x6C++0x03 line.long 0x00 "ENT11,TRNG Entropy Read Register 11" else hgroup.long 0x6C++0x03 hide.long 0x00 "ENT11,TRNG Entropy Read Register 11" endif if (((per.l(ad:0x400A0000))&0x10420)==0x420) rgroup.long 0x70++0x03 line.long 0x00 "ENT12,TRNG Entropy Read Register 12" else hgroup.long 0x70++0x03 hide.long 0x00 "ENT12,TRNG Entropy Read Register 12" endif if (((per.l(ad:0x400A0000))&0x10420)==0x420) rgroup.long 0x74++0x03 line.long 0x00 "ENT13,TRNG Entropy Read Register 13" else hgroup.long 0x74++0x03 hide.long 0x00 "ENT13,TRNG Entropy Read Register 13" endif if (((per.l(ad:0x400A0000))&0x10420)==0x420) rgroup.long 0x78++0x03 line.long 0x00 "ENT14,TRNG Entropy Read Register 14" else hgroup.long 0x78++0x03 hide.long 0x00 "ENT14,TRNG Entropy Read Register 14" endif if (((per.l(ad:0x400A0000))&0x10420)==0x420) hgroup.long 0x7C++0x03 hide.long 0x00 "ENT15,TRNG Entropy Read Register 15" in else hgroup.long 0x7C++0x03 hide.long 0x00 "ENT15,TRNG Entropy Read Register 15" endif else if (((per.l(ad:0x400A0000))&0x10420)==0x420) hgroup.long 0x40++0x03 hide.long 0x00 "ENT0,TRNG Entropy Read Register 0" in else hgroup.long 0x40++0x03 hide.long 0x00 "ENT0,TRNG Entropy Read Register 0" endif if (((per.l(ad:0x400A0000))&0x10420)==0x420) hgroup.long 0x44++0x03 hide.long 0x00 "ENT1,TRNG Entropy Read Register 1" in else hgroup.long 0x44++0x03 hide.long 0x00 "ENT1,TRNG Entropy Read Register 1" endif if (((per.l(ad:0x400A0000))&0x10420)==0x420) hgroup.long 0x48++0x03 hide.long 0x00 "ENT2,TRNG Entropy Read Register 2" in else hgroup.long 0x48++0x03 hide.long 0x00 "ENT2,TRNG Entropy Read Register 2" endif if (((per.l(ad:0x400A0000))&0x10420)==0x420) hgroup.long 0x4C++0x03 hide.long 0x00 "ENT3,TRNG Entropy Read Register 3" in else hgroup.long 0x4C++0x03 hide.long 0x00 "ENT3,TRNG Entropy Read Register 3" endif if (((per.l(ad:0x400A0000))&0x10420)==0x420) hgroup.long 0x50++0x03 hide.long 0x00 "ENT4,TRNG Entropy Read Register 4" in else hgroup.long 0x50++0x03 hide.long 0x00 "ENT4,TRNG Entropy Read Register 4" endif if (((per.l(ad:0x400A0000))&0x10420)==0x420) hgroup.long 0x54++0x03 hide.long 0x00 "ENT5,TRNG Entropy Read Register 5" in else hgroup.long 0x54++0x03 hide.long 0x00 "ENT5,TRNG Entropy Read Register 5" endif if (((per.l(ad:0x400A0000))&0x10420)==0x420) hgroup.long 0x58++0x03 hide.long 0x00 "ENT6,TRNG Entropy Read Register 6" in else hgroup.long 0x58++0x03 hide.long 0x00 "ENT6,TRNG Entropy Read Register 6" endif if (((per.l(ad:0x400A0000))&0x10420)==0x420) hgroup.long 0x5C++0x03 hide.long 0x00 "ENT7,TRNG Entropy Read Register 7" in else hgroup.long 0x5C++0x03 hide.long 0x00 "ENT7,TRNG Entropy Read Register 7" endif if (((per.l(ad:0x400A0000))&0x10420)==0x420) hgroup.long 0x60++0x03 hide.long 0x00 "ENT8,TRNG Entropy Read Register 8" in else hgroup.long 0x60++0x03 hide.long 0x00 "ENT8,TRNG Entropy Read Register 8" endif if (((per.l(ad:0x400A0000))&0x10420)==0x420) hgroup.long 0x64++0x03 hide.long 0x00 "ENT9,TRNG Entropy Read Register 9" in else hgroup.long 0x64++0x03 hide.long 0x00 "ENT9,TRNG Entropy Read Register 9" endif if (((per.l(ad:0x400A0000))&0x10420)==0x420) hgroup.long 0x68++0x03 hide.long 0x00 "ENT10,TRNG Entropy Read Register 10" in else hgroup.long 0x68++0x03 hide.long 0x00 "ENT10,TRNG Entropy Read Register 10" endif if (((per.l(ad:0x400A0000))&0x10420)==0x420) hgroup.long 0x6C++0x03 hide.long 0x00 "ENT11,TRNG Entropy Read Register 11" in else hgroup.long 0x6C++0x03 hide.long 0x00 "ENT11,TRNG Entropy Read Register 11" endif if (((per.l(ad:0x400A0000))&0x10420)==0x420) hgroup.long 0x70++0x03 hide.long 0x00 "ENT12,TRNG Entropy Read Register 12" in else hgroup.long 0x70++0x03 hide.long 0x00 "ENT12,TRNG Entropy Read Register 12" endif if (((per.l(ad:0x400A0000))&0x10420)==0x420) hgroup.long 0x74++0x03 hide.long 0x00 "ENT13,TRNG Entropy Read Register 13" in else hgroup.long 0x74++0x03 hide.long 0x00 "ENT13,TRNG Entropy Read Register 13" endif if (((per.l(ad:0x400A0000))&0x10420)==0x420) hgroup.long 0x78++0x03 hide.long 0x00 "ENT14,TRNG Entropy Read Register 14" in else hgroup.long 0x78++0x03 hide.long 0x00 "ENT14,TRNG Entropy Read Register 14" endif if (((per.l(ad:0x400A0000))&0x10420)==0x420) hgroup.long 0x7C++0x03 hide.long 0x00 "ENT15,TRNG Entropy Read Register 15" in else hgroup.long 0x7C++0x03 hide.long 0x00 "ENT15,TRNG Entropy Read Register 15" endif endif if (((per.l(ad:0x400A0000))&0x10000)==0x0) rgroup.long 0x80++0x03 line.long 0x00 "PKRCNT10,TRNG Statistical Check Poker Count 1 And 0 Register" hexmask.long.word 0x00 16.--31. 1. " PKR_1_CT ,Poker 1h count" hexmask.long.word 0x00 0.--15. 1. " PKR_0_CT ,Poker 0h count" rgroup.long 0x84++0x03 line.long 0x00 "PKRCNT32,TRNG Statistical Check Poker Count 3 And 2 Register" hexmask.long.word 0x00 16.--31. 1. " PKR_3_CT ,Poker 3h count" hexmask.long.word 0x00 0.--15. 1. " PKR_2_CT ,Poker 2h count" rgroup.long 0x88++0x03 line.long 0x00 "PKRCNT54,TRNG Statistical Check Poker Count 5 And 4 Register" hexmask.long.word 0x00 16.--31. 1. " PKR_5_CT ,Poker 5h count" hexmask.long.word 0x00 0.--15. 1. " PKR_4_CT ,Poker 4h count" rgroup.long 0x8C++0x03 line.long 0x00 "PKRCNT76,TRNG Statistical Check Poker Count 7 And 6 Register" hexmask.long.word 0x00 16.--31. 1. " PKR_7_CT ,Poker 7h count" hexmask.long.word 0x00 0.--15. 1. " PKR_6_CT ,Poker 6h count" rgroup.long 0x90++0x03 line.long 0x00 "PKRCNT98,TRNG Statistical Check Poker Count 9 And 8 Register" hexmask.long.word 0x00 16.--31. 1. " PKR_9_CT ,Poker 9h count" hexmask.long.word 0x00 0.--15. 1. " PKR_8_CT ,Poker 8h count" rgroup.long 0x94++0x03 line.long 0x00 "PKRCNTBA,TRNG Statistical Check Poker Count B And A Register" hexmask.long.word 0x00 16.--31. 1. " PKR_B_CT ,Poker Bh count" hexmask.long.word 0x00 0.--15. 1. " PKR_A_CT ,Poker Ah count" rgroup.long 0x98++0x03 line.long 0x00 "PKRCNTDC,TRNG Statistical Check Poker Count D And C Register" hexmask.long.word 0x00 16.--31. 1. " PKR_D_CT ,Poker Dh count" hexmask.long.word 0x00 0.--15. 1. " PKR_C_CT ,Poker Ch count" rgroup.long 0x9C++0x03 line.long 0x00 "PKRCNTFE,TRNG Statistical Check Poker Count F And E Register" hexmask.long.word 0x00 16.--31. 1. " PKR_F_CT ,Poker Fh count" hexmask.long.word 0x00 0.--15. 1. " PKR_E_CT ,Poker Eh count" else hgroup.long 0x80++0x03 hide.long 0x00 "PKRCNT10,TRNG Statistical Check Poker Count 1 And 0 Register" hgroup.long 0x84++0x03 hide.long 0x00 "PKRCNT32,TRNG Statistical Check Poker Count 3 And 2 Register" hgroup.long 0x88++0x03 hide.long 0x00 "PKRCNT54,TRNG Statistical Check Poker Count 5 And 4 Register" hgroup.long 0x8C++0x03 hide.long 0x00 "PKRCNT76,TRNG Statistical Check Poker Count 7 And 6 Register" hgroup.long 0x90++0x03 hide.long 0x00 "PKRCNT98,TRNG Statistical Check Poker Count 9 And 8 Register" hgroup.long 0x94++0x03 hide.long 0x00 "PKRCNTBA,TRNG Statistical Check Poker Count B And A Register" hgroup.long 0x98++0x03 hide.long 0x00 "PKRCNTDC,TRNG Statistical Check Poker Count D And C Register" hgroup.long 0x9C++0x03 hide.long 0x00 "PKRCNTFE,TRNG Statistical Check Poker Count F And E Register" endif sif (cpuis("MK8?FN256V*")||cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")||cpuis("MKV5*")) group.long 0xB0++0x0F line.long 0x00 "SEC_CFG,TRNG Security Configuration Register" bitfld.long 0x00 1. " NO_PRGM ,TRNG registers cannot be programmed" "No,Yes" line.long 0x04 "INT_CTRL,TRNG Interrupt Control Register" bitfld.long 0x04 2. " FRQ_CT_FAIL ,Frequency count fail interrupt control status" "Cleared,Active" bitfld.long 0x04 1. " ENT_VAL ,Entropy valid interrupt control status" "Cleared,Active" bitfld.long 0x04 0. " HW_ERR ,HW error interrupt control status" "Cleared,Active" line.long 0x08 "INT_MASK,TRNG Mask Register" bitfld.long 0x08 2. " FRQ_CT_FAIL ,Frequency count fail interrupt mask" "Masked,Not masked" bitfld.long 0x08 1. " ENT_VAL ,Entropy valid interrupt mask" "Masked,Not masked" bitfld.long 0x08 0. " HW_ERR ,HW error interrupt mask" "Masked,Not masked" line.long 0x0C "INT_STATUS,TRNG Interrupt Status Register" bitfld.long 0x0C 2. " FRQ_CT_FAIL ,Frequency count fail interrupt status" "Not failed,Failed" rbitfld.long 0x0C 1. " ENT_VAL ,Entropy valid interrupt status" "Invalid,Valid" rbitfld.long 0x0C 0. " HW_ERR ,HW error interrupt status" "No error,Error" else group.long 0xA0++0x0F line.long 0x00 "SEC_CFG,TRNG Security Configuration Register" bitfld.long 0x00 1. " NO_PRGM ,TRNG registers cannot be programmed" "No,Yes" line.long 0x04 "INT_CTRL,TRNG Interrupt Control Register" bitfld.long 0x04 2. " FRQ_CT_FAIL ,Frequency count fail interrupt control status" "Cleared,Active" bitfld.long 0x04 1. " ENT_VAL ,Entropy valid interrupt control status" "Cleared,Active" bitfld.long 0x04 0. " HW_ERR ,HW error interrupt control status" "Cleared,Active" line.long 0x08 "INT_MASK,TRNG Mask Register" bitfld.long 0x08 2. " FRQ_CT_FAIL ,Frequency count fail interrupt mask" "Masked,Not masked" bitfld.long 0x08 1. " ENT_VAL ,Entropy valid interrupt mask" "Masked,Not masked" bitfld.long 0x08 0. " HW_ERR ,HW error interrupt mask" "Masked,Not masked" line.long 0x0C "INT_STATUS,TRNG Interrupt Status Register" sif (cpuis("K32W0?2S1M*")||cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) rbitfld.long 0x0C 2. " FRQ_CT_FAIL ,Frequency count fail interrupt status" "Not failed,Failed" else bitfld.long 0x0C 2. " FRQ_CT_FAIL ,Frequency count fail interrupt status" "Not failed,Failed" endif newline rbitfld.long 0x0C 1. " ENT_VAL ,Entropy valid interrupt status" "Invalid,Valid" rbitfld.long 0x0C 0. " HW_ERR ,HW error interrupt status" "No error,Error" endif rgroup.long 0xF0++0x07 line.long 0x00 "VID1,Version ID (MS) Register" hexmask.long.word 0x00 16.--31. 1. " TRNG_IP_ID ,Shows IP ID" hexmask.long.byte 0x00 8.--15. 1. " TRNG_MAJ_REV ,Shows IP's major revision of the TRNG" hexmask.long.byte 0x00 0.--7. 1. " TRNG_MIN_REV ,Shows IP's minor revision of the TRNG" line.long 0x04 "VID2,Version ID (LS) Register" hexmask.long.byte 0x04 24.--31. 1. " TRNG_ERA ,Shows compile options for the TRNG" hexmask.long.byte 0x04 16.--23. 1. " TRNG_INTG_OPT ,Shows integration options for the TRNG" hexmask.long.byte 0x04 8.--15. 1. " TRNG_ECO_REV ,Shows IP's ECO revision of the TRNG" newline hexmask.long.byte 0x04 0.--7. 1. " TRNG_CONFIG_OPT ,Shows IP's Configuration options for the TRNG" width 0x0B tree.end endif sif cpuis("MK82FN256VDC15")||cpuis("MK82FN256VLL15") tree "LTC (LP Trusted Cryptography)" base ad:0x400D1000 width 14. if (((per.l(ad:0x400D1000))&0xF00000)==0x800000) if (((per.l(ad:0x400D1000))&0x3F)==0x01) group.long 0x00++0x03 line.long 0x00 "LTC0_MDPK,LTC Mode (PublicKey)" bitfld.long 0x00 20.--23. " ALG ,Algorithm" ",AES,DES,,,,,,PKHA,?..." bitfld.long 0x00 19. " ARAM ,Aram" "A not selected,A selected" bitfld.long 0x00 18. " BRAM ,Bram" "B not selected,B selected" newline bitfld.long 0x00 17. " ERAM ,Eram" "E not selected,E selected" bitfld.long 0x00 16. " NRAM ,Nram" "N not selected,N selected" bitfld.long 0x00 9. " Q3 ,Quadrant 3" "Not selected,Selected" newline bitfld.long 0x00 8. " Q2 ,Quadrant 2" "Not selected,Selected" bitfld.long 0x00 7. " Q1 ,Quadrant 1" "Not selected,Selected" bitfld.long 0x00 6. " Q0 ,Quadrant 0" "Not selected,Selected" newline bitfld.long 0x00 0.--5. " Function ,Function" ",,(A + B) mod N,(A - B) mod N,(B - A) mod N,(A x B) mod N,A^E mod N,A mod N,A^-1 mod N,(P1 + P2),(P2 + P2),(E x P1),,,GCD(A,N),Miller-Rabin Primality Test,?..." elif (((per.l(ad:0x400D1000))&0x1F)==(0x10||0x11)) group.long 0x00++0x03 line.long 0x00 "LTC0_MDPK,LTC Mode (PublicKey)" bitfld.long 0x00 20.--23. " ALG ,Algorithm" ",AES,DES,,,,,,PKHA,?..." bitfld.long 0x00 17.--19. " Source_Register ,Source Register" "A,B,,N,?..." bitfld.long 0x00 10.--11. 16. " Destination_Register ,Destination Register" "A,B,E,N,?..." newline bitfld.long 0x00 8.--9. " SOURCE_SEGMENT ,Source Segment" "0,1,2,3" bitfld.long 0x00 6.--7. " DESTINATION_SEGMENT ,Destination Segment" "0,1,2,3" newline newline bitfld.long 0x00 0.--5. " FUNCTION ,Function" ",,(A + B) mod N,(A - B) mod N,(B - A) mod N,(A x B) mod N,A^E mod N,A mod N,A^-1 mod N,(P1 + P2),(P2 + P2),(E x P1),,,GCD(A,N),Miller-Rabin Primality Test,?..." elif (((per.l(ad:0x400D1000))&0xF0)==0x00) group.long 0x00++0x03 line.long 0x00 "LTC0_MDPK,LTC Mode (PublicKey)" bitfld.long 0x00 20.--23. " ALG ,Algorithm" ",AES,DES,,,,,,PKHA,?..." bitfld.long 0x00 19. " INM ,Inputs in Montgomery Format" "Normal,Montgomery" bitfld.long 0x00 18. " OUTM ,Outputs in Montgomery format" "Normal,Montgomery" newline bitfld.long 0x00 17. " F2M ,F2m" "Integer,Binary" bitfld.long 0x00 16. " R2 ,R2 mod N" "Calculated,Input" bitfld.long 0x00 10. " TEQ ,Timing Equalized" "Not Equalized,Equalized" newline bitfld.long 0x00 8.--9. " OUTSEL ,Output destination select" "B,A,?..." newline bitfld.long 0x00 0.--5. " Function ,Function" ",,(A + B) mod N,(A - B) mod N,(B - A) mod N,(A x B) mod N,A^E mod N,A mod N,A^-1 mod N,(P1 + P2),(P2 + P2),(E x P1),,,GCD(A,N),Miller-Rabin Primality Test,?..." else group.long 0x00++0x03 line.long 0x00 "LTC0_MDPK,LTC Mode (PublicKey)" bitfld.long 0x00 20.--23. " ALG ,Algorithm" ",AES,DES,,,,,,PKHA,?..." newline newline newline bitfld.long 0x00 0.--5. " Function ,Function" ",,(A + B) mod N,(A - B) mod N,(B - A) mod N,(A x B) mod N,A^E mod N,A mod N,A^-1 mod N,(P1 + P2),(P2 + P2),(E x P1),,,GCD(A,N),Miller-Rabin Primality Test,?..." endif elif (((per.l(ad:0x400D1000))&0xFF0000)==0x100000)&&(((per.l(ad:0x400D1000))&0x1F00)==0x200) group.long 0x00++0x03 line.long 0x00 "LTC0_MD,LTC Mode (non-PKHA/non-RNG use)" hexmask.long.byte 0x00 16.--23. 1. " ALG ,Algorithm" hexmask.long.word 0x00 4.--12. 1. " AAI ,Additional Algorithm information" bitfld.long 0x00 2.--3. " AS ,Algorithm State" "Updated,Initialized,Finalized,Initialized/Finalized" newline bitfld.long 0x00 1. " ICV_TEST ,ICV Checking" "Not Compared,Compared" bitfld.long 0x00 0. " ENC ,Encrypt/Decrypt" "Decrypted,Encrypted" else group.long 0x00++0x03 line.long 0x00 "LTC0_MD,LTC Mode (non-PKHA/non-RNG use)" bitfld.long 0x00 16.--23. " ALG ,Algorithm" ",,,,,,,,,,,,,,,,AES,,,,,,,,,,,,,,,,DES,3DES,?..." hexmask.long.word 0x00 4.--12. 1. " AAI ,Additional Algorithm information" bitfld.long 0x00 2.--3. " AS ,Algorithm State" "Updated,Initialized,Finalized,Initialized/Finalized" newline bitfld.long 0x00 1. " ICV_TEST ,Test AES fault detection" "Not Injected,Injected" bitfld.long 0x00 0. " ENC ,Encrypt/Decrypt" "Decrypted,Encrypted" endif group.long 0x08++0x03 line.long 0x00 "LTC0_KS,LTC Key Size" bitfld.long 0x00 0.--5. " KS ,Key Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x10++0x03 line.long 0x00 "LTC0_DS,LTC Data Size" hexmask.long.word 0x00 0.--11. 1. " DS ,Data Size" group.long 0x18++0x03 line.long 0x00 "LTC0_ICVS,LTC ICV Size" bitfld.long 0x00 0.--4. " ICVS ,ICV Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" wgroup.long 0x30++0x03 line.long 0x00 "LTC0_COM,LTC Command" sif cpuis("MKL82Z*") bitfld.long 0x00 7. " MD ,Reset MDHA" "No effect,Reset" newline endif bitfld.long 0x00 6. " PK ,Reset PKHA" "No effect,Reset" bitfld.long 0x00 2. " DES ,Reset DESA" "No effect,Reset" bitfld.long 0x00 1. " AES ,Reset AESA" "No effect,Reset" bitfld.long 0x00 0. " ALL ,Reset All Internal Logic" "No effect,Reset" group.long 0x34++0x03 line.long 0x00 "LTC0_CTL,LTC Control" bitfld.long 0x00 31. " KAL ,Key Register Access Lock" "Not locked,Locked" bitfld.long 0x00 23. " COS ,Context Register Output Byte Swap" "Not swapped,Swapped" bitfld.long 0x00 22. " CIS ,Context Register Input Byte Swap" "Not swapped,Swapped" newline bitfld.long 0x00 21. " KOS ,Key Register Output Byte Swap" "Not swapped,Swapped" bitfld.long 0x00 20. " KIS ,Key Register Input Byte Swap" "Not swapped,Swapped" bitfld.long 0x00 17. " OFS ,Output FIFO Byte Swap" "Not swapped,Swapped" newline bitfld.long 0x00 16. " IFS ,Input FIFO Byte Swap" "Not swapped,Swapped" bitfld.long 0x00 13. " OFR ,Output FIFO DMA Request Size" "1 Entry,4 Entries" bitfld.long 0x00 12. " OFE ,Output FIFO DMA Enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " IFR ,Input FIFO DMA Request Size" "1 Entry,4 Entries" bitfld.long 0x00 8. " IFE ,Input FIFO DMA Enable" "Disabled,Enabled" bitfld.long 0x00 4. " PDE ,PKHA Register DMA Enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " IM ,Interrupt Mask" "Not masked,Masked" wgroup.long 0x40++0x03 line.long 0x00 "LTC0_CW,LTC Clear Written" bitfld.long 0x00 31. " CIF ,Clear Input FIFO" "No effect,Clear" bitfld.long 0x00 30. " COF ,Clear Output FIFO" "No effect,Clear" bitfld.long 0x00 15. " CPKE ,Clear the PKHA E Size Register" "No effect,Clear" bitfld.long 0x00 14. " CPKN ,Clear the PKHA N Size Register" "No effect,Clear" newline bitfld.long 0x00 13. " CPKB ,Clear the PHKA B Size Register" "No effect,Clear" bitfld.long 0x00 12. " CPKA ,Clear the PHKA A Size Register" "No effect,Clear" bitfld.long 0x00 6. " CKR ,Clear the Key Register" "No effect,Clear" bitfld.long 0x00 5. " CCR ,Clear the Context Register" "No effect,Clear" newline bitfld.long 0x00 3. " CICV ,Clear the ICV Size Register" "No effect,Clear" bitfld.long 0x00 2. " CDS ,Clear the Data Size Register" "No effect,Clear" bitfld.long 0x00 0. " CM ,Clear the Mode Register" "No effect,Clear" group.long 0x48++0x03 line.long 0x00 "LTC0_STA,LTC Status" rbitfld.long 0x00 30. " PKZ ,Public Key Operation is Zero" "Not zero,Zero" rbitfld.long 0x00 29. " PKO ,Public Key Operation is One" "Not one,One" rbitfld.long 0x00 28. " PKP ,Public Key is Prime" "Not prime,Prime" newline sif cpuis("MKL82Z*") bitfld.long 0x00 24. " DPARRN ,Asserted after POR and after every 50K blocks processed by AESA and DESA" "Not asserted,Asserted" newline endif newline rbitfld.long 0x00 20. " EI ,Error Interrupt" "Not error,Error" eventfld.long 0x00 16. " DI ,Done Interrupt asserted" "Not asserted,Asserted" newline sif cpuis("MKL82Z*") bitfld.long 0x00 7. " MB ,MDHA Busy" "Idle,Busy" newline endif rbitfld.long 0x00 6. " PB ,PKHA Busy" "Idle,Busy" newline rbitfld.long 0x00 2. " DB ,DESA Busy" "Idle,Busy" rbitfld.long 0x00 1. " AB ,AESA Busy" "Idle,Busy" newline rgroup.long 0x4C++0x03 line.long 0x00 "LTC0_ESTA,LTC Error Status" bitfld.long 0x00 8.--11. " CL1 ,algorithms" "LTC General Error,AES,DES,,,,,,Public Key,?..." bitfld.long 0x00 0.--3. " ERRID1 ,Error ID 1" ",Mode,Data size,Key size,PKHA A register size,PKHA B register size,Data arrived out of sequence,PKHA divide by zero,PKHA modulus even,DES key parity,ICV check failed,Internal hardware failure,CCM AAD size,,,Invalid crypto engine selected" group.long 0x58++0x03 line.long 0x00 "LTC0_AADSZ,LTC AAD Size" bitfld.long 0x00 31. " AL ,AAD Last" "Not last,Last" bitfld.long 0x00 0.--3. " AADSZ ,AAD size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif (!(cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))) group.long 0x60++0x03 line.long 0x00 "LTC0_IVSZ,LTC IV Size" bitfld.long 0x00 31. " IL ,IV Last" "Not last,Last" bitfld.long 0x00 0.--3. " IVSZ ,IV size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" wgroup.long 0x68++0x03 line.long 0x00 "LTC0_DPAMS,LTC DPA Mask Seed" group.long 0x80++0x03 line.long 0x00 "LTC0_PKASZ,LTC PKHA A Size" hexmask.long.word 0x00 0.--8. 1. " PKASZ ,PKHA A Size" group.long 0x88++0x03 line.long 0x00 "LTC0_PKBSZ,LTC PKHA B Size" hexmask.long.word 0x00 0.--8. 1. " PKBSZ ,PKHA B Size" group.long 0x90++0x03 line.long 0x00 "LTC0_PKNSZ,LTC PKHA N Size" hexmask.long.word 0x00 0.--8. 1. " PKNSZ ,PKHA N Size" group.long 0x98++0x03 line.long 0x00 "LTC0_PKESZ,LTC PKHA E Size" hexmask.long.word 0x00 0.--8. 1. " PKESZ ,PKHA E Size" endif newline width 14. sif (!(cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))) group.long 0x100++0x03 line.long 0x00 "LTC0_CTX_0,LTC Context" group.long 0x104++0x03 line.long 0x00 "LTC0_CTX_1,LTC Context" group.long 0x108++0x03 line.long 0x00 "LTC0_CTX_2,LTC Context" group.long 0x10C++0x03 line.long 0x00 "LTC0_CTX_3,LTC Context" group.long 0x110++0x03 line.long 0x00 "LTC0_CTX_4,LTC Context" group.long 0x114++0x03 line.long 0x00 "LTC0_CTX_5,LTC Context" group.long 0x118++0x03 line.long 0x00 "LTC0_CTX_6,LTC Context" group.long 0x11C++0x03 line.long 0x00 "LTC0_CTX_7,LTC Context" group.long 0x120++0x03 line.long 0x00 "LTC0_CTX_8,LTC Context" group.long 0x124++0x03 line.long 0x00 "LTC0_CTX_9,LTC Context" group.long 0x128++0x03 line.long 0x00 "LTC0_CTX_10,LTC Context" group.long 0x12C++0x03 line.long 0x00 "LTC0_CTX_11,LTC Context" group.long 0x130++0x03 line.long 0x00 "LTC0_CTX_12,LTC Context" group.long 0x134++0x03 line.long 0x00 "LTC0_CTX_13,LTC Context" group.long 0x138++0x03 line.long 0x00 "LTC0_CTX_14,LTC Context" group.long 0x13C++0x03 line.long 0x00 "LTC0_CTX_15,LTC Context" else group.long 0x100++0x03 line.long 0x00 "LTC0_CTX_0,LTC Context" group.long 0x104++0x03 line.long 0x00 "LTC0_CTX_1,LTC Context" group.long 0x108++0x03 line.long 0x00 "LTC0_CTX_2,LTC Context" group.long 0x10C++0x03 line.long 0x00 "LTC0_CTX_3,LTC Context" group.long 0x110++0x03 line.long 0x00 "LTC0_CTX_4,LTC Context" group.long 0x114++0x03 line.long 0x00 "LTC0_CTX_5,LTC Context" group.long 0x118++0x03 line.long 0x00 "LTC0_CTX_6,LTC Context" group.long 0x11C++0x03 line.long 0x00 "LTC0_CTX_7,LTC Context" group.long 0x120++0x03 line.long 0x00 "LTC0_CTX_8,LTC Context" group.long 0x124++0x03 line.long 0x00 "LTC0_CTX_9,LTC Context" group.long 0x128++0x03 line.long 0x00 "LTC0_CTX_10,LTC Context" group.long 0x12C++0x03 line.long 0x00 "LTC0_CTX_11,LTC Context" group.long 0x130++0x03 line.long 0x00 "LTC0_CTX_12,LTC Context" group.long 0x134++0x03 line.long 0x00 "LTC0_CTX_13,LTC Context" endif group.long 0x200++0x1F line.long 0x00 "LTC0_KEY_0,LTC Keys" line.long 0x04 "LTC0_KEY_1,LTC Keys" line.long 0x08 "LTC0_KEY_2,LTC Keys" line.long 0x0C "LTC0_KEY_3,LTC Keys" sif (!(cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))) line.long 0x10 "LTC0_KEY_4,LTC Keys" line.long 0x14 "LTC0_KEY_5,LTC Keys" line.long 0x18 "LTC0_KEY_6,LTC Keys" line.long 0x1C "LTC0_KEY_7,LTC Keys" endif sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")||cpuis("MKL82Z*")) rgroup.long 0x4F0++0x07 line.long 0x00 "LTC0_VID1,LTC Version ID" hexmask.long.word 0x00 16.--31. 1. " IP_ID ,ID" hexmask.long.byte 0x00 8.--15. 1. " MAJ_REV ,Major revision number" hexmask.long.byte 0x00 0.--7. 1. " MIN_REV ,Minor revision number" line.long 0x04 "LTC0_VID2,LTC Version ID 2" hexmask.long.byte 0x00 8.--15. 1. " ARCH_ERA ,Architectural ERA" hexmask.long.byte 0x00 0.--7. 1. " ECO_REV ,ECO Revision Number" endif sif (!(cpuis("MKW40Z*")||cpuis("MKW30Z*")||cpuis("MKW20Z*"))) rgroup.long 0x4F8++0x03 line.long 0x00 "LTC0_CHAVID,LTC CHA Version ID" sif cpuis("MKL82Z*") bitfld.long 0x00 28.--31. " MDHAVID , MDHA Hashing Version ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " MDHAREV ,MDHA Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.long 0x00 20.--23. " PKHAVID ,PK Version ID" "32 bit,64 bit,128 bit,16 bit,?..." bitfld.long 0x00 16.--19. " PKHAREV ,PK Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DESVID ,DES Version ID(0x0)" "High-performance,Low-performance,?..." bitfld.long 0x00 8.--11. " DESREV ,DES Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. " AESVID ,AES Version ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " AESREV ,AES Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif rgroup.long 0x7C0++0x03 line.long 0x00 "LTC0_FIFOSTA,LTC FIFO Status" bitfld.long 0x00 31. " OFF ,Output FIFO Full" "Not Full,Full" hexmask.long.byte 0x00 16.--22. 1. " OFL ,Output FIFO Level" bitfld.long 0x00 15. " IFF ,Input FIFO Full" "Not full,Full" hexmask.long.byte 0x00 0.--6. 1. " IFL ,Input FIFO Level" wgroup.long 0x7E0++0x03 line.long 0x00 "LTC0_IFIFO,LTC Input Data FIFO" rgroup.long 0x7F0++0x03 line.long 0x00 "LTC0_OFIFO,LTC Output Data FIFO" sif (!(cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*"))) group.long 0x800++0x03 line.long 0x00 "LTC0_PKA0_0,LTC PKHA A0" group.long 0x804++0x03 line.long 0x00 "LTC0_PKA0_1,LTC PKHA A0" group.long 0x808++0x03 line.long 0x00 "LTC0_PKA0_2,LTC PKHA A0" group.long 0x80C++0x03 line.long 0x00 "LTC0_PKA0_3,LTC PKHA A0" group.long 0x810++0x03 line.long 0x00 "LTC0_PKA0_4,LTC PKHA A0" group.long 0x814++0x03 line.long 0x00 "LTC0_PKA0_5,LTC PKHA A0" group.long 0x818++0x03 line.long 0x00 "LTC0_PKA0_6,LTC PKHA A0" group.long 0x81C++0x03 line.long 0x00 "LTC0_PKA0_7,LTC PKHA A0" group.long 0x820++0x03 line.long 0x00 "LTC0_PKA0_8,LTC PKHA A0" group.long 0x824++0x03 line.long 0x00 "LTC0_PKA0_9,LTC PKHA A0" group.long 0x828++0x03 line.long 0x00 "LTC0_PKA0_10,LTC PKHA A0" group.long 0x82C++0x03 line.long 0x00 "LTC0_PKA0_11,LTC PKHA A0" group.long 0x830++0x03 line.long 0x00 "LTC0_PKA0_12,LTC PKHA A0" group.long 0x834++0x03 line.long 0x00 "LTC0_PKA0_13,LTC PKHA A0" group.long 0x838++0x03 line.long 0x00 "LTC0_PKA0_14,LTC PKHA A0" group.long 0x83C++0x03 line.long 0x00 "LTC0_PKA0_15,LTC PKHA A0" group.long 0x840++0x03 line.long 0x00 "LTC0_PKA1_0,LTC PKHA A1" group.long 0x844++0x03 line.long 0x00 "LTC0_PKA1_1,LTC PKHA A1" group.long 0x848++0x03 line.long 0x00 "LTC0_PKA1_2,LTC PKHA A1" group.long 0x84C++0x03 line.long 0x00 "LTC0_PKA1_3,LTC PKHA A1" group.long 0x850++0x03 line.long 0x00 "LTC0_PKA1_4,LTC PKHA A1" group.long 0x854++0x03 line.long 0x00 "LTC0_PKA1_5,LTC PKHA A1" group.long 0x858++0x03 line.long 0x00 "LTC0_PKA1_6,LTC PKHA A1" group.long 0x85C++0x03 line.long 0x00 "LTC0_PKA1_7,LTC PKHA A1" group.long 0x860++0x03 line.long 0x00 "LTC0_PKA1_8,LTC PKHA A1" group.long 0x864++0x03 line.long 0x00 "LTC0_PKA1_9,LTC PKHA A1" group.long 0x868++0x03 line.long 0x00 "LTC0_PKA1_10,LTC PKHA A1" group.long 0x86C++0x03 line.long 0x00 "LTC0_PKA1_11,LTC PKHA A1" group.long 0x870++0x03 line.long 0x00 "LTC0_PKA1_12,LTC PKHA A1" group.long 0x874++0x03 line.long 0x00 "LTC0_PKA1_13,LTC PKHA A1" group.long 0x878++0x03 line.long 0x00 "LTC0_PKA1_14,LTC PKHA A1" group.long 0x87C++0x03 line.long 0x00 "LTC0_PKA1_15,LTC PKHA A1" group.long 0x880++0x03 line.long 0x00 "LTC0_PKA2_0,LTC PKHA A2" group.long 0x884++0x03 line.long 0x00 "LTC0_PKA2_1,LTC PKHA A2" group.long 0x888++0x03 line.long 0x00 "LTC0_PKA2_2,LTC PKHA A2" group.long 0x88C++0x03 line.long 0x00 "LTC0_PKA2_3,LTC PKHA A2" group.long 0x890++0x03 line.long 0x00 "LTC0_PKA2_4,LTC PKHA A2" group.long 0x894++0x03 line.long 0x00 "LTC0_PKA2_5,LTC PKHA A2" group.long 0x898++0x03 line.long 0x00 "LTC0_PKA2_6,LTC PKHA A2" group.long 0x89C++0x03 line.long 0x00 "LTC0_PKA2_7,LTC PKHA A2" group.long 0x8A0++0x03 line.long 0x00 "LTC0_PKA2_8,LTC PKHA A2" group.long 0x8A4++0x03 line.long 0x00 "LTC0_PKA2_9,LTC PKHA A2" group.long 0x8A8++0x03 line.long 0x00 "LTC0_PKA2_10,LTC PKHA A2" group.long 0x8AC++0x03 line.long 0x00 "LTC0_PKA2_11,LTC PKHA A2" group.long 0x8B0++0x03 line.long 0x00 "LTC0_PKA2_12,LTC PKHA A2" group.long 0x8B4++0x03 line.long 0x00 "LTC0_PKA2_13,LTC PKHA A2" group.long 0x8B8++0x03 line.long 0x00 "LTC0_PKA2_14,LTC PKHA A2" group.long 0x8BC++0x03 line.long 0x00 "LTC0_PKA2_15,LTC PKHA A2" group.long 0x8C0++0x03 line.long 0x00 "LTC0_PKA3_0,LTC PKHA A3" group.long 0x8C4++0x03 line.long 0x00 "LTC0_PKA3_1,LTC PKHA A3" group.long 0x8C8++0x03 line.long 0x00 "LTC0_PKA3_2,LTC PKHA A3" group.long 0x8CC++0x03 line.long 0x00 "LTC0_PKA3_3,LTC PKHA A3" group.long 0x8D0++0x03 line.long 0x00 "LTC0_PKA3_4,LTC PKHA A3" group.long 0x8D4++0x03 line.long 0x00 "LTC0_PKA3_5,LTC PKHA A3" group.long 0x8D8++0x03 line.long 0x00 "LTC0_PKA3_6,LTC PKHA A3" group.long 0x8DC++0x03 line.long 0x00 "LTC0_PKA3_7,LTC PKHA A3" group.long 0x8E0++0x03 line.long 0x00 "LTC0_PKA3_8,LTC PKHA A3" group.long 0x8E4++0x03 line.long 0x00 "LTC0_PKA3_9,LTC PKHA A3" group.long 0x8E8++0x03 line.long 0x00 "LTC0_PKA3_10,LTC PKHA A3" group.long 0x8EC++0x03 line.long 0x00 "LTC0_PKA3_11,LTC PKHA A3" group.long 0x8F0++0x03 line.long 0x00 "LTC0_PKA3_12,LTC PKHA A3" group.long 0x8F4++0x03 line.long 0x00 "LTC0_PKA3_13,LTC PKHA A3" group.long 0x8F8++0x03 line.long 0x00 "LTC0_PKA3_14,LTC PKHA A3" group.long 0x8FC++0x03 line.long 0x00 "LTC0_PKA3_15,LTC PKHA A3" group.long 0xA00++0x03 line.long 0x00 "LTC0_PKB0_0,LTC PKHA B0" group.long 0xA04++0x03 line.long 0x00 "LTC0_PKB0_1,LTC PKHA B0" group.long 0xA08++0x03 line.long 0x00 "LTC0_PKB0_2,LTC PKHA B0" group.long 0xA0C++0x03 line.long 0x00 "LTC0_PKB0_3,LTC PKHA B0" group.long 0xA10++0x03 line.long 0x00 "LTC0_PKB0_4,LTC PKHA B0" group.long 0xA14++0x03 line.long 0x00 "LTC0_PKB0_5,LTC PKHA B0" group.long 0xA18++0x03 line.long 0x00 "LTC0_PKB0_6,LTC PKHA B0" group.long 0xA1C++0x03 line.long 0x00 "LTC0_PKB0_7,LTC PKHA B0" group.long 0xA20++0x03 line.long 0x00 "LTC0_PKB0_8,LTC PKHA B0" group.long 0xA24++0x03 line.long 0x00 "LTC0_PKB0_9,LTC PKHA B0" group.long 0xA28++0x03 line.long 0x00 "LTC0_PKB0_10,LTC PKHA B0" group.long 0xA2C++0x03 line.long 0x00 "LTC0_PKB0_11,LTC PKHA B0" group.long 0xA30++0x03 line.long 0x00 "LTC0_PKB0_12,LTC PKHA B0" group.long 0xA34++0x03 line.long 0x00 "LTC0_PKB0_13,LTC PKHA B0" group.long 0xA38++0x03 line.long 0x00 "LTC0_PKB0_14,LTC PKHA B0" group.long 0xA3C++0x03 line.long 0x00 "LTC0_PKB0_15,LTC PKHA B0" group.long 0xA40++0x03 line.long 0x00 "LTC0_PKB1_0,LTC PKHA B1" group.long 0xA44++0x03 line.long 0x00 "LTC0_PKB1_1,LTC PKHA B1" group.long 0xA48++0x03 line.long 0x00 "LTC0_PKB1_2,LTC PKHA B1" group.long 0xA4C++0x03 line.long 0x00 "LTC0_PKB1_3,LTC PKHA B1" group.long 0xA50++0x03 line.long 0x00 "LTC0_PKB1_4,LTC PKHA B1" group.long 0xA54++0x03 line.long 0x00 "LTC0_PKB1_5,LTC PKHA B1" group.long 0xA58++0x03 line.long 0x00 "LTC0_PKB1_6,LTC PKHA B1" group.long 0xA5C++0x03 line.long 0x00 "LTC0_PKB1_7,LTC PKHA B1" group.long 0xA60++0x03 line.long 0x00 "LTC0_PKB1_8,LTC PKHA B1" group.long 0xA64++0x03 line.long 0x00 "LTC0_PKB1_9,LTC PKHA B1" group.long 0xA68++0x03 line.long 0x00 "LTC0_PKB1_10,LTC PKHA B1" group.long 0xA6C++0x03 line.long 0x00 "LTC0_PKB1_11,LTC PKHA B1" group.long 0xA70++0x03 line.long 0x00 "LTC0_PKB1_12,LTC PKHA B1" group.long 0xA74++0x03 line.long 0x00 "LTC0_PKB1_13,LTC PKHA B1" group.long 0xA78++0x03 line.long 0x00 "LTC0_PKB1_14,LTC PKHA B1" group.long 0xA7C++0x03 line.long 0x00 "LTC0_PKB1_15,LTC PKHA B1" group.long 0xA80++0x03 line.long 0x00 "LTC0_PKB2_0,LTC PKHA B2" group.long 0xA84++0x03 line.long 0x00 "LTC0_PKB2_1,LTC PKHA B2" group.long 0xA88++0x03 line.long 0x00 "LTC0_PKB2_2,LTC PKHA B2" group.long 0xA8C++0x03 line.long 0x00 "LTC0_PKB2_3,LTC PKHA B2" group.long 0xA90++0x03 line.long 0x00 "LTC0_PKB2_4,LTC PKHA B2" group.long 0xA94++0x03 line.long 0x00 "LTC0_PKB2_5,LTC PKHA B2" group.long 0xA98++0x03 line.long 0x00 "LTC0_PKB2_6,LTC PKHA B2" group.long 0xA9C++0x03 line.long 0x00 "LTC0_PKB2_7,LTC PKHA B2" group.long 0xAA0++0x03 line.long 0x00 "LTC0_PKB2_8,LTC PKHA B2" group.long 0xAA4++0x03 line.long 0x00 "LTC0_PKB2_9,LTC PKHA B2" group.long 0xAA8++0x03 line.long 0x00 "LTC0_PKB2_10,LTC PKHA B2" group.long 0xAAC++0x03 line.long 0x00 "LTC0_PKB2_11,LTC PKHA B2" group.long 0xAB0++0x03 line.long 0x00 "LTC0_PKB2_12,LTC PKHA B2" group.long 0xAB4++0x03 line.long 0x00 "LTC0_PKB2_13,LTC PKHA B2" group.long 0xAB8++0x03 line.long 0x00 "LTC0_PKB2_14,LTC PKHA B2" group.long 0xABC++0x03 line.long 0x00 "LTC0_PKB2_15,LTC PKHA B2" group.long 0xAC0++0x03 line.long 0x00 "LTC0_PKB3_0,LTC PKHA B3" group.long 0xAC4++0x03 line.long 0x00 "LTC0_PKB3_1,LTC PKHA B3" group.long 0xAC8++0x03 line.long 0x00 "LTC0_PKB3_2,LTC PKHA B3" group.long 0xACC++0x03 line.long 0x00 "LTC0_PKB3_3,LTC PKHA B3" group.long 0xAD0++0x03 line.long 0x00 "LTC0_PKB3_4,LTC PKHA B3" group.long 0xAD4++0x03 line.long 0x00 "LTC0_PKB3_5,LTC PKHA B3" group.long 0xAD8++0x03 line.long 0x00 "LTC0_PKB3_6,LTC PKHA B3" group.long 0xADC++0x03 line.long 0x00 "LTC0_PKB3_7,LTC PKHA B3" group.long 0xAE0++0x03 line.long 0x00 "LTC0_PKB3_8,LTC PKHA B3" group.long 0xAE4++0x03 line.long 0x00 "LTC0_PKB3_9,LTC PKHA B3" group.long 0xAE8++0x03 line.long 0x00 "LTC0_PKB3_10,LTC PKHA B3" group.long 0xAEC++0x03 line.long 0x00 "LTC0_PKB3_11,LTC PKHA B3" group.long 0xAF0++0x03 line.long 0x00 "LTC0_PKB3_12,LTC PKHA B3" group.long 0xAF4++0x03 line.long 0x00 "LTC0_PKB3_13,LTC PKHA B3" group.long 0xAF8++0x03 line.long 0x00 "LTC0_PKB3_14,LTC PKHA B3" group.long 0xAFC++0x03 line.long 0x00 "LTC0_PKB3_15,LTC PKHA B3" group.long 0xC00++0x03 line.long 0x00 "LTC0_PKN0_0,LTC PKHA N0" group.long 0xC04++0x03 line.long 0x00 "LTC0_PKN0_1,LTC PKHA N0" group.long 0xC08++0x03 line.long 0x00 "LTC0_PKN0_2,LTC PKHA N0" group.long 0xC0C++0x03 line.long 0x00 "LTC0_PKN0_3,LTC PKHA N0" group.long 0xC10++0x03 line.long 0x00 "LTC0_PKN0_4,LTC PKHA N0" group.long 0xC14++0x03 line.long 0x00 "LTC0_PKN0_5,LTC PKHA N0" group.long 0xC18++0x03 line.long 0x00 "LTC0_PKN0_6,LTC PKHA N0" group.long 0xC1C++0x03 line.long 0x00 "LTC0_PKN0_7,LTC PKHA N0" group.long 0xC20++0x03 line.long 0x00 "LTC0_PKN0_8,LTC PKHA N0" group.long 0xC24++0x03 line.long 0x00 "LTC0_PKN0_9,LTC PKHA N0" group.long 0xC28++0x03 line.long 0x00 "LTC0_PKN0_10,LTC PKHA N0" group.long 0xC2C++0x03 line.long 0x00 "LTC0_PKN0_11,LTC PKHA N0" group.long 0xC30++0x03 line.long 0x00 "LTC0_PKN0_12,LTC PKHA N0" group.long 0xC34++0x03 line.long 0x00 "LTC0_PKN0_13,LTC PKHA N0" group.long 0xC38++0x03 line.long 0x00 "LTC0_PKN0_14,LTC PKHA N0" group.long 0xC3C++0x03 line.long 0x00 "LTC0_PKN0_15,LTC PKHA N0" group.long 0xC40++0x03 line.long 0x00 "LTC0_PKN1_0,LTC PKHA N1" group.long 0xC44++0x03 line.long 0x00 "LTC0_PKN1_1,LTC PKHA N1" group.long 0xC48++0x03 line.long 0x00 "LTC0_PKN1_2,LTC PKHA N1" group.long 0xC4C++0x03 line.long 0x00 "LTC0_PKN1_3,LTC PKHA N1" group.long 0xC50++0x03 line.long 0x00 "LTC0_PKN1_4,LTC PKHA N1" group.long 0xC54++0x03 line.long 0x00 "LTC0_PKN1_5,LTC PKHA N1" group.long 0xC58++0x03 line.long 0x00 "LTC0_PKN1_6,LTC PKHA N1" group.long 0xC5C++0x03 line.long 0x00 "LTC0_PKN1_7,LTC PKHA N1" group.long 0xC60++0x03 line.long 0x00 "LTC0_PKN1_8,LTC PKHA N1" group.long 0xC64++0x03 line.long 0x00 "LTC0_PKN1_9,LTC PKHA N1" group.long 0xC68++0x03 line.long 0x00 "LTC0_PKN1_10,LTC PKHA N1" group.long 0xC6C++0x03 line.long 0x00 "LTC0_PKN1_11,LTC PKHA N1" group.long 0xC70++0x03 line.long 0x00 "LTC0_PKN1_12,LTC PKHA N1" group.long 0xC74++0x03 line.long 0x00 "LTC0_PKN1_13,LTC PKHA N1" group.long 0xC78++0x03 line.long 0x00 "LTC0_PKN1_14,LTC PKHA N1" group.long 0xC7C++0x03 line.long 0x00 "LTC0_PKN1_15,LTC PKHA N1" group.long 0xC80++0x03 line.long 0x00 "LTC0_PKN2_0,LTC PKHA N2" group.long 0xC84++0x03 line.long 0x00 "LTC0_PKN2_1,LTC PKHA N2" group.long 0xC88++0x03 line.long 0x00 "LTC0_PKN2_2,LTC PKHA N2" group.long 0xC8C++0x03 line.long 0x00 "LTC0_PKN2_3,LTC PKHA N2" group.long 0xC90++0x03 line.long 0x00 "LTC0_PKN2_4,LTC PKHA N2" group.long 0xC94++0x03 line.long 0x00 "LTC0_PKN2_5,LTC PKHA N2" group.long 0xC98++0x03 line.long 0x00 "LTC0_PKN2_6,LTC PKHA N2" group.long 0xC9C++0x03 line.long 0x00 "LTC0_PKN2_7,LTC PKHA N2" group.long 0xCA0++0x03 line.long 0x00 "LTC0_PKN2_8,LTC PKHA N2" group.long 0xCA4++0x03 line.long 0x00 "LTC0_PKN2_9,LTC PKHA N2" group.long 0xCA8++0x03 line.long 0x00 "LTC0_PKN2_10,LTC PKHA N2" group.long 0xCAC++0x03 line.long 0x00 "LTC0_PKN2_11,LTC PKHA N2" group.long 0xCB0++0x03 line.long 0x00 "LTC0_PKN2_12,LTC PKHA N2" group.long 0xCB4++0x03 line.long 0x00 "LTC0_PKN2_13,LTC PKHA N2" group.long 0xCB8++0x03 line.long 0x00 "LTC0_PKN2_14,LTC PKHA N2" group.long 0xCBC++0x03 line.long 0x00 "LTC0_PKN2_15,LTC PKHA N2" group.long 0xCC0++0x03 line.long 0x00 "LTC0_PKN3_0,LTC PKHA N3" group.long 0xCC4++0x03 line.long 0x00 "LTC0_PKN3_1,LTC PKHA N3" group.long 0xCC8++0x03 line.long 0x00 "LTC0_PKN3_2,LTC PKHA N3" group.long 0xCCC++0x03 line.long 0x00 "LTC0_PKN3_3,LTC PKHA N3" group.long 0xCD0++0x03 line.long 0x00 "LTC0_PKN3_4,LTC PKHA N3" group.long 0xCD4++0x03 line.long 0x00 "LTC0_PKN3_5,LTC PKHA N3" group.long 0xCD8++0x03 line.long 0x00 "LTC0_PKN3_6,LTC PKHA N3" group.long 0xCDC++0x03 line.long 0x00 "LTC0_PKN3_7,LTC PKHA N3" group.long 0xCE0++0x03 line.long 0x00 "LTC0_PKN3_8,LTC PKHA N3" group.long 0xCE4++0x03 line.long 0x00 "LTC0_PKN3_9,LTC PKHA N3" group.long 0xCE8++0x03 line.long 0x00 "LTC0_PKN3_10,LTC PKHA N3" group.long 0xCEC++0x03 line.long 0x00 "LTC0_PKN3_11,LTC PKHA N3" group.long 0xCF0++0x03 line.long 0x00 "LTC0_PKN3_12,LTC PKHA N3" group.long 0xCF4++0x03 line.long 0x00 "LTC0_PKN3_13,LTC PKHA N3" group.long 0xCF8++0x03 line.long 0x00 "LTC0_PKN3_14,LTC PKHA N3" group.long 0xCFC++0x03 line.long 0x00 "LTC0_PKN3_15,LTC PKHA N3" wgroup.long 0xE00++0x03 line.long 0x00 "LTC0_PKE_0,LTC PKHA E" wgroup.long 0xE04++0x03 line.long 0x00 "LTC0_PKE_1,LTC PKHA E" wgroup.long 0xE08++0x03 line.long 0x00 "LTC0_PKE_2,LTC PKHA E" wgroup.long 0xE0C++0x03 line.long 0x00 "LTC0_PKE_3,LTC PKHA E" wgroup.long 0xE10++0x03 line.long 0x00 "LTC0_PKE_4,LTC PKHA E" wgroup.long 0xE14++0x03 line.long 0x00 "LTC0_PKE_5,LTC PKHA E" wgroup.long 0xE18++0x03 line.long 0x00 "LTC0_PKE_6,LTC PKHA E" wgroup.long 0xE1C++0x03 line.long 0x00 "LTC0_PKE_7,LTC PKHA E" wgroup.long 0xE20++0x03 line.long 0x00 "LTC0_PKE_8,LTC PKHA E" wgroup.long 0xE24++0x03 line.long 0x00 "LTC0_PKE_9,LTC PKHA E" wgroup.long 0xE28++0x03 line.long 0x00 "LTC0_PKE_10,LTC PKHA E" wgroup.long 0xE2C++0x03 line.long 0x00 "LTC0_PKE_11,LTC PKHA E" wgroup.long 0xE30++0x03 line.long 0x00 "LTC0_PKE_12,LTC PKHA E" wgroup.long 0xE34++0x03 line.long 0x00 "LTC0_PKE_13,LTC PKHA E" wgroup.long 0xE38++0x03 line.long 0x00 "LTC0_PKE_14,LTC PKHA E" wgroup.long 0xE3C++0x03 line.long 0x00 "LTC0_PKE_15,LTC PKHA E" wgroup.long 0xE40++0x03 line.long 0x00 "LTC0_PKE_16,LTC PKHA E" wgroup.long 0xE44++0x03 line.long 0x00 "LTC0_PKE_17,LTC PKHA E" wgroup.long 0xE48++0x03 line.long 0x00 "LTC0_PKE_18,LTC PKHA E" wgroup.long 0xE4C++0x03 line.long 0x00 "LTC0_PKE_19,LTC PKHA E" wgroup.long 0xE50++0x03 line.long 0x00 "LTC0_PKE_20,LTC PKHA E" wgroup.long 0xE54++0x03 line.long 0x00 "LTC0_PKE_21,LTC PKHA E" wgroup.long 0xE58++0x03 line.long 0x00 "LTC0_PKE_22,LTC PKHA E" wgroup.long 0xE5C++0x03 line.long 0x00 "LTC0_PKE_23,LTC PKHA E" wgroup.long 0xE60++0x03 line.long 0x00 "LTC0_PKE_24,LTC PKHA E" wgroup.long 0xE64++0x03 line.long 0x00 "LTC0_PKE_25,LTC PKHA E" wgroup.long 0xE68++0x03 line.long 0x00 "LTC0_PKE_26,LTC PKHA E" wgroup.long 0xE6C++0x03 line.long 0x00 "LTC0_PKE_27,LTC PKHA E" wgroup.long 0xE70++0x03 line.long 0x00 "LTC0_PKE_28,LTC PKHA E" wgroup.long 0xE74++0x03 line.long 0x00 "LTC0_PKE_29,LTC PKHA E" wgroup.long 0xE78++0x03 line.long 0x00 "LTC0_PKE_30,LTC PKHA E" wgroup.long 0xE7C++0x03 line.long 0x00 "LTC0_PKE_31,LTC PKHA E" wgroup.long 0xE80++0x03 line.long 0x00 "LTC0_PKE_32,LTC PKHA E" wgroup.long 0xE84++0x03 line.long 0x00 "LTC0_PKE_33,LTC PKHA E" wgroup.long 0xE88++0x03 line.long 0x00 "LTC0_PKE_34,LTC PKHA E" wgroup.long 0xE8C++0x03 line.long 0x00 "LTC0_PKE_35,LTC PKHA E" wgroup.long 0xE90++0x03 line.long 0x00 "LTC0_PKE_36,LTC PKHA E" wgroup.long 0xE94++0x03 line.long 0x00 "LTC0_PKE_37,LTC PKHA E" wgroup.long 0xE98++0x03 line.long 0x00 "LTC0_PKE_38,LTC PKHA E" wgroup.long 0xE9C++0x03 line.long 0x00 "LTC0_PKE_39,LTC PKHA E" wgroup.long 0xEA0++0x03 line.long 0x00 "LTC0_PKE_40,LTC PKHA E" wgroup.long 0xEA4++0x03 line.long 0x00 "LTC0_PKE_41,LTC PKHA E" wgroup.long 0xEA8++0x03 line.long 0x00 "LTC0_PKE_42,LTC PKHA E" wgroup.long 0xEAC++0x03 line.long 0x00 "LTC0_PKE_43,LTC PKHA E" wgroup.long 0xEB0++0x03 line.long 0x00 "LTC0_PKE_44,LTC PKHA E" wgroup.long 0xEB4++0x03 line.long 0x00 "LTC0_PKE_45,LTC PKHA E" wgroup.long 0xEB8++0x03 line.long 0x00 "LTC0_PKE_46,LTC PKHA E" wgroup.long 0xEBC++0x03 line.long 0x00 "LTC0_PKE_47,LTC PKHA E" wgroup.long 0xEC0++0x03 line.long 0x00 "LTC0_PKE_48,LTC PKHA E" wgroup.long 0xEC4++0x03 line.long 0x00 "LTC0_PKE_49,LTC PKHA E" wgroup.long 0xEC8++0x03 line.long 0x00 "LTC0_PKE_50,LTC PKHA E" wgroup.long 0xECC++0x03 line.long 0x00 "LTC0_PKE_51,LTC PKHA E" wgroup.long 0xED0++0x03 line.long 0x00 "LTC0_PKE_52,LTC PKHA E" wgroup.long 0xED4++0x03 line.long 0x00 "LTC0_PKE_53,LTC PKHA E" wgroup.long 0xED8++0x03 line.long 0x00 "LTC0_PKE_54,LTC PKHA E" wgroup.long 0xEDC++0x03 line.long 0x00 "LTC0_PKE_55,LTC PKHA E" wgroup.long 0xEE0++0x03 line.long 0x00 "LTC0_PKE_56,LTC PKHA E" wgroup.long 0xEE4++0x03 line.long 0x00 "LTC0_PKE_57,LTC PKHA E" wgroup.long 0xEE8++0x03 line.long 0x00 "LTC0_PKE_58,LTC PKHA E" wgroup.long 0xEEC++0x03 line.long 0x00 "LTC0_PKE_59,LTC PKHA E" wgroup.long 0xEF0++0x03 line.long 0x00 "LTC0_PKE_60,LTC PKHA E" wgroup.long 0xEF4++0x03 line.long 0x00 "LTC0_PKE_61,LTC PKHA E" wgroup.long 0xEF8++0x03 line.long 0x00 "LTC0_PKE_62,LTC PKHA E" wgroup.long 0xEFC++0x03 line.long 0x00 "LTC0_PKE_63,LTC PKHA E" elif (cpuis("MKW40Z*")||cpuis("MKW30Z*")||cpuis("MKW20Z*")) rgroup.long 0x8F0++0x03 line.long 0x00 "LTC0_VID1,LTC Version ID" hexmask.long.word 0x00 16.--31. 1. " IP_ID ,ID" hexmask.long.byte 0x00 8.--15. 1. " MAJ_REV ,Major revision number" hexmask.long.byte 0x00 0.--7. 1. " MIN_REV ,Minor revision number" rgroup.long 0x8F8++0x03 line.long 0x00 "LTC0_CHAVID,LTC CHA Version ID" bitfld.long 0x00 4.--7. " AESVID ,AES Version ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " AESREV ,AES Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif width 0x0B tree.end endif tree "ADC (Analog-to-Digital Converter)" base ad:0x4003B000 width 11. if (((per.l(ad:0x4003B000+0x0))&0x20)==0x00) group.long 0x0++0x03 line.long 0x00 "SC1A,ADC Status and Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "ADC0_DP0,ADC0_DP1,PGA0_DP,ADC0_DP3,,,,,ADC0_SE8,ADC0_SE9,,,ADC0_SE12,ADC0_SE13,ADC0_SE14,ADC0_SE15,,ADC0_SE17,ADC0_SE18,ADC0_DM0,ADC0_DM1,,,12-bit DAC0,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "ADC0_DP0,ADC0_DP1,PGA0_DP,ADC0_DP3,,,,,ADC0_SE8,ADC0_SE9,,,ADC0_SE12,ADC0_SE13,ADC0_SE14,ADC0_SE15,,ADC0_SE17,ADC0_SE18,ADC0_DM0,ADC0_DM1,,,12-bit DAC0,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "ADC0_DP0,ADC0_DP1,PGA0_DP,ADC0_DP3,,,,,ADC0_SE8,ADC0_SE9,ADC0_SE10,ADC0_SE11,ADC0_SE12,ADC0_SE13,ADC0_SE14,ADC0_SE15,ADC0_SE16,ADC0_SE17,ADC0_SE18,ADC0_DM0,ADC0_DM1,,,12-bit DAC0,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("MK60DN512VMC10R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "ADC0_DP0,ADC0_DP1,PGA0_DP,ADC0_DP3,,,,,ADC0_SE8,ADC0_SE9,,,ADC0_SE12,ADC0_SE13,ADC0_SE14,ADC0_SE15,,ADC0_SE17,ADC0_SE18,ADC0_DM0,ADC0_DM1,ADC0_SE21,ADC0_SE22,12-bit DAC0/SE23,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("KK60DN512ZCAB10R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "ADC0_DP0,ADC0_DP1,PGA0_DP,ADC0_DP3,,,,,ADC0_SE8,ADC0_SE9,,,ADC0_SE12,ADC0_SE13,ADC0_SE14,ADC0_SE15,,ADC0_SE17,ADC0_SE18,ADC0_DM0,ADC0_DM1,,,12-bit DAC0/ADC0_SE23,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("MK63FN1M0VLQ12R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "ADC0_DP0,ADC0_DP1,ADC0_DP2,ADC0_DP3,,,,,ADC0_SE8,ADC0_SE9,ADC0_SE10,ADC0_SE11,ADC0_SE12,ADC0_SE13,ADC0_SE14,ADC0_SE15,ADC0_SE16,ADC0_SE17,ADC0_SE18,ADC0_DM0,ADC0_DM1,ADC0_SE21,ADC0_SE22,,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("KK60FN1M0VLQ15") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "ADC0_DP0,ADC0_DP1,PGA0_DP,ADC0_DP3,,,,,ADC0_SE8,ADC0_SE9,ADC0_SE10,ADC0_SE11,ADC0_SE12,ADC0_SE13,ADC0_SE14,ADC0_SE15,ADC0_SE16,ADC0_SE17,ADC0_SE18,ADC0_DM0,ADC0_DM1,ADC0_SE21,ADC0_SE22,12-bit DAC0/ADC0_SE23,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "ADC0_DCP0,,,ADC0_DP3,ADC0_SE4a,ADC0_SE5a,ADC0_SE6a,ADC0_SE7a,ADC0_SE8,ADC0_SE9,ADC0_SE10,ADC0_SE11,ADC0_SE12,ADC0_SE13,ADC0_SE14,ADC0_SE15,ADC_SE16,ADC0_SE17,ADC0_SE18,ADC0_DM0,,ADC0_SE21,ADC0_SE22,12-bit DAC0/ADC0_SE23,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("MK66FN2M0VLQ18R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",,,ADC0_DP3,,,,,ADC0_SE8,ADC0_SE9,ADC0_SE10,ADC0_SE11,ADC0_SE12,ADC0_SE13,ADC0_SE14,ADC0_SE15,ADC0_SE16,ADC0_SE17,ADC0_SE18,ADC0_DM0,,ADC0_SE21,ADC0_SE22,12-bit DAC0/ADC0_SE23,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" endif elif cpuis("MK84FN2M0CAU15R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,,AD3,AD4a,AD5a,AD6a,AD7a,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,,AD17,AD18,,AD20,AD21,AD22,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled" elif cpuis("MK8?FN256VR")||cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQR")||cpuis("MK30DX256VLL7R")||cpuis("MK70FN1M0VMJ1R")||cpuis("MK40DRZR10")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60FN1M0VLQ15")||cpuis("MK60DN512ZCAB10R")||cpuis("MK8?FN256V*") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DADP0,DADP1,DADP2,DADP3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,AD16,AD17,AD18,AD19,AD20,AD21,AD22,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled" else newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,AD16,AD17,AD18,AD19,AD20,AD21,AD22,AD23,,,Temp sensor,Bandgap,,,VREFSL,Disabled" endif else group.long 0x0++0x03 line.long 0x00 "SC1A,ADC Status and Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,PGA0_DP/PGA0_DM,DP3/DM3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (Diff),Bandgap (Diff),,VREFH (Diff),,Disabled" elif cpuis("MK63FN1M0VLQ12R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,DP2/DM2,DP3/DM3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (Diff),Bandgap (Diff),,VREFH (Diff),,Disabled" elif cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,,,DP3/DM3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (Diff),Bandgap (Diff),,,,Disabled" elif cpuis("MK66FN2M0VLQ18R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",,,DP3/DM3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (Diff),Bandgap (Diff),,,,Disabled" endif elif cpuis("MK84FN2M0CAU15R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,,AD3,,,,,,,,,,,,,,,,,,,,,Sense bus,,Temp sensor,Bandgap,,-VREFSH,,Disabled" else newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DAD0,DAD1,DAD2,DAD3,,,,,,,,,,,,,,,,,,,,,,,Temp Sensor,Bandgap,,-VREFSH,,Disabled" endif endif if (((per.l(ad:0x4003B000+0x4))&0x20)==0x00) group.long 0x4++0x03 line.long 0x00 "SC1B,ADC Status and Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "ADC0_DP0,ADC0_DP1,PGA0_DP,ADC0_DP3,ADC0_SE4b,ADC0_SE5b,ADC0_SE6b,ADC0_SE7b,ADC0_SE8,ADC0_SE9,,,ADC0_SE12,ADC0_SE13,ADC0_SE14,ADC0_SE15,,ADC0_SE17,ADC0_SE18,ADC0_DM0,ADC0_DM1,,,12-bit DAC0,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "ADC0_DP0,ADC0_DP1,PGA0_DP,ADC0_DP3,ADC0_SE4b,ADC0_SE5b,ADC0_SE6b,ADC0_SE7b,ADC0_SE8,ADC0_SE9,,,ADC0_SE12,ADC0_SE13,ADC0_SE14,ADC0_SE15,,ADC0_SE17,ADC0_SE18,ADC0_DM0,ADC0_DM1,,,12-bit DAC0,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "ADC0_DP0,ADC0_DP1,PGA0_DP,ADC0_DP3,ADC0_SE4b,ADC0_SE5b,ADC0_SE6b,ADC0_SE7b,ADC0_SE8,ADC0_SE9,ADC0_SE10,ADC0_SE11,ADC0_SE12,ADC0_SE13,ADC0_SE14,ADC0_SE15,ADC0_SE16,ADC0_SE17,ADC0_SE18,ADC0_DM0,ADC0_DM1,,,12-bit DAC0,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("MK60DN512VMC10R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "ADC0_DP0,ADC0_DP1,PGA0_DP,ADC0_DP3,ADC0_SE4b,ADC0_SE5b,ADC0_SE6b,ADC0_SE7b,ADC0_SE8,ADC0_SE9,,,ADC0_SE12,ADC0_SE13,ADC0_SE14,ADC0_SE15,,ADC0_SE17,ADC0_SE18,ADC0_DM0,ADC0_DM1,ADC0_SE21,ADC0_SE22,12-bit DAC0/SE23,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("KK60DN512ZCAB10R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "ADC0_DP0,ADC0_DP1,PGA0_DP,ADC0_DP3,ADC0_SE4b,ADC0_SE5b,ADC0_SE6b,ADC0_SE7b,ADC0_SE8,ADC0_SE9,,,ADC0_SE12,ADC0_SE13,ADC0_SE14,ADC0_SE15,,ADC0_SE17,ADC0_SE18,ADC0_DM0,ADC0_DM1,,,12-bit DAC0/ADC0_SE23,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("MK63FN1M0VLQ12R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "ADC0_DP0,ADC0_DP1,ADC0_DP2,ADC0_DP3,ADC0_SE4b,ADC0_SE5b,ADC0_SE6b,ADC0_SE7b,ADC0_SE8,ADC0_SE9,ADC0_SE10,ADC0_SE11,ADC0_SE12,ADC0_SE13,ADC0_SE14,ADC0_SE15,ADC0_SE16,ADC0_SE17,ADC0_SE18,ADC0_DM0,ADC0_DM1,ADC0_SE21,ADC0_SE22,,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("KK60FN1M0VLQ15") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "ADC0_DP0,ADC0_DP1,PGA0_DP,ADC0_DP3,ADC0_SE4b,ADC0_SE5b,ADC0_SE6b,ADC0_SE7b,ADC0_SE8,ADC0_SE9,ADC_SE10,ADC0_SE11,ADC0_SE12,ADC0_SE13,ADC0_SE14,ADC0_SE15,ADC_SE16,ADC0_SE17,ADC0_SE18,ADC0_DM0,ADC0_DM1,ADC0_SE21,ADC0_SE22,12-bit DAC0/ADC0_SE23,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "ADC0_DCP0,,,ADC0_DP3,ADC0_SE4b,ADC0_SE5b,ADC0_SE6b,ADC0_SE7b,ADC0_SE8,ADC0_SE9,ADC_SE10,ADC0_SE11,ADC0_SE12,ADC0_SE13,ADC0_SE14,ADC0_SE15,ADC_SE16,ADC0_SE17,ADC0_SE18,ADC0_DM0,,ADC0_SE21,ADC0_SE22,12-bit DAC0/ADC0_SE23,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("MK66FN2M0VLQ18R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",,,ADC0_DP3,ADC0_SE4b,ADC0_SE5b,ADC0_SE6b,ADC0_SE7b,ADC0_SE8,ADC0_SE9,ADC0_SE10,ADC0_SE11,ADC0_SE12,ADC0_SE13,ADC0_SE14,ADC0_SE15,ADC_SE16,ADC0_SE17,ADC0_SE18,ADC0_DM0,,ADC0_SE21,ADC0_SE22,12-bit DAC0/ADC0_SE23,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" endif elif cpuis("MK84FN2M0CAU15R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,,AD3,AD4a,AD5a,AD6a,AD7a,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,,AD17,AD18,,AD20,AD21,AD22,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled" elif cpuis("MK8?FN256VR")||cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQR")||cpuis("MK30DX256VLL7R")||cpuis("MK70FN1M0VMJ1R")||cpuis("MK40DRZR10")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60FN1M0VLQ15")||cpuis("MK60DN512ZCAB10R")||cpuis("MK8?FN256V*") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DADP0,DADP1,DADP2,DADP3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,AD16,AD17,AD18,AD19,AD20,AD21,AD22,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled" else newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,AD16,AD17,AD18,AD19,AD20,AD21,AD22,AD23,,,Temp sensor,Bandgap,,,VREFSL,Disabled" endif else group.long 0x4++0x03 line.long 0x00 "SC1B,ADC Status and Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,PGA0_DP/PGA0_DM,DP3/DM3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (Diff),Bandgap (Diff),,VREFH (Diff),,Disabled" elif cpuis("MK63FN1M0VLQ12R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,DP2/DM2,DP3/DM3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (Diff),Bandgap (Diff),,VREFH (Diff),,Disabled" elif cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,,,DP3/DM3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (Diff),Bandgap (Diff),,,,Disabled" elif cpuis("MK66FN2M0VLQ18R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",,,DP3/DM3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (Diff),Bandgap (Diff),,,,Disabled" endif elif cpuis("MK84FN2M0CAU15R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,,AD3,,,,,,,,,,,,,,,,,,,,,Sense bus,,Temp sensor,Bandgap,,-VREFSH,,Disabled" else newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DAD0,DAD1,DAD2,DAD3,,,,,,,,,,,,,,,,,,,,,,,Temp Sensor,Bandgap,,-VREFSH,,Disabled" endif endif newline sif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") if (((per.l(ad:0x4003B000))&0x20)==0x00)&&(((per.l(ad:0x4003B000+0x04))&0x20)==0x00) group.long 0x08++0x03 line.long 0x00 "CFG1,ADC Configuration Register 1" bitfld.long 0x00 7. " ADLPC ,Low-power configuration" "Normal,Low-power" bitfld.long 0x00 5.--6. " ADIV ,Clock divide select" "/1,/2,/4,/8" bitfld.long 0x00 4. " ADLSMP ,Sample time configuration" "Short,Long" newline bitfld.long 0x00 2.--3. " MODE ,Conversion mode selection" "Single-ended 8-bit,Single-ended 12-bit,Single-ended 10-bit,Single-ended 16-bit" bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "Bus-clock,Bus-clock/2,ALTCLK,ADACK" else group.long 0x08++0x03 line.long 0x00 "CFG1,ADC Configuration Register 1" bitfld.long 0x00 7. " ADLPC ,Low-power configuration" "Normal,Low-power" bitfld.long 0x00 5.--6. " ADIV ,Clock divide select" "/1,/2,/4,/8" bitfld.long 0x00 4. " ADLSMP ,Sample time configuration" "Short,Long" newline bitfld.long 0x00 2.--3. " MODE ,Conversion mode selection" "Differential 9-bit,Differential 13-bit,Differential 11-bit,Differential 16-bit" bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "Bus-clock,Bus-clock/2,ALTCLK,ADACK" endif else group.long 0x08++0x03 line.long 0x00 "CFG1,ADC Configuration Register 1" bitfld.long 0x00 7. " ADLPC ,Low-power configuration" "Normal,Low-power" bitfld.long 0x00 5.--6. " ADIV ,Clock divide select" "/1,/2,/4,/8" bitfld.long 0x00 4. " ADLSMP ,Sample time configuration" "Short,Long" newline bitfld.long 0x00 2.--3. " MODE ,Conversion mode selection" "Single-ended 8-bit/Diff 9-bit,Single-ended 12-bit/Diff 13-bit,Single-ended 10-bit/Diff 11-bit,Single ended 16-bit/Diff 16-bit" sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256VR")||cpuis("MK8?FN256V*") newline bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "Bus clock,ALTCLK2,ALTCLK,ADACK" else newline bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "Bus-clock,Bus-clock/2,ALTCLK,ADACK" endif endif group.long 0x0C++0x03 line.long 0x00 "CFG2,ADC Configuration Register 2" bitfld.long 0x00 4. " MUXSEL ,ADC Mux select" "ADCA,ADCB" bitfld.long 0x00 3. " ADACKEN ,Asynchronous clock output enable" "Disabled,Enabled" bitfld.long 0x00 2. " ADHSC ,High speed configuration" "Normal,High-Speed" newline bitfld.long 0x00 0.--1. " ADLSTS ,Long sample time select" "24 ADCK cycles,16 ADCK cycles,10 ADCK cycles,6 ADCK cycles" newline sif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") hgroup.long 0x10++0x03 hide.long 0x00 "RA,ADC Data Result Register" in hgroup.long 0x14++0x03 hide.long 0x00 "RB,ADC Data Result Register" in else if (((per.l(ad:0x4003B000))&0x20)==0x00) if (((per.l(ad:0x4003B000+0x08))&0x0C)==0x00) rgroup.long 0x10++0x07 line.long 0x00 "RA,ADC Data Result Register" hexmask.long.byte 0x00 0.--7. 1. " D ,Data result" line.long 0x04 "RB,ADC Data Result Register" hexmask.long.byte 0x04 0.--7. 1. " D ,Data result" elif (((per.l(ad:0x4003B000+0x08))&0x0C)==0x04) rgroup.long 0x10++0x07 line.long 0x00 "RA,ADC Data Result Register" hexmask.long.word 0x00 0.--11. 1. " D ,Data result" line.long 0x04 "RB,ADC Data Result Register" hexmask.long.word 0x04 0.--11. 1. " D ,Data result" elif (((per.l(ad:0x4003B000+0x08))&0x0C)==0x08) rgroup.long 0x10++0x07 line.long 0x00 "RA,ADC Data Result Register" hexmask.long.word 0x00 0.--9. 1. " D ,Data result" line.long 0x04 "RB,ADC Data Result Register" hexmask.long.word 0x04 0.--9. 1. " D ,Data result" else rgroup.long 0x10++0x07 line.long 0x00 "RA,ADC Data Result Register" hexmask.long.word 0x00 0.--15. 1. " D ,Data result" line.long 0x04 "RB,ADC Data Result Register" hexmask.long.word 0x04 0.--15. 1. " D ,Data result" endif else if (((per.l(ad:0x4003B000+0x08))&0x0C)==0x00) rgroup.long 0x10++0x07 line.long 0x00 "RA,ADC Data Result Register" hexmask.long.word 0x00 0.--8. 1. " D ,Data result" line.long 0x04 "RB,ADC Data Result Register" hexmask.long.word 0x04 0.--8. 1. " D ,Data result" elif (((per.l(ad:0x4003B000+0x08))&0x0C)==0x04) rgroup.long 0x10++0x07 line.long 0x00 "RA,ADC Data Result Register" hexmask.long.word 0x00 0.--12. 1. " D ,Data result" line.long 0x04 "RB,ADC Data Result Register" hexmask.long.word 0x04 0.--12. 1. " D ,Data result" elif (((per.l(ad:0x4003B000+0x08))&0x0C)==0x08) rgroup.long 0x10++0x07 line.long 0x00 "RA,ADC Data Result Register" hexmask.long.word 0x00 0.--10. 1. " D ,Data result" line.long 0x04 "RB,ADC Data Result Register" hexmask.long.word 0x04 0.--10. 1. " D ,Data result" else rgroup.long 0x10++0x07 line.long 0x00 "RA,ADC Data Result Register" hexmask.long.word 0x00 0.--15. 1. " D ,Data result" line.long 0x04 "RB,ADC Data Result Register" hexmask.long.word 0x04 0.--15. 1. " D ,Data result" endif endif endif sif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK8?FN256V*") if (((per.l(ad:0x4003B000))&0x20)==0x00) if (((per.l(ad:0x4003B000+0x08))&0x0C)==0x00) group.long 0x18++0x03 line.long 0x00 "CV1,Compare Value Register" hexmask.long.byte 0x00 0.--7. 1. " CV ,Compare value" if (((per.l(ad:0x4003B000+0x20))&0x08)==0x08) group.long 0x1C++0x03 line.long 0x00 "CV2,Compare Value Register" hexmask.long.byte 0x00 0.--7. 1. " CV ,Compare value" endif elif (((per.l(ad:0x4003B000+0x08))&0x0C)==0x04) group.long 0x18++0x03 line.long 0x00 "CV1,Compare Value Register" hexmask.long.word 0x00 0.--11. 1. " CV ,Compare value" if (((per.l(ad:0x4003B000+0x20))&0x08)==0x08) group.long 0x1C++0x03 line.long 0x00 "CV2,Compare Value Register" hexmask.long.word 0x00 0.--11. 1. " CV ,Compare value" endif elif (((per.l(ad:0x4003B000+0x08))&0x0C)==0x08) group.long 0x18++0x03 line.long 0x00 "CV1,Compare Value Register" hexmask.long.word 0x00 0.--9. 1. " CV ,Compare value" if (((per.l(ad:0x4003B000+0x20))&0x08)==0x08) group.long 0x1C++0x03 line.long 0x00 "CV2,Compare Value Register" hexmask.long.word 0x00 0.--9. 1. " CV ,Compare value" endif else group.long 0x18++0x03 line.long 0x00 "CV1,Compare Value Register" hexmask.long.word 0x00 0.--15. 1. " CV ,Compare value" if (((per.l(ad:0x4003B000+0x20))&0x08)==0x08) group.long 0x1C++0x03 line.long 0x00 "CV2,Compare Value Register" hexmask.long.word 0x00 0.--15. 1. " CV ,Compare value" endif endif else if (((per.l(ad:0x4003B000+0x08))&0x0C)==0x00) group.long 0x18++0x03 line.long 0x00 "CV1,Compare Value Register" hexmask.long.word 0x00 0.--8. 1. " CV ,Compare value" if (((per.l(ad:0x4003B000+0x20))&0x08)==0x08) group.long 0x1C++0x03 line.long 0x00 "CV2,Compare Value Register" hexmask.long.word 0x00 0.--8. 1. " CV ,Compare value" endif elif (((per.l(ad:0x4003B000+0x08))&0x0C)==0x04) group.long 0x18++0x03 line.long 0x00 "CV1,Compare Value Register" hexmask.long.word 0x00 0.--12. 1. " CV ,Compare value" if (((per.l(ad:0x4003B000+0x20))&0x08)==0x08) group.long 0x1C++0x03 line.long 0x00 "CV2,Compare Value Register" hexmask.long.word 0x00 0.--12. 1. " CV ,Compare value" endif elif (((per.l(ad:0x4003B000+0x08))&0x0C)==0x08) group.long 0x18++0x03 line.long 0x00 "CV1,Compare Value Register" hexmask.long.word 0x00 0.--10. 1. " CV ,Compare value" if (((per.l(ad:0x4003B000+0x20))&0x08)==0x08) group.long 0x1C++0x03 line.long 0x00 "CV2,Compare Value Register" hexmask.long.word 0x00 0.--10. 1. " CV ,Compare value" endif else group.long 0x18++0x03 line.long 0x00 "CV1,Compare Value Register" hexmask.long.word 0x00 0.--15. 1. " CV ,Compare value" if (((per.l(ad:0x4003B000+0x20))&0x08)==0x08) group.long 0x1C++0x03 line.long 0x00 "CV2,Compare Value Register" hexmask.long.word 0x00 0.--15. 1. " CV ,Compare value" endif endif endif else group.long 0x18++0x03 line.long 0x00 "CV1,Compare Value Register" hexmask.long.word 0x00 0.--15. 1. " CV ,Compare value" if (((per.l(ad:0x4003B000+0x20))&0x08)==0x08) group.long 0x1C++0x03 line.long 0x00 "CV2,Compare Value Register" hexmask.long.word 0x00 0.--15. 1. " CV ,Compare value" endif endif group.long 0x20++0x2F line.long 0x00 "SC2,Status and Control Register 2" rbitfld.long 0x00 7. " ADACT ,Conversion active" "Not in progress,In progress" bitfld.long 0x00 6. " ADTRG ,Conversion trigger select" "Software,Hardware" bitfld.long 0x00 5. " ACFE ,Compare function enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " ACFGT ,Compare function greater than enable" "Disabled,Enabled" bitfld.long 0x00 3. " ACREN ,Compare function range enable" "Disabled,Enabled" bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 0.--1. " REFSEL ,Voltage reference selection" "Default,Alternate,?..." line.long 0x04 "SC3,Status and Control Register 3" bitfld.long 0x04 7. " CAL ,Calibration" "Not started,Started" eventfld.long 0x04 6. " CALF ,Calibration failed flag" "Not occurred,Occurred" bitfld.long 0x04 3. " ADCO ,Continuous conversion enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " AVGE ,Hardware average enable" "Disabled,Enabled" bitfld.long 0x04 0.--1. " AVGS ,Hardware average select" "4 samples,8 samples,16 samples,32 samples" line.long 0x08 "OFS,ADC Offset Correction Register" hexmask.long.word 0x08 0.--15. 1. " OFS ,Offset error correction value" line.long 0x0C "PG,ADC Plus-Side Gain Register" hexmask.long.word 0x0C 0.--15. 1. " PG ,Plus-side gain" line.long 0x10 "MG,ADC Minus-Side Gain Register" hexmask.long.word 0x10 0.--15. 1. " MG ,Minus-side Gain" line.long 0x14 "CLPD,ADC Plus-Side General Calibration Value Register" bitfld.long 0x14 0.--5. " CLPD ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x18 "CLPS,ADC Plus-Side General Calibration Value Register" bitfld.long 0x18 0.--5. " CLPS ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "CLP4,ADC Plus-Side General Calibration Value Register" hexmask.long.word 0x1C 0.--9. 1. " CLP4 ,Calibration value" line.long 0x20 "CLP3,ADC Plus-Side General Calibration Value Register" hexmask.long.word 0x20 0.--8. 1. " CLP3 ,Calibration value" line.long 0x24 "CLP2,ADC Plus-Side General Calibration Value Register" hexmask.long.byte 0x24 0.--7. 1. " CLP2 ,Calibration value" line.long 0x28 "CLP1,ADC Plus-Side General Calibration Value Register" hexmask.long.byte 0x28 0.--6. 1. " CLP1 ,Calibration value" line.long 0x2C "CLP0,ADC Plus-Side General Calibration Value Register" bitfld.long 0x2C 0.--5. " CLP0 ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif !cpuis("MK63FR")&&!cpuis("MK84FN2M0CAU15R")&&!cpuis("MK8?FN256VR")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R")||cpuis("MK8?FN256V*") sif cpuis("MK??FR")||cpuis("KK60FN1M0VLQ15") group.long 0x50++0x03 line.long 0x00 "PGA,ADC PGA Register" bitfld.long 0x00 23. " PGAEN ,PGA enable" "Disabled,Enabled" bitfld.long 0x00 21. " PGACHPB ,PGA chopping enable" "Disabled,Enabled" bitfld.long 0x00 20. " PGALPB ,PGA low-power mode control" "Low,Normal" newline bitfld.long 0x00 16.--19. " PGAG ,PGA gain setting" "1,2,4,8,16,32,64,?..." bitfld.long 0x00 14. " PGAOFSM ,PGA run mode" "Normal,Offset measurement" else group.long 0x50++0x03 line.long 0x00 "PGA,ADC PGA Register" bitfld.long 0x00 23. " PGAEN ,PGA enable" "Disabled,Enabled" bitfld.long 0x00 20. " PGALPB ,PGA low-power mode control" "Low,Normal" bitfld.long 0x00 16.--19. " PGAG ,PGA gain setting" "1,2,4,8,16,32,64,?..." endif endif group.long 0x54++0x1B line.long 0x00 "CLMD,ADC Minus-Side General Calibration Value Register" bitfld.long 0x00 0.--5. " CLMD ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "CLMS,ADC Minus-Side General Calibration Value Register" bitfld.long 0x04 0.--5. " CLMS ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "CLM4,ADC Minus-Side General Calibration Value Register" hexmask.long.word 0x08 0.--9. 1. " CLM4 ,Calibration value" line.long 0x0C "CLM3,ADC Minus-Side General Calibration Value Register" hexmask.long.word 0x0C 0.--8. 1. " CLM3 ,Calibration value" line.long 0x10 "CLM2,ADC Minus-Side General Calibration Value Register" hexmask.long.byte 0x10 0.--7. 1. " CLM2 ,Calibration value" line.long 0x14 "CLM1,ADC Minus-Side General Calibration Value Register" hexmask.long.byte 0x14 0.--6. 1. " CLM1 ,Calibration value" line.long 0x18 "CLM0,ADC Minus-Side General Calibration Value Register" bitfld.long 0x18 0.--5. " CLM0 ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" width 0x0B tree.end tree.open "CMP (Comparator)" tree "CMP_0" base ad:0x40073000 width 12. group.byte 0x00++0x05 line.byte 0x00 "CR0,CMP Control Register 0" bitfld.byte 0x00 4.--6. " FILTER_CNT ,Filter sample count" "Disabled,1 sample,2 samples,3 samples,4 samples,5 samples,6 samples,7 samples" bitfld.byte 0x00 0.--1. " HYSTCTR ,Comparator hard block hysteresis control" "Level 0,Level 1,Level 2,Level 3" line.byte 0x01 "CR1,CMP Control Register 1" bitfld.byte 0x01 7. " SE ,Sample enable" "Disabled,Enabled" bitfld.byte 0x01 6. " WE ,Windowing enable" "Disabled,Enabled" sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") newline bitfld.byte 0x01 5. " TRIGM ,Trigger mode enable" "Disabled,Enabled" endif newline bitfld.byte 0x01 4. " PMODE ,Power mode select" "Low-speed,High-speed" bitfld.byte 0x01 3. " INV ,Comparator INVERT" "Not inverted,Inverted" bitfld.byte 0x01 2. " COS ,Comparator output select" "COUT,COUTA" newline bitfld.byte 0x01 1. " OPE ,Comparator output pin enable" "Disabled,Enabled" bitfld.byte 0x01 0. " EN ,Comparator module enable" "Disabled,Enabled" line.byte 0x02 "FPR,CMP Filter Period Register" line.byte 0x03 "SCR,CMP Status and Control Register" bitfld.byte 0x03 6. " DMAEN ,DMA enable control" "Disabled,Enabled" sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*"))||cpuis("MK40D*Z*10")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60DN512ZCAB10R")||cpuis("KK60DN512ZCAB10R") newline bitfld.byte 0x03 5. " SMELB ,Stop mode edge/level interrupt control" "Level,Edge" endif newline bitfld.byte 0x03 4. " IER ,Comparator interrupt enable rising" "Disabled,Enabled" bitfld.byte 0x03 3. " IEF ,Comparator interrupt enable falling" "Disabled,Enabled" eventfld.byte 0x03 2. " CFR ,Analog comparator flag rising" "Not occurred,Occurred" newline eventfld.byte 0x03 1. " CFF ,Analog comparator flag falling" "Not occurred,Occurred" rbitfld.byte 0x03 0. " COUT ,Analog comparator output" "Low,High" line.byte 0x04 "DACCR,DAC Control Register" bitfld.byte 0x04 7. " DACEN ,DAC enable" "Disabled,Enabled" newline sif !cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("KK60FN1M0VLQ15")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.byte 0x04 6. " VRSEL ,Supply voltage reference source select" "Vin1,Vin2" else bitfld.byte 0x04 6. " VRSEL ,Supply voltage reference source select" "VREF_OUT,VDD" endif newline bitfld.byte 0x04 0.--5. " VOSEL ,DAC output voltage level select" "1/64 Vin,2/64 Vin,3/64 Vin,4/64 Vin,5/64 Vin,6/64 Vin,7/64 Vin,8/64 Vin,9/64 Vin,10/64 Vin,11/64 Vin,12/64 Vin,13/64 Vin,14/64 Vin,15/64 Vin,16/64 Vin,17/64 Vin,18/64 Vin,19/64 Vin,20/64 Vin,21/64 Vin,22/64 Vin,23/64 Vin,24/64 Vin,25/64 Vin,26/64 Vin,27/64 Vin,28/64 Vin,29/64 Vin,30/64 Vin,31/64 Vin,32/64 Vin,33/64 Vin,34/64 Vin,35/64 Vin,36/64 Vin,37/64 Vin,38/64 Vin,39/64 Vin,40/64 Vin,41/64 Vin,42/64 Vin,43/64 Vin,44/64 Vin,45/64 Vin,46/64 Vin,47/64 Vin,48/64 Vin,49/64 Vin,50/64 Vin,51/64 Vin,52/64 Vin,53/64 Vin,54/64 Vin,55/64 Vin,56/64 Vin,57/64 Vin,58/64 Vin,59/64 Vin,60/64 Vin,61/64 Vin,62/64 Vin,63/64 Vin,Vin" line.byte 0x05 "MUXCR,MUX Control Register" sif !(cpuis("MK70*"))&&!cpuis("MK8?FN256V*") sif cpuis("MK60D*AB10")||cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*")||cpuis("MK40D*Z*10")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60DN512ZCAB10R")||cpuis("KK60DN512ZCAB10R") bitfld.byte 0x05 7. " PEN ,PMUX enable" "Disabled,Enabled" newline elif cpuis("MK63*F")||cpuis("MK64*F")||cpuis("MK65*F")||cpuis("MK66*F")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R")||cpuis("KK65FN2M0CAC18R") bitfld.byte 0x05 7. " PSTM ,Pass through mode enable" "Disabled,Enabled" newline endif sif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("") bitfld.byte 0x05 6. " PSTM ,Pass through mode enable" "Disabled,Enabled" elif !cpuis("MK??F*")&&!cpuis("MK30DN512ZVLK10")&&!cpuis("MK30D????ZVLQ*")&&!cpuis("MK50DN512ZCLL10")&&!cpuis("MK50DX256ZCLL10")&&!cpuis("MK50DN512ZCLQ10")&&!cpuis("MK50DX256ZCLQ10")&&!cpuis("MK51DN512ZCLL10")&&!cpuis("MK51DN512ZCMC10")&&!cpuis("MK51DX256ZCMC10")&&!cpuis("MK51DN256ZCMD10")&&!cpuis("MK51DN512ZCLQ10")&&!cpuis("MK52DN512ZCLQ10")&&!cpuis("MK52DN512ZCMD10")&&!cpuis("MK53DN512ZCLQ10")&&!cpuis("MK53DN512ZCMD10")&&!cpuis("MK53DX256ZCLQ10")&&!cpuis("MK40D*Z*10")&&!cpuis("MK60DN512ZCAB10R")&&!cpuis("KK60DN512ZCAB10R") bitfld.byte 0x05 6. " PSTM ,Pass through mode enable" "Disabled,Enabled" else bitfld.byte 0x05 6. " MEN ,MMUX enable" "Disabled,Enabled" endif newline endif sif cpuis("MK84FN2M0CAU15R") newline bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,,VREF Out/IN5,Bandgap,6-bit DAC" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,,VREF Out/IN5,Bandgap,6-bit DAC" elif cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*")||cpuis("MK30DX256VLL7*") newline bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "CMP0_IN0,CMP0_IN1,CMP0_IN2,CMP0_IN3,CMP0_IN4,VREF Out/CMP0_IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "CMP0_IN0,CMP0_IN1,CMP0_IN2,CMP0_IN3,CMP0_IN4,VREF Out/CMP0_IN5,Bandgap,6-bit DAC0" elif cpuis("MK70*") newline bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "CMP0_IN0,CMP0_IN1,CMP0_IN2,CMP0_IN3,12b DAC1,VREF Out/CMP0_IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "CMP0_IN0,CMP0_IN1,CMP0_IN2,CMP0_IN3,12b DAC1,VREF Out/CMP0_IN5,Bandgap,6-bit DAC0" elif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") newline bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "CMP0_IN0,CMP0_IN1,CMP0_IN2,CMP0_IN3,CMP0_IN4,VREF out/CMP0_IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "CMP0_IN0,CMP0_IN1,CMP0_IN2,CMP0_IN3,CMP0_IN4,VREF output/CMP0_IN5,Bandgap,6-bit DAC0" elif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R") newline sif cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "CMP0_IN0,CMP0_IN1,CMP0_IN2,CMP0_IN3,12 bit DAC1/CMP0_IN4,VREF Out/CMP0_IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "CMP0_IN0,CMP0_IN1,CMP0_IN2,CMP0_IN3,12 bit DAC1/CMP0_IN4,VREF Out/CMP0_IN5,Bandgap,6-bit DAC0" else bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "CMP0_IN0,CMP0_IN1,CMP0_IN2,CMP0_IN3,CMP0_IN4,VREF Out/CMP0_IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "CMP0_IN0,CMP0_IN1,CMP0_IN2,CMP0_IN3,CMP0_IN4,VREF Out/CMP0_IN5,Bandgap,6-bit DAC0" endif elif cpuis("MK60DN512VMC10R") newline bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "CMP0_IN0,CMP0_IN1,CMP0_IN2,CMP0_IN3,12b DAC0_OUT/CMP0_IN4,VREF Out/CMP0_IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "CMP0_IN0,CMP0_IN1,CMP0_IN2,CMP0_IN3,12b DAC0_OUT/CMP0_IN4,VREF Out/CMP0_IN5,Bandgap,6-bit DAC0" elif cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512ZVMC10R") newline bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "CMP0_IN0,CMP0_IN1,CMP0_IN2,CMP0_IN3,12 bit DAC1/CMP0_IN4,VREF Out/CMP0_IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "CMP0_IN0,CMP0_IN1,CMP0_IN2,CMP0_IN3,CMP0_IN4,VREF Out/CMP0_IN5,Bandgap,6-bit DAC0" elif cpuis("KK60FN1M0VLQ15") newline bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "CMP0_IN0,CMP0_IN1,CMP0_IN2,CMP0_IN3,12b DAC1,VREF Out/CMP0_IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "CMP0_IN0,CMP0_IN1,CMP0_IN2,CMP0_IN3,12b DAC1,VREF Out/CMP0_IN5,Bandgap,6-bit DAC0" elif cpuis("KK60DN512ZCAB10R") newline bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "CMP0_IN0,CMP0_IN1,CMP0_IN2,CMP0_IN3,CMP0_IN4,VREF Out/CMP0_IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "CMP0_IN0,CMP0_IN1,CMP0_IN2,CMP0_IN3,CMP0_IN4,VREF Out/CMP0_IN5,Bandgap,6-bit DAC0" elif cpuis("MK63FN1M0VLQ12R") newline bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "CMP0_IN0,CMP0_IN1,CMP0_IN2,CMP0_IN3,12-bit DAC1_OUT/CMP0_IN4,,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "CMP0_IN0,CMP0_IN1,CMP0_IN2,CMP0_IN3,12-bit DAC1_OUT/CMP0_IN4,,Bandgap,6-bit DAC0" elif cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") newline bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "CMP0_IN0,CMP0_IN1,CMP0_IN2,CMP0_IN3,12b DAC1_OUT/CMP0_IN4,VREF Out/CMP0_IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "CMP0_IN0,CMP0_IN1,CMP0_IN2,CMP0_IN3,12b DAC1_OUT/CMP0_IN4,VREF Out/CMP0_IN5,Bandgap,6-bit DAC0" else newline bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,IN6,IN7" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,IN6,IN7" endif width 0x0B tree.end tree "CMP_1" base ad:0x40073000 width 12. group.byte 0x08++0x05 line.byte 0x00 "CR0,CMP Control Register 0" bitfld.byte 0x00 4.--6. " FILTER_CNT ,Filter sample count" "Disabled,1 sample,2 samples,3 samples,4 samples,5 samples,6 samples,7 samples" bitfld.byte 0x00 0.--1. " HYSTCTR ,Comparator hard block hysteresis control" "Level 0,Level 1,Level 2,Level 3" line.byte 0x01 "CR1,CMP Control Register 1" bitfld.byte 0x01 7. " SE ,Sample enable" "Disabled,Enabled" bitfld.byte 0x01 6. " WE ,Windowing enable" "Disabled,Enabled" sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") newline bitfld.byte 0x01 5. " TRIGM ,Trigger mode enable" "Disabled,Enabled" endif newline bitfld.byte 0x01 4. " PMODE ,Power mode select" "Low-speed,High-speed" bitfld.byte 0x01 3. " INV ,Comparator INVERT" "Not inverted,Inverted" bitfld.byte 0x01 2. " COS ,Comparator output select" "COUT,COUTA" newline bitfld.byte 0x01 1. " OPE ,Comparator output pin enable" "Disabled,Enabled" bitfld.byte 0x01 0. " EN ,Comparator module enable" "Disabled,Enabled" line.byte 0x02 "FPR,CMP Filter Period Register" line.byte 0x03 "SCR,CMP Status and Control Register" bitfld.byte 0x03 6. " DMAEN ,DMA enable control" "Disabled,Enabled" sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*"))||cpuis("MK40D*Z*10")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60DN512ZCAB10R")||cpuis("KK60DN512ZCAB10R") newline bitfld.byte 0x03 5. " SMELB ,Stop mode edge/level interrupt control" "Level,Edge" endif newline bitfld.byte 0x03 4. " IER ,Comparator interrupt enable rising" "Disabled,Enabled" bitfld.byte 0x03 3. " IEF ,Comparator interrupt enable falling" "Disabled,Enabled" eventfld.byte 0x03 2. " CFR ,Analog comparator flag rising" "Not occurred,Occurred" newline eventfld.byte 0x03 1. " CFF ,Analog comparator flag falling" "Not occurred,Occurred" rbitfld.byte 0x03 0. " COUT ,Analog comparator output" "Low,High" line.byte 0x04 "DACCR,DAC Control Register" bitfld.byte 0x04 7. " DACEN ,DAC enable" "Disabled,Enabled" newline sif !cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("KK60FN1M0VLQ15")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.byte 0x04 6. " VRSEL ,Supply voltage reference source select" "Vin1,Vin2" else bitfld.byte 0x04 6. " VRSEL ,Supply voltage reference source select" "VREF_OUT,VDD" endif newline bitfld.byte 0x04 0.--5. " VOSEL ,DAC output voltage level select" "1/64 Vin,2/64 Vin,3/64 Vin,4/64 Vin,5/64 Vin,6/64 Vin,7/64 Vin,8/64 Vin,9/64 Vin,10/64 Vin,11/64 Vin,12/64 Vin,13/64 Vin,14/64 Vin,15/64 Vin,16/64 Vin,17/64 Vin,18/64 Vin,19/64 Vin,20/64 Vin,21/64 Vin,22/64 Vin,23/64 Vin,24/64 Vin,25/64 Vin,26/64 Vin,27/64 Vin,28/64 Vin,29/64 Vin,30/64 Vin,31/64 Vin,32/64 Vin,33/64 Vin,34/64 Vin,35/64 Vin,36/64 Vin,37/64 Vin,38/64 Vin,39/64 Vin,40/64 Vin,41/64 Vin,42/64 Vin,43/64 Vin,44/64 Vin,45/64 Vin,46/64 Vin,47/64 Vin,48/64 Vin,49/64 Vin,50/64 Vin,51/64 Vin,52/64 Vin,53/64 Vin,54/64 Vin,55/64 Vin,56/64 Vin,57/64 Vin,58/64 Vin,59/64 Vin,60/64 Vin,61/64 Vin,62/64 Vin,63/64 Vin,Vin" line.byte 0x05 "MUXCR,MUX Control Register" sif !(cpuis("MK70*"))&&!cpuis("MK8?FN256V*") sif cpuis("MK60D*AB10")||cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*")||cpuis("MK40D*Z*10")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60DN512ZCAB10R")||cpuis("KK60DN512ZCAB10R") bitfld.byte 0x05 7. " PEN ,PMUX enable" "Disabled,Enabled" newline elif cpuis("MK63*F")||cpuis("MK64*F")||cpuis("MK65*F")||cpuis("MK66*F")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R")||cpuis("KK65FN2M0CAC18R") bitfld.byte 0x05 7. " PSTM ,Pass through mode enable" "Disabled,Enabled" newline endif sif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("") bitfld.byte 0x05 6. " PSTM ,Pass through mode enable" "Disabled,Enabled" elif !cpuis("MK??F*")&&!cpuis("MK30DN512ZVLK10")&&!cpuis("MK30D????ZVLQ*")&&!cpuis("MK50DN512ZCLL10")&&!cpuis("MK50DX256ZCLL10")&&!cpuis("MK50DN512ZCLQ10")&&!cpuis("MK50DX256ZCLQ10")&&!cpuis("MK51DN512ZCLL10")&&!cpuis("MK51DN512ZCMC10")&&!cpuis("MK51DX256ZCMC10")&&!cpuis("MK51DN256ZCMD10")&&!cpuis("MK51DN512ZCLQ10")&&!cpuis("MK52DN512ZCLQ10")&&!cpuis("MK52DN512ZCMD10")&&!cpuis("MK53DN512ZCLQ10")&&!cpuis("MK53DN512ZCMD10")&&!cpuis("MK53DX256ZCLQ10")&&!cpuis("MK40D*Z*10")&&!cpuis("MK60DN512ZCAB10R")&&!cpuis("KK60DN512ZCAB10R") bitfld.byte 0x05 6. " PSTM ,Pass through mode enable" "Disabled,Enabled" else bitfld.byte 0x05 6. " MEN ,MMUX enable" "Disabled,Enabled" endif newline endif sif cpuis("MK84FN2M0CAU15R") newline bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,,VREF Out/IN5,Bandgap,6-bit DAC" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,,VREF Out/IN5,Bandgap,6-bit DAC" elif cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*")||cpuis("MK30DX256VLL7*") newline bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "CMP1_IN0,CMP1_IN1,,12b DAC0/CMP1_IN3,,VREF Out/CMP1_IN5,Bandgap,6-bit DAC1" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "CMP1_IN0,CMP1_IN1,,12b DAC0/CMP1_IN3,,VREF Out/CMP1_IN5,Bandgap,6-bit DAC1" elif cpuis("MK70*") newline bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "CMP1_IN0,CMP1_IN1,ADC0SE16/CMP1_IN2,12b DAC0/CMP1_IN3,,VREF Out/CMP1_IN5,Bandgap,6-bit DAC1" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "CMP1_IN0,CMP1_IN1,ADC0SE16/CMP1_IN2,12b DAC0/CMP1_IN3,,VREF Out/CMP1_IN5,Bandgap,6-bit DAC1" elif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") newline bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "CMP1_IN0,CMP1_IN1,Op-amp 0 output/CMP1_IN2,12b DAC0/CMP1_IN3,,VREF out/CMP1_IN5,Bandgap,6-bit DAC1" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "CMP1_IN0,CMP1_IN1,Op-amp 0 output/CMP1_IN2,12b DAC0/CMP1_IN3,,VREF out/CMP1_IN5,Bandgap,6-bit DAC1" elif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R") newline bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "CMP1_IN0,CMP1_IN1,,12b DAC0/CMP1_IN3,,VREF Out/CMP1_IN5,Bandgap,6-bit DAC1" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "CMP1_IN0,CMP1_IN1,,12b DAC0/CMP1_IN3,,VREF Out/CMP1_IN5,Bandgap,6-bit DAC1" elif cpuis("MK60DN512VMC10R") newline bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "CMP1_IN0,CMP1_IN1,CMP1_IN2,12b DAC0/CMP1_IN3,,VREF Out/CMP1_IN5,Bandgap,6-bit DAC1" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "CMP1_IN0,CMP1_IN1,CMP1_IN2,12b DAC0/CMP1_IN3,,VREF Out/CMP1_IN5,Bandgap,6-bit DAC1" elif cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512ZVMC10R") newline bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "CMP1_IN0,CMP1_IN1,,12b DAC0/CMP1_IN3,,VREF Out/CMP1_IN5,Bandgap,6-bit DAC1" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "CMP1_IN0,CMP1_IN1,,12b DAC0/CMP1_IN3,,VREF Out/CMP1_IN5,Bandgap,6-bit DAC1" elif cpuis("KK60FN1M0VLQ15") newline bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "CMP1_IN0,CMP1_IN1,ADC0SE16/CMP1_IN2,12b DAC0/CMP1_IN3,,VREF Out/CMP1_IN5,Bandgap,6-bit DAC1" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "CMP1_IN0,CMP1_IN1,ADC0SE16/CMP1_IN2,12b DAC0/CMP1_IN3,,VREF Out/CMP1_IN5,Bandgap,6-bit DAC1" elif cpuis("KK60DN512ZCAB10R") newline bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "CMP1_IN0,CMP1_IN1,CMP1_IN2,12b DAC0_OUT/CMP1_IN3,,VREF Out/CMP1_IN5,Bandgap,6-bit DAC1" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "CMP1_IN0,CMP1_IN1,CMP1_IN2,12b DAC0_OUT/CMP1_IN3,,VREF Out/CMP1_IN5,Bandgap,6-bit DAC1" elif cpuis("MK63FN1M0VLQ12R") newline bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "CMP1_IN0,CMP1_IN1,ADC0_SE16/CMP1_IN2,12b ,,,Bandgap,6-bit DAC1" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "CMP1_IN0,CMP1_IN1,ADC0_SE16/CMP1_IN2,12b ,,,Bandgap,6-bit DAC1" elif cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") newline bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "CMP1_IN0,CMP1_IN1,ADC0_SE16/CMP1_IN2,12b DAC0_OUT/CMP1_IN3,,VREF Out/CMP1_IN5,Bandgap,6-bit DAC1" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "CMP1_IN0,CMP1_IN1,ADC0_SE16/CMP1_IN2,12b DAC0_OUT/CMP1_IN3,,VREF Out/CMP1_IN5,Bandgap,6-bit DAC1" else newline bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,IN6,IN7" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,IN6,IN7" endif width 0x0B tree.end tree.end tree "VREFV1 (Voltage Reference)" base ad:0x40074000 width 5. group.byte 0x00++0x01 line.byte 0x00 "TRM,VREF Trim Register" bitfld.byte 0x00 6. " CHOPEN ,Chop oscillator enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " TRIM ,Trim bits" "Min,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,Max" line.byte 0x01 "SC,VREF Status and Control Register" bitfld.byte 0x01 7. " VREFEN ,Internal Voltage Reference enable" "Disabled,Enabled" bitfld.byte 0x01 6. " REGEN ,Internal 1.75 V regulator enable" "Disabled,Enabled" bitfld.byte 0x01 5. " ICOMPEN ,Second order curvature compensation enable" "Disabled,Enabled" rbitfld.byte 0x01 2. " VREFST ,Internal Voltage Reference stable" "Not stable,Stable" newline bitfld.byte 0x01 0.--1. " MODE_LV ,Buffer Mode selection" "Bandgap,High power,Low power,?..." width 0x0B tree.end tree "DAC (12-bit Digital-to-Analog Converter)" base ad:0x400CC000 width 8. sif cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10") group.byte 0x00++0x01 line.byte 0x00 "DAT0L,DAC Data Low Register" line.byte 0x01 "DAT0H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x2++0x00 line.byte 0x00 "DAT1L,DAC Data Low Register" group.byte 0x4++0x00 line.byte 0x00 "DAT2L,DAC Data Low Register" group.byte 0x6++0x00 line.byte 0x00 "DAT3L,DAC Data Low Register" group.byte 0x8++0x00 line.byte 0x00 "DAT4L,DAC Data Low Register" group.byte 0xA++0x00 line.byte 0x00 "DAT5L,DAC Data Low Register" group.byte 0xC++0x00 line.byte 0x00 "DAT6L,DAC Data Low Register" group.byte 0xE++0x00 line.byte 0x00 "DAT7L,DAC Data Low Register" group.byte 0x10++0x00 line.byte 0x00 "DAT8L,DAC Data Low Register" group.byte 0x12++0x00 line.byte 0x00 "DAT9L,DAC Data Low Register" group.byte 0x14++0x00 line.byte 0x00 "DAT10L,DAC Data Low Register" group.byte 0x16++0x00 line.byte 0x00 "DAT11L,DAC Data Low Register" group.byte 0x18++0x00 line.byte 0x00 "DAT12L,DAC Data Low Register" group.byte 0x1A++0x00 line.byte 0x00 "DAT13L,DAC Data Low Register" group.byte 0x1C++0x00 line.byte 0x00 "DAT14L,DAC Data Low Register" group.byte 0x1E++0x00 line.byte 0x00 "DAT15L,DAC Data Low Register" else group.byte 0x0++0x01 line.byte 0x00 "DAT0L,DAC Data Low Register" line.byte 0x01 "DAT0H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x2++0x01 line.byte 0x00 "DAT1L,DAC Data Low Register" line.byte 0x01 "DAT1H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x4++0x01 line.byte 0x00 "DAT2L,DAC Data Low Register" line.byte 0x01 "DAT2H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x6++0x01 line.byte 0x00 "DAT3L,DAC Data Low Register" line.byte 0x01 "DAT3H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x8++0x01 line.byte 0x00 "DAT4L,DAC Data Low Register" line.byte 0x01 "DAT4H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0xA++0x01 line.byte 0x00 "DAT5L,DAC Data Low Register" line.byte 0x01 "DAT5H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0xC++0x01 line.byte 0x00 "DAT6L,DAC Data Low Register" line.byte 0x01 "DAT6H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0xE++0x01 line.byte 0x00 "DAT7L,DAC Data Low Register" line.byte 0x01 "DAT7H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x10++0x01 line.byte 0x00 "DAT8L,DAC Data Low Register" line.byte 0x01 "DAT8H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x12++0x01 line.byte 0x00 "DAT9L,DAC Data Low Register" line.byte 0x01 "DAT9H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x14++0x01 line.byte 0x00 "DAT10L,DAC Data Low Register" line.byte 0x01 "DAT10H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x16++0x01 line.byte 0x00 "DAT11L,DAC Data Low Register" line.byte 0x01 "DAT11H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x18++0x01 line.byte 0x00 "DAT12L,DAC Data Low Register" line.byte 0x01 "DAT12H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x1A++0x01 line.byte 0x00 "DAT13L,DAC Data Low Register" line.byte 0x01 "DAT13H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x1C++0x01 line.byte 0x00 "DAT14L,DAC Data Low Register" line.byte 0x01 "DAT14H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x1E++0x01 line.byte 0x00 "DAT15L,DAC Data Low Register" line.byte 0x01 "DAT15H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" endif newline width 4. group.byte 0x20++0x01 line.byte 0x00 "SR,DAC Status Register" bitfld.byte 0x00 2. " DACBFWMF ,DAC buffer reached the watermark level" "Not reached,Reached" bitfld.byte 0x00 1. " DACBFRPTF ,DAC buffer read pointer is zero" "Not zero,Zero" bitfld.byte 0x00 0. " DACBFRPBF ,DAC buffer read pointer bottom position flag (pointer not equal/equal to the DACBFUP)" "Not equal,Equal" line.byte 0x01 "C0,DAC Control Register" bitfld.byte 0x01 7. " DACEN ,DAC enable" "Disabled,Enabled" bitfld.byte 0x01 6. " DACRFS ,DAC reference select" "VREF_OUT,VDDA" bitfld.byte 0x01 5. " DACTRGSEL ,DAC trigger select" "Hardware,Software" bitfld.byte 0x01 4. " DACSWTRG ,DAC software trigger" "Not valid,Valid" newline bitfld.byte 0x01 3. " LPEN ,DAC low power control" "High-Power,Low-Power" bitfld.byte 0x01 2. " DACBWIEN ,DAC buffer watermark interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 1. " DACBTIEN ,DAC buffer read pointer top flag interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 0. " DACBBIEN ,DAC buffer read pointer bottom flag interrupt enable" "Disabled,Enabled" sif cpuis("MK22FN128*")||cpuis("MK22FN256*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FX512AVMC12")||cpuis("MK70*")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MKS2?FN???V??12")||cpuis("KK22FN???C?P12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VFX12*")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN???CAH12R")||cpuis("MK27FN2M0VMI15")||cpuis("?K28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") if (((per.b(ad:0x400CC000+0x22))&0x06)==0x06) group.byte 0x22++0x00 line.byte 0x00 "C1,DAC Control Register 1" bitfld.byte 0x00 7. " DMAEN ,DMA enable select" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " DACBFWM ,DAC buffer watermark (Quantity of data remaining in FIFO that will set watermark status)" "2 or less,Max/4 or less,Max/2 or less,Max-2 or less" bitfld.byte 0x00 1.--2. " DACBFMD ,DAC buffer work mode select" "Normal,Swing,One-Time scan,FIFO" bitfld.byte 0x00 0. " DACBFEN ,DAC buffer enable" "Disabled,Enabled" else group.byte 0x22++0x00 line.byte 0x00 "C1,DAC Control Register 1" bitfld.byte 0x00 7. " DMAEN ,DMA enable select" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " DACBFWM ,DAC buffer watermark select" "1 word,2 words,3 words,4 words" bitfld.byte 0x00 1.--2. " DACBFMD ,DAC buffer work mode select" "Normal,Swing,One-Time scan,FIFO" bitfld.byte 0x00 0. " DACBFEN ,DAC buffer enable" "Disabled,Enabled" endif elif cpuis("MK22FX512AVLH12")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVLH12R") group.byte 0x22++0x00 line.byte 0x00 "C1,DAC Control Register 1" bitfld.byte 0x00 7. " DMAEN ,DMA enable select" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " DACBFWM ,DAC buffer watermark select" "1 word,2 words,?..." bitfld.byte 0x00 1.--2. " DACBFMD ,DAC buffer work mode select" "Normal,,One-Time scan,?..." bitfld.byte 0x00 0. " DACBFEN ,DAC buffer enable" "Disabled,Enabled" elif cpuis("MK02*") group.byte 0x22++0x00 line.byte 0x00 "C1,DAC Control Register 1" bitfld.byte 0x00 7. " DMAEN ,DMA enable select" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " DACBFWM ,DAC buffer watermark select" "1 word,2 words,3 words,4 words" bitfld.byte 0x00 1.--2. " DACBFMD ,DAC buffer work mode select" "Normal,Swing,One-Time scan,FIFO" bitfld.byte 0x00 0. " DACBFEN ,DAC buffer enable" "Disabled,Enabled" else group.byte 0x22++0x00 line.byte 0x00 "C1,DAC Control Register 1" bitfld.byte 0x00 7. " DMAEN ,DMA enable select" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " DACBFWM ,DAC buffer watermark select" "1 word,2 words,3 words,4 words" bitfld.byte 0x00 1.--2. " DACBFMD ,DAC buffer work mode select" "Normal,Swing,One-Time scan,?..." bitfld.byte 0x00 0. " DACBFEN ,DAC buffer enable" "Disabled,Enabled" endif group.byte 0x23++0x00 line.byte 0x00 "C2,DAC Control Register 2" sif cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FX512AVLH12R") bitfld.byte 0x00 4. " DACBFRP ,DAC buffer read pointer" "0,1" bitfld.byte 0x00 0. " DACBFUP ,DAC buffer upper limit" "0,1" else bitfld.byte 0x00 4.--7. " DACBFRP ,DAC buffer read pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " DACBFUP ,DAC buffer upper limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif width 0x0B tree.end tree.open "FTM (FlexTimer Module)" tree "FTM_0" base ad:0x40038000 width 10. if (((per.l(ad:0x40038000+0x54))&0x04)==0x04) group.long 0x00++0x03 line.long 0x00 "SC,Status And Control" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " CPWMS ,Center-Aligned PWM select" "Up counting mode,Up-Down counting mode" bitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clock,System clock,Fixed frequency clock,External clock" newline bitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" else group.long 0x00++0x03 line.long 0x00 "SC,Status And Control" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " CPWMS ,Center-Aligned PWM select" "Up counting mode,Up-Down counting mode" rbitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clock,System clock,Fixed frequency clock,External clock" newline rbitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" endif group.long 0x04++0x07 line.long 0x00 "CNT,Counter" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" line.long 0x04 "MOD,Modulo" hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value" if ((((per.l(ad:0x40038000+0x64))&0x05)==0x00)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0xC))&0x30)==0x00)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x04)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x05)==0x00)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0xC))&0x30)==0x00)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x00)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x05)==0x00)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0xC))&0x30)==0x10)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x04)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x05)==0x00)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0xC))&0x30)==0x10)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x00)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x05)==0x00)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0xC))&0x30)==(0x20||0x30))&&(((per.l(ad:0x40038000+0x54))&0x04)==0x04)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x05)==0x00)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0xC))&0x30)==(0x20||0x30))&&(((per.l(ad:0x40038000+0x54))&0x04)==0x00)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x05)==0x00)&&(((per.l(ad:0x40038000))&0x20)==0x20)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x04)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x05)==0x00)&&(((per.l(ad:0x40038000))&0x20)==0x20)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x00)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x05)==0x01)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x04)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x05)==0x01)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x00)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x05)==0x04)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x04)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x05)==0x04)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x00)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0xC++0x03 hide.long 0x00 "C0SC,Channel (0) Status And Control" endif group.long (0xC+0x04)++0x03 line.long 0x00 "C0V,Channel (0) Value" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" if ((((per.l(ad:0x40038000+0x64))&0x05)==0x00)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x14))&0x30)==0x00)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x04)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x05)==0x00)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x14))&0x30)==0x00)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x00)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x05)==0x00)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x14))&0x30)==0x10)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x04)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x05)==0x00)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x14))&0x30)==0x10)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x00)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x05)==0x00)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x14))&0x30)==(0x20||0x30))&&(((per.l(ad:0x40038000+0x54))&0x04)==0x04)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x05)==0x00)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x14))&0x30)==(0x20||0x30))&&(((per.l(ad:0x40038000+0x54))&0x04)==0x00)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x05)==0x00)&&(((per.l(ad:0x40038000))&0x20)==0x20)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x04)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x05)==0x00)&&(((per.l(ad:0x40038000))&0x20)==0x20)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x00)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x05)==0x01)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x04)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x05)==0x01)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x00)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x05)==0x04)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x04)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x05)==0x04)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x00)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x14++0x03 hide.long 0x00 "C1SC,Channel (1) Status And Control" endif group.long (0x14+0x04)++0x03 line.long 0x00 "C1V,Channel (1) Value" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" if ((((per.l(ad:0x40038000+0x64))&0x500)==0x00)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x1C))&0x30)==0x00)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x04)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x500)==0x00)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x1C))&0x30)==0x00)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x00)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x500)==0x00)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x1C))&0x30)==0x10)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x04)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x500)==0x00)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x1C))&0x30)==0x10)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x00)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x500)==0x00)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x1C))&0x30)==(0x20||0x30))&&(((per.l(ad:0x40038000+0x54))&0x04)==0x04)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x500)==0x00)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x1C))&0x30)==(0x20||0x30))&&(((per.l(ad:0x40038000+0x54))&0x04)==0x00)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x500)==0x00)&&(((per.l(ad:0x40038000))&0x20)==0x20)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x04)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x500)==0x00)&&(((per.l(ad:0x40038000))&0x20)==0x20)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x00)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x500)==0x100)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x04)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x500)==0x100)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x00)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x500)==0x400)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x04)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x500)==0x400)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x00)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x1C++0x03 hide.long 0x00 "C2SC,Channel (2) Status And Control" endif group.long (0x1C+0x04)++0x03 line.long 0x00 "C2V,Channel (2) Value" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" if ((((per.l(ad:0x40038000+0x64))&0x500)==0x00)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x24))&0x30)==0x00)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x04)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x500)==0x00)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x24))&0x30)==0x00)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x00)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x500)==0x00)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x24))&0x30)==0x10)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x04)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x500)==0x00)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x24))&0x30)==0x10)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x00)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x500)==0x00)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x24))&0x30)==(0x20||0x30))&&(((per.l(ad:0x40038000+0x54))&0x04)==0x04)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x500)==0x00)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x24))&0x30)==(0x20||0x30))&&(((per.l(ad:0x40038000+0x54))&0x04)==0x00)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x500)==0x00)&&(((per.l(ad:0x40038000))&0x20)==0x20)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x04)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x500)==0x00)&&(((per.l(ad:0x40038000))&0x20)==0x20)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x00)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x500)==0x100)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x04)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x500)==0x100)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x00)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x500)==0x400)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x04)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x500)==0x400)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x00)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x24++0x03 hide.long 0x00 "C3SC,Channel (3) Status And Control" endif group.long (0x24+0x04)++0x03 line.long 0x00 "C3V,Channel (3) Value" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" if ((((per.l(ad:0x40038000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x2C))&0x30)==0x00)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x04)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x2C))&0x30)==0x00)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x00)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x2C))&0x30)==0x10)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x04)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x2C))&0x30)==0x10)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x00)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x2C))&0x30)==(0x20||0x30))&&(((per.l(ad:0x40038000+0x54))&0x04)==0x04)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x2C))&0x30)==(0x20||0x30))&&(((per.l(ad:0x40038000+0x54))&0x04)==0x00)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x40038000))&0x20)==0x20)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x04)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x40038000))&0x20)==0x20)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x00)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x50000)==0x10000)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x04)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x50000)==0x10000)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x00)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x50000)==0x40000)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x04)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x50000)==0x40000)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x00)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x2C++0x03 hide.long 0x00 "C4SC,Channel (4) Status And Control" endif group.long (0x2C+0x04)++0x03 line.long 0x00 "C4V,Channel (4) Value" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" if ((((per.l(ad:0x40038000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x34))&0x30)==0x00)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x04)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x34))&0x30)==0x00)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x00)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x34))&0x30)==0x10)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x04)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x34))&0x30)==0x10)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x00)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x34))&0x30)==(0x20||0x30))&&(((per.l(ad:0x40038000+0x54))&0x04)==0x04)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x34))&0x30)==(0x20||0x30))&&(((per.l(ad:0x40038000+0x54))&0x04)==0x00)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x40038000))&0x20)==0x20)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x04)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x40038000))&0x20)==0x20)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x00)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x50000)==0x10000)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x04)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x50000)==0x10000)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x00)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x50000)==0x40000)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x04)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x50000)==0x40000)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x00)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x34++0x03 hide.long 0x00 "C5SC,Channel (5) Status And Control" endif group.long (0x34+0x04)++0x03 line.long 0x00 "C5V,Channel (5) Value" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" if ((((per.l(ad:0x40038000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x3C))&0x30)==0x00)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x04)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x3C))&0x30)==0x00)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x00)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x3C))&0x30)==0x10)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x04)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x3C))&0x30)==0x10)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x00)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x3C))&0x30)==(0x20||0x30))&&(((per.l(ad:0x40038000+0x54))&0x04)==0x04)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x3C))&0x30)==(0x20||0x30))&&(((per.l(ad:0x40038000+0x54))&0x04)==0x00)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x40038000))&0x20)==0x20)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x04)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x40038000))&0x20)==0x20)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x00)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x5000000)==0x1000000)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x04)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x5000000)==0x1000000)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x00)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x5000000)==0x4000000)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x04)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x5000000)==0x4000000)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x00)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x3C++0x03 hide.long 0x00 "C6SC,Channel (6) Status And Control" endif group.long (0x3C+0x04)++0x03 line.long 0x00 "C6V,Channel (6) Value" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" if ((((per.l(ad:0x40038000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x44))&0x30)==0x00)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x04)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x44))&0x30)==0x00)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x00)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x44))&0x30)==0x10)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x04)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x44))&0x30)==0x10)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x00)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x44))&0x30)==(0x20||0x30))&&(((per.l(ad:0x40038000+0x54))&0x04)==0x04)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x44))&0x30)==(0x20||0x30))&&(((per.l(ad:0x40038000+0x54))&0x04)==0x00)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x40038000))&0x20)==0x20)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x04)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x40038000))&0x20)==0x20)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x00)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x5000000)==0x1000000)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x04)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x5000000)==0x1000000)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x00)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x5000000)==0x4000000)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x04)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40038000+0x64))&0x5000000)==0x4000000)&&(((per.l(ad:0x40038000))&0x20)==0x00)&&(((per.l(ad:0x40038000+0x54))&0x04)==0x00)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x44++0x03 hide.long 0x00 "C7SC,Channel (7) Status And Control" endif group.long (0x44+0x04)++0x03 line.long 0x00 "C7V,Channel (7) Value" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" newline group.long 0x4C++0x03 line.long 0x00 "CNTIN,Counter Initial Value" hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial value of the FTM counter" hgroup.long 0x50++0x03 hide.long 0x00 "STATUS,Capture And Compare Status" in if (((per.l(ad:0x40038000+0x54))&0x04)==0x04) group.long 0x54++0x03 line.long 0x00 "MODE,Features Mode Selection" bitfld.long 0x00 7. " FAULTIE ,Fault Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5.--6. " FAULTM ,Fault Control Mode" "Disabled,Enabled for even channels/Manual clear,Enabled for all channels/Manual clear,Enabled for all channels/Automatic clear" bitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode" "Disabled,Enabled" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialized" bitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" else group.long 0x54++0x03 line.long 0x00 "MODE,Features Mode Selection" bitfld.long 0x00 7. " FAULTIE ,Fault Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 5.--6. " FAULTM ,Fault Control Mode" "Disabled,Enabled for even channels/Manual clear,Enabled for all channels/Manual clear,Enabled for all channels/Automatic clear" rbitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode" "Disabled,Enabled" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialized" rbitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" endif newline group.long 0x58++0x0B line.long 0x00 "SYNC,Synchronization" bitfld.long 0x00 7. " SWSYNC ,PWM synchronization software trigger" "Not selected,Selected" bitfld.long 0x00 6. " TRIG2 ,PWM synchronization hardware trigger 2" "Disabled,Enabled" bitfld.long 0x00 5. " TRIG1 ,PWM synchronization hardware trigger 1" "Disabled,Enabled" bitfld.long 0x00 4. " TRIG0 ,PWM synchronization hardware trigger 0" "Disabled,Enabled" newline bitfld.long 0x00 3. " SYNCHOM ,Output mask synchronization" "At rising edges of system clock,PWM synchronization" bitfld.long 0x00 2. " REINIT ,FTM counter reinitialization by synchronization" "Count normally,Trigger detected" bitfld.long 0x00 1. " CNTMAX ,Maximum loading point enable" "Disabled,Enabled" bitfld.long 0x00 0. " CNTMIN ,Minimum loading point enable" "Disabled,Enabled" line.long 0x04 "OUTINIT,Initial State For Channels Output" bitfld.long 0x04 7. " CH7OI ,Channel 7 output initialization value" "0,1" bitfld.long 0x04 6. " CH6OI ,Channel 6 output initialization value" "0,1" bitfld.long 0x04 5. " CH5OI ,Channel 5 output initialization value" "0,1" bitfld.long 0x04 4. " CH4OI ,Channel 4 output initialization value" "0,1" newline bitfld.long 0x04 3. " CH3OI ,Channel 3 output initialization value" "0,1" bitfld.long 0x04 2. " CH2OI ,Channel 2 output initialization value" "0,1" bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1" bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1" line.long 0x08 "OUTMASK,Output Mask" bitfld.long 0x08 7. " CH7OM ,Channel 7 output mask" "Not masked,Masked" bitfld.long 0x08 6. " CH6OM ,Channel 6 output mask" "Not masked,Masked" bitfld.long 0x08 5. " CH5OM ,Channel 5 output mask" "Not masked,Masked" bitfld.long 0x08 4. " CH4OM ,Channel 4 output mask" "Not masked,Masked" newline bitfld.long 0x08 3. " CH3OM ,Channel 3 output mask" "Not masked,Masked" bitfld.long 0x08 2. " CH2OM ,Channel 2 output mask" "Not masked,Masked" bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked" bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked" if (((per.l(ad:0x40038000+0x54))&0x04)==0x04) group.long 0x64++0x07 line.long 0x00 "COMBINE,Function For Linked Channels" bitfld.long 0x00 30. " FAULTEN3 ,Fault Control Enable For n = 6" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,Synchronization enable for n = 6" "Disabled,Enabled" bitfld.long 0x00 28. " DTEN3 ,Deadtime enable for n = 6" "Disabled,Enabled" bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures for n = 6" "Inactive,Active" newline bitfld.long 0x00 26. " DECAPEN3 ,Dual Edge Capture Mode Enable for n = 6" "Disabled,Enabled" bitfld.long 0x00 25. " COMP3 ,Complement of channel (N) for n = 6" "Same,Complemented" bitfld.long 0x00 24. " COMBINE3 ,Combine channels for n = 6" "Independed,Combined" bitfld.long 0x00 22. " FAULTEN2 ,Fault Control Enable For n = 4" "Disabled,Enabled" newline bitfld.long 0x00 21. " SYNCEN2 ,Synchronization enable for n = 4" "Disabled,Enabled" bitfld.long 0x00 20. " DTEN2 ,Deadtime enable for n = 4" "Disabled,Enabled" bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures for n = 4" "Inactive,Active" bitfld.long 0x00 18. " DECAPEN2 ,Dual Edge Capture Mode Enable for n = 4" "Disabled,Enabled" newline bitfld.long 0x00 17. " COMP2 ,Complement of channel (N) for n = 4" "Same,Complemented" bitfld.long 0x00 16. " COMBINE2 ,Combine channels for n = 4" "Independed,Combined" bitfld.long 0x00 14. " FAULTEN1 ,Fault Control Enable For n = 2" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,Synchronization enable for n = 2" "Disabled,Enabled" newline bitfld.long 0x00 12. " DTEN1 ,Deadtime enable for n = 2" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures for n = 2" "Inactive,Active" bitfld.long 0x00 10. " DECAPEN1 ,Dual Edge Capture Mode Enable for n = 2" "Disabled,Enabled" bitfld.long 0x00 9. " COMP1 ,Complement of channel (N) for n = 2" "Same,Complemented" newline bitfld.long 0x00 8. " COMBINE1 ,Combine channels for n = 2" "Independed,Combined" bitfld.long 0x00 6. " FAULTEN0 ,Fault Control Enable For n = 0" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,Synchronization enable for n = 0" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime enable for n = 0" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures for n = 0" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual Edge Capture Mode Enable for n = 0" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complement of channel (N) for n = 0" "Same,Complemented" bitfld.long 0x00 0. " COMBINE0 ,Combine channels for n = 0" "Independed,Combined" line.long 0x04 "DEADTIME,Deadtime Insertion Control" bitfld.long 0x04 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x04 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x64++0x03 line.long 0x00 "COMBINE,Function For Linked Channels" rbitfld.long 0x00 30. " FAULTEN3 ,Fault Control Enable For n = 6" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,Synchronization enable for n = 6" "Disabled,Enabled" rbitfld.long 0x00 28. " DTEN3 ,Deadtime enable for n = 6" "Disabled,Enabled" bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures for n = 6" "Inactive,Active" newline rbitfld.long 0x00 26. " DECAPEN3 ,Dual Edge Capture Mode Enable for n = 6" "Disabled,Enabled" rbitfld.long 0x00 25. " COMP3 ,Complement of channel (N) for n = 6" "Same,Complemented" rbitfld.long 0x00 24. " COMBINE3 ,Combine channels for n = 6" "Independed,Combined" rbitfld.long 0x00 22. " FAULTEN2 ,Fault Control Enable For n = 4" "Disabled,Enabled" newline bitfld.long 0x00 21. " SYNCEN2 ,Synchronization enable for n = 4" "Disabled,Enabled" rbitfld.long 0x00 20. " DTEN2 ,Deadtime enable for n = 4" "Disabled,Enabled" bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures for n = 4" "Inactive,Active" rbitfld.long 0x00 18. " DECAPEN2 ,Dual Edge Capture Mode Enable for n = 4" "Disabled,Enabled" newline rbitfld.long 0x00 17. " COMP2 ,Complement of channel (N) for n = 4" "Same,Complemented" rbitfld.long 0x00 16. " COMBINE2 ,Combine channels for n = 4" "Independed,Combined" rbitfld.long 0x00 14. " FAULTEN1 ,Fault Control Enable For n = 2" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,Synchronization enable for n = 2" "Disabled,Enabled" newline rbitfld.long 0x00 12. " DTEN1 ,Deadtime enable for n = 2" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures for n = 2" "Inactive,Active" rbitfld.long 0x00 10. " DECAPEN1 ,Dual Edge Capture Mode Enable for n = 2" "Disabled,Enabled" rbitfld.long 0x00 9. " COMP1 ,Complement of channel (N) for n = 2" "Same,Complemented" newline rbitfld.long 0x00 8. " COMBINE1 ,Combine channels for n = 2" "Independed,Combined" rbitfld.long 0x00 6. " FAULTEN0 ,Fault Control Enable For n = 0" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,Synchronization enable for n = 0" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable for n = 0" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures for n = 0" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual Edge Capture Mode Enable for n = 0" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complement of channel (N) for n = 0" "Same,Complemented" rbitfld.long 0x00 0. " COMBINE0 ,Combine channels for n = 0" "Independed,Combined" rgroup.long 0x68++0x03 line.long 0x00 "DEADTIME,Deadtime Insertion Control" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x6C++0x03 line.long 0x00 "EXTTRIG,FTM External Trigger" rbitfld.long 0x00 7. " TRIGF ,Channel trigger flag" "Not occurred,Occurred" bitfld.long 0x00 6. " INITTRIGEN ,Initialization trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " CH1TRIG ,Channel 1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 4. " CH0TRIG ,Channel 0 trigger enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " CH5TRIG ,Channel 5 trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " CH4TRIG ,Channel 4 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " CH3TRIG ,Channel 3 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " CH2TRIG ,Channel 2 trigger enable" "Disabled,Enabled" if (((per.l(ad:0x40038000+0x54))&0x04)==0x04) group.long 0x70++0x03 line.long 0x00 "POL,Channels Polarity" bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "High,Low" bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "High,Low" bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "High,Low" bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "High,Low" newline bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "High,Low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "High,Low" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "High,Low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "High,Low" else rgroup.long 0x70++0x03 line.long 0x00 "POL,Channels Polarity" bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "High,Low" bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "High,Low" bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "High,Low" bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "High,Low" newline bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "High,Low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "High,Low" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "High,Low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "High,Low" endif hgroup.long 0x74++0x03 hide.long 0x00 "FMS,Fault Mode Status" in newline group.long 0x78++0x03 line.long 0x00 "FILTER,Input Capture Filter Control" bitfld.long 0x00 12.--15. " CH3FVAL ,Channel 3 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " CH2FVAL ,Channel 2 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (((per.l(ad:0x40038000+0x54))&0x04)==0x04) group.long 0x7C++0x03 line.long 0x00 "FLTCTRL,Fault Control" bitfld.long 0x00 8.--11. " FFVAL ,Fault Input Filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " FFLTR3EN ,Fault Input 3 Filter Enable" "Disabled,Enabled" bitfld.long 0x00 6. " FFLTR2EN ,Fault Input 2 Filter Enable" "Disabled,Enabled" bitfld.long 0x00 5. " FFLTR1EN ,Fault Input 1 Filter Enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " FFLTR0EN ,Fault Input 0 Filter Enable" "Disabled,Enabled" bitfld.long 0x00 3. " FAULT3EN ,Fault Input 3 Enable" "Disabled,Enabled" bitfld.long 0x00 2. " FAULT2EN ,Fault Input 2 Enable" "Disabled,Enabled" bitfld.long 0x00 1. " FAULT1EN ,Fault Input 1 Enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " FAULT0EN ,Fault Input 0 Enable" "Disabled,Enabled" else group.long 0x7C++0x03 line.long 0x00 "FLTCTRL,Fault Control" bitfld.long 0x00 8.--11. " FFVAL ,Fault Input Filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 7. " FFLTR3EN ,Fault Input 3 Filter Enable" "Disabled,Enabled" rbitfld.long 0x00 6. " FFLTR2EN ,Fault Input 2 Filter Enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FFLTR1EN ,Fault Input 1 Filter Enable" "Disabled,Enabled" newline rbitfld.long 0x00 4. " FFLTR0EN ,Fault Input 0 Filter Enable" "Disabled,Enabled" rbitfld.long 0x00 3. " FAULT3EN ,Fault Input 3 Enable" "Disabled,Enabled" rbitfld.long 0x00 2. " FAULT2EN ,Fault Input 2 Enable" "Disabled,Enabled" rbitfld.long 0x00 1. " FAULT1EN ,Fault Input 1 Enable" "Disabled,Enabled" newline rbitfld.long 0x00 0. " FAULT0EN ,Fault Input 0 Enable" "Disabled,Enabled" endif if (((per.l(ad:0x40038000+0x54))&0x04)==0x04) group.long 0x80++0x03 line.long 0x00 "QDCTRL,Quadrature Decoder Control And Status" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" newline bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "A and B encoding,Count and direction encoding" rbitfld.long 0x00 2. " QUADIR ,FTM counter direction in quadrature decoder mode" "Decreasing,Increasing" rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Bottom,Top" bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "QDCTRL,Quadrature Decoder Control And Status" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" newline bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "A and B encoding,Count and direction encoding" rbitfld.long 0x00 2. " QUADIR ,FTM counter direction in quadrature decoder mode" "Decreasing,Increasing" rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Bottom,Top" rbitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "CONF,Configuration" bitfld.long 0x00 10. " GTBEOUT ,Global time base output" "Disabled,Enabled" bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " BDMMODE ,Selects the FTM behavior in BDM mode" "0,1,2,3" bitfld.long 0x00 0.--4. " NUMTOF ,Selects the ratio between the number of counter overflows to the number of times the TOF bit is set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x40038000+0x54))&0x04)==0x04) group.long 0x88++0x03 line.long 0x00 "FLTPOL,FTM Fault Input Polarity" bitfld.long 0x00 3. " FLT3POL ,Fault Input 3 Polarity" "Active high,Active low" bitfld.long 0x00 2. " FLT2POL ,Fault Input 2 Polarity" "Active high,Active low" bitfld.long 0x00 1. " FLT1POL ,Fault Input 1 Polarity" "Active high,Active low" bitfld.long 0x00 0. " FLT0POL ,Fault Input 0 Polarity" "Active high,Active low" else rgroup.long 0x88++0x03 line.long 0x00 "FLTPOL,FTM Fault Input Polarity" bitfld.long 0x00 3. " FLT3POL ,Fault Input 3 Polarity" "Active high,Active low" bitfld.long 0x00 2. " FLT2POL ,Fault Input 2 Polarity" "Active high,Active low" bitfld.long 0x00 1. " FLT1POL ,Fault Input 1 Polarity" "Active high,Active low" bitfld.long 0x00 0. " FLT0POL ,Fault Input 0 Polarity" "Active high,Active low" endif group.long 0x8C++0x0F line.long 0x00 "SYNCONF,Synchronization Configuration" bitfld.long 0x00 20. " HWSOC ,Software output control synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 18. " HWOM ,Output mask synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 17. " HWWRBUF ,MOD CNTIN and CV registers synchronization is activated by a hardware trigger" "Not activated,Activated" newline bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 12. " SWSOC ,Software output control synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 10. " SWOM ,Output mask synchronization is activated by the software trigger" "Not activated,Activated" newline bitfld.long 0x00 9. " SWWRBUF ,MOD CNTIN and CV registers synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 7. " SYNCMODE ,Synchronization mode" "Legacy PWM,Enhanced PWM" bitfld.long 0x00 5. " SWOC ,SWOCTRL register synchronization" "At rising edges of system clock,PWM synchronization" newline bitfld.long 0x00 4. " INVC ,INVCTRL register synchronization" "At rising edges of system clock,PWM synchronization" bitfld.long 0x00 2. " CNTINC ,CNTIN register synchronization" "At rising edges of system clock,PWM synchronization" bitfld.long 0x00 0. " HWTRIGMODE ,Hardware trigger mode" "Cleared,Not cleared" line.long 0x04 "INVCTRL,FTM Inverting Control" bitfld.long 0x04 3. " INV3EN ,Pair channels 3 inverting enable" "Disabled,Enabled" bitfld.long 0x04 2. " INV2EN ,Pair channels 2 inverting enable" "Disabled,Enabled" bitfld.long 0x04 1. " INV1EN ,Pair channels 1 inverting enable" "Disabled,Enabled" bitfld.long 0x04 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled" line.long 0x08 "SWOCTRL,FTM Software Output Control" bitfld.long 0x08 15. " CH7OCV ,Channel 7 software output control value" "Force 0,Force 1" bitfld.long 0x08 14. " CH6OCV ,Channel 6 software output control value" "Force 0,Force 1" bitfld.long 0x08 13. " CH5OCV ,Channel 5 software output control value" "Force 0,Force 1" bitfld.long 0x08 12. " CH4OCV ,Channel 4 software output control value" "Force 0,Force 1" newline bitfld.long 0x08 11. " CH3OCV ,Channel 3 software output control value" "Force 0,Force 1" bitfld.long 0x08 10. " CH2OCV ,Channel 2 software output control value" "Force 0,Force 1" bitfld.long 0x08 9. " CH1OCV ,Channel 1 software output control value" "Force 0,Force 1" bitfld.long 0x08 8. " CH0OCV ,Channel 0 software output control value" "Force 0,Force 1" newline bitfld.long 0x08 7. " CH7OC ,Channel 7 software output control enable" "Disabled,Enabled" bitfld.long 0x08 6. " CH6OC ,Channel 6 software output control enable" "Disabled,Enabled" bitfld.long 0x08 5. " CH5OC ,Channel 5 software output control enable" "Disabled,Enabled" bitfld.long 0x08 4. " CH4OC ,Channel 4 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled" bitfld.long 0x08 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled" bitfld.long 0x08 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled" bitfld.long 0x08 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled" line.long 0x0C "PWMLOAD,FTM PWM Load" bitfld.long 0x0C 9. " LDOK ,Load enable" "Disabled,Enabled" newline bitfld.long 0x0C 7. " CH7SEL ,Channel 7 select" "Not included,Included" bitfld.long 0x0C 6. " CH6SEL ,Channel 6 select" "Not included,Included" bitfld.long 0x0C 5. " CH5SEL ,Channel 5 select" "Not included,Included" bitfld.long 0x0C 4. " CH4SEL ,Channel 4 select" "Not included,Included" newline bitfld.long 0x0C 3. " CH3SEL ,Channel 3 select" "Not included,Included" bitfld.long 0x0C 2. " CH2SEL ,Channel 2 select" "Not included,Included" bitfld.long 0x0C 1. " CH1SEL ,Channel 1 select" "Not included,Included" bitfld.long 0x0C 0. " CH0SEL ,Channel 0 select" "Not included,Included" width 0x0B tree.end tree "FTM_1" base ad:0x40039000 width 10. if (((per.l(ad:0x40039000+0x54))&0x04)==0x04) group.long 0x00++0x03 line.long 0x00 "SC,Status And Control" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " CPWMS ,Center-Aligned PWM select" "Up counting mode,Up-Down counting mode" bitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clock,System clock,Fixed frequency clock,External clock" newline bitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" else group.long 0x00++0x03 line.long 0x00 "SC,Status And Control" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " CPWMS ,Center-Aligned PWM select" "Up counting mode,Up-Down counting mode" rbitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clock,System clock,Fixed frequency clock,External clock" newline rbitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" endif group.long 0x04++0x07 line.long 0x00 "CNT,Counter" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" line.long 0x04 "MOD,Modulo" hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value" if ((((per.l(ad:0x40039000+0x64))&0x05)==0x00)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0xC))&0x30)==0x00)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x04)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x05)==0x00)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0xC))&0x30)==0x00)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x00)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x05)==0x00)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0xC))&0x30)==0x10)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x04)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x05)==0x00)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0xC))&0x30)==0x10)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x00)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x05)==0x00)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0xC))&0x30)==(0x20||0x30))&&(((per.l(ad:0x40039000+0x54))&0x04)==0x04)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x05)==0x00)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0xC))&0x30)==(0x20||0x30))&&(((per.l(ad:0x40039000+0x54))&0x04)==0x00)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x05)==0x00)&&(((per.l(ad:0x40039000))&0x20)==0x20)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x04)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x05)==0x00)&&(((per.l(ad:0x40039000))&0x20)==0x20)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x00)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x05)==0x01)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x04)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x05)==0x01)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x00)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x05)==0x04)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x04)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x05)==0x04)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x00)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0xC++0x03 hide.long 0x00 "C0SC,Channel (0) Status And Control" endif group.long (0xC+0x04)++0x03 line.long 0x00 "C0V,Channel (0) Value" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" if ((((per.l(ad:0x40039000+0x64))&0x05)==0x00)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x14))&0x30)==0x00)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x04)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x05)==0x00)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x14))&0x30)==0x00)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x00)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x05)==0x00)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x14))&0x30)==0x10)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x04)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x05)==0x00)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x14))&0x30)==0x10)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x00)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x05)==0x00)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x14))&0x30)==(0x20||0x30))&&(((per.l(ad:0x40039000+0x54))&0x04)==0x04)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x05)==0x00)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x14))&0x30)==(0x20||0x30))&&(((per.l(ad:0x40039000+0x54))&0x04)==0x00)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x05)==0x00)&&(((per.l(ad:0x40039000))&0x20)==0x20)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x04)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x05)==0x00)&&(((per.l(ad:0x40039000))&0x20)==0x20)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x00)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x05)==0x01)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x04)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x05)==0x01)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x00)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x05)==0x04)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x04)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x05)==0x04)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x00)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x14++0x03 hide.long 0x00 "C1SC,Channel (1) Status And Control" endif group.long (0x14+0x04)++0x03 line.long 0x00 "C1V,Channel (1) Value" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" if ((((per.l(ad:0x40039000+0x64))&0x500)==0x00)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x1C))&0x30)==0x00)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x04)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x500)==0x00)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x1C))&0x30)==0x00)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x00)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x500)==0x00)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x1C))&0x30)==0x10)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x04)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x500)==0x00)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x1C))&0x30)==0x10)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x00)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x500)==0x00)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x1C))&0x30)==(0x20||0x30))&&(((per.l(ad:0x40039000+0x54))&0x04)==0x04)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x500)==0x00)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x1C))&0x30)==(0x20||0x30))&&(((per.l(ad:0x40039000+0x54))&0x04)==0x00)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x500)==0x00)&&(((per.l(ad:0x40039000))&0x20)==0x20)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x04)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x500)==0x00)&&(((per.l(ad:0x40039000))&0x20)==0x20)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x00)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x500)==0x100)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x04)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x500)==0x100)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x00)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x500)==0x400)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x04)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x500)==0x400)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x00)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x1C++0x03 hide.long 0x00 "C2SC,Channel (2) Status And Control" endif group.long (0x1C+0x04)++0x03 line.long 0x00 "C2V,Channel (2) Value" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" if ((((per.l(ad:0x40039000+0x64))&0x500)==0x00)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x24))&0x30)==0x00)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x04)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x500)==0x00)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x24))&0x30)==0x00)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x00)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x500)==0x00)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x24))&0x30)==0x10)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x04)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x500)==0x00)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x24))&0x30)==0x10)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x00)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x500)==0x00)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x24))&0x30)==(0x20||0x30))&&(((per.l(ad:0x40039000+0x54))&0x04)==0x04)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x500)==0x00)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x24))&0x30)==(0x20||0x30))&&(((per.l(ad:0x40039000+0x54))&0x04)==0x00)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x500)==0x00)&&(((per.l(ad:0x40039000))&0x20)==0x20)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x04)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x500)==0x00)&&(((per.l(ad:0x40039000))&0x20)==0x20)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x00)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x500)==0x100)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x04)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x500)==0x100)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x00)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x500)==0x400)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x04)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x500)==0x400)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x00)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x24++0x03 hide.long 0x00 "C3SC,Channel (3) Status And Control" endif group.long (0x24+0x04)++0x03 line.long 0x00 "C3V,Channel (3) Value" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" if ((((per.l(ad:0x40039000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x2C))&0x30)==0x00)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x04)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x2C))&0x30)==0x00)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x00)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x2C))&0x30)==0x10)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x04)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x2C))&0x30)==0x10)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x00)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x2C))&0x30)==(0x20||0x30))&&(((per.l(ad:0x40039000+0x54))&0x04)==0x04)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x2C))&0x30)==(0x20||0x30))&&(((per.l(ad:0x40039000+0x54))&0x04)==0x00)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x40039000))&0x20)==0x20)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x04)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x40039000))&0x20)==0x20)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x00)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x50000)==0x10000)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x04)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x50000)==0x10000)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x00)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x50000)==0x40000)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x04)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x50000)==0x40000)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x00)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x2C++0x03 hide.long 0x00 "C4SC,Channel (4) Status And Control" endif group.long (0x2C+0x04)++0x03 line.long 0x00 "C4V,Channel (4) Value" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" if ((((per.l(ad:0x40039000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x34))&0x30)==0x00)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x04)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x34))&0x30)==0x00)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x00)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x34))&0x30)==0x10)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x04)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x34))&0x30)==0x10)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x00)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x34))&0x30)==(0x20||0x30))&&(((per.l(ad:0x40039000+0x54))&0x04)==0x04)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x34))&0x30)==(0x20||0x30))&&(((per.l(ad:0x40039000+0x54))&0x04)==0x00)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x40039000))&0x20)==0x20)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x04)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x40039000))&0x20)==0x20)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x00)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x50000)==0x10000)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x04)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x50000)==0x10000)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x00)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x50000)==0x40000)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x04)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x50000)==0x40000)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x00)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x34++0x03 hide.long 0x00 "C5SC,Channel (5) Status And Control" endif group.long (0x34+0x04)++0x03 line.long 0x00 "C5V,Channel (5) Value" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" if ((((per.l(ad:0x40039000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x3C))&0x30)==0x00)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x04)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x3C))&0x30)==0x00)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x00)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x3C))&0x30)==0x10)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x04)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x3C))&0x30)==0x10)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x00)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x3C))&0x30)==(0x20||0x30))&&(((per.l(ad:0x40039000+0x54))&0x04)==0x04)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x3C))&0x30)==(0x20||0x30))&&(((per.l(ad:0x40039000+0x54))&0x04)==0x00)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x40039000))&0x20)==0x20)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x04)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x40039000))&0x20)==0x20)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x00)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x5000000)==0x1000000)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x04)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x5000000)==0x1000000)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x00)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x5000000)==0x4000000)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x04)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x5000000)==0x4000000)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x00)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x3C++0x03 hide.long 0x00 "C6SC,Channel (6) Status And Control" endif group.long (0x3C+0x04)++0x03 line.long 0x00 "C6V,Channel (6) Value" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" if ((((per.l(ad:0x40039000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x44))&0x30)==0x00)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x04)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x44))&0x30)==0x00)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x00)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x44))&0x30)==0x10)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x04)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x44))&0x30)==0x10)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x00)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x44))&0x30)==(0x20||0x30))&&(((per.l(ad:0x40039000+0x54))&0x04)==0x04)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x44))&0x30)==(0x20||0x30))&&(((per.l(ad:0x40039000+0x54))&0x04)==0x00)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x40039000))&0x20)==0x20)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x04)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x40039000))&0x20)==0x20)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x00)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x5000000)==0x1000000)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x04)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x5000000)==0x1000000)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x00)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x5000000)==0x4000000)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x04)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x40039000+0x64))&0x5000000)==0x4000000)&&(((per.l(ad:0x40039000))&0x20)==0x00)&&(((per.l(ad:0x40039000+0x54))&0x04)==0x00)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x44++0x03 hide.long 0x00 "C7SC,Channel (7) Status And Control" endif group.long (0x44+0x04)++0x03 line.long 0x00 "C7V,Channel (7) Value" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" newline group.long 0x4C++0x03 line.long 0x00 "CNTIN,Counter Initial Value" hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial value of the FTM counter" hgroup.long 0x50++0x03 hide.long 0x00 "STATUS,Capture And Compare Status" in if (((per.l(ad:0x40039000+0x54))&0x04)==0x04) group.long 0x54++0x03 line.long 0x00 "MODE,Features Mode Selection" bitfld.long 0x00 7. " FAULTIE ,Fault Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5.--6. " FAULTM ,Fault Control Mode" "Disabled,Enabled for even channels/Manual clear,Enabled for all channels/Manual clear,Enabled for all channels/Automatic clear" bitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode" "Disabled,Enabled" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialized" bitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" else group.long 0x54++0x03 line.long 0x00 "MODE,Features Mode Selection" bitfld.long 0x00 7. " FAULTIE ,Fault Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 5.--6. " FAULTM ,Fault Control Mode" "Disabled,Enabled for even channels/Manual clear,Enabled for all channels/Manual clear,Enabled for all channels/Automatic clear" rbitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode" "Disabled,Enabled" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialized" rbitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" endif newline group.long 0x58++0x0B line.long 0x00 "SYNC,Synchronization" bitfld.long 0x00 7. " SWSYNC ,PWM synchronization software trigger" "Not selected,Selected" bitfld.long 0x00 6. " TRIG2 ,PWM synchronization hardware trigger 2" "Disabled,Enabled" bitfld.long 0x00 5. " TRIG1 ,PWM synchronization hardware trigger 1" "Disabled,Enabled" bitfld.long 0x00 4. " TRIG0 ,PWM synchronization hardware trigger 0" "Disabled,Enabled" newline bitfld.long 0x00 3. " SYNCHOM ,Output mask synchronization" "At rising edges of system clock,PWM synchronization" bitfld.long 0x00 2. " REINIT ,FTM counter reinitialization by synchronization" "Count normally,Trigger detected" bitfld.long 0x00 1. " CNTMAX ,Maximum loading point enable" "Disabled,Enabled" bitfld.long 0x00 0. " CNTMIN ,Minimum loading point enable" "Disabled,Enabled" line.long 0x04 "OUTINIT,Initial State For Channels Output" bitfld.long 0x04 7. " CH7OI ,Channel 7 output initialization value" "0,1" bitfld.long 0x04 6. " CH6OI ,Channel 6 output initialization value" "0,1" bitfld.long 0x04 5. " CH5OI ,Channel 5 output initialization value" "0,1" bitfld.long 0x04 4. " CH4OI ,Channel 4 output initialization value" "0,1" newline bitfld.long 0x04 3. " CH3OI ,Channel 3 output initialization value" "0,1" bitfld.long 0x04 2. " CH2OI ,Channel 2 output initialization value" "0,1" bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1" bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1" line.long 0x08 "OUTMASK,Output Mask" bitfld.long 0x08 7. " CH7OM ,Channel 7 output mask" "Not masked,Masked" bitfld.long 0x08 6. " CH6OM ,Channel 6 output mask" "Not masked,Masked" bitfld.long 0x08 5. " CH5OM ,Channel 5 output mask" "Not masked,Masked" bitfld.long 0x08 4. " CH4OM ,Channel 4 output mask" "Not masked,Masked" newline bitfld.long 0x08 3. " CH3OM ,Channel 3 output mask" "Not masked,Masked" bitfld.long 0x08 2. " CH2OM ,Channel 2 output mask" "Not masked,Masked" bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked" bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked" if (((per.l(ad:0x40039000+0x54))&0x04)==0x04) group.long 0x64++0x07 line.long 0x00 "COMBINE,Function For Linked Channels" bitfld.long 0x00 30. " FAULTEN3 ,Fault Control Enable For n = 6" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,Synchronization enable for n = 6" "Disabled,Enabled" bitfld.long 0x00 28. " DTEN3 ,Deadtime enable for n = 6" "Disabled,Enabled" bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures for n = 6" "Inactive,Active" newline bitfld.long 0x00 26. " DECAPEN3 ,Dual Edge Capture Mode Enable for n = 6" "Disabled,Enabled" bitfld.long 0x00 25. " COMP3 ,Complement of channel (N) for n = 6" "Same,Complemented" bitfld.long 0x00 24. " COMBINE3 ,Combine channels for n = 6" "Independed,Combined" bitfld.long 0x00 22. " FAULTEN2 ,Fault Control Enable For n = 4" "Disabled,Enabled" newline bitfld.long 0x00 21. " SYNCEN2 ,Synchronization enable for n = 4" "Disabled,Enabled" bitfld.long 0x00 20. " DTEN2 ,Deadtime enable for n = 4" "Disabled,Enabled" bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures for n = 4" "Inactive,Active" bitfld.long 0x00 18. " DECAPEN2 ,Dual Edge Capture Mode Enable for n = 4" "Disabled,Enabled" newline bitfld.long 0x00 17. " COMP2 ,Complement of channel (N) for n = 4" "Same,Complemented" bitfld.long 0x00 16. " COMBINE2 ,Combine channels for n = 4" "Independed,Combined" bitfld.long 0x00 14. " FAULTEN1 ,Fault Control Enable For n = 2" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,Synchronization enable for n = 2" "Disabled,Enabled" newline bitfld.long 0x00 12. " DTEN1 ,Deadtime enable for n = 2" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures for n = 2" "Inactive,Active" bitfld.long 0x00 10. " DECAPEN1 ,Dual Edge Capture Mode Enable for n = 2" "Disabled,Enabled" bitfld.long 0x00 9. " COMP1 ,Complement of channel (N) for n = 2" "Same,Complemented" newline bitfld.long 0x00 8. " COMBINE1 ,Combine channels for n = 2" "Independed,Combined" bitfld.long 0x00 6. " FAULTEN0 ,Fault Control Enable For n = 0" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,Synchronization enable for n = 0" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime enable for n = 0" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures for n = 0" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual Edge Capture Mode Enable for n = 0" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complement of channel (N) for n = 0" "Same,Complemented" bitfld.long 0x00 0. " COMBINE0 ,Combine channels for n = 0" "Independed,Combined" line.long 0x04 "DEADTIME,Deadtime Insertion Control" bitfld.long 0x04 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x04 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x64++0x03 line.long 0x00 "COMBINE,Function For Linked Channels" rbitfld.long 0x00 30. " FAULTEN3 ,Fault Control Enable For n = 6" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,Synchronization enable for n = 6" "Disabled,Enabled" rbitfld.long 0x00 28. " DTEN3 ,Deadtime enable for n = 6" "Disabled,Enabled" bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures for n = 6" "Inactive,Active" newline rbitfld.long 0x00 26. " DECAPEN3 ,Dual Edge Capture Mode Enable for n = 6" "Disabled,Enabled" rbitfld.long 0x00 25. " COMP3 ,Complement of channel (N) for n = 6" "Same,Complemented" rbitfld.long 0x00 24. " COMBINE3 ,Combine channels for n = 6" "Independed,Combined" rbitfld.long 0x00 22. " FAULTEN2 ,Fault Control Enable For n = 4" "Disabled,Enabled" newline bitfld.long 0x00 21. " SYNCEN2 ,Synchronization enable for n = 4" "Disabled,Enabled" rbitfld.long 0x00 20. " DTEN2 ,Deadtime enable for n = 4" "Disabled,Enabled" bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures for n = 4" "Inactive,Active" rbitfld.long 0x00 18. " DECAPEN2 ,Dual Edge Capture Mode Enable for n = 4" "Disabled,Enabled" newline rbitfld.long 0x00 17. " COMP2 ,Complement of channel (N) for n = 4" "Same,Complemented" rbitfld.long 0x00 16. " COMBINE2 ,Combine channels for n = 4" "Independed,Combined" rbitfld.long 0x00 14. " FAULTEN1 ,Fault Control Enable For n = 2" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,Synchronization enable for n = 2" "Disabled,Enabled" newline rbitfld.long 0x00 12. " DTEN1 ,Deadtime enable for n = 2" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures for n = 2" "Inactive,Active" rbitfld.long 0x00 10. " DECAPEN1 ,Dual Edge Capture Mode Enable for n = 2" "Disabled,Enabled" rbitfld.long 0x00 9. " COMP1 ,Complement of channel (N) for n = 2" "Same,Complemented" newline rbitfld.long 0x00 8. " COMBINE1 ,Combine channels for n = 2" "Independed,Combined" rbitfld.long 0x00 6. " FAULTEN0 ,Fault Control Enable For n = 0" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,Synchronization enable for n = 0" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable for n = 0" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures for n = 0" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual Edge Capture Mode Enable for n = 0" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complement of channel (N) for n = 0" "Same,Complemented" rbitfld.long 0x00 0. " COMBINE0 ,Combine channels for n = 0" "Independed,Combined" rgroup.long 0x68++0x03 line.long 0x00 "DEADTIME,Deadtime Insertion Control" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x6C++0x03 line.long 0x00 "EXTTRIG,FTM External Trigger" rbitfld.long 0x00 7. " TRIGF ,Channel trigger flag" "Not occurred,Occurred" bitfld.long 0x00 6. " INITTRIGEN ,Initialization trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " CH1TRIG ,Channel 1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 4. " CH0TRIG ,Channel 0 trigger enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " CH5TRIG ,Channel 5 trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " CH4TRIG ,Channel 4 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " CH3TRIG ,Channel 3 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " CH2TRIG ,Channel 2 trigger enable" "Disabled,Enabled" if (((per.l(ad:0x40039000+0x54))&0x04)==0x04) group.long 0x70++0x03 line.long 0x00 "POL,Channels Polarity" bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "High,Low" bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "High,Low" bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "High,Low" bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "High,Low" newline bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "High,Low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "High,Low" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "High,Low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "High,Low" else rgroup.long 0x70++0x03 line.long 0x00 "POL,Channels Polarity" bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "High,Low" bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "High,Low" bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "High,Low" bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "High,Low" newline bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "High,Low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "High,Low" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "High,Low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "High,Low" endif hgroup.long 0x74++0x03 hide.long 0x00 "FMS,Fault Mode Status" in newline group.long 0x78++0x03 line.long 0x00 "FILTER,Input Capture Filter Control" bitfld.long 0x00 12.--15. " CH3FVAL ,Channel 3 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " CH2FVAL ,Channel 2 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (((per.l(ad:0x40039000+0x54))&0x04)==0x04) group.long 0x7C++0x03 line.long 0x00 "FLTCTRL,Fault Control" bitfld.long 0x00 8.--11. " FFVAL ,Fault Input Filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " FFLTR3EN ,Fault Input 3 Filter Enable" "Disabled,Enabled" bitfld.long 0x00 6. " FFLTR2EN ,Fault Input 2 Filter Enable" "Disabled,Enabled" bitfld.long 0x00 5. " FFLTR1EN ,Fault Input 1 Filter Enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " FFLTR0EN ,Fault Input 0 Filter Enable" "Disabled,Enabled" bitfld.long 0x00 3. " FAULT3EN ,Fault Input 3 Enable" "Disabled,Enabled" bitfld.long 0x00 2. " FAULT2EN ,Fault Input 2 Enable" "Disabled,Enabled" bitfld.long 0x00 1. " FAULT1EN ,Fault Input 1 Enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " FAULT0EN ,Fault Input 0 Enable" "Disabled,Enabled" else group.long 0x7C++0x03 line.long 0x00 "FLTCTRL,Fault Control" bitfld.long 0x00 8.--11. " FFVAL ,Fault Input Filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 7. " FFLTR3EN ,Fault Input 3 Filter Enable" "Disabled,Enabled" rbitfld.long 0x00 6. " FFLTR2EN ,Fault Input 2 Filter Enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FFLTR1EN ,Fault Input 1 Filter Enable" "Disabled,Enabled" newline rbitfld.long 0x00 4. " FFLTR0EN ,Fault Input 0 Filter Enable" "Disabled,Enabled" rbitfld.long 0x00 3. " FAULT3EN ,Fault Input 3 Enable" "Disabled,Enabled" rbitfld.long 0x00 2. " FAULT2EN ,Fault Input 2 Enable" "Disabled,Enabled" rbitfld.long 0x00 1. " FAULT1EN ,Fault Input 1 Enable" "Disabled,Enabled" newline rbitfld.long 0x00 0. " FAULT0EN ,Fault Input 0 Enable" "Disabled,Enabled" endif if (((per.l(ad:0x40039000+0x54))&0x04)==0x04) group.long 0x80++0x03 line.long 0x00 "QDCTRL,Quadrature Decoder Control And Status" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" newline bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "A and B encoding,Count and direction encoding" rbitfld.long 0x00 2. " QUADIR ,FTM counter direction in quadrature decoder mode" "Decreasing,Increasing" rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Bottom,Top" bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "QDCTRL,Quadrature Decoder Control And Status" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" newline bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "A and B encoding,Count and direction encoding" rbitfld.long 0x00 2. " QUADIR ,FTM counter direction in quadrature decoder mode" "Decreasing,Increasing" rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Bottom,Top" rbitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "CONF,Configuration" bitfld.long 0x00 10. " GTBEOUT ,Global time base output" "Disabled,Enabled" bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " BDMMODE ,Selects the FTM behavior in BDM mode" "0,1,2,3" bitfld.long 0x00 0.--4. " NUMTOF ,Selects the ratio between the number of counter overflows to the number of times the TOF bit is set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x40039000+0x54))&0x04)==0x04) group.long 0x88++0x03 line.long 0x00 "FLTPOL,FTM Fault Input Polarity" bitfld.long 0x00 3. " FLT3POL ,Fault Input 3 Polarity" "Active high,Active low" bitfld.long 0x00 2. " FLT2POL ,Fault Input 2 Polarity" "Active high,Active low" bitfld.long 0x00 1. " FLT1POL ,Fault Input 1 Polarity" "Active high,Active low" bitfld.long 0x00 0. " FLT0POL ,Fault Input 0 Polarity" "Active high,Active low" else rgroup.long 0x88++0x03 line.long 0x00 "FLTPOL,FTM Fault Input Polarity" bitfld.long 0x00 3. " FLT3POL ,Fault Input 3 Polarity" "Active high,Active low" bitfld.long 0x00 2. " FLT2POL ,Fault Input 2 Polarity" "Active high,Active low" bitfld.long 0x00 1. " FLT1POL ,Fault Input 1 Polarity" "Active high,Active low" bitfld.long 0x00 0. " FLT0POL ,Fault Input 0 Polarity" "Active high,Active low" endif group.long 0x8C++0x0F line.long 0x00 "SYNCONF,Synchronization Configuration" bitfld.long 0x00 20. " HWSOC ,Software output control synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 18. " HWOM ,Output mask synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 17. " HWWRBUF ,MOD CNTIN and CV registers synchronization is activated by a hardware trigger" "Not activated,Activated" newline bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 12. " SWSOC ,Software output control synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 10. " SWOM ,Output mask synchronization is activated by the software trigger" "Not activated,Activated" newline bitfld.long 0x00 9. " SWWRBUF ,MOD CNTIN and CV registers synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 7. " SYNCMODE ,Synchronization mode" "Legacy PWM,Enhanced PWM" bitfld.long 0x00 5. " SWOC ,SWOCTRL register synchronization" "At rising edges of system clock,PWM synchronization" newline bitfld.long 0x00 4. " INVC ,INVCTRL register synchronization" "At rising edges of system clock,PWM synchronization" bitfld.long 0x00 2. " CNTINC ,CNTIN register synchronization" "At rising edges of system clock,PWM synchronization" bitfld.long 0x00 0. " HWTRIGMODE ,Hardware trigger mode" "Cleared,Not cleared" line.long 0x04 "INVCTRL,FTM Inverting Control" bitfld.long 0x04 3. " INV3EN ,Pair channels 3 inverting enable" "Disabled,Enabled" bitfld.long 0x04 2. " INV2EN ,Pair channels 2 inverting enable" "Disabled,Enabled" bitfld.long 0x04 1. " INV1EN ,Pair channels 1 inverting enable" "Disabled,Enabled" bitfld.long 0x04 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled" line.long 0x08 "SWOCTRL,FTM Software Output Control" bitfld.long 0x08 15. " CH7OCV ,Channel 7 software output control value" "Force 0,Force 1" bitfld.long 0x08 14. " CH6OCV ,Channel 6 software output control value" "Force 0,Force 1" bitfld.long 0x08 13. " CH5OCV ,Channel 5 software output control value" "Force 0,Force 1" bitfld.long 0x08 12. " CH4OCV ,Channel 4 software output control value" "Force 0,Force 1" newline bitfld.long 0x08 11. " CH3OCV ,Channel 3 software output control value" "Force 0,Force 1" bitfld.long 0x08 10. " CH2OCV ,Channel 2 software output control value" "Force 0,Force 1" bitfld.long 0x08 9. " CH1OCV ,Channel 1 software output control value" "Force 0,Force 1" bitfld.long 0x08 8. " CH0OCV ,Channel 0 software output control value" "Force 0,Force 1" newline bitfld.long 0x08 7. " CH7OC ,Channel 7 software output control enable" "Disabled,Enabled" bitfld.long 0x08 6. " CH6OC ,Channel 6 software output control enable" "Disabled,Enabled" bitfld.long 0x08 5. " CH5OC ,Channel 5 software output control enable" "Disabled,Enabled" bitfld.long 0x08 4. " CH4OC ,Channel 4 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled" bitfld.long 0x08 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled" bitfld.long 0x08 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled" bitfld.long 0x08 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled" line.long 0x0C "PWMLOAD,FTM PWM Load" bitfld.long 0x0C 9. " LDOK ,Load enable" "Disabled,Enabled" newline bitfld.long 0x0C 7. " CH7SEL ,Channel 7 select" "Not included,Included" bitfld.long 0x0C 6. " CH6SEL ,Channel 6 select" "Not included,Included" bitfld.long 0x0C 5. " CH5SEL ,Channel 5 select" "Not included,Included" bitfld.long 0x0C 4. " CH4SEL ,Channel 4 select" "Not included,Included" newline bitfld.long 0x0C 3. " CH3SEL ,Channel 3 select" "Not included,Included" bitfld.long 0x0C 2. " CH2SEL ,Channel 2 select" "Not included,Included" bitfld.long 0x0C 1. " CH1SEL ,Channel 1 select" "Not included,Included" bitfld.long 0x0C 0. " CH0SEL ,Channel 0 select" "Not included,Included" width 0x0B tree.end tree "FTM_2" base ad:0x4003A000 width 10. if (((per.l(ad:0x4003A000+0x54))&0x04)==0x04) group.long 0x00++0x03 line.long 0x00 "SC,Status And Control" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " CPWMS ,Center-Aligned PWM select" "Up counting mode,Up-Down counting mode" bitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clock,System clock,Fixed frequency clock,External clock" newline bitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" else group.long 0x00++0x03 line.long 0x00 "SC,Status And Control" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " CPWMS ,Center-Aligned PWM select" "Up counting mode,Up-Down counting mode" rbitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clock,System clock,Fixed frequency clock,External clock" newline rbitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" endif group.long 0x04++0x07 line.long 0x00 "CNT,Counter" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" line.long 0x04 "MOD,Modulo" hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value" if ((((per.l(ad:0x4003A000+0x64))&0x05)==0x00)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0xC))&0x30)==0x00)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x04)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x05)==0x00)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0xC))&0x30)==0x00)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x00)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x05)==0x00)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0xC))&0x30)==0x10)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x04)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x05)==0x00)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0xC))&0x30)==0x10)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x00)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x05)==0x00)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0xC))&0x30)==(0x20||0x30))&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x04)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x05)==0x00)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0xC))&0x30)==(0x20||0x30))&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x00)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x05)==0x00)&&(((per.l(ad:0x4003A000))&0x20)==0x20)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x04)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x05)==0x00)&&(((per.l(ad:0x4003A000))&0x20)==0x20)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x00)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x05)==0x01)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x04)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x05)==0x01)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x00)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x05)==0x04)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x04)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x05)==0x04)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x00)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0xC++0x03 hide.long 0x00 "C0SC,Channel (0) Status And Control" endif group.long (0xC+0x04)++0x03 line.long 0x00 "C0V,Channel (0) Value" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" if ((((per.l(ad:0x4003A000+0x64))&0x05)==0x00)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x14))&0x30)==0x00)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x04)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x05)==0x00)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x14))&0x30)==0x00)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x00)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x05)==0x00)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x14))&0x30)==0x10)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x04)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x05)==0x00)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x14))&0x30)==0x10)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x00)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x05)==0x00)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x14))&0x30)==(0x20||0x30))&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x04)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x05)==0x00)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x14))&0x30)==(0x20||0x30))&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x00)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x05)==0x00)&&(((per.l(ad:0x4003A000))&0x20)==0x20)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x04)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x05)==0x00)&&(((per.l(ad:0x4003A000))&0x20)==0x20)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x00)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x05)==0x01)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x04)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x05)==0x01)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x00)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x05)==0x04)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x04)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x05)==0x04)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x00)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x14++0x03 hide.long 0x00 "C1SC,Channel (1) Status And Control" endif group.long (0x14+0x04)++0x03 line.long 0x00 "C1V,Channel (1) Value" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" if ((((per.l(ad:0x4003A000+0x64))&0x500)==0x00)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x1C))&0x30)==0x00)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x04)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x500)==0x00)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x1C))&0x30)==0x00)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x00)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x500)==0x00)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x1C))&0x30)==0x10)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x04)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x500)==0x00)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x1C))&0x30)==0x10)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x00)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x500)==0x00)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x1C))&0x30)==(0x20||0x30))&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x04)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x500)==0x00)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x1C))&0x30)==(0x20||0x30))&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x00)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x500)==0x00)&&(((per.l(ad:0x4003A000))&0x20)==0x20)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x04)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x500)==0x00)&&(((per.l(ad:0x4003A000))&0x20)==0x20)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x00)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x500)==0x100)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x04)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x500)==0x100)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x00)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x500)==0x400)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x04)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x500)==0x400)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x00)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x1C++0x03 hide.long 0x00 "C2SC,Channel (2) Status And Control" endif group.long (0x1C+0x04)++0x03 line.long 0x00 "C2V,Channel (2) Value" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" if ((((per.l(ad:0x4003A000+0x64))&0x500)==0x00)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x24))&0x30)==0x00)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x04)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x500)==0x00)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x24))&0x30)==0x00)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x00)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x500)==0x00)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x24))&0x30)==0x10)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x04)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x500)==0x00)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x24))&0x30)==0x10)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x00)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x500)==0x00)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x24))&0x30)==(0x20||0x30))&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x04)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x500)==0x00)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x24))&0x30)==(0x20||0x30))&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x00)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x500)==0x00)&&(((per.l(ad:0x4003A000))&0x20)==0x20)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x04)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x500)==0x00)&&(((per.l(ad:0x4003A000))&0x20)==0x20)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x00)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x500)==0x100)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x04)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x500)==0x100)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x00)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x500)==0x400)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x04)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x500)==0x400)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x00)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x24++0x03 hide.long 0x00 "C3SC,Channel (3) Status And Control" endif group.long (0x24+0x04)++0x03 line.long 0x00 "C3V,Channel (3) Value" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" if ((((per.l(ad:0x4003A000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x2C))&0x30)==0x00)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x04)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x2C))&0x30)==0x00)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x00)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x2C))&0x30)==0x10)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x04)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x2C))&0x30)==0x10)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x00)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x2C))&0x30)==(0x20||0x30))&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x04)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x2C))&0x30)==(0x20||0x30))&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x00)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x4003A000))&0x20)==0x20)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x04)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x4003A000))&0x20)==0x20)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x00)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x50000)==0x10000)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x04)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x50000)==0x10000)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x00)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x50000)==0x40000)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x04)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x50000)==0x40000)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x00)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x2C++0x03 hide.long 0x00 "C4SC,Channel (4) Status And Control" endif group.long (0x2C+0x04)++0x03 line.long 0x00 "C4V,Channel (4) Value" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" if ((((per.l(ad:0x4003A000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x34))&0x30)==0x00)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x04)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x34))&0x30)==0x00)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x00)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x34))&0x30)==0x10)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x04)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x34))&0x30)==0x10)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x00)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x34))&0x30)==(0x20||0x30))&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x04)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x34))&0x30)==(0x20||0x30))&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x00)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x4003A000))&0x20)==0x20)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x04)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x4003A000))&0x20)==0x20)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x00)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x50000)==0x10000)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x04)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x50000)==0x10000)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x00)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x50000)==0x40000)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x04)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x50000)==0x40000)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x00)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x34++0x03 hide.long 0x00 "C5SC,Channel (5) Status And Control" endif group.long (0x34+0x04)++0x03 line.long 0x00 "C5V,Channel (5) Value" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" if ((((per.l(ad:0x4003A000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x3C))&0x30)==0x00)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x04)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x3C))&0x30)==0x00)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x00)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x3C))&0x30)==0x10)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x04)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x3C))&0x30)==0x10)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x00)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x3C))&0x30)==(0x20||0x30))&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x04)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x3C))&0x30)==(0x20||0x30))&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x00)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x4003A000))&0x20)==0x20)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x04)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x4003A000))&0x20)==0x20)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x00)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x5000000)==0x1000000)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x04)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x5000000)==0x1000000)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x00)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x5000000)==0x4000000)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x04)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x5000000)==0x4000000)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x00)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x3C++0x03 hide.long 0x00 "C6SC,Channel (6) Status And Control" endif group.long (0x3C+0x04)++0x03 line.long 0x00 "C6V,Channel (6) Value" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" if ((((per.l(ad:0x4003A000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x44))&0x30)==0x00)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x04)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x44))&0x30)==0x00)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x00)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x44))&0x30)==0x10)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x04)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x44))&0x30)==0x10)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x00)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x44))&0x30)==(0x20||0x30))&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x04)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x44))&0x30)==(0x20||0x30))&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x00)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x4003A000))&0x20)==0x20)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x04)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x4003A000))&0x20)==0x20)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x00)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x5000000)==0x1000000)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x04)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x5000000)==0x1000000)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x00)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x5000000)==0x4000000)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x04)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x4003A000+0x64))&0x5000000)==0x4000000)&&(((per.l(ad:0x4003A000))&0x20)==0x00)&&(((per.l(ad:0x4003A000+0x54))&0x04)==0x00)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x44++0x03 hide.long 0x00 "C7SC,Channel (7) Status And Control" endif group.long (0x44+0x04)++0x03 line.long 0x00 "C7V,Channel (7) Value" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" newline group.long 0x4C++0x03 line.long 0x00 "CNTIN,Counter Initial Value" hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial value of the FTM counter" hgroup.long 0x50++0x03 hide.long 0x00 "STATUS,Capture And Compare Status" in if (((per.l(ad:0x4003A000+0x54))&0x04)==0x04) group.long 0x54++0x03 line.long 0x00 "MODE,Features Mode Selection" bitfld.long 0x00 7. " FAULTIE ,Fault Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5.--6. " FAULTM ,Fault Control Mode" "Disabled,Enabled for even channels/Manual clear,Enabled for all channels/Manual clear,Enabled for all channels/Automatic clear" bitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode" "Disabled,Enabled" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialized" bitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" else group.long 0x54++0x03 line.long 0x00 "MODE,Features Mode Selection" bitfld.long 0x00 7. " FAULTIE ,Fault Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 5.--6. " FAULTM ,Fault Control Mode" "Disabled,Enabled for even channels/Manual clear,Enabled for all channels/Manual clear,Enabled for all channels/Automatic clear" rbitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode" "Disabled,Enabled" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialized" rbitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" endif newline group.long 0x58++0x0B line.long 0x00 "SYNC,Synchronization" bitfld.long 0x00 7. " SWSYNC ,PWM synchronization software trigger" "Not selected,Selected" bitfld.long 0x00 6. " TRIG2 ,PWM synchronization hardware trigger 2" "Disabled,Enabled" bitfld.long 0x00 5. " TRIG1 ,PWM synchronization hardware trigger 1" "Disabled,Enabled" bitfld.long 0x00 4. " TRIG0 ,PWM synchronization hardware trigger 0" "Disabled,Enabled" newline bitfld.long 0x00 3. " SYNCHOM ,Output mask synchronization" "At rising edges of system clock,PWM synchronization" bitfld.long 0x00 2. " REINIT ,FTM counter reinitialization by synchronization" "Count normally,Trigger detected" bitfld.long 0x00 1. " CNTMAX ,Maximum loading point enable" "Disabled,Enabled" bitfld.long 0x00 0. " CNTMIN ,Minimum loading point enable" "Disabled,Enabled" line.long 0x04 "OUTINIT,Initial State For Channels Output" bitfld.long 0x04 7. " CH7OI ,Channel 7 output initialization value" "0,1" bitfld.long 0x04 6. " CH6OI ,Channel 6 output initialization value" "0,1" bitfld.long 0x04 5. " CH5OI ,Channel 5 output initialization value" "0,1" bitfld.long 0x04 4. " CH4OI ,Channel 4 output initialization value" "0,1" newline bitfld.long 0x04 3. " CH3OI ,Channel 3 output initialization value" "0,1" bitfld.long 0x04 2. " CH2OI ,Channel 2 output initialization value" "0,1" bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1" bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1" line.long 0x08 "OUTMASK,Output Mask" bitfld.long 0x08 7. " CH7OM ,Channel 7 output mask" "Not masked,Masked" bitfld.long 0x08 6. " CH6OM ,Channel 6 output mask" "Not masked,Masked" bitfld.long 0x08 5. " CH5OM ,Channel 5 output mask" "Not masked,Masked" bitfld.long 0x08 4. " CH4OM ,Channel 4 output mask" "Not masked,Masked" newline bitfld.long 0x08 3. " CH3OM ,Channel 3 output mask" "Not masked,Masked" bitfld.long 0x08 2. " CH2OM ,Channel 2 output mask" "Not masked,Masked" bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked" bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked" if (((per.l(ad:0x4003A000+0x54))&0x04)==0x04) group.long 0x64++0x07 line.long 0x00 "COMBINE,Function For Linked Channels" bitfld.long 0x00 30. " FAULTEN3 ,Fault Control Enable For n = 6" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,Synchronization enable for n = 6" "Disabled,Enabled" bitfld.long 0x00 28. " DTEN3 ,Deadtime enable for n = 6" "Disabled,Enabled" bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures for n = 6" "Inactive,Active" newline bitfld.long 0x00 26. " DECAPEN3 ,Dual Edge Capture Mode Enable for n = 6" "Disabled,Enabled" bitfld.long 0x00 25. " COMP3 ,Complement of channel (N) for n = 6" "Same,Complemented" bitfld.long 0x00 24. " COMBINE3 ,Combine channels for n = 6" "Independed,Combined" bitfld.long 0x00 22. " FAULTEN2 ,Fault Control Enable For n = 4" "Disabled,Enabled" newline bitfld.long 0x00 21. " SYNCEN2 ,Synchronization enable for n = 4" "Disabled,Enabled" bitfld.long 0x00 20. " DTEN2 ,Deadtime enable for n = 4" "Disabled,Enabled" bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures for n = 4" "Inactive,Active" bitfld.long 0x00 18. " DECAPEN2 ,Dual Edge Capture Mode Enable for n = 4" "Disabled,Enabled" newline bitfld.long 0x00 17. " COMP2 ,Complement of channel (N) for n = 4" "Same,Complemented" bitfld.long 0x00 16. " COMBINE2 ,Combine channels for n = 4" "Independed,Combined" bitfld.long 0x00 14. " FAULTEN1 ,Fault Control Enable For n = 2" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,Synchronization enable for n = 2" "Disabled,Enabled" newline bitfld.long 0x00 12. " DTEN1 ,Deadtime enable for n = 2" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures for n = 2" "Inactive,Active" bitfld.long 0x00 10. " DECAPEN1 ,Dual Edge Capture Mode Enable for n = 2" "Disabled,Enabled" bitfld.long 0x00 9. " COMP1 ,Complement of channel (N) for n = 2" "Same,Complemented" newline bitfld.long 0x00 8. " COMBINE1 ,Combine channels for n = 2" "Independed,Combined" bitfld.long 0x00 6. " FAULTEN0 ,Fault Control Enable For n = 0" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,Synchronization enable for n = 0" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime enable for n = 0" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures for n = 0" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual Edge Capture Mode Enable for n = 0" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complement of channel (N) for n = 0" "Same,Complemented" bitfld.long 0x00 0. " COMBINE0 ,Combine channels for n = 0" "Independed,Combined" line.long 0x04 "DEADTIME,Deadtime Insertion Control" bitfld.long 0x04 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x04 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x64++0x03 line.long 0x00 "COMBINE,Function For Linked Channels" rbitfld.long 0x00 30. " FAULTEN3 ,Fault Control Enable For n = 6" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,Synchronization enable for n = 6" "Disabled,Enabled" rbitfld.long 0x00 28. " DTEN3 ,Deadtime enable for n = 6" "Disabled,Enabled" bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures for n = 6" "Inactive,Active" newline rbitfld.long 0x00 26. " DECAPEN3 ,Dual Edge Capture Mode Enable for n = 6" "Disabled,Enabled" rbitfld.long 0x00 25. " COMP3 ,Complement of channel (N) for n = 6" "Same,Complemented" rbitfld.long 0x00 24. " COMBINE3 ,Combine channels for n = 6" "Independed,Combined" rbitfld.long 0x00 22. " FAULTEN2 ,Fault Control Enable For n = 4" "Disabled,Enabled" newline bitfld.long 0x00 21. " SYNCEN2 ,Synchronization enable for n = 4" "Disabled,Enabled" rbitfld.long 0x00 20. " DTEN2 ,Deadtime enable for n = 4" "Disabled,Enabled" bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures for n = 4" "Inactive,Active" rbitfld.long 0x00 18. " DECAPEN2 ,Dual Edge Capture Mode Enable for n = 4" "Disabled,Enabled" newline rbitfld.long 0x00 17. " COMP2 ,Complement of channel (N) for n = 4" "Same,Complemented" rbitfld.long 0x00 16. " COMBINE2 ,Combine channels for n = 4" "Independed,Combined" rbitfld.long 0x00 14. " FAULTEN1 ,Fault Control Enable For n = 2" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,Synchronization enable for n = 2" "Disabled,Enabled" newline rbitfld.long 0x00 12. " DTEN1 ,Deadtime enable for n = 2" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures for n = 2" "Inactive,Active" rbitfld.long 0x00 10. " DECAPEN1 ,Dual Edge Capture Mode Enable for n = 2" "Disabled,Enabled" rbitfld.long 0x00 9. " COMP1 ,Complement of channel (N) for n = 2" "Same,Complemented" newline rbitfld.long 0x00 8. " COMBINE1 ,Combine channels for n = 2" "Independed,Combined" rbitfld.long 0x00 6. " FAULTEN0 ,Fault Control Enable For n = 0" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,Synchronization enable for n = 0" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable for n = 0" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures for n = 0" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual Edge Capture Mode Enable for n = 0" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complement of channel (N) for n = 0" "Same,Complemented" rbitfld.long 0x00 0. " COMBINE0 ,Combine channels for n = 0" "Independed,Combined" rgroup.long 0x68++0x03 line.long 0x00 "DEADTIME,Deadtime Insertion Control" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x6C++0x03 line.long 0x00 "EXTTRIG,FTM External Trigger" rbitfld.long 0x00 7. " TRIGF ,Channel trigger flag" "Not occurred,Occurred" bitfld.long 0x00 6. " INITTRIGEN ,Initialization trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " CH1TRIG ,Channel 1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 4. " CH0TRIG ,Channel 0 trigger enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " CH5TRIG ,Channel 5 trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " CH4TRIG ,Channel 4 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " CH3TRIG ,Channel 3 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " CH2TRIG ,Channel 2 trigger enable" "Disabled,Enabled" if (((per.l(ad:0x4003A000+0x54))&0x04)==0x04) group.long 0x70++0x03 line.long 0x00 "POL,Channels Polarity" bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "High,Low" bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "High,Low" bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "High,Low" bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "High,Low" newline bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "High,Low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "High,Low" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "High,Low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "High,Low" else rgroup.long 0x70++0x03 line.long 0x00 "POL,Channels Polarity" bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "High,Low" bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "High,Low" bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "High,Low" bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "High,Low" newline bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "High,Low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "High,Low" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "High,Low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "High,Low" endif hgroup.long 0x74++0x03 hide.long 0x00 "FMS,Fault Mode Status" in newline group.long 0x78++0x03 line.long 0x00 "FILTER,Input Capture Filter Control" bitfld.long 0x00 12.--15. " CH3FVAL ,Channel 3 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " CH2FVAL ,Channel 2 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (((per.l(ad:0x4003A000+0x54))&0x04)==0x04) group.long 0x7C++0x03 line.long 0x00 "FLTCTRL,Fault Control" bitfld.long 0x00 8.--11. " FFVAL ,Fault Input Filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " FFLTR3EN ,Fault Input 3 Filter Enable" "Disabled,Enabled" bitfld.long 0x00 6. " FFLTR2EN ,Fault Input 2 Filter Enable" "Disabled,Enabled" bitfld.long 0x00 5. " FFLTR1EN ,Fault Input 1 Filter Enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " FFLTR0EN ,Fault Input 0 Filter Enable" "Disabled,Enabled" bitfld.long 0x00 3. " FAULT3EN ,Fault Input 3 Enable" "Disabled,Enabled" bitfld.long 0x00 2. " FAULT2EN ,Fault Input 2 Enable" "Disabled,Enabled" bitfld.long 0x00 1. " FAULT1EN ,Fault Input 1 Enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " FAULT0EN ,Fault Input 0 Enable" "Disabled,Enabled" else group.long 0x7C++0x03 line.long 0x00 "FLTCTRL,Fault Control" bitfld.long 0x00 8.--11. " FFVAL ,Fault Input Filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 7. " FFLTR3EN ,Fault Input 3 Filter Enable" "Disabled,Enabled" rbitfld.long 0x00 6. " FFLTR2EN ,Fault Input 2 Filter Enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FFLTR1EN ,Fault Input 1 Filter Enable" "Disabled,Enabled" newline rbitfld.long 0x00 4. " FFLTR0EN ,Fault Input 0 Filter Enable" "Disabled,Enabled" rbitfld.long 0x00 3. " FAULT3EN ,Fault Input 3 Enable" "Disabled,Enabled" rbitfld.long 0x00 2. " FAULT2EN ,Fault Input 2 Enable" "Disabled,Enabled" rbitfld.long 0x00 1. " FAULT1EN ,Fault Input 1 Enable" "Disabled,Enabled" newline rbitfld.long 0x00 0. " FAULT0EN ,Fault Input 0 Enable" "Disabled,Enabled" endif if (((per.l(ad:0x4003A000+0x54))&0x04)==0x04) group.long 0x80++0x03 line.long 0x00 "QDCTRL,Quadrature Decoder Control And Status" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" newline bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "A and B encoding,Count and direction encoding" rbitfld.long 0x00 2. " QUADIR ,FTM counter direction in quadrature decoder mode" "Decreasing,Increasing" rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Bottom,Top" bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "QDCTRL,Quadrature Decoder Control And Status" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" newline bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "A and B encoding,Count and direction encoding" rbitfld.long 0x00 2. " QUADIR ,FTM counter direction in quadrature decoder mode" "Decreasing,Increasing" rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Bottom,Top" rbitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "CONF,Configuration" bitfld.long 0x00 10. " GTBEOUT ,Global time base output" "Disabled,Enabled" bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " BDMMODE ,Selects the FTM behavior in BDM mode" "0,1,2,3" bitfld.long 0x00 0.--4. " NUMTOF ,Selects the ratio between the number of counter overflows to the number of times the TOF bit is set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x4003A000+0x54))&0x04)==0x04) group.long 0x88++0x03 line.long 0x00 "FLTPOL,FTM Fault Input Polarity" bitfld.long 0x00 3. " FLT3POL ,Fault Input 3 Polarity" "Active high,Active low" bitfld.long 0x00 2. " FLT2POL ,Fault Input 2 Polarity" "Active high,Active low" bitfld.long 0x00 1. " FLT1POL ,Fault Input 1 Polarity" "Active high,Active low" bitfld.long 0x00 0. " FLT0POL ,Fault Input 0 Polarity" "Active high,Active low" else rgroup.long 0x88++0x03 line.long 0x00 "FLTPOL,FTM Fault Input Polarity" bitfld.long 0x00 3. " FLT3POL ,Fault Input 3 Polarity" "Active high,Active low" bitfld.long 0x00 2. " FLT2POL ,Fault Input 2 Polarity" "Active high,Active low" bitfld.long 0x00 1. " FLT1POL ,Fault Input 1 Polarity" "Active high,Active low" bitfld.long 0x00 0. " FLT0POL ,Fault Input 0 Polarity" "Active high,Active low" endif group.long 0x8C++0x0F line.long 0x00 "SYNCONF,Synchronization Configuration" bitfld.long 0x00 20. " HWSOC ,Software output control synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 18. " HWOM ,Output mask synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 17. " HWWRBUF ,MOD CNTIN and CV registers synchronization is activated by a hardware trigger" "Not activated,Activated" newline bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 12. " SWSOC ,Software output control synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 10. " SWOM ,Output mask synchronization is activated by the software trigger" "Not activated,Activated" newline bitfld.long 0x00 9. " SWWRBUF ,MOD CNTIN and CV registers synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 7. " SYNCMODE ,Synchronization mode" "Legacy PWM,Enhanced PWM" bitfld.long 0x00 5. " SWOC ,SWOCTRL register synchronization" "At rising edges of system clock,PWM synchronization" newline bitfld.long 0x00 4. " INVC ,INVCTRL register synchronization" "At rising edges of system clock,PWM synchronization" bitfld.long 0x00 2. " CNTINC ,CNTIN register synchronization" "At rising edges of system clock,PWM synchronization" bitfld.long 0x00 0. " HWTRIGMODE ,Hardware trigger mode" "Cleared,Not cleared" line.long 0x04 "INVCTRL,FTM Inverting Control" bitfld.long 0x04 3. " INV3EN ,Pair channels 3 inverting enable" "Disabled,Enabled" bitfld.long 0x04 2. " INV2EN ,Pair channels 2 inverting enable" "Disabled,Enabled" bitfld.long 0x04 1. " INV1EN ,Pair channels 1 inverting enable" "Disabled,Enabled" bitfld.long 0x04 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled" line.long 0x08 "SWOCTRL,FTM Software Output Control" bitfld.long 0x08 15. " CH7OCV ,Channel 7 software output control value" "Force 0,Force 1" bitfld.long 0x08 14. " CH6OCV ,Channel 6 software output control value" "Force 0,Force 1" bitfld.long 0x08 13. " CH5OCV ,Channel 5 software output control value" "Force 0,Force 1" bitfld.long 0x08 12. " CH4OCV ,Channel 4 software output control value" "Force 0,Force 1" newline bitfld.long 0x08 11. " CH3OCV ,Channel 3 software output control value" "Force 0,Force 1" bitfld.long 0x08 10. " CH2OCV ,Channel 2 software output control value" "Force 0,Force 1" bitfld.long 0x08 9. " CH1OCV ,Channel 1 software output control value" "Force 0,Force 1" bitfld.long 0x08 8. " CH0OCV ,Channel 0 software output control value" "Force 0,Force 1" newline bitfld.long 0x08 7. " CH7OC ,Channel 7 software output control enable" "Disabled,Enabled" bitfld.long 0x08 6. " CH6OC ,Channel 6 software output control enable" "Disabled,Enabled" bitfld.long 0x08 5. " CH5OC ,Channel 5 software output control enable" "Disabled,Enabled" bitfld.long 0x08 4. " CH4OC ,Channel 4 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled" bitfld.long 0x08 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled" bitfld.long 0x08 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled" bitfld.long 0x08 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled" line.long 0x0C "PWMLOAD,FTM PWM Load" bitfld.long 0x0C 9. " LDOK ,Load enable" "Disabled,Enabled" newline bitfld.long 0x0C 7. " CH7SEL ,Channel 7 select" "Not included,Included" bitfld.long 0x0C 6. " CH6SEL ,Channel 6 select" "Not included,Included" bitfld.long 0x0C 5. " CH5SEL ,Channel 5 select" "Not included,Included" bitfld.long 0x0C 4. " CH4SEL ,Channel 4 select" "Not included,Included" newline bitfld.long 0x0C 3. " CH3SEL ,Channel 3 select" "Not included,Included" bitfld.long 0x0C 2. " CH2SEL ,Channel 2 select" "Not included,Included" bitfld.long 0x0C 1. " CH1SEL ,Channel 1 select" "Not included,Included" bitfld.long 0x0C 0. " CH0SEL ,Channel 0 select" "Not included,Included" width 0x0B tree.end tree "FTM_3" base ad:0x400B9000 width 10. if (((per.l(ad:0x400B9000+0x54))&0x04)==0x04) group.long 0x00++0x03 line.long 0x00 "SC,Status And Control" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " CPWMS ,Center-Aligned PWM select" "Up counting mode,Up-Down counting mode" bitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clock,System clock,Fixed frequency clock,External clock" newline bitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" else group.long 0x00++0x03 line.long 0x00 "SC,Status And Control" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " CPWMS ,Center-Aligned PWM select" "Up counting mode,Up-Down counting mode" rbitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clock,System clock,Fixed frequency clock,External clock" newline rbitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" endif group.long 0x04++0x07 line.long 0x00 "CNT,Counter" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" line.long 0x04 "MOD,Modulo" hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value" if ((((per.l(ad:0x400B9000+0x64))&0x05)==0x00)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0xC))&0x30)==0x00)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x04)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x05)==0x00)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0xC))&0x30)==0x00)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x00)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x05)==0x00)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0xC))&0x30)==0x10)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x04)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x05)==0x00)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0xC))&0x30)==0x10)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x00)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x05)==0x00)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0xC))&0x30)==(0x20||0x30))&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x04)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x05)==0x00)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0xC))&0x30)==(0x20||0x30))&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x00)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x05)==0x00)&&(((per.l(ad:0x400B9000))&0x20)==0x20)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x04)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x05)==0x00)&&(((per.l(ad:0x400B9000))&0x20)==0x20)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x00)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x05)==0x01)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x04)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x05)==0x01)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x00)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x05)==0x04)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x04)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x05)==0x04)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x00)) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0xC++0x03 hide.long 0x00 "C0SC,Channel (0) Status And Control" endif group.long (0xC+0x04)++0x03 line.long 0x00 "C0V,Channel (0) Value" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" if ((((per.l(ad:0x400B9000+0x64))&0x05)==0x00)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x14))&0x30)==0x00)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x04)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x05)==0x00)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x14))&0x30)==0x00)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x00)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x05)==0x00)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x14))&0x30)==0x10)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x04)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x05)==0x00)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x14))&0x30)==0x10)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x00)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x05)==0x00)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x14))&0x30)==(0x20||0x30))&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x04)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x05)==0x00)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x14))&0x30)==(0x20||0x30))&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x00)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x05)==0x00)&&(((per.l(ad:0x400B9000))&0x20)==0x20)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x04)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x05)==0x00)&&(((per.l(ad:0x400B9000))&0x20)==0x20)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x00)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x05)==0x01)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x04)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x05)==0x01)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x00)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x05)==0x04)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x04)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x05)==0x04)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x00)) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x14++0x03 hide.long 0x00 "C1SC,Channel (1) Status And Control" endif group.long (0x14+0x04)++0x03 line.long 0x00 "C1V,Channel (1) Value" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" if ((((per.l(ad:0x400B9000+0x64))&0x500)==0x00)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x1C))&0x30)==0x00)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x04)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x500)==0x00)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x1C))&0x30)==0x00)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x00)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x500)==0x00)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x1C))&0x30)==0x10)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x04)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x500)==0x00)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x1C))&0x30)==0x10)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x00)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x500)==0x00)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x1C))&0x30)==(0x20||0x30))&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x04)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x500)==0x00)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x1C))&0x30)==(0x20||0x30))&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x00)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x500)==0x00)&&(((per.l(ad:0x400B9000))&0x20)==0x20)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x04)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x500)==0x00)&&(((per.l(ad:0x400B9000))&0x20)==0x20)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x00)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x500)==0x100)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x04)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x500)==0x100)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x00)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x500)==0x400)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x04)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x500)==0x400)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x00)) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x1C++0x03 hide.long 0x00 "C2SC,Channel (2) Status And Control" endif group.long (0x1C+0x04)++0x03 line.long 0x00 "C2V,Channel (2) Value" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" if ((((per.l(ad:0x400B9000+0x64))&0x500)==0x00)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x24))&0x30)==0x00)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x04)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x500)==0x00)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x24))&0x30)==0x00)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x00)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x500)==0x00)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x24))&0x30)==0x10)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x04)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x500)==0x00)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x24))&0x30)==0x10)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x00)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x500)==0x00)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x24))&0x30)==(0x20||0x30))&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x04)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x500)==0x00)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x24))&0x30)==(0x20||0x30))&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x00)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x500)==0x00)&&(((per.l(ad:0x400B9000))&0x20)==0x20)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x04)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x500)==0x00)&&(((per.l(ad:0x400B9000))&0x20)==0x20)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x00)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x500)==0x100)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x04)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x500)==0x100)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x00)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x500)==0x400)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x04)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x500)==0x400)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x00)) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x24++0x03 hide.long 0x00 "C3SC,Channel (3) Status And Control" endif group.long (0x24+0x04)++0x03 line.long 0x00 "C3V,Channel (3) Value" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" if ((((per.l(ad:0x400B9000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x2C))&0x30)==0x00)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x04)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x2C))&0x30)==0x00)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x00)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x2C))&0x30)==0x10)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x04)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x2C))&0x30)==0x10)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x00)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x2C))&0x30)==(0x20||0x30))&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x04)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x2C))&0x30)==(0x20||0x30))&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x00)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x400B9000))&0x20)==0x20)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x04)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x400B9000))&0x20)==0x20)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x00)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x50000)==0x10000)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x04)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x50000)==0x10000)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x00)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x50000)==0x40000)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x04)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x50000)==0x40000)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x00)) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x2C++0x03 hide.long 0x00 "C4SC,Channel (4) Status And Control" endif group.long (0x2C+0x04)++0x03 line.long 0x00 "C4V,Channel (4) Value" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" if ((((per.l(ad:0x400B9000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x34))&0x30)==0x00)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x04)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x34))&0x30)==0x00)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x00)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x34))&0x30)==0x10)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x04)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x34))&0x30)==0x10)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x00)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x34))&0x30)==(0x20||0x30))&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x04)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x34))&0x30)==(0x20||0x30))&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x00)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x400B9000))&0x20)==0x20)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x04)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x50000)==0x00)&&(((per.l(ad:0x400B9000))&0x20)==0x20)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x00)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x50000)==0x10000)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x04)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x50000)==0x10000)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x00)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x50000)==0x40000)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x04)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x50000)==0x40000)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x00)) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x34++0x03 hide.long 0x00 "C5SC,Channel (5) Status And Control" endif group.long (0x34+0x04)++0x03 line.long 0x00 "C5V,Channel (5) Value" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" if ((((per.l(ad:0x400B9000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x3C))&0x30)==0x00)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x04)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x3C))&0x30)==0x00)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x00)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x3C))&0x30)==0x10)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x04)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x3C))&0x30)==0x10)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x00)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x3C))&0x30)==(0x20||0x30))&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x04)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x3C))&0x30)==(0x20||0x30))&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x00)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x400B9000))&0x20)==0x20)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x04)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x400B9000))&0x20)==0x20)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x00)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x5000000)==0x1000000)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x04)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x5000000)==0x1000000)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x00)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x5000000)==0x4000000)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x04)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x5000000)==0x4000000)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x00)) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x3C++0x03 hide.long 0x00 "C6SC,Channel (6) Status And Control" endif group.long (0x3C+0x04)++0x03 line.long 0x00 "C6V,Channel (6) Value" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" if ((((per.l(ad:0x400B9000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x44))&0x30)==0x00)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x04)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x44))&0x30)==0x00)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x00)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x44))&0x30)==0x10)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x04)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x44))&0x30)==0x10)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x00)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Toggle output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x44))&0x30)==(0x20||0x30))&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x04)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x44))&0x30)==(0x20||0x30))&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x00)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Input capture,Output compare,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x400B9000))&0x20)==0x20)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x04)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x5000000)==0x00)&&(((per.l(ad:0x400B9000))&0x20)==0x20)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x00)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Set output,Clear output,Set output" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x5000000)==0x1000000)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x04)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x5000000)==0x1000000)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x00)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "Combine PWM,Combine PWM,Combine PWM,Combine PWM" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" ",Low-true pulses,High-true pulses,Low-true pulses" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x5000000)==0x4000000)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x04)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((((per.l(ad:0x400B9000+0x64))&0x5000000)==0x4000000)&&(((per.l(ad:0x400B9000))&0x20)==0x00)&&(((per.l(ad:0x400B9000+0x54))&0x04)==0x00)) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control" rbitfld.long 0x00 7. " CHF ,Channel flag" "Not occured,Occured" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel mode select" "One-Shot capture,Continuous capture,One-Shot capture,Continuous capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising edge,Falling edge,Both edge" newline rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "Not reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else hgroup.long 0x44++0x03 hide.long 0x00 "C7SC,Channel (7) Status And Control" endif group.long (0x44+0x04)++0x03 line.long 0x00 "C7V,Channel (7) Value" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" newline group.long 0x4C++0x03 line.long 0x00 "CNTIN,Counter Initial Value" hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial value of the FTM counter" hgroup.long 0x50++0x03 hide.long 0x00 "STATUS,Capture And Compare Status" in if (((per.l(ad:0x400B9000+0x54))&0x04)==0x04) group.long 0x54++0x03 line.long 0x00 "MODE,Features Mode Selection" bitfld.long 0x00 7. " FAULTIE ,Fault Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5.--6. " FAULTM ,Fault Control Mode" "Disabled,Enabled for even channels/Manual clear,Enabled for all channels/Manual clear,Enabled for all channels/Automatic clear" bitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode" "Disabled,Enabled" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialized" bitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" else group.long 0x54++0x03 line.long 0x00 "MODE,Features Mode Selection" bitfld.long 0x00 7. " FAULTIE ,Fault Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 5.--6. " FAULTM ,Fault Control Mode" "Disabled,Enabled for even channels/Manual clear,Enabled for all channels/Manual clear,Enabled for all channels/Automatic clear" rbitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode" "Disabled,Enabled" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialized" rbitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" endif newline group.long 0x58++0x0B line.long 0x00 "SYNC,Synchronization" bitfld.long 0x00 7. " SWSYNC ,PWM synchronization software trigger" "Not selected,Selected" bitfld.long 0x00 6. " TRIG2 ,PWM synchronization hardware trigger 2" "Disabled,Enabled" bitfld.long 0x00 5. " TRIG1 ,PWM synchronization hardware trigger 1" "Disabled,Enabled" bitfld.long 0x00 4. " TRIG0 ,PWM synchronization hardware trigger 0" "Disabled,Enabled" newline bitfld.long 0x00 3. " SYNCHOM ,Output mask synchronization" "At rising edges of system clock,PWM synchronization" bitfld.long 0x00 2. " REINIT ,FTM counter reinitialization by synchronization" "Count normally,Trigger detected" bitfld.long 0x00 1. " CNTMAX ,Maximum loading point enable" "Disabled,Enabled" bitfld.long 0x00 0. " CNTMIN ,Minimum loading point enable" "Disabled,Enabled" line.long 0x04 "OUTINIT,Initial State For Channels Output" bitfld.long 0x04 7. " CH7OI ,Channel 7 output initialization value" "0,1" bitfld.long 0x04 6. " CH6OI ,Channel 6 output initialization value" "0,1" bitfld.long 0x04 5. " CH5OI ,Channel 5 output initialization value" "0,1" bitfld.long 0x04 4. " CH4OI ,Channel 4 output initialization value" "0,1" newline bitfld.long 0x04 3. " CH3OI ,Channel 3 output initialization value" "0,1" bitfld.long 0x04 2. " CH2OI ,Channel 2 output initialization value" "0,1" bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1" bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1" line.long 0x08 "OUTMASK,Output Mask" bitfld.long 0x08 7. " CH7OM ,Channel 7 output mask" "Not masked,Masked" bitfld.long 0x08 6. " CH6OM ,Channel 6 output mask" "Not masked,Masked" bitfld.long 0x08 5. " CH5OM ,Channel 5 output mask" "Not masked,Masked" bitfld.long 0x08 4. " CH4OM ,Channel 4 output mask" "Not masked,Masked" newline bitfld.long 0x08 3. " CH3OM ,Channel 3 output mask" "Not masked,Masked" bitfld.long 0x08 2. " CH2OM ,Channel 2 output mask" "Not masked,Masked" bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked" bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked" if (((per.l(ad:0x400B9000+0x54))&0x04)==0x04) group.long 0x64++0x07 line.long 0x00 "COMBINE,Function For Linked Channels" bitfld.long 0x00 30. " FAULTEN3 ,Fault Control Enable For n = 6" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,Synchronization enable for n = 6" "Disabled,Enabled" bitfld.long 0x00 28. " DTEN3 ,Deadtime enable for n = 6" "Disabled,Enabled" bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures for n = 6" "Inactive,Active" newline bitfld.long 0x00 26. " DECAPEN3 ,Dual Edge Capture Mode Enable for n = 6" "Disabled,Enabled" bitfld.long 0x00 25. " COMP3 ,Complement of channel (N) for n = 6" "Same,Complemented" bitfld.long 0x00 24. " COMBINE3 ,Combine channels for n = 6" "Independed,Combined" bitfld.long 0x00 22. " FAULTEN2 ,Fault Control Enable For n = 4" "Disabled,Enabled" newline bitfld.long 0x00 21. " SYNCEN2 ,Synchronization enable for n = 4" "Disabled,Enabled" bitfld.long 0x00 20. " DTEN2 ,Deadtime enable for n = 4" "Disabled,Enabled" bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures for n = 4" "Inactive,Active" bitfld.long 0x00 18. " DECAPEN2 ,Dual Edge Capture Mode Enable for n = 4" "Disabled,Enabled" newline bitfld.long 0x00 17. " COMP2 ,Complement of channel (N) for n = 4" "Same,Complemented" bitfld.long 0x00 16. " COMBINE2 ,Combine channels for n = 4" "Independed,Combined" bitfld.long 0x00 14. " FAULTEN1 ,Fault Control Enable For n = 2" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,Synchronization enable for n = 2" "Disabled,Enabled" newline bitfld.long 0x00 12. " DTEN1 ,Deadtime enable for n = 2" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures for n = 2" "Inactive,Active" bitfld.long 0x00 10. " DECAPEN1 ,Dual Edge Capture Mode Enable for n = 2" "Disabled,Enabled" bitfld.long 0x00 9. " COMP1 ,Complement of channel (N) for n = 2" "Same,Complemented" newline bitfld.long 0x00 8. " COMBINE1 ,Combine channels for n = 2" "Independed,Combined" bitfld.long 0x00 6. " FAULTEN0 ,Fault Control Enable For n = 0" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,Synchronization enable for n = 0" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime enable for n = 0" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures for n = 0" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual Edge Capture Mode Enable for n = 0" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complement of channel (N) for n = 0" "Same,Complemented" bitfld.long 0x00 0. " COMBINE0 ,Combine channels for n = 0" "Independed,Combined" line.long 0x04 "DEADTIME,Deadtime Insertion Control" bitfld.long 0x04 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x04 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x64++0x03 line.long 0x00 "COMBINE,Function For Linked Channels" rbitfld.long 0x00 30. " FAULTEN3 ,Fault Control Enable For n = 6" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,Synchronization enable for n = 6" "Disabled,Enabled" rbitfld.long 0x00 28. " DTEN3 ,Deadtime enable for n = 6" "Disabled,Enabled" bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures for n = 6" "Inactive,Active" newline rbitfld.long 0x00 26. " DECAPEN3 ,Dual Edge Capture Mode Enable for n = 6" "Disabled,Enabled" rbitfld.long 0x00 25. " COMP3 ,Complement of channel (N) for n = 6" "Same,Complemented" rbitfld.long 0x00 24. " COMBINE3 ,Combine channels for n = 6" "Independed,Combined" rbitfld.long 0x00 22. " FAULTEN2 ,Fault Control Enable For n = 4" "Disabled,Enabled" newline bitfld.long 0x00 21. " SYNCEN2 ,Synchronization enable for n = 4" "Disabled,Enabled" rbitfld.long 0x00 20. " DTEN2 ,Deadtime enable for n = 4" "Disabled,Enabled" bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures for n = 4" "Inactive,Active" rbitfld.long 0x00 18. " DECAPEN2 ,Dual Edge Capture Mode Enable for n = 4" "Disabled,Enabled" newline rbitfld.long 0x00 17. " COMP2 ,Complement of channel (N) for n = 4" "Same,Complemented" rbitfld.long 0x00 16. " COMBINE2 ,Combine channels for n = 4" "Independed,Combined" rbitfld.long 0x00 14. " FAULTEN1 ,Fault Control Enable For n = 2" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,Synchronization enable for n = 2" "Disabled,Enabled" newline rbitfld.long 0x00 12. " DTEN1 ,Deadtime enable for n = 2" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures for n = 2" "Inactive,Active" rbitfld.long 0x00 10. " DECAPEN1 ,Dual Edge Capture Mode Enable for n = 2" "Disabled,Enabled" rbitfld.long 0x00 9. " COMP1 ,Complement of channel (N) for n = 2" "Same,Complemented" newline rbitfld.long 0x00 8. " COMBINE1 ,Combine channels for n = 2" "Independed,Combined" rbitfld.long 0x00 6. " FAULTEN0 ,Fault Control Enable For n = 0" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,Synchronization enable for n = 0" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable for n = 0" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures for n = 0" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual Edge Capture Mode Enable for n = 0" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complement of channel (N) for n = 0" "Same,Complemented" rbitfld.long 0x00 0. " COMBINE0 ,Combine channels for n = 0" "Independed,Combined" rgroup.long 0x68++0x03 line.long 0x00 "DEADTIME,Deadtime Insertion Control" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x6C++0x03 line.long 0x00 "EXTTRIG,FTM External Trigger" rbitfld.long 0x00 7. " TRIGF ,Channel trigger flag" "Not occurred,Occurred" bitfld.long 0x00 6. " INITTRIGEN ,Initialization trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " CH1TRIG ,Channel 1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 4. " CH0TRIG ,Channel 0 trigger enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " CH5TRIG ,Channel 5 trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " CH4TRIG ,Channel 4 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " CH3TRIG ,Channel 3 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " CH2TRIG ,Channel 2 trigger enable" "Disabled,Enabled" if (((per.l(ad:0x400B9000+0x54))&0x04)==0x04) group.long 0x70++0x03 line.long 0x00 "POL,Channels Polarity" bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "High,Low" bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "High,Low" bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "High,Low" bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "High,Low" newline bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "High,Low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "High,Low" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "High,Low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "High,Low" else rgroup.long 0x70++0x03 line.long 0x00 "POL,Channels Polarity" bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "High,Low" bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "High,Low" bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "High,Low" bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "High,Low" newline bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "High,Low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "High,Low" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "High,Low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "High,Low" endif hgroup.long 0x74++0x03 hide.long 0x00 "FMS,Fault Mode Status" in newline group.long 0x78++0x03 line.long 0x00 "FILTER,Input Capture Filter Control" bitfld.long 0x00 12.--15. " CH3FVAL ,Channel 3 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " CH2FVAL ,Channel 2 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (((per.l(ad:0x400B9000+0x54))&0x04)==0x04) group.long 0x7C++0x03 line.long 0x00 "FLTCTRL,Fault Control" bitfld.long 0x00 8.--11. " FFVAL ,Fault Input Filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " FFLTR3EN ,Fault Input 3 Filter Enable" "Disabled,Enabled" bitfld.long 0x00 6. " FFLTR2EN ,Fault Input 2 Filter Enable" "Disabled,Enabled" bitfld.long 0x00 5. " FFLTR1EN ,Fault Input 1 Filter Enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " FFLTR0EN ,Fault Input 0 Filter Enable" "Disabled,Enabled" bitfld.long 0x00 3. " FAULT3EN ,Fault Input 3 Enable" "Disabled,Enabled" bitfld.long 0x00 2. " FAULT2EN ,Fault Input 2 Enable" "Disabled,Enabled" bitfld.long 0x00 1. " FAULT1EN ,Fault Input 1 Enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " FAULT0EN ,Fault Input 0 Enable" "Disabled,Enabled" else group.long 0x7C++0x03 line.long 0x00 "FLTCTRL,Fault Control" bitfld.long 0x00 8.--11. " FFVAL ,Fault Input Filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 7. " FFLTR3EN ,Fault Input 3 Filter Enable" "Disabled,Enabled" rbitfld.long 0x00 6. " FFLTR2EN ,Fault Input 2 Filter Enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FFLTR1EN ,Fault Input 1 Filter Enable" "Disabled,Enabled" newline rbitfld.long 0x00 4. " FFLTR0EN ,Fault Input 0 Filter Enable" "Disabled,Enabled" rbitfld.long 0x00 3. " FAULT3EN ,Fault Input 3 Enable" "Disabled,Enabled" rbitfld.long 0x00 2. " FAULT2EN ,Fault Input 2 Enable" "Disabled,Enabled" rbitfld.long 0x00 1. " FAULT1EN ,Fault Input 1 Enable" "Disabled,Enabled" newline rbitfld.long 0x00 0. " FAULT0EN ,Fault Input 0 Enable" "Disabled,Enabled" endif if (((per.l(ad:0x400B9000+0x54))&0x04)==0x04) group.long 0x80++0x03 line.long 0x00 "QDCTRL,Quadrature Decoder Control And Status" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" newline bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "A and B encoding,Count and direction encoding" rbitfld.long 0x00 2. " QUADIR ,FTM counter direction in quadrature decoder mode" "Decreasing,Increasing" rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Bottom,Top" bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "QDCTRL,Quadrature Decoder Control And Status" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" newline bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "A and B encoding,Count and direction encoding" rbitfld.long 0x00 2. " QUADIR ,FTM counter direction in quadrature decoder mode" "Decreasing,Increasing" rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Bottom,Top" rbitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "CONF,Configuration" bitfld.long 0x00 10. " GTBEOUT ,Global time base output" "Disabled,Enabled" bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " BDMMODE ,Selects the FTM behavior in BDM mode" "0,1,2,3" bitfld.long 0x00 0.--4. " NUMTOF ,Selects the ratio between the number of counter overflows to the number of times the TOF bit is set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x400B9000+0x54))&0x04)==0x04) group.long 0x88++0x03 line.long 0x00 "FLTPOL,FTM Fault Input Polarity" bitfld.long 0x00 3. " FLT3POL ,Fault Input 3 Polarity" "Active high,Active low" bitfld.long 0x00 2. " FLT2POL ,Fault Input 2 Polarity" "Active high,Active low" bitfld.long 0x00 1. " FLT1POL ,Fault Input 1 Polarity" "Active high,Active low" bitfld.long 0x00 0. " FLT0POL ,Fault Input 0 Polarity" "Active high,Active low" else rgroup.long 0x88++0x03 line.long 0x00 "FLTPOL,FTM Fault Input Polarity" bitfld.long 0x00 3. " FLT3POL ,Fault Input 3 Polarity" "Active high,Active low" bitfld.long 0x00 2. " FLT2POL ,Fault Input 2 Polarity" "Active high,Active low" bitfld.long 0x00 1. " FLT1POL ,Fault Input 1 Polarity" "Active high,Active low" bitfld.long 0x00 0. " FLT0POL ,Fault Input 0 Polarity" "Active high,Active low" endif group.long 0x8C++0x0F line.long 0x00 "SYNCONF,Synchronization Configuration" bitfld.long 0x00 20. " HWSOC ,Software output control synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 18. " HWOM ,Output mask synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 17. " HWWRBUF ,MOD CNTIN and CV registers synchronization is activated by a hardware trigger" "Not activated,Activated" newline bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 12. " SWSOC ,Software output control synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 10. " SWOM ,Output mask synchronization is activated by the software trigger" "Not activated,Activated" newline bitfld.long 0x00 9. " SWWRBUF ,MOD CNTIN and CV registers synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 7. " SYNCMODE ,Synchronization mode" "Legacy PWM,Enhanced PWM" bitfld.long 0x00 5. " SWOC ,SWOCTRL register synchronization" "At rising edges of system clock,PWM synchronization" newline bitfld.long 0x00 4. " INVC ,INVCTRL register synchronization" "At rising edges of system clock,PWM synchronization" bitfld.long 0x00 2. " CNTINC ,CNTIN register synchronization" "At rising edges of system clock,PWM synchronization" bitfld.long 0x00 0. " HWTRIGMODE ,Hardware trigger mode" "Cleared,Not cleared" line.long 0x04 "INVCTRL,FTM Inverting Control" bitfld.long 0x04 3. " INV3EN ,Pair channels 3 inverting enable" "Disabled,Enabled" bitfld.long 0x04 2. " INV2EN ,Pair channels 2 inverting enable" "Disabled,Enabled" bitfld.long 0x04 1. " INV1EN ,Pair channels 1 inverting enable" "Disabled,Enabled" bitfld.long 0x04 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled" line.long 0x08 "SWOCTRL,FTM Software Output Control" bitfld.long 0x08 15. " CH7OCV ,Channel 7 software output control value" "Force 0,Force 1" bitfld.long 0x08 14. " CH6OCV ,Channel 6 software output control value" "Force 0,Force 1" bitfld.long 0x08 13. " CH5OCV ,Channel 5 software output control value" "Force 0,Force 1" bitfld.long 0x08 12. " CH4OCV ,Channel 4 software output control value" "Force 0,Force 1" newline bitfld.long 0x08 11. " CH3OCV ,Channel 3 software output control value" "Force 0,Force 1" bitfld.long 0x08 10. " CH2OCV ,Channel 2 software output control value" "Force 0,Force 1" bitfld.long 0x08 9. " CH1OCV ,Channel 1 software output control value" "Force 0,Force 1" bitfld.long 0x08 8. " CH0OCV ,Channel 0 software output control value" "Force 0,Force 1" newline bitfld.long 0x08 7. " CH7OC ,Channel 7 software output control enable" "Disabled,Enabled" bitfld.long 0x08 6. " CH6OC ,Channel 6 software output control enable" "Disabled,Enabled" bitfld.long 0x08 5. " CH5OC ,Channel 5 software output control enable" "Disabled,Enabled" bitfld.long 0x08 4. " CH4OC ,Channel 4 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled" bitfld.long 0x08 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled" bitfld.long 0x08 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled" bitfld.long 0x08 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled" line.long 0x0C "PWMLOAD,FTM PWM Load" bitfld.long 0x0C 9. " LDOK ,Load enable" "Disabled,Enabled" newline bitfld.long 0x0C 7. " CH7SEL ,Channel 7 select" "Not included,Included" bitfld.long 0x0C 6. " CH6SEL ,Channel 6 select" "Not included,Included" bitfld.long 0x0C 5. " CH5SEL ,Channel 5 select" "Not included,Included" bitfld.long 0x0C 4. " CH4SEL ,Channel 4 select" "Not included,Included" newline bitfld.long 0x0C 3. " CH3SEL ,Channel 3 select" "Not included,Included" bitfld.long 0x0C 2. " CH2SEL ,Channel 2 select" "Not included,Included" bitfld.long 0x0C 1. " CH1SEL ,Channel 1 select" "Not included,Included" bitfld.long 0x0C 0. " CH0SEL ,Channel 0 select" "Not included,Included" width 0x0B tree.end tree.end tree.open "TPM (Timer/PWM Module)" tree "TPM_1" base ad:0x400C9000 width 13. group.long 0x00++0x0B line.long 0x00 "TPM1_SC,Status And Control" sif !cpuis("MKL02*")&&!cpuis("MKL03Z*") bitfld.long 0x00 8. " DMA ,DMA enable" "Disabled,Enabled" newline endif eventfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting mode,Up-down counting mode" newline bitfld.long 0x00 3.--4. " CMOD ,Clock mode selection" "Disabled,Incremented on TPM counter clock,Incremented on rising edge of TPM_EXTCLK,?..." bitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" line.long 0x04 "TPM1_CNT,Counter" hexmask.long.word 0x04 0.--15. 1. " COUNT ,Counter value" line.long 0x08 "TPM1_MOD,Modulo" hexmask.long.word 0x08 0.--15. 1. " MOD ,Modulo value" newline sif cpuis("MK8?FN256V*") if ((per.l(ad:0x400C9000)&0x20)==0x00)&&((per.l(ad:0x400C9000+0xC)&0x30)==0x00)&&((per.l(ad:0x400C9000+0xC)&0xC)==0x00) group.long 0xC++0x03 line.long 0x00 "TPM1_C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" "None,Software compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((per.l(ad:0x400C9000)&0x20)==0x00)&&((per.l(ad:0x400C9000+0xC)&0x30)==0x10)&&((per.l(ad:0x400C9000+0xC)&0xC)==0x00) group.long 0xC++0x03 line.long 0x00 "TPM1_C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" "None,Software compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Not used,Toggle,Clear,Set" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((per.l(ad:0x400C9000)&0x20)==0x00)&&((per.l(ad:0x400C9000+0xC)&0x30)==0x00)&&((per.l(ad:0x400C9000+0xC)&0xC)!=0x00) group.long 0xC++0x03 line.long 0x00 "TPM1_C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((per.l(ad:0x400C9000)&0x20)==0x00)&&((per.l(ad:0x400C9000+0xC)&0x30)==0x10)&&((per.l(ad:0x400C9000+0xC)&0xC)!=0x00) group.long 0xC++0x03 line.long 0x00 "TPM1_C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Not used,Toggle,Clear,Set" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((per.l(ad:0x400C9000)&0x20)==0x00)&&((per.l(ad:0x400C9000+0xC)&0x30)==0x20)&&((per.l(ad:0x400C9000+0xC)&0xC)!=0x00) group.long 0xC++0x03 line.long 0x00 "TPM1_C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" ",Low,High,Low" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((per.l(ad:0x400C9000)&0x20)==0x00)&&((per.l(ad:0x400C9000+0xC)&0x30)==0x30)&&((per.l(ad:0x400C9000+0xC)&0xC)!=0x00) group.long 0xC++0x03 line.long 0x00 "TPM1_C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" ",High,Low,?..." bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((per.l(ad:0x400C9000)&0x20)==0x20)&&((per.l(ad:0x400C9000+0xC)&0x30)==0x00)&&((per.l(ad:0x400C9000+0xC)&0xC)==0x00) group.long 0xC++0x03 line.long 0x00 "TPM1_C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" "None,Software compare,Center-aligned PWM,?..." newline bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Disabled,Low,High,?..." bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((per.l(ad:0x400C9000)&0x20)==0x20)&&((per.l(ad:0x400C9000+0xC)&0x30)==0x10)&&((per.l(ad:0x400C9000+0xC)&0xC)==0x00) group.long 0xC++0x03 line.long 0x00 "TPM1_C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" "None,Software compare,Center-aligned PWM,?..." newline bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Not used,Low,High,?..." bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((per.l(ad:0x400C9000)&0x20)==0x20)&&((per.l(ad:0x400C9000+0xC)&0x30)==0x00)&&((per.l(ad:0x400C9000+0xC)&0xC)!=0x00) group.long 0xC++0x03 line.long 0x00 "TPM1_C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" ",,Center-aligned PWM,?..." newline bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Disabled,?..." bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((per.l(ad:0x400C9000)&0x20)==0x20)&&((per.l(ad:0x400C9000+0xC)&0x30)==0x20)&&((per.l(ad:0x400C9000+0xC)&0xC)!=0x00) group.long 0xC++0x03 line.long 0x00 "TPM1_C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" ",,Center-aligned PWM,?..." newline bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" ",Low,High,?..." bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((per.l(ad:0x400C9000)&0x20)==0x20)&&((per.l(ad:0x400C9000+0xC)&0x10)==0x20)&&((per.l(ad:0x400C9000+0xC)&0xC)!=0x00) group.long 0xC++0x03 line.long 0x00 "TPM1_C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" ",,Center-aligned PWM,?..." newline bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Not used,?..." bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "TPM1_C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" ",,Center-aligned PWM,?..." newline bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "?..." bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif group.long (0xC+0x04)++0x03 line.long 0x00 "TPM1_C0V,Channel 0 Value" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" if ((per.l(ad:0x400C9000)&0x20)==0x00)&&((per.l(ad:0x400C9000+0x14)&0x30)==0x00)&&((per.l(ad:0x400C9000+0x14)&0xC)==0x00) group.long 0x14++0x03 line.long 0x00 "TPM1_C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" "None,Software compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((per.l(ad:0x400C9000)&0x20)==0x00)&&((per.l(ad:0x400C9000+0x14)&0x30)==0x10)&&((per.l(ad:0x400C9000+0x14)&0xC)==0x00) group.long 0x14++0x03 line.long 0x00 "TPM1_C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" "None,Software compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Not used,Toggle,Clear,Set" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((per.l(ad:0x400C9000)&0x20)==0x00)&&((per.l(ad:0x400C9000+0x14)&0x30)==0x00)&&((per.l(ad:0x400C9000+0x14)&0xC)!=0x00) group.long 0x14++0x03 line.long 0x00 "TPM1_C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((per.l(ad:0x400C9000)&0x20)==0x00)&&((per.l(ad:0x400C9000+0x14)&0x30)==0x10)&&((per.l(ad:0x400C9000+0x14)&0xC)!=0x00) group.long 0x14++0x03 line.long 0x00 "TPM1_C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Not used,Toggle,Clear,Set" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((per.l(ad:0x400C9000)&0x20)==0x00)&&((per.l(ad:0x400C9000+0x14)&0x30)==0x20)&&((per.l(ad:0x400C9000+0x14)&0xC)!=0x00) group.long 0x14++0x03 line.long 0x00 "TPM1_C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" ",Low,High,Low" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((per.l(ad:0x400C9000)&0x20)==0x00)&&((per.l(ad:0x400C9000+0x14)&0x30)==0x30)&&((per.l(ad:0x400C9000+0x14)&0xC)!=0x00) group.long 0x14++0x03 line.long 0x00 "TPM1_C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" ",High,Low,?..." bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((per.l(ad:0x400C9000)&0x20)==0x20)&&((per.l(ad:0x400C9000+0x14)&0x30)==0x00)&&((per.l(ad:0x400C9000+0x14)&0xC)==0x00) group.long 0x14++0x03 line.long 0x00 "TPM1_C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" "None,Software compare,Center-aligned PWM,?..." newline bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Disabled,Low,High,?..." bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((per.l(ad:0x400C9000)&0x20)==0x20)&&((per.l(ad:0x400C9000+0x14)&0x30)==0x10)&&((per.l(ad:0x400C9000+0x14)&0xC)==0x00) group.long 0x14++0x03 line.long 0x00 "TPM1_C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" "None,Software compare,Center-aligned PWM,?..." newline bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Not used,Low,High,?..." bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((per.l(ad:0x400C9000)&0x20)==0x20)&&((per.l(ad:0x400C9000+0x14)&0x30)==0x00)&&((per.l(ad:0x400C9000+0x14)&0xC)!=0x00) group.long 0x14++0x03 line.long 0x00 "TPM1_C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" ",,Center-aligned PWM,?..." newline bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Disabled,?..." bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((per.l(ad:0x400C9000)&0x20)==0x20)&&((per.l(ad:0x400C9000+0x14)&0x30)==0x20)&&((per.l(ad:0x400C9000+0x14)&0xC)!=0x00) group.long 0x14++0x03 line.long 0x00 "TPM1_C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" ",,Center-aligned PWM,?..." newline bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" ",Low,High,?..." bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((per.l(ad:0x400C9000)&0x20)==0x20)&&((per.l(ad:0x400C9000+0x14)&0x10)==0x20)&&((per.l(ad:0x400C9000+0x14)&0xC)!=0x00) group.long 0x14++0x03 line.long 0x00 "TPM1_C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" ",,Center-aligned PWM,?..." newline bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Not used,?..." bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "TPM1_C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" ",,Center-aligned PWM,?..." newline bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "?..." bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif group.long (0x14+0x04)++0x03 line.long 0x00 "TPM1_C1V,Channel 1 Value" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" else if ((per.l(ad:0x400C9000)&0x20)==0x00)&&((per.l(ad:0x400C9000+0xC)&0x30)==0x00) group.long 0xC++0x03 line.long 0x00 "TPM1_C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/input capture,Software compare/output compare,Software compare/edge-aligned PWM,Software compare/output compare" newline bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Disabled,Rising,Falling,Both" sif !cpuis("MKL02*")&&!cpuis("MKL03Z*") newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif elif ((per.l(ad:0x400C9000)&0x20)==0x00)&&((per.l(ad:0x400C9000+0xC)&0x30)==0x10) group.long 0xC++0x03 line.long 0x00 "TPM1_C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/input capture,Software compare/output compare,Software compare/edge-aligned PWM,Software compare/output compare" newline bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Not used,Toggle,Clear,Set" sif !cpuis("MKL02*")&&!cpuis("MKL03Z*") newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif elif ((per.l(ad:0x400C9000)&0x20)==0x00)&&((per.l(ad:0x400C9000+0xC)&0x30)==0x20) group.long 0xC++0x03 line.long 0x00 "TPM1_C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/input capture,Software compare/output compare,Software compare/edge-aligned PWM,Software compare/output compare" newline bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Not used,Low,High,Low" sif !cpuis("MKL02*")&&!cpuis("MKL03Z*") newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif elif ((per.l(ad:0x400C9000)&0x20)==0x00)&&((per.l(ad:0x400C9000+0xC)&0x30)==0x30) group.long 0xC++0x03 line.long 0x00 "TPM1_C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/input capture,Software compare/output compare,Software compare/edge-aligned PWM,Software compare/output compare" newline bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Not used,High,Low,High" sif !cpuis("MKL02*")&&!cpuis("MKL03Z*") newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif elif ((per.l(ad:0x400C9000)&0x20)==0x20)&&((per.l(ad:0x400C9000+0xC)&0x30)==0x00) group.long 0xC++0x03 line.long 0x00 "TPM1_C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/reserved,Software compare/reserved,Software compare/center-aligned PWM,Software compare/reserved" newline bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Disabled,?..." sif !cpuis("MKL02*")&&!cpuis("MKL03Z*") newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif elif ((per.l(ad:0x400C9000)&0x20)==0x20)&&((per.l(ad:0x400C9000+0xC)&0x30)==0x20) group.long 0xC++0x03 line.long 0x00 "TPM1_C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/reserved,Software compare/reserved,Software compare/center-aligned PWM,Software compare/reserved" newline bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Not used,Low,High,Low" sif !cpuis("MKL02*")&&!cpuis("MKL03Z*") newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else group.long 0xC++0x03 line.long 0x00 "TPM1_C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/reserved,Software compare/reserved,Software compare/center-aligned PWM,Software compare/reserved" newline bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Not used,?..." sif !cpuis("MKL02*")&&!cpuis("MKL03Z*") newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif group.long (0xC+0x04)++0x03 line.long 0x00 "TPM1_C0V,Channel 0 Value" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" if ((per.l(ad:0x400C9000)&0x20)==0x00)&&((per.l(ad:0x400C9000+0x14)&0x30)==0x00) group.long 0x14++0x03 line.long 0x00 "TPM1_C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/input capture,Software compare/output compare,Software compare/edge-aligned PWM,Software compare/output compare" newline bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Disabled,Rising,Falling,Both" sif !cpuis("MKL02*")&&!cpuis("MKL03Z*") newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif elif ((per.l(ad:0x400C9000)&0x20)==0x00)&&((per.l(ad:0x400C9000+0x14)&0x30)==0x10) group.long 0x14++0x03 line.long 0x00 "TPM1_C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/input capture,Software compare/output compare,Software compare/edge-aligned PWM,Software compare/output compare" newline bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Not used,Toggle,Clear,Set" sif !cpuis("MKL02*")&&!cpuis("MKL03Z*") newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif elif ((per.l(ad:0x400C9000)&0x20)==0x00)&&((per.l(ad:0x400C9000+0x14)&0x30)==0x20) group.long 0x14++0x03 line.long 0x00 "TPM1_C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/input capture,Software compare/output compare,Software compare/edge-aligned PWM,Software compare/output compare" newline bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Not used,Low,High,Low" sif !cpuis("MKL02*")&&!cpuis("MKL03Z*") newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif elif ((per.l(ad:0x400C9000)&0x20)==0x00)&&((per.l(ad:0x400C9000+0x14)&0x30)==0x30) group.long 0x14++0x03 line.long 0x00 "TPM1_C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/input capture,Software compare/output compare,Software compare/edge-aligned PWM,Software compare/output compare" newline bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Not used,High,Low,High" sif !cpuis("MKL02*")&&!cpuis("MKL03Z*") newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif elif ((per.l(ad:0x400C9000)&0x20)==0x20)&&((per.l(ad:0x400C9000+0x14)&0x30)==0x00) group.long 0x14++0x03 line.long 0x00 "TPM1_C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/reserved,Software compare/reserved,Software compare/center-aligned PWM,Software compare/reserved" newline bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Disabled,?..." sif !cpuis("MKL02*")&&!cpuis("MKL03Z*") newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif elif ((per.l(ad:0x400C9000)&0x20)==0x20)&&((per.l(ad:0x400C9000+0x14)&0x30)==0x20) group.long 0x14++0x03 line.long 0x00 "TPM1_C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/reserved,Software compare/reserved,Software compare/center-aligned PWM,Software compare/reserved" newline bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Not used,Low,High,Low" sif !cpuis("MKL02*")&&!cpuis("MKL03Z*") newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else group.long 0x14++0x03 line.long 0x00 "TPM1_C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/reserved,Software compare/reserved,Software compare/center-aligned PWM,Software compare/reserved" newline bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Not used,?..." sif !cpuis("MKL02*")&&!cpuis("MKL03Z*") newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif group.long (0x14+0x04)++0x03 line.long 0x00 "TPM1_C1V,Channel 1 Value" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" endif newline group.long 0x50++0x03 line.long 0x00 "TPM1_STATUS,Capture And Compare Status" eventfld.long 0x00 8. " TOF ,Timer overflow flag" "No overflow,Overflow" newline eventfld.long 0x00 1. " CH_1F ,Channel 1 flag" "Not occurred,Occurred" eventfld.long 0x00 0. " CH_0F ,Channel 0 flag" "Not occurred,Occurred" sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MKL82Z*") group.long 0x64++0x03 line.long 0x00 "TPM1_COMBINE,Combine Channel Register" bitfld.long 0x00 1. " COMSWAP0 ,Combine Channel 0 and 1 Swap" "Not swapped,Swapped" bitfld.long 0x00 0. " COMBINE0 ,Combine Channels 0 and 1 Enable" "Disabled,Enabled" endif sif cpuis("MKL13*")||cpuis("MKL17Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")||cpuis("MK84FN2M0CAU15R*")||cpuis("MK8?FN256V*")||cpuis("MKL82Z*") group.long 0x70++0x03 line.long 0x00 "TPM1_POL,Channel Polarity" bitfld.long 0x00 1. " POL_1 ,Channel 1 polarity" "High,Low" bitfld.long 0x00 0. " POL_0 ,Channel 0 polarity" "High,Low" endif newline sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MKL82Z*") sif cpuis("MK84FN2M0CAU15R") group.long 0x78++0x03 line.long 0x00 "TPM1_FILTER,Filter Control" bitfld.long 0x00 4.--7. " CH1FVAL ,Channel 1 Filter Value" "Disabled,4 clock cycles,8 clock cycles,12 clock cycles,16 clock cycles,40 clock cycles,48 clock cycles,56 clock cycles,64 clock cycles,72 clock cycles,80 clock cycles,88 clock cycles,96 clock cycles,104 clock cycles,112 clock cycles,116 clock cycles" bitfld.long 0x00 0.--3. " CH1FVAL ,Channel 0 Filter Value" "Disabled,4 clock cycles,8 clock cycles,12 clock cycles,16 clock cycles,40 clock cycles,48 clock cycles,56 clock cycles,64 clock cycles,72 clock cycles,80 clock cycles,88 clock cycles,96 clock cycles,104 clock cycles,112 clock cycles,116 clock cycles" else group.long 0x78++0x03 line.long 0x00 "TPM1_FILTER,Filter Control" bitfld.long 0x00 4.--7. " CH1FVAL ,Channel 1 Filter Value" "Disabled,4 clock cycles,8 clock cycles,12 clock cycles,16 clock cycles,20 clock cycles,24 clock cycles,28 clock cycles,32 clock cycles,36 clock cycles,40 clock cycles,44 clock cycles,48 clock cycles,52 clock cycles,56 clock cycles,60 clock cycles" bitfld.long 0x00 0.--3. " CH1FVAL ,Channel 0 Filter Value" "Disabled,4 clock cycles,8 clock cycles,12 clock cycles,16 clock cycles,20 clock cycles,24 clock cycles,28 clock cycles,32 clock cycles,36 clock cycles,40 clock cycles,44 clock cycles,48 clock cycles,52 clock cycles,56 clock cycles,60 clock cycles" endif group.long 0x80++0x03 line.long 0x00 "TPM1_QDCTRL,Quadrature Decoder Control and Status" bitfld.long 0x00 3. " QUADMODE ,Selects encoding mode used in quadrature decoder mode" "Phase encode,Count and direction encode" rbitfld.long 0x00 2. " QUADIR ,Counter Direction in Quadrature Decode Mode" "Decrement,Increment" rbitfld.long 0x00 1. " TOFDIR ,TOF bit was set on the top or the bottom of counting" "Bottom,Top" newline bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" endif sif cpuis("MKL17Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MKL82Z*") if (((per.l(ad:0x400C9000+0x84)&0x800000))==0x00) group.long 0x84++0x03 line.long 0x00 "TPM1_CONF,Configuration" sif cpuis("MK84FN2M0CAU15R") bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "EXTRG_IN,CMP_0,,,PIT Ch.0 Output,PIT Ch.1 Output,PIT Ch.2 Output,PIT Ch.3 Output,FTM_0 trigger,FTM_1 trigger,FTM_2 trigger,FTM_3 trigger,RTC alarm,RTC seconds,LPTMR Output,Software Trigger" newline elif cpuis("MK8?FN256V*") bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "EXTRG_IN,CMP_0,CMP_1,,PIT Ch.0 Output,PIT Ch.1 Output,PIT Ch.2 Output,PIT Ch.3 Output,FTM_0 trigger,FTM_1 trigger,FTM_2 trigger,FTM_3 trigger,RTC alarm,RTC seconds,LPTMR Output,Software Trigger" newline else bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "EXTRG_IN,CMP0 output,,,PIT trigger 0,PIT trigger 1,,,TPM0 overflow,TPM1 overflow,TPM2 overflow,,RTC alarm,RTC seconds,LPTMR trigger,?..." newline endif bitfld.long 0x00 23. " TRGSRC ,Trigger source" "External,Internal" bitfld.long 0x00 22. " TRGPOL ,Trigger polarity" "Active high,Active low" bitfld.long 0x00 19. " CPOT ,Counter pause on trigger" "Disabled,Enabled" newline bitfld.long 0x00 18. " CROT ,Counter reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 17. " CSOO ,Counter stop on overflow" "Not stopped,Stopped" bitfld.long 0x00 16. " CSOT ,Counter start on trigger" "Not started,Started" newline bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled" bitfld.long 0x00 8. " GTBSYNC ,Global time base synchronization" "Disabled,Enabled" bitfld.long 0x00 6.--7. " DBGMODE ,Debug mode" "LPTPM paused,,,LPTPM enabled" newline bitfld.long 0x00 5. " DOZEEN ,Doze enable" "Disabled,Enabled" else group.long 0x84++0x03 line.long 0x00 "TPM1_CONF,Configuration" sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*") bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" ",Ch_0 pin input capture,Ch_1 pin input capture,Ch_0 or ch_1 pin input capture,?..." newline else bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" ",Ch_0 pin input capture,Ch_1 pin input capture,Ch_0 or ch_1 pin input capture,Ch_2 pin input capture,Ch_0 or ch_2 pin input capture,Ch_1 or ch_2 pin input capture,Ch_0 or ch_1 or ch_2 pin input capture,Ch_3 pin input capture,Ch_0 or ch_3 pin input capture,Ch_1 or ch_3 pin input capture,Ch_0 or ch_1 or ch_3 pin input capture,Ch_2 or ch_3 pin input capture,Ch_0 or ch_2 or ch_3 pin input capture,Ch_1 or ch_2 or ch_3 pin input capture,Ch_0 or ch_1 or ch_2 or ch_3 pin input capture" newline endif bitfld.long 0x00 23. " TRGSRC ,Trigger source" "External,Internal" bitfld.long 0x00 22. " TRGPOL ,Trigger polarity" "Active high,Active low" bitfld.long 0x00 19. " CPOT ,Counter pause on trigger" "Disabled,Enabled" newline bitfld.long 0x00 18. " CROT ,Counter reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 17. " CSOO ,Counter stop on overflow" "Not stopped,Stopped" bitfld.long 0x00 16. " CSOT ,Counter start on trigger" "Not started,Started" newline bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled" bitfld.long 0x00 8. " GTBSYNC ,Global time base synchronization" "Disabled,Enabled" bitfld.long 0x00 6.--7. " DBGMODE ,Debug mode" "LPTPM paused,,,LPTPM enabled" newline bitfld.long 0x00 5. " DOZEEN ,Doze enable" "Disabled,Enabled" endif else group.long 0x84++0x03 line.long 0x00 "TPM1_CONF,Configuration" sif cpuis("MKL02*") bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "EXTRG_IN,CMP0 output,,,,,,,TPM0 overflow,TMP1 overflow,,,,,LPTMR trigger,?..." newline elif cpuis("MKL03Z*") bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "EXTRG_IN,CMP0 output,,,,,,,TPM0 overflow,TPM1 overflow,,,RTC alarm,RTC seconds,LPTMR trigger,?..." newline elif cpuis("MKL04*")||cpuis("MKL05*") bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "EXTRG_IN,CMP0 output,,,PIT trigger 0,PIT trigger 1,,,TPM0 overflow,TPM1 overflow,,,RTC alarm,RTC seconds,LPTMR trigger,?..." newline else bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "EXTRG_IN,CMP0 output,,,PIT trigger 0,PIT trigger 1,,,TPM0 overflow,TPM1 overflow,TPM2 overflow,,RTC alarm,RTC seconds,LPTMR trigger,?..." newline endif bitfld.long 0x00 18. " CROT ,Counter reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 17. " CSOO ,Counter stop on overflow" "Not stopped,Stopped" newline bitfld.long 0x00 16. " CSOT ,Counter start on trigger" "Not started,Started" bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled" newline bitfld.long 0x00 6.--7. " DBGMODE ,Debug mode" "LPTPM paused,,,LPTPM enabled" bitfld.long 0x00 5. " DOZEEN ,Doze enable" "Disabled,Enabled" endif width 0x0B tree.end tree "TPM_2" base ad:0x400CA000 width 13. group.long 0x00++0x0B line.long 0x00 "TPM2_SC,Status And Control" sif !cpuis("MKL02*")&&!cpuis("MKL03Z*") bitfld.long 0x00 8. " DMA ,DMA enable" "Disabled,Enabled" newline endif eventfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting mode,Up-down counting mode" newline bitfld.long 0x00 3.--4. " CMOD ,Clock mode selection" "Disabled,Incremented on TPM counter clock,Incremented on rising edge of TPM_EXTCLK,?..." bitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" line.long 0x04 "TPM2_CNT,Counter" hexmask.long.word 0x04 0.--15. 1. " COUNT ,Counter value" line.long 0x08 "TPM2_MOD,Modulo" hexmask.long.word 0x08 0.--15. 1. " MOD ,Modulo value" newline sif cpuis("MK8?FN256V*") if ((per.l(ad:0x400CA000)&0x20)==0x00)&&((per.l(ad:0x400CA000+0xC)&0x30)==0x00)&&((per.l(ad:0x400CA000+0xC)&0xC)==0x00) group.long 0xC++0x03 line.long 0x00 "TPM2_C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" "None,Software compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((per.l(ad:0x400CA000)&0x20)==0x00)&&((per.l(ad:0x400CA000+0xC)&0x30)==0x10)&&((per.l(ad:0x400CA000+0xC)&0xC)==0x00) group.long 0xC++0x03 line.long 0x00 "TPM2_C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" "None,Software compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Not used,Toggle,Clear,Set" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((per.l(ad:0x400CA000)&0x20)==0x00)&&((per.l(ad:0x400CA000+0xC)&0x30)==0x00)&&((per.l(ad:0x400CA000+0xC)&0xC)!=0x00) group.long 0xC++0x03 line.long 0x00 "TPM2_C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((per.l(ad:0x400CA000)&0x20)==0x00)&&((per.l(ad:0x400CA000+0xC)&0x30)==0x10)&&((per.l(ad:0x400CA000+0xC)&0xC)!=0x00) group.long 0xC++0x03 line.long 0x00 "TPM2_C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Not used,Toggle,Clear,Set" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((per.l(ad:0x400CA000)&0x20)==0x00)&&((per.l(ad:0x400CA000+0xC)&0x30)==0x20)&&((per.l(ad:0x400CA000+0xC)&0xC)!=0x00) group.long 0xC++0x03 line.long 0x00 "TPM2_C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" ",Low,High,Low" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((per.l(ad:0x400CA000)&0x20)==0x00)&&((per.l(ad:0x400CA000+0xC)&0x30)==0x30)&&((per.l(ad:0x400CA000+0xC)&0xC)!=0x00) group.long 0xC++0x03 line.long 0x00 "TPM2_C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" ",High,Low,?..." bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((per.l(ad:0x400CA000)&0x20)==0x20)&&((per.l(ad:0x400CA000+0xC)&0x30)==0x00)&&((per.l(ad:0x400CA000+0xC)&0xC)==0x00) group.long 0xC++0x03 line.long 0x00 "TPM2_C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" "None,Software compare,Center-aligned PWM,?..." newline bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Disabled,Low,High,?..." bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((per.l(ad:0x400CA000)&0x20)==0x20)&&((per.l(ad:0x400CA000+0xC)&0x30)==0x10)&&((per.l(ad:0x400CA000+0xC)&0xC)==0x00) group.long 0xC++0x03 line.long 0x00 "TPM2_C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" "None,Software compare,Center-aligned PWM,?..." newline bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Not used,Low,High,?..." bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((per.l(ad:0x400CA000)&0x20)==0x20)&&((per.l(ad:0x400CA000+0xC)&0x30)==0x00)&&((per.l(ad:0x400CA000+0xC)&0xC)!=0x00) group.long 0xC++0x03 line.long 0x00 "TPM2_C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" ",,Center-aligned PWM,?..." newline bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Disabled,?..." bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((per.l(ad:0x400CA000)&0x20)==0x20)&&((per.l(ad:0x400CA000+0xC)&0x30)==0x20)&&((per.l(ad:0x400CA000+0xC)&0xC)!=0x00) group.long 0xC++0x03 line.long 0x00 "TPM2_C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" ",,Center-aligned PWM,?..." newline bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" ",Low,High,?..." bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((per.l(ad:0x400CA000)&0x20)==0x20)&&((per.l(ad:0x400CA000+0xC)&0x10)==0x20)&&((per.l(ad:0x400CA000+0xC)&0xC)!=0x00) group.long 0xC++0x03 line.long 0x00 "TPM2_C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" ",,Center-aligned PWM,?..." newline bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Not used,?..." bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "TPM2_C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select" ",,Center-aligned PWM,?..." newline bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "?..." bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif group.long (0xC+0x04)++0x03 line.long 0x00 "TPM2_C0V,Channel 0 Value" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" if ((per.l(ad:0x400CA000)&0x20)==0x00)&&((per.l(ad:0x400CA000+0x14)&0x30)==0x00)&&((per.l(ad:0x400CA000+0x14)&0xC)==0x00) group.long 0x14++0x03 line.long 0x00 "TPM2_C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" "None,Software compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((per.l(ad:0x400CA000)&0x20)==0x00)&&((per.l(ad:0x400CA000+0x14)&0x30)==0x10)&&((per.l(ad:0x400CA000+0x14)&0xC)==0x00) group.long 0x14++0x03 line.long 0x00 "TPM2_C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" "None,Software compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Not used,Toggle,Clear,Set" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((per.l(ad:0x400CA000)&0x20)==0x00)&&((per.l(ad:0x400CA000+0x14)&0x30)==0x00)&&((per.l(ad:0x400CA000+0x14)&0xC)!=0x00) group.long 0x14++0x03 line.long 0x00 "TPM2_C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((per.l(ad:0x400CA000)&0x20)==0x00)&&((per.l(ad:0x400CA000+0x14)&0x30)==0x10)&&((per.l(ad:0x400CA000+0x14)&0xC)!=0x00) group.long 0x14++0x03 line.long 0x00 "TPM2_C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Not used,Toggle,Clear,Set" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((per.l(ad:0x400CA000)&0x20)==0x00)&&((per.l(ad:0x400CA000+0x14)&0x30)==0x20)&&((per.l(ad:0x400CA000+0x14)&0xC)!=0x00) group.long 0x14++0x03 line.long 0x00 "TPM2_C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" ",Low,High,Low" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((per.l(ad:0x400CA000)&0x20)==0x00)&&((per.l(ad:0x400CA000+0x14)&0x30)==0x30)&&((per.l(ad:0x400CA000+0x14)&0xC)!=0x00) group.long 0x14++0x03 line.long 0x00 "TPM2_C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" "Input capture,Output compare,Edge-aligned PWM,Output compare" newline bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" ",High,Low,?..." bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((per.l(ad:0x400CA000)&0x20)==0x20)&&((per.l(ad:0x400CA000+0x14)&0x30)==0x00)&&((per.l(ad:0x400CA000+0x14)&0xC)==0x00) group.long 0x14++0x03 line.long 0x00 "TPM2_C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" "None,Software compare,Center-aligned PWM,?..." newline bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Disabled,Low,High,?..." bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((per.l(ad:0x400CA000)&0x20)==0x20)&&((per.l(ad:0x400CA000+0x14)&0x30)==0x10)&&((per.l(ad:0x400CA000+0x14)&0xC)==0x00) group.long 0x14++0x03 line.long 0x00 "TPM2_C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" "None,Software compare,Center-aligned PWM,?..." newline bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Not used,Low,High,?..." bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((per.l(ad:0x400CA000)&0x20)==0x20)&&((per.l(ad:0x400CA000+0x14)&0x30)==0x00)&&((per.l(ad:0x400CA000+0x14)&0xC)!=0x00) group.long 0x14++0x03 line.long 0x00 "TPM2_C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" ",,Center-aligned PWM,?..." newline bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Disabled,?..." bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((per.l(ad:0x400CA000)&0x20)==0x20)&&((per.l(ad:0x400CA000+0x14)&0x30)==0x20)&&((per.l(ad:0x400CA000+0x14)&0xC)!=0x00) group.long 0x14++0x03 line.long 0x00 "TPM2_C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" ",,Center-aligned PWM,?..." newline bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" ",Low,High,?..." bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif ((per.l(ad:0x400CA000)&0x20)==0x20)&&((per.l(ad:0x400CA000+0x14)&0x10)==0x20)&&((per.l(ad:0x400CA000+0x14)&0xC)!=0x00) group.long 0x14++0x03 line.long 0x00 "TPM2_C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" ",,Center-aligned PWM,?..." newline bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Not used,?..." bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "TPM2_C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select" ",,Center-aligned PWM,?..." newline bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "?..." bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif group.long (0x14+0x04)++0x03 line.long 0x00 "TPM2_C1V,Channel 1 Value" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" else if ((per.l(ad:0x400CA000)&0x20)==0x00)&&((per.l(ad:0x400CA000+0xC)&0x30)==0x00) group.long 0xC++0x03 line.long 0x00 "TPM2_C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/input capture,Software compare/output compare,Software compare/edge-aligned PWM,Software compare/output compare" newline bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Disabled,Rising,Falling,Both" sif !cpuis("MKL02*")&&!cpuis("MKL03Z*") newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif elif ((per.l(ad:0x400CA000)&0x20)==0x00)&&((per.l(ad:0x400CA000+0xC)&0x30)==0x10) group.long 0xC++0x03 line.long 0x00 "TPM2_C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/input capture,Software compare/output compare,Software compare/edge-aligned PWM,Software compare/output compare" newline bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Not used,Toggle,Clear,Set" sif !cpuis("MKL02*")&&!cpuis("MKL03Z*") newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif elif ((per.l(ad:0x400CA000)&0x20)==0x00)&&((per.l(ad:0x400CA000+0xC)&0x30)==0x20) group.long 0xC++0x03 line.long 0x00 "TPM2_C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/input capture,Software compare/output compare,Software compare/edge-aligned PWM,Software compare/output compare" newline bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Not used,Low,High,Low" sif !cpuis("MKL02*")&&!cpuis("MKL03Z*") newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif elif ((per.l(ad:0x400CA000)&0x20)==0x00)&&((per.l(ad:0x400CA000+0xC)&0x30)==0x30) group.long 0xC++0x03 line.long 0x00 "TPM2_C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/input capture,Software compare/output compare,Software compare/edge-aligned PWM,Software compare/output compare" newline bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Not used,High,Low,High" sif !cpuis("MKL02*")&&!cpuis("MKL03Z*") newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif elif ((per.l(ad:0x400CA000)&0x20)==0x20)&&((per.l(ad:0x400CA000+0xC)&0x30)==0x00) group.long 0xC++0x03 line.long 0x00 "TPM2_C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/reserved,Software compare/reserved,Software compare/center-aligned PWM,Software compare/reserved" newline bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Disabled,?..." sif !cpuis("MKL02*")&&!cpuis("MKL03Z*") newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif elif ((per.l(ad:0x400CA000)&0x20)==0x20)&&((per.l(ad:0x400CA000+0xC)&0x30)==0x20) group.long 0xC++0x03 line.long 0x00 "TPM2_C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/reserved,Software compare/reserved,Software compare/center-aligned PWM,Software compare/reserved" newline bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Not used,Low,High,Low" sif !cpuis("MKL02*")&&!cpuis("MKL03Z*") newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else group.long 0xC++0x03 line.long 0x00 "TPM2_C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS0B/MS0A ,Channel mode select (ELS0 = 0/ELS0 != 0)" "None/reserved,Software compare/reserved,Software compare/center-aligned PWM,Software compare/reserved" newline bitfld.long 0x00 2.--3. " ELS0B/ELS0A ,Edge or level select" "Not used,?..." sif !cpuis("MKL02*")&&!cpuis("MKL03Z*") newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif group.long (0xC+0x04)++0x03 line.long 0x00 "TPM2_C0V,Channel 0 Value" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" if ((per.l(ad:0x400CA000)&0x20)==0x00)&&((per.l(ad:0x400CA000+0x14)&0x30)==0x00) group.long 0x14++0x03 line.long 0x00 "TPM2_C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/input capture,Software compare/output compare,Software compare/edge-aligned PWM,Software compare/output compare" newline bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Disabled,Rising,Falling,Both" sif !cpuis("MKL02*")&&!cpuis("MKL03Z*") newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif elif ((per.l(ad:0x400CA000)&0x20)==0x00)&&((per.l(ad:0x400CA000+0x14)&0x30)==0x10) group.long 0x14++0x03 line.long 0x00 "TPM2_C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/input capture,Software compare/output compare,Software compare/edge-aligned PWM,Software compare/output compare" newline bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Not used,Toggle,Clear,Set" sif !cpuis("MKL02*")&&!cpuis("MKL03Z*") newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif elif ((per.l(ad:0x400CA000)&0x20)==0x00)&&((per.l(ad:0x400CA000+0x14)&0x30)==0x20) group.long 0x14++0x03 line.long 0x00 "TPM2_C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/input capture,Software compare/output compare,Software compare/edge-aligned PWM,Software compare/output compare" newline bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Not used,Low,High,Low" sif !cpuis("MKL02*")&&!cpuis("MKL03Z*") newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif elif ((per.l(ad:0x400CA000)&0x20)==0x00)&&((per.l(ad:0x400CA000+0x14)&0x30)==0x30) group.long 0x14++0x03 line.long 0x00 "TPM2_C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/input capture,Software compare/output compare,Software compare/edge-aligned PWM,Software compare/output compare" newline bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Not used,High,Low,High" sif !cpuis("MKL02*")&&!cpuis("MKL03Z*") newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif elif ((per.l(ad:0x400CA000)&0x20)==0x20)&&((per.l(ad:0x400CA000+0x14)&0x30)==0x00) group.long 0x14++0x03 line.long 0x00 "TPM2_C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/reserved,Software compare/reserved,Software compare/center-aligned PWM,Software compare/reserved" newline bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Disabled,?..." sif !cpuis("MKL02*")&&!cpuis("MKL03Z*") newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif elif ((per.l(ad:0x400CA000)&0x20)==0x20)&&((per.l(ad:0x400CA000+0x14)&0x30)==0x20) group.long 0x14++0x03 line.long 0x00 "TPM2_C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/reserved,Software compare/reserved,Software compare/center-aligned PWM,Software compare/reserved" newline bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Not used,Low,High,Low" sif !cpuis("MKL02*")&&!cpuis("MKL03Z*") newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else group.long 0x14++0x03 line.long 0x00 "TPM2_C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS1B/MS1A ,Channel mode select (ELS1 = 0/ELS1 != 0)" "None/reserved,Software compare/reserved,Software compare/center-aligned PWM,Software compare/reserved" newline bitfld.long 0x00 2.--3. " ELS1B/ELS1A ,Edge or level select" "Not used,?..." sif !cpuis("MKL02*")&&!cpuis("MKL03Z*") newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif group.long (0x14+0x04)++0x03 line.long 0x00 "TPM2_C1V,Channel 1 Value" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" endif newline group.long 0x50++0x03 line.long 0x00 "TPM2_STATUS,Capture And Compare Status" eventfld.long 0x00 8. " TOF ,Timer overflow flag" "No overflow,Overflow" newline eventfld.long 0x00 1. " CH_1F ,Channel 1 flag" "Not occurred,Occurred" eventfld.long 0x00 0. " CH_0F ,Channel 0 flag" "Not occurred,Occurred" sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MKL82Z*") group.long 0x64++0x03 line.long 0x00 "TPM2_COMBINE,Combine Channel Register" bitfld.long 0x00 1. " COMSWAP0 ,Combine Channel 0 and 1 Swap" "Not swapped,Swapped" bitfld.long 0x00 0. " COMBINE0 ,Combine Channels 0 and 1 Enable" "Disabled,Enabled" endif sif cpuis("MKL13*")||cpuis("MKL17Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")||cpuis("MK84FN2M0CAU15R*")||cpuis("MK8?FN256V*")||cpuis("MKL82Z*") group.long 0x70++0x03 line.long 0x00 "TPM2_POL,Channel Polarity" bitfld.long 0x00 1. " POL_1 ,Channel 1 polarity" "High,Low" bitfld.long 0x00 0. " POL_0 ,Channel 0 polarity" "High,Low" endif newline sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MKL82Z*") sif cpuis("MK84FN2M0CAU15R") group.long 0x78++0x03 line.long 0x00 "TPM2_FILTER,Filter Control" bitfld.long 0x00 4.--7. " CH1FVAL ,Channel 1 Filter Value" "Disabled,4 clock cycles,8 clock cycles,12 clock cycles,16 clock cycles,40 clock cycles,48 clock cycles,56 clock cycles,64 clock cycles,72 clock cycles,80 clock cycles,88 clock cycles,96 clock cycles,104 clock cycles,112 clock cycles,116 clock cycles" bitfld.long 0x00 0.--3. " CH1FVAL ,Channel 0 Filter Value" "Disabled,4 clock cycles,8 clock cycles,12 clock cycles,16 clock cycles,40 clock cycles,48 clock cycles,56 clock cycles,64 clock cycles,72 clock cycles,80 clock cycles,88 clock cycles,96 clock cycles,104 clock cycles,112 clock cycles,116 clock cycles" else group.long 0x78++0x03 line.long 0x00 "TPM2_FILTER,Filter Control" bitfld.long 0x00 4.--7. " CH1FVAL ,Channel 1 Filter Value" "Disabled,4 clock cycles,8 clock cycles,12 clock cycles,16 clock cycles,20 clock cycles,24 clock cycles,28 clock cycles,32 clock cycles,36 clock cycles,40 clock cycles,44 clock cycles,48 clock cycles,52 clock cycles,56 clock cycles,60 clock cycles" bitfld.long 0x00 0.--3. " CH1FVAL ,Channel 0 Filter Value" "Disabled,4 clock cycles,8 clock cycles,12 clock cycles,16 clock cycles,20 clock cycles,24 clock cycles,28 clock cycles,32 clock cycles,36 clock cycles,40 clock cycles,44 clock cycles,48 clock cycles,52 clock cycles,56 clock cycles,60 clock cycles" endif group.long 0x80++0x03 line.long 0x00 "TPM2_QDCTRL,Quadrature Decoder Control and Status" bitfld.long 0x00 3. " QUADMODE ,Selects encoding mode used in quadrature decoder mode" "Phase encode,Count and direction encode" rbitfld.long 0x00 2. " QUADIR ,Counter Direction in Quadrature Decode Mode" "Decrement,Increment" rbitfld.long 0x00 1. " TOFDIR ,TOF bit was set on the top or the bottom of counting" "Bottom,Top" newline bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" endif sif cpuis("MKL17Z*")||cpuis("MKL27Z*")||cpuis("MKL33Z*")||cpuis("MKL43Z*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MKL82Z*") if (((per.l(ad:0x400CA000+0x84)&0x800000))==0x00) group.long 0x84++0x03 line.long 0x00 "TPM2_CONF,Configuration" sif cpuis("MK84FN2M0CAU15R") bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "EXTRG_IN,CMP_0,,,PIT Ch.0 Output,PIT Ch.1 Output,PIT Ch.2 Output,PIT Ch.3 Output,FTM_0 trigger,FTM_1 trigger,FTM_2 trigger,FTM_3 trigger,RTC alarm,RTC seconds,LPTMR Output,Software Trigger" newline elif cpuis("MK8?FN256V*") bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "EXTRG_IN,CMP_0,CMP_1,,PIT Ch.0 Output,PIT Ch.1 Output,PIT Ch.2 Output,PIT Ch.3 Output,FTM_0 trigger,FTM_1 trigger,FTM_2 trigger,FTM_3 trigger,RTC alarm,RTC seconds,LPTMR Output,Software Trigger" newline else bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "EXTRG_IN,CMP0 output,,,PIT trigger 0,PIT trigger 1,,,TPM0 overflow,TPM1 overflow,TPM2 overflow,,RTC alarm,RTC seconds,LPTMR trigger,?..." newline endif bitfld.long 0x00 23. " TRGSRC ,Trigger source" "External,Internal" bitfld.long 0x00 22. " TRGPOL ,Trigger polarity" "Active high,Active low" bitfld.long 0x00 19. " CPOT ,Counter pause on trigger" "Disabled,Enabled" newline bitfld.long 0x00 18. " CROT ,Counter reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 17. " CSOO ,Counter stop on overflow" "Not stopped,Stopped" bitfld.long 0x00 16. " CSOT ,Counter start on trigger" "Not started,Started" newline bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled" bitfld.long 0x00 8. " GTBSYNC ,Global time base synchronization" "Disabled,Enabled" bitfld.long 0x00 6.--7. " DBGMODE ,Debug mode" "LPTPM paused,,,LPTPM enabled" newline bitfld.long 0x00 5. " DOZEEN ,Doze enable" "Disabled,Enabled" else group.long 0x84++0x03 line.long 0x00 "TPM2_CONF,Configuration" sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*") bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" ",Ch_0 pin input capture,Ch_1 pin input capture,Ch_0 or ch_1 pin input capture,?..." newline else bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" ",Ch_0 pin input capture,Ch_1 pin input capture,Ch_0 or ch_1 pin input capture,Ch_2 pin input capture,Ch_0 or ch_2 pin input capture,Ch_1 or ch_2 pin input capture,Ch_0 or ch_1 or ch_2 pin input capture,Ch_3 pin input capture,Ch_0 or ch_3 pin input capture,Ch_1 or ch_3 pin input capture,Ch_0 or ch_1 or ch_3 pin input capture,Ch_2 or ch_3 pin input capture,Ch_0 or ch_2 or ch_3 pin input capture,Ch_1 or ch_2 or ch_3 pin input capture,Ch_0 or ch_1 or ch_2 or ch_3 pin input capture" newline endif bitfld.long 0x00 23. " TRGSRC ,Trigger source" "External,Internal" bitfld.long 0x00 22. " TRGPOL ,Trigger polarity" "Active high,Active low" bitfld.long 0x00 19. " CPOT ,Counter pause on trigger" "Disabled,Enabled" newline bitfld.long 0x00 18. " CROT ,Counter reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 17. " CSOO ,Counter stop on overflow" "Not stopped,Stopped" bitfld.long 0x00 16. " CSOT ,Counter start on trigger" "Not started,Started" newline bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled" bitfld.long 0x00 8. " GTBSYNC ,Global time base synchronization" "Disabled,Enabled" bitfld.long 0x00 6.--7. " DBGMODE ,Debug mode" "LPTPM paused,,,LPTPM enabled" newline bitfld.long 0x00 5. " DOZEEN ,Doze enable" "Disabled,Enabled" endif else group.long 0x84++0x03 line.long 0x00 "TPM2_CONF,Configuration" sif cpuis("MKL02*") bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "EXTRG_IN,CMP0 output,,,,,,,TPM0 overflow,TMP1 overflow,,,,,LPTMR trigger,?..." newline elif cpuis("MKL03Z*") bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "EXTRG_IN,CMP0 output,,,,,,,TPM0 overflow,TPM1 overflow,,,RTC alarm,RTC seconds,LPTMR trigger,?..." newline elif cpuis("MKL04*")||cpuis("MKL05*") bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "EXTRG_IN,CMP0 output,,,PIT trigger 0,PIT trigger 1,,,TPM0 overflow,TPM1 overflow,,,RTC alarm,RTC seconds,LPTMR trigger,?..." newline else bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "EXTRG_IN,CMP0 output,,,PIT trigger 0,PIT trigger 1,,,TPM0 overflow,TPM1 overflow,TPM2 overflow,,RTC alarm,RTC seconds,LPTMR trigger,?..." newline endif bitfld.long 0x00 18. " CROT ,Counter reload on trigger" "Not reloaded,Reloaded" bitfld.long 0x00 17. " CSOO ,Counter stop on overflow" "Not stopped,Stopped" newline bitfld.long 0x00 16. " CSOT ,Counter start on trigger" "Not started,Started" bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled" newline bitfld.long 0x00 6.--7. " DBGMODE ,Debug mode" "LPTPM paused,,,LPTPM enabled" bitfld.long 0x00 5. " DOZEEN ,Doze enable" "Disabled,Enabled" endif width 0x0B tree.end tree.end tree.open "LPTMR (Low-Power Timer)" tree "LPTMR_0" base ad:0x40040000 width 5. sif cpuis("MK11D*")||cpuis("MK63*")||cpuis("MK64*")||cpuis("MK02*")||cpuis("MK65*")||cpuis("MK66*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20DX256VLK10R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK20DX256VLQ10R")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK21FX512VMD10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FX512VMC10")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MK10DN512ZVLK10*")||cpuis("MK10DN512ZVLL10*")||cpuis("MK10DN512ZVMC10")||cpuis("MK10DN512ZVLQ10")||cpuis("MK10DN512ZVMD10")||cpuis("MK10DX256ZVLQ10*")||cpuis("MK10DX256ZVMD10")||cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*")||cpuis("MK30DX256VLL7*")||cpuis("MK70*")||cpuis("MK40D*Z*10")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZCAB10R")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK27FN2M0VMI15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN128VLH10R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK20DN512VLK10R")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10")||cpuis("MK20DX256ZVLQ10R")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") if (((per.l(ad:0x40040000+0x00))&0x01)==0x01) group.long 0x00++0x03 line.long 0x00 "CSR,Low Power Timer Control Status Register" eventfld.long 0x00 7. " TCF ,Timer compare flag" "Not equaled,Equaled" bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled" newline sif cpuis("MK20DX256VLK10R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK20DX256VLQ10R")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK21FX512VMD10")||cpuis("MK21FN1M0VMD10")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLH12")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||(cpuis("MK40DN512ZVLQ10"))||(cpuis("MK40DN512ZVMD10"))||(cpuis("MK40DX128ZVLQ10"))||(cpuis("MK40DX256ZVLQ10"))||(cpuis("MK40DX256ZVMD10"))||(cpuis("MK40DN512ZVLL10"))||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN128VLH10R")||cpuis("MK20DN512VLK10R")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10")||cpuis("MK20DX256ZVLQ10R")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R") rbitfld.long 0x00 4.--5. " TPS ,Timer pin select" "CMP 0 output,LPTMR_ALT1 pin,LPTMR_ALT2 pin,?..." else rbitfld.long 0x00 4.--5. " TPS ,Timer pin select" "CMP 0 output,LPTMR_ALT1 pin,LPTMR_ALT2 pin,LPTMR_ALT3 pin" endif newline rbitfld.long 0x00 3. " TPP ,Timer pin polarity" "Active high,Active low" rbitfld.long 0x00 2. " TFC ,Timer free running counter" "Reset on TCF set,Reset on overflow" rbitfld.long 0x00 1. " TMS ,Timer mode select" "Time counter,Pulse counter" newline bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "CSR,Low Power Timer Control Status Register" eventfld.long 0x00 7. " TCF ,Timer compare flag" "Not equaled,Equaled" bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled" newline sif cpuis("MK20DX256VLK10R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK20DX256VLQ10R")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK21FX512VMD10")||cpuis("MK21FN1M0VMD10")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLH12")||(cpuis("MK40DN512ZVLQ10"))||(cpuis("MK40DN512ZVMD10"))||(cpuis("MK40DX128ZVLQ10"))||(cpuis("MK40DX256ZVLQ10"))||(cpuis("MK40DX256ZVMD10"))||(cpuis("MK40DN512ZVLL10"))||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN128VLH10R")||cpuis("MK20DN512VLK10R")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10")||cpuis("MK20DX256ZVLQ10R")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 4.--5. " TPS ,Timer pin select" "CMP 0 output,LPTMR_ALT1 pin,LPTMR_ALT2 pin,?..." elif cpuis("MK8?FN256V*")||cpuis("MK40D*Z*10")||cpuis("MK21FX512VMC10")||cpuis("MK21FN1M0VMC10")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 4.--5. " TPS ,Timer pin select" "CMP 0 output,LPTMR_ALT1 pin,LPTMR_ALT2 pin,LPTMR_ALT3 pin" else rbitfld.long 0x00 4.--5. " TPS ,Timer pin select" "CMP 0 output,LPTMR_ALT1 pin,LPTMR_ALT2 pin,LPTMR_ALT3 pin" endif newline bitfld.long 0x00 3. " TPP ,Timer pin polarity" "Active high,Active low" bitfld.long 0x00 2. " TFC ,Timer free running counter" "Reset on TCF set,Reset on overflow" bitfld.long 0x00 1. " TMS ,Timer mode select" "Time counter,Pulse counter" newline bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled" endif else group.long 0x00++0x03 line.long 0x00 "CSR,Low Power Timer Control Status Register" eventfld.long 0x00 7. " TCF ,Timer compare flag" "Not equaled,Equaled" bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " TPS ,Timer pin select" "Input 0,Input 1,Input 2,Input 3" newline bitfld.long 0x00 3. " TPP ,Timer pin polarity" "Active high,Active low" bitfld.long 0x00 2. " TFC ,Timer free running counter" "Reset on TCF set,Reset on overflow" bitfld.long 0x00 1. " TMS ,Timer mode select" "Time counter,Pulse counter" newline bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled" endif if ((per.l(ad:0x40040000)&0x02)==0x00) if (((per.l(ad:0x40040000+0x00))&0x01)==0x01) rgroup.long 0x04++0x03 line.long 0x00 "PSR,Low Power Timer Prescale Register" bitfld.long 0x00 3.--6. " PRESCALE ,Prescale value" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 2. " PBYP ,Prescaler bypass" "Not bypassed,Bypassed" bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "MCGIRCLK,LPO 1kHz,ERCLK32K,OSCERCLK" else group.long 0x04++0x03 line.long 0x00 "PSR,Low Power Timer Prescale Register" bitfld.long 0x00 3.--6. " PRESCALE ,Prescale value" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 2. " PBYP ,Prescaler bypass" "Not bypassed,Bypassed" bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "MCGIRCLK,LPO 1kHz,ERCLK32K,OSCERCLK" endif else if (((per.l(ad:0x40040000+0x00))&0x01)==0x01) rgroup.long 0x04++0x03 line.long 0x00 "PSR,Low Power Timer Prescale Register" bitfld.long 0x00 3.--6. " GFW ,Glitch filter width" ",2 clk edges,4 clk edges,8 clk edges,16 clk edges,32 clk edges,64 clk edges,128 clk edges,256 clk edges,512 clk edges,1024 clk edges,2048 clk edges,4096 clk edges,8192 clk edges,16384 clk edges,32768 clk edges" bitfld.long 0x00 2. " PBYP ,Glitch filter bypass" "Not bypassed,Bypassed" bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "MCGIRCLK,LPO 1kHz,ERCLK32K,OSCERCLK" else group.long 0x04++0x03 line.long 0x00 "PSR,Low Power Timer Prescale Register" bitfld.long 0x00 3.--6. " GFW ,Glitch filter width" ",2 clk edges,4 clk edges,8 clk edges,16 clk edges,32 clk edges,64 clk edges,128 clk edges,256 clk edges,512 clk edges,1024 clk edges,2048 clk edges,4096 clk edges,8192 clk edges,16384 clk edges,32768 clk edges" bitfld.long 0x00 2. " PBYP ,Glitch filter bypass" "Not bypassed,Bypassed" bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "MCGIRCLK,LPO 1kHz,ERCLK32K,OSCERCLK" endif endif sif cpuis("MK84FN2M0CAU15R") if (((per.l(ad:0x40040000+0x00))&0x81)==0x80) rgroup.long 0x08++0x03 line.long 0x00 "CMR,Low Power Timer Compare Register" else group.long 0x08++0x03 line.long 0x00 "CMR,Low Power Timer Compare Register" endif rgroup.long 0x0C++0x03 line.long 0x00 "CNR,Low Power Timer Counter Register" elif cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK27FN2M0VMI15") if (((per.l(ad:0x40040000+0x00))&0x81)==0x80) rgroup.long 0x08++0x03 line.long 0x00 "CMR,Low Power Timer Compare Register" else group.long 0x08++0x03 line.long 0x00 "CMR,Low Power Timer Compare Register" endif group.long 0x0C++0x03 line.long 0x00 "CNR,Low Power Timer Counter Register" elif cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22FN128VLH10R")||cpuis("MK22FX512AVLH12R")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R")||cpuis("KK60FN1M0VLQ15") if (((per.l(ad:0x40040000+0x00))&0x81)==0x80) rgroup.long 0x08++0x03 line.long 0x00 "CMR,Low Power Timer Compare Register" hexmask.long.word 0x00 0.--15. 1. " COMPARE ,Compare value" else group.long 0x08++0x03 line.long 0x00 "CMR,Low Power Timer Compare Register" hexmask.long.word 0x00 0.--15. 1. " COMPARE ,Compare value" endif group.long 0x0C++0x03 line.long 0x00 "CNR,Low Power Timer Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Counter value" else if (((per.l(ad:0x40040000+0x00))&0x81)==0x80) rgroup.long 0x08++0x03 line.long 0x00 "CMR,Low Power Timer Compare Register" hexmask.long.word 0x00 0.--15. 1. " COMPARE ,Compare value" else group.long 0x08++0x03 line.long 0x00 "CMR,Low Power Timer Compare Register" hexmask.long.word 0x00 0.--15. 1. " COMPARE ,Compare value" endif rgroup.long 0x0C++0x03 line.long 0x00 "CNR,Low Power Timer Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Counter value" endif width 0x0B tree.end tree "LPTMR_1" base ad:0x40044000 width 5. sif cpuis("MK11D*")||cpuis("MK63*")||cpuis("MK64*")||cpuis("MK02*")||cpuis("MK65*")||cpuis("MK66*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20DX256VLK10R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK20DX256VLQ10R")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK21FX512VMD10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FX512VMC10")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MK10DN512ZVLK10*")||cpuis("MK10DN512ZVLL10*")||cpuis("MK10DN512ZVMC10")||cpuis("MK10DN512ZVLQ10")||cpuis("MK10DN512ZVMD10")||cpuis("MK10DX256ZVLQ10*")||cpuis("MK10DX256ZVMD10")||cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*")||cpuis("MK30DX256VLL7*")||cpuis("MK70*")||cpuis("MK40D*Z*10")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZCAB10R")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK27FN2M0VMI15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN128VLH10R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK20DN512VLK10R")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10")||cpuis("MK20DX256ZVLQ10R")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") if (((per.l(ad:0x40044000+0x00))&0x01)==0x01) group.long 0x00++0x03 line.long 0x00 "CSR,Low Power Timer Control Status Register" eventfld.long 0x00 7. " TCF ,Timer compare flag" "Not equaled,Equaled" bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled" newline sif cpuis("MK20DX256VLK10R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK20DX256VLQ10R")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK21FX512VMD10")||cpuis("MK21FN1M0VMD10")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLH12")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||(cpuis("MK40DN512ZVLQ10"))||(cpuis("MK40DN512ZVMD10"))||(cpuis("MK40DX128ZVLQ10"))||(cpuis("MK40DX256ZVLQ10"))||(cpuis("MK40DX256ZVMD10"))||(cpuis("MK40DN512ZVLL10"))||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN128VLH10R")||cpuis("MK20DN512VLK10R")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10")||cpuis("MK20DX256ZVLQ10R")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R") rbitfld.long 0x00 4.--5. " TPS ,Timer pin select" "CMP 0 output,LPTMR_ALT1 pin,LPTMR_ALT2 pin,?..." else rbitfld.long 0x00 4.--5. " TPS ,Timer pin select" "CMP 0 output,LPTMR_ALT1 pin,LPTMR_ALT2 pin,LPTMR_ALT3 pin" endif newline rbitfld.long 0x00 3. " TPP ,Timer pin polarity" "Active high,Active low" rbitfld.long 0x00 2. " TFC ,Timer free running counter" "Reset on TCF set,Reset on overflow" rbitfld.long 0x00 1. " TMS ,Timer mode select" "Time counter,Pulse counter" newline bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "CSR,Low Power Timer Control Status Register" eventfld.long 0x00 7. " TCF ,Timer compare flag" "Not equaled,Equaled" bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled" newline sif cpuis("MK20DX256VLK10R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK20DX256VLQ10R")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK21FX512VMD10")||cpuis("MK21FN1M0VMD10")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLH12")||(cpuis("MK40DN512ZVLQ10"))||(cpuis("MK40DN512ZVMD10"))||(cpuis("MK40DX128ZVLQ10"))||(cpuis("MK40DX256ZVLQ10"))||(cpuis("MK40DX256ZVMD10"))||(cpuis("MK40DN512ZVLL10"))||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN128VLH10R")||cpuis("MK20DN512VLK10R")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10")||cpuis("MK20DX256ZVLQ10R")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 4.--5. " TPS ,Timer pin select" "CMP 0 output,LPTMR_ALT1 pin,LPTMR_ALT2 pin,?..." elif cpuis("MK8?FN256V*")||cpuis("MK40D*Z*10")||cpuis("MK21FX512VMC10")||cpuis("MK21FN1M0VMC10")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 4.--5. " TPS ,Timer pin select" "CMP 0 output,LPTMR_ALT1 pin,LPTMR_ALT2 pin,LPTMR_ALT3 pin" else rbitfld.long 0x00 4.--5. " TPS ,Timer pin select" "CMP 0 output,LPTMR_ALT1 pin,LPTMR_ALT2 pin,LPTMR_ALT3 pin" endif newline bitfld.long 0x00 3. " TPP ,Timer pin polarity" "Active high,Active low" bitfld.long 0x00 2. " TFC ,Timer free running counter" "Reset on TCF set,Reset on overflow" bitfld.long 0x00 1. " TMS ,Timer mode select" "Time counter,Pulse counter" newline bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled" endif else group.long 0x00++0x03 line.long 0x00 "CSR,Low Power Timer Control Status Register" eventfld.long 0x00 7. " TCF ,Timer compare flag" "Not equaled,Equaled" bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " TPS ,Timer pin select" "Input 0,Input 1,Input 2,Input 3" newline bitfld.long 0x00 3. " TPP ,Timer pin polarity" "Active high,Active low" bitfld.long 0x00 2. " TFC ,Timer free running counter" "Reset on TCF set,Reset on overflow" bitfld.long 0x00 1. " TMS ,Timer mode select" "Time counter,Pulse counter" newline bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled" endif if ((per.l(ad:0x40044000)&0x02)==0x00) if (((per.l(ad:0x40044000+0x00))&0x01)==0x01) rgroup.long 0x04++0x03 line.long 0x00 "PSR,Low Power Timer Prescale Register" bitfld.long 0x00 3.--6. " PRESCALE ,Prescale value" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 2. " PBYP ,Prescaler bypass" "Not bypassed,Bypassed" bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "MCGIRCLK,LPO 1kHz,ERCLK32K,OSCERCLK" else group.long 0x04++0x03 line.long 0x00 "PSR,Low Power Timer Prescale Register" bitfld.long 0x00 3.--6. " PRESCALE ,Prescale value" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 2. " PBYP ,Prescaler bypass" "Not bypassed,Bypassed" bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "MCGIRCLK,LPO 1kHz,ERCLK32K,OSCERCLK" endif else if (((per.l(ad:0x40044000+0x00))&0x01)==0x01) rgroup.long 0x04++0x03 line.long 0x00 "PSR,Low Power Timer Prescale Register" bitfld.long 0x00 3.--6. " GFW ,Glitch filter width" ",2 clk edges,4 clk edges,8 clk edges,16 clk edges,32 clk edges,64 clk edges,128 clk edges,256 clk edges,512 clk edges,1024 clk edges,2048 clk edges,4096 clk edges,8192 clk edges,16384 clk edges,32768 clk edges" bitfld.long 0x00 2. " PBYP ,Glitch filter bypass" "Not bypassed,Bypassed" bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "MCGIRCLK,LPO 1kHz,ERCLK32K,OSCERCLK" else group.long 0x04++0x03 line.long 0x00 "PSR,Low Power Timer Prescale Register" bitfld.long 0x00 3.--6. " GFW ,Glitch filter width" ",2 clk edges,4 clk edges,8 clk edges,16 clk edges,32 clk edges,64 clk edges,128 clk edges,256 clk edges,512 clk edges,1024 clk edges,2048 clk edges,4096 clk edges,8192 clk edges,16384 clk edges,32768 clk edges" bitfld.long 0x00 2. " PBYP ,Glitch filter bypass" "Not bypassed,Bypassed" bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "MCGIRCLK,LPO 1kHz,ERCLK32K,OSCERCLK" endif endif sif cpuis("MK84FN2M0CAU15R") if (((per.l(ad:0x40044000+0x00))&0x81)==0x80) rgroup.long 0x08++0x03 line.long 0x00 "CMR,Low Power Timer Compare Register" else group.long 0x08++0x03 line.long 0x00 "CMR,Low Power Timer Compare Register" endif rgroup.long 0x0C++0x03 line.long 0x00 "CNR,Low Power Timer Counter Register" elif cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK27FN2M0VMI15") if (((per.l(ad:0x40044000+0x00))&0x81)==0x80) rgroup.long 0x08++0x03 line.long 0x00 "CMR,Low Power Timer Compare Register" else group.long 0x08++0x03 line.long 0x00 "CMR,Low Power Timer Compare Register" endif group.long 0x0C++0x03 line.long 0x00 "CNR,Low Power Timer Counter Register" elif cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22FN128VLH10R")||cpuis("MK22FX512AVLH12R")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R")||cpuis("KK60FN1M0VLQ15") if (((per.l(ad:0x40044000+0x00))&0x81)==0x80) rgroup.long 0x08++0x03 line.long 0x00 "CMR,Low Power Timer Compare Register" hexmask.long.word 0x00 0.--15. 1. " COMPARE ,Compare value" else group.long 0x08++0x03 line.long 0x00 "CMR,Low Power Timer Compare Register" hexmask.long.word 0x00 0.--15. 1. " COMPARE ,Compare value" endif group.long 0x0C++0x03 line.long 0x00 "CNR,Low Power Timer Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Counter value" else if (((per.l(ad:0x40044000+0x00))&0x81)==0x80) rgroup.long 0x08++0x03 line.long 0x00 "CMR,Low Power Timer Compare Register" hexmask.long.word 0x00 0.--15. 1. " COMPARE ,Compare value" else group.long 0x08++0x03 line.long 0x00 "CMR,Low Power Timer Compare Register" hexmask.long.word 0x00 0.--15. 1. " COMPARE ,Compare value" endif rgroup.long 0x0C++0x03 line.long 0x00 "CNR,Low Power Timer Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Counter value" endif width 0x0B tree.end tree.end tree "CMT (Carrier Modulator Transmitter)" base ad:0x40062000 width 6. group.byte 0x00++0x04 line.byte 0x00 "CGH1,CMT Carrier Generator High Data Register 1" line.byte 0x01 "CGL1,CMT Carrier Generator Low Data Register 1" line.byte 0x02 "CGH2,CMT Carrier Generator High Data Register 2" line.byte 0x03 "CGL2,CMT Carrier Generator Low Data Register 2" line.byte 0x04 "OC,CMT Output Control Register" bitfld.byte 0x04 7. " IROL ,IRO latch control" "Low,High" bitfld.byte 0x04 6. " CMTPOL ,CMT output polarity" "Active low,Active high" bitfld.byte 0x04 5. " IROPEN ,IRO pin enable" "Disabled,Enabled" hgroup.byte 0x05++0x00 hide.byte 0x00 "MSC,CMT Modulator Status and Control Register" in group.byte 0x06++0x05 line.byte 0x00 "CMD1,CMT Modulator Data Register Mark High" line.byte 0x01 "CMD2,CMT Modulator Data Register Mark Low" line.byte 0x02 "CMD3,CMT Modulator Data Register Space High" line.byte 0x03 "CMD4,CMT Modulator Data Register Space Low" line.byte 0x04 "PPS,CMT Primary Prescaler Register" bitfld.byte 0x04 0.--3. " PPSDIV ,Primary prescaler divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" line.byte 0x05 "DMA,CMT Direct Memory Access Register" bitfld.byte 0x05 0. " DMA ,DMA enable" "Disabled,Enabled" width 0x0B tree.end tree "PDB (Programmable Delay Block)" base ad:0x40036000 width 6. group.long 0x00++0x07 line.long 0x00 "SC,Status and Control Register" bitfld.long 0x00 18.--19. " LDMOD ,Load mode select" "Immediately after 1 to LDOK,PDB reach MOD,Trigger input detected,Trigger input detected/PDB reach MOD" newline bitfld.long 0x00 17. " PDBEIE ,PDB sequence error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 16. " SWTRIG ,Software trigger" "Not triggered,Triggered" bitfld.long 0x00 15. " DMAEN ,DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 12.--14. " PRESCALER ,Prescaler divider select (of multiplication factor)" "MULT,MULT*2,MULT*4,MULT*8,MULT*16,MULT*32,MULT*64,MULT*128" newline sif cpuis("MK20DN512*AB10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLQ10*")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,CMP 2,PIT Ch 0 output,PIT Ch 1 output,PIT Ch 2 output,PIT Ch 3 output,FTM0,FTM1,FTM2,,RTC alarm,RTC seconds,LPTMR output,Software trigger" elif cpuis("MK21D*AVLK5")||cpuis("MK21D*AVMC5")||cpuis("MK22FN256*")||cpuis("MK22FN128*")||cpuis("MK22FN256VLL12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,,PIT Ch 0 output,PIT Ch 1 output,PIT Ch 2 output,PIT Ch 3 output,FTM0,FTM1,FTM2,,RTC alarm,RTC seconds,LPTMR output,Software trigger" elif cpuis("KK26FN2M0CAC18R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,CMP 2,PIT Ch 0 output,PIT Ch 1 output,PIT Ch 2 output,PIT Ch 3 output,FTM0,FTM1,FTM2,FTM3,RTC alarm,RTC seconds,LPTMR output,Software trigger" elif (cpuis("MK21F*AVLQ12")||cpuis("MK21F*AVMD12"))||cpuis("MK21F*AVMC12")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12*")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK28FN2M0CAU15R")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK27FN2M0VMI15") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,,PIT Ch 0 output,PIT Ch 1 output,PIT Ch 2 output,PIT Ch 3 output,FTM0,FTM1,FTM2,FTM3,RTC alarm,RTC seconds,LPTMR output,Software trigger" elif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,CMP 2,PIT0 Ch 0 output,PIT0 Ch 1 output,PIT1 Ch 0 output,PIT1 Ch 1 output,,,,LPTMR output,RTC alarm,RTC clock out,XBAR out 39,Software trigger" elif cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,,,PIT Ch 0 output,PIT Ch 1 output,PIT Ch 2 output,PIT Ch 3 output,TPM0 overflow,TPM1 overflow,TPM2 overflow,,RTC alarm,RTC seconds,LPTMR output,Software trigger" else bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "Trigger-In 0,Trigger-In 1,Trigger-In 2,Trigger-In 3,Trigger-In 4,Trigger-In 5,Trigger-In 6,Trigger-In 7,Trigger-In 8,Trigger-In 9,Trigger-In 10,Trigger-In 11,Trigger-In 12,Trigger-In 13,Trigger-In 14,Software trigger" endif newline bitfld.long 0x00 7. " PDBEN ,PDB enable" "Disabled,Enabled" bitfld.long 0x00 6. " PDBIF ,PDB interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 5. " PDBIE ,PDB interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " MULT ,Multiplication factor select for prescaler" "1,10,20,40" bitfld.long 0x00 1. " CONT ,Continuous mode enable" "One-Shot,Continuous" bitfld.long 0x00 0. " LDOK ,Load OK" "Not updated,Updated" line.long 0x04 "MOD,Modulus Register" hexmask.long.word 0x04 0.--15. 1. " MOD ,PDB modulus" rgroup.long 0x08++0x03 line.long 0x00 "CNT,Counter Register" hexmask.long.word 0x00 0.--15. 1. " CNT ,PDB counter" group.long 0x0C++0x03 line.long 0x00 "IDLY,Interrupt Delay Register" hexmask.long.word 0x00 0.--15. 1. " IDLY ,PDB interrupt delay" newline width 10. tree "Channel 0" group.long 0x10++0x0F line.long 0x00 "CH0_C1,Channel 0 Control Register 1" sif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.long 0x00 19. " BB[3] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 18. " BB[2] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 17. " BB[1] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 16. " BB[0] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " TOS[3] ,PDB channel pre-trigger output select" "Not selected,Selected" bitfld.long 0x00 10. " TOS[2] ,PDB channel pre-trigger output select" "Not selected,Selected" bitfld.long 0x00 9. " TOS[1] ,PDB channel pre-trigger output select" "Not selected,Selected" bitfld.long 0x00 8. " TOS[0] ,PDB channel pre-trigger output select" "Not selected,Selected" newline bitfld.long 0x00 3. " EN[3] ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " EN[2] ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " EN[1] ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN[0] ,PDB channel pre-trigger enable" "Disabled,Enabled" elif cpuis("MKS2?FN???V??12")||cpuis("KK22FN???C?P12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VFX12*")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN???CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN128VLH10R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("?K28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.long 0x00 23. " BB[7] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 22. " BB[6] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 21. " BB[5] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 20. " BB[4] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BB[3] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 18. " BB[2] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 17. " BB[1] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 16. " BB[0] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" newline bitfld.long 0x00 15. " TOS[7] ,PDB channel pre-trigger output select" "Not selected,Selected" bitfld.long 0x00 14. " TOS[6] ,PDB channel pre-trigger output select" "Not selected,Selected" bitfld.long 0x00 13. " TOS[5] ,PDB channel pre-trigger output select" "Not selected,Selected" bitfld.long 0x00 12. " TOS[4] ,PDB channel pre-trigger output select" "Not selected,Selected" newline bitfld.long 0x00 11. " TOS[3] ,PDB channel pre-trigger output select" "Not selected,Selected" bitfld.long 0x00 10. " TOS[2] ,PDB channel pre-trigger output select" "Not selected,Selected" bitfld.long 0x00 9. " TOS[1] ,PDB channel pre-trigger output select" "Not selected,Selected" bitfld.long 0x00 8. " TOS[0] ,PDB channel pre-trigger output select" "Not selected,Selected" newline bitfld.long 0x00 7. " EN[7] ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 6. " EN[6] ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " EN[5] ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 4. " EN[4] ,PDB channel pre-trigger enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " EN[3] ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " EN[2] ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " EN[1] ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN[0] ,PDB channel pre-trigger enable" "Disabled,Enabled" else bitfld.long 0x00 17. " BB[1] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 16. " BB[0] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 9. " TOS[1] ,PDB channel pre-trigger output select" "Not selected,Selected" bitfld.long 0x00 8. " TOS[0] ,PDB channel pre-trigger output select" "Not selected,Selected" newline bitfld.long 0x00 1. " EN[1] ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN[0] ,PDB channel pre-trigger enable" "Disabled,Enabled" endif line.long 0x04 "CH0_S,Channel 0 Status Register" sif cpuis("MKS2?FN???V??12")||cpuis("KK22FN???C?P12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VFX12*")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN???CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN128VLH10R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("?K28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.long 0x04 23. " CF[7] ,PDB channel flag" "Not occurred,Occurred" bitfld.long 0x04 22. " CF[6] ,PDB channel flag" "Not occurred,Occurred" bitfld.long 0x04 21. " CF[5] ,PDB channel flag" "Not occurred,Occurred" bitfld.long 0x04 20. " CF[4] ,PDB channel flag" "Not occurred,Occurred" newline endif bitfld.long 0x04 19. " CF[3] ,PDB channel flag" "Not occurred,Occurred" bitfld.long 0x04 18. " CF[2] ,PDB channel flag" "Not occurred,Occurred" bitfld.long 0x04 17. " CF[1] ,PDB channel flag" "Not occurred,Occurred" bitfld.long 0x04 16. " CF[0] ,PDB channel flag" "Not occurred,Occurred" newline sif cpuis("MKS2?FN???V??12")||cpuis("KK22FN???C?P12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VFX12*")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN???CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN128VLH10R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("?K28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.long 0x04 7. " ERR[7] ,PDB channel sequence error flag" "No error,Error" bitfld.long 0x04 6. " ERR[6] ,PDB channel sequence error flag" "No error,Error" bitfld.long 0x04 5. " ERR[5] ,PDB channel sequence error flag" "No error,Error" bitfld.long 0x04 4. " ERR[4] ,PDB channel sequence error flag" "No error,Error" newline endif bitfld.long 0x04 3. " ERR[3] ,PDB channel sequence error flag" "No error,Error" bitfld.long 0x04 2. " ERR[2] ,PDB channel sequence error flag" "No error,Error" bitfld.long 0x04 1. " ERR[1] ,PDB channel sequence error flag" "No error,Error" bitfld.long 0x04 0. " ERR[0] ,PDB channel sequence error flag" "No error,Error" line.long 0x08 "CH0_DLY0,Channel 0 Delay 0 Register" hexmask.long.word 0x08 0.--15. 1. " DLY ,PDB channel delay" line.long 0x0C "CH0_DLY1,Channel 0 Delay 1 Register" hexmask.long.word 0x0C 0.--15. 1. " DLY ,PDB channel delay" sif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") group.long (0x10+0x20)++0x07 line.long 0x00 "CH0_DLY2,Channel 0 Delay 2 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" line.long 0x04 "CH0_DLY3,Channel 0 Delay 3 Register" hexmask.long.word 0x04 0.--15. 1. " DLY ,PDB channel delay" endif tree.end newline sif !cpuis("MKM34Z256VLL7*")&&!cpuis("MKM34Z256VLQ7") group.long 0x150++0x07 line.long 0x00 "DACINTC0,DAC Interval Trigger 0 Control Register" bitfld.long 0x00 1. " EXT ,DAC external trigger input enable" "Disabled,Enabled" bitfld.long 0x00 0. " TOE ,DAC interval trigger enable" "Disabled,Enabled" line.long 0x04 "DACINT0,DAC Interval 0 Register" hexmask.long.word 0x04 0.--15. 1. " INT ,DAC interval" endif group.long 0x190++0x03 line.long 0x00 "POEN,Pulse-Out 0 Enable Register" bitfld.long 0x00 1. " POEN[1] ,PDB pulse out enable" "Disabled,Enabled" bitfld.long 0x00 0. " POEN[0] ,PDB pulse out enable" "Disabled,Enabled" sif cpuis("KK22FN???C?P12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VFX12*")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN???CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R") group.long 0x194++0x03 line.long 0x00 "PO0DLY,Pulse-Out 0 Delay Register" hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB pulse-out delay 1" hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB pulse-out delay 2" elif cpuis("MK27FN2M0VMI15")||cpuis("?K28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") group.long 0x194++0x03 line.long 0x00 "PO0DLY,Pulse-Out 0 Delay Register" hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB pulse-out delay 1" hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB pulse-out delay 2" group.long 0x198++0x03 line.long 0x00 "PO1DLY,Pulse-Out 1 Delay Register" hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB pulse-out delay 1" hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB pulse-out delay 2" elif cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R") group.long 0x194++0x03 line.long 0x00 "PO0DLY,Pulse-Out 0 Delay Register" hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB pulse-out delay 1" hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB pulse-out delay 2" group.long 0x198++0x03 line.long 0x00 "PO1DLY,Pulse-Out 1 Delay Register" hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB pulse-out delay 1" hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB pulse-out delay 2" group.long 0x19C++0x03 line.long 0x00 "PO2DLY,Pulse-Out 2 Delay Register" hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB pulse-out delay 1" hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB pulse-out delay 2" elif cpuis("KK26FN2M0CAC18R") group.long 0x194++0x03 line.long 0x00 "PO0DLY,Pulse-Out 0 Delay Register" hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB pulse-out delay 1" hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB pulse-out delay 2" group.long 0x198++0x03 line.long 0x00 "PO1DLY,Pulse-Out 1 Delay Register" hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB pulse-out delay 1" hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB pulse-out delay 2" group.long 0x19C++0x03 line.long 0x00 "PO2DLY,Pulse-Out 2 Delay Register" hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB pulse-out delay 1" hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB pulse-out delay 2" group.long 0x1A0++0x03 line.long 0x00 "PO3DLY,Pulse-Out 3 Delay Register" hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB pulse-out delay 1" hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB pulse-out delay 2" else group.long 0x194++0x03 line.long 0x00 "PO0DLY,Pulse-Out 0 Delay Register" hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB pulse-out delay 1" hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB pulse-out delay 2" group.long 0x198++0x03 line.long 0x00 "PO1DLY,Pulse-Out 1 Delay Register" hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB pulse-out delay 1" hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB pulse-out delay 2" endif width 0x0B tree.end tree "PIT (Periodic Interrupt Timer)" base ad:0x40037000 sif cpuis("MK65*F*")||cpuis("MK66*F*")||cpuis("MK26FN*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK65FN2M0CAC18R") width 9. group.long 0x00++0x03 line.long 0x00 "MCR,PIT Module Control Register" bitfld.long 0x00 1. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 0. " FRZ ,Freeze in debug mode" "Not stopped,Stopped" sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") rgroup.long 0xE0++0x07 line.long 0x00 "LTMR64H,PIT Upper Lifetime Timer Register" line.long 0x04 "LTMR64L,PIT Lower Lifetime Timer Register" else group.long 0xE0++0x07 line.long 0x00 "LTMR64H,PIT Upper Lifetime Timer Register" line.long 0x04 "LTMR64L,PIT Lower Lifetime Timer Register" endif else width 8. group.long 0x00++0x03 line.long 0x00 "MCR,PIT Module Control Register" bitfld.long 0x00 1. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 0. " FRZ ,Freeze in debug mode" "Not stopped,Stopped" endif width 9. group.long 0x100++0x03 "PIT 0 Registers" line.long 0x00 "LDVAL0,PIT0 Timer Load Value Register" rgroup.long (0x100+0x4)++0x03 line.long 0x00 "CVAL0,PIT0 Current Timer Value Register" group.long (0x100+0x08)++0x03 line.long 0x00 "TCTRL0,PIT0 Timer Control Register" sif !cpuis("MK?0F*")&&!cpuis("MK?0D*5")&&!cpuis("MK?0DN*AB10")&&!cpuis("MK20DN512*AB10R")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVLQ10R")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R") sif cpuis("MK20FN1M0VLQ12R")||cpuis("MK02*")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MK20DX256VLQ10R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK21FX512VMD10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FX512VMC10")||cpuis("MK8?FN256V*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK30DX256VLL7*")||cpuis("MK70*")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK60DN512VMC10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK27FN2M0VMI15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN128VLH10R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK20DN512VLK10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15") endif endif bitfld.long 0x00 1. " TIE ,Timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled" group.long (0x100+0x0C)++0x03 line.long 0x00 "TFLG0,PIT0 Timer Flag Register" eventfld.long 0x00 0. " TIF ,Timer interrupt flag" "Not occurred,Occurred" group.long 0x110++0x03 "PIT 1 Registers" line.long 0x00 "LDVAL1,PIT1 Timer Load Value Register" rgroup.long (0x110+0x4)++0x03 line.long 0x00 "CVAL1,PIT1 Current Timer Value Register" group.long (0x110+0x08)++0x03 line.long 0x00 "TCTRL1,PIT1 Timer Control Register" sif !cpuis("MK?0F*")&&!cpuis("MK?0D*5")&&!cpuis("MK?0DN*AB10")&&!cpuis("MK20DN512*AB10R")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVLQ10R")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R") sif cpuis("MK20FN1M0VLQ12R")||cpuis("MK02*")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MK20DX256VLQ10R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK21FX512VMD10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FX512VMC10")||cpuis("MK8?FN256V*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK30DX256VLL7*")||cpuis("MK70*")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK60DN512VMC10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK27FN2M0VMI15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN128VLH10R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK20DN512VLK10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 2. " CHN ,Chain mode" "Not chained,Chained" newline endif endif bitfld.long 0x00 1. " TIE ,Timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled" group.long (0x110+0x0C)++0x03 line.long 0x00 "TFLG1,PIT1 Timer Flag Register" eventfld.long 0x00 0. " TIF ,Timer interrupt flag" "Not occurred,Occurred" group.long 0x120++0x03 "PIT 2 Registers" line.long 0x00 "LDVAL2,PIT2 Timer Load Value Register" rgroup.long (0x120+0x4)++0x03 line.long 0x00 "CVAL2,PIT2 Current Timer Value Register" group.long (0x120+0x08)++0x03 line.long 0x00 "TCTRL2,PIT2 Timer Control Register" sif !cpuis("MK?0F*")&&!cpuis("MK?0D*5")&&!cpuis("MK?0DN*AB10")&&!cpuis("MK20DN512*AB10R")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVLQ10R")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R") sif cpuis("MK20FN1M0VLQ12R")||cpuis("MK02*")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MK20DX256VLQ10R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK21FX512VMD10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FX512VMC10")||cpuis("MK8?FN256V*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK30DX256VLL7*")||cpuis("MK70*")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK60DN512VMC10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK27FN2M0VMI15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN128VLH10R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK20DN512VLK10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 2. " CHN ,Chain mode" "Not chained,Chained" newline endif endif bitfld.long 0x00 1. " TIE ,Timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled" group.long (0x120+0x0C)++0x03 line.long 0x00 "TFLG2,PIT2 Timer Flag Register" eventfld.long 0x00 0. " TIF ,Timer interrupt flag" "Not occurred,Occurred" group.long 0x130++0x03 "PIT 3 Registers" line.long 0x00 "LDVAL3,PIT3 Timer Load Value Register" rgroup.long (0x130+0x4)++0x03 line.long 0x00 "CVAL3,PIT3 Current Timer Value Register" group.long (0x130+0x08)++0x03 line.long 0x00 "TCTRL3,PIT3 Timer Control Register" sif !cpuis("MK?0F*")&&!cpuis("MK?0D*5")&&!cpuis("MK?0DN*AB10")&&!cpuis("MK20DN512*AB10R")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVLQ10R")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R") sif cpuis("MK20FN1M0VLQ12R")||cpuis("MK02*")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MK20DX256VLQ10R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK21FX512VMD10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FX512VMC10")||cpuis("MK8?FN256V*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK30DX256VLL7*")||cpuis("MK70*")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK60DN512VMC10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK27FN2M0VMI15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN128VLH10R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK20DN512VLK10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 2. " CHN ,Chain mode" "Not chained,Chained" newline endif endif bitfld.long 0x00 1. " TIE ,Timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled" group.long (0x130+0x0C)++0x03 line.long 0x00 "TFLG3,PIT3 Timer Flag Register" eventfld.long 0x00 0. " TIF ,Timer interrupt flag" "Not occurred,Occurred" width 0x0B tree.end tree "RTC (Real Time Clock)" base ad:0x4003D000 width 5. if ((per.l(ad:0x4003D000+0x14)&0x10)==0x00) group.long 0x00++0x07 line.long 0x00 "TSR,RTC Time Seconds Register" line.long 0x04 "TPR,RTC Time Prescaler Register" hexmask.long.word 0x04 0.--15. 1. " TPR ,Time prescaler" else rgroup.long 0x00++0x07 line.long 0x00 "TSR,RTC Time Seconds Register" line.long 0x04 "TPR,RTC Time Prescaler Register" hexmask.long.word 0x04 0.--15. 1. " TPR ,Time prescaler" endif group.long 0x08++0x17 line.long 0x00 "TAR,RTC Time Alarm Register" line.long 0x04 "TCR,RTC Time Compensation Register" hexmask.long.byte 0x04 24.--31. 1. " CIC ,Compensation interval counter" hexmask.long.byte 0x04 16.--23. 1. " TCV ,Time compensation value" hexmask.long.byte 0x04 8.--15. 1. " CIR ,Compensation interval register" hexmask.long.byte 0x04 0.--7. 1. " TCR ,Time compensation register" line.long 0x08 "CR,RTC Control Register" bitfld.long 0x08 13. " SC2P ,Oscillator 2pF load configure" "Disabled,Enabled" bitfld.long 0x08 12. " SC4P ,Oscillator 4pF load configure" "Disabled,Enabled" bitfld.long 0x08 11. " SC8P ,Oscillator 8pF load configure" "Disabled,Enabled" bitfld.long 0x08 10. " SC16P ,Oscillator 16pF load configure" "Disabled,Enabled" newline bitfld.long 0x08 9. " CLKO ,Indicates whether clock is output to other peripherals or not" "Output,Not output" bitfld.long 0x08 8. " OSCE ,Oscillator enable" "Disabled,Enabled" newline sif cpuis("MK21F*")||cpuis("MK22F*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15") sif !cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN256CAH12R")&&!cpuis("MK22FN256VMP12")&&!cpuis("MK22FN512VLH12")&&!cpuis("MK22FN512VLL12")&&!cpuis("MK22FN512VMP12")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FX512AVLK12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK20DX64VMB7")&&!cpuis("MK20DX128VMB7")&&!cpuis("MK20DX256VMB7")&&!cpuis("MK20DN32VEX5")&&!cpuis("MK20DN64VEX5")&&!cpuis("MK20DN128VEX5")&&!cpuis("MK20DX32VEX5")&&!cpuis("MK20DX64VEX5")&&!cpuis("MK20DX128VEX5")&&!cpuis("MK20DX64VEX7")&&!cpuis("MK20DX128VEX7")&&!cpuis("MK20DX256VEX7")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN128VLH10R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK22FN512VLH12R")&&!cpuis("MK22FN512VFX12")&&!cpuis("MK22FN512VFX12R")&&!cpuis("MK22FN256VLL12R") bitfld.long 0x08 4. " WPS ,Wakeup pin select (wakeup pin asserts when RTC interrupt asserts / wakeup pin outputs the RTC 32kHz clock)" "Interrupt,RTC 32kHz clock" newline endif endif bitfld.long 0x08 3. " UM ,Update mode (registers can be written when locked under limited conditions)" "No,Yes" bitfld.long 0x08 2. " SUP ,Supervisor write access" "Supervisor,Non-supervisor" newline sif !cpuis("MK20DX256VLK10R")&&!cpuis("MK20DX256VLK7R")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN128CAH12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN256CAH12R")&&!cpuis("MK22FN256VMP12")&&!cpuis("MK22FN512VLH12")&&!cpuis("MK22FN512VLL12")&&!cpuis("MK22FN512VMP12")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FX512AVLK12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MKS20FN128VFT12")&&!cpuis("MKS20FN128VLH12")&&!cpuis("MKS20FN128VLL12")&&!cpuis("MKS20FN256VFT12")&&!cpuis("MKS20FN256VLH12")&&!cpuis("MKS20FN256VLL12")&&!cpuis("MKS22FN128VFT12")&&!cpuis("MKS22FN128VLH12")&&!cpuis("MKS22FN128VLL12")&&!cpuis("MKS22FN256VFT12")&&!cpuis("MKS22FN256VLH12")&&!cpuis("MKS22FN256VLL12")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FN256VLL12R")&&!cpuis("MK22FN512VFX12")&&!cpuis("MK22FN512VFX12R")&&!cpuis("MK22FN512VLH12R")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVLQ10R")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("MK22FN128VLH10R") bitfld.long 0x08 1. " WPE ,Wakeup pin enable" "Disabled,Enabled" newline endif bitfld.long 0x08 0. " SWR ,Software reset" "No effect,Reset" line.long 0x0C "SR,RTC Status Register" bitfld.long 0x0C 4. " TCE ,Time counter enable" "Disabled,Enabled" newline sif !cpuis("MK20D*")&&!cpuis("MK22FN128*")&&!cpuis("MK22FN128*")&&!cpuis("MK24FN*")&&!cpuis("MK84FN2M0CAU15R")&&!cpuis("MK8?FN256V*")&&!cpuis("MK22FN256CAH12R")&&!cpuis("MK22FN256CAP12R")&&!cpuis("MK22FN256VMP12")&&!cpuis("MK22FN512CAP12R")&&!cpuis("MK22FN512CBP12R")&&!cpuis("MK22FN512VDC12")&&!cpuis("MK22FN512VLH12")&&!cpuis("MK22FN512VLL12")&&!cpuis("MK22FN512VMP12")&&!cpuis("KK22FN256CAP12R")&&!cpuis("KK22FN512CBP12R")&&!cpuis("MK22FN512VDC12R")&&!cpuis("MK22FN512VFX12")&&!cpuis("MK22FN512VFX12R")&&!cpuis("MK22FN512VLH12R")&&!cpuis("KK22FN128CAH12R")&&!cpuis("KK22FN256CAH12R")&&!cpuis("KK22FN256CAH12R")&&!cpuis("MK22FN256VLL12R")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVLQ10R")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK22FN128VLH10R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("MKS20FN128VFT12")&&!cpuis("MKS20FN128VLH12")&&!cpuis("MKS20FN128VLL12")&&!cpuis("MKS20FN256VFT12")&&!cpuis("MKS20FN256VLH12")&&!cpuis("MKS20FN256VLL12")&&!cpuis("MKS22FN128VFT12")&&!cpuis("MKS22FN128VLH12")&&!cpuis("MKS22FN128VLL12")&&!cpuis("MKS22FN256VFT12")&&!cpuis("MKS22FN256VLH12")&&!cpuis("MKS22FN256VLL12") rbitfld.long 0x0C 3. " MOF ,Monotonic overflow flag" "No overflow,Overflow" rbitfld.long 0x0C 2. " TAF ,Time alarm flag" "Not occurred,Occurred" newline else rbitfld.long 0x0C 2. " TAF ,Time alarm flag" "Not occurred,Occurred" newline endif rbitfld.long 0x0C 1. " TOF ,Time overflow flag" "No overflow,Overflow" rbitfld.long 0x0C 0. " TIF ,Time invalid flag" "Valid,Invalid" line.long 0x10 "LR,RTC Lock Register" sif !cpuis("MK20FN1M0VLQ12R") sif cpuis("MK20F*") bitfld.long 0x10 15. " TIL ,Tamper interrupt lock" "Locked,Not locked" bitfld.long 0x10 14. " TTL ,Tamper trim lock" "Locked,Not locked" bitfld.long 0x10 13. " TDL ,Tamper detect lock" "Locked,Not locked" bitfld.long 0x10 12. " TEL ,Tamper enable lock" "Locked,Not locked" newline endif endif sif !cpuis("MK20D*")&&!cpuis("MK24FN256VDC12")&&!cpuis("MK24FN1M0CAJ12R")&&!cpuis("MK24FN1M0VDC12R")&&!cpuis("MK24FN1M0VLL12")&&!cpuis("MK24FN1M0VLL12R")&&!cpuis("MK24FN1M0VLQ12R")&&!cpuis("MK22FN128*")&&!cpuis("MK24FN*")&&!cpuis("MK84FN2M0CAU15R")&&!cpuis("MK8?FN256V*")&&!cpuis("MK22FN256CAH12R")&&!cpuis("MK22FN256CAP12R")&&!cpuis("MK22FN256VMP12")&&!cpuis("MK22FN512CAP12R")&&!cpuis("MK22FN512CBP12R")&&!cpuis("MK22FN512VDC12")&&!cpuis("MK22FN512VLH12")&&!cpuis("MK22FN512VLL12")&&!cpuis("MK22FN512VMP12") sif cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVLH12")||cpuis("KK26FN2M0CAC18R")||cpuis("MK21DX256AVMC5R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FX512AVLH12R") bitfld.long 0x10 11. " MCHL ,Monotonic counter high lock" "Locked,Not locked" bitfld.long 0x10 10. " MCLL ,Monotonic counter low lock" "Locked,Not locked" bitfld.long 0x10 9. " MEL ,Monotonic enable lock" "Locked,Not locked" bitfld.long 0x10 8. " TTSL ,Tamper time seconds lock" "Locked,Not locked" newline endif endif bitfld.long 0x10 6. " LRL ,Lock register lock" "Locked,Not locked" bitfld.long 0x10 5. " SRL ,Status register lock" "Locked,Not locked" bitfld.long 0x10 4. " CRL ,Control register lock" "Locked,Not locked" bitfld.long 0x10 3. " TCL ,Time compensation lock" "Locked,Not locked" line.long 0x14 "IER,RTC Interrupt Enable Register" sif !cpuis("MK20D*5")&&!cpuis("MK20D*7")&&!cpuis("MK20F*")&&!cpuis("MK20DX256VMC7R")&&!cpuis("MK20DX256VLK7R")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK20DX256VLK7R")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN128CAH12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN256CAH12R")&&!cpuis("MK22FN256VMP12")&&!cpuis("MK22FN512VLL12")&&!cpuis("MK22FN512VMP12")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FX512AVLK12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK20DX64VMB7")&&!cpuis("MK20DX128VMB7")&&!cpuis("MK20DX256VMB7")&&!cpuis("MKS20FN128VFT12")&&!cpuis("MKS20FN128VLH12")&&!cpuis("MKS20FN128VLL12")&&!cpuis("MKS20FN256VFT12")&&!cpuis("MKS20FN256VLH12")&&!cpuis("MKS20FN256VLL12")&&!cpuis("MKS22FN128VFT12")&&!cpuis("MKS22FN128VLH12")&&!cpuis("MKS22FN128VLL12")&&!cpuis("MKS22FN256VFT12")&&!cpuis("MKS22FN256VLH12")&&!cpuis("MKS22FN256VLL12")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FN256VLL12R")&&!cpuis("MK22FN512VFX12")&&!cpuis("MK22FN512VFX12R")&&!cpuis("MK22FN512VLH12R")&&!cpuis("MK22FN128VLH10R")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVLQ10R")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10") bitfld.long 0x14 7. " WPON ,Wakeup pin on" "No effect,Wake up" newline endif sif !cpuis("MK20DN*AB10")&&!cpuis("MK20DN512*AB10R")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVLQ10R")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R") bitfld.long 0x14 4. " TSIE ,Time seconds interrupt enable" "Disabled,Enabled" newline endif sif !cpuis("MK20D*")&&!cpuis("MK22FN128*")&&!cpuis("MK24FN*")&&!cpuis("MK84FN2M0CAU15R")&&!cpuis("MK8?FN256V*")&&!cpuis("MK22FN256CAH12R")&&!cpuis("MK22FN256CAP12R")&&!cpuis("MK22FN256VMP12")&&!cpuis("MK22FN512CAP12R")&&!cpuis("MK22FN512CBP12R")&&!cpuis("MK22FN512VDC12")&&!cpuis("MK22FN512VLH12")&&!cpuis("MK22FN512VLL12")&&!cpuis("MK22FN512VMP12")&&!cpuis("MK24FN1M0CAJ12R")&&!cpuis("MK24FN1M0VDC12R")&&!cpuis("MK24FN1M0VLL12")&&!cpuis("MK24FN1M0VLL12R")&&!cpuis("MK24FN1M0VLQ12R")&&!cpuis("MK24FN256VDC12")&&!cpuis("KK22FN256CAP12R")&&!cpuis("KK22FN512CBP12R")&&!cpuis("MK22FN512VDC12R")&&!cpuis("MK22FN512VFX12")&&!cpuis("MK22FN512VFX12R")&&!cpuis("MK22FN512VLH12R")&&!cpuis("KK22FN128CAH12R")&&!cpuis("KK22FN256CAH12R")&&!cpuis("MK22FN256VLL12R")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVLQ10R")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK22FN128VLH10R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("MKS20FN128VFT12")&&!cpuis("MKS20FN128VLH12")&&!cpuis("MKS20FN128VLL12")&&!cpuis("MKS20FN256VFT12")&&!cpuis("MKS20FN256VLH12")&&!cpuis("MKS20FN256VLL12")&&!cpuis("MKS22FN128VFT12")&&!cpuis("MKS22FN128VLH12")&&!cpuis("MKS22FN128VLL12")&&!cpuis("MKS22FN256VFT12")&&!cpuis("MKS22FN256VLH12")&&!cpuis("MKS22FN256VLL12") sif cpuis("MK22FX512AVLH12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVMD12")||cpuis("KK26FN2M0CAC18R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FX512AVLH12R") bitfld.long 0x14 3. " MOIE ,Monotonic overflow interrupt enable" "Disabled,Enabled" newline endif endif bitfld.long 0x14 2. " TAIE ,Time alarm interrupt enable" "Disabled,Enabled" bitfld.long 0x14 1. " TOIE ,Time overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x14 0. " TIIE ,Time invalid interrupt enable" "Disabled,Enabled" sif !cpuis("MK20D*")&&!cpuis("MK22FN128*")&&!cpuis("MK24FN*")&&!cpuis("MK84FN2M0CAU15R")&&!cpuis("MK8?FN256V*")&&!cpuis("MK22FN256CAH12R")&&!cpuis("MK22FN256CAP12R")&&!cpuis("MK22FN256VMP12")&&!cpuis("MK22FN512CAP12R")&&!cpuis("MK22FN512CBP12R")&&!cpuis("MK22FN512VDC12")&&!cpuis("MK22FN512VLH12")&&!cpuis("MK22FN512VLL12")&&!cpuis("MK22FN512VMP12") sif cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVLH12")||cpuis("KK26FN2M0CAC18R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FX512AVLH12R") rgroup.long 0x20++0x03 line.long 0x00 "TTSR,RTC Tamper Time Seconds Register" group.long 0x24++0x0B line.long 0x00 "MER,RTC Monotonic Enable Register" bitfld.long 0x00 4. " MCE ,Monotonic counter enable" "Disabled,Enabled" line.long 0x04 "MCLR,RTC Monotonic Counter Low Register" line.long 0x08 "MCHR,RTC Monotonic Counter High Register" sif !cpuis("MK20FN1M0VLQ12R") sif cpuis("MK20F*") group.long 0x30++0x0F line.long 0x00 "TER,RTC Tamper Enable Register" bitfld.long 0x00 5. " TME ,Test mode enable" "Disabled,Enabled" bitfld.long 0x00 4. " FSE ,Flash security enable" "Disabled,Enabled" bitfld.long 0x00 3. " TTE ,Temperature tamper enable" "Disabled,Enabled" bitfld.long 0x00 2. " CTE ,Clock tamper enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " VTE ,Voltage tamper enable" "Disabled,Enabled" line.long 0x04 "TDR,RTC Tamper Detect Register" eventfld.long 0x04 5. " TMF ,Test mode flag" "Not Detected,Detected" eventfld.long 0x04 4. " FSF ,Flash security flag" "Not Detected,Detected" eventfld.long 0x04 3. " TTF ,Temperature tamper flag" "Not Detected,Detected" eventfld.long 0x04 2. " CTF ,Clock tamper flag" "Not Detected,Detected" newline eventfld.long 0x04 1. " VTF ,Voltage tamper flag" "Not Detected,Detected" line.long 0x08 "TTR,RTC Tamper Trim Register" bitfld.long 0x08 15.--17. " TDTH ,Temperature detect trim high" "0,1,2,3,4,5,6,7" bitfld.long 0x08 12.--14. " TDTL ,Temperature detect trim low" "0,1,2,3,4,5,6,7" bitfld.long 0x08 9.--11. " CDTH ,Clock detect trim high" "0,1,2,3,4,5,6,7" bitfld.long 0x08 6.--8. " CDTL ,Clock detect trim low" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 3.--5. " VDTH ,Voltage detect trim high" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0.--2. " VDTL ,Voltage detect trim low" "0,1,2,3,4,5,6,7" line.long 0x0C "TIR,RTC Tamper Interrupt Register" bitfld.long 0x0C 5. " TMIE ,Test mode interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 4. " FSIE ,Flash security interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 3. " TTIE ,Temperature tamper interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 2. " CTIE ,Clock tamper interrupt enable" "Disabled,Enabled" newline bitfld.long 0x0C 1. " VTIE ,Voltage tamper interrupt enable" "Disabled,Enabled" endif endif endif endif group.long 0x800++0x07 line.long 0x00 "WAR,RTC Write Access Register" sif !cpuis("MK20FN1M0VLQ12R") sif cpuis("MK20F*") bitfld.long 0x00 15. " TIRW ,Tamper interrupt register write (writes ignored)" "Ignored,Normal" bitfld.long 0x00 14. " TTRW ,Tamper trim register write (writes ignored)" "Ignored,Normal" bitfld.long 0x00 13. " TDRW ,Tamper detect register write (writes ignored)" "Ignored,Normal" bitfld.long 0x00 12. " TERW ,Tamper enable register write (writes ignored)" "Ignored,Normal" newline endif endif sif !cpuis("MK20D*")&&!cpuis("MK24FN256VDC12")&&!cpuis("MK24FN1M0CAJ12R")&&!cpuis("MK24FN1M0VDC12R")&&!cpuis("MK24FN1M0VLL12")&&!cpuis("MK24FN1M0VLL12R")&&!cpuis("MK24FN1M0VLQ12R")&&!cpuis("MK22FN128*")&&!cpuis("MK24FN*")&&!cpuis("MK84FN2M0CAU15R")&&!cpuis("MK8?FN256V*")&&!cpuis("MK22FN256CAH12R")&&!cpuis("MK22FN256CAP12R")&&!cpuis("MK22FN256VMP12")&&!cpuis("MK22FN512CAP12R")&&!cpuis("MK22FN512CBP12R")&&!cpuis("MK22FN512VDC12")&&!cpuis("MK22FN512VLH12")&&!cpuis("MK22FN512VLL12")&&!cpuis("MK22FN512VMP12")&&!cpuis("KK22FN256CAP12R")&&!cpuis("KK22FN512CBP12R")&&!cpuis("MK22FN512VDC12R")&&!cpuis("MK22FN512VFX12")&&!cpuis("MK22FN512VFX12R")&&!cpuis("MK22FN512VLH12R")&&!cpuis("KK22FN128CAH12R")&&!cpuis("KK22FN256CAH12R")&&!cpuis("MK22FN256VLL12R")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVLQ10R")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK22FN128VLH10R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("MKS20FN128VFT12")&&!cpuis("MKS20FN128VLH12")&&!cpuis("MKS20FN128VLL12")&&!cpuis("MKS20FN256VFT12")&&!cpuis("MKS20FN256VLH12")&&!cpuis("MKS20FN256VLL12")&&!cpuis("MKS22FN128VFT12")&&!cpuis("MKS22FN128VLH12")&&!cpuis("MKS22FN128VLL12")&&!cpuis("MKS22FN256VFT12")&&!cpuis("MKS22FN256VLH12")&&!cpuis("MKS22FN256VLL12") sif cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FX512AVLK12")||cpuis("KK26FN2M0CAC18R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FX512AVLH12R") bitfld.long 0x00 11. " MCHW ,Monotonic counter high write" "Ignored,Normal" bitfld.long 0x00 10. " MCLW ,Monotonic counter low write" "Ignored,Normal" bitfld.long 0x00 9. " MERW ,Monotonic enable register write" "Ignored,Normal" bitfld.long 0x00 8. " TTSW ,Tamper time seconds write" "Ignored,Normal" newline endif endif bitfld.long 0x00 7. " IERW ,Interrupt enable register write" "Ignored,Normal" bitfld.long 0x00 6. " LRW ,Lock register write" "Ignored,Normal" bitfld.long 0x00 5. " SRW ,Status register write" "Ignored,Normal" bitfld.long 0x00 4. " CRW ,Control register write" "Ignored,Normal" newline bitfld.long 0x00 3. " TCRW ,Time compensation register write" "Ignored,Normal" bitfld.long 0x00 2. " TARW ,Time alarm register write" "Ignored,Normal" bitfld.long 0x00 1. " TPRW ,Time prescaler register write" "Ignored,Normal" bitfld.long 0x00 0. " TSRW ,Time seconds register write" "Ignored,Normal" line.long 0x04 "RAR,RTC Read Access Register" sif !cpuis("MK20FN1M0VLQ12R") sif cpuis("MK20F*") bitfld.long 0x04 15. " TIRR ,Tamper interrupt register read (reads ignored)" "Ignored,Normal" bitfld.long 0x04 14. " TTRR ,Tamper trim register read (reads ignored)" "Ignored,Normal" bitfld.long 0x04 13. " TDRR ,Tamper detect register read (reads ignored)" "Ignored,Normal" bitfld.long 0x04 12. " TERR ,Tamper enable register read (reads ignored)" "Ignored,Normal" newline endif endif sif !cpuis("MK20D*")&&!cpuis("MK24FN256VDC12")&&!cpuis("MK24FN1M0CAJ12R")&&!cpuis("MK24FN1M0VDC12R")&&!cpuis("MK24FN1M0VLL12")&&!cpuis("MK24FN1M0VLL12R")&&!cpuis("MK24FN1M0VLQ12R")&&!cpuis("MK22FN128*")&&!cpuis("MK24FN*")&&!cpuis("MK84FN2M0CAU15R")&&!cpuis("MK8?FN256V*")&&!cpuis("MK22FN256CAH12R")&&!cpuis("MK22FN256CAP12R")&&!cpuis("MK22FN256VMP12")&&!cpuis("MK22FN512CAP12R")&&!cpuis("MK22FN512CBP12R")&&!cpuis("MK22FN512VDC12")&&!cpuis("MK22FN512VLH12")&&!cpuis("MK22FN512VLL12")&&!cpuis("MK22FN512VMP12")&&!cpuis("KK22FN256CAP12R")&&!cpuis("KK22FN512CBP12R")&&!cpuis("MK22FN512VDC12R")&&!cpuis("MK22FN512VFX12")&&!cpuis("MK22FN512VFX12R")&&!cpuis("MK22FN512VLH12R")&&!cpuis("KK22FN128CAH12R")&&!cpuis("KK22FN256CAH12R")&&!cpuis("MK22FN256VLL12R")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVLQ10R")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK22FN128VLH10R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("MKS20FN128VFT12")&&!cpuis("MKS20FN128VLH12")&&!cpuis("MKS20FN128VLL12")&&!cpuis("MKS20FN256VFT12")&&!cpuis("MKS20FN256VLH12")&&!cpuis("MKS20FN256VLL12")&&!cpuis("MKS22FN128VFT12")&&!cpuis("MKS22FN128VLH12")&&!cpuis("MKS22FN128VLL12")&&!cpuis("MKS22FN256VFT12")&&!cpuis("MKS22FN256VLH12")&&!cpuis("MKS22FN256VLL12") sif cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVLH12")||cpuis("KK26FN2M0CAC18R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FX512AVLH12R") bitfld.long 0x04 11. " MCHR ,Monotonic counter high read" "Ignored,Normal" bitfld.long 0x04 10. " MCLR ,Monotonic counter low read" "Ignored,Normal" bitfld.long 0x04 9. " MERR ,Monotonic enable register read" "Ignored,Normal" bitfld.long 0x04 8. " TTSR ,Tamper time seconds read" "Ignored,Normal" newline endif endif bitfld.long 0x04 7. " IERR ,Interrupt enable register read" "Ignored,Normal" bitfld.long 0x04 6. " LRR ,Lock register read" "Ignored,Normal" bitfld.long 0x04 5. " SRR ,Status register read" "Ignored,Normal" bitfld.long 0x04 4. " CRR ,Control register read" "Ignored,Normal" newline bitfld.long 0x04 3. " TCRR ,Time compensation register read" "Ignored,Normal" bitfld.long 0x04 2. " TARR ,Time alarm register read" "Ignored,Normal" bitfld.long 0x04 1. " TPRR ,Time prescaler register read" "Ignored,Normal" bitfld.long 0x04 0. " TSRR ,Time seconds register read" "Ignored,Normal" width 0x0B tree.end tree "USBOTG (Universal Serial Bus OTG Controller)" base ad:0x40072000 width 10. rgroup.byte 0x00++0x00 line.byte 0x00 "PERID,Peripheral ID Register" hexmask.byte 0x00 0.--5. 1. " ID ,Peripheral identification" rgroup.byte 0x04++0x00 line.byte 0x00 "IDCOMP,Peripheral ID Complement Register" hexmask.byte 0x00 0.--5. 1. " NID ,Ones complement of peripheral identification" rgroup.byte 0x08++0x00 line.byte 0x00 "REV,Peripheral Revision Register" rgroup.byte 0x0C++0x00 line.byte 0x00 "ADDINFO,Peripheral Additional Info Register" sif !cpuis("MK26FN*")&&!cpuis("MK22FN128*")&&!cpuis("MK22FN256*")&&!cpuis("MK21F*AVMC12")&&!cpuis("MK21D*AVMC5")&&!cpuis("MK21F*AVLQ12")&&!cpuis("MK21F*AVMD12")&&!cpuis("MK21D*AVLK5")&&!cpuis("MK65F*")&&!cpuis("MK66F*")&&!cpuis("MK84FN2M0CAU15R")&&!cpuis("MK8?FN256V*")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK22FX512AVLK12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK70FN1M0VMJ1*")&&!cpuis("MK22FN512CAP12R")&&!cpuis("MK22FN512CBP12R")&&!cpuis("MK22FN512VLL12")&&!cpuis("MK22FN512VMP12")&&!cpuis("MK24FN1M0CAJ12R")&&!cpuis("MK24FN1M0VDC12R")&&!cpuis("MK24FN1M0VLL12")&&!cpuis("MK24FN1M0VLL12R")&&!cpuis("MK24FN1M0VLQ12R")&&!cpuis("MK24FN256VDC12")&&!cpuis("MKS2?FN???V??12")&&!cpuis("MK21D*AVMC5R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("KK22FN???C?P12R")&&!cpuis("MK22FN512VDC12*")&&!cpuis("MK22FN512VFX12*")&&!cpuis("MK22FN512VLH12R")&&!cpuis("KK22FN???CAH12R")&&!cpuis("MK22FN256VLL12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("?K28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("KK65FN2M0CAC18R") bitfld.byte 0x00 3.--7. " IRQ_NUM ,Assigned interrupt request number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline endif bitfld.byte 0x00 0. " IEHOST ,Host mode enable" "Disabled,Enabled" sif cpuis("MK20DN512*AB10R")||cpuis("MK21D*AVLK5")||(cpuis("MK21F*AVLQ12")||cpuis("MK21F*AVMD12"))||cpuis("MK21D*AVMC5")||cpuis("MK21F*AVMC12")||cpuis("MK22FX512*")||cpuis("MK22FN256*")||cpuis("MK22FN128*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK20DX256VLQ10R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK20DX256VLK10R")||cpuis("MK21FX512VMD10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FX512VMC10")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MK70FN1M0VMJ1*")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN256VDC12")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60DN512ZCAB10R")||cpuis("KK60FN1M0VLQ15")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVLL10") sif cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("MK63FN1M0VLQ12R") group.byte 0x10++0x00 line.byte 0x00 "OTGISTAT,OTG Interrupt Status Register" eventfld.byte 0x00 6. " ONE_MSEC ,1 millisecond timer expired interrupt" "No interrupt,Interrupt" eventfld.byte 0x00 5. " LINE_STATE_CHG ,USB line state change interrupt" "No interrupt,Interrupt" elif cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R") group.byte 0x10++0x00 line.byte 0x00 "OTGISTAT,OTG Interrupt Status Register" bitfld.byte 0x00 7. " ID_CHG ,ID Signal from USB connector change interrupt" "No interrupt,Interrupt" bitfld.byte 0x00 6. " ONE_MSEC ,1 millisecond timer expired interrupt" "No interrupt,Interrupt" bitfld.byte 0x00 5. " LINE_STATE_CHG ,USB line state change interrupt" "No interrupt,Interrupt" newline bitfld.byte 0x00 3. " SESS_VLD_CHG ,VBUS change indicating session valid/invalid interrupt" "No interrupt,Interrupt" bitfld.byte 0x00 2. " B_SESS_CHG ,VBUS change on B device interrupt" "No interrupt,Interrupt" bitfld.byte 0x00 0. " A_VBUS_CHG ,VBUS change on A device interrupt" "No interrupt,Interrupt" else group.byte 0x10++0x00 line.byte 0x00 "OTGISTAT,OTG Interrupt Status Register" eventfld.byte 0x00 7. " ID_CHG ,ID signal from USB connector change interrupt" "No interrupt,Interrupt" eventfld.byte 0x00 6. " ONE_MSEC ,1 millisecond timer expired interrupt" "No interrupt,Interrupt" eventfld.byte 0x00 5. " LINE_STATE_CHG ,USB line state change interrupt" "No interrupt,Interrupt" newline eventfld.byte 0x00 3. " SESS_VLD_CHG ,VBUS change indicating session valid/invalid interrupt" "No interrupt,Interrupt" eventfld.byte 0x00 2. " B_SESS_CHG ,VBUS change on B device interrupt" "No interrupt,Interrupt" eventfld.byte 0x00 0. " A_VBUS_CHG ,VBUS change on A device interrupt" "No interrupt,Interrupt" endif elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MKS2?FN???V??12")||cpuis("KK22FN???C?P12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VFX12*")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN???CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("?K28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") group.byte 0x10++0x00 line.byte 0x00 "OTGISTAT,OTG Interrupt Status Register" eventfld.byte 0x00 6. " ONE_MSEC ,1 millisecond timer expired interrupt" "No interrupt,Interrupt" eventfld.byte 0x00 5. " LINE_STATE_CHG ,USB line state change interrupt" "No interrupt,Interrupt" else group.byte 0x10++0x00 line.byte 0x00 "OTGISTAT,OTG Interrupt Status Register" bitfld.byte 0x00 7. " IDCHG ,ID signal from USB connector change interrupt" "No interrupt,Interrupt" bitfld.byte 0x00 6. " ONEMSEC ,1 millisecond timer expired interrupt" "No interrupt,Interrupt" bitfld.byte 0x00 5. " LINE_STATE_CHG ,USB line state change interrupt" "No interrupt,Interrupt" newline bitfld.byte 0x00 3. " SESSVLDCHG ,VBUS change indicating session valid/invalid interrupt" "No interrupt,Interrupt" bitfld.byte 0x00 2. " B_SESS_CHG ,VBUS change on B device interrupt" "No interrupt,Interrupt" bitfld.byte 0x00 0. " AVBUSCHG ,VBUS change on A device interrupt" "No interrupt,Interrupt" endif sif cpuis("MK8?FN256V*") group.byte 0x14++0x00 line.byte 0x00 "OTGICR,OTG Interrupt Control Register" bitfld.byte 0x00 6. " ONE_MSEC_EN ,1 millisecond interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 5. " LINE_STATE_EN ,Line state change interrupt enable" "Disabled,Enabled" else group.byte 0x14++0x00 line.byte 0x00 "OTGICR,OTG Interrupt Control Register" bitfld.byte 0x00 7. " ID_EN ,ID interrupt enable" "Disabled,Enabled" newline sif !cpuis("MK84FN2M0CAU15R")&&!cpuis("MK22FN128CAH12R")&&!cpuis("MK22FN256CAH12R")&&!cpuis("MK22FN256CAP12R")&&!cpuis("MK22FN256VMP12")&&!cpuis("MK22FN512CAP12R")&&!cpuis("MK22FN512CBP12R")&&!cpuis("MK22FN512VDC12")&&!cpuis("MK22FN512VLH12")&&!cpuis("MK22FN512VLL12")&&!cpuis("MK22FN512VMP12")&&!cpuis("MK24FN1M0CAJ12R")&&!cpuis("MK24FN1M0VDC12R")&&!cpuis("MK24FN1M0VLL12")&&!cpuis("MK24FN1M0VLL12R")&&!cpuis("MK24FN1M0VLQ12R")&&!cpuis("MKS2?FN???V??12")&&!cpuis("KK22FN???C?P12R")&&!cpuis("MK22FN512VDC12*")&&!cpuis("MK22FN512VFX12*")&&!cpuis("MK22FN512VLH12R")&&!cpuis("KK22FN???CAH12R")&&!cpuis("MK22FN256VLL12R")&&!cpuis("MK22FN128VLH10R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("?K28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK63FN1M0VLQ12R") bitfld.byte 0x00 6. " ONE_MSEC_EN ,1 millisecond interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 5. " LINE_STATE_EN ,Line state change interrupt enable" "Disabled,Enabled" newline endif bitfld.byte 0x00 3. " SESS_VLD_EN ,Session valid interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 2. " B_SESS_EN ,B session end interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 0. " A_VBUS_EN ,A VBUS valid interrupt enable" "Disabled,Enabled" endif sif cpuis("MK20DN512*AB10R")||cpuis("MK21D*AVLK5")||cpuis("MK21F*AVLQ12")||cpuis("MK21F*AVMD12")||cpuis("MK21D*AVMC5")||cpuis("MK21F*AVMC12")||cpuis("MK22FX512*")||cpuis("MK22FN256*")||cpuis("MK22FN128*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK70FN1M0VMJ1*")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN256VDC12") sif !cpuis("MK22FX512AVLK12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVLH12") sif cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R") group.byte 0x18++0x00 line.byte 0x00 "OTGSTAT,OTG Status Register" bitfld.byte 0x00 5. " LINE_STATE_STABLE ,LINE_STATE_CHG bit stable" "Not stable,Stable" elif cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FX512AVLH12R") group.byte 0x18++0x00 line.byte 0x00 "OTGSTAT,OTG Status Register" bitfld.byte 0x00 7. " ID ,Current state of the ID pin on USB connector" "Type A cable,No/Type B cable" bitfld.byte 0x00 6. " ONE_MSEC_EN ,1 millisecond interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 5. " LINE_STATE_STABLE ,LINE_STATE_CHG bit stable" "Not stable,Stable" newline bitfld.byte 0x00 3. " SESS_VLD ,Session valid" "Invalid,Valid" bitfld.byte 0x00 2. " B_SESS_END ,B session end" "Not end,End" bitfld.byte 0x00 0. " A_VBUS_VLD ,A VBUS valid" "Invalid,Valid" else group.byte 0x18++0x00 line.byte 0x00 "OTGSTAT,OTG Status Register" bitfld.byte 0x00 7. " ID ,Current state of the ID pin on USB connector" "Type A cable,No/Type B cable" bitfld.byte 0x00 5. " LINE_STATE_STABLE ,LINE_STATE_CHG bit stable" "Not stable,Stable" bitfld.byte 0x00 3. " SESS_VLD ,Session valid" "Below valid trsh,Above valid trsh" newline bitfld.byte 0x00 2. " B_SESS_END ,B Session end" "Above end trsh,Below end trsh" bitfld.byte 0x00 0. " A_VBUS_VLD ,A VBUS valid" "Below valid trsh,Above valid trsh" endif else group.byte 0x18++0x00 line.byte 0x00 "OTGSTAT,OTG Status Register" bitfld.byte 0x00 7. " ID ,Current state of the ID pin on USB connector" "Type A cable,No/Type B cable" bitfld.byte 0x00 6. " ONE_MSEC_EN ,1 millisecond interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 5. " LINE_STATE_STABLE ,LINE_STATE_CHG bit stable" "Not stable,Stable" newline bitfld.byte 0x00 3. " SESS_VLD ,Session valid" "Invalid,Valid" bitfld.byte 0x00 2. " B_SESS_END ,B session end" "Not end,End" bitfld.byte 0x00 0. " A_VBUS_VLD ,A VBUS valid" "Invalid,Valid" endif elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MKS2?FN???V??12")||cpuis("KK22FN???C?P12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VFX12*")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN???CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("?K28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") group.byte 0x18++0x00 line.byte 0x00 "OTGSTAT,OTG Status Register" bitfld.byte 0x00 5. " LINE_STATE_STABLE ,LINE_STATE_CHG bit stable" "Not stable,Stable" elif cpuis("MK20DX256VLQ10R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK21FX512VMD10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FX512VMC10")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10") group.byte 0x18++0x00 line.byte 0x00 "OTGSTAT,OTG Status Register" bitfld.byte 0x00 7. " ID ,Current state of the ID pin on USB connector" "Type A cable,No/Type B cable" rbitfld.byte 0x00 6. " ONE_MSEC_EN ,1 millisecond interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 5. " LINE_STATE_STABLE ,LINE_STATE_CHG bit stable" "Not stable,Stable" newline bitfld.byte 0x00 3. " SESS_VLD ,Session valid" "Invalid,Valid" bitfld.byte 0x00 2. " B_SESS_END ,B session end" "Not end,End" bitfld.byte 0x00 0. " A_VBUS_VLD ,A VBUS valid" "Invalid,Valid" elif cpuis("MK63FN1M0VLQ12R") group.byte 0x18++0x00 line.byte 0x00 "OTGSTAT,OTG Status Register" bitfld.byte 0x00 6. " ONEMSECEN ,1 millisecond interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 5. " LINESTATESTABLE ,LINE_STATE_CHG bit stable" "Not stable,Stable" else group.byte 0x18++0x00 line.byte 0x00 "OTGSTAT,OTG Status Register" bitfld.byte 0x00 7. " ID ,Current state of the ID pin on USB connector" "Type A cable,No/Type B cable" bitfld.byte 0x00 6. " ONE_MSEC_EN ,1 millisecond interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 5. " LINE_STATE_STABLE ,LINE_STATE_CHG bit stable" "Not stable,Stable" newline bitfld.byte 0x00 3. " SESS_VLD ,Session valid" "Invalid,Valid" bitfld.byte 0x00 2. " B_SESS_END ,B session end" "Not end,End" bitfld.byte 0x00 0. " A_VBUS_VLD ,A VBUS valid" "Invalid,Valid" endif sif cpuis("MK20DN512*AB10R")||cpuis("MK21D*AVLK5")||cpuis("MK21F*AVLQ12")||cpuis("MK21F*AVMD12")||cpuis("MK21D*AVMC5")||cpuis("MK21F*AVMC12")||cpuis("MK22FX512*")||cpuis("MK22FN256*")||cpuis("MK22FN128*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63*")||cpuis("MK64*")||cpuis("MK65*")||cpuis("MK66*")||cpuis("MK8?FN256V*")||cpuis("MK20DX256VLQ10R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK21FX512VMD10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FX512VMC10")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MK70FN1M0VMJ1*")||cpuis("MK40*Z*10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60FN1M0VLQ15")||cpuis("MK60DN512ZCAB10R")||cpuis("MKS2?FN???V??12")||cpuis("KK22FN???CAH12R")||cpuis("MK20D????ZVLL10")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D*AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK22FN???C?P12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VFX12*")||cpuis("MK22FN512VLH12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("?K28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK27FN2M0VMI15")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60DN512ZCAB10R")||cpuis("KK60FN1M0VLQ15")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVLL10") if ((per.b(ad:0x40072000+0x94)&0x08)==0x08) group.byte 0x1C++0x00 line.byte 0x00 "OTGCTL,OTG Control Register" bitfld.byte 0x00 7. " DP_HIGH ,D+ data line pull-up resistor enable" "Disabled,Enabled" bitfld.byte 0x00 5. " DP_LOW ,D+ data line pull-down resistor enable" "Disabled,Enabled" bitfld.byte 0x00 4. " DM_LOW ,D- data line pull-down resistor enable" "Disabled,Enabled" newline bitfld.byte 0x00 2. " OTG_EN ,On-The-Go pull-up/pull-down resistor enable" "D+ D- pull-down,Controlled by DP & DM" else group.byte 0x1C++0x00 line.byte 0x00 "OTGCTL,OTG Control Register" bitfld.byte 0x00 7. " DP_HIGH ,D+ data line pull-up resistor enable" "Disabled,Enabled" bitfld.byte 0x00 5. " DP_LOW ,D+ data line pull-down resistor enable" "Disabled,Enabled" bitfld.byte 0x00 4. " DM_LOW ,D- data line pull-down resistor enable" "Disabled,Enabled" newline bitfld.byte 0x00 2. " OTG_EN ,On-The-Go pull-up/pull-down resistor enable" "D+ pull-up,Controlled by DP & DM" endif else group.byte 0x1C++0x00 line.byte 0x00 "OTGCTL,OTG Control Register" bitfld.byte 0x00 7. " DP_HIGH ,D+ data line pull-up resistor enable" "Disabled,Enabled" bitfld.byte 0x00 5. " DP_LOW ,D+ data line pull-down resistor enable" "Disabled,Enabled" bitfld.byte 0x00 4. " DM_LOW ,D- data line pull-down resistor enable" "Disabled,Enabled" newline bitfld.byte 0x00 2. " OTG_EN ,On-The-Go pull-up/pull-down resistor enable" "Disabled,Enabled" endif sif cpuis("MK20DN512*AB10R")||cpuis("MK27FN2M0VMI15")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FX512VMC12R")||cpuis("MK21D*AVLK5")||cpuis("MK21F*AVLQ12")||cpuis("MK21F*AVMD12")||cpuis("MK21D*AVMC5")||cpuis("MK21F*AVMC12")||cpuis("MK22FX512*")||cpuis("MK22FN256*")||cpuis("MK22FN128*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK70FN1M0VMJ1*")||cpuis("MK40D*Z*")||cpuis("MKS2?FN???V??12")||cpuis("?K28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60DN512ZCAB10R")||cpuis("KK60FN1M0VLQ15")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVLL10") if ((per.b(ad:0x40072000+0x94)&0x08)==0x08) group.byte 0x80++0x00 line.byte 0x00 "ISTAT,Interrupt Status Register" eventfld.byte 0x00 7. " STALL ,Stall interrupt" "No interrupt,Interrupt" eventfld.byte 0x00 6. " ATTACH ,Attach interrupt" "No interrupt,Interrupt" newline eventfld.byte 0x00 5. " RESUME ,Signal remote wake-up signaling interrupt" "No interrupt,Interrupt" eventfld.byte 0x00 4. " SLEEP ,Idle on USB bus (for 3ms) interrupt" "No interrupt,Interrupt" eventfld.byte 0x00 3. " TOKDNE ,Token completed interrupt" "No interrupt,Interrupt" newline eventfld.byte 0x00 2. " SOF_TOK ,Start of frame token interrupt" "No interrupt,Interrupt" eventfld.byte 0x00 1. " ERROR ,Error interrupt" "No interrupt,Interrupt" eventfld.byte 0x00 0. " USB_RST ,USB reset interrupt" "No interrupt,Interrupt" group.byte 0x84++0x00 line.byte 0x00 "INTEN,Interrupt Enable Register" bitfld.byte 0x00 7. " STALL_EN ,STALL interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 6. " ATTACH_EN ,ATTACH interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 5. " RESUME_EN ,RESUME interrupt enable" "Disabled,Enabled" newline bitfld.byte 0x00 4. " SLEEP_EN ,SLEEP interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 3. " TOK_DNE_EN ,TOK_DNE interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 2. " SOF_TOK_EN ,SOF_TOK interrupt enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " ERROR_EN ,ERROR interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 0. " USB_RST_EN ,USB_RST interrupt enable" "Disabled,Enabled" group.byte 0x88++0x00 line.byte 0x00 "ERRSTAT,Error Interrupt Status Register" eventfld.byte 0x00 7. " BTS_ERR ,Bit stuff error interrupt" "No interrupt,Interrupt" eventfld.byte 0x00 5. " DMA_ERR ,DMA error interrupt" "No interrupt,Interrupt" eventfld.byte 0x00 4. " BTO_ERR ,Bus turnaround timeout error interrupt" "No interrupt,Interrupt" newline eventfld.byte 0x00 3. " DFN8 ,Data received was not 8 bits in length interrupt" "No interrupt,Interrupt" eventfld.byte 0x00 2. " CRC16 ,CRC16 error interrupt" "No interrupt,Interrupt" eventfld.byte 0x00 1. " EOF ,End of frame error interrupt" "No interrupt,Interrupt" newline eventfld.byte 0x00 0. " PID_ERR ,PID check failed interrupt" "No interrupt,Interrupt" group.byte 0x8C++0x00 line.byte 0x00 "ERREN,Error Interrupt Enable Register" bitfld.byte 0x00 7. " BTS_ERR_EN ,BTS_ERR interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 5. " DMA_ERR_EN ,DMA_ERR interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 4. " BTO_ERR_EN ,BTO_ERR interrupt enable" "Disabled,Enabled" newline bitfld.byte 0x00 3. " DFN8_EN ,DFN8 interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 2. " CRC16_EN ,CRC16 interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 1. " EOF_EN ,CRC5/EOF interrupt enable" "Disabled,Enabled" newline bitfld.byte 0x00 0. " PID_ERR_EN ,PID_ERR interrupt enable" "Disabled,Enabled" else group.byte 0x80++0x00 line.byte 0x00 "ISTAT,Interrupt Status Register" eventfld.byte 0x00 7. " STALL ,Stall interrupt" "No interrupt,Interrupt" newline eventfld.byte 0x00 5. " RESUME ,Signal remote wake-up signaling interrupt" "No interrupt,Interrupt" eventfld.byte 0x00 4. " SLEEP ,Idle on USB bus (for 3ms) interrupt" "No interrupt,Interrupt" eventfld.byte 0x00 3. " TOKDNE ,Token completed interrupt" "No interrupt,Interrupt" newline eventfld.byte 0x00 2. " SOF_TOK ,Start of frame token interrupt" "No interrupt,Interrupt" eventfld.byte 0x00 1. " ERROR ,Error interrupt" "No interrupt,Interrupt" eventfld.byte 0x00 0. " USB_RST ,USB reset interrupt" "No interrupt,Interrupt" group.byte 0x84++0x00 line.byte 0x00 "INTEN,Interrupt Enable Register" bitfld.byte 0x00 7. " STALL_EN ,STALL interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 6. " ATTACH_EN ,ATTACH interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 5. " RESUME_EN ,RESUME interrupt enable" "Disabled,Enabled" newline bitfld.byte 0x00 4. " SLEEP_EN ,SLEEP interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 3. " TOK_DNE_EN ,TOK_DNE interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 2. " SOF_TOK_EN ,SOF_TOK interrupt enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " ERROR_EN ,ERROR interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 0. " USB_RST_EN ,USB_RST interrupt enable" "Disabled,Enabled" group.byte 0x88++0x00 line.byte 0x00 "ERRSTAT,Error Interrupt Status Register" eventfld.byte 0x00 7. " BTS_ERR ,Bit stuff error interrupt" "No interrupt,Interrupt" eventfld.byte 0x00 5. " DMA_ERR ,DMA error interrupt" "No interrupt,Interrupt" eventfld.byte 0x00 4. " BTO ,Bus turnaround timeout error interrupt" "No interrupt,Interrupt" newline eventfld.byte 0x00 3. " DFN8 ,Data received was not 8 bits in length interrupt" "No interrupt,Interrupt" eventfld.byte 0x00 2. " CRC16 ,CRC16 error interrupt" "No interrupt,Interrupt" eventfld.byte 0x00 1. " CRC5 ,CRC5 error interrupt" "No interrupt,Interrupt" newline eventfld.byte 0x00 0. " PID_ERR ,PID check failed interrupt" "No interrupt,Interrupt" group.byte 0x8C++0x00 line.byte 0x00 "ERREN,Error Interrupt Enable Register" bitfld.byte 0x00 7. " BTS_ERR_EN ,BTS_ERR interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 5. " DMA_ERR_EN ,DMA_ERR interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 4. " BTO_ERR_EN ,BTO_ERR interrupt enable" "Disabled,Enabled" newline bitfld.byte 0x00 3. " DFN8_EN ,DFN8 interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 2. " CRC16_EN ,CRC16 interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 1. " CRC5_EN ,CRC5/EOF interrupt enable" "Disabled,Enabled" newline bitfld.byte 0x00 0. " PID_ERR_EN ,PID_ERR interrupt enable" "Disabled,Enabled" endif endif sif cpuis("MK20DN512*AB10R")||cpuis("MK21D*AVLK5")||cpuis("MK21F*AVLQ12")||cpuis("MK21F*AVMD12")||cpuis("MK21D*AVMC5")||cpuis("MK21F*AVMC12")||cpuis("MK22FX512*")||cpuis("MK22FN256*")||cpuis("MK22FN128*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20DX256VLQ10R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK21FX512VMD10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FX512VMC10")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK70FN1M0VMJ1*")||cpuis("MK40*Z*10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK20D????ZVLL10")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MKS2?FN???V??12")||cpuis("MK20D????ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D*AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK22FN???C?P12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VFX12*")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN???CAH12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("?K28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") if (((per.b(ad:0x40072000+0x80))&0x08)==0x08) rgroup.byte 0x90++0x00 line.byte 0x00 "STAT,Status Register" hexmask.byte 0x00 4.--7. 0x10 " ENDP ,Endpoint address" bitfld.byte 0x00 3. " TX ,Receive/Transmit indicator" "Receive,Transmit" bitfld.byte 0x00 2. " ODD ,Last buffer descriptor in odd bank of BDT" "Even,Odd" else hgroup.byte 0x90++0x00 hide.byte 0x00 "STAT,Status Register" endif elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60DN512ZCAB10R")||cpuis("KK60FN1M0VLQ15")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVLL10") if ((per.b(ad:0x40072000+0x80)&0x08)==0x08) rgroup.byte 0x90++0x00 line.byte 0x00 "STAT,Status Register" hexmask.byte 0x00 4.--7. 0x10 " ENDP ,Endpoint address" bitfld.byte 0x00 3. " TX ,Transmit indicator" "Receive,Transmit" bitfld.byte 0x00 2. " ODD ,Last buffer descriptor in odd bank of BDT" "Even,Odd" else hgroup.byte 0x90++0x00 hide.byte 0x00 "STAT,Status Register" in endif else if ((per.b(ad:0x40072000+0x80)&0x08)==0x08) rgroup.byte 0x90++0x00 line.byte 0x00 "STAT,Status Register" hexmask.byte 0x00 4.--7. 0x10 " ENDP ,Endpoint address" bitfld.byte 0x00 3. " TX ,Transmit indicator" "Receive,Transmit" bitfld.byte 0x00 2. " ODD ,Last buffer descriptor in odd bank of BDT" "Even,Odd" else hgroup.byte 0x90++0x00 hide.byte 0x00 "STAT,Status Register" endif endif if ((per.b(ad:0x40072000+0x94)&0x08)==0x08) group.byte 0x94++0x00 line.byte 0x00 "CTL,Control Register" bitfld.byte 0x00 7. " JSTATE ,Live USB differential receiver JSTATE signal" "Low,High" bitfld.byte 0x00 6. " SE0 ,Live USB single ended zero signal" "Low,High" bitfld.byte 0x00 5. " TOKEN_BUSY ,USB module is busy executing a USB token" "Not busy,Busy" newline bitfld.byte 0x00 4. " RESET ,USB reset" "No reset,Reset" newline bitfld.byte 0x00 3. " HOST_MODE_EN ,Host mode enable" "Disabled,Enabled" bitfld.byte 0x00 2. " RESUME ,Resume signaling enable" "Disabled,Enabled" bitfld.byte 0x00 1. " ODD_RST ,BDT ODD ping/pong bits reset" "No reset,Reset" newline bitfld.byte 0x00 0. " USB_EN_SOF_EN ,USB enable" "Disabled,Enabled" else group.byte 0x94++0x00 line.byte 0x00 "CTL,Control Register" bitfld.byte 0x00 7. " JSTATE ,Live USB differential receiver JSTATE signal" "Low,High" bitfld.byte 0x00 6. " SE0 ,Live USB single ended zero signal" "Low,High" bitfld.byte 0x00 5. " TX_SUSPEND ,TXD_SUSPEND is set when the SIE has disabled packet transmission and reception" "No,Yes" newline newline bitfld.byte 0x00 3. " HOST_MODE_EN ,Host mode enable" "Disabled,Enabled" bitfld.byte 0x00 2. " RESUME ,Resume signaling enable" "Disabled,Enabled" bitfld.byte 0x00 1. " ODD_RST ,BDT ODD ping/pong bits reset" "No reset,Reset" newline bitfld.byte 0x00 0. " USB_EN_SOF_EN ,USB Enable" "Disabled,Enabled" endif group.byte 0x98++0x00 line.byte 0x00 "ADDR,Address Register" bitfld.byte 0x00 7. " LS_EN ,Low speed enable" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 0x01 " ADDR ,USB address" group.byte 0x9C++0x00 line.byte 0x00 "BDTPAGE1,BDT Page Register 1" hexmask.byte 0x00 1.--7. 0x02 " BDT_BA[15:9] ,BDT base address bits [15:9]" group.byte 0xA0++0x00 line.byte 0x00 "FRMNUML,Frame Number Register Low" group.byte 0xA4++0x00 line.byte 0x00 "FRMNUMH,Frame Number Register High" bitfld.byte 0x00 0.--2. " FRM[10:8] ,Upper 3 bits of BDT system memory address" "0,1,2,3,4,5,6,7" sif cpuis("MK20DN512*AB10R")||cpuis("MK21D*AVLK5")||cpuis("MK21F*AVLQ12")||cpuis("MK21F*AVMD12")||cpuis("MK21D*AVMC5")||cpuis("MK21F*AVMC12")||cpuis("MK22FX512*")||cpuis("MK22FN256*")||cpuis("MK22FN128*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63*")||cpuis("MK64*")||cpuis("MK65*")||cpuis("MK66*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20DX256VLQ10R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK21FX512VMD10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FX512VMC10")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MK70FN1M0VMJ1*")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN1M0VMC10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40*Z*10")||cpuis("MKS2?FN???V??12")||cpuis("MK20D????ZVLL10")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D*AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK22FN???C?P12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VFX12*")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN???CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("?K28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60DN512ZCAB10R")||cpuis("KK60FN1M0VLQ15")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVLL10") if ((per.b(ad:0x40072000+0x94)&0x08)==0x08) if (((per.b(ad:0x40072000+0x94))&0x20)==0x20) rgroup.byte 0xA8++0x00 line.byte 0x00 "TOKEN,Token Register" bitfld.byte 0x00 4.--7. " TOKEN_PID ,Token type" ",Out,,,,,,,,In,,,,Setup,?..." hexmask.byte 0x00 0.--3. 0x01 " TOKEN_ENDPT ,Endpoint address for the token command" else group.byte 0xA8++0x00 line.byte 0x00 "TOKEN,Token Register" bitfld.byte 0x00 4.--7. " TOKEN_PID ,Token type" ",Out,,,,,,,,In,,,,Setup,?..." hexmask.byte 0x00 0.--3. 0x01 " TOKEN_ENDPT ,Endpoint address for the token command" endif group.byte 0xAC++0x00 line.byte 0x00 "SOFTHLD,SOF Threshold Register" else hgroup.byte 0xA8++0x00 hide.byte 0x00 "TOKEN,Token Register" hgroup.byte 0xAC++0x00 hide.byte 0x00 "SOFTHLD,SOF Threshold Register" endif else if ((per.b(ad:0x40072000+0x94)&0x08)==0x08) group.byte 0xA8++0x0 line.byte 0x00 "TOKEN,Token Register" bitfld.byte 0x00 4.--7. " TOKEN_PID ,Token type" ",Out,,,,,,,,In,,,,Setup,?..." bitfld.byte 0x00 0.--3. " TOKEN_ENDPT ,Endpoint address for the token command" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111" group.byte 0xAC++0x0 line.byte 0x00 "SOFTHLD,SOF Threshold Register" else hgroup.byte 0xA8++0x0 hide.byte 0x00 "TOKEN,Token Register" hgroup.byte 0xAC++0x0 hide.byte 0x00 "SOFTHLD,SOF Threshold Register" endif endif group.byte 0xB0++0x00 line.byte 0x00 "BDTPAGE2,BDT Page Register 2" group.byte 0xB4++0x00 line.byte 0x00 "BDTPAGE3,BDT Page Register 3" width 9. tree "Endpoints 0-15" if ((per.b(ad:0x40072000+0x94)&0x08)==0x08)&&((per.b(ad:0x40072000+0xC0)&0x0C)==0x0C) group.byte 0xC0++0x00 line.byte 0x00 "ENDPT0,Endpoint Control Register 0" bitfld.byte 0x00 7. " HOST_WO_HUB ,Host communicate to directly connected low speed device" "Not directly,Directly or no LS dev" bitfld.byte 0x00 6. " RETRY_DIS ,Negative hardware acknowledgment transactions retry disable" "No,Yes" newline bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (SETUP) transfers disable" "No,Yes" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 1. " EP_STALL ,Endpoint stall" "Not stalled,Stalled" newline bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" elif ((per.b(ad:0x40072000+0x94)&0x08)==0x00)&&((per.b(ad:0x40072000+0xC0)&0x0C)==0x0C) group.byte 0xC0++0x00 line.byte 0x00 "ENDPT0,Endpoint Control Register 0" newline bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (SETUP) transfers disable" "No,Yes" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 1. " EP_STALL ,Endpoint stall" "Not stalled,Stalled" newline bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" elif ((per.b(ad:0x40072000+0x94)&0x08)==0x08)&&((per.b(ad:0x40072000+0xC0)&0x0C)!=0x0C) group.byte 0xC0++0x00 line.byte 0x00 "ENDPT0,Endpoint Control Register 0" bitfld.byte 0x00 7. " HOST_WO_HUB ,Host communicate to directly connected low speed device" "Not directly,Directly or no LS dev" bitfld.byte 0x00 6. " RETRY_DIS ,Negative hardware acknowledgment transactions retry disable" "No,Yes" newline bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" newline else group.byte 0xC0++0x00 line.byte 0x00 "ENDPT0,Endpoint Control Register 0" newline bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" endif if (((per.b(ad:0x40072000+0xC4)&0x0C)==0x0C)) group.byte 0xC4++0x00 line.byte 0x00 "ENDPT1,Endpoint Control Register 1" bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (SETUP) transfers disable" "No,Yes" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " EP_STALL ,Endpoint stall" "Not stalled,Stalled" bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" elif (((per.b(ad:0x40072000+0xC4)&0x0C)==0x08)||((per.b(ad:0x40072000+0xC4)&0x0C)==0x04)) group.byte 0xC4++0x00 line.byte 0x00 "ENDPT1,Endpoint Control Register 1" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " EP_STALL ,Endpoint stall" "Not stalled,Stalled" bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" else group.byte 0xC4++0x00 line.byte 0x00 "ENDPT1,Endpoint Control Register 1" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" endif if (((per.b(ad:0x40072000+0xC8)&0x0C)==0x0C)) group.byte 0xC8++0x00 line.byte 0x00 "ENDPT2,Endpoint Control Register 2" bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (SETUP) transfers disable" "No,Yes" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " EP_STALL ,Endpoint stall" "Not stalled,Stalled" bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" elif (((per.b(ad:0x40072000+0xC8)&0x0C)==0x08)||((per.b(ad:0x40072000+0xC8)&0x0C)==0x04)) group.byte 0xC8++0x00 line.byte 0x00 "ENDPT2,Endpoint Control Register 2" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " EP_STALL ,Endpoint stall" "Not stalled,Stalled" bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" else group.byte 0xC8++0x00 line.byte 0x00 "ENDPT2,Endpoint Control Register 2" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" endif if (((per.b(ad:0x40072000+0xCC)&0x0C)==0x0C)) group.byte 0xCC++0x00 line.byte 0x00 "ENDPT3,Endpoint Control Register 3" bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (SETUP) transfers disable" "No,Yes" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " EP_STALL ,Endpoint stall" "Not stalled,Stalled" bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" elif (((per.b(ad:0x40072000+0xCC)&0x0C)==0x08)||((per.b(ad:0x40072000+0xCC)&0x0C)==0x04)) group.byte 0xCC++0x00 line.byte 0x00 "ENDPT3,Endpoint Control Register 3" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " EP_STALL ,Endpoint stall" "Not stalled,Stalled" bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" else group.byte 0xCC++0x00 line.byte 0x00 "ENDPT3,Endpoint Control Register 3" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" endif if (((per.b(ad:0x40072000+0xD0)&0x0C)==0x0C)) group.byte 0xD0++0x00 line.byte 0x00 "ENDPT4,Endpoint Control Register 4" bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (SETUP) transfers disable" "No,Yes" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " EP_STALL ,Endpoint stall" "Not stalled,Stalled" bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" elif (((per.b(ad:0x40072000+0xD0)&0x0C)==0x08)||((per.b(ad:0x40072000+0xD0)&0x0C)==0x04)) group.byte 0xD0++0x00 line.byte 0x00 "ENDPT4,Endpoint Control Register 4" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " EP_STALL ,Endpoint stall" "Not stalled,Stalled" bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" else group.byte 0xD0++0x00 line.byte 0x00 "ENDPT4,Endpoint Control Register 4" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" endif if (((per.b(ad:0x40072000+0xD4)&0x0C)==0x0C)) group.byte 0xD4++0x00 line.byte 0x00 "ENDPT5,Endpoint Control Register 5" bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (SETUP) transfers disable" "No,Yes" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " EP_STALL ,Endpoint stall" "Not stalled,Stalled" bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" elif (((per.b(ad:0x40072000+0xD4)&0x0C)==0x08)||((per.b(ad:0x40072000+0xD4)&0x0C)==0x04)) group.byte 0xD4++0x00 line.byte 0x00 "ENDPT5,Endpoint Control Register 5" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " EP_STALL ,Endpoint stall" "Not stalled,Stalled" bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" else group.byte 0xD4++0x00 line.byte 0x00 "ENDPT5,Endpoint Control Register 5" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" endif if (((per.b(ad:0x40072000+0xD8)&0x0C)==0x0C)) group.byte 0xD8++0x00 line.byte 0x00 "ENDPT6,Endpoint Control Register 6" bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (SETUP) transfers disable" "No,Yes" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " EP_STALL ,Endpoint stall" "Not stalled,Stalled" bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" elif (((per.b(ad:0x40072000+0xD8)&0x0C)==0x08)||((per.b(ad:0x40072000+0xD8)&0x0C)==0x04)) group.byte 0xD8++0x00 line.byte 0x00 "ENDPT6,Endpoint Control Register 6" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " EP_STALL ,Endpoint stall" "Not stalled,Stalled" bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" else group.byte 0xD8++0x00 line.byte 0x00 "ENDPT6,Endpoint Control Register 6" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" endif if (((per.b(ad:0x40072000+0xDC)&0x0C)==0x0C)) group.byte 0xDC++0x00 line.byte 0x00 "ENDPT7,Endpoint Control Register 7" bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (SETUP) transfers disable" "No,Yes" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " EP_STALL ,Endpoint stall" "Not stalled,Stalled" bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" elif (((per.b(ad:0x40072000+0xDC)&0x0C)==0x08)||((per.b(ad:0x40072000+0xDC)&0x0C)==0x04)) group.byte 0xDC++0x00 line.byte 0x00 "ENDPT7,Endpoint Control Register 7" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " EP_STALL ,Endpoint stall" "Not stalled,Stalled" bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" else group.byte 0xDC++0x00 line.byte 0x00 "ENDPT7,Endpoint Control Register 7" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" endif if (((per.b(ad:0x40072000+0xE0)&0x0C)==0x0C)) group.byte 0xE0++0x00 line.byte 0x00 "ENDPT8,Endpoint Control Register 8" bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (SETUP) transfers disable" "No,Yes" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " EP_STALL ,Endpoint stall" "Not stalled,Stalled" bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" elif (((per.b(ad:0x40072000+0xE0)&0x0C)==0x08)||((per.b(ad:0x40072000+0xE0)&0x0C)==0x04)) group.byte 0xE0++0x00 line.byte 0x00 "ENDPT8,Endpoint Control Register 8" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " EP_STALL ,Endpoint stall" "Not stalled,Stalled" bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" else group.byte 0xE0++0x00 line.byte 0x00 "ENDPT8,Endpoint Control Register 8" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" endif if (((per.b(ad:0x40072000+0xE4)&0x0C)==0x0C)) group.byte 0xE4++0x00 line.byte 0x00 "ENDPT9,Endpoint Control Register 9" bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (SETUP) transfers disable" "No,Yes" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " EP_STALL ,Endpoint stall" "Not stalled,Stalled" bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" elif (((per.b(ad:0x40072000+0xE4)&0x0C)==0x08)||((per.b(ad:0x40072000+0xE4)&0x0C)==0x04)) group.byte 0xE4++0x00 line.byte 0x00 "ENDPT9,Endpoint Control Register 9" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " EP_STALL ,Endpoint stall" "Not stalled,Stalled" bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" else group.byte 0xE4++0x00 line.byte 0x00 "ENDPT9,Endpoint Control Register 9" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" endif if (((per.b(ad:0x40072000+0xE8)&0x0C)==0x0C)) group.byte 0xE8++0x00 line.byte 0x00 "ENDPT10,Endpoint Control Register 10" bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (SETUP) transfers disable" "No,Yes" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " EP_STALL ,Endpoint stall" "Not stalled,Stalled" bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" elif (((per.b(ad:0x40072000+0xE8)&0x0C)==0x08)||((per.b(ad:0x40072000+0xE8)&0x0C)==0x04)) group.byte 0xE8++0x00 line.byte 0x00 "ENDPT10,Endpoint Control Register 10" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " EP_STALL ,Endpoint stall" "Not stalled,Stalled" bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" else group.byte 0xE8++0x00 line.byte 0x00 "ENDPT10,Endpoint Control Register 10" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" endif if (((per.b(ad:0x40072000+0xEC)&0x0C)==0x0C)) group.byte 0xEC++0x00 line.byte 0x00 "ENDPT11,Endpoint Control Register 11" bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (SETUP) transfers disable" "No,Yes" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " EP_STALL ,Endpoint stall" "Not stalled,Stalled" bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" elif (((per.b(ad:0x40072000+0xEC)&0x0C)==0x08)||((per.b(ad:0x40072000+0xEC)&0x0C)==0x04)) group.byte 0xEC++0x00 line.byte 0x00 "ENDPT11,Endpoint Control Register 11" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " EP_STALL ,Endpoint stall" "Not stalled,Stalled" bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" else group.byte 0xEC++0x00 line.byte 0x00 "ENDPT11,Endpoint Control Register 11" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" endif if (((per.b(ad:0x40072000+0xF0)&0x0C)==0x0C)) group.byte 0xF0++0x00 line.byte 0x00 "ENDPT12,Endpoint Control Register 12" bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (SETUP) transfers disable" "No,Yes" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " EP_STALL ,Endpoint stall" "Not stalled,Stalled" bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" elif (((per.b(ad:0x40072000+0xF0)&0x0C)==0x08)||((per.b(ad:0x40072000+0xF0)&0x0C)==0x04)) group.byte 0xF0++0x00 line.byte 0x00 "ENDPT12,Endpoint Control Register 12" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " EP_STALL ,Endpoint stall" "Not stalled,Stalled" bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" else group.byte 0xF0++0x00 line.byte 0x00 "ENDPT12,Endpoint Control Register 12" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" endif if (((per.b(ad:0x40072000+0xF4)&0x0C)==0x0C)) group.byte 0xF4++0x00 line.byte 0x00 "ENDPT13,Endpoint Control Register 13" bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (SETUP) transfers disable" "No,Yes" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " EP_STALL ,Endpoint stall" "Not stalled,Stalled" bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" elif (((per.b(ad:0x40072000+0xF4)&0x0C)==0x08)||((per.b(ad:0x40072000+0xF4)&0x0C)==0x04)) group.byte 0xF4++0x00 line.byte 0x00 "ENDPT13,Endpoint Control Register 13" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " EP_STALL ,Endpoint stall" "Not stalled,Stalled" bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" else group.byte 0xF4++0x00 line.byte 0x00 "ENDPT13,Endpoint Control Register 13" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" endif if (((per.b(ad:0x40072000+0xF8)&0x0C)==0x0C)) group.byte 0xF8++0x00 line.byte 0x00 "ENDPT14,Endpoint Control Register 14" bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (SETUP) transfers disable" "No,Yes" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " EP_STALL ,Endpoint stall" "Not stalled,Stalled" bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" elif (((per.b(ad:0x40072000+0xF8)&0x0C)==0x08)||((per.b(ad:0x40072000+0xF8)&0x0C)==0x04)) group.byte 0xF8++0x00 line.byte 0x00 "ENDPT14,Endpoint Control Register 14" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " EP_STALL ,Endpoint stall" "Not stalled,Stalled" bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" else group.byte 0xF8++0x00 line.byte 0x00 "ENDPT14,Endpoint Control Register 14" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" endif if (((per.b(ad:0x40072000+0xFC)&0x0C)==0x0C)) group.byte 0xFC++0x00 line.byte 0x00 "ENDPT15,Endpoint Control Register 15" bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (SETUP) transfers disable" "No,Yes" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " EP_STALL ,Endpoint stall" "Not stalled,Stalled" bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" elif (((per.b(ad:0x40072000+0xFC)&0x0C)==0x08)||((per.b(ad:0x40072000+0xFC)&0x0C)==0x04)) group.byte 0xFC++0x00 line.byte 0x00 "ENDPT15,Endpoint Control Register 15" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " EP_STALL ,Endpoint stall" "Not stalled,Stalled" bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" else group.byte 0xFC++0x00 line.byte 0x00 "ENDPT15,Endpoint Control Register 15" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" endif tree.end newline sif cpuis("MK28FN2M0CAU15R")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") if ((per.b(ad:0x40072000+0x100)&0x10)==0x10) group.byte 0x100++0x00 line.byte 0x00 "USBCTRL,USB Control Register" bitfld.byte 0x00 7. " SUSP ,USB transceiver suspend state" "Not suspended,Suspended" bitfld.byte 0x00 6. " PDE ,USB transceiver weak pull-downs enable" "Disabled,Enabled" newline bitfld.byte 0x00 4. " UARTSEL ,Selects USB signals to be used as UART signals" "Not used,Used" else group.byte 0x100++0x00 line.byte 0x00 "USBCTRL,USB Control Register" bitfld.byte 0x00 7. " SUSP ,USB transceiver suspend state" "Not suspended,Suspended" bitfld.byte 0x00 6. " PDE ,USB transceiver weak pull-downs enable" "Disabled,Enabled" newline bitfld.byte 0x00 5. " UARTCHLS ,UART signal channel select (USB DP/DM signals)" "UART TX/RX,UART RX/TX" bitfld.byte 0x00 4. " UARTSEL ,Selects USB signals to be used as UART signals" "Not used,Used" endif else group.byte 0x100++0x00 line.byte 0x00 "USBCTRL,USB Control Register" bitfld.byte 0x00 7. " SUSP ,USB transceiver suspend state" "Not suspended,Suspended" bitfld.byte 0x00 6. " PDE ,USB transceiver weak pull-downs enable" "Disabled,Enabled" sif !cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK21FX512VMD10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK20DX256VLK7R")&&!cpuis("MK20DX256VMC7R")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK22FX512AVLK12")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK70FN1M0VMJ1*")&&!cpuis("MK22FN128CAH12R")&&!cpuis("MK22FN256CAH12R")&&!cpuis("MK22FN256CAP12R")&&!cpuis("MK22FN256VMP12")&&!cpuis("MK22FN512CAP12R")&&!cpuis("MK22FN512CBP12R")&&!cpuis("MK22FN512VDC12")&&!cpuis("MK22FN512VLH12")&&!cpuis("MK22FN512VLL12")&&!cpuis("MK22FN512VMP12")&&!cpuis("MK22FN1M0VMC10")&&!cpuis("MK20DN32VEX5")&&!cpuis("MK20DN64VEX5")&&!cpuis("MK20DN128VEX5")&&!cpuis("MK20DX32VEX5")&&!cpuis("MK20DX64VEX5")&&!cpuis("MK20DX128VEX5")&&!cpuis("MK20DX64VEX7")&&!cpuis("MK20DX128VEX7")&&!cpuis("MK20DX256VEX7")&&!cpuis("MK20DX64VMB7")&&!cpuis("MK20DX128VMB7")&&!cpuis("MK20DX256VMB7")&&!cpuis("MK24FN1M0CAJ12R")&&!cpuis("MK24FN1M0VDC12R")&&!cpuis("MK24FN1M0VLL12")&&!cpuis("MK24FN1M0VLL12R")&&!cpuis("MK24FN1M0VLQ12R")&&!cpuis("MK24FN256VDC12")&&!cpuis("MK40*Z*10")&&!cpuis("MK66FN2M0VLQ18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("MK65FN2M0CAC18R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60FN1M0VLQ15")&&!cpuis("MK60DN512ZCAB10R")&&!cpuis("MK20D????ZVLQ10*")&&!cpuis("MK20D????ZVMD10")&&!cpuis("MK20D????ZVLL10")&&!cpuis("MK20DN512ZVMC10*")&&!cpuis("MK20D????ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK21D*AVMC5R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("KK22FN???C?P12R")&&!cpuis("MK22FN512VDC12*")&&!cpuis("MK22FN512VFX12*")&&!cpuis("MK22FN512VLH12R")&&!cpuis("KK22FN???CAH12R")&&!cpuis("MK22FN256VLL12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK22FN128VLH10R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("KK26FN2M0CAC18R")&&!cpuis("MK50DN512ZCLL10")&&!cpuis("MK50DX256ZCLL10")&&!cpuis("MK50DN512ZCLQ10")&&!cpuis("MK50DX256ZCLQ10")&&!cpuis("MK51DN512ZCLL10")&&!cpuis("MK51DN512ZCMC10")&&!cpuis("MK51DX256ZCMC10")&&!cpuis("MK51DN256ZCMD10")&&!cpuis("MK51DN512ZCLQ10")&&!cpuis("MK52DN512ZCLQ10")&&!cpuis("MK52DN512ZCMD10")&&!cpuis("MK53DN512ZCLQ10")&&!cpuis("MK53DN512ZCMD10")&&!cpuis("MK53DX256ZCLQ10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("KK60FN1M0VLQ15")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("KK65FN2M0CAC18R") newline bitfld.byte 0x00 5. " UARTCHLS ,UART signal channel select (USB DP/DM signals)" "UART TX/RX,UART RX/TX" bitfld.byte 0x00 4. " UARTSEL ,Selects USB signals to be used as UART signals" "Not used,Used" endif endif rgroup.byte 0x104++0x00 line.byte 0x00 "OBSERVE,USB OTG Observe Register" bitfld.byte 0x00 7. " DP_PU ,D+ Pull up signal output observability" "Disabled,Enabled" bitfld.byte 0x00 6. " DP_PD ,D+ Pull down signal output observability" "Disabled,Enabled" bitfld.byte 0x00 4. " DM_PD ,D- Pull down signal output observability" "Disabled,Enabled" group.byte 0x108++0x00 line.byte 0x00 "CONTROL,USB OTG Control Register" bitfld.byte 0x00 4. " DPPULLUP_NONOTG ,DP Pull up in the USB OTG control" "Disabled,Enabled" sif (cpuis("MK6*"))||cpuis("MK22FN256*")||cpuis("MK22FN128*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FX512AVLH12R")||cpuis("KK26FN2M0CAC18R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") group.byte 0x10C++0x00 line.byte 0x00 "USBTRC0,USB Transceiver Control Register 0" bitfld.byte 0x00 7. " USBRESET ,USB_OTG module hard reset" "No reset,Reset" bitfld.byte 0x00 5. " USBRESMEN ,Asynchronous resume interrupt enable" "Disabled,Enabled" sif !cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60FN1M0VLQ15")&&!cpuis("KK60DN512ZCAB10R") rbitfld.byte 0x00 2. " USB_CLK_RECOVERY_INT ,Combined USB clock recovery interrupt status" "No interrupt,Interrupt" endif newline rbitfld.byte 0x00 1. " SYNC_DET ,Synchronous USB interrupt detect" "Not detected,Detected" rbitfld.byte 0x00 0. " USB_RESUME_INT ,USB asynchronous interrupt" "No interrupt,Interrupt" elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK28FN2M0CAU15R")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK27FN2M0VMI15")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12") if ((per.b(ad:0x40072000+0x12C)&0x18)==0x18) group.byte 0x10C++0x00 line.byte 0x00 "USBTRC0,USB Transceiver Control Register 0" bitfld.byte 0x00 7. " USBRESET ,USB_OTG module hard reset" "No reset,Reset" bitfld.byte 0x00 5. " USBRESMEN ,Asynchronous resume interrupt enable" "Disabled,Enabled" newline rbitfld.byte 0x00 4. " VFEDG_DET ,VREGIN falling edge interrupt detect" "Not detected,Detected" rbitfld.byte 0x00 3. " VREDG_DET ,VREGIN rising edge interrupt detect" "Not detected,Detected" newline rbitfld.byte 0x00 2. " USB_CLK_RECOVERY_INT ,Combined USB clock recovery interrupt status" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " SYNC_DET ,Synchronous USB interrupt detect" "Not detected,Detected" newline rbitfld.byte 0x00 0. " USB_RESUME_INT ,USB asynchronous interrupt" "No interrupt,Interrupt" elif ((per.b(ad:0x40072000+0x12C)&0x18)==0x10) group.byte 0x10C++0x00 line.byte 0x00 "USBTRC0,USB Transceiver Control Register 0" bitfld.byte 0x00 7. " USBRESET ,USB_OTG module hard reset" "No reset,Reset" bitfld.byte 0x00 5. " USBRESMEN ,Asynchronous resume interrupt enable" "Disabled,Enabled" newline rbitfld.byte 0x00 4. " VFEDG_DET ,VREGIN falling edge interrupt detect" "Not detected,Detected" newline rbitfld.byte 0x00 2. " USB_CLK_RECOVERY_INT ,Combined USB clock recovery interrupt status" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " SYNC_DET ,Synchronous USB interrupt detect" "Not detected,Detected" newline rbitfld.byte 0x00 0. " USB_RESUME_INT ,USB asynchronous interrupt" "No interrupt,Interrupt" elif ((per.b(ad:0x40072000+0x12C)&0x18)==0x08) group.byte 0x10C++0x00 line.byte 0x00 "USBTRC0,USB Transceiver Control Register 0" bitfld.byte 0x00 7. " USBRESET ,USB_OTG module hard reset" "No reset,Reset" bitfld.byte 0x00 5. " USBRESMEN ,Asynchronous resume interrupt enable" "Disabled,Enabled" newline rbitfld.byte 0x00 3. " VREDG_DET ,VREGIN rising edge interrupt detect" "Not detected,Detected" newline rbitfld.byte 0x00 2. " USB_CLK_RECOVERY_INT ,Combined USB clock recovery interrupt status" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " SYNC_DET ,Synchronous USB interrupt detect" "Not detected,Detected" newline rbitfld.byte 0x00 0. " USB_RESUME_INT ,USB asynchronous interrupt" "No interrupt,Interrupt" else group.byte 0x10C++0x00 line.byte 0x00 "USBTRC0,USB Transceiver Control Register 0" bitfld.byte 0x00 7. " USBRESET ,USB_OTG module hard reset" "No reset,Reset" bitfld.byte 0x00 5. " USBRESMEN ,Asynchronous resume interrupt enable" "Disabled,Enabled" newline newline rbitfld.byte 0x00 2. " USB_CLK_RECOVERY_INT ,Combined USB clock recovery interrupt status" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " SYNC_DET ,Synchronous USB interrupt detect" "Not detected,Detected" newline rbitfld.byte 0x00 0. " USB_RESUME_INT ,USB asynchronous interrupt" "No interrupt,Interrupt" endif else group.byte 0x10C++0x00 line.byte 0x00 "USBTRC0,USB Transceiver Control Register 0" bitfld.byte 0x00 7. " USBRESET ,USB_OTG module hard reset" "No reset,Reset" bitfld.byte 0x00 5. " USBRESMEN ,Asynchronous resume interrupt enable" "Disabled,Enabled" newline rbitfld.byte 0x00 1. " SYNC_DET ,Synchronous USB interrupt detect" "Not detected,Detected" rbitfld.byte 0x00 0. " USB_RESUME_INT ,USB asynchronous interrupt" "No interrupt,Interrupt" endif newline width 14. sif cpuis("MK21D*AVLK5")||cpuis("MK21F*AVLQ12")||cpuis("MK21F*AVMD12")||cpuis("MK21D*AVMC5")||cpuis("MK21F*AVMC12")||cpuis("MK22FX512*")||cpuis("MK22FN256*")||cpuis("MK22FN128*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20DX256VLQ10R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK21FX512VMD10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FX512VMC10")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK60DN512VMC10R")||cpuis("MK60FN1M0VLQ15")||cpuis("MK60DN512ZCAB10R")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") sif cpuis("MK22FX512VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN128VLH10R")||cpuis("MK22FN256VLL12R") group.byte 0x114++0x00 line.byte 0x00 "USBFRMADJUST,Frame Adjust Register" else if ((per.b(ad:0x40072000+0x94)&0x08)==0x08) group.byte 0x114++0x00 line.byte 0x00 "USBFRMADJUST,Frame Adjust Register" else hgroup.byte 0x114++0x00 hide.byte 0x00 "USBFRMADJUST,Frame Adjust Register" endif endif elif !cpuis("MK?0DN*AB10")&&!cpuis("MK20DN512ZCAB10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK20D????ZVLL10")&&!cpuis("MK20D????ZVLQ10*")&&!cpuis("MK20D????ZVMD10")&&!cpuis("MK20DN512ZVMC10*")&&!cpuis("MK20D????ZVLK10")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("KK60DN512ZCAB10R") group.byte 0x114++0x00 line.byte 0x00 "USBFRMADJUST,Frame Adjust Register" endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("?K28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK27FN2M0VMI15") if ((per.b(ad:0x40072000+0x94)&0x08)==0x08) group.byte 0x12C++0x00 line.byte 0x00 "MISCCTRL,Miscellaneous Control register" bitfld.byte 0x00 4. " VFEDG_EN ,VREGIN falling edge interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 3. " VREDG_EN ,VREGIN rising edge interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 1. " SOFBUSSET ,SOF_TOK interrupt generation mode select" "SOF threshold value,Counter reaches 0" bitfld.byte 0x00 0. " SOFDYNTHLD ,Dynamic SOF threshold compare mode" "Byte time,8 byte times" else group.byte 0x12C++0x00 line.byte 0x00 "MISCCTRL,Miscellaneous Control register" bitfld.byte 0x00 4. " VFEDG_EN ,VREGIN falling edge interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 3. " VREDG_EN ,VREGIN rising edge interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 2. " OWNERRISODIS ,OWN error detect for ISO IN / ISO OUT disable" "No,Yes" endif elif cpuis("MKS2?FN???V??12") if ((per.b(ad:0x40072000+0x94)&0x08)==0x08) group.byte 0x12C++0x00 line.byte 0x00 "MISCCTRL,Miscellaneous Control register" bitfld.byte 0x00 7. " STL_ADJ_EN ,VREGIN falling edge interrupt enable" "Disabled,Enabled" newline bitfld.byte 0x00 4. " VFEDG_EN ,VREGIN falling edge interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 3. " VREDG_EN ,VREGIN rising edge interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 1. " SOFBUSSET ,SOF_TOK interrupt generation mode select" "SOF threshold value,Counter reaches 0" bitfld.byte 0x00 0. " SOFDYNTHLD ,Dynamic SOF threshold compare mode" "Byte time,8 byte times" else group.byte 0x12C++0x00 line.byte 0x00 "MISCCTRL,Miscellaneous Control register" bitfld.byte 0x00 4. " VFEDG_EN ,VREGIN falling edge interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 3. " VREDG_EN ,VREGIN rising edge interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 2. " OWNERRISODIS ,OWN error detect for ISO IN / ISO OUT disable" "No,Yes" endif endif newline width 18. sif cpuis("MKS2?FN???V??12") if (((per.b(ad:0x40072000+0x94)&0x8)!=0x8)&&((per.b(ad:0x40072000+0x12C)&0x80)==0x80)) group.byte 0x130++0x00 line.byte 0x00 "STALL_IL_DIS,Peripheral Mode Stall Disable For Endpoints 7 To 0 In IN Direction" bitfld.byte 0x00 7. " STALL_I_DIS7 ,Dynamic SOF threshold compare mode" "No,Yes" bitfld.byte 0x00 6. " STALL_I_DIS6 ,Dynamic SOF threshold compare mode" "No,Yes" bitfld.byte 0x00 5. " STALL_I_DIS5 ,Dynamic SOF threshold compare mode" "No,Yes" bitfld.byte 0x00 4. " STALL_I_DIS4 ,Dynamic SOF threshold compare mode" "No,Yes" newline bitfld.byte 0x00 3. " STALL_I_DIS3 ,Dynamic SOF threshold compare mode" "No,Yes" bitfld.byte 0x00 2. " STALL_I_DIS2 ,Dynamic SOF threshold compare mode" "No,Yes" bitfld.byte 0x00 1. " STALL_I_DIS1 ,Dynamic SOF threshold compare mode" "No,Yes" bitfld.byte 0x00 0. " STALL_I_DIS0 ,Dynamic SOF threshold compare mode" "No,Yes" group.byte 0x134++0x00 line.byte 0x00 "STALL_IH_DIS,Peripheral Mode Stall Disable For Endpoints 15 To 8 In IN Direction" bitfld.byte 0x00 7. " STALL_I_DIS15 ,Dynamic SOF threshold compare mode" "No,Yes" bitfld.byte 0x00 6. " STALL_I_DIS14 ,Dynamic SOF threshold compare mode" "No,Yes" bitfld.byte 0x00 5. " STALL_I_DIS13 ,Dynamic SOF threshold compare mode" "No,Yes" bitfld.byte 0x00 4. " STALL_I_DIS12 ,Dynamic SOF threshold compare mode" "No,Yes" newline bitfld.byte 0x00 3. " STALL_I_DIS11 ,Dynamic SOF threshold compare mode" "No,Yes" bitfld.byte 0x00 2. " STALL_I_DIS10 ,Dynamic SOF threshold compare mode" "No,Yes" bitfld.byte 0x00 1. " STALL_I_DIS9 ,Dynamic SOF threshold compare mode" "No,Yes" bitfld.byte 0x00 0. " STALL_I_DIS8 ,Dynamic SOF threshold compare mode" "No,Yes" group.byte 0x138++0x00 line.byte 0x00 "STALL_OL_DIS,Peripheral Mode Stall Disable For Endpoints 7 To 0 In OUT Direction" bitfld.byte 0x00 7. " STALL_O_DIS7 ,Dynamic SOF threshold compare mode" "No,Yes" bitfld.byte 0x00 6. " STALL_O_DIS6 ,Dynamic SOF threshold compare mode" "No,Yes" bitfld.byte 0x00 5. " STALL_O_DIS5 ,Dynamic SOF threshold compare mode" "No,Yes" bitfld.byte 0x00 4. " STALL_O_DIS4 ,Dynamic SOF threshold compare mode" "No,Yes" newline bitfld.byte 0x00 3. " STALL_O_DIS3 ,Dynamic SOF threshold compare mode" "No,Yes" bitfld.byte 0x00 2. " STALL_O_DIS2 ,Dynamic SOF threshold compare mode" "No,Yes" bitfld.byte 0x00 1. " STALL_O_DIS1 ,Dynamic SOF threshold compare mode" "No,Yes" bitfld.byte 0x00 0. " STALL_O_DIS0 ,Dynamic SOF threshold compare mode" "No,Yes" group.byte 0x13C++0x00 line.byte 0x00 "STALL_OH_DIS,Peripheral Mode Stall Disable For Endpoints 15 To 0 In OUT Direction" bitfld.byte 0x00 7. " STALL_O_DIS15 ,Dynamic SOF threshold compare mode" "No,Yes" bitfld.byte 0x00 6. " STALL_O_DIS14 ,Dynamic SOF threshold compare mode" "No,Yes" bitfld.byte 0x00 5. " STALL_O_DIS13 ,Dynamic SOF threshold compare mode" "No,Yes" bitfld.byte 0x00 4. " STALL_O_DIS12 ,Dynamic SOF threshold compare mode" "No,Yes" newline bitfld.byte 0x00 3. " STALL_O_DIS11 ,Dynamic SOF threshold compare mode" "No,Yes" bitfld.byte 0x00 2. " STALL_O_DIS10 ,Dynamic SOF threshold compare mode" "No,Yes" bitfld.byte 0x00 1. " STALL_O_DIS9 ,Dynamic SOF threshold compare mode" "No,Yes" bitfld.byte 0x00 0. " STALL_O_DIS8 ,Dynamic SOF threshold compare mode" "No,Yes" endif endif newline width 28. sif !cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DN512ZCAB10R")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("KK60FN1M0VLQ15")&&!cpuis("KK60DN512ZCAB10R") sif cpuis("MK6*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK27FN2M0VMI15")||cpuis("?K28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") group.byte 0x140++0x00 line.byte 0x00 "CLK_RECOVER_CTRL,USB Clock Recovery Control Register" bitfld.byte 0x00 7. " CLOCK_RECOVER_EN ,Crystal-less USB enable" "Disabled,Enabled" bitfld.byte 0x00 6. " RESET_RESUME_ROUGH_EN ,Reset/resume to rough phase enable" "Resume,Reset" newline bitfld.byte 0x00 5. " RESTART_IFRTRIM_EN ,Restart from IFR trim value" "No effect,Restart" group.byte 0x144++0x00 line.byte 0x00 "CLK_RECOVER_IRC_EN,IRC48M Oscillator Enable Register" bitfld.byte 0x00 1. " IRC_EN ,IRC48M enable" "Disabled,Enabled" bitfld.byte 0x00 0. " REG_EN ,IRC48M regulator enable" "Disabled,Enabled" sif !cpuis("MK63F*")&&!cpuis("MK64F*") group.byte 0x154++0x00 line.byte 0x00 "CLK_RECOVER_INT_EN,Clock Recovery Combined Interrupt Enable Register" bitfld.byte 0x00 4. " OVF_ERROR_EN ,Determines whether OVF_ERROR condition signal is used in generation of USB_CLK_RECOVERY_INT" "Disabled,Enabled" elif cpuis("MK63FN1M0VLQ12R") group.byte 0x154++0x00 line.byte 0x00 "CLK_RECOVER_INT_EN,Clock Recovery Combined Interrupt Enable Register" bitfld.byte 0x00 4. " OVF_ERROR_EN ,Determines whether OVF_ERROR condition signal is used in generation of USB_CLK_RECOVERY_INT" "Disabled,Enabled" endif sif cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK27FN2M0VMI15")||cpuis("?K28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") group.byte 0x15C++0x00 line.byte 0x00 "CLK_RECOVER_INT_STATUS,Clock Recovery Separated Interrupt Status Register" eventfld.byte 0x00 4. " OVF_ERROR ,USB clock recovery error flag" "No interrupt,Interrupt" else hgroup.byte 0x15C++0x00 hide.byte 0x00 "CLK_RECOVER_INT_STATUS,Clock Recovery Separated Interrupt Status Register" in endif elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MKS2?FN???V??12")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VFX12*")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN???C?P12R")||cpuis("KK22FN???CAH12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK22FN128*")||cpuis("MK22FN256*") if ((per.b(ad:0x40072000+0x144)&0x02)==0x02) group.byte 0x140++0x00 line.byte 0x00 "CLK_RECOVER_CTRL,USB Clock Recovery Control Register" bitfld.byte 0x00 7. " CLOCK_RECOVER_EN ,Crystal-less USB enable" "Disabled,Enabled" bitfld.byte 0x00 6. " RESET_RESUME_ROUGH_EN ,Reset/resume to rough phase enable" "Resume,Reset" newline bitfld.byte 0x00 5. " RESTART_IFRTRIM_EN ,Restart from IFR trim value" "No effect,Restart" else hgroup.byte 0x140++0x00 hide.byte 0x00 "CLK_RECOVER_CTRL,USB Clock Recovery Control Register" endif group.byte 0x144++0x00 line.byte 0x00 "CLK_RECOVER_IRC_EN,IRC48M Oscillator Enable Register" bitfld.byte 0x00 1. " IRC_EN ,IRC48M enable" "Disabled,Enabled" bitfld.byte 0x00 0. " REG_EN ,IRC48M regulator enable" "Disabled,Enabled" group.byte 0x154++0x00 line.byte 0x00 "CLK_RECOVER_INT_EN,Clock Recovery Combined Interrupt Enable Register" bitfld.byte 0x00 4. " OVF_ERROR_EN ,Determines whether OVF_ERROR condition signal is used in generation of USB_CLK_RECOVERY_INT" "Disabled,Enabled" group.byte 0x15C++0x00 line.byte 0x00 "CLK_RECOVER_INT_STATUS,Clock Recovery Separated Interrupt Status Register" eventfld.byte 0x00 4. " OVF_ERROR ,USB clock recovery error flag" "No interrupt,Interrupt" endif endif width 0x0B tree.end tree "USBDCD (USB Device Charger Detection Module)" base ad:0x40035000 width 9. group.long 0x00++0x07 line.long 0x00 "CONTROL,USBDCD Control Register" bitfld.long 0x00 25. " SR ,Software reset" "No reset,Reset" bitfld.long 0x00 24. " START ,Start change detection sequence" "No start,Start" newline sif !cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60FN1M0VLQ15")&&!cpuis("MK60DN512ZCAB10R")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("KK60FN1M0VLQ15")&&!cpuis("KK60DN512ZCAB10R") sif cpuis("MK6*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 17. " BC12 ,BC1.2 compatibility" "BC1.1,BC1.2" newline endif endif bitfld.long 0x00 16. " IE ,Interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 8. " IF ,Interrupt flag" "Not pending,Pending" bitfld.long 0x00 0. " IACK ,Interrupt acknowledge" "No effect,Clear" line.long 0x04 "CLOCK,USBDCD Clock Register" hexmask.long.word 0x04 2.--11. 1. " CLOCK_SPEED ,Numerical value of clock speed in binary" bitfld.long 0x04 0. " CLOCK_UNIT ,Unit of measurement encoding for clock speed" "kHz,MHz" newline rgroup.long 0x08++0x03 line.long 0x00 "STATUS,USBDCD Status Register" bitfld.long 0x00 22. " ACTIVE ,Active status indicator" "Not running,Running" bitfld.long 0x00 21. " TO ,Timeout flag" "No timeout,Timeout" newline bitfld.long 0x00 20. " ERR ,Error flag" "No error,Error" newline bitfld.long 0x00 18.--19. " SEQ_STAT ,Charger detection sequence status" "Disabled / Data pins not detected,Data pin contact detection completed,Charger detection completed,Charger type detection completed" newline bitfld.long 0x00 16.--17. " SEQ_RES ,Charger detection sequence results" "No results,Standard host,Charging port,Dedicated charger" newline sif !cpuis("MK63*")&&!cpuis("MK64*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60FN1M0VLQ15")&&!cpuis("MK60DN512ZCAB10R")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15")&&!cpuis("MK60DN512ZVLL10") sif cpuis("MK6*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("KK65FN2M0CAC18R") width 17. group.long 0x0C++0x03 line.long 0x00 "SIGNAL_OVERRIDE,Signal Override Register" bitfld.long 0x00 0.--1. " PS ,Phase selection" "No overrides,,VDP_SRC enabled,?..." newline endif endif width 13. group.long 0x10++0x07 line.long 0x00 "TIMER0,USBDCD TIMER0 Register" hexmask.long.word 0x00 16.--25. 1. " TSEQ_INIT ,Sequence initiation time (in ms)" hexmask.long.word 0x00 0.--11. 1. " TUNIT_CON ,Unit connection timer elapse (in ms)" line.long 0x04 "TIMER1,USBDCD TIMER1 Register" hexmask.long.word 0x04 16.--25. 1. " TDCD_DBNC ,Time period to debounce D+ signal (in ms)" hexmask.long.word 0x04 0.--9. 1. " TVDPSRC_ON ,Time period comparator enabled (in ms)" sif !cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60FN1M0VLQ15")&&!cpuis("MK60DN512ZCAB10R")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("KK60FN1M0VLQ15")&&!cpuis("KK60DN512ZCAB10R") sif (cpuis("MK6*"))||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("KK65FN2M0CAC18R") if (((per.l(ad:0x40035000+0x00))&0x20000)==0x20000) group.long 0x18++0x03 line.long 0x00 "TIMER2_BC12,USBDCD TIMER2_BC12 Register" hexmask.long.word 0x00 16.--25. 1. " TWAIT_AFTER_PRD ,Sets the amount of time (in ms) that the module waits after primary detection before start to secondary detection" hexmask.long.word 0x00 0.--9. 1. " TVDMSRC_ON ,Sets the amount of time (in ms) that the module enables the V DM_SRC" else group.long 0x18++0x03 line.long 0x00 "TIMER2_BC11,USBDCD TIMER2_BC11 Register" hexmask.long.word 0x00 16.--25. 1. " TVDPSRC_CON ,Time period before enabling D+ pull-up (in ms)" bitfld.long 0x00 0.--3. " CHECK_DM ,Time before check of D- line (in ms)" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else group.long 0x18++0x03 line.long 0x00 "TIMER2,USBDCD TIMER2 Register" hexmask.long.word 0x00 16.--25. 1. " TVDPSRC_CON ,Time period before enabling d+ pull-up (in ms)" bitfld.long 0x00 0.--3. " CHECK_DM ,Time before check of D- line (in ms)" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else group.long 0x18++0x03 line.long 0x00 "TIMER2,USBDCD TIMER2 Register" hexmask.long.word 0x00 16.--25. 1. " TVDPSRC_CON ,Time period before enabling d+ pull-up (in ms)" bitfld.long 0x00 0.--3. " CHECK_DM ,Time before check of D- line (in ms)" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif width 0x0B tree.end tree.open "SPI (Serial Peripheral Interface)" tree "SPI_0" base ad:0x4002C000 width 19. sif cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK40DN512ZVLL10") if (((per.l(ad:0x4002C000+0x0C))&0x2000000)==0x0000000)&&(((per.l(ad:0x4002C000+0x10))&0x2000000)==0x0000000) if ((per.l(ad:0x4002C000)&0x80000000)==0x80000000) if ((per.l(ad:0x4002C000)&0x4000)==0x4000) group.long 0x00++0x03 line.long 0x00 "MCR,DSPI0 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI0 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline bitfld.long 0x00 21. " PCSIS5 ,Peripheral chip select 5 inactive state" "Low,High" bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 4 inactive state" "Low,High" newline bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" sif cpuis("MK40DN512ZVLL10") bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" endif newline bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" newline rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0,1,2,?..." newline bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" else group.long 0x00++0x03 line.long 0x00 "MCR,DSPI0 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI0 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline bitfld.long 0x00 21. " PCSIS5 ,Peripheral chip select 5 inactive state" "Low,High" bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 4 inactive state" "Low,High" newline bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" sif cpuis("MK40DN512ZVLL10") bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" endif newline bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" newline bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0,1,2,?..." newline bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" endif else if ((per.l(ad:0x4002C000)&0x4000)==0x4000) group.long 0x00++0x03 line.long 0x00 "MCR,DSPI0 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI0 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" newline bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0,1,2,?..." bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" else group.long 0x00++0x03 line.long 0x00 "MCR,DSPI0 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI0 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" newline bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0,1,2,?..." bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" endif endif else if ((per.l(ad:0x4002C000)&0x80000000)==0x80000000) if ((per.l(ad:0x4002C000)&0x4000)==0x4000) group.long 0x00++0x03 line.long 0x00 "MCR,DSPI0 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI0 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline bitfld.long 0x00 21. " PCSIS5 ,Peripheral chip select 5 inactive state" "Low,High" bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 4 inactive state" "Low,High" newline bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" sif cpuis("MK40DN512ZVLL10") bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" endif newline bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" newline bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" else group.long 0x00++0x03 line.long 0x00 "MCR,DSPI0 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI0 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline bitfld.long 0x00 21. " PCSIS5 ,Peripheral chip select 5 inactive state" "Low,High" bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 4 inactive state" "Low,High" newline bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" sif cpuis("MK40DN512ZVLL10") bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" endif newline bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" newline rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" endif else if ((per.l(ad:0x4002C000)&0x4000)==0x4000) group.long 0x00++0x03 line.long 0x00 "MCR,DSPI0 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI0 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" newline bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" else group.long 0x00++0x03 line.long 0x00 "MCR,DSPI0 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI0 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" newline bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" endif endif endif elif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") if (((per.l(ad:0x4002C000+0x2C))&0x40000000)==0x40000000) if (((per.l(ad:0x4002C000+0x0C))&0x2000000)==0x0000000)&&(((per.l(ad:0x4002C000+0x10))&0x2000000)==0x0000000) group.long 0x00++0x03 line.long 0x00 "MCR,DSPI0 Module Configuration Register" rbitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" rbitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" rbitfld.long 0x00 28.--29. " DCONF ,DSPI0 configuration" "SPI,?..." rbitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline rbitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" sif !cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10") rbitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" endif newline rbitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline sif cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512VMC10R") rbitfld.long 0x00 20. " PCSIS[4] ,Peripheral chip select 4 inactive state" "Low,High" rbitfld.long 0x00 19. " [3] ,Peripheral chip select 3 inactive state" "Low,High" rbitfld.long 0x00 18. " [2] ,Peripheral chip select 2 inactive state" "Low,High" rbitfld.long 0x00 17. " [1] ,Peripheral chip select 1 inactive state" "Low,High" newline rbitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High" newline else rbitfld.long 0x00 21. " PCSIS[5] ,Peripheral chip select 5 inactive state" "Low,High" rbitfld.long 0x00 20. " [4] ,Peripheral chip select 4 inactive state" "Low,High" rbitfld.long 0x00 19. " [3] ,Peripheral chip select 3 inactive state" "Low,High" rbitfld.long 0x00 18. " [2] ,Peripheral chip select 2 inactive state" "Low,High" newline rbitfld.long 0x00 17. " [1] ,Peripheral chip select 1 inactive state" "Low,High" rbitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High" newline endif newline rbitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline rbitfld.long 0x00 11. " CLR_TXF ,Clear Tx FIFO" "No effect,Clear" rbitfld.long 0x00 10. " CLR_RXF ,Clear Rx FIFO" "No effect,Clear" rbitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 clocks,1 clock,2 clocks,?..." bitfld.long 0x00 0. " HALT ,Start/stop DSPI transfers" "Start,Stop" else group.long 0x00++0x03 line.long 0x00 "MCR,DSPI0 Module Configuration Register" rbitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" rbitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" rbitfld.long 0x00 28.--29. " DCONF ,DSPI0 configuration" "SPI,?..." rbitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline rbitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" sif !cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10") rbitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" endif newline rbitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline sif cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512VMC10R") rbitfld.long 0x00 20. " PCSIS[4] ,Peripheral chip select 4 inactive state" "Low,High" rbitfld.long 0x00 19. " [3] ,Peripheral chip select 3 inactive state" "Low,High" rbitfld.long 0x00 18. " [2] ,Peripheral chip select 2 inactive state" "Low,High" rbitfld.long 0x00 17. " [1] ,Peripheral chip select 1 inactive state" "Low,High" newline rbitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High" newline else rbitfld.long 0x00 21. " PCSIS[5] ,Peripheral chip select 5 inactive state" "Low,High" rbitfld.long 0x00 20. " [4] ,Peripheral chip select 4 inactive state" "Low,High" rbitfld.long 0x00 19. " [3] ,Peripheral chip select 3 inactive state" "Low,High" rbitfld.long 0x00 18. " [2] ,Peripheral chip select 2 inactive state" "Low,High" newline rbitfld.long 0x00 17. " [1] ,Peripheral chip select 1 inactive state" "Low,High" rbitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High" newline endif newline rbitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline rbitfld.long 0x00 11. " CLR_TXF ,Clear Tx FIFO" "No effect,Clear" rbitfld.long 0x00 10. " CLR_RXF ,Clear Rx FIFO" "No effect,Clear" bitfld.long 0x00 0. " HALT ,Start/stop DSPI transfers" "Start,Stop" endif else if (((per.l(ad:0x4002C000+0x0C))&0x2000000)==0x0000000)&&(((per.l(ad:0x4002C000+0x10))&0x2000000)==0x0000000) if ((per.l(ad:0x4002C000)&0x4000)==0x4000) group.long 0x00++0x03 line.long 0x00 "MCR,DSPI0 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI0 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" sif !cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10") bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" endif newline bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline sif cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512VMC10R") bitfld.long 0x00 20. " PCSIS[4] ,Peripheral chip select 4 inactive state" "Low,High" bitfld.long 0x00 19. " [3] ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " [2] ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " [1] ,Peripheral chip select 1 inactive state" "Low,High" newline bitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High" newline else bitfld.long 0x00 21. " PCSIS[5] ,Peripheral chip select 5 inactive state" "Low,High" bitfld.long 0x00 20. " [4] ,Peripheral chip select 4 inactive state" "Low,High" bitfld.long 0x00 19. " [3] ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " [2] ,Peripheral chip select 2 inactive state" "Low,High" newline bitfld.long 0x00 17. " [1] ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High" newline endif newline bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Clear Tx FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear Rx FIFO" "No effect,Clear" bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 clocks,1 clock,2 clocks,?..." bitfld.long 0x00 0. " HALT ,Start/stop DSPI transfers" "Start,Stop" else group.long 0x00++0x03 line.long 0x00 "MCR,DSPI0 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI0 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" sif !cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10") bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" endif newline bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline sif cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512VMC10R") bitfld.long 0x00 20. " PCSIS[4] ,Peripheral chip select 4 inactive state" "Low,High" bitfld.long 0x00 19. " [3] ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " [2] ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " [1] ,Peripheral chip select 1 inactive state" "Low,High" newline bitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High" newline else bitfld.long 0x00 21. " PCSIS[5] ,Peripheral chip select 5 inactive state" "Low,High" bitfld.long 0x00 20. " [4] ,Peripheral chip select 4 inactive state" "Low,High" bitfld.long 0x00 19. " [3] ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " [2] ,Peripheral chip select 2 inactive state" "Low,High" newline bitfld.long 0x00 17. " [1] ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High" newline endif newline bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Clear Tx FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear Rx FIFO" "No effect,Clear" bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 clocks,1 clock,2 clocks,?..." bitfld.long 0x00 0. " HALT ,Start/stop DSPI transfers" "Start,Stop" endif else if ((per.l(ad:0x4002C000)&0x4000)==0x4000) group.long 0x00++0x03 line.long 0x00 "MCR,DSPI0 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI0 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" sif !cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10") bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" endif newline bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline sif cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512VMC10R") bitfld.long 0x00 20. " PCSIS[4] ,Peripheral chip select 4 inactive state" "Low,High" bitfld.long 0x00 19. " [3] ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " [2] ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " [1] ,Peripheral chip select 1 inactive state" "Low,High" newline bitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High" newline else bitfld.long 0x00 21. " PCSIS[5] ,Peripheral chip select 5 inactive state" "Low,High" bitfld.long 0x00 20. " [4] ,Peripheral chip select 4 inactive state" "Low,High" bitfld.long 0x00 19. " [3] ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " [2] ,Peripheral chip select 2 inactive state" "Low,High" newline bitfld.long 0x00 17. " [1] ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High" newline endif newline bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Clear Tx FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear Rx FIFO" "No effect,Clear" bitfld.long 0x00 0. " HALT ,Start/stop DSPI transfers" "Start,Stop" else group.long 0x00++0x03 line.long 0x00 "MCR,DSPI0 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI0 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" sif !cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10") bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" endif newline bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline sif cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512VMC10R") bitfld.long 0x00 20. " PCSIS[4] ,Peripheral chip select 4 inactive state" "Low,High" bitfld.long 0x00 19. " [3] ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " [2] ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " [1] ,Peripheral chip select 1 inactive state" "Low,High" newline bitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High" newline else bitfld.long 0x00 21. " PCSIS[5] ,Peripheral chip select 5 inactive state" "Low,High" bitfld.long 0x00 20. " [4] ,Peripheral chip select 4 inactive state" "Low,High" bitfld.long 0x00 19. " [3] ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " [2] ,Peripheral chip select 2 inactive state" "Low,High" newline bitfld.long 0x00 17. " [1] ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High" newline endif newline bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Clear Tx FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear Rx FIFO" "No effect,Clear" bitfld.long 0x00 0. " HALT ,Start/stop DSPI transfers" "Start,Stop" endif endif endif else if (((per.l(ad:0x4002C000+0x0C))&0x2000000)==0x0000000)&&(((per.l(ad:0x4002C000+0x10))&0x2000000)==0x0000000) group.long 0x00++0x03 line.long 0x00 "MCR,DSPI0 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" newline sif cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK40DN512ZVLL10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZCAB10R")||cpuis("MK60FN1M0VLQ15") bitfld.long 0x00 28.--29. " DCONF ,DSPI0 configuration" "SPI,?..." newline else rbitfld.long 0x00 28.--29. " DCONF ,DSPI0 configuration" "SPI,?..." newline endif bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" newline sif cpuis("MK??F*")||(cpuis("MK30D????ZVLQ*"))||cpuis("MK30DN512ZVLK10")||cpuis("MK40DN512ZVLL10")||cpuis("MKL82*")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60FN1M0VLQ15") bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" newline endif bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline sif (cpuis("MK70*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")) bitfld.long 0x00 21. " PCSIS5 ,Peripheral chip select 5 inactive state" "Low,High" bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 4 inactive state" "Low,High" bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" newline bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" newline else sif cpuis("MKL82*") bitfld.long 0x00 21. " PCSIS5 ,Peripheral chip select 5 inactive state" "Low,High" bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 4 inactive state" "Low,High" newline else sif cpuis("MK??F*")||(cpuis("MK30D????ZVLQ*"))||cpuis("MK30DN512ZVLK10")||cpuis("MK40DN512ZVLL10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60FN1M0VLQ15") bitfld.long 0x00 21. " PCSIS5 ,Peripheral chip select 5 inactive state" "Low,High" newline endif bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 4 inactive state" "Low,High" newline endif bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" newline endif bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline sif cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10") rbitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" rbitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" newline else bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" newline endif bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0,1,2,?..." bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" else group.long 0x00++0x03 line.long 0x00 "MCR,DSPI0 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" newline sif cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK40DN512ZVLL10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZCAB10R")||cpuis("MK60FN1M0VLQ15") bitfld.long 0x00 28.--29. " DCONF ,DSPI0 configuration" "SPI,?..." newline else rbitfld.long 0x00 28.--29. " DCONF ,DSPI0 configuration" "SPI,?..." newline endif bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" newline sif cpuis("MK??F*")||(cpuis("MK30D????ZVLQ*"))||cpuis("MK30DN512ZVLK10")||cpuis("MK40DN512ZVLL10")||cpuis("MKL82*")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60FN1M0VLQ15") bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" newline endif bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline sif (cpuis("MK70*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")) bitfld.long 0x00 21. " PCSIS5 ,Peripheral chip select 5 inactive state" "Low,High" bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 4 inactive state" "Low,High" bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" newline bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" newline else sif cpuis("MKL82*") bitfld.long 0x00 21. " PCSIS5 ,Peripheral chip select 5 inactive state" "Low,High" bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 4 inactive state" "Low,High" newline else sif cpuis("MK??F*")||(cpuis("MK30D????ZVLQ*"))||cpuis("MK30DN512ZVLK10")||cpuis("MK40DN512ZVLL10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60FN1M0VLQ15") bitfld.long 0x00 21. " PCSIS5 ,Peripheral chip select 5 inactive state" "Low,High" newline endif bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 4 inactive state" "Low,High" newline endif bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" newline endif bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline sif cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10") rbitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" rbitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" newline else bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" newline endif bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" endif endif newline sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") if (((per.l(ad:0x4002C000+0x2C))&0x40000000)==0x40000000) rgroup.long 0x08++0x03 line.long 0x00 "TCR,DSPI0 Transfer Count Register" hexmask.long.word 0x00 16.--31. 1. " SPI_TCNT ,SPI transfer counter" else group.long 0x08++0x03 line.long 0x00 "TCR,DSPI0 Transfer Count Register" hexmask.long.word 0x00 16.--31. 1. " SPI_TCNT ,SPI transfer counter" endif else group.long 0x08++0x03 line.long 0x00 "TCR,DSPI0 Transfer Count Register" hexmask.long.word 0x00 16.--31. 1. " SPI_TCNT ,SPI transfer counter" endif sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60DN512ZCAB10R") if (((per.l(ad:0x4002C000+0x2C))&0x40000000)==0x40000000) if ((per.l(ad:0x4002C000)&0x80000000)==0x80000000) rgroup.long 0xC++0x03 line.long 0x00 "CTAR0,DSPI0 Clock and Transfer Attributes Register 0" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" newline bitfld.long 0x00 24. " LSBFE ,LBS First" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7" newline bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" newline bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" rgroup.long 0x10++0x03 line.long 0x00 "CTAR1,DSPI0 Clock and Transfer Attributes Register 1" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" newline bitfld.long 0x00 24. " LSBFE ,LBS First" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7" newline bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" newline bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" else rgroup.long 0x0C++0x03 line.long 0x00 "CTAR0_SLAVE,DSPI0 Clock and Transfer Attributes Register (In Slave Mode)" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Low,High" bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" endif else if ((per.l(ad:0x4002C000)&0x80000000)==0x80000000) group.long 0xC++0x03 line.long 0x00 "CTAR0,DSPI0 Clock and Transfer Attributes Register 0" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" newline bitfld.long 0x00 24. " LSBFE ,LBS First" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7" newline bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" newline bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" group.long 0x10++0x03 line.long 0x00 "CTAR1,DSPI0 Clock and Transfer Attributes Register 1" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" newline bitfld.long 0x00 24. " LSBFE ,LBS First" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7" newline bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" newline bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" else group.long 0x0C++0x03 line.long 0x00 "CTAR0_SLAVE,DSPI0 Clock and Transfer Attributes Register (In Slave Mode)" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Low,High" bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" endif endif else if ((per.l(ad:0x4002C000)&0x80000000)==0x80000000) group.long 0xC++0x03 line.long 0x00 "CTAR0,DSPI0 Clock and Transfer Attributes Register 0" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" newline bitfld.long 0x00 24. " LSBFE ,LBS First" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7" newline bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" newline bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" group.long 0x10++0x03 line.long 0x00 "CTAR1,DSPI0 Clock and Transfer Attributes Register 1" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" newline bitfld.long 0x00 24. " LSBFE ,LBS First" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7" newline bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" newline bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" else group.long 0x0C++0x03 line.long 0x00 "CTAR0_SLAVE,DSPI0 Clock and Transfer Attributes Register 0" sif cpuis("MKL82*") bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" newline else bitfld.long 0x00 27.--31. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline endif bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" sif !cpuis("MK8?FN256V*")&&!cpuis("MK40DN512ZVLL10")&&!cpuis("MKL82*")&&!cpuis("MK40DN512ZVLQ10")&&!cpuis("MK40DN512ZVMD10")&&!cpuis("MK40DX128ZVLQ10")&&!cpuis("MK40DX256ZVLQ10")&&!cpuis("MK40DX256ZVMD10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512VMC10R") sif cpuis("MK60DN512ZCAB10R")||cpuis("MK60FN1M0VLQ15")||cpuis("MK60DN512ZVLQ10R") hgroup.long 0x10++0x03 hide.long 0x00 "CTAR1_SLAVE,DSPI0 Clock and Transfer Attributes Register 1" endif endif endif endif group.long 0x2C++0x03 line.long 0x00 "SR,DSPI0 Status Register" eventfld.long 0x00 31. " TCF ,Transfer complete flag" "Not completed,Completed" sif cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*")||cpuis("MK30DX256VLL7*")||cpuis("MK70*")||cpuis("MK40DN512ZVLL10")||cpuis("MKL82*")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK60FN1M0VLQ15")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK8?FN256V*") newline eventfld.long 0x00 30. " TXRXS ,TX and RX status" "Disabled,Enabled" else newline rbitfld.long 0x00 30. " TXRXS ,TX and RX status" "Disabled,Enabled" endif newline eventfld.long 0x00 28. " EOQF ,End of queue flag" "Not occurred,Occurred" eventfld.long 0x00 27. " TFUF ,Transmit FIFO underflow flag" "No underflow,Underflow" eventfld.long 0x00 25. " TFFF ,Transmit FIFO fill flag" "Full,Not full" eventfld.long 0x00 19. " RFOF ,Receive FIFO overflow flag" "No overflow,Overflow" newline eventfld.long 0x00 17. " RFDF ,Receive FIFO drain flag" "Empty,Not empty" rbitfld.long 0x00 12.--15. " TXCTR ,TX FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 8.--11. " TXNXTPTR ,Transmit next pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 4.--7. " RXCTR ,RX FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 0.--3. " POPNXTPTR ,Pop next pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") if (((per.l(ad:0x4002C000+0x2C))&0x40000000)==0x40000000) rgroup.long 0x30++0x03 line.long 0x00 "RSER,DSPI0 DMA/Interrupt Request Select and Enable Register" bitfld.long 0x00 31. " TCF_RE ,Transmission complete request enable" "Disabled,Enabled" bitfld.long 0x00 28. " EOQF_RE ,DSPI finished request enable" "Disabled,Enabled" bitfld.long 0x00 27. " TFUF_RE ,Transmit FIFO underflow request enable" "Disabled,Enabled" bitfld.long 0x00 25. " TFFF_RE ,Transmit FIFO fill request enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " TFFF_DIRS ,Transmit FIFO fill DMA / Interrupt request select" "Interrupt,DMA" bitfld.long 0x00 19. " RFOF_RE ,Receive FIFO overflow request enable" "Disabled,Enabled" bitfld.long 0x00 17. " RFDF_RE ,Receive FIFO drain request enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " RFDF_DIRS ,Receive FIFO drain DMA / Interrupt request select" "Interrupt,DMA" else group.long 0x30++0x03 line.long 0x00 "RSER,DSPI0 DMA/Interrupt Request Select and Enable Register" bitfld.long 0x00 31. " TCF_RE ,Transmission complete request enable" "Disabled,Enabled" bitfld.long 0x00 28. " EOQF_RE ,DSPI finished request enable" "Disabled,Enabled" bitfld.long 0x00 27. " TFUF_RE ,Transmit FIFO underflow request enable" "Disabled,Enabled" bitfld.long 0x00 25. " TFFF_RE ,Transmit FIFO fill request enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " TFFF_DIRS ,Transmit FIFO fill DMA / Interrupt request select" "Interrupt,DMA" bitfld.long 0x00 19. " RFOF_RE ,Receive FIFO overflow request enable" "Disabled,Enabled" bitfld.long 0x00 17. " RFDF_RE ,Receive FIFO drain request enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " RFDF_DIRS ,Receive FIFO drain DMA / Interrupt request select" "Interrupt,DMA" endif else group.long 0x30++0x03 line.long 0x00 "RSER,DSPI0 DMA/Interrupt Request Select and Enable Register" bitfld.long 0x00 31. " TCF_RE ,Transmission complete request enable" "Disabled,Enabled" bitfld.long 0x00 28. " EOQF_RE ,DSPI finished request enable" "Disabled,Enabled" bitfld.long 0x00 27. " TFUF_RE ,Transmit FIFO underflow request enable" "Disabled,Enabled" bitfld.long 0x00 25. " TFFF_RE ,Transmit FIFO fill request enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " TFFF_DIRS ,Transmit FIFO fill DMA / Interrupt request select" "Interrupt,DMA" bitfld.long 0x00 19. " RFOF_RE ,Receive FIFO overflow request enable" "Disabled,Enabled" bitfld.long 0x00 17. " RFDF_RE ,Receive FIFO drain request enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " RFDF_DIRS ,Receive FIFO drain DMA / Interrupt request select" "Interrupt,DMA" endif if ((per.l(ad:0x4002C000)&0x80000000)==0x80000000) group.long 0x34++0x3 line.long 0x00 "PUSHR,DSPI0 PUSH TX FIFO Register" bitfld.long 0x00 31. " CONT ,Continuous peripheral chip select enable" "Return to inactive,Keep asserted" bitfld.long 0x00 28.--30. " CTAS ,Clock and transfer attributes select" "CTAR0,CTAR1,?..." bitfld.long 0x00 27. " EOQ ,End Of queue" "Not ended,Ended" bitfld.long 0x00 26. " CTCNT ,Clear transfer counter" "No effect,Clear" newline sif !cpuis("MK30DN512ZVLK10")&&!cpuis("MK30D????ZVLQ*")&&!cpuis("MK30DX256VLL7*")&&!cpuis("MK70*") sif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 21. " PCS5 ,PCS 5 signal assertion" "Negated,Asserted" bitfld.long 0x00 20. " PCS4 ,PCS 4 signal assertion" "Negated,Asserted" bitfld.long 0x00 19. " PCS3 ,PCS 3 signal assertion" "Negated,Asserted" bitfld.long 0x00 18. " PCS2 ,PCS 2 signal assertion" "Negated,Asserted" newline bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted" bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" newline elif cpuis("MK*LL*")||cpuis("MK*MC*")||cpuis("MK*LQ*")||cpuis("MK*MD*")||cpuis("MK*VMJ*")||cpuis("MK*AB*")||cpuis("MK6*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK40DN512ZVLL10")||cpuis("MKL82*")||cpuis("MK40DN512ZVLL10")||cpuis("MK53DX256ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCLL10")||cpuis("MK50DN512ZCMD10") bitfld.long 0x00 21. " PCS5 ,PCS 5 signal assertion" "Negated,Asserted" bitfld.long 0x00 20. " PCS4 ,PCS 4 signal assertion" "Negated,Asserted" newline sif cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 19. " PCS3 ,PCS 3 signal assertion" "Negated,Asserted" bitfld.long 0x00 18. " PCS2 ,PCS 2 signal assertion" "Negated,Asserted" bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted" newline bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" newline elif cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0CAC18R") bitfld.long 0x00 19. " PCS3 ,PCS 3 signal assertion" "Negated,Asserted" bitfld.long 0x00 18. " PCS2 ,PCS 2 signal assertion" "Negated,Asserted" bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted" newline bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" newline elif cpuis("MK60DN512ZCAB10R") bitfld.long 0x00 19. " PCS3 ,PCS 3 signal assertion" "Negated,Asserted" bitfld.long 0x00 18. " PCS2 ,PCS 2 signal assertion" "Negated,Asserted" bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted" newline bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" newline else bitfld.long 0x00 19. " PCS3 ,PCS 3 signal assertion" "Negated,Asserted" bitfld.long 0x00 18. " PCS2 ,PCS 2 signal assertion" "Negated,Asserted" bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted" newline sif cpuis("MK40DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted" bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" newline else sif cpuis("MK*VLL10")||cpuis("MK*AB*")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10") bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted" bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" newline else bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted" bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" newline endif endif endif else bitfld.long 0x00 20. " PCS4 ,PCS 4 signal assertion" "Negated,Asserted" bitfld.long 0x00 19. " PCS3 ,PCS 3 signal assertion" "Negated,Asserted" bitfld.long 0x00 18. " PCS2 ,PCS 2 signal assertion" "Negated,Asserted" bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted" newline bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" newline endif else bitfld.long 0x00 21. " PCS5 ,PCS 5 signal assertion" "Negated,Asserted" bitfld.long 0x00 20. " PCS4 ,PCS 4 signal assertion" "Negated,Asserted" newline bitfld.long 0x00 19. " PCS3 ,PCS 3 signal assertion" "Negated,Asserted" bitfld.long 0x00 18. " PCS2 ,PCS 2 signal assertion" "Negated,Asserted" newline bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted" bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" newline endif hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" else sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*")||cpuis("MK70*")||cpuis("MK40DN512ZVLL10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10"))||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60FN1M0VLQ15")||cpuis("MK60FN1M0VLQ15") group.long 0x34++0x03 line.long 0x00 "PUSHR_SLAVE,DSPI0 PUSH TX FIFO Register" sif cpuis("MK?0D*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK30DX256VLL7*")||cpuis("MKL82*")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK60DN512VMC10R") hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" endif endif endif newline width 16. sif cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK40DN512ZVLL10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10") rgroup.long 0x38++0x03 line.long 0x00 "POPR,DSPI0 POP RX FIFO Register" else hgroup.long 0x38++0x03 hide.long 0x00 "POPR,DSPI0 POP RX FIFO Register" in endif if ((per.l(ad:0x4002C000)&0x80000000)==0x80000000) rgroup.long 0x3C++0x03 line.long 0x00 "TXFR0,DSPI0 Transmit FIFO Register 0" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x40++0x03 line.long 0x00 "TXFR1,DSPI0 Transmit FIFO Register 1" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x44++0x03 line.long 0x00 "TXFR2,DSPI0 Transmit FIFO Register 2" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x48++0x03 line.long 0x00 "TXFR3,DSPI0 Transmit FIFO Register 3" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" else sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") rgroup.long 0x3C++0x03 line.long 0x00 "TXFR0,DSPI0 Transmit FIFO Register 0" rgroup.long 0x40++0x03 line.long 0x00 "TXFR1,DSPI0 Transmit FIFO Register 1" rgroup.long 0x44++0x03 line.long 0x00 "TXFR2,DSPI0 Transmit FIFO Register 2" rgroup.long 0x48++0x03 line.long 0x00 "TXFR3,DSPI0 Transmit FIFO Register 3" elif !cpuis("MK8?FN256V*") hgroup.long 0x3C++0x03 hide.long 0x00 "TXFR0,DSPI0 Transmit FIFO Register 0" in hgroup.long 0x40++0x03 hide.long 0x00 "TXFR1,DSPI0 Transmit FIFO Register 1" in hgroup.long 0x44++0x03 hide.long 0x00 "TXFR2,DSPI0 Transmit FIFO Register 2" in hgroup.long 0x48++0x03 hide.long 0x00 "TXFR3,DSPI0 Transmit FIFO Register 3" in endif endif sif cpuis("MK8?FN256V*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DX256VLL7*")||cpuis("MK70*")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") rgroup.long (0x7C+0x0)++0x03 line.long 0x00 "RXFR0,DSPI0 Receive FIFO Register 0" rgroup.long (0x7C+0x4)++0x03 line.long 0x00 "RXFR1,DSPI0 Receive FIFO Register 1" rgroup.long (0x7C+0x8)++0x03 line.long 0x00 "RXFR2,DSPI0 Receive FIFO Register 2" rgroup.long (0x7C+0xC)++0x03 line.long 0x00 "RXFR3,DSPI0 Receive FIFO Register 3" else hgroup.long 0x0++0x03 "DSPI0 Rx FIFO Registers" hide.long 0x00 "RXFR0,DSPI0 Receive FIFO Register 0" in hgroup.long 0x4++0x03 "DSPI0 Rx FIFO Registers" hide.long 0x00 "RXFR1,DSPI0 Receive FIFO Register 1" in hgroup.long 0x8++0x03 "DSPI0 Rx FIFO Registers" hide.long 0x00 "RXFR2,DSPI0 Receive FIFO Register 2" in hgroup.long 0xC++0x03 "DSPI0 Rx FIFO Registers" hide.long 0x00 "RXFR3,DSPI0 Receive FIFO Register 3" in endif width 0x0B tree.end tree "SPI_1" base ad:0x4002D000 width 19. sif cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK40DN512ZVLL10") if (((per.l(ad:0x4002D000+0x0C))&0x2000000)==0x0000000)&&(((per.l(ad:0x4002D000+0x10))&0x2000000)==0x0000000) if ((per.l(ad:0x4002D000)&0x80000000)==0x80000000) if ((per.l(ad:0x4002D000)&0x4000)==0x4000) group.long 0x00++0x03 line.long 0x00 "MCR,DSPI1 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI1 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline newline bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" sif cpuis("MK40DN512ZVLL10") bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" endif newline bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" newline rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0,1,2,?..." newline bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" else group.long 0x00++0x03 line.long 0x00 "MCR,DSPI1 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI1 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline newline bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" sif cpuis("MK40DN512ZVLL10") bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" endif newline bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" newline bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0,1,2,?..." newline bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" endif else if ((per.l(ad:0x4002D000)&0x4000)==0x4000) group.long 0x00++0x03 line.long 0x00 "MCR,DSPI1 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI1 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" newline bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0,1,2,?..." bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" else group.long 0x00++0x03 line.long 0x00 "MCR,DSPI1 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI1 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" newline bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0,1,2,?..." bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" endif endif else if ((per.l(ad:0x4002D000)&0x80000000)==0x80000000) if ((per.l(ad:0x4002D000)&0x4000)==0x4000) group.long 0x00++0x03 line.long 0x00 "MCR,DSPI1 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI1 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline newline bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" sif cpuis("MK40DN512ZVLL10") bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" endif newline bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" newline bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" else group.long 0x00++0x03 line.long 0x00 "MCR,DSPI1 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI1 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline newline bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" sif cpuis("MK40DN512ZVLL10") bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" endif newline bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" newline rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" endif else if ((per.l(ad:0x4002D000)&0x4000)==0x4000) group.long 0x00++0x03 line.long 0x00 "MCR,DSPI1 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI1 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" newline bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" else group.long 0x00++0x03 line.long 0x00 "MCR,DSPI1 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI1 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" newline bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" endif endif endif elif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") if (((per.l(ad:0x4002D000+0x2C))&0x40000000)==0x40000000) if (((per.l(ad:0x4002D000+0x0C))&0x2000000)==0x0000000)&&(((per.l(ad:0x4002D000+0x10))&0x2000000)==0x0000000) group.long 0x00++0x03 line.long 0x00 "MCR,DSPI1 Module Configuration Register" rbitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" rbitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" rbitfld.long 0x00 28.--29. " DCONF ,DSPI1 configuration" "SPI,?..." rbitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline rbitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" sif !cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10") rbitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" endif newline rbitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline sif !cpuis("KK60DN512ZCAB10R") rbitfld.long 0x00 19. " PCSIS[3] ,Peripheral chip select 3 inactive state" "Low,High" rbitfld.long 0x00 18. " [2] ,Peripheral chip select 2 inactive state" "Low,High" rbitfld.long 0x00 17. " [1] ,Peripheral chip select 1 inactive state" "Low,High" rbitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High" endif newline rbitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline rbitfld.long 0x00 11. " CLR_TXF ,Clear Tx FIFO" "No effect,Clear" rbitfld.long 0x00 10. " CLR_RXF ,Clear Rx FIFO" "No effect,Clear" rbitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 clocks,1 clock,2 clocks,?..." bitfld.long 0x00 0. " HALT ,Start/stop DSPI transfers" "Start,Stop" else group.long 0x00++0x03 line.long 0x00 "MCR,DSPI1 Module Configuration Register" rbitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" rbitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" rbitfld.long 0x00 28.--29. " DCONF ,DSPI1 configuration" "SPI,?..." rbitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline rbitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" sif !cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10") rbitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" endif newline rbitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline sif !cpuis("KK60DN512ZCAB10R") rbitfld.long 0x00 19. " PCSIS[3] ,Peripheral chip select 3 inactive state" "Low,High" rbitfld.long 0x00 18. " [2] ,Peripheral chip select 2 inactive state" "Low,High" rbitfld.long 0x00 17. " [1] ,Peripheral chip select 1 inactive state" "Low,High" rbitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High" endif newline rbitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline rbitfld.long 0x00 11. " CLR_TXF ,Clear Tx FIFO" "No effect,Clear" rbitfld.long 0x00 10. " CLR_RXF ,Clear Rx FIFO" "No effect,Clear" bitfld.long 0x00 0. " HALT ,Start/stop DSPI transfers" "Start,Stop" endif else if (((per.l(ad:0x4002D000+0x0C))&0x2000000)==0x0000000)&&(((per.l(ad:0x4002D000+0x10))&0x2000000)==0x0000000) if ((per.l(ad:0x4002D000)&0x4000)==0x4000) group.long 0x00++0x03 line.long 0x00 "MCR,DSPI1 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI1 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" sif !cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10") bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" endif newline bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline sif !cpuis("KK60DN512ZCAB10R") bitfld.long 0x00 19. " PCSIS[3] ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " [2] ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " [1] ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High" endif newline bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Clear Tx FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear Rx FIFO" "No effect,Clear" bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 clocks,1 clock,2 clocks,?..." bitfld.long 0x00 0. " HALT ,Start/stop DSPI transfers" "Start,Stop" else group.long 0x00++0x03 line.long 0x00 "MCR,DSPI1 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI1 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" sif !cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10") bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" endif newline bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline sif !cpuis("KK60DN512ZCAB10R") bitfld.long 0x00 19. " PCSIS[3] ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " [2] ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " [1] ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High" endif newline bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Clear Tx FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear Rx FIFO" "No effect,Clear" bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 clocks,1 clock,2 clocks,?..." bitfld.long 0x00 0. " HALT ,Start/stop DSPI transfers" "Start,Stop" endif else if ((per.l(ad:0x4002D000)&0x4000)==0x4000) group.long 0x00++0x03 line.long 0x00 "MCR,DSPI1 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI1 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" sif !cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10") bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" endif newline bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline sif !cpuis("KK60DN512ZCAB10R") bitfld.long 0x00 19. " PCSIS[3] ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " [2] ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " [1] ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High" endif newline bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Clear Tx FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear Rx FIFO" "No effect,Clear" bitfld.long 0x00 0. " HALT ,Start/stop DSPI transfers" "Start,Stop" else group.long 0x00++0x03 line.long 0x00 "MCR,DSPI1 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI1 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" sif !cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10") bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" endif newline bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline sif !cpuis("KK60DN512ZCAB10R") bitfld.long 0x00 19. " PCSIS[3] ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " [2] ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " [1] ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High" endif newline bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Clear Tx FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear Rx FIFO" "No effect,Clear" bitfld.long 0x00 0. " HALT ,Start/stop DSPI transfers" "Start,Stop" endif endif endif else if (((per.l(ad:0x4002D000+0x0C))&0x2000000)==0x0000000)&&(((per.l(ad:0x4002D000+0x10))&0x2000000)==0x0000000) group.long 0x00++0x03 line.long 0x00 "MCR,DSPI1 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" newline sif cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK40DN512ZVLL10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZCAB10R")||cpuis("MK60FN1M0VLQ15") bitfld.long 0x00 28.--29. " DCONF ,DSPI1 configuration" "SPI,?..." newline else rbitfld.long 0x00 28.--29. " DCONF ,DSPI1 configuration" "SPI,?..." newline endif bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" newline sif cpuis("MK??F*")||(cpuis("MK30D????ZVLQ*"))||cpuis("MK30DN512ZVLK10")||cpuis("MK40DN512ZVLL10")||cpuis("MKL82*")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60FN1M0VLQ15") bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" newline endif bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline sif (cpuis("MK70*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")) sif !cpuis("MK50DN512ZCLL10")&&!cpuis("MK50DX256ZCLL10")&&!cpuis("MK51DN512ZCLL10") bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High" newline endif bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" newline else sif cpuis("MKL82*") else sif cpuis("MK??F*")||(cpuis("MK30D????ZVLQ*"))||cpuis("MK30DN512ZVLK10")||cpuis("MK40DN512ZVLL10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60FN1M0VLQ15") bitfld.long 0x00 21. " PCSIS5 ,Peripheral chip select 5 inactive state" "Low,High" newline endif bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 4 inactive state" "Low,High" newline endif bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" newline endif bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline sif cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10") rbitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" rbitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" newline else bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" newline endif bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0,1,2,?..." bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" else group.long 0x00++0x03 line.long 0x00 "MCR,DSPI1 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" newline sif cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK40DN512ZVLL10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZCAB10R")||cpuis("MK60FN1M0VLQ15") bitfld.long 0x00 28.--29. " DCONF ,DSPI1 configuration" "SPI,?..." newline else rbitfld.long 0x00 28.--29. " DCONF ,DSPI1 configuration" "SPI,?..." newline endif bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" newline sif cpuis("MK??F*")||(cpuis("MK30D????ZVLQ*"))||cpuis("MK30DN512ZVLK10")||cpuis("MK40DN512ZVLL10")||cpuis("MKL82*")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60FN1M0VLQ15") bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" newline endif bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline sif (cpuis("MK70*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")) sif !cpuis("MK50DN512ZCLL10")&&!cpuis("MK50DX256ZCLL10")&&!cpuis("MK51DN512ZCLL10") bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High" newline endif bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" newline else sif cpuis("MKL82*") else sif cpuis("MK??F*")||(cpuis("MK30D????ZVLQ*"))||cpuis("MK30DN512ZVLK10")||cpuis("MK40DN512ZVLL10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60FN1M0VLQ15") bitfld.long 0x00 21. " PCSIS5 ,Peripheral chip select 5 inactive state" "Low,High" newline endif bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 4 inactive state" "Low,High" newline endif bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" newline endif bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline sif cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10") rbitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" rbitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" newline else bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" newline endif bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" endif endif newline sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") if (((per.l(ad:0x4002D000+0x2C))&0x40000000)==0x40000000) rgroup.long 0x08++0x03 line.long 0x00 "TCR,DSPI1 Transfer Count Register" hexmask.long.word 0x00 16.--31. 1. " SPI_TCNT ,SPI transfer counter" else group.long 0x08++0x03 line.long 0x00 "TCR,DSPI1 Transfer Count Register" hexmask.long.word 0x00 16.--31. 1. " SPI_TCNT ,SPI transfer counter" endif else group.long 0x08++0x03 line.long 0x00 "TCR,DSPI1 Transfer Count Register" hexmask.long.word 0x00 16.--31. 1. " SPI_TCNT ,SPI transfer counter" endif sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60DN512ZCAB10R") if (((per.l(ad:0x4002D000+0x2C))&0x40000000)==0x40000000) if ((per.l(ad:0x4002D000)&0x80000000)==0x80000000) rgroup.long 0xC++0x03 line.long 0x00 "CTAR0,DSPI1 Clock and Transfer Attributes Register 0" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" newline bitfld.long 0x00 24. " LSBFE ,LBS First" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7" newline bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" newline bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" rgroup.long 0x10++0x03 line.long 0x00 "CTAR1,DSPI1 Clock and Transfer Attributes Register 1" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" newline bitfld.long 0x00 24. " LSBFE ,LBS First" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7" newline bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" newline bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" else rgroup.long 0x0C++0x03 line.long 0x00 "CTAR0_SLAVE,DSPI1 Clock and Transfer Attributes Register (In Slave Mode)" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Low,High" bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" endif else if ((per.l(ad:0x4002D000)&0x80000000)==0x80000000) group.long 0xC++0x03 line.long 0x00 "CTAR0,DSPI1 Clock and Transfer Attributes Register 0" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" newline bitfld.long 0x00 24. " LSBFE ,LBS First" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7" newline bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" newline bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" group.long 0x10++0x03 line.long 0x00 "CTAR1,DSPI1 Clock and Transfer Attributes Register 1" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" newline bitfld.long 0x00 24. " LSBFE ,LBS First" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7" newline bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" newline bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" else group.long 0x0C++0x03 line.long 0x00 "CTAR0_SLAVE,DSPI1 Clock and Transfer Attributes Register (In Slave Mode)" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Low,High" bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" endif endif else if ((per.l(ad:0x4002D000)&0x80000000)==0x80000000) group.long 0xC++0x03 line.long 0x00 "CTAR0,DSPI1 Clock and Transfer Attributes Register 0" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" newline bitfld.long 0x00 24. " LSBFE ,LBS First" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7" newline bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" newline bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" group.long 0x10++0x03 line.long 0x00 "CTAR1,DSPI1 Clock and Transfer Attributes Register 1" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" newline bitfld.long 0x00 24. " LSBFE ,LBS First" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7" newline bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" newline bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" else group.long 0x0C++0x03 line.long 0x00 "CTAR0_SLAVE,DSPI1 Clock and Transfer Attributes Register 0" sif cpuis("MKL82*") bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" newline else bitfld.long 0x00 27.--31. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline endif bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" sif !cpuis("MK8?FN256V*")&&!cpuis("MK40DN512ZVLL10")&&!cpuis("MKL82*")&&!cpuis("MK40DN512ZVLQ10")&&!cpuis("MK40DN512ZVMD10")&&!cpuis("MK40DX128ZVLQ10")&&!cpuis("MK40DX256ZVLQ10")&&!cpuis("MK40DX256ZVMD10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512VMC10R") sif cpuis("MK60DN512ZCAB10R")||cpuis("MK60FN1M0VLQ15")||cpuis("MK60DN512ZVLQ10R") hgroup.long 0x10++0x03 hide.long 0x00 "CTAR1_SLAVE,DSPI1 Clock and Transfer Attributes Register 1" endif endif endif endif group.long 0x2C++0x03 line.long 0x00 "SR,DSPI1 Status Register" eventfld.long 0x00 31. " TCF ,Transfer complete flag" "Not completed,Completed" sif cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*")||cpuis("MK30DX256VLL7*")||cpuis("MK70*")||cpuis("MK40DN512ZVLL10")||cpuis("MKL82*")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK60FN1M0VLQ15")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK8?FN256V*") newline eventfld.long 0x00 30. " TXRXS ,TX and RX status" "Disabled,Enabled" else newline rbitfld.long 0x00 30. " TXRXS ,TX and RX status" "Disabled,Enabled" endif newline eventfld.long 0x00 28. " EOQF ,End of queue flag" "Not occurred,Occurred" eventfld.long 0x00 27. " TFUF ,Transmit FIFO underflow flag" "No underflow,Underflow" eventfld.long 0x00 25. " TFFF ,Transmit FIFO fill flag" "Full,Not full" eventfld.long 0x00 19. " RFOF ,Receive FIFO overflow flag" "No overflow,Overflow" newline eventfld.long 0x00 17. " RFDF ,Receive FIFO drain flag" "Empty,Not empty" rbitfld.long 0x00 12.--15. " TXCTR ,TX FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 8.--11. " TXNXTPTR ,Transmit next pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 4.--7. " RXCTR ,RX FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 0.--3. " POPNXTPTR ,Pop next pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") if (((per.l(ad:0x4002D000+0x2C))&0x40000000)==0x40000000) rgroup.long 0x30++0x03 line.long 0x00 "RSER,DSPI1 DMA/Interrupt Request Select and Enable Register" bitfld.long 0x00 31. " TCF_RE ,Transmission complete request enable" "Disabled,Enabled" bitfld.long 0x00 28. " EOQF_RE ,DSPI finished request enable" "Disabled,Enabled" bitfld.long 0x00 27. " TFUF_RE ,Transmit FIFO underflow request enable" "Disabled,Enabled" bitfld.long 0x00 25. " TFFF_RE ,Transmit FIFO fill request enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " TFFF_DIRS ,Transmit FIFO fill DMA / Interrupt request select" "Interrupt,DMA" bitfld.long 0x00 19. " RFOF_RE ,Receive FIFO overflow request enable" "Disabled,Enabled" bitfld.long 0x00 17. " RFDF_RE ,Receive FIFO drain request enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " RFDF_DIRS ,Receive FIFO drain DMA / Interrupt request select" "Interrupt,DMA" else group.long 0x30++0x03 line.long 0x00 "RSER,DSPI1 DMA/Interrupt Request Select and Enable Register" bitfld.long 0x00 31. " TCF_RE ,Transmission complete request enable" "Disabled,Enabled" bitfld.long 0x00 28. " EOQF_RE ,DSPI finished request enable" "Disabled,Enabled" bitfld.long 0x00 27. " TFUF_RE ,Transmit FIFO underflow request enable" "Disabled,Enabled" bitfld.long 0x00 25. " TFFF_RE ,Transmit FIFO fill request enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " TFFF_DIRS ,Transmit FIFO fill DMA / Interrupt request select" "Interrupt,DMA" bitfld.long 0x00 19. " RFOF_RE ,Receive FIFO overflow request enable" "Disabled,Enabled" bitfld.long 0x00 17. " RFDF_RE ,Receive FIFO drain request enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " RFDF_DIRS ,Receive FIFO drain DMA / Interrupt request select" "Interrupt,DMA" endif else group.long 0x30++0x03 line.long 0x00 "RSER,DSPI1 DMA/Interrupt Request Select and Enable Register" bitfld.long 0x00 31. " TCF_RE ,Transmission complete request enable" "Disabled,Enabled" bitfld.long 0x00 28. " EOQF_RE ,DSPI finished request enable" "Disabled,Enabled" bitfld.long 0x00 27. " TFUF_RE ,Transmit FIFO underflow request enable" "Disabled,Enabled" bitfld.long 0x00 25. " TFFF_RE ,Transmit FIFO fill request enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " TFFF_DIRS ,Transmit FIFO fill DMA / Interrupt request select" "Interrupt,DMA" bitfld.long 0x00 19. " RFOF_RE ,Receive FIFO overflow request enable" "Disabled,Enabled" bitfld.long 0x00 17. " RFDF_RE ,Receive FIFO drain request enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " RFDF_DIRS ,Receive FIFO drain DMA / Interrupt request select" "Interrupt,DMA" endif if ((per.l(ad:0x4002D000)&0x80000000)==0x80000000) group.long 0x34++0x3 line.long 0x00 "PUSHR,DSPI1 PUSH TX FIFO Register" bitfld.long 0x00 31. " CONT ,Continuous peripheral chip select enable" "Return to inactive,Keep asserted" bitfld.long 0x00 28.--30. " CTAS ,Clock and transfer attributes select" "CTAR0,CTAR1,?..." bitfld.long 0x00 27. " EOQ ,End Of queue" "Not ended,Ended" bitfld.long 0x00 26. " CTCNT ,Clear transfer counter" "No effect,Clear" newline sif !cpuis("MK30DN512ZVLK10")&&!cpuis("MK30D????ZVLQ*")&&!cpuis("MK30DX256VLL7*")&&!cpuis("MK70*") sif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") sif !cpuis("KK60DN512ZCAB10R") sif !cpuis("MK50DN512ZCLL10")&&!cpuis("MK50DX256ZCLL10")&&!cpuis("MK51DN512ZCLL10") bitfld.long 0x00 19. " PCS3 ,PCS 3 signal assertion" "Negated,Asserted" newline endif bitfld.long 0x00 18. " PCS2 ,PCS 2 signal assertion" "Negated,Asserted" bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted" bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" newline endif elif cpuis("MK*LL*")||cpuis("MK*MC*")||cpuis("MK*LQ*")||cpuis("MK*MD*")||cpuis("MK*VMJ*")||cpuis("MK*AB*")||cpuis("MK6*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK40DN512ZVLL10")||cpuis("MKL82*")||cpuis("MK40DN512ZVLL10")||cpuis("MK53DX256ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCLL10")||cpuis("MK50DN512ZCMD10") sif cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" newline elif cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0CAC18R") bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" newline elif cpuis("MK60DN512ZCAB10R") else bitfld.long 0x00 19. " PCS3 ,PCS 3 signal assertion" "Negated,Asserted" bitfld.long 0x00 18. " PCS2 ,PCS 2 signal assertion" "Negated,Asserted" bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted" newline sif cpuis("MK40DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted" bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" newline else sif cpuis("MK*VLL10")||cpuis("MK*AB*")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10") bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted" bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" newline else bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted" bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" newline endif endif endif else sif !cpuis("MK*LH7") bitfld.long 0x00 18. " PCS2 ,PCS 2 signal assertion" "Negated,Asserted" bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted" newline endif bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" newline endif else bitfld.long 0x00 19. " PCS3 ,PCS 3 signal assertion" "Negated,Asserted" bitfld.long 0x00 18. " PCS2 ,PCS 2 signal assertion" "Negated,Asserted" newline bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted" bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" newline endif hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" else sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*")||cpuis("MK70*")||cpuis("MK40DN512ZVLL10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10"))||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60FN1M0VLQ15")||cpuis("MK60FN1M0VLQ15") group.long 0x34++0x03 line.long 0x00 "PUSHR_SLAVE,DSPI1 PUSH TX FIFO Register" sif cpuis("MK?0D*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK30DX256VLL7*")||cpuis("MKL82*")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK60DN512VMC10R") hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" endif endif endif newline width 16. sif cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK40DN512ZVLL10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10") rgroup.long 0x38++0x03 line.long 0x00 "POPR,DSPI1 POP RX FIFO Register" else hgroup.long 0x38++0x03 hide.long 0x00 "POPR,DSPI1 POP RX FIFO Register" in endif if ((per.l(ad:0x4002D000)&0x80000000)==0x80000000) rgroup.long 0x3C++0x03 line.long 0x00 "TXFR0,DSPI1 Transmit FIFO Register 0" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x40++0x03 line.long 0x00 "TXFR1,DSPI1 Transmit FIFO Register 1" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x44++0x03 line.long 0x00 "TXFR2,DSPI1 Transmit FIFO Register 2" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x48++0x03 line.long 0x00 "TXFR3,DSPI1 Transmit FIFO Register 3" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" else sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") rgroup.long 0x3C++0x03 line.long 0x00 "TXFR0,DSPI1 Transmit FIFO Register 0" rgroup.long 0x40++0x03 line.long 0x00 "TXFR1,DSPI1 Transmit FIFO Register 1" rgroup.long 0x44++0x03 line.long 0x00 "TXFR2,DSPI1 Transmit FIFO Register 2" rgroup.long 0x48++0x03 line.long 0x00 "TXFR3,DSPI1 Transmit FIFO Register 3" elif !cpuis("MK8?FN256V*") hgroup.long 0x3C++0x03 hide.long 0x00 "TXFR0,DSPI1 Transmit FIFO Register 0" in hgroup.long 0x40++0x03 hide.long 0x00 "TXFR1,DSPI1 Transmit FIFO Register 1" in hgroup.long 0x44++0x03 hide.long 0x00 "TXFR2,DSPI1 Transmit FIFO Register 2" in hgroup.long 0x48++0x03 hide.long 0x00 "TXFR3,DSPI1 Transmit FIFO Register 3" in endif endif sif cpuis("MK8?FN256V*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DX256VLL7*")||cpuis("MK70*")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") rgroup.long (0x7C+0x0)++0x03 line.long 0x00 "RXFR0,DSPI1 Receive FIFO Register 0" rgroup.long (0x7C+0x4)++0x03 line.long 0x00 "RXFR1,DSPI1 Receive FIFO Register 1" rgroup.long (0x7C+0x8)++0x03 line.long 0x00 "RXFR2,DSPI1 Receive FIFO Register 2" rgroup.long (0x7C+0xC)++0x03 line.long 0x00 "RXFR3,DSPI1 Receive FIFO Register 3" else hgroup.long 0x0++0x03 "DSPI1 Rx FIFO Registers" hide.long 0x00 "RXFR0,DSPI1 Receive FIFO Register 0" in hgroup.long 0x4++0x03 "DSPI1 Rx FIFO Registers" hide.long 0x00 "RXFR1,DSPI1 Receive FIFO Register 1" in hgroup.long 0x8++0x03 "DSPI1 Rx FIFO Registers" hide.long 0x00 "RXFR2,DSPI1 Receive FIFO Register 2" in hgroup.long 0xC++0x03 "DSPI1 Rx FIFO Registers" hide.long 0x00 "RXFR3,DSPI1 Receive FIFO Register 3" in endif width 0x0B tree.end tree "SPI_2" base ad:0x400AC000 width 19. sif cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK40DN512ZVLL10") if (((per.l(ad:0x400AC000+0x0C))&0x2000000)==0x0000000)&&(((per.l(ad:0x400AC000+0x10))&0x2000000)==0x0000000) if ((per.l(ad:0x400AC000)&0x80000000)==0x80000000) if ((per.l(ad:0x400AC000)&0x4000)==0x4000) group.long 0x00++0x03 line.long 0x00 "MCR,DSPI2 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI2 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline newline sif cpuis("MK40DN512ZVLL10") newline bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" endif newline bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" newline rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0,1,2,?..." newline bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" else group.long 0x00++0x03 line.long 0x00 "MCR,DSPI2 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI2 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline newline sif cpuis("MK40DN512ZVLL10") newline bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" endif newline bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" newline bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0,1,2,?..." newline bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" endif else if ((per.l(ad:0x400AC000)&0x4000)==0x4000) group.long 0x00++0x03 line.long 0x00 "MCR,DSPI2 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI2 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" newline bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0,1,2,?..." bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" else group.long 0x00++0x03 line.long 0x00 "MCR,DSPI2 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI2 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" newline bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0,1,2,?..." bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" endif endif else if ((per.l(ad:0x400AC000)&0x80000000)==0x80000000) if ((per.l(ad:0x400AC000)&0x4000)==0x4000) group.long 0x00++0x03 line.long 0x00 "MCR,DSPI2 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI2 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline newline sif cpuis("MK40DN512ZVLL10") textfld " " bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" endif newline bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" newline bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" else group.long 0x00++0x03 line.long 0x00 "MCR,DSPI2 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI2 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline newline sif cpuis("MK40DN512ZVLL10") textfld " " bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" endif newline bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" newline rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" endif else if ((per.l(ad:0x400AC000)&0x4000)==0x4000) group.long 0x00++0x03 line.long 0x00 "MCR,DSPI2 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI2 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" newline bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" else group.long 0x00++0x03 line.long 0x00 "MCR,DSPI2 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI2 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" newline bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" endif endif endif elif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") if (((per.l(ad:0x400AC000+0x2C))&0x40000000)==0x40000000) if (((per.l(ad:0x400AC000+0x0C))&0x2000000)==0x0000000)&&(((per.l(ad:0x400AC000+0x10))&0x2000000)==0x0000000) group.long 0x00++0x03 line.long 0x00 "MCR,DSPI2 Module Configuration Register" rbitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" rbitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" rbitfld.long 0x00 28.--29. " DCONF ,DSPI2 configuration" "SPI,?..." rbitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline rbitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" sif !cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10") rbitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" endif newline rbitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline sif cpuis("KK60DN512ZCAB10R") rbitfld.long 0x00 16. " PCSIS[0] ,Peripheral chip select 0 inactive state" "Low,High" else rbitfld.long 0x00 17. " PCSIS[1] ,Peripheral chip select 1 inactive state" "Low,High" rbitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High" endif newline rbitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline rbitfld.long 0x00 11. " CLR_TXF ,Clear Tx FIFO" "No effect,Clear" rbitfld.long 0x00 10. " CLR_RXF ,Clear Rx FIFO" "No effect,Clear" rbitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 clocks,1 clock,2 clocks,?..." bitfld.long 0x00 0. " HALT ,Start/stop DSPI transfers" "Start,Stop" else group.long 0x00++0x03 line.long 0x00 "MCR,DSPI2 Module Configuration Register" rbitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" rbitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" rbitfld.long 0x00 28.--29. " DCONF ,DSPI2 configuration" "SPI,?..." rbitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline rbitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" sif !cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10") rbitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" endif newline rbitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline sif cpuis("KK60DN512ZCAB10R") rbitfld.long 0x00 16. " PCSIS[0] ,Peripheral chip select 0 inactive state" "Low,High" else rbitfld.long 0x00 17. " PCSIS[1] ,Peripheral chip select 1 inactive state" "Low,High" rbitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High" endif newline rbitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline rbitfld.long 0x00 11. " CLR_TXF ,Clear Tx FIFO" "No effect,Clear" rbitfld.long 0x00 10. " CLR_RXF ,Clear Rx FIFO" "No effect,Clear" bitfld.long 0x00 0. " HALT ,Start/stop DSPI transfers" "Start,Stop" endif else if (((per.l(ad:0x400AC000+0x0C))&0x2000000)==0x0000000)&&(((per.l(ad:0x400AC000+0x10))&0x2000000)==0x0000000) if ((per.l(ad:0x400AC000)&0x4000)==0x4000) group.long 0x00++0x03 line.long 0x00 "MCR,DSPI2 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI2 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" sif !cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10") bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" endif newline bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline sif cpuis("KK60DN512ZCAB10R") bitfld.long 0x00 16. " PCSIS[0] ,Peripheral chip select 0 inactive state" "Low,High" else bitfld.long 0x00 17. " PCSIS[1] ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High" endif newline bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Clear Tx FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear Rx FIFO" "No effect,Clear" bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 clocks,1 clock,2 clocks,?..." bitfld.long 0x00 0. " HALT ,Start/stop DSPI transfers" "Start,Stop" else group.long 0x00++0x03 line.long 0x00 "MCR,DSPI2 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI2 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" sif !cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10") bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" endif newline bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline sif cpuis("KK60DN512ZCAB10R") bitfld.long 0x00 16. " PCSIS[0] ,Peripheral chip select 0 inactive state" "Low,High" else bitfld.long 0x00 17. " PCSIS[1] ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High" endif newline bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Clear Tx FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear Rx FIFO" "No effect,Clear" bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 clocks,1 clock,2 clocks,?..." bitfld.long 0x00 0. " HALT ,Start/stop DSPI transfers" "Start,Stop" endif else if ((per.l(ad:0x400AC000)&0x4000)==0x4000) group.long 0x00++0x03 line.long 0x00 "MCR,DSPI2 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI2 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" sif !cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10") bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" endif newline bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline sif cpuis("KK60DN512ZCAB10R") bitfld.long 0x00 16. " PCSIS[0] ,Peripheral chip select 0 inactive state" "Low,High" else bitfld.long 0x00 17. " PCSIS[1] ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High" endif newline bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Clear Tx FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear Rx FIFO" "No effect,Clear" bitfld.long 0x00 0. " HALT ,Start/stop DSPI transfers" "Start,Stop" else group.long 0x00++0x03 line.long 0x00 "MCR,DSPI2 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI2 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" sif !cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10") bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" endif newline bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline sif cpuis("KK60DN512ZCAB10R") bitfld.long 0x00 16. " PCSIS[0] ,Peripheral chip select 0 inactive state" "Low,High" else bitfld.long 0x00 17. " PCSIS[1] ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High" endif newline bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Clear Tx FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear Rx FIFO" "No effect,Clear" bitfld.long 0x00 0. " HALT ,Start/stop DSPI transfers" "Start,Stop" endif endif endif else if (((per.l(ad:0x400AC000+0x0C))&0x2000000)==0x0000000)&&(((per.l(ad:0x400AC000+0x10))&0x2000000)==0x0000000) group.long 0x00++0x03 line.long 0x00 "MCR,DSPI2 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" newline sif cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK40DN512ZVLL10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZCAB10R")||cpuis("MK60FN1M0VLQ15") bitfld.long 0x00 28.--29. " DCONF ,DSPI2 configuration" "SPI,?..." newline else rbitfld.long 0x00 28.--29. " DCONF ,DSPI2 configuration" "SPI,?..." newline endif bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" newline sif cpuis("MK??F*")||(cpuis("MK30D????ZVLQ*"))||cpuis("MK30DN512ZVLK10")||cpuis("MK40DN512ZVLL10")||cpuis("MKL82*")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60FN1M0VLQ15") bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" newline endif bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline sif (cpuis("MK70*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")) sif !cpuis("MK50DN512ZCLL10")&&!cpuis("MK50DX256ZCLL10")&&!cpuis("MK51DN512ZCLL10") bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" newline endif bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" newline else sif cpuis("MKL82*") else sif cpuis("MK??F*")||(cpuis("MK30D????ZVLQ*"))||cpuis("MK30DN512ZVLK10")||cpuis("MK40DN512ZVLL10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60FN1M0VLQ15") bitfld.long 0x00 21. " PCSIS5 ,Peripheral chip select 5 inactive state" "Low,High" newline endif bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 4 inactive state" "Low,High" newline endif bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" newline endif bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline sif cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10") rbitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" rbitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" newline else bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" newline endif bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0,1,2,?..." bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" else group.long 0x00++0x03 line.long 0x00 "MCR,DSPI2 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" newline sif cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK40DN512ZVLL10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZCAB10R")||cpuis("MK60FN1M0VLQ15") bitfld.long 0x00 28.--29. " DCONF ,DSPI2 configuration" "SPI,?..." newline else rbitfld.long 0x00 28.--29. " DCONF ,DSPI2 configuration" "SPI,?..." newline endif bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" newline sif cpuis("MK??F*")||(cpuis("MK30D????ZVLQ*"))||cpuis("MK30DN512ZVLK10")||cpuis("MK40DN512ZVLL10")||cpuis("MKL82*")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60FN1M0VLQ15") bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" newline endif bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline sif (cpuis("MK70*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")) sif !cpuis("MK50DN512ZCLL10")&&!cpuis("MK50DX256ZCLL10")&&!cpuis("MK51DN512ZCLL10") bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" newline endif bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" newline else sif cpuis("MKL82*") else sif cpuis("MK??F*")||(cpuis("MK30D????ZVLQ*"))||cpuis("MK30DN512ZVLK10")||cpuis("MK40DN512ZVLL10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60FN1M0VLQ15") bitfld.long 0x00 21. " PCSIS5 ,Peripheral chip select 5 inactive state" "Low,High" newline endif bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 4 inactive state" "Low,High" newline endif bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" newline endif bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline sif cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10") rbitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" rbitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" newline else bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" newline endif bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" endif endif newline sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") if (((per.l(ad:0x400AC000+0x2C))&0x40000000)==0x40000000) rgroup.long 0x08++0x03 line.long 0x00 "TCR,DSPI2 Transfer Count Register" hexmask.long.word 0x00 16.--31. 1. " SPI_TCNT ,SPI transfer counter" else group.long 0x08++0x03 line.long 0x00 "TCR,DSPI2 Transfer Count Register" hexmask.long.word 0x00 16.--31. 1. " SPI_TCNT ,SPI transfer counter" endif else group.long 0x08++0x03 line.long 0x00 "TCR,DSPI2 Transfer Count Register" hexmask.long.word 0x00 16.--31. 1. " SPI_TCNT ,SPI transfer counter" endif sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60DN512ZCAB10R") if (((per.l(ad:0x400AC000+0x2C))&0x40000000)==0x40000000) if ((per.l(ad:0x400AC000)&0x80000000)==0x80000000) rgroup.long 0xC++0x03 line.long 0x00 "CTAR0,DSPI2 Clock and Transfer Attributes Register 0" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" newline bitfld.long 0x00 24. " LSBFE ,LBS First" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7" newline bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" newline bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" rgroup.long 0x10++0x03 line.long 0x00 "CTAR1,DSPI2 Clock and Transfer Attributes Register 1" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" newline bitfld.long 0x00 24. " LSBFE ,LBS First" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7" newline bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" newline bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" else rgroup.long 0x0C++0x03 line.long 0x00 "CTAR0_SLAVE,DSPI2 Clock and Transfer Attributes Register (In Slave Mode)" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Low,High" bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" endif else if ((per.l(ad:0x400AC000)&0x80000000)==0x80000000) group.long 0xC++0x03 line.long 0x00 "CTAR0,DSPI2 Clock and Transfer Attributes Register 0" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" newline bitfld.long 0x00 24. " LSBFE ,LBS First" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7" newline bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" newline bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" group.long 0x10++0x03 line.long 0x00 "CTAR1,DSPI2 Clock and Transfer Attributes Register 1" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" newline bitfld.long 0x00 24. " LSBFE ,LBS First" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7" newline bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" newline bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" else group.long 0x0C++0x03 line.long 0x00 "CTAR0_SLAVE,DSPI2 Clock and Transfer Attributes Register (In Slave Mode)" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Low,High" bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" endif endif else if ((per.l(ad:0x400AC000)&0x80000000)==0x80000000) group.long 0xC++0x03 line.long 0x00 "CTAR0,DSPI2 Clock and Transfer Attributes Register 0" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" newline bitfld.long 0x00 24. " LSBFE ,LBS First" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7" newline bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" newline bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" group.long 0x10++0x03 line.long 0x00 "CTAR1,DSPI2 Clock and Transfer Attributes Register 1" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" newline bitfld.long 0x00 24. " LSBFE ,LBS First" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7" newline bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" newline bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" else group.long 0x0C++0x03 line.long 0x00 "CTAR0_SLAVE,DSPI2 Clock and Transfer Attributes Register 0" sif cpuis("MKL82*") bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" newline else bitfld.long 0x00 27.--31. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline endif bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" sif !cpuis("MK8?FN256V*")&&!cpuis("MK40DN512ZVLL10")&&!cpuis("MKL82*")&&!cpuis("MK40DN512ZVLQ10")&&!cpuis("MK40DN512ZVMD10")&&!cpuis("MK40DX128ZVLQ10")&&!cpuis("MK40DX256ZVLQ10")&&!cpuis("MK40DX256ZVMD10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512VMC10R") sif cpuis("MK60DN512ZCAB10R")||cpuis("MK60FN1M0VLQ15")||cpuis("MK60DN512ZVLQ10R") hgroup.long 0x10++0x03 hide.long 0x00 "CTAR1_SLAVE,DSPI2 Clock and Transfer Attributes Register 1" endif endif endif endif group.long 0x2C++0x03 line.long 0x00 "SR,DSPI2 Status Register" eventfld.long 0x00 31. " TCF ,Transfer complete flag" "Not completed,Completed" sif cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*")||cpuis("MK30DX256VLL7*")||cpuis("MK70*")||cpuis("MK40DN512ZVLL10")||cpuis("MKL82*")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK60FN1M0VLQ15")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK8?FN256V*") newline eventfld.long 0x00 30. " TXRXS ,TX and RX status" "Disabled,Enabled" else newline rbitfld.long 0x00 30. " TXRXS ,TX and RX status" "Disabled,Enabled" endif newline eventfld.long 0x00 28. " EOQF ,End of queue flag" "Not occurred,Occurred" eventfld.long 0x00 27. " TFUF ,Transmit FIFO underflow flag" "No underflow,Underflow" eventfld.long 0x00 25. " TFFF ,Transmit FIFO fill flag" "Full,Not full" eventfld.long 0x00 19. " RFOF ,Receive FIFO overflow flag" "No overflow,Overflow" newline eventfld.long 0x00 17. " RFDF ,Receive FIFO drain flag" "Empty,Not empty" rbitfld.long 0x00 12.--15. " TXCTR ,TX FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 8.--11. " TXNXTPTR ,Transmit next pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 4.--7. " RXCTR ,RX FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 0.--3. " POPNXTPTR ,Pop next pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") if (((per.l(ad:0x400AC000+0x2C))&0x40000000)==0x40000000) rgroup.long 0x30++0x03 line.long 0x00 "RSER,DSPI2 DMA/Interrupt Request Select and Enable Register" bitfld.long 0x00 31. " TCF_RE ,Transmission complete request enable" "Disabled,Enabled" bitfld.long 0x00 28. " EOQF_RE ,DSPI finished request enable" "Disabled,Enabled" bitfld.long 0x00 27. " TFUF_RE ,Transmit FIFO underflow request enable" "Disabled,Enabled" bitfld.long 0x00 25. " TFFF_RE ,Transmit FIFO fill request enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " TFFF_DIRS ,Transmit FIFO fill DMA / Interrupt request select" "Interrupt,DMA" bitfld.long 0x00 19. " RFOF_RE ,Receive FIFO overflow request enable" "Disabled,Enabled" bitfld.long 0x00 17. " RFDF_RE ,Receive FIFO drain request enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " RFDF_DIRS ,Receive FIFO drain DMA / Interrupt request select" "Interrupt,DMA" else group.long 0x30++0x03 line.long 0x00 "RSER,DSPI2 DMA/Interrupt Request Select and Enable Register" bitfld.long 0x00 31. " TCF_RE ,Transmission complete request enable" "Disabled,Enabled" bitfld.long 0x00 28. " EOQF_RE ,DSPI finished request enable" "Disabled,Enabled" bitfld.long 0x00 27. " TFUF_RE ,Transmit FIFO underflow request enable" "Disabled,Enabled" bitfld.long 0x00 25. " TFFF_RE ,Transmit FIFO fill request enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " TFFF_DIRS ,Transmit FIFO fill DMA / Interrupt request select" "Interrupt,DMA" bitfld.long 0x00 19. " RFOF_RE ,Receive FIFO overflow request enable" "Disabled,Enabled" bitfld.long 0x00 17. " RFDF_RE ,Receive FIFO drain request enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " RFDF_DIRS ,Receive FIFO drain DMA / Interrupt request select" "Interrupt,DMA" endif else group.long 0x30++0x03 line.long 0x00 "RSER,DSPI2 DMA/Interrupt Request Select and Enable Register" bitfld.long 0x00 31. " TCF_RE ,Transmission complete request enable" "Disabled,Enabled" bitfld.long 0x00 28. " EOQF_RE ,DSPI finished request enable" "Disabled,Enabled" bitfld.long 0x00 27. " TFUF_RE ,Transmit FIFO underflow request enable" "Disabled,Enabled" bitfld.long 0x00 25. " TFFF_RE ,Transmit FIFO fill request enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " TFFF_DIRS ,Transmit FIFO fill DMA / Interrupt request select" "Interrupt,DMA" bitfld.long 0x00 19. " RFOF_RE ,Receive FIFO overflow request enable" "Disabled,Enabled" bitfld.long 0x00 17. " RFDF_RE ,Receive FIFO drain request enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " RFDF_DIRS ,Receive FIFO drain DMA / Interrupt request select" "Interrupt,DMA" endif if ((per.l(ad:0x400AC000)&0x80000000)==0x80000000) group.long 0x34++0x3 line.long 0x00 "PUSHR,DSPI2 PUSH TX FIFO Register" bitfld.long 0x00 31. " CONT ,Continuous peripheral chip select enable" "Return to inactive,Keep asserted" bitfld.long 0x00 28.--30. " CTAS ,Clock and transfer attributes select" "CTAR0,CTAR1,?..." bitfld.long 0x00 27. " EOQ ,End Of queue" "Not ended,Ended" bitfld.long 0x00 26. " CTCNT ,Clear transfer counter" "No effect,Clear" newline sif !cpuis("MK30DN512ZVLK10")&&!cpuis("MK30D????ZVLQ*")&&!cpuis("MK30DX256VLL7*")&&!cpuis("MK70*") sif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") sif !cpuis("MK50DN512ZCLL10")&&!cpuis("MK50DX256ZCLL10")&&!cpuis("MK51DN512ZCLL10") bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted" newline endif bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" newline elif cpuis("MK*LL*")||cpuis("MK*MC*")||cpuis("MK*LQ*")||cpuis("MK*MD*")||cpuis("MK*VMJ*")||cpuis("MK*AB*")||cpuis("MK6*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK40DN512ZVLL10")||cpuis("MKL82*")||cpuis("MK40DN512ZVLL10")||cpuis("MK53DX256ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCLL10")||cpuis("MK50DN512ZCMD10") sif cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 19. " PCS3 ,PCS 3 signal assertion" "Negated,Asserted" bitfld.long 0x00 18. " PCS2 ,PCS 2 signal assertion" "Negated,Asserted" bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted" newline bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" newline elif cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0CAC18R") bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" newline elif cpuis("MK60DN512ZCAB10R") bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" newline else sif cpuis("MK40DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted" bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" newline else sif cpuis("MK*VLL10")||cpuis("MK*AB*")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10") bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" newline else bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted" bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" newline endif endif endif else endif else bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted" bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" newline endif hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" else sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*")||cpuis("MK70*")||cpuis("MK40DN512ZVLL10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10"))||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60FN1M0VLQ15")||cpuis("MK60FN1M0VLQ15") group.long 0x34++0x03 line.long 0x00 "PUSHR_SLAVE,DSPI2 PUSH TX FIFO Register" sif cpuis("MK?0D*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK30DX256VLL7*")||cpuis("MKL82*")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK60DN512VMC10R") hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" endif endif endif newline width 16. sif cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK40DN512ZVLL10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10") rgroup.long 0x38++0x03 line.long 0x00 "POPR,DSPI2 POP RX FIFO Register" else hgroup.long 0x38++0x03 hide.long 0x00 "POPR,DSPI2 POP RX FIFO Register" in endif if ((per.l(ad:0x400AC000)&0x80000000)==0x80000000) rgroup.long 0x3C++0x03 line.long 0x00 "TXFR0,DSPI2 Transmit FIFO Register 0" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x40++0x03 line.long 0x00 "TXFR1,DSPI2 Transmit FIFO Register 1" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x44++0x03 line.long 0x00 "TXFR2,DSPI2 Transmit FIFO Register 2" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x48++0x03 line.long 0x00 "TXFR3,DSPI2 Transmit FIFO Register 3" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" else sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") rgroup.long 0x3C++0x03 line.long 0x00 "TXFR0,DSPI2 Transmit FIFO Register 0" rgroup.long 0x40++0x03 line.long 0x00 "TXFR1,DSPI2 Transmit FIFO Register 1" rgroup.long 0x44++0x03 line.long 0x00 "TXFR2,DSPI2 Transmit FIFO Register 2" rgroup.long 0x48++0x03 line.long 0x00 "TXFR3,DSPI2 Transmit FIFO Register 3" elif !cpuis("MK8?FN256V*") hgroup.long 0x3C++0x03 hide.long 0x00 "TXFR0,DSPI2 Transmit FIFO Register 0" in hgroup.long 0x40++0x03 hide.long 0x00 "TXFR1,DSPI2 Transmit FIFO Register 1" in hgroup.long 0x44++0x03 hide.long 0x00 "TXFR2,DSPI2 Transmit FIFO Register 2" in hgroup.long 0x48++0x03 hide.long 0x00 "TXFR3,DSPI2 Transmit FIFO Register 3" in endif endif sif cpuis("MK8?FN256V*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DX256VLL7*")||cpuis("MK70*")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") rgroup.long (0x7C+0x0)++0x03 line.long 0x00 "RXFR0,DSPI2 Receive FIFO Register 0" rgroup.long (0x7C+0x4)++0x03 line.long 0x00 "RXFR1,DSPI2 Receive FIFO Register 1" rgroup.long (0x7C+0x8)++0x03 line.long 0x00 "RXFR2,DSPI2 Receive FIFO Register 2" rgroup.long (0x7C+0xC)++0x03 line.long 0x00 "RXFR3,DSPI2 Receive FIFO Register 3" else hgroup.long 0x0++0x03 "DSPI2 Rx FIFO Registers" hide.long 0x00 "RXFR0,DSPI2 Receive FIFO Register 0" in hgroup.long 0x4++0x03 "DSPI2 Rx FIFO Registers" hide.long 0x00 "RXFR1,DSPI2 Receive FIFO Register 1" in hgroup.long 0x8++0x03 "DSPI2 Rx FIFO Registers" hide.long 0x00 "RXFR2,DSPI2 Receive FIFO Register 2" in hgroup.long 0xC++0x03 "DSPI2 Rx FIFO Registers" hide.long 0x00 "RXFR3,DSPI2 Receive FIFO Register 3" in endif width 0x0B tree.end tree.end tree.open "I2C (Inter-Integrated Circuit)" tree "I2C_0" base ad:0x40066000 width 6. group.byte 0x00++0x03 line.byte 0x00 "A1,IIC0 Address Register 1" hexmask.byte 0x00 1.--7. 0x02 " AD ,Slave address bits [7:1]" line.byte 0x01 "F,IIC0 Frequency Divider Register" bitfld.byte 0x01 6.--7. " MULT ,Multiplier factor" "1,2,4,?..." bitfld.byte 0x01 0.--5. " ICR ,Clock rate (I2C baud rate/SDA hold time/SCL start hold time/SCL stop hold time)" "20/7/6/11,22/7/7/12,24/8/8/13,26/8/9/14,28/9/10/15,30/9/11/16,34/10/13/18,40/10/16/21,28/7/10/15,32/7/12/17,36/9/14/19,40/9/16/21,44/11/18/23,48/11/20/25,56/13/24/29,68/13/30/35,48/9/18/25,56/9/22/29,64/13/26/33,72/13/30/37,80/17/34/41,88/17/38/45,104/21/46/53,128/21/58/65,80/9/38/41,96/9/46/49,112/17/54/57,128/17/62/65,144/25/70/73,160/25/78/81,192/33/94/97,240/33/118/121,160/17/78/81,192/17/94/97,224/33/110/113,256/33/126/129,288/49/142/145,320/49/158/161,384/65/190/193,480/65/238/241,320/33/158/161,384/33/190/193,448/65/222/225,512/65/254/257,576/97/286/289,640/97/318/321,768/129/382/385,960/129/478/481,640/65/318/321,768/65/382/385,896/129/446/449,1024/129/510/513,1152/193/574/577,1280/193/638/641,1536/257/766/769,1920/257/958/961,1280/129/638/641,1536/129/766/769,1792/257/894/897,2048/257/1022/1025,2304/385/1150/1153,2560/385/1278/1281,3072/513/1534/1537,3840/513/1918/1921" line.byte 0x02 "C1,IIC0 Control Register 1" bitfld.byte 0x02 7. " IICEN ,IIC0 enable" "Disabled,Enabled" bitfld.byte 0x02 6. " IICIE ,IIC0 interrupt enable" "Disabled,Enabled" bitfld.byte 0x02 5. " MST ,Master mode select" "Slave,Master" bitfld.byte 0x02 4. " TX ,Transmit mode select" "Receive,Transmit" newline bitfld.byte 0x02 3. " TXAK ,Transmit acknowledge enable" "Disabled,Enabled" bitfld.byte 0x02 2. " RSTA ,Repeat START" "No effect,Start" bitfld.byte 0x02 1. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.byte 0x02 0. " DMAEN ,DMA enable" "Disabled,Enabled" line.byte 0x03 "S,IIC0 Status Register" rbitfld.byte 0x03 7. " TCF ,Transfer complete flag" "Not completed,Completed" bitfld.byte 0x03 6. " IAAS ,Addressed as a slave" "Not addressed,Addressed" rbitfld.byte 0x03 5. " BUSY ,Bus busy" "Idle,Busy" eventfld.byte 0x03 4. " ARBL ,Arbitration lost" "Not lost,Lost" newline bitfld.byte 0x03 3. " RAM ,Range address match" "Not matched,Matched" rbitfld.byte 0x03 2. " SRW ,Slave read/write" "Write,Read" eventfld.byte 0x03 1. " IICIF ,Interrupt flag" "No interrupt,Interrupt" rbitfld.byte 0x03 0. " RXAK ,Receive acknowledge" "Acknowledged,Not acknowledged" newline hgroup.byte 0x04++0x00 hide.byte 0x00 "D,IIC0 Data I/O Register" in if ((per.b(ad:0x40066000+0x05)&0x40)==0x40) group.byte 0x05++0x00 line.byte 0x00 "C2,IIC0 Control Register 2" bitfld.byte 0x00 7. " GCAEN ,Enables general call address" "Disabled,Enabled" bitfld.byte 0x00 6. " ADEXT ,Controls the number of bits used for the slave address" "7-bit,10-bit" bitfld.byte 0x00 5. " HDRS ,Controls the drive capability of the I2C pads" "Normal,High" bitfld.byte 0x00 4. " SBRC ,Slave baud rate control" "Master baud rate,Independent" newline bitfld.byte 0x00 3. " RMEN ,Controls slave address matching for addresses between the values of the A1 and RA registers" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " AD[10:8] ,Slave address bits [10:8]" "000,001,010,011,100,101,110,111" else group.byte 0x05++0x00 line.byte 0x00 "C2,IIC0 Control Register 2" bitfld.byte 0x00 7. " GCAEN ,Enables general call address" "Disabled,Enabled" bitfld.byte 0x00 6. " ADEXT ,Controls the number of bits used for the slave address" "7-bit,10-bit" bitfld.byte 0x00 5. " HDRS ,Controls the drive capability of the I2C pads" "Normal,High" bitfld.byte 0x00 4. " SBRC ,Slave baud rate control. Enables independent slave mode baud rate at maximum frequency" "Master's,Independent" newline bitfld.byte 0x00 3. " RMEN ,Controls slave address matching for addresses between the values of the A1 and RA registers" "Disabled,Enabled" endif group.byte 0x06++0x05 line.byte 0x00 "FLT,IIC0 Programmable Input Glitch Filter Register" sif cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60FN1M0VLQ15")||cpuis("MK60DN512ZVLL10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R") bitfld.byte 0x00 0.--4. " FLT ,IIC0 programmable filter factor" "No filter,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else sif cpuis("MK21F*")||cpuis("MK22F*")||cpuis("MK02*")||cpuis("MK6*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.byte 0x00 7. " SHEN ,Stop hold enable" "Disabled,Enabled" eventfld.byte 0x00 6. " STOPF ,IIC0 bus stop detect flag" "Not detected,Detected" bitfld.byte 0x00 5. " SSIE ,I2C bus stop or start interrupt enable" "Disabled,Enabled" eventfld.byte 0x00 4. " STARTF ,I2C bus start detect flag" "Not started,Started" newline bitfld.byte 0x00 0.--3. " FLT ,IIC0 programmable filter factor" "No filter,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.byte 0x00 0.--4. " FLT ,IIC0 programmable filter factor" "No filter,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif endif line.byte 0x01 "RA,IIC0 Range Address Register" hexmask.byte 0x01 1.--7. 0x02 " RAD ,Range slave address" line.byte 0x02 "SMB,IIC0 SMBus Control and Status Register" bitfld.byte 0x02 7. " FACK ,Fast NACK/ACK enable" "NACK/ACK on following,ACK/NACK by TXAK" bitfld.byte 0x02 6. " ALERTEN ,SMBus alert response address enable" "Disabled,Enabled" bitfld.byte 0x02 5. " SIICAEN ,Second IIC0 address enable" "Disabled,Enabled" bitfld.byte 0x02 4. " TCKSEL ,Timeout counter clock select" "Clock / 64,Clock" newline eventfld.byte 0x02 3. " SLTF ,SCL low timeout flag" "Not occurred,Occurred" rbitfld.byte 0x02 2. " SHTF1 ,SCL high timeout flag 1" "Not occurred,Occurred" eventfld.byte 0x02 1. " SHTF2 ,SCL high timeout flag 2" "Not occurred,Occurred" bitfld.byte 0x02 0. " SHTF2IE ,SHTF2 interrupt enable" "Disabled,Enabled" line.byte 0x03 "A2,IIC0 Address Register 2" hexmask.byte 0x03 1.--7. 0x02 " SAD ,SMBus address" line.byte 0x04 "SLTH,IIC0 SCL Low Timeout High Register" line.byte 0x05 "SLTL,IIC0 SCL Low Timeout Low Register" sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") group.byte 0x0C++0x00 line.byte 0x00 "S2,IIC0 Status Register 2" eventfld.byte 0x00 1. " ERROR ,Read or write errors with the Tx and Rx buffers" "No error,Error" rbitfld.byte 0x00 0. " EMPTY ,Tx or Rx buffer is empty" "Not empty,Empty" endif width 0x0B tree.end tree "I2C_1" base ad:0x40067000 width 6. group.byte 0x00++0x03 line.byte 0x00 "A1,IIC1 Address Register 1" hexmask.byte 0x00 1.--7. 0x02 " AD ,Slave address bits [7:1]" line.byte 0x01 "F,IIC1 Frequency Divider Register" bitfld.byte 0x01 6.--7. " MULT ,Multiplier factor" "1,2,4,?..." bitfld.byte 0x01 0.--5. " ICR ,Clock rate (I2C baud rate/SDA hold time/SCL start hold time/SCL stop hold time)" "20/7/6/11,22/7/7/12,24/8/8/13,26/8/9/14,28/9/10/15,30/9/11/16,34/10/13/18,40/10/16/21,28/7/10/15,32/7/12/17,36/9/14/19,40/9/16/21,44/11/18/23,48/11/20/25,56/13/24/29,68/13/30/35,48/9/18/25,56/9/22/29,64/13/26/33,72/13/30/37,80/17/34/41,88/17/38/45,104/21/46/53,128/21/58/65,80/9/38/41,96/9/46/49,112/17/54/57,128/17/62/65,144/25/70/73,160/25/78/81,192/33/94/97,240/33/118/121,160/17/78/81,192/17/94/97,224/33/110/113,256/33/126/129,288/49/142/145,320/49/158/161,384/65/190/193,480/65/238/241,320/33/158/161,384/33/190/193,448/65/222/225,512/65/254/257,576/97/286/289,640/97/318/321,768/129/382/385,960/129/478/481,640/65/318/321,768/65/382/385,896/129/446/449,1024/129/510/513,1152/193/574/577,1280/193/638/641,1536/257/766/769,1920/257/958/961,1280/129/638/641,1536/129/766/769,1792/257/894/897,2048/257/1022/1025,2304/385/1150/1153,2560/385/1278/1281,3072/513/1534/1537,3840/513/1918/1921" line.byte 0x02 "C1,IIC1 Control Register 1" bitfld.byte 0x02 7. " IICEN ,IIC1 enable" "Disabled,Enabled" bitfld.byte 0x02 6. " IICIE ,IIC1 interrupt enable" "Disabled,Enabled" bitfld.byte 0x02 5. " MST ,Master mode select" "Slave,Master" bitfld.byte 0x02 4. " TX ,Transmit mode select" "Receive,Transmit" newline bitfld.byte 0x02 3. " TXAK ,Transmit acknowledge enable" "Disabled,Enabled" bitfld.byte 0x02 2. " RSTA ,Repeat START" "No effect,Start" bitfld.byte 0x02 1. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.byte 0x02 0. " DMAEN ,DMA enable" "Disabled,Enabled" line.byte 0x03 "S,IIC1 Status Register" rbitfld.byte 0x03 7. " TCF ,Transfer complete flag" "Not completed,Completed" bitfld.byte 0x03 6. " IAAS ,Addressed as a slave" "Not addressed,Addressed" rbitfld.byte 0x03 5. " BUSY ,Bus busy" "Idle,Busy" eventfld.byte 0x03 4. " ARBL ,Arbitration lost" "Not lost,Lost" newline bitfld.byte 0x03 3. " RAM ,Range address match" "Not matched,Matched" rbitfld.byte 0x03 2. " SRW ,Slave read/write" "Write,Read" eventfld.byte 0x03 1. " IICIF ,Interrupt flag" "No interrupt,Interrupt" rbitfld.byte 0x03 0. " RXAK ,Receive acknowledge" "Acknowledged,Not acknowledged" newline hgroup.byte 0x04++0x00 hide.byte 0x00 "D,IIC1 Data I/O Register" in if ((per.b(ad:0x40067000+0x05)&0x40)==0x40) group.byte 0x05++0x00 line.byte 0x00 "C2,IIC1 Control Register 2" bitfld.byte 0x00 7. " GCAEN ,Enables general call address" "Disabled,Enabled" bitfld.byte 0x00 6. " ADEXT ,Controls the number of bits used for the slave address" "7-bit,10-bit" bitfld.byte 0x00 5. " HDRS ,Controls the drive capability of the I2C pads" "Normal,High" bitfld.byte 0x00 4. " SBRC ,Slave baud rate control" "Master baud rate,Independent" newline bitfld.byte 0x00 3. " RMEN ,Controls slave address matching for addresses between the values of the A1 and RA registers" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " AD[10:8] ,Slave address bits [10:8]" "000,001,010,011,100,101,110,111" else group.byte 0x05++0x00 line.byte 0x00 "C2,IIC1 Control Register 2" bitfld.byte 0x00 7. " GCAEN ,Enables general call address" "Disabled,Enabled" bitfld.byte 0x00 6. " ADEXT ,Controls the number of bits used for the slave address" "7-bit,10-bit" bitfld.byte 0x00 5. " HDRS ,Controls the drive capability of the I2C pads" "Normal,High" bitfld.byte 0x00 4. " SBRC ,Slave baud rate control. Enables independent slave mode baud rate at maximum frequency" "Master's,Independent" newline bitfld.byte 0x00 3. " RMEN ,Controls slave address matching for addresses between the values of the A1 and RA registers" "Disabled,Enabled" endif group.byte 0x06++0x05 line.byte 0x00 "FLT,IIC1 Programmable Input Glitch Filter Register" sif cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60FN1M0VLQ15")||cpuis("MK60DN512ZVLL10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R") bitfld.byte 0x00 0.--4. " FLT ,IIC1 programmable filter factor" "No filter,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else sif cpuis("MK21F*")||cpuis("MK22F*")||cpuis("MK02*")||cpuis("MK6*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.byte 0x00 7. " SHEN ,Stop hold enable" "Disabled,Enabled" eventfld.byte 0x00 6. " STOPF ,IIC1 bus stop detect flag" "Not detected,Detected" bitfld.byte 0x00 5. " SSIE ,I2C bus stop or start interrupt enable" "Disabled,Enabled" eventfld.byte 0x00 4. " STARTF ,I2C bus start detect flag" "Not started,Started" newline bitfld.byte 0x00 0.--3. " FLT ,IIC1 programmable filter factor" "No filter,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.byte 0x00 0.--4. " FLT ,IIC1 programmable filter factor" "No filter,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif endif line.byte 0x01 "RA,IIC1 Range Address Register" hexmask.byte 0x01 1.--7. 0x02 " RAD ,Range slave address" line.byte 0x02 "SMB,IIC1 SMBus Control and Status Register" bitfld.byte 0x02 7. " FACK ,Fast NACK/ACK enable" "NACK/ACK on following,ACK/NACK by TXAK" bitfld.byte 0x02 6. " ALERTEN ,SMBus alert response address enable" "Disabled,Enabled" bitfld.byte 0x02 5. " SIICAEN ,Second IIC1 address enable" "Disabled,Enabled" bitfld.byte 0x02 4. " TCKSEL ,Timeout counter clock select" "Clock / 64,Clock" newline eventfld.byte 0x02 3. " SLTF ,SCL low timeout flag" "Not occurred,Occurred" rbitfld.byte 0x02 2. " SHTF1 ,SCL high timeout flag 1" "Not occurred,Occurred" eventfld.byte 0x02 1. " SHTF2 ,SCL high timeout flag 2" "Not occurred,Occurred" bitfld.byte 0x02 0. " SHTF2IE ,SHTF2 interrupt enable" "Disabled,Enabled" line.byte 0x03 "A2,IIC1 Address Register 2" hexmask.byte 0x03 1.--7. 0x02 " SAD ,SMBus address" line.byte 0x04 "SLTH,IIC1 SCL Low Timeout High Register" line.byte 0x05 "SLTL,IIC1 SCL Low Timeout Low Register" sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") group.byte 0x0C++0x00 line.byte 0x00 "S2,IIC1 Status Register 2" eventfld.byte 0x00 1. " ERROR ,Read or write errors with the Tx and Rx buffers" "No error,Error" rbitfld.byte 0x00 0. " EMPTY ,Tx or Rx buffer is empty" "Not empty,Empty" endif width 0x0B tree.end tree "I2C_2" base ad:0x400E6000 width 6. group.byte 0x00++0x03 line.byte 0x00 "A1,IIC2 Address Register 1" hexmask.byte 0x00 1.--7. 0x02 " AD ,Slave address bits [7:1]" line.byte 0x01 "F,IIC2 Frequency Divider Register" bitfld.byte 0x01 6.--7. " MULT ,Multiplier factor" "1,2,4,?..." bitfld.byte 0x01 0.--5. " ICR ,Clock rate (I2C baud rate/SDA hold time/SCL start hold time/SCL stop hold time)" "20/7/6/11,22/7/7/12,24/8/8/13,26/8/9/14,28/9/10/15,30/9/11/16,34/10/13/18,40/10/16/21,28/7/10/15,32/7/12/17,36/9/14/19,40/9/16/21,44/11/18/23,48/11/20/25,56/13/24/29,68/13/30/35,48/9/18/25,56/9/22/29,64/13/26/33,72/13/30/37,80/17/34/41,88/17/38/45,104/21/46/53,128/21/58/65,80/9/38/41,96/9/46/49,112/17/54/57,128/17/62/65,144/25/70/73,160/25/78/81,192/33/94/97,240/33/118/121,160/17/78/81,192/17/94/97,224/33/110/113,256/33/126/129,288/49/142/145,320/49/158/161,384/65/190/193,480/65/238/241,320/33/158/161,384/33/190/193,448/65/222/225,512/65/254/257,576/97/286/289,640/97/318/321,768/129/382/385,960/129/478/481,640/65/318/321,768/65/382/385,896/129/446/449,1024/129/510/513,1152/193/574/577,1280/193/638/641,1536/257/766/769,1920/257/958/961,1280/129/638/641,1536/129/766/769,1792/257/894/897,2048/257/1022/1025,2304/385/1150/1153,2560/385/1278/1281,3072/513/1534/1537,3840/513/1918/1921" line.byte 0x02 "C1,IIC2 Control Register 1" bitfld.byte 0x02 7. " IICEN ,IIC2 enable" "Disabled,Enabled" bitfld.byte 0x02 6. " IICIE ,IIC2 interrupt enable" "Disabled,Enabled" bitfld.byte 0x02 5. " MST ,Master mode select" "Slave,Master" bitfld.byte 0x02 4. " TX ,Transmit mode select" "Receive,Transmit" newline bitfld.byte 0x02 3. " TXAK ,Transmit acknowledge enable" "Disabled,Enabled" bitfld.byte 0x02 2. " RSTA ,Repeat START" "No effect,Start" bitfld.byte 0x02 1. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.byte 0x02 0. " DMAEN ,DMA enable" "Disabled,Enabled" line.byte 0x03 "S,IIC2 Status Register" rbitfld.byte 0x03 7. " TCF ,Transfer complete flag" "Not completed,Completed" bitfld.byte 0x03 6. " IAAS ,Addressed as a slave" "Not addressed,Addressed" rbitfld.byte 0x03 5. " BUSY ,Bus busy" "Idle,Busy" eventfld.byte 0x03 4. " ARBL ,Arbitration lost" "Not lost,Lost" newline bitfld.byte 0x03 3. " RAM ,Range address match" "Not matched,Matched" rbitfld.byte 0x03 2. " SRW ,Slave read/write" "Write,Read" eventfld.byte 0x03 1. " IICIF ,Interrupt flag" "No interrupt,Interrupt" rbitfld.byte 0x03 0. " RXAK ,Receive acknowledge" "Acknowledged,Not acknowledged" newline hgroup.byte 0x04++0x00 hide.byte 0x00 "D,IIC2 Data I/O Register" in if ((per.b(ad:0x400E6000+0x05)&0x40)==0x40) group.byte 0x05++0x00 line.byte 0x00 "C2,IIC2 Control Register 2" bitfld.byte 0x00 7. " GCAEN ,Enables general call address" "Disabled,Enabled" bitfld.byte 0x00 6. " ADEXT ,Controls the number of bits used for the slave address" "7-bit,10-bit" bitfld.byte 0x00 5. " HDRS ,Controls the drive capability of the I2C pads" "Normal,High" bitfld.byte 0x00 4. " SBRC ,Slave baud rate control" "Master baud rate,Independent" newline bitfld.byte 0x00 3. " RMEN ,Controls slave address matching for addresses between the values of the A1 and RA registers" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " AD[10:8] ,Slave address bits [10:8]" "000,001,010,011,100,101,110,111" else group.byte 0x05++0x00 line.byte 0x00 "C2,IIC2 Control Register 2" bitfld.byte 0x00 7. " GCAEN ,Enables general call address" "Disabled,Enabled" bitfld.byte 0x00 6. " ADEXT ,Controls the number of bits used for the slave address" "7-bit,10-bit" bitfld.byte 0x00 5. " HDRS ,Controls the drive capability of the I2C pads" "Normal,High" bitfld.byte 0x00 4. " SBRC ,Slave baud rate control. Enables independent slave mode baud rate at maximum frequency" "Master's,Independent" newline bitfld.byte 0x00 3. " RMEN ,Controls slave address matching for addresses between the values of the A1 and RA registers" "Disabled,Enabled" endif group.byte 0x06++0x05 line.byte 0x00 "FLT,IIC2 Programmable Input Glitch Filter Register" sif cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60FN1M0VLQ15")||cpuis("MK60DN512ZVLL10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R") bitfld.byte 0x00 0.--4. " FLT ,IIC2 programmable filter factor" "No filter,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else sif cpuis("MK21F*")||cpuis("MK22F*")||cpuis("MK02*")||cpuis("MK6*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.byte 0x00 7. " SHEN ,Stop hold enable" "Disabled,Enabled" eventfld.byte 0x00 6. " STOPF ,IIC2 bus stop detect flag" "Not detected,Detected" bitfld.byte 0x00 5. " SSIE ,I2C bus stop or start interrupt enable" "Disabled,Enabled" eventfld.byte 0x00 4. " STARTF ,I2C bus start detect flag" "Not started,Started" newline bitfld.byte 0x00 0.--3. " FLT ,IIC2 programmable filter factor" "No filter,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.byte 0x00 0.--4. " FLT ,IIC2 programmable filter factor" "No filter,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif endif line.byte 0x01 "RA,IIC2 Range Address Register" hexmask.byte 0x01 1.--7. 0x02 " RAD ,Range slave address" line.byte 0x02 "SMB,IIC2 SMBus Control and Status Register" bitfld.byte 0x02 7. " FACK ,Fast NACK/ACK enable" "NACK/ACK on following,ACK/NACK by TXAK" bitfld.byte 0x02 6. " ALERTEN ,SMBus alert response address enable" "Disabled,Enabled" bitfld.byte 0x02 5. " SIICAEN ,Second IIC2 address enable" "Disabled,Enabled" bitfld.byte 0x02 4. " TCKSEL ,Timeout counter clock select" "Clock / 64,Clock" newline eventfld.byte 0x02 3. " SLTF ,SCL low timeout flag" "Not occurred,Occurred" rbitfld.byte 0x02 2. " SHTF1 ,SCL high timeout flag 1" "Not occurred,Occurred" eventfld.byte 0x02 1. " SHTF2 ,SCL high timeout flag 2" "Not occurred,Occurred" bitfld.byte 0x02 0. " SHTF2IE ,SHTF2 interrupt enable" "Disabled,Enabled" line.byte 0x03 "A2,IIC2 Address Register 2" hexmask.byte 0x03 1.--7. 0x02 " SAD ,SMBus address" line.byte 0x04 "SLTH,IIC2 SCL Low Timeout High Register" line.byte 0x05 "SLTL,IIC2 SCL Low Timeout Low Register" sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") group.byte 0x0C++0x00 line.byte 0x00 "S2,IIC2 Status Register 2" eventfld.byte 0x00 1. " ERROR ,Read or write errors with the Tx and Rx buffers" "No error,Error" rbitfld.byte 0x00 0. " EMPTY ,Tx or Rx buffer is empty" "Not empty,Empty" endif width 0x0B tree.end tree "I2C_3" base ad:0x400E7000 width 6. group.byte 0x00++0x03 line.byte 0x00 "A1,IIC3 Address Register 1" hexmask.byte 0x00 1.--7. 0x02 " AD ,Slave address bits [7:1]" line.byte 0x01 "F,IIC3 Frequency Divider Register" bitfld.byte 0x01 6.--7. " MULT ,Multiplier factor" "1,2,4,?..." bitfld.byte 0x01 0.--5. " ICR ,Clock rate (I2C baud rate/SDA hold time/SCL start hold time/SCL stop hold time)" "20/7/6/11,22/7/7/12,24/8/8/13,26/8/9/14,28/9/10/15,30/9/11/16,34/10/13/18,40/10/16/21,28/7/10/15,32/7/12/17,36/9/14/19,40/9/16/21,44/11/18/23,48/11/20/25,56/13/24/29,68/13/30/35,48/9/18/25,56/9/22/29,64/13/26/33,72/13/30/37,80/17/34/41,88/17/38/45,104/21/46/53,128/21/58/65,80/9/38/41,96/9/46/49,112/17/54/57,128/17/62/65,144/25/70/73,160/25/78/81,192/33/94/97,240/33/118/121,160/17/78/81,192/17/94/97,224/33/110/113,256/33/126/129,288/49/142/145,320/49/158/161,384/65/190/193,480/65/238/241,320/33/158/161,384/33/190/193,448/65/222/225,512/65/254/257,576/97/286/289,640/97/318/321,768/129/382/385,960/129/478/481,640/65/318/321,768/65/382/385,896/129/446/449,1024/129/510/513,1152/193/574/577,1280/193/638/641,1536/257/766/769,1920/257/958/961,1280/129/638/641,1536/129/766/769,1792/257/894/897,2048/257/1022/1025,2304/385/1150/1153,2560/385/1278/1281,3072/513/1534/1537,3840/513/1918/1921" line.byte 0x02 "C1,IIC3 Control Register 1" bitfld.byte 0x02 7. " IICEN ,IIC3 enable" "Disabled,Enabled" bitfld.byte 0x02 6. " IICIE ,IIC3 interrupt enable" "Disabled,Enabled" bitfld.byte 0x02 5. " MST ,Master mode select" "Slave,Master" bitfld.byte 0x02 4. " TX ,Transmit mode select" "Receive,Transmit" newline bitfld.byte 0x02 3. " TXAK ,Transmit acknowledge enable" "Disabled,Enabled" bitfld.byte 0x02 2. " RSTA ,Repeat START" "No effect,Start" bitfld.byte 0x02 1. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.byte 0x02 0. " DMAEN ,DMA enable" "Disabled,Enabled" line.byte 0x03 "S,IIC3 Status Register" rbitfld.byte 0x03 7. " TCF ,Transfer complete flag" "Not completed,Completed" bitfld.byte 0x03 6. " IAAS ,Addressed as a slave" "Not addressed,Addressed" rbitfld.byte 0x03 5. " BUSY ,Bus busy" "Idle,Busy" eventfld.byte 0x03 4. " ARBL ,Arbitration lost" "Not lost,Lost" newline bitfld.byte 0x03 3. " RAM ,Range address match" "Not matched,Matched" rbitfld.byte 0x03 2. " SRW ,Slave read/write" "Write,Read" eventfld.byte 0x03 1. " IICIF ,Interrupt flag" "No interrupt,Interrupt" rbitfld.byte 0x03 0. " RXAK ,Receive acknowledge" "Acknowledged,Not acknowledged" newline hgroup.byte 0x04++0x00 hide.byte 0x00 "D,IIC3 Data I/O Register" in if ((per.b(ad:0x400E7000+0x05)&0x40)==0x40) group.byte 0x05++0x00 line.byte 0x00 "C2,IIC3 Control Register 2" bitfld.byte 0x00 7. " GCAEN ,Enables general call address" "Disabled,Enabled" bitfld.byte 0x00 6. " ADEXT ,Controls the number of bits used for the slave address" "7-bit,10-bit" bitfld.byte 0x00 5. " HDRS ,Controls the drive capability of the I2C pads" "Normal,High" bitfld.byte 0x00 4. " SBRC ,Slave baud rate control" "Master baud rate,Independent" newline bitfld.byte 0x00 3. " RMEN ,Controls slave address matching for addresses between the values of the A1 and RA registers" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " AD[10:8] ,Slave address bits [10:8]" "000,001,010,011,100,101,110,111" else group.byte 0x05++0x00 line.byte 0x00 "C2,IIC3 Control Register 2" bitfld.byte 0x00 7. " GCAEN ,Enables general call address" "Disabled,Enabled" bitfld.byte 0x00 6. " ADEXT ,Controls the number of bits used for the slave address" "7-bit,10-bit" bitfld.byte 0x00 5. " HDRS ,Controls the drive capability of the I2C pads" "Normal,High" bitfld.byte 0x00 4. " SBRC ,Slave baud rate control. Enables independent slave mode baud rate at maximum frequency" "Master's,Independent" newline bitfld.byte 0x00 3. " RMEN ,Controls slave address matching for addresses between the values of the A1 and RA registers" "Disabled,Enabled" endif group.byte 0x06++0x05 line.byte 0x00 "FLT,IIC3 Programmable Input Glitch Filter Register" sif cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60FN1M0VLQ15")||cpuis("MK60DN512ZVLL10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R") bitfld.byte 0x00 0.--4. " FLT ,IIC3 programmable filter factor" "No filter,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else sif cpuis("MK21F*")||cpuis("MK22F*")||cpuis("MK02*")||cpuis("MK6*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.byte 0x00 7. " SHEN ,Stop hold enable" "Disabled,Enabled" eventfld.byte 0x00 6. " STOPF ,IIC3 bus stop detect flag" "Not detected,Detected" bitfld.byte 0x00 5. " SSIE ,I2C bus stop or start interrupt enable" "Disabled,Enabled" eventfld.byte 0x00 4. " STARTF ,I2C bus start detect flag" "Not started,Started" newline bitfld.byte 0x00 0.--3. " FLT ,IIC3 programmable filter factor" "No filter,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.byte 0x00 0.--4. " FLT ,IIC3 programmable filter factor" "No filter,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif endif line.byte 0x01 "RA,IIC3 Range Address Register" hexmask.byte 0x01 1.--7. 0x02 " RAD ,Range slave address" line.byte 0x02 "SMB,IIC3 SMBus Control and Status Register" bitfld.byte 0x02 7. " FACK ,Fast NACK/ACK enable" "NACK/ACK on following,ACK/NACK by TXAK" bitfld.byte 0x02 6. " ALERTEN ,SMBus alert response address enable" "Disabled,Enabled" bitfld.byte 0x02 5. " SIICAEN ,Second IIC3 address enable" "Disabled,Enabled" bitfld.byte 0x02 4. " TCKSEL ,Timeout counter clock select" "Clock / 64,Clock" newline eventfld.byte 0x02 3. " SLTF ,SCL low timeout flag" "Not occurred,Occurred" rbitfld.byte 0x02 2. " SHTF1 ,SCL high timeout flag 1" "Not occurred,Occurred" eventfld.byte 0x02 1. " SHTF2 ,SCL high timeout flag 2" "Not occurred,Occurred" bitfld.byte 0x02 0. " SHTF2IE ,SHTF2 interrupt enable" "Disabled,Enabled" line.byte 0x03 "A2,IIC3 Address Register 2" hexmask.byte 0x03 1.--7. 0x02 " SAD ,SMBus address" line.byte 0x04 "SLTH,IIC3 SCL Low Timeout High Register" line.byte 0x05 "SLTL,IIC3 SCL Low Timeout Low Register" sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") group.byte 0x0C++0x00 line.byte 0x00 "S2,IIC3 Status Register 2" eventfld.byte 0x00 1. " ERROR ,Read or write errors with the Tx and Rx buffers" "No error,Error" rbitfld.byte 0x00 0. " EMPTY ,Tx or Rx buffer is empty" "Not empty,Empty" endif width 0x0B tree.end tree.end tree.open "LPUART (Low Power Universal Asynchronous Receiver/Transmitter)" tree "LPUART_0" base ad:0x400C4000 width 7. if (((per.l(ad:0x400C4000+0x08))&0xC0000)==0x0) group.long 0x00++0x07 line.long 0x00 "BAUD,LPUART0 Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Normal,Automatic" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Normal,Automatic" bitfld.long 0x00 29. " M10 ,10-bit mode select" "8 bit/9 bit,10 bit" newline bitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address Match,Idle Match,Match On/Off,RWU Enabled" bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Rising,Both" bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 stop bit,2 stop bits" newline hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" line.long 0x04 "STAT,LPUART0 Status Register" eventfld.long 0x04 31. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.long 0x04 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not occurred,Occurred" bitfld.long 0x04 29. " MSBF ,MSB first" "LSB first,MSB first" newline bitfld.long 0x04 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" bitfld.long 0x04 27. " RWUID ,Receive wake up idle detect" "Not detected,Detected" bitfld.long 0x04 26. " BRK13 ,Break character generation length" "10/11/12/13 bit,13/14/15/16 bit" newline bitfld.long 0x04 25. " LBKDE ,LIN break detection enable" "10/11/12/13 bit,11/12/14/15 bit" rbitfld.long 0x04 24. " RAF ,Receiver active flag" "Idle,Active" rbitfld.long 0x04 23. " TDRE ,Transmit data register empty flag" "Full,Empty" newline rbitfld.long 0x04 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x04 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x04 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x04 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x04 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x04 17. " FE ,Framing error flag" "No error,Error" newline eventfld.long 0x04 16. " PF ,Parity error flag" "No error,Error" eventfld.long 0x04 15. " MA1F ,Match 1 flag" "Not equal,Equal" eventfld.long 0x04 14. " MA2F ,Match 2 flag" "Not equal,Equal" elif (((per.l(ad:0x400C4000+0x08))&0x80000)==0x0) group.long 0x00++0x07 line.long 0x00 "BAUD,LPUART0 Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Normal,Automatic" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Normal,Automatic" rbitfld.long 0x00 29. " M10 ,10-bit mode select" "8 bit/9 bit,10 bit" newline rbitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address Match,Idle Match,Match On/Off,RWU Enabled" rbitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Rising,Both" rbitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 stop bit,2 stop bits" newline hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" line.long 0x04 "STAT,LPUART0 Status Register" eventfld.long 0x04 31. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.long 0x04 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not occurred,Occurred" rbitfld.long 0x04 29. " MSBF ,MSB first" "LSB first,MSB first" newline bitfld.long 0x04 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" rbitfld.long 0x04 27. " RWUID ,Receive wake up idle detect" "Not detected,Detected" bitfld.long 0x04 26. " BRK13 ,Break character generation length" "10/11/12/13 bit,13/14/15/16 bit" newline bitfld.long 0x04 25. " LBKDE ,LIN break detection enable" "10/11/12/13 bit,11/12/14/15 bit" rbitfld.long 0x04 24. " RAF ,Receiver active flag" "Idle,Active" rbitfld.long 0x04 23. " TDRE ,Transmit data register empty flag" "Full,Empty" newline rbitfld.long 0x04 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x04 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x04 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x04 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x04 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x04 17. " FE ,Framing error flag" "No error,Error" newline eventfld.long 0x04 16. " PF ,Parity error flag" "No error,Error" eventfld.long 0x04 15. " MA1F ,Match 1 flag" "Not equal,Equal" eventfld.long 0x04 14. " MA2F ,Match 2 flag" "Not equal,Equal" elif (((per.l(ad:0x400C4000+0x08))&0x40000)==0x0) group.long 0x00++0x07 line.long 0x00 "BAUD,LPUART0 Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Normal,Automatic" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Normal,Automatic" rbitfld.long 0x00 29. " M10 ,10-bit mode select" "8 bit/9 bit,10 bit" newline rbitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address Match,Idle Match,Match On/Off,RWU Enabled" bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Rising,Both" bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 stop bit,2 stop bits" newline hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" line.long 0x04 "STAT,LPUART0 Status Register" eventfld.long 0x04 31. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.long 0x04 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not occurred,Occurred" rbitfld.long 0x04 29. " MSBF ,MSB first" "LSB first,MSB first" newline bitfld.long 0x04 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" bitfld.long 0x04 27. " RWUID ,Receive wake up idle detect" "Not detected,Detected" rbitfld.long 0x04 26. " BRK13 ,Break character generation length" "10/11/12/13 bit,13/14/15/16 bit" newline bitfld.long 0x04 25. " LBKDE ,LIN break detection enable" "10/11/12/13 bit,11/12/14/15 bit" rbitfld.long 0x04 24. " RAF ,Receiver active flag" "Idle,Active" rbitfld.long 0x04 23. " TDRE ,Transmit data register empty flag" "Full,Empty" newline rbitfld.long 0x04 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x04 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x04 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x04 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x04 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x04 17. " FE ,Framing error flag" "No error,Error" newline eventfld.long 0x04 16. " PF ,Parity error flag" "No error,Error" eventfld.long 0x04 15. " MA1F ,Match 1 flag" "Not equal,Equal" eventfld.long 0x04 14. " MA2F ,Match 2 flag" "Not equal,Equal" else group.long 0x00++0x07 line.long 0x00 "BAUD,LPUART0 Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Normal,Automatic" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Normal,Automatic" rbitfld.long 0x00 29. " M10 ,10-bit mode select" "8 bit/9 bit,10 bit" newline rbitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address Match,Idle Match,Match On/Off,RWU Enabled" rbitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Rising,Both" rbitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 stop bit,2 stop bits" newline hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" line.long 0x04 "STAT,LPUART0 Status Register" eventfld.long 0x04 31. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.long 0x04 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not occurred,Occurred" rbitfld.long 0x04 29. " MSBF ,MSB first" "LSB first,MSB first" newline bitfld.long 0x04 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" rbitfld.long 0x04 27. " RWUID ,Receive wake up idle detect" "Not detected,Detected" rbitfld.long 0x04 26. " BRK13 ,Break character generation length" "10/11/12/13 bit,13/14/15/16 bit" newline bitfld.long 0x04 25. " LBKDE ,LIN break detection enable" "10/11/12/13 bit,11/12/14/15 bit" rbitfld.long 0x04 24. " RAF ,Receiver active flag" "Idle,Active" rbitfld.long 0x04 23. " TDRE ,Transmit data register empty flag" "Full,Empty" newline rbitfld.long 0x04 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x04 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x04 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x04 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x04 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x04 17. " FE ,Framing error flag" "No error,Error" newline eventfld.long 0x04 16. " PF ,Parity error flag" "No error,Error" eventfld.long 0x04 15. " MA1F ,Match 1 flag" "Not equal,Equal" eventfld.long 0x04 14. " MA2F ,Match 2 flag" "Not equal,Equal" endif if (((per.l(ad:0x400C4000+0x08))&0xC0000)==0x0) if ((per.b(ad:0x400C4000+0x8)&0x80)==0x80) group.long 0x08++0x03 line.long 0x00 "CTRL,LPUART0 Control Register" bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High" bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High" bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output" newline bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby" newline bitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break" bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars" bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop" bitfld.long 0x00 6. " DOZEEN ,Doze enable" "LPUART enabled,LPUART disabled" newline bitfld.long 0x00 5. " RSRC ,Receiver source select" "Disconnected,Connected" bitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8 bit,9 bit" bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" newline bitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit" bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" else group.long 0x08++0x03 line.long 0x00 "CTRL,LPUART0 Control Register" bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High" bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High" bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output" newline bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby" newline bitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break" bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars" bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop" bitfld.long 0x00 6. " DOZEEN ,Doze enable" "LPUART enabled,LPUART disabled" newline bitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8 bit,9 bit" bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" bitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit" newline bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" endif else if ((per.b(ad:0x400C4000+0x8)&0x80)==0x80) group.long 0x08++0x03 line.long 0x00 "CTRL,LPUART0 Control Register" rbitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High" rbitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High" rbitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output" newline rbitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" rbitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" rbitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby" newline rbitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break" rbitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars" rbitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop" rbitfld.long 0x00 6. " DOZEEN ,Doze enable" "LPUART enabled,LPUART disabled" newline rbitfld.long 0x00 5. " RSRC ,Receiver source select" "Disconnected,Connected" rbitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8 bit,9 bit" rbitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" newline rbitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit" rbitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" rbitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" else group.long 0x08++0x03 line.long 0x00 "CTRL,LPUART0 Control Register" rbitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High" rbitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High" rbitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output" newline rbitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" rbitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" rbitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby" newline rbitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break" rbitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars" rbitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop" rbitfld.long 0x00 6. " DOZEEN ,Doze enable" "LPUART enabled,LPUART disabled" newline rbitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8 bit,9 bit" rbitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" rbitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit" newline rbitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" rbitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" endif endif newline hgroup.long 0x0C++0x03 hide.long 0x00 "DATA,LPUART0 Data Register" in newline sif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")||cpuis("MKS2?FN???V??12")||cpuis("KK22FN???C?P12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VFX12*")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN???CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("?K28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") if (((per.l(ad:0x400C4000)&0xC0000000)==0xC0000000)) rgroup.long 0x10++0x03 line.long 0x00 "MATCH,LPUART0 Match Address Register" hexmask.long.word 0x00 16.--25. 1. " MA2 ,Match address 2" hexmask.long.word 0x00 0.--9. 1. " MA1 ,Match address 1" else group.long 0x10++0x03 line.long 0x00 "MATCH,LPUART0 Match Address Register" hexmask.long.word 0x00 16.--25. 1. " MA2 ,Match address 2" hexmask.long.word 0x00 0.--9. 1. " MA1 ,Match address 1" endif else group.long 0x10++0x03 line.long 0x00 "MATCH,LPUART0 Match Address Register" hexmask.long.word 0x00 16.--25. 1. " MA2 ,Match address 2" hexmask.long.word 0x00 0.--9. 1. " MA1 ,Match address 1" endif group.long 0x14++0x03 line.long 0x00 "MODIR,LPUART0 Modem IrDA Register" bitfld.long 0x00 18. " IREN ,Infrared enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR" sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*") newline hexmask.long.byte 0x00 8.--15. 1. " RTSWATER ,Receive RTS Configuration" endif newline bitfld.long 0x00 5. " TXCTSSRC ,Transmit CTS source" "LPUART_CTS,Inverted Receiver Match" newline bitfld.long 0x00 4. " TXCTSC ,Transmit CTS configuration" "At start,At idle" bitfld.long 0x00 3. " RXRTSE ,Receiver request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Low,High" newline bitfld.long 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "Disabled,Enabled" sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK27FN2M0VMI15")||cpuis("?K28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") if ((((per.l(ad:0x400C4000+0x08))&0xC0000)==0x00)&&(((per.l(ad:0x400C4000+0x18))&0x800000)==0x800000)) group.long 0x18++0x03 line.long 0x00 "FIFO,LPUART0 FIFO Register" rbitfld.long 0x00 23. " TXEMPT ,Transmit Buffer/FIFO Empty" "Not empty,Empty" rbitfld.long 0x00 22. " RXEMPT ,Receive Buffer/FIFO Empty" "Not empty,Empty" eventfld.long 0x00 17. " TXOF ,Transmitter Buffer Overflow Flag" "No overflow,Overflow" eventfld.long 0x00 16. " RXUF ,Receiver Buffer Underflow Flag" "No underfow,Underflow" newline bitfld.long 0x00 15. " TXFLUSH ,Transmit FIFO/Buffer Flush" "No effect,Flush" bitfld.long 0x00 14. " RXFLUSH ,Receive FIFO/Buffer Flush" "No effect,Flush" bitfld.long 0x00 10.--12. " RXIDEN ,Receiver Idle Empty Enable. Enable RDRF assertion due to partially filled FIFO when receiver is idle for defined number of characters" "Disabled,1,2,4,8,16,32,64" bitfld.long 0x00 9. " TXOFE ,Transmit FIFO Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " RXUFE ,Receive FIFO Underflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 7. " TXFE ,Transmit FIFO Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO. Buffer Depth (datawords)" "1,4,8,16,32,64,128,256" bitfld.long 0x00 3. " RXFE ,Receive FIFO Enable" "Disabled,Enabled" newline rbitfld.long 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO. Buffer Depth (datawords)" "1,4,8,16,32,64,128,256" else rgroup.long 0x18++0x03 line.long 0x00 "FIFO,LPUART0 FIFO Register" bitfld.long 0x00 23. " TXEMPT ,Transmit Buffer/FIFO Empty" "Not empty,Empty" bitfld.long 0x00 22. " RXEMPT ,Receive Buffer/FIFO Empty" "Not empty,Empty" bitfld.long 0x00 17. " TXOF ,Transmitter Buffer Overflow Flag" "No overflow,Overflow" bitfld.long 0x00 16. " RXUF ,Receiver Buffer Underflow Flag" "No underfow,Underflow" newline bitfld.long 0x00 15. " TXFLUSH ,Transmit FIFO/Buffer Flush" "No effect,Flush" bitfld.long 0x00 14. " RXFLUSH ,Receive FIFO/Buffer Flush" "No effect,Flush" bitfld.long 0x00 10.--12. " RXIDEN ,Receiver Idle Empty Enable. Enable RDRF assertion due to partially filled FIFO when receiver is idle for defined number of characters" "Disabled,1,2,4,8,16,32,64" bitfld.long 0x00 9. " TXOFE ,Transmit FIFO Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " RXUFE ,Receive FIFO Underflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 7. " TXFE ,Transmit FIFO Enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO. Buffer Depth (datawords)" "1,4,8,16,32,64,128,256" bitfld.long 0x00 3. " RXFE ,Receive FIFO Enable" "Disabled,Enabled" newline bitfld.long 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO. Buffer Depth (datawords)" "1,4,8,16,32,64,128,256" endif if (((per.l(ad:0x400C4000+0x08))&0x80000)==0x80000) rgroup.long 0x1C++0x03 line.long 0x00 "WATER,LPUART0 Watermark Register" hexmask.long.byte 0x00 24.--31. 1. " RXCOUNT ,Receive Counter" hexmask.long.byte 0x00 16.--23. 1. " RXWATER ,Receive Watermark" hexmask.long.byte 0x00 8.--15. 1. " TXCOUNT ,Transmit Counter" hexmask.long.byte 0x00 0.--7. 1. " TXWATER ,Transmit Watermark" else group.long 0x1C++0x03 line.long 0x00 "WATER,LPUART0 Watermark Register" hexmask.long.byte 0x00 24.--31. 1. " RXCOUNT ,Receive Counter" hexmask.long.byte 0x00 16.--23. 1. " RXWATER ,Receive Watermark" hexmask.long.byte 0x00 8.--15. 1. " TXCOUNT ,Transmit Counter" hexmask.long.byte 0x00 0.--7. 1. " TXWATER ,Transmit Watermark" endif endif width 0x0B tree.end tree "LPUART_1" base ad:0x400C5000 width 7. if (((per.l(ad:0x400C5000+0x08))&0xC0000)==0x0) group.long 0x00++0x07 line.long 0x00 "BAUD,LPUART1 Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Normal,Automatic" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Normal,Automatic" bitfld.long 0x00 29. " M10 ,10-bit mode select" "8 bit/9 bit,10 bit" newline bitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address Match,Idle Match,Match On/Off,RWU Enabled" bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Rising,Both" bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 stop bit,2 stop bits" newline hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" line.long 0x04 "STAT,LPUART1 Status Register" eventfld.long 0x04 31. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.long 0x04 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not occurred,Occurred" bitfld.long 0x04 29. " MSBF ,MSB first" "LSB first,MSB first" newline bitfld.long 0x04 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" bitfld.long 0x04 27. " RWUID ,Receive wake up idle detect" "Not detected,Detected" bitfld.long 0x04 26. " BRK13 ,Break character generation length" "10/11/12/13 bit,13/14/15/16 bit" newline bitfld.long 0x04 25. " LBKDE ,LIN break detection enable" "10/11/12/13 bit,11/12/14/15 bit" rbitfld.long 0x04 24. " RAF ,Receiver active flag" "Idle,Active" rbitfld.long 0x04 23. " TDRE ,Transmit data register empty flag" "Full,Empty" newline rbitfld.long 0x04 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x04 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x04 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x04 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x04 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x04 17. " FE ,Framing error flag" "No error,Error" newline eventfld.long 0x04 16. " PF ,Parity error flag" "No error,Error" eventfld.long 0x04 15. " MA1F ,Match 1 flag" "Not equal,Equal" eventfld.long 0x04 14. " MA2F ,Match 2 flag" "Not equal,Equal" elif (((per.l(ad:0x400C5000+0x08))&0x80000)==0x0) group.long 0x00++0x07 line.long 0x00 "BAUD,LPUART1 Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Normal,Automatic" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Normal,Automatic" rbitfld.long 0x00 29. " M10 ,10-bit mode select" "8 bit/9 bit,10 bit" newline rbitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address Match,Idle Match,Match On/Off,RWU Enabled" rbitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Rising,Both" rbitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 stop bit,2 stop bits" newline hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" line.long 0x04 "STAT,LPUART1 Status Register" eventfld.long 0x04 31. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.long 0x04 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not occurred,Occurred" rbitfld.long 0x04 29. " MSBF ,MSB first" "LSB first,MSB first" newline bitfld.long 0x04 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" rbitfld.long 0x04 27. " RWUID ,Receive wake up idle detect" "Not detected,Detected" bitfld.long 0x04 26. " BRK13 ,Break character generation length" "10/11/12/13 bit,13/14/15/16 bit" newline bitfld.long 0x04 25. " LBKDE ,LIN break detection enable" "10/11/12/13 bit,11/12/14/15 bit" rbitfld.long 0x04 24. " RAF ,Receiver active flag" "Idle,Active" rbitfld.long 0x04 23. " TDRE ,Transmit data register empty flag" "Full,Empty" newline rbitfld.long 0x04 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x04 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x04 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x04 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x04 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x04 17. " FE ,Framing error flag" "No error,Error" newline eventfld.long 0x04 16. " PF ,Parity error flag" "No error,Error" eventfld.long 0x04 15. " MA1F ,Match 1 flag" "Not equal,Equal" eventfld.long 0x04 14. " MA2F ,Match 2 flag" "Not equal,Equal" elif (((per.l(ad:0x400C5000+0x08))&0x40000)==0x0) group.long 0x00++0x07 line.long 0x00 "BAUD,LPUART1 Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Normal,Automatic" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Normal,Automatic" rbitfld.long 0x00 29. " M10 ,10-bit mode select" "8 bit/9 bit,10 bit" newline rbitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address Match,Idle Match,Match On/Off,RWU Enabled" bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Rising,Both" bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 stop bit,2 stop bits" newline hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" line.long 0x04 "STAT,LPUART1 Status Register" eventfld.long 0x04 31. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.long 0x04 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not occurred,Occurred" rbitfld.long 0x04 29. " MSBF ,MSB first" "LSB first,MSB first" newline bitfld.long 0x04 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" bitfld.long 0x04 27. " RWUID ,Receive wake up idle detect" "Not detected,Detected" rbitfld.long 0x04 26. " BRK13 ,Break character generation length" "10/11/12/13 bit,13/14/15/16 bit" newline bitfld.long 0x04 25. " LBKDE ,LIN break detection enable" "10/11/12/13 bit,11/12/14/15 bit" rbitfld.long 0x04 24. " RAF ,Receiver active flag" "Idle,Active" rbitfld.long 0x04 23. " TDRE ,Transmit data register empty flag" "Full,Empty" newline rbitfld.long 0x04 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x04 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x04 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x04 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x04 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x04 17. " FE ,Framing error flag" "No error,Error" newline eventfld.long 0x04 16. " PF ,Parity error flag" "No error,Error" eventfld.long 0x04 15. " MA1F ,Match 1 flag" "Not equal,Equal" eventfld.long 0x04 14. " MA2F ,Match 2 flag" "Not equal,Equal" else group.long 0x00++0x07 line.long 0x00 "BAUD,LPUART1 Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Normal,Automatic" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Normal,Automatic" rbitfld.long 0x00 29. " M10 ,10-bit mode select" "8 bit/9 bit,10 bit" newline rbitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address Match,Idle Match,Match On/Off,RWU Enabled" rbitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Rising,Both" rbitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 stop bit,2 stop bits" newline hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" line.long 0x04 "STAT,LPUART1 Status Register" eventfld.long 0x04 31. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.long 0x04 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not occurred,Occurred" rbitfld.long 0x04 29. " MSBF ,MSB first" "LSB first,MSB first" newline bitfld.long 0x04 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" rbitfld.long 0x04 27. " RWUID ,Receive wake up idle detect" "Not detected,Detected" rbitfld.long 0x04 26. " BRK13 ,Break character generation length" "10/11/12/13 bit,13/14/15/16 bit" newline bitfld.long 0x04 25. " LBKDE ,LIN break detection enable" "10/11/12/13 bit,11/12/14/15 bit" rbitfld.long 0x04 24. " RAF ,Receiver active flag" "Idle,Active" rbitfld.long 0x04 23. " TDRE ,Transmit data register empty flag" "Full,Empty" newline rbitfld.long 0x04 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x04 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x04 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x04 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x04 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x04 17. " FE ,Framing error flag" "No error,Error" newline eventfld.long 0x04 16. " PF ,Parity error flag" "No error,Error" eventfld.long 0x04 15. " MA1F ,Match 1 flag" "Not equal,Equal" eventfld.long 0x04 14. " MA2F ,Match 2 flag" "Not equal,Equal" endif if (((per.l(ad:0x400C5000+0x08))&0xC0000)==0x0) if ((per.b(ad:0x400C5000+0x8)&0x80)==0x80) group.long 0x08++0x03 line.long 0x00 "CTRL,LPUART1 Control Register" bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High" bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High" bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output" newline bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby" newline bitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break" bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars" bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop" bitfld.long 0x00 6. " DOZEEN ,Doze enable" "LPUART enabled,LPUART disabled" newline bitfld.long 0x00 5. " RSRC ,Receiver source select" "Disconnected,Connected" bitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8 bit,9 bit" bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" newline bitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit" bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" else group.long 0x08++0x03 line.long 0x00 "CTRL,LPUART1 Control Register" bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High" bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High" bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output" newline bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby" newline bitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break" bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars" bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop" bitfld.long 0x00 6. " DOZEEN ,Doze enable" "LPUART enabled,LPUART disabled" newline bitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8 bit,9 bit" bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" bitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit" newline bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" endif else if ((per.b(ad:0x400C5000+0x8)&0x80)==0x80) group.long 0x08++0x03 line.long 0x00 "CTRL,LPUART1 Control Register" rbitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High" rbitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High" rbitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output" newline rbitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" rbitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" rbitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby" newline rbitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break" rbitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars" rbitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop" rbitfld.long 0x00 6. " DOZEEN ,Doze enable" "LPUART enabled,LPUART disabled" newline rbitfld.long 0x00 5. " RSRC ,Receiver source select" "Disconnected,Connected" rbitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8 bit,9 bit" rbitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" newline rbitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit" rbitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" rbitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" else group.long 0x08++0x03 line.long 0x00 "CTRL,LPUART1 Control Register" rbitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High" rbitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High" rbitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output" newline rbitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" rbitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" rbitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby" newline rbitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break" rbitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars" rbitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop" rbitfld.long 0x00 6. " DOZEEN ,Doze enable" "LPUART enabled,LPUART disabled" newline rbitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8 bit,9 bit" rbitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" rbitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit" newline rbitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" rbitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" endif endif newline hgroup.long 0x0C++0x03 hide.long 0x00 "DATA,LPUART1 Data Register" in newline sif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")||cpuis("MKS2?FN???V??12")||cpuis("KK22FN???C?P12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VFX12*")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN???CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("?K28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") if (((per.l(ad:0x400C5000)&0xC0000000)==0xC0000000)) rgroup.long 0x10++0x03 line.long 0x00 "MATCH,LPUART1 Match Address Register" hexmask.long.word 0x00 16.--25. 1. " MA2 ,Match address 2" hexmask.long.word 0x00 0.--9. 1. " MA1 ,Match address 1" else group.long 0x10++0x03 line.long 0x00 "MATCH,LPUART1 Match Address Register" hexmask.long.word 0x00 16.--25. 1. " MA2 ,Match address 2" hexmask.long.word 0x00 0.--9. 1. " MA1 ,Match address 1" endif else group.long 0x10++0x03 line.long 0x00 "MATCH,LPUART1 Match Address Register" hexmask.long.word 0x00 16.--25. 1. " MA2 ,Match address 2" hexmask.long.word 0x00 0.--9. 1. " MA1 ,Match address 1" endif group.long 0x14++0x03 line.long 0x00 "MODIR,LPUART1 Modem IrDA Register" bitfld.long 0x00 18. " IREN ,Infrared enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR" sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*") newline hexmask.long.byte 0x00 8.--15. 1. " RTSWATER ,Receive RTS Configuration" endif newline bitfld.long 0x00 5. " TXCTSSRC ,Transmit CTS source" "LPUART_CTS,Inverted Receiver Match" newline bitfld.long 0x00 4. " TXCTSC ,Transmit CTS configuration" "At start,At idle" bitfld.long 0x00 3. " RXRTSE ,Receiver request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Low,High" newline bitfld.long 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "Disabled,Enabled" sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK27FN2M0VMI15")||cpuis("?K28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") if ((((per.l(ad:0x400C5000+0x08))&0xC0000)==0x00)&&(((per.l(ad:0x400C5000+0x18))&0x800000)==0x800000)) group.long 0x18++0x03 line.long 0x00 "FIFO,LPUART1 FIFO Register" rbitfld.long 0x00 23. " TXEMPT ,Transmit Buffer/FIFO Empty" "Not empty,Empty" rbitfld.long 0x00 22. " RXEMPT ,Receive Buffer/FIFO Empty" "Not empty,Empty" eventfld.long 0x00 17. " TXOF ,Transmitter Buffer Overflow Flag" "No overflow,Overflow" eventfld.long 0x00 16. " RXUF ,Receiver Buffer Underflow Flag" "No underfow,Underflow" newline bitfld.long 0x00 15. " TXFLUSH ,Transmit FIFO/Buffer Flush" "No effect,Flush" bitfld.long 0x00 14. " RXFLUSH ,Receive FIFO/Buffer Flush" "No effect,Flush" bitfld.long 0x00 10.--12. " RXIDEN ,Receiver Idle Empty Enable. Enable RDRF assertion due to partially filled FIFO when receiver is idle for defined number of characters" "Disabled,1,2,4,8,16,32,64" bitfld.long 0x00 9. " TXOFE ,Transmit FIFO Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " RXUFE ,Receive FIFO Underflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 7. " TXFE ,Transmit FIFO Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO. Buffer Depth (datawords)" "1,4,8,16,32,64,128,256" bitfld.long 0x00 3. " RXFE ,Receive FIFO Enable" "Disabled,Enabled" newline rbitfld.long 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO. Buffer Depth (datawords)" "1,4,8,16,32,64,128,256" else rgroup.long 0x18++0x03 line.long 0x00 "FIFO,LPUART1 FIFO Register" bitfld.long 0x00 23. " TXEMPT ,Transmit Buffer/FIFO Empty" "Not empty,Empty" bitfld.long 0x00 22. " RXEMPT ,Receive Buffer/FIFO Empty" "Not empty,Empty" bitfld.long 0x00 17. " TXOF ,Transmitter Buffer Overflow Flag" "No overflow,Overflow" bitfld.long 0x00 16. " RXUF ,Receiver Buffer Underflow Flag" "No underfow,Underflow" newline bitfld.long 0x00 15. " TXFLUSH ,Transmit FIFO/Buffer Flush" "No effect,Flush" bitfld.long 0x00 14. " RXFLUSH ,Receive FIFO/Buffer Flush" "No effect,Flush" bitfld.long 0x00 10.--12. " RXIDEN ,Receiver Idle Empty Enable. Enable RDRF assertion due to partially filled FIFO when receiver is idle for defined number of characters" "Disabled,1,2,4,8,16,32,64" bitfld.long 0x00 9. " TXOFE ,Transmit FIFO Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " RXUFE ,Receive FIFO Underflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 7. " TXFE ,Transmit FIFO Enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO. Buffer Depth (datawords)" "1,4,8,16,32,64,128,256" bitfld.long 0x00 3. " RXFE ,Receive FIFO Enable" "Disabled,Enabled" newline bitfld.long 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO. Buffer Depth (datawords)" "1,4,8,16,32,64,128,256" endif if (((per.l(ad:0x400C5000+0x08))&0x80000)==0x80000) rgroup.long 0x1C++0x03 line.long 0x00 "WATER,LPUART1 Watermark Register" hexmask.long.byte 0x00 24.--31. 1. " RXCOUNT ,Receive Counter" hexmask.long.byte 0x00 16.--23. 1. " RXWATER ,Receive Watermark" hexmask.long.byte 0x00 8.--15. 1. " TXCOUNT ,Transmit Counter" hexmask.long.byte 0x00 0.--7. 1. " TXWATER ,Transmit Watermark" else group.long 0x1C++0x03 line.long 0x00 "WATER,LPUART1 Watermark Register" hexmask.long.byte 0x00 24.--31. 1. " RXCOUNT ,Receive Counter" hexmask.long.byte 0x00 16.--23. 1. " RXWATER ,Receive Watermark" hexmask.long.byte 0x00 8.--15. 1. " TXCOUNT ,Transmit Counter" hexmask.long.byte 0x00 0.--7. 1. " TXWATER ,Transmit Watermark" endif endif width 0x0B tree.end tree "LPUART_2" base ad:0x400C6000 width 7. if (((per.l(ad:0x400C6000+0x08))&0xC0000)==0x0) group.long 0x00++0x07 line.long 0x00 "BAUD,LPUART2 Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Normal,Automatic" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Normal,Automatic" bitfld.long 0x00 29. " M10 ,10-bit mode select" "8 bit/9 bit,10 bit" newline bitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address Match,Idle Match,Match On/Off,RWU Enabled" bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Rising,Both" bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 stop bit,2 stop bits" newline hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" line.long 0x04 "STAT,LPUART2 Status Register" eventfld.long 0x04 31. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.long 0x04 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not occurred,Occurred" bitfld.long 0x04 29. " MSBF ,MSB first" "LSB first,MSB first" newline bitfld.long 0x04 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" bitfld.long 0x04 27. " RWUID ,Receive wake up idle detect" "Not detected,Detected" bitfld.long 0x04 26. " BRK13 ,Break character generation length" "10/11/12/13 bit,13/14/15/16 bit" newline bitfld.long 0x04 25. " LBKDE ,LIN break detection enable" "10/11/12/13 bit,11/12/14/15 bit" rbitfld.long 0x04 24. " RAF ,Receiver active flag" "Idle,Active" rbitfld.long 0x04 23. " TDRE ,Transmit data register empty flag" "Full,Empty" newline rbitfld.long 0x04 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x04 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x04 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x04 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x04 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x04 17. " FE ,Framing error flag" "No error,Error" newline eventfld.long 0x04 16. " PF ,Parity error flag" "No error,Error" eventfld.long 0x04 15. " MA1F ,Match 1 flag" "Not equal,Equal" eventfld.long 0x04 14. " MA2F ,Match 2 flag" "Not equal,Equal" elif (((per.l(ad:0x400C6000+0x08))&0x80000)==0x0) group.long 0x00++0x07 line.long 0x00 "BAUD,LPUART2 Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Normal,Automatic" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Normal,Automatic" rbitfld.long 0x00 29. " M10 ,10-bit mode select" "8 bit/9 bit,10 bit" newline rbitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address Match,Idle Match,Match On/Off,RWU Enabled" rbitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Rising,Both" rbitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 stop bit,2 stop bits" newline hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" line.long 0x04 "STAT,LPUART2 Status Register" eventfld.long 0x04 31. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.long 0x04 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not occurred,Occurred" rbitfld.long 0x04 29. " MSBF ,MSB first" "LSB first,MSB first" newline bitfld.long 0x04 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" rbitfld.long 0x04 27. " RWUID ,Receive wake up idle detect" "Not detected,Detected" bitfld.long 0x04 26. " BRK13 ,Break character generation length" "10/11/12/13 bit,13/14/15/16 bit" newline bitfld.long 0x04 25. " LBKDE ,LIN break detection enable" "10/11/12/13 bit,11/12/14/15 bit" rbitfld.long 0x04 24. " RAF ,Receiver active flag" "Idle,Active" rbitfld.long 0x04 23. " TDRE ,Transmit data register empty flag" "Full,Empty" newline rbitfld.long 0x04 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x04 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x04 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x04 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x04 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x04 17. " FE ,Framing error flag" "No error,Error" newline eventfld.long 0x04 16. " PF ,Parity error flag" "No error,Error" eventfld.long 0x04 15. " MA1F ,Match 1 flag" "Not equal,Equal" eventfld.long 0x04 14. " MA2F ,Match 2 flag" "Not equal,Equal" elif (((per.l(ad:0x400C6000+0x08))&0x40000)==0x0) group.long 0x00++0x07 line.long 0x00 "BAUD,LPUART2 Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Normal,Automatic" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Normal,Automatic" rbitfld.long 0x00 29. " M10 ,10-bit mode select" "8 bit/9 bit,10 bit" newline rbitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address Match,Idle Match,Match On/Off,RWU Enabled" bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Rising,Both" bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 stop bit,2 stop bits" newline hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" line.long 0x04 "STAT,LPUART2 Status Register" eventfld.long 0x04 31. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.long 0x04 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not occurred,Occurred" rbitfld.long 0x04 29. " MSBF ,MSB first" "LSB first,MSB first" newline bitfld.long 0x04 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" bitfld.long 0x04 27. " RWUID ,Receive wake up idle detect" "Not detected,Detected" rbitfld.long 0x04 26. " BRK13 ,Break character generation length" "10/11/12/13 bit,13/14/15/16 bit" newline bitfld.long 0x04 25. " LBKDE ,LIN break detection enable" "10/11/12/13 bit,11/12/14/15 bit" rbitfld.long 0x04 24. " RAF ,Receiver active flag" "Idle,Active" rbitfld.long 0x04 23. " TDRE ,Transmit data register empty flag" "Full,Empty" newline rbitfld.long 0x04 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x04 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x04 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x04 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x04 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x04 17. " FE ,Framing error flag" "No error,Error" newline eventfld.long 0x04 16. " PF ,Parity error flag" "No error,Error" eventfld.long 0x04 15. " MA1F ,Match 1 flag" "Not equal,Equal" eventfld.long 0x04 14. " MA2F ,Match 2 flag" "Not equal,Equal" else group.long 0x00++0x07 line.long 0x00 "BAUD,LPUART2 Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Normal,Automatic" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Normal,Automatic" rbitfld.long 0x00 29. " M10 ,10-bit mode select" "8 bit/9 bit,10 bit" newline rbitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address Match,Idle Match,Match On/Off,RWU Enabled" rbitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Rising,Both" rbitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 stop bit,2 stop bits" newline hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" line.long 0x04 "STAT,LPUART2 Status Register" eventfld.long 0x04 31. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.long 0x04 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not occurred,Occurred" rbitfld.long 0x04 29. " MSBF ,MSB first" "LSB first,MSB first" newline bitfld.long 0x04 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" rbitfld.long 0x04 27. " RWUID ,Receive wake up idle detect" "Not detected,Detected" rbitfld.long 0x04 26. " BRK13 ,Break character generation length" "10/11/12/13 bit,13/14/15/16 bit" newline bitfld.long 0x04 25. " LBKDE ,LIN break detection enable" "10/11/12/13 bit,11/12/14/15 bit" rbitfld.long 0x04 24. " RAF ,Receiver active flag" "Idle,Active" rbitfld.long 0x04 23. " TDRE ,Transmit data register empty flag" "Full,Empty" newline rbitfld.long 0x04 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x04 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x04 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x04 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x04 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x04 17. " FE ,Framing error flag" "No error,Error" newline eventfld.long 0x04 16. " PF ,Parity error flag" "No error,Error" eventfld.long 0x04 15. " MA1F ,Match 1 flag" "Not equal,Equal" eventfld.long 0x04 14. " MA2F ,Match 2 flag" "Not equal,Equal" endif if (((per.l(ad:0x400C6000+0x08))&0xC0000)==0x0) if ((per.b(ad:0x400C6000+0x8)&0x80)==0x80) group.long 0x08++0x03 line.long 0x00 "CTRL,LPUART2 Control Register" bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High" bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High" bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output" newline bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby" newline bitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break" bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars" bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop" bitfld.long 0x00 6. " DOZEEN ,Doze enable" "LPUART enabled,LPUART disabled" newline bitfld.long 0x00 5. " RSRC ,Receiver source select" "Disconnected,Connected" bitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8 bit,9 bit" bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" newline bitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit" bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" else group.long 0x08++0x03 line.long 0x00 "CTRL,LPUART2 Control Register" bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High" bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High" bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output" newline bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby" newline bitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break" bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars" bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop" bitfld.long 0x00 6. " DOZEEN ,Doze enable" "LPUART enabled,LPUART disabled" newline bitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8 bit,9 bit" bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" bitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit" newline bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" endif else if ((per.b(ad:0x400C6000+0x8)&0x80)==0x80) group.long 0x08++0x03 line.long 0x00 "CTRL,LPUART2 Control Register" rbitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High" rbitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High" rbitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output" newline rbitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" rbitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" rbitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby" newline rbitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break" rbitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars" rbitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop" rbitfld.long 0x00 6. " DOZEEN ,Doze enable" "LPUART enabled,LPUART disabled" newline rbitfld.long 0x00 5. " RSRC ,Receiver source select" "Disconnected,Connected" rbitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8 bit,9 bit" rbitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" newline rbitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit" rbitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" rbitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" else group.long 0x08++0x03 line.long 0x00 "CTRL,LPUART2 Control Register" rbitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High" rbitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High" rbitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output" newline rbitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" rbitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" rbitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby" newline rbitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break" rbitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars" rbitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop" rbitfld.long 0x00 6. " DOZEEN ,Doze enable" "LPUART enabled,LPUART disabled" newline rbitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8 bit,9 bit" rbitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" rbitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit" newline rbitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" rbitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" endif endif newline hgroup.long 0x0C++0x03 hide.long 0x00 "DATA,LPUART2 Data Register" in newline sif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")||cpuis("MKS2?FN???V??12")||cpuis("KK22FN???C?P12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VFX12*")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN???CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("?K28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") if (((per.l(ad:0x400C6000)&0xC0000000)==0xC0000000)) rgroup.long 0x10++0x03 line.long 0x00 "MATCH,LPUART2 Match Address Register" hexmask.long.word 0x00 16.--25. 1. " MA2 ,Match address 2" hexmask.long.word 0x00 0.--9. 1. " MA1 ,Match address 1" else group.long 0x10++0x03 line.long 0x00 "MATCH,LPUART2 Match Address Register" hexmask.long.word 0x00 16.--25. 1. " MA2 ,Match address 2" hexmask.long.word 0x00 0.--9. 1. " MA1 ,Match address 1" endif else group.long 0x10++0x03 line.long 0x00 "MATCH,LPUART2 Match Address Register" hexmask.long.word 0x00 16.--25. 1. " MA2 ,Match address 2" hexmask.long.word 0x00 0.--9. 1. " MA1 ,Match address 1" endif group.long 0x14++0x03 line.long 0x00 "MODIR,LPUART2 Modem IrDA Register" bitfld.long 0x00 18. " IREN ,Infrared enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR" sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*") newline hexmask.long.byte 0x00 8.--15. 1. " RTSWATER ,Receive RTS Configuration" endif newline bitfld.long 0x00 5. " TXCTSSRC ,Transmit CTS source" "LPUART_CTS,Inverted Receiver Match" newline bitfld.long 0x00 4. " TXCTSC ,Transmit CTS configuration" "At start,At idle" bitfld.long 0x00 3. " RXRTSE ,Receiver request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Low,High" newline bitfld.long 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "Disabled,Enabled" sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK27FN2M0VMI15")||cpuis("?K28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") if ((((per.l(ad:0x400C6000+0x08))&0xC0000)==0x00)&&(((per.l(ad:0x400C6000+0x18))&0x800000)==0x800000)) group.long 0x18++0x03 line.long 0x00 "FIFO,LPUART2 FIFO Register" rbitfld.long 0x00 23. " TXEMPT ,Transmit Buffer/FIFO Empty" "Not empty,Empty" rbitfld.long 0x00 22. " RXEMPT ,Receive Buffer/FIFO Empty" "Not empty,Empty" eventfld.long 0x00 17. " TXOF ,Transmitter Buffer Overflow Flag" "No overflow,Overflow" eventfld.long 0x00 16. " RXUF ,Receiver Buffer Underflow Flag" "No underfow,Underflow" newline bitfld.long 0x00 15. " TXFLUSH ,Transmit FIFO/Buffer Flush" "No effect,Flush" bitfld.long 0x00 14. " RXFLUSH ,Receive FIFO/Buffer Flush" "No effect,Flush" bitfld.long 0x00 10.--12. " RXIDEN ,Receiver Idle Empty Enable. Enable RDRF assertion due to partially filled FIFO when receiver is idle for defined number of characters" "Disabled,1,2,4,8,16,32,64" bitfld.long 0x00 9. " TXOFE ,Transmit FIFO Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " RXUFE ,Receive FIFO Underflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 7. " TXFE ,Transmit FIFO Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO. Buffer Depth (datawords)" "1,4,8,16,32,64,128,256" bitfld.long 0x00 3. " RXFE ,Receive FIFO Enable" "Disabled,Enabled" newline rbitfld.long 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO. Buffer Depth (datawords)" "1,4,8,16,32,64,128,256" else rgroup.long 0x18++0x03 line.long 0x00 "FIFO,LPUART2 FIFO Register" bitfld.long 0x00 23. " TXEMPT ,Transmit Buffer/FIFO Empty" "Not empty,Empty" bitfld.long 0x00 22. " RXEMPT ,Receive Buffer/FIFO Empty" "Not empty,Empty" bitfld.long 0x00 17. " TXOF ,Transmitter Buffer Overflow Flag" "No overflow,Overflow" bitfld.long 0x00 16. " RXUF ,Receiver Buffer Underflow Flag" "No underfow,Underflow" newline bitfld.long 0x00 15. " TXFLUSH ,Transmit FIFO/Buffer Flush" "No effect,Flush" bitfld.long 0x00 14. " RXFLUSH ,Receive FIFO/Buffer Flush" "No effect,Flush" bitfld.long 0x00 10.--12. " RXIDEN ,Receiver Idle Empty Enable. Enable RDRF assertion due to partially filled FIFO when receiver is idle for defined number of characters" "Disabled,1,2,4,8,16,32,64" bitfld.long 0x00 9. " TXOFE ,Transmit FIFO Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " RXUFE ,Receive FIFO Underflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 7. " TXFE ,Transmit FIFO Enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO. Buffer Depth (datawords)" "1,4,8,16,32,64,128,256" bitfld.long 0x00 3. " RXFE ,Receive FIFO Enable" "Disabled,Enabled" newline bitfld.long 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO. Buffer Depth (datawords)" "1,4,8,16,32,64,128,256" endif if (((per.l(ad:0x400C6000+0x08))&0x80000)==0x80000) rgroup.long 0x1C++0x03 line.long 0x00 "WATER,LPUART2 Watermark Register" hexmask.long.byte 0x00 24.--31. 1. " RXCOUNT ,Receive Counter" hexmask.long.byte 0x00 16.--23. 1. " RXWATER ,Receive Watermark" hexmask.long.byte 0x00 8.--15. 1. " TXCOUNT ,Transmit Counter" hexmask.long.byte 0x00 0.--7. 1. " TXWATER ,Transmit Watermark" else group.long 0x1C++0x03 line.long 0x00 "WATER,LPUART2 Watermark Register" hexmask.long.byte 0x00 24.--31. 1. " RXCOUNT ,Receive Counter" hexmask.long.byte 0x00 16.--23. 1. " RXWATER ,Receive Watermark" hexmask.long.byte 0x00 8.--15. 1. " TXCOUNT ,Transmit Counter" hexmask.long.byte 0x00 0.--7. 1. " TXWATER ,Transmit Watermark" endif endif width 0x0B tree.end tree "LPUART_3" base ad:0x400C7000 width 7. if (((per.l(ad:0x400C7000+0x08))&0xC0000)==0x0) group.long 0x00++0x07 line.long 0x00 "BAUD,LPUART3 Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Normal,Automatic" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Normal,Automatic" bitfld.long 0x00 29. " M10 ,10-bit mode select" "8 bit/9 bit,10 bit" newline bitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address Match,Idle Match,Match On/Off,RWU Enabled" bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Rising,Both" bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 stop bit,2 stop bits" newline hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" line.long 0x04 "STAT,LPUART3 Status Register" eventfld.long 0x04 31. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.long 0x04 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not occurred,Occurred" bitfld.long 0x04 29. " MSBF ,MSB first" "LSB first,MSB first" newline bitfld.long 0x04 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" bitfld.long 0x04 27. " RWUID ,Receive wake up idle detect" "Not detected,Detected" bitfld.long 0x04 26. " BRK13 ,Break character generation length" "10/11/12/13 bit,13/14/15/16 bit" newline bitfld.long 0x04 25. " LBKDE ,LIN break detection enable" "10/11/12/13 bit,11/12/14/15 bit" rbitfld.long 0x04 24. " RAF ,Receiver active flag" "Idle,Active" rbitfld.long 0x04 23. " TDRE ,Transmit data register empty flag" "Full,Empty" newline rbitfld.long 0x04 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x04 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x04 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x04 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x04 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x04 17. " FE ,Framing error flag" "No error,Error" newline eventfld.long 0x04 16. " PF ,Parity error flag" "No error,Error" eventfld.long 0x04 15. " MA1F ,Match 1 flag" "Not equal,Equal" eventfld.long 0x04 14. " MA2F ,Match 2 flag" "Not equal,Equal" elif (((per.l(ad:0x400C7000+0x08))&0x80000)==0x0) group.long 0x00++0x07 line.long 0x00 "BAUD,LPUART3 Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Normal,Automatic" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Normal,Automatic" rbitfld.long 0x00 29. " M10 ,10-bit mode select" "8 bit/9 bit,10 bit" newline rbitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address Match,Idle Match,Match On/Off,RWU Enabled" rbitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Rising,Both" rbitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 stop bit,2 stop bits" newline hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" line.long 0x04 "STAT,LPUART3 Status Register" eventfld.long 0x04 31. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.long 0x04 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not occurred,Occurred" rbitfld.long 0x04 29. " MSBF ,MSB first" "LSB first,MSB first" newline bitfld.long 0x04 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" rbitfld.long 0x04 27. " RWUID ,Receive wake up idle detect" "Not detected,Detected" bitfld.long 0x04 26. " BRK13 ,Break character generation length" "10/11/12/13 bit,13/14/15/16 bit" newline bitfld.long 0x04 25. " LBKDE ,LIN break detection enable" "10/11/12/13 bit,11/12/14/15 bit" rbitfld.long 0x04 24. " RAF ,Receiver active flag" "Idle,Active" rbitfld.long 0x04 23. " TDRE ,Transmit data register empty flag" "Full,Empty" newline rbitfld.long 0x04 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x04 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x04 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x04 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x04 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x04 17. " FE ,Framing error flag" "No error,Error" newline eventfld.long 0x04 16. " PF ,Parity error flag" "No error,Error" eventfld.long 0x04 15. " MA1F ,Match 1 flag" "Not equal,Equal" eventfld.long 0x04 14. " MA2F ,Match 2 flag" "Not equal,Equal" elif (((per.l(ad:0x400C7000+0x08))&0x40000)==0x0) group.long 0x00++0x07 line.long 0x00 "BAUD,LPUART3 Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Normal,Automatic" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Normal,Automatic" rbitfld.long 0x00 29. " M10 ,10-bit mode select" "8 bit/9 bit,10 bit" newline rbitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address Match,Idle Match,Match On/Off,RWU Enabled" bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Rising,Both" bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 stop bit,2 stop bits" newline hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" line.long 0x04 "STAT,LPUART3 Status Register" eventfld.long 0x04 31. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.long 0x04 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not occurred,Occurred" rbitfld.long 0x04 29. " MSBF ,MSB first" "LSB first,MSB first" newline bitfld.long 0x04 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" bitfld.long 0x04 27. " RWUID ,Receive wake up idle detect" "Not detected,Detected" rbitfld.long 0x04 26. " BRK13 ,Break character generation length" "10/11/12/13 bit,13/14/15/16 bit" newline bitfld.long 0x04 25. " LBKDE ,LIN break detection enable" "10/11/12/13 bit,11/12/14/15 bit" rbitfld.long 0x04 24. " RAF ,Receiver active flag" "Idle,Active" rbitfld.long 0x04 23. " TDRE ,Transmit data register empty flag" "Full,Empty" newline rbitfld.long 0x04 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x04 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x04 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x04 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x04 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x04 17. " FE ,Framing error flag" "No error,Error" newline eventfld.long 0x04 16. " PF ,Parity error flag" "No error,Error" eventfld.long 0x04 15. " MA1F ,Match 1 flag" "Not equal,Equal" eventfld.long 0x04 14. " MA2F ,Match 2 flag" "Not equal,Equal" else group.long 0x00++0x07 line.long 0x00 "BAUD,LPUART3 Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Normal,Automatic" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Normal,Automatic" rbitfld.long 0x00 29. " M10 ,10-bit mode select" "8 bit/9 bit,10 bit" newline rbitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address Match,Idle Match,Match On/Off,RWU Enabled" rbitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Rising,Both" rbitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 stop bit,2 stop bits" newline hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" line.long 0x04 "STAT,LPUART3 Status Register" eventfld.long 0x04 31. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.long 0x04 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not occurred,Occurred" rbitfld.long 0x04 29. " MSBF ,MSB first" "LSB first,MSB first" newline bitfld.long 0x04 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" rbitfld.long 0x04 27. " RWUID ,Receive wake up idle detect" "Not detected,Detected" rbitfld.long 0x04 26. " BRK13 ,Break character generation length" "10/11/12/13 bit,13/14/15/16 bit" newline bitfld.long 0x04 25. " LBKDE ,LIN break detection enable" "10/11/12/13 bit,11/12/14/15 bit" rbitfld.long 0x04 24. " RAF ,Receiver active flag" "Idle,Active" rbitfld.long 0x04 23. " TDRE ,Transmit data register empty flag" "Full,Empty" newline rbitfld.long 0x04 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x04 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x04 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x04 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x04 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x04 17. " FE ,Framing error flag" "No error,Error" newline eventfld.long 0x04 16. " PF ,Parity error flag" "No error,Error" eventfld.long 0x04 15. " MA1F ,Match 1 flag" "Not equal,Equal" eventfld.long 0x04 14. " MA2F ,Match 2 flag" "Not equal,Equal" endif if (((per.l(ad:0x400C7000+0x08))&0xC0000)==0x0) if ((per.b(ad:0x400C7000+0x8)&0x80)==0x80) group.long 0x08++0x03 line.long 0x00 "CTRL,LPUART3 Control Register" bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High" bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High" bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output" newline bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby" newline bitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break" bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars" bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop" bitfld.long 0x00 6. " DOZEEN ,Doze enable" "LPUART enabled,LPUART disabled" newline bitfld.long 0x00 5. " RSRC ,Receiver source select" "Disconnected,Connected" bitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8 bit,9 bit" bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" newline bitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit" bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" else group.long 0x08++0x03 line.long 0x00 "CTRL,LPUART3 Control Register" bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High" bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High" bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output" newline bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby" newline bitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break" bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars" bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop" bitfld.long 0x00 6. " DOZEEN ,Doze enable" "LPUART enabled,LPUART disabled" newline bitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8 bit,9 bit" bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" bitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit" newline bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" endif else if ((per.b(ad:0x400C7000+0x8)&0x80)==0x80) group.long 0x08++0x03 line.long 0x00 "CTRL,LPUART3 Control Register" rbitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High" rbitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High" rbitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output" newline rbitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" rbitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" rbitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby" newline rbitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break" rbitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars" rbitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop" rbitfld.long 0x00 6. " DOZEEN ,Doze enable" "LPUART enabled,LPUART disabled" newline rbitfld.long 0x00 5. " RSRC ,Receiver source select" "Disconnected,Connected" rbitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8 bit,9 bit" rbitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" newline rbitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit" rbitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" rbitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" else group.long 0x08++0x03 line.long 0x00 "CTRL,LPUART3 Control Register" rbitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High" rbitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High" rbitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output" newline rbitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" rbitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" rbitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby" newline rbitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break" rbitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars" rbitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop" rbitfld.long 0x00 6. " DOZEEN ,Doze enable" "LPUART enabled,LPUART disabled" newline rbitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8 bit,9 bit" rbitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" rbitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit" newline rbitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" rbitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" endif endif newline hgroup.long 0x0C++0x03 hide.long 0x00 "DATA,LPUART3 Data Register" in newline sif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")||cpuis("MKS2?FN???V??12")||cpuis("KK22FN???C?P12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VFX12*")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN???CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("?K28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") if (((per.l(ad:0x400C7000)&0xC0000000)==0xC0000000)) rgroup.long 0x10++0x03 line.long 0x00 "MATCH,LPUART3 Match Address Register" hexmask.long.word 0x00 16.--25. 1. " MA2 ,Match address 2" hexmask.long.word 0x00 0.--9. 1. " MA1 ,Match address 1" else group.long 0x10++0x03 line.long 0x00 "MATCH,LPUART3 Match Address Register" hexmask.long.word 0x00 16.--25. 1. " MA2 ,Match address 2" hexmask.long.word 0x00 0.--9. 1. " MA1 ,Match address 1" endif else group.long 0x10++0x03 line.long 0x00 "MATCH,LPUART3 Match Address Register" hexmask.long.word 0x00 16.--25. 1. " MA2 ,Match address 2" hexmask.long.word 0x00 0.--9. 1. " MA1 ,Match address 1" endif group.long 0x14++0x03 line.long 0x00 "MODIR,LPUART3 Modem IrDA Register" bitfld.long 0x00 18. " IREN ,Infrared enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR" sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*") newline hexmask.long.byte 0x00 8.--15. 1. " RTSWATER ,Receive RTS Configuration" endif newline bitfld.long 0x00 5. " TXCTSSRC ,Transmit CTS source" "LPUART_CTS,Inverted Receiver Match" newline bitfld.long 0x00 4. " TXCTSC ,Transmit CTS configuration" "At start,At idle" bitfld.long 0x00 3. " RXRTSE ,Receiver request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Low,High" newline bitfld.long 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "Disabled,Enabled" sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK27FN2M0VMI15")||cpuis("?K28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") if ((((per.l(ad:0x400C7000+0x08))&0xC0000)==0x00)&&(((per.l(ad:0x400C7000+0x18))&0x800000)==0x800000)) group.long 0x18++0x03 line.long 0x00 "FIFO,LPUART3 FIFO Register" rbitfld.long 0x00 23. " TXEMPT ,Transmit Buffer/FIFO Empty" "Not empty,Empty" rbitfld.long 0x00 22. " RXEMPT ,Receive Buffer/FIFO Empty" "Not empty,Empty" eventfld.long 0x00 17. " TXOF ,Transmitter Buffer Overflow Flag" "No overflow,Overflow" eventfld.long 0x00 16. " RXUF ,Receiver Buffer Underflow Flag" "No underfow,Underflow" newline bitfld.long 0x00 15. " TXFLUSH ,Transmit FIFO/Buffer Flush" "No effect,Flush" bitfld.long 0x00 14. " RXFLUSH ,Receive FIFO/Buffer Flush" "No effect,Flush" bitfld.long 0x00 10.--12. " RXIDEN ,Receiver Idle Empty Enable. Enable RDRF assertion due to partially filled FIFO when receiver is idle for defined number of characters" "Disabled,1,2,4,8,16,32,64" bitfld.long 0x00 9. " TXOFE ,Transmit FIFO Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " RXUFE ,Receive FIFO Underflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 7. " TXFE ,Transmit FIFO Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO. Buffer Depth (datawords)" "1,4,8,16,32,64,128,256" bitfld.long 0x00 3. " RXFE ,Receive FIFO Enable" "Disabled,Enabled" newline rbitfld.long 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO. Buffer Depth (datawords)" "1,4,8,16,32,64,128,256" else rgroup.long 0x18++0x03 line.long 0x00 "FIFO,LPUART3 FIFO Register" bitfld.long 0x00 23. " TXEMPT ,Transmit Buffer/FIFO Empty" "Not empty,Empty" bitfld.long 0x00 22. " RXEMPT ,Receive Buffer/FIFO Empty" "Not empty,Empty" bitfld.long 0x00 17. " TXOF ,Transmitter Buffer Overflow Flag" "No overflow,Overflow" bitfld.long 0x00 16. " RXUF ,Receiver Buffer Underflow Flag" "No underfow,Underflow" newline bitfld.long 0x00 15. " TXFLUSH ,Transmit FIFO/Buffer Flush" "No effect,Flush" bitfld.long 0x00 14. " RXFLUSH ,Receive FIFO/Buffer Flush" "No effect,Flush" bitfld.long 0x00 10.--12. " RXIDEN ,Receiver Idle Empty Enable. Enable RDRF assertion due to partially filled FIFO when receiver is idle for defined number of characters" "Disabled,1,2,4,8,16,32,64" bitfld.long 0x00 9. " TXOFE ,Transmit FIFO Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " RXUFE ,Receive FIFO Underflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 7. " TXFE ,Transmit FIFO Enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO. Buffer Depth (datawords)" "1,4,8,16,32,64,128,256" bitfld.long 0x00 3. " RXFE ,Receive FIFO Enable" "Disabled,Enabled" newline bitfld.long 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO. Buffer Depth (datawords)" "1,4,8,16,32,64,128,256" endif if (((per.l(ad:0x400C7000+0x08))&0x80000)==0x80000) rgroup.long 0x1C++0x03 line.long 0x00 "WATER,LPUART3 Watermark Register" hexmask.long.byte 0x00 24.--31. 1. " RXCOUNT ,Receive Counter" hexmask.long.byte 0x00 16.--23. 1. " RXWATER ,Receive Watermark" hexmask.long.byte 0x00 8.--15. 1. " TXCOUNT ,Transmit Counter" hexmask.long.byte 0x00 0.--7. 1. " TXWATER ,Transmit Watermark" else group.long 0x1C++0x03 line.long 0x00 "WATER,LPUART3 Watermark Register" hexmask.long.byte 0x00 24.--31. 1. " RXCOUNT ,Receive Counter" hexmask.long.byte 0x00 16.--23. 1. " RXWATER ,Receive Watermark" hexmask.long.byte 0x00 8.--15. 1. " TXCOUNT ,Transmit Counter" hexmask.long.byte 0x00 0.--7. 1. " TXWATER ,Transmit Watermark" endif endif width 0x0B tree.end tree "LPUART_4" base ad:0x400D6000 width 7. if (((per.l(ad:0x400D6000+0x08))&0xC0000)==0x0) group.long 0x00++0x07 line.long 0x00 "BAUD,LPUART4 Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Normal,Automatic" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Normal,Automatic" bitfld.long 0x00 29. " M10 ,10-bit mode select" "8 bit/9 bit,10 bit" newline bitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address Match,Idle Match,Match On/Off,RWU Enabled" bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Rising,Both" bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 stop bit,2 stop bits" newline hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" line.long 0x04 "STAT,LPUART4 Status Register" eventfld.long 0x04 31. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.long 0x04 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not occurred,Occurred" bitfld.long 0x04 29. " MSBF ,MSB first" "LSB first,MSB first" newline bitfld.long 0x04 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" bitfld.long 0x04 27. " RWUID ,Receive wake up idle detect" "Not detected,Detected" bitfld.long 0x04 26. " BRK13 ,Break character generation length" "10/11/12/13 bit,13/14/15/16 bit" newline bitfld.long 0x04 25. " LBKDE ,LIN break detection enable" "10/11/12/13 bit,11/12/14/15 bit" rbitfld.long 0x04 24. " RAF ,Receiver active flag" "Idle,Active" rbitfld.long 0x04 23. " TDRE ,Transmit data register empty flag" "Full,Empty" newline rbitfld.long 0x04 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x04 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x04 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x04 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x04 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x04 17. " FE ,Framing error flag" "No error,Error" newline eventfld.long 0x04 16. " PF ,Parity error flag" "No error,Error" eventfld.long 0x04 15. " MA1F ,Match 1 flag" "Not equal,Equal" eventfld.long 0x04 14. " MA2F ,Match 2 flag" "Not equal,Equal" elif (((per.l(ad:0x400D6000+0x08))&0x80000)==0x0) group.long 0x00++0x07 line.long 0x00 "BAUD,LPUART4 Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Normal,Automatic" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Normal,Automatic" rbitfld.long 0x00 29. " M10 ,10-bit mode select" "8 bit/9 bit,10 bit" newline rbitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address Match,Idle Match,Match On/Off,RWU Enabled" rbitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Rising,Both" rbitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 stop bit,2 stop bits" newline hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" line.long 0x04 "STAT,LPUART4 Status Register" eventfld.long 0x04 31. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.long 0x04 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not occurred,Occurred" rbitfld.long 0x04 29. " MSBF ,MSB first" "LSB first,MSB first" newline bitfld.long 0x04 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" rbitfld.long 0x04 27. " RWUID ,Receive wake up idle detect" "Not detected,Detected" bitfld.long 0x04 26. " BRK13 ,Break character generation length" "10/11/12/13 bit,13/14/15/16 bit" newline bitfld.long 0x04 25. " LBKDE ,LIN break detection enable" "10/11/12/13 bit,11/12/14/15 bit" rbitfld.long 0x04 24. " RAF ,Receiver active flag" "Idle,Active" rbitfld.long 0x04 23. " TDRE ,Transmit data register empty flag" "Full,Empty" newline rbitfld.long 0x04 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x04 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x04 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x04 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x04 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x04 17. " FE ,Framing error flag" "No error,Error" newline eventfld.long 0x04 16. " PF ,Parity error flag" "No error,Error" eventfld.long 0x04 15. " MA1F ,Match 1 flag" "Not equal,Equal" eventfld.long 0x04 14. " MA2F ,Match 2 flag" "Not equal,Equal" elif (((per.l(ad:0x400D6000+0x08))&0x40000)==0x0) group.long 0x00++0x07 line.long 0x00 "BAUD,LPUART4 Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Normal,Automatic" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Normal,Automatic" rbitfld.long 0x00 29. " M10 ,10-bit mode select" "8 bit/9 bit,10 bit" newline rbitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address Match,Idle Match,Match On/Off,RWU Enabled" bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Rising,Both" bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 stop bit,2 stop bits" newline hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" line.long 0x04 "STAT,LPUART4 Status Register" eventfld.long 0x04 31. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.long 0x04 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not occurred,Occurred" rbitfld.long 0x04 29. " MSBF ,MSB first" "LSB first,MSB first" newline bitfld.long 0x04 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" bitfld.long 0x04 27. " RWUID ,Receive wake up idle detect" "Not detected,Detected" rbitfld.long 0x04 26. " BRK13 ,Break character generation length" "10/11/12/13 bit,13/14/15/16 bit" newline bitfld.long 0x04 25. " LBKDE ,LIN break detection enable" "10/11/12/13 bit,11/12/14/15 bit" rbitfld.long 0x04 24. " RAF ,Receiver active flag" "Idle,Active" rbitfld.long 0x04 23. " TDRE ,Transmit data register empty flag" "Full,Empty" newline rbitfld.long 0x04 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x04 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x04 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x04 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x04 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x04 17. " FE ,Framing error flag" "No error,Error" newline eventfld.long 0x04 16. " PF ,Parity error flag" "No error,Error" eventfld.long 0x04 15. " MA1F ,Match 1 flag" "Not equal,Equal" eventfld.long 0x04 14. " MA2F ,Match 2 flag" "Not equal,Equal" else group.long 0x00++0x07 line.long 0x00 "BAUD,LPUART4 Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Normal,Automatic" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Normal,Automatic" rbitfld.long 0x00 29. " M10 ,10-bit mode select" "8 bit/9 bit,10 bit" newline rbitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address Match,Idle Match,Match On/Off,RWU Enabled" rbitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Rising,Both" rbitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 stop bit,2 stop bits" newline hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" line.long 0x04 "STAT,LPUART4 Status Register" eventfld.long 0x04 31. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.long 0x04 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not occurred,Occurred" rbitfld.long 0x04 29. " MSBF ,MSB first" "LSB first,MSB first" newline bitfld.long 0x04 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" rbitfld.long 0x04 27. " RWUID ,Receive wake up idle detect" "Not detected,Detected" rbitfld.long 0x04 26. " BRK13 ,Break character generation length" "10/11/12/13 bit,13/14/15/16 bit" newline bitfld.long 0x04 25. " LBKDE ,LIN break detection enable" "10/11/12/13 bit,11/12/14/15 bit" rbitfld.long 0x04 24. " RAF ,Receiver active flag" "Idle,Active" rbitfld.long 0x04 23. " TDRE ,Transmit data register empty flag" "Full,Empty" newline rbitfld.long 0x04 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x04 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x04 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x04 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x04 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x04 17. " FE ,Framing error flag" "No error,Error" newline eventfld.long 0x04 16. " PF ,Parity error flag" "No error,Error" eventfld.long 0x04 15. " MA1F ,Match 1 flag" "Not equal,Equal" eventfld.long 0x04 14. " MA2F ,Match 2 flag" "Not equal,Equal" endif if (((per.l(ad:0x400D6000+0x08))&0xC0000)==0x0) if ((per.b(ad:0x400D6000+0x8)&0x80)==0x80) group.long 0x08++0x03 line.long 0x00 "CTRL,LPUART4 Control Register" bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High" bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High" bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output" newline bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby" newline bitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break" bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars" bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop" bitfld.long 0x00 6. " DOZEEN ,Doze enable" "LPUART enabled,LPUART disabled" newline bitfld.long 0x00 5. " RSRC ,Receiver source select" "Disconnected,Connected" bitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8 bit,9 bit" bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" newline bitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit" bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" else group.long 0x08++0x03 line.long 0x00 "CTRL,LPUART4 Control Register" bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High" bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High" bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output" newline bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby" newline bitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break" bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars" bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop" bitfld.long 0x00 6. " DOZEEN ,Doze enable" "LPUART enabled,LPUART disabled" newline bitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8 bit,9 bit" bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" bitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit" newline bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" endif else if ((per.b(ad:0x400D6000+0x8)&0x80)==0x80) group.long 0x08++0x03 line.long 0x00 "CTRL,LPUART4 Control Register" rbitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High" rbitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High" rbitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output" newline rbitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" rbitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" rbitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby" newline rbitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break" rbitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars" rbitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop" rbitfld.long 0x00 6. " DOZEEN ,Doze enable" "LPUART enabled,LPUART disabled" newline rbitfld.long 0x00 5. " RSRC ,Receiver source select" "Disconnected,Connected" rbitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8 bit,9 bit" rbitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" newline rbitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit" rbitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" rbitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" else group.long 0x08++0x03 line.long 0x00 "CTRL,LPUART4 Control Register" rbitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High" rbitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High" rbitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output" newline rbitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" rbitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" rbitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby" newline rbitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break" rbitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars" rbitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop" rbitfld.long 0x00 6. " DOZEEN ,Doze enable" "LPUART enabled,LPUART disabled" newline rbitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8 bit,9 bit" rbitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" rbitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit" newline rbitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" rbitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" endif endif newline hgroup.long 0x0C++0x03 hide.long 0x00 "DATA,LPUART4 Data Register" in newline sif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")||cpuis("MKS2?FN???V??12")||cpuis("KK22FN???C?P12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VFX12*")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN???CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("?K28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") if (((per.l(ad:0x400D6000)&0xC0000000)==0xC0000000)) rgroup.long 0x10++0x03 line.long 0x00 "MATCH,LPUART4 Match Address Register" hexmask.long.word 0x00 16.--25. 1. " MA2 ,Match address 2" hexmask.long.word 0x00 0.--9. 1. " MA1 ,Match address 1" else group.long 0x10++0x03 line.long 0x00 "MATCH,LPUART4 Match Address Register" hexmask.long.word 0x00 16.--25. 1. " MA2 ,Match address 2" hexmask.long.word 0x00 0.--9. 1. " MA1 ,Match address 1" endif else group.long 0x10++0x03 line.long 0x00 "MATCH,LPUART4 Match Address Register" hexmask.long.word 0x00 16.--25. 1. " MA2 ,Match address 2" hexmask.long.word 0x00 0.--9. 1. " MA1 ,Match address 1" endif group.long 0x14++0x03 line.long 0x00 "MODIR,LPUART4 Modem IrDA Register" bitfld.long 0x00 18. " IREN ,Infrared enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR" sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*") newline hexmask.long.byte 0x00 8.--15. 1. " RTSWATER ,Receive RTS Configuration" endif newline bitfld.long 0x00 5. " TXCTSSRC ,Transmit CTS source" "LPUART_CTS,Inverted Receiver Match" newline bitfld.long 0x00 4. " TXCTSC ,Transmit CTS configuration" "At start,At idle" bitfld.long 0x00 3. " RXRTSE ,Receiver request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Low,High" newline bitfld.long 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "Disabled,Enabled" sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK27FN2M0VMI15")||cpuis("?K28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") if ((((per.l(ad:0x400D6000+0x08))&0xC0000)==0x00)&&(((per.l(ad:0x400D6000+0x18))&0x800000)==0x800000)) group.long 0x18++0x03 line.long 0x00 "FIFO,LPUART4 FIFO Register" rbitfld.long 0x00 23. " TXEMPT ,Transmit Buffer/FIFO Empty" "Not empty,Empty" rbitfld.long 0x00 22. " RXEMPT ,Receive Buffer/FIFO Empty" "Not empty,Empty" eventfld.long 0x00 17. " TXOF ,Transmitter Buffer Overflow Flag" "No overflow,Overflow" eventfld.long 0x00 16. " RXUF ,Receiver Buffer Underflow Flag" "No underfow,Underflow" newline bitfld.long 0x00 15. " TXFLUSH ,Transmit FIFO/Buffer Flush" "No effect,Flush" bitfld.long 0x00 14. " RXFLUSH ,Receive FIFO/Buffer Flush" "No effect,Flush" bitfld.long 0x00 10.--12. " RXIDEN ,Receiver Idle Empty Enable. Enable RDRF assertion due to partially filled FIFO when receiver is idle for defined number of characters" "Disabled,1,2,4,8,16,32,64" bitfld.long 0x00 9. " TXOFE ,Transmit FIFO Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " RXUFE ,Receive FIFO Underflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 7. " TXFE ,Transmit FIFO Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO. Buffer Depth (datawords)" "1,4,8,16,32,64,128,256" bitfld.long 0x00 3. " RXFE ,Receive FIFO Enable" "Disabled,Enabled" newline rbitfld.long 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO. Buffer Depth (datawords)" "1,4,8,16,32,64,128,256" else rgroup.long 0x18++0x03 line.long 0x00 "FIFO,LPUART4 FIFO Register" bitfld.long 0x00 23. " TXEMPT ,Transmit Buffer/FIFO Empty" "Not empty,Empty" bitfld.long 0x00 22. " RXEMPT ,Receive Buffer/FIFO Empty" "Not empty,Empty" bitfld.long 0x00 17. " TXOF ,Transmitter Buffer Overflow Flag" "No overflow,Overflow" bitfld.long 0x00 16. " RXUF ,Receiver Buffer Underflow Flag" "No underfow,Underflow" newline bitfld.long 0x00 15. " TXFLUSH ,Transmit FIFO/Buffer Flush" "No effect,Flush" bitfld.long 0x00 14. " RXFLUSH ,Receive FIFO/Buffer Flush" "No effect,Flush" bitfld.long 0x00 10.--12. " RXIDEN ,Receiver Idle Empty Enable. Enable RDRF assertion due to partially filled FIFO when receiver is idle for defined number of characters" "Disabled,1,2,4,8,16,32,64" bitfld.long 0x00 9. " TXOFE ,Transmit FIFO Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " RXUFE ,Receive FIFO Underflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 7. " TXFE ,Transmit FIFO Enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO. Buffer Depth (datawords)" "1,4,8,16,32,64,128,256" bitfld.long 0x00 3. " RXFE ,Receive FIFO Enable" "Disabled,Enabled" newline bitfld.long 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO. Buffer Depth (datawords)" "1,4,8,16,32,64,128,256" endif if (((per.l(ad:0x400D6000+0x08))&0x80000)==0x80000) rgroup.long 0x1C++0x03 line.long 0x00 "WATER,LPUART4 Watermark Register" hexmask.long.byte 0x00 24.--31. 1. " RXCOUNT ,Receive Counter" hexmask.long.byte 0x00 16.--23. 1. " RXWATER ,Receive Watermark" hexmask.long.byte 0x00 8.--15. 1. " TXCOUNT ,Transmit Counter" hexmask.long.byte 0x00 0.--7. 1. " TXWATER ,Transmit Watermark" else group.long 0x1C++0x03 line.long 0x00 "WATER,LPUART4 Watermark Register" hexmask.long.byte 0x00 24.--31. 1. " RXCOUNT ,Receive Counter" hexmask.long.byte 0x00 16.--23. 1. " RXWATER ,Receive Watermark" hexmask.long.byte 0x00 8.--15. 1. " TXCOUNT ,Transmit Counter" hexmask.long.byte 0x00 0.--7. 1. " TXWATER ,Transmit Watermark" endif endif width 0x0B tree.end tree.end tree "FlexIO" base ad:0x400DF000 width 12. rgroup.long 0x00++0x07 "Common Registers" line.long 0x00 "VERID,Version ID Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major revision number" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor revision number" hexmask.long.word 0x00 0.--15. 1. " FEATURE ,Feature specification number" line.long 0x04 "PARAM,Parameter Register" hexmask.long.byte 0x04 24.--31. 1. " TRIGGER ,Number of external triggers implemented" hexmask.long.byte 0x04 16.--23. 1. " PIN ,Number of pins implemented" hexmask.long.byte 0x04 8.--15. 1. " TIMER ,Number of timers implemented" newline hexmask.long.byte 0x04 0.--7. 1. " SHIFTER ,Number of shifters implemented" group.long 0x08++0x03 line.long 0x00 "CTRL,Flexio Control Register" bitfld.long 0x00 31. " DOZEN ,Disables flexio operation in doze modes" "Flexio enabled,Flexio disabled" bitfld.long 0x00 30. " DBGE ,Enables flexio operation in debug mode" "Disabled,Enabled" bitfld.long 0x00 2. " FASTACC ,Enables fast register accesses to flexio registers" "Normal access,Fast access" newline bitfld.long 0x00 1. " SWRST ,Software reset" "Disabled,Enabled" bitfld.long 0x00 0. " FLEXEN ,Flexio module enable" "Disabled,Enabled" newline sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MKL82Z*")||cpuis("IMXRT1021") rgroup.long 0x0C++0x03 line.long 0x00 "PIN,Pin State Register" bitfld.long 0x00 31. " PDI[31] ,Pin 31 data input" "0,1" bitfld.long 0x00 30. " PDI[30] ,Pin 30 data input" "0,1" bitfld.long 0x00 29. " PDI[29] ,Pin 29 data input" "0,1" bitfld.long 0x00 28. " PDI[28] ,Pin 28 data input" "0,1" newline bitfld.long 0x00 27. " PDI[27] ,Pin 27 data input" "0,1" bitfld.long 0x00 26. " PDI[26] ,Pin 26 data input" "0,1" bitfld.long 0x00 25. " PDI[25] ,Pin 25 data input" "0,1" bitfld.long 0x00 24. " PDI[24] ,Pin 24 data input" "0,1" newline bitfld.long 0x00 23. " PDI[23] ,Pin 23 data input" "0,1" bitfld.long 0x00 22. " PDI[22] ,Pin 22 data input" "0,1" bitfld.long 0x00 21. " PDI[21] ,Pin 21 data input" "0,1" bitfld.long 0x00 20. " PDI[20] ,Pin 20 data input" "0,1" newline bitfld.long 0x00 19. " PDI[19] ,Pin 19 data input" "0,1" bitfld.long 0x00 18. " PDI[18] ,Pin 18 data input" "0,1" bitfld.long 0x00 17. " PDI[17] ,Pin 17 data input" "0,1" bitfld.long 0x00 16. " PDI[16] ,Pin 16 data input" "0,1" newline bitfld.long 0x00 15. " PDI[15] ,Pin 15 data input" "0,1" bitfld.long 0x00 14. " PDI[14] ,Pin 14 data input" "0,1" bitfld.long 0x00 13. " PDI[13] ,Pin 13 data input" "0,1" bitfld.long 0x00 12. " PDI[12] ,Pin 12 data input" "0,1" newline bitfld.long 0x00 11. " PDI[11] ,Pin 11 data input" "0,1" bitfld.long 0x00 10. " PDI[10] ,Pin 10 data input" "0,1" bitfld.long 0x00 9. " PDI[9] ,Pin 9 data input" "0,1" bitfld.long 0x00 8. " PDI[8] ,Pin 8 data input" "0,1" newline bitfld.long 0x00 7. " PDI[7] ,Pin 7 data input" "0,1" bitfld.long 0x00 6. " PDI[6] ,Pin 6 data input" "0,1" bitfld.long 0x00 5. " PDI[5] ,Pin 5 data input" "0,1" bitfld.long 0x00 4. " PDI[4] ,Pin 4 data input" "0,1" newline bitfld.long 0x00 3. " PDI[3] ,Pin 3 data input" "0,1" bitfld.long 0x00 2. " PDI[2] ,Pin 2 data input" "0,1" bitfld.long 0x00 1. " PDI[1] ,Pin 1 data input" "0,1" bitfld.long 0x00 0. " PDI[0] ,Pin 0 data input" "0,1" endif group.long 0x10++0x0B line.long 0x00 "SHIFTSTAT,Shifter Status Register" sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MKL82Z*") eventfld.long 0x00 7. " SSF[7] ,Shifter 7 status flag" "Cleared,Set" eventfld.long 0x00 6. " SSF[6] ,Shifter 6 status flag" "Cleared,Set" eventfld.long 0x00 5. " SSF[5] ,Shifter 5 status flag" "Cleared,Set" eventfld.long 0x00 4. " SSF[4] ,Shifter 4 status flag" "Cleared,Set" newline endif eventfld.long 0x00 3. " SSF[3] ,Shifter 3 status flag" "Cleared,Set" eventfld.long 0x00 2. " SSF[2] ,Shifter 2 status flag" "Cleared,Set" eventfld.long 0x00 1. " SSF[1] ,Shifter 1 status flag" "Cleared,Set" eventfld.long 0x00 0. " SSF[0] ,Shifter 0 status flag" "Cleared,Set" line.long 0x04 "SHIFTERR,Shifter Error Register" sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MKL82Z*") eventfld.long 0x04 7. " SEF[7] ,Shifter 7 error flags" "Cleared,Set" eventfld.long 0x04 6. " SEF[6] ,Shifter 6 error flags" "Cleared,Set" eventfld.long 0x04 5. " SEF[5] ,Shifter 5 error flags" "Cleared,Set" eventfld.long 0x04 4. " SEF[4] ,Shifter 4 error flags" "Cleared,Set" newline endif eventfld.long 0x04 3. " SEF[3] ,Shifter 3 error flags" "Cleared,Set" eventfld.long 0x04 2. " SEF[2] ,Shifter 2 error flags" "Cleared,Set" eventfld.long 0x04 1. " SEF[1] ,Shifter 1 error flags" "Cleared,Set" eventfld.long 0x04 0. " SEF[0] ,Shifter 0 error flags" "Cleared,Set" line.long 0x08 "TIMSTAT,Timer Status Register" sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MKL82Z*") eventfld.long 0x08 7. " TSF[7] ,Timer 7 status flags" "Cleared,Set" eventfld.long 0x08 6. " TSF[6] ,Timer 6 status flags" "Cleared,Set" eventfld.long 0x08 5. " TSF[5] ,Timer 5 status flags" "Cleared,Set" eventfld.long 0x08 4. " TSF[4] ,Timer 4 status flags" "Cleared,Set" newline endif eventfld.long 0x08 3. " TSF[3] ,Timer 3 status flags" "Cleared,Set" eventfld.long 0x08 2. " TSF[2] ,Timer 2 status flags" "Cleared,Set" eventfld.long 0x08 1. " TSF[1] ,Timer 1 status flags" "Cleared,Set" eventfld.long 0x08 0. " TSF[0] ,Timer 0 status flags" "Cleared,Set" group.long 0x20++0x0B line.long 0x00 "SHIFTSIEN,Shifter Status Interrupt Enable Register" sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MKL82Z*") bitfld.long 0x00 7. " SSIE[7] ,Enables interrupt generation when SSF[7] is set" "Disabled,Enabled" bitfld.long 0x00 6. " SSIE[6] ,Enables interrupt generation when SSF[6] is set" "Disabled,Enabled" bitfld.long 0x00 5. " SSIE[5] ,Enables interrupt generation when SSF[5] is set" "Disabled,Enabled" bitfld.long 0x00 4. " SSIE[4] ,Enables interrupt generation when SSF[4] is set" "Disabled,Enabled" newline endif bitfld.long 0x00 3. " SSIE[3] ,Enables interrupt generation when SSF[3] is set" "Disabled,Enabled" bitfld.long 0x00 2. " SSIE[2] ,Enables interrupt generation when SSF[2] is set" "Disabled,Enabled" bitfld.long 0x00 1. " SSIE[1] ,Enables interrupt generation when SSF[1] is set" "Disabled,Enabled" bitfld.long 0x00 0. " SSIE[0] ,Enables interrupt generation when SSF[0] is set" "Disabled,Enabled" line.long 0x04 "SHIFTEIEN,Shifter Error Interrupt Enable Register" sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MKL82Z*") bitfld.long 0x04 7. " SEIE[7] ,Enables interrupt generation when SEF[7] is set" "Disabled,Enabled" bitfld.long 0x04 6. " SEIE[6] ,Enables interrupt generation when SEF[6] is set" "Disabled,Enabled" bitfld.long 0x04 5. " SEIE[5] ,Enables interrupt generation when SEF[5] is set" "Disabled,Enabled" bitfld.long 0x04 4. " SEIE[4] ,Enables interrupt generation when SEF[4] is set" "Disabled,Enabled" newline endif bitfld.long 0x04 3. " SEIE[3] ,Enables interrupt generation when SEF[3] is set" "Disabled,Enabled" bitfld.long 0x04 2. " SEIE[2] ,Enables interrupt generation when SEF[2] is set" "Disabled,Enabled" bitfld.long 0x04 1. " SEIE[1] ,Enables interrupt generation when SEF[1] is set" "Disabled,Enabled" bitfld.long 0x04 0. " SEIE[0] ,Enables interrupt generation when SEF[0] is set" "Disabled,Enabled" line.long 0x08 "TIMIEN,Timer Interrupt Enable Register" sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MKL82Z*") bitfld.long 0x08 7. " TEIE[7] ,Enables interrupt generation when TSF[7] is set" "Disabled,Enabled" bitfld.long 0x08 6. " TEIE[6] ,Enables interrupt generation when TSF[6] is set" "Disabled,Enabled" bitfld.long 0x08 5. " TEIE[5] ,Enables interrupt generation when TSF[5] is set" "Disabled,Enabled" bitfld.long 0x08 4. " TEIE[4] ,Enables interrupt generation when TSF[4] is set" "Disabled,Enabled" newline endif bitfld.long 0x08 3. " TEIE[3] ,Enables interrupt generation when TSF[3] is set" "Disabled,Enabled" bitfld.long 0x08 2. " TEIE[2] ,Enables interrupt generation when TSF[2] is set" "Disabled,Enabled" bitfld.long 0x08 1. " TEIE[1] ,Enables interrupt generation when TSF[1] is set" "Disabled,Enabled" bitfld.long 0x08 0. " TEIE[0] ,Enables interrupt generation when TSF[0] is set" "Disabled,Enabled" group.long 0x30++0x03 line.long 0x00 "SHIFTSDEN,Shifter Status DMA Enable Register" sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MKL82Z*") bitfld.long 0x00 7. " SSDE[7] ,Enables DMA request generation when SSF[7] is set" "Disabled,Enabled" bitfld.long 0x00 6. " SSDE[6] ,Enables DMA request generation when SSF[6] is set" "Disabled,Enabled" bitfld.long 0x00 5. " SSDE[5] ,Enables DMA request generation when SSF[5] is set" "Disabled,Enabled" bitfld.long 0x00 4. " SSDE[4] ,Enables DMA request generation when SSF[4] is set" "Disabled,Enabled" newline endif bitfld.long 0x00 3. " SSDE[3] ,Enables DMA request generation when SSF[3] is set" "Disabled,Enabled" bitfld.long 0x00 2. " SSDE[2] ,Enables DMA request generation when SSF[2] is set" "Disabled,Enabled" bitfld.long 0x00 1. " SSDE[1] ,Enables DMA request generation when SSF[1] is set" "Disabled,Enabled" bitfld.long 0x00 0. " SSDE[0] ,Enables DMA request generation when SSF[0] is set" "Disabled,Enabled" sif cpuis("MK84FN2M0CAU15R") group.long 0x40++0x03 line.long 0x00 "SHIFTSTATE,Shifter State Register" bitfld.long 0x00 0.--3. " STATE ,Current state pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif cpuis("MK8?FN256V*")||cpuis("MKL82Z*")||cpuis("IMXRT1021") group.long 0x40++0x03 line.long 0x00 "SHIFTSTATE,Shifter State Register" bitfld.long 0x00 0.--2. " STATE ,Current state pointer" "0,1,2,3,4,5,6,7" endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MKL82Z*") width 17. tree "Shifter Registers" group.long (0x0+0x80)++0x03 line.long 0x00 "SHIFTCTL_0,Shifter Control 0 Register" bitfld.long 0x00 24.--26. " TIMSEL ,Selects which timer is used for controlling the logic/shift register and generating the shift clock" "Timer 0,Timer 1,Timer 2,Timer 3,Timer 4,Timer 5,Timer 6,Timer 7" bitfld.long 0x00 23. " TIMPOL ,Timer polarity" "Posedge,Negedge" bitfld.long 0x00 16.--17. " PINCFG ,Shifter pin configuration" "Disabled,Open drain or bidir/Out,Bidir/Out data,Output" newline bitfld.long 0x00 8.--12. " PINSEL ,Shifter pin select" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7,FXIO0_D8,FXIO0_D9,FXIO0_D10,FXIO0_D11,FXIO0_D12,FXIO0_D13,FXIO0_D14,FXIO0_D15,FXIO0_D16,FXIO0_D17,FXIO0_D18,FXIO0_D19,FXIO0_D20,FXIO0_D21,FXIO0_D22,FXIO0_D23,FXIO0_D24,FXIO0_D25,FXIO0_D26,FXIO0_D27,FXIO0_D28,FXIO0_D29,FXIO0_D30,FXIO0_D31" bitfld.long 0x00 7. " PINPOL ,Shifter pin polarity" "Active high,Active low" bitfld.long 0x00 0.--2. " SMOD ,Configures the mode of the shifter" "Disabled,Receive mode,Transmit mode,,Match store,Match continuous,State mode,Logic mode" newline if (((per.l(ad:0x400DF000+0x80+0x0))&0x07)==0x05) group.long (0x0+0x100)++0x03 line.long 0x00 "SHIFTCFG_0,Shifter Configuration 0 Register" bitfld.long 0x00 16.--20. " PWIDTH ,Parallel width" "1-bit shift,4-bit shift,4-bit shift,4-bit shift,8-bit shift,8-bit shift,8-bit shift,8-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift" bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output" group.long (0x0+0x200)++0x03 line.long 0x00 "SHIFTBUF_0,Shifter Buffer 0 Register" hexmask.long.word 0x00 16.--31. 1. " SHIFTBUF[31:16] ,Shift buffer data to match" newline bitfld.long 0x00 15. " SHIFTBUF[15] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 14. " SHIFTBUF[14] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 13. " SHIFTBUF[13] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 12. " SHIFTBUF[12] ,Shift buffer mask" "Not masked,Masked" newline bitfld.long 0x00 11. " SHIFTBUF[11] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 10. " SHIFTBUF[10] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 9. " SHIFTBUF[9] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 8. " SHIFTBUF[8] ,Shift buffer mask" "Not masked,Masked" newline bitfld.long 0x00 7. " SHIFTBUF[7] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 6. " SHIFTBUF[6] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 5. " SHIFTBUF[5] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 4. " SHIFTBUF[4] ,Shift buffer mask" "Not masked,Masked" newline bitfld.long 0x00 3. " SHIFTBUF[3] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 2. " SHIFTBUF[2] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 1. " SHIFTBUF[1] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 0. " SHIFTBUF[0] ,Shift buffer mask" "Not masked,Masked" group.long (0x0+0x280)++0x03 line.long 0x00 "SHIFTBUFBIS_0,Shifter Buffer 0 Bit Swapped Register" group.long (0x0+0x300)++0x03 line.long 0x00 "SHIFTBUFBYS_0,Shifter Buffer 0 Byte Swapped Register" group.long (0x0+0x380)++0x03 line.long 0x00 "SHIFTBUFBBS_0,Shifter Buffer 0 Bit Byte Swapped Register" else group.long (0x0+0x100)++0x03 line.long 0x00 "SHIFTCFG_0,Shifter Configuration 0 Register" bitfld.long 0x00 16.--20. " PWIDTH ,Parallel width" "1-bit shift,4-bit shift,4-bit shift,4-bit shift,8-bit shift,8-bit shift,8-bit shift,8-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift" bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output" bitfld.long 0x00 4.--5. " SSTOP ,Shifter stop bit" "Disabled,,0 on store,1 on store" newline bitfld.long 0x00 0.--1. " SSTART ,Shifter start bit" "Disabled / load on enable,Disabled / load on first shift,0 before first shift,1 before first shift" group.long (0x0+0x200)++0x03 line.long 0x00 "SHIFTBUF_0,Shifter Buffer 0 Register" group.long (0x0+0x280)++0x03 line.long 0x00 "SHIFTBUFBIS_0,Shifter Buffer 0 Bit Swapped Register" group.long (0x0+0x300)++0x03 line.long 0x00 "SHIFTBUFBYS_0,Shifter Buffer 0 Byte Swapped Register" group.long (0x0+0x380)++0x03 line.long 0x00 "SHIFTBUFBBS_0,Shifter Buffer 0 Bit Byte Swapped Register" endif group.long (0x4+0x80)++0x03 line.long 0x00 "SHIFTCTL_1,Shifter Control 1 Register" bitfld.long 0x00 24.--26. " TIMSEL ,Selects which timer is used for controlling the logic/shift register and generating the shift clock" "Timer 0,Timer 1,Timer 2,Timer 3,Timer 4,Timer 5,Timer 6,Timer 7" bitfld.long 0x00 23. " TIMPOL ,Timer polarity" "Posedge,Negedge" bitfld.long 0x00 16.--17. " PINCFG ,Shifter pin configuration" "Disabled,Open drain or bidir/Out,Bidir/Out data,Output" newline bitfld.long 0x00 8.--12. " PINSEL ,Shifter pin select" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7,FXIO0_D8,FXIO0_D9,FXIO0_D10,FXIO0_D11,FXIO0_D12,FXIO0_D13,FXIO0_D14,FXIO0_D15,FXIO0_D16,FXIO0_D17,FXIO0_D18,FXIO0_D19,FXIO0_D20,FXIO0_D21,FXIO0_D22,FXIO0_D23,FXIO0_D24,FXIO0_D25,FXIO0_D26,FXIO0_D27,FXIO0_D28,FXIO0_D29,FXIO0_D30,FXIO0_D31" bitfld.long 0x00 7. " PINPOL ,Shifter pin polarity" "Active high,Active low" bitfld.long 0x00 0.--2. " SMOD ,Configures the mode of the shifter" "Disabled,Receive mode,Transmit mode,,Match store,Match continuous,State mode,Logic mode" newline if (((per.l(ad:0x400DF000+0x80+0x4))&0x07)==0x05) group.long (0x4+0x100)++0x03 line.long 0x00 "SHIFTCFG_1,Shifter Configuration 1 Register" bitfld.long 0x00 16.--20. " PWIDTH ,Parallel width" "1-bit shift,4-bit shift,4-bit shift,4-bit shift,8-bit shift,8-bit shift,8-bit shift,8-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift" bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output" group.long (0x4+0x200)++0x03 line.long 0x00 "SHIFTBUF_1,Shifter Buffer 1 Register" hexmask.long.word 0x00 16.--31. 1. " SHIFTBUF[31:16] ,Shift buffer data to match" newline bitfld.long 0x00 15. " SHIFTBUF[15] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 14. " SHIFTBUF[14] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 13. " SHIFTBUF[13] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 12. " SHIFTBUF[12] ,Shift buffer mask" "Not masked,Masked" newline bitfld.long 0x00 11. " SHIFTBUF[11] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 10. " SHIFTBUF[10] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 9. " SHIFTBUF[9] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 8. " SHIFTBUF[8] ,Shift buffer mask" "Not masked,Masked" newline bitfld.long 0x00 7. " SHIFTBUF[7] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 6. " SHIFTBUF[6] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 5. " SHIFTBUF[5] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 4. " SHIFTBUF[4] ,Shift buffer mask" "Not masked,Masked" newline bitfld.long 0x00 3. " SHIFTBUF[3] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 2. " SHIFTBUF[2] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 1. " SHIFTBUF[1] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 0. " SHIFTBUF[0] ,Shift buffer mask" "Not masked,Masked" group.long (0x4+0x280)++0x03 line.long 0x00 "SHIFTBUFBIS_1,Shifter Buffer 1 Bit Swapped Register" group.long (0x4+0x300)++0x03 line.long 0x00 "SHIFTBUFBYS_1,Shifter Buffer 1 Byte Swapped Register" group.long (0x4+0x380)++0x03 line.long 0x00 "SHIFTBUFBBS_1,Shifter Buffer 1 Bit Byte Swapped Register" else group.long (0x4+0x100)++0x03 line.long 0x00 "SHIFTCFG_1,Shifter Configuration 1 Register" bitfld.long 0x00 16.--20. " PWIDTH ,Parallel width" "1-bit shift,4-bit shift,4-bit shift,4-bit shift,8-bit shift,8-bit shift,8-bit shift,8-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift" bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output" bitfld.long 0x00 4.--5. " SSTOP ,Shifter stop bit" "Disabled,,0 on store,1 on store" newline bitfld.long 0x00 0.--1. " SSTART ,Shifter start bit" "Disabled / load on enable,Disabled / load on first shift,0 before first shift,1 before first shift" group.long (0x4+0x200)++0x03 line.long 0x00 "SHIFTBUF_1,Shifter Buffer 1 Register" group.long (0x4+0x280)++0x03 line.long 0x00 "SHIFTBUFBIS_1,Shifter Buffer 1 Bit Swapped Register" group.long (0x4+0x300)++0x03 line.long 0x00 "SHIFTBUFBYS_1,Shifter Buffer 1 Byte Swapped Register" group.long (0x4+0x380)++0x03 line.long 0x00 "SHIFTBUFBBS_1,Shifter Buffer 1 Bit Byte Swapped Register" endif group.long (0x8+0x80)++0x03 line.long 0x00 "SHIFTCTL_2,Shifter Control 2 Register" bitfld.long 0x00 24.--26. " TIMSEL ,Selects which timer is used for controlling the logic/shift register and generating the shift clock" "Timer 0,Timer 1,Timer 2,Timer 3,Timer 4,Timer 5,Timer 6,Timer 7" bitfld.long 0x00 23. " TIMPOL ,Timer polarity" "Posedge,Negedge" bitfld.long 0x00 16.--17. " PINCFG ,Shifter pin configuration" "Disabled,Open drain or bidir/Out,Bidir/Out data,Output" newline bitfld.long 0x00 8.--12. " PINSEL ,Shifter pin select" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7,FXIO0_D8,FXIO0_D9,FXIO0_D10,FXIO0_D11,FXIO0_D12,FXIO0_D13,FXIO0_D14,FXIO0_D15,FXIO0_D16,FXIO0_D17,FXIO0_D18,FXIO0_D19,FXIO0_D20,FXIO0_D21,FXIO0_D22,FXIO0_D23,FXIO0_D24,FXIO0_D25,FXIO0_D26,FXIO0_D27,FXIO0_D28,FXIO0_D29,FXIO0_D30,FXIO0_D31" bitfld.long 0x00 7. " PINPOL ,Shifter pin polarity" "Active high,Active low" bitfld.long 0x00 0.--2. " SMOD ,Configures the mode of the shifter" "Disabled,Receive mode,Transmit mode,,Match store,Match continuous,State mode,Logic mode" newline if (((per.l(ad:0x400DF000+0x80+0x8))&0x07)==0x05) group.long (0x8+0x100)++0x03 line.long 0x00 "SHIFTCFG_2,Shifter Configuration 2 Register" bitfld.long 0x00 16.--20. " PWIDTH ,Parallel width" "1-bit shift,4-bit shift,4-bit shift,4-bit shift,8-bit shift,8-bit shift,8-bit shift,8-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift" bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output" group.long (0x8+0x200)++0x03 line.long 0x00 "SHIFTBUF_2,Shifter Buffer 2 Register" hexmask.long.word 0x00 16.--31. 1. " SHIFTBUF[31:16] ,Shift buffer data to match" newline bitfld.long 0x00 15. " SHIFTBUF[15] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 14. " SHIFTBUF[14] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 13. " SHIFTBUF[13] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 12. " SHIFTBUF[12] ,Shift buffer mask" "Not masked,Masked" newline bitfld.long 0x00 11. " SHIFTBUF[11] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 10. " SHIFTBUF[10] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 9. " SHIFTBUF[9] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 8. " SHIFTBUF[8] ,Shift buffer mask" "Not masked,Masked" newline bitfld.long 0x00 7. " SHIFTBUF[7] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 6. " SHIFTBUF[6] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 5. " SHIFTBUF[5] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 4. " SHIFTBUF[4] ,Shift buffer mask" "Not masked,Masked" newline bitfld.long 0x00 3. " SHIFTBUF[3] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 2. " SHIFTBUF[2] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 1. " SHIFTBUF[1] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 0. " SHIFTBUF[0] ,Shift buffer mask" "Not masked,Masked" group.long (0x8+0x280)++0x03 line.long 0x00 "SHIFTBUFBIS_2,Shifter Buffer 2 Bit Swapped Register" group.long (0x8+0x300)++0x03 line.long 0x00 "SHIFTBUFBYS_2,Shifter Buffer 2 Byte Swapped Register" group.long (0x8+0x380)++0x03 line.long 0x00 "SHIFTBUFBBS_2,Shifter Buffer 2 Bit Byte Swapped Register" else group.long (0x8+0x100)++0x03 line.long 0x00 "SHIFTCFG_2,Shifter Configuration 2 Register" bitfld.long 0x00 16.--20. " PWIDTH ,Parallel width" "1-bit shift,4-bit shift,4-bit shift,4-bit shift,8-bit shift,8-bit shift,8-bit shift,8-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift" bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output" bitfld.long 0x00 4.--5. " SSTOP ,Shifter stop bit" "Disabled,,0 on store,1 on store" newline bitfld.long 0x00 0.--1. " SSTART ,Shifter start bit" "Disabled / load on enable,Disabled / load on first shift,0 before first shift,1 before first shift" group.long (0x8+0x200)++0x03 line.long 0x00 "SHIFTBUF_2,Shifter Buffer 2 Register" group.long (0x8+0x280)++0x03 line.long 0x00 "SHIFTBUFBIS_2,Shifter Buffer 2 Bit Swapped Register" group.long (0x8+0x300)++0x03 line.long 0x00 "SHIFTBUFBYS_2,Shifter Buffer 2 Byte Swapped Register" group.long (0x8+0x380)++0x03 line.long 0x00 "SHIFTBUFBBS_2,Shifter Buffer 2 Bit Byte Swapped Register" endif group.long (0xC+0x80)++0x03 line.long 0x00 "SHIFTCTL_3,Shifter Control 3 Register" bitfld.long 0x00 24.--26. " TIMSEL ,Selects which timer is used for controlling the logic/shift register and generating the shift clock" "Timer 0,Timer 1,Timer 2,Timer 3,Timer 4,Timer 5,Timer 6,Timer 7" bitfld.long 0x00 23. " TIMPOL ,Timer polarity" "Posedge,Negedge" bitfld.long 0x00 16.--17. " PINCFG ,Shifter pin configuration" "Disabled,Open drain or bidir/Out,Bidir/Out data,Output" newline bitfld.long 0x00 8.--12. " PINSEL ,Shifter pin select" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7,FXIO0_D8,FXIO0_D9,FXIO0_D10,FXIO0_D11,FXIO0_D12,FXIO0_D13,FXIO0_D14,FXIO0_D15,FXIO0_D16,FXIO0_D17,FXIO0_D18,FXIO0_D19,FXIO0_D20,FXIO0_D21,FXIO0_D22,FXIO0_D23,FXIO0_D24,FXIO0_D25,FXIO0_D26,FXIO0_D27,FXIO0_D28,FXIO0_D29,FXIO0_D30,FXIO0_D31" bitfld.long 0x00 7. " PINPOL ,Shifter pin polarity" "Active high,Active low" bitfld.long 0x00 0.--2. " SMOD ,Configures the mode of the shifter" "Disabled,Receive mode,Transmit mode,,Match store,Match continuous,State mode,Logic mode" newline if (((per.l(ad:0x400DF000+0x80+0xC))&0x07)==0x05) group.long (0xC+0x100)++0x03 line.long 0x00 "SHIFTCFG_3,Shifter Configuration 3 Register" bitfld.long 0x00 16.--20. " PWIDTH ,Parallel width" "1-bit shift,4-bit shift,4-bit shift,4-bit shift,8-bit shift,8-bit shift,8-bit shift,8-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift" bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output" group.long (0xC+0x200)++0x03 line.long 0x00 "SHIFTBUF_3,Shifter Buffer 3 Register" hexmask.long.word 0x00 16.--31. 1. " SHIFTBUF[31:16] ,Shift buffer data to match" newline bitfld.long 0x00 15. " SHIFTBUF[15] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 14. " SHIFTBUF[14] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 13. " SHIFTBUF[13] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 12. " SHIFTBUF[12] ,Shift buffer mask" "Not masked,Masked" newline bitfld.long 0x00 11. " SHIFTBUF[11] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 10. " SHIFTBUF[10] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 9. " SHIFTBUF[9] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 8. " SHIFTBUF[8] ,Shift buffer mask" "Not masked,Masked" newline bitfld.long 0x00 7. " SHIFTBUF[7] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 6. " SHIFTBUF[6] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 5. " SHIFTBUF[5] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 4. " SHIFTBUF[4] ,Shift buffer mask" "Not masked,Masked" newline bitfld.long 0x00 3. " SHIFTBUF[3] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 2. " SHIFTBUF[2] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 1. " SHIFTBUF[1] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 0. " SHIFTBUF[0] ,Shift buffer mask" "Not masked,Masked" group.long (0xC+0x280)++0x03 line.long 0x00 "SHIFTBUFBIS_3,Shifter Buffer 3 Bit Swapped Register" group.long (0xC+0x300)++0x03 line.long 0x00 "SHIFTBUFBYS_3,Shifter Buffer 3 Byte Swapped Register" group.long (0xC+0x380)++0x03 line.long 0x00 "SHIFTBUFBBS_3,Shifter Buffer 3 Bit Byte Swapped Register" else group.long (0xC+0x100)++0x03 line.long 0x00 "SHIFTCFG_3,Shifter Configuration 3 Register" bitfld.long 0x00 16.--20. " PWIDTH ,Parallel width" "1-bit shift,4-bit shift,4-bit shift,4-bit shift,8-bit shift,8-bit shift,8-bit shift,8-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift" bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output" bitfld.long 0x00 4.--5. " SSTOP ,Shifter stop bit" "Disabled,,0 on store,1 on store" newline bitfld.long 0x00 0.--1. " SSTART ,Shifter start bit" "Disabled / load on enable,Disabled / load on first shift,0 before first shift,1 before first shift" group.long (0xC+0x200)++0x03 line.long 0x00 "SHIFTBUF_3,Shifter Buffer 3 Register" group.long (0xC+0x280)++0x03 line.long 0x00 "SHIFTBUFBIS_3,Shifter Buffer 3 Bit Swapped Register" group.long (0xC+0x300)++0x03 line.long 0x00 "SHIFTBUFBYS_3,Shifter Buffer 3 Byte Swapped Register" group.long (0xC+0x380)++0x03 line.long 0x00 "SHIFTBUFBBS_3,Shifter Buffer 3 Bit Byte Swapped Register" endif group.long (0x10+0x80)++0x03 line.long 0x00 "SHIFTCTL_4,Shifter Control 4 Register" bitfld.long 0x00 24.--26. " TIMSEL ,Selects which timer is used for controlling the logic/shift register and generating the shift clock" "Timer 0,Timer 1,Timer 2,Timer 3,Timer 4,Timer 5,Timer 6,Timer 7" bitfld.long 0x00 23. " TIMPOL ,Timer polarity" "Posedge,Negedge" bitfld.long 0x00 16.--17. " PINCFG ,Shifter pin configuration" "Disabled,Open drain or bidir/Out,Bidir/Out data,Output" newline bitfld.long 0x00 8.--12. " PINSEL ,Shifter pin select" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7,FXIO0_D8,FXIO0_D9,FXIO0_D10,FXIO0_D11,FXIO0_D12,FXIO0_D13,FXIO0_D14,FXIO0_D15,FXIO0_D16,FXIO0_D17,FXIO0_D18,FXIO0_D19,FXIO0_D20,FXIO0_D21,FXIO0_D22,FXIO0_D23,FXIO0_D24,FXIO0_D25,FXIO0_D26,FXIO0_D27,FXIO0_D28,FXIO0_D29,FXIO0_D30,FXIO0_D31" bitfld.long 0x00 7. " PINPOL ,Shifter pin polarity" "Active high,Active low" bitfld.long 0x00 0.--2. " SMOD ,Configures the mode of the shifter" "Disabled,Receive mode,Transmit mode,,Match store,Match continuous,State mode,Logic mode" newline if (((per.l(ad:0x400DF000+0x80+0x10))&0x07)==0x05) group.long (0x10+0x100)++0x03 line.long 0x00 "SHIFTCFG_4,Shifter Configuration 4 Register" bitfld.long 0x00 16.--20. " PWIDTH ,Parallel width" "1-bit shift,4-bit shift,4-bit shift,4-bit shift,8-bit shift,8-bit shift,8-bit shift,8-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift" bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output" group.long (0x10+0x200)++0x03 line.long 0x00 "SHIFTBUF_4,Shifter Buffer 4 Register" hexmask.long.word 0x00 16.--31. 1. " SHIFTBUF[31:16] ,Shift buffer data to match" newline bitfld.long 0x00 15. " SHIFTBUF[15] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 14. " SHIFTBUF[14] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 13. " SHIFTBUF[13] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 12. " SHIFTBUF[12] ,Shift buffer mask" "Not masked,Masked" newline bitfld.long 0x00 11. " SHIFTBUF[11] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 10. " SHIFTBUF[10] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 9. " SHIFTBUF[9] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 8. " SHIFTBUF[8] ,Shift buffer mask" "Not masked,Masked" newline bitfld.long 0x00 7. " SHIFTBUF[7] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 6. " SHIFTBUF[6] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 5. " SHIFTBUF[5] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 4. " SHIFTBUF[4] ,Shift buffer mask" "Not masked,Masked" newline bitfld.long 0x00 3. " SHIFTBUF[3] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 2. " SHIFTBUF[2] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 1. " SHIFTBUF[1] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 0. " SHIFTBUF[0] ,Shift buffer mask" "Not masked,Masked" group.long (0x10+0x280)++0x03 line.long 0x00 "SHIFTBUFBIS_4,Shifter Buffer 4 Bit Swapped Register" group.long (0x10+0x300)++0x03 line.long 0x00 "SHIFTBUFBYS_4,Shifter Buffer 4 Byte Swapped Register" group.long (0x10+0x380)++0x03 line.long 0x00 "SHIFTBUFBBS_4,Shifter Buffer 4 Bit Byte Swapped Register" else group.long (0x10+0x100)++0x03 line.long 0x00 "SHIFTCFG_4,Shifter Configuration 4 Register" bitfld.long 0x00 16.--20. " PWIDTH ,Parallel width" "1-bit shift,4-bit shift,4-bit shift,4-bit shift,8-bit shift,8-bit shift,8-bit shift,8-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift" bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output" bitfld.long 0x00 4.--5. " SSTOP ,Shifter stop bit" "Disabled,,0 on store,1 on store" newline bitfld.long 0x00 0.--1. " SSTART ,Shifter start bit" "Disabled / load on enable,Disabled / load on first shift,0 before first shift,1 before first shift" group.long (0x10+0x200)++0x03 line.long 0x00 "SHIFTBUF_4,Shifter Buffer 4 Register" group.long (0x10+0x280)++0x03 line.long 0x00 "SHIFTBUFBIS_4,Shifter Buffer 4 Bit Swapped Register" group.long (0x10+0x300)++0x03 line.long 0x00 "SHIFTBUFBYS_4,Shifter Buffer 4 Byte Swapped Register" group.long (0x10+0x380)++0x03 line.long 0x00 "SHIFTBUFBBS_4,Shifter Buffer 4 Bit Byte Swapped Register" endif group.long (0x14+0x80)++0x03 line.long 0x00 "SHIFTCTL_5,Shifter Control 5 Register" bitfld.long 0x00 24.--26. " TIMSEL ,Selects which timer is used for controlling the logic/shift register and generating the shift clock" "Timer 0,Timer 1,Timer 2,Timer 3,Timer 4,Timer 5,Timer 6,Timer 7" bitfld.long 0x00 23. " TIMPOL ,Timer polarity" "Posedge,Negedge" bitfld.long 0x00 16.--17. " PINCFG ,Shifter pin configuration" "Disabled,Open drain or bidir/Out,Bidir/Out data,Output" newline bitfld.long 0x00 8.--12. " PINSEL ,Shifter pin select" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7,FXIO0_D8,FXIO0_D9,FXIO0_D10,FXIO0_D11,FXIO0_D12,FXIO0_D13,FXIO0_D14,FXIO0_D15,FXIO0_D16,FXIO0_D17,FXIO0_D18,FXIO0_D19,FXIO0_D20,FXIO0_D21,FXIO0_D22,FXIO0_D23,FXIO0_D24,FXIO0_D25,FXIO0_D26,FXIO0_D27,FXIO0_D28,FXIO0_D29,FXIO0_D30,FXIO0_D31" bitfld.long 0x00 7. " PINPOL ,Shifter pin polarity" "Active high,Active low" bitfld.long 0x00 0.--2. " SMOD ,Configures the mode of the shifter" "Disabled,Receive mode,Transmit mode,,Match store,Match continuous,State mode,Logic mode" newline if (((per.l(ad:0x400DF000+0x80+0x14))&0x07)==0x05) group.long (0x14+0x100)++0x03 line.long 0x00 "SHIFTCFG_5,Shifter Configuration 5 Register" bitfld.long 0x00 16.--20. " PWIDTH ,Parallel width" "1-bit shift,4-bit shift,4-bit shift,4-bit shift,8-bit shift,8-bit shift,8-bit shift,8-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift" bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output" group.long (0x14+0x200)++0x03 line.long 0x00 "SHIFTBUF_5,Shifter Buffer 5 Register" hexmask.long.word 0x00 16.--31. 1. " SHIFTBUF[31:16] ,Shift buffer data to match" newline bitfld.long 0x00 15. " SHIFTBUF[15] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 14. " SHIFTBUF[14] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 13. " SHIFTBUF[13] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 12. " SHIFTBUF[12] ,Shift buffer mask" "Not masked,Masked" newline bitfld.long 0x00 11. " SHIFTBUF[11] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 10. " SHIFTBUF[10] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 9. " SHIFTBUF[9] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 8. " SHIFTBUF[8] ,Shift buffer mask" "Not masked,Masked" newline bitfld.long 0x00 7. " SHIFTBUF[7] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 6. " SHIFTBUF[6] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 5. " SHIFTBUF[5] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 4. " SHIFTBUF[4] ,Shift buffer mask" "Not masked,Masked" newline bitfld.long 0x00 3. " SHIFTBUF[3] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 2. " SHIFTBUF[2] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 1. " SHIFTBUF[1] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 0. " SHIFTBUF[0] ,Shift buffer mask" "Not masked,Masked" group.long (0x14+0x280)++0x03 line.long 0x00 "SHIFTBUFBIS_5,Shifter Buffer 5 Bit Swapped Register" group.long (0x14+0x300)++0x03 line.long 0x00 "SHIFTBUFBYS_5,Shifter Buffer 5 Byte Swapped Register" group.long (0x14+0x380)++0x03 line.long 0x00 "SHIFTBUFBBS_5,Shifter Buffer 5 Bit Byte Swapped Register" else group.long (0x14+0x100)++0x03 line.long 0x00 "SHIFTCFG_5,Shifter Configuration 5 Register" bitfld.long 0x00 16.--20. " PWIDTH ,Parallel width" "1-bit shift,4-bit shift,4-bit shift,4-bit shift,8-bit shift,8-bit shift,8-bit shift,8-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift" bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output" bitfld.long 0x00 4.--5. " SSTOP ,Shifter stop bit" "Disabled,,0 on store,1 on store" newline bitfld.long 0x00 0.--1. " SSTART ,Shifter start bit" "Disabled / load on enable,Disabled / load on first shift,0 before first shift,1 before first shift" group.long (0x14+0x200)++0x03 line.long 0x00 "SHIFTBUF_5,Shifter Buffer 5 Register" group.long (0x14+0x280)++0x03 line.long 0x00 "SHIFTBUFBIS_5,Shifter Buffer 5 Bit Swapped Register" group.long (0x14+0x300)++0x03 line.long 0x00 "SHIFTBUFBYS_5,Shifter Buffer 5 Byte Swapped Register" group.long (0x14+0x380)++0x03 line.long 0x00 "SHIFTBUFBBS_5,Shifter Buffer 5 Bit Byte Swapped Register" endif group.long (0x18+0x80)++0x03 line.long 0x00 "SHIFTCTL_6,Shifter Control 6 Register" bitfld.long 0x00 24.--26. " TIMSEL ,Selects which timer is used for controlling the logic/shift register and generating the shift clock" "Timer 0,Timer 1,Timer 2,Timer 3,Timer 4,Timer 5,Timer 6,Timer 7" bitfld.long 0x00 23. " TIMPOL ,Timer polarity" "Posedge,Negedge" bitfld.long 0x00 16.--17. " PINCFG ,Shifter pin configuration" "Disabled,Open drain or bidir/Out,Bidir/Out data,Output" newline bitfld.long 0x00 8.--12. " PINSEL ,Shifter pin select" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7,FXIO0_D8,FXIO0_D9,FXIO0_D10,FXIO0_D11,FXIO0_D12,FXIO0_D13,FXIO0_D14,FXIO0_D15,FXIO0_D16,FXIO0_D17,FXIO0_D18,FXIO0_D19,FXIO0_D20,FXIO0_D21,FXIO0_D22,FXIO0_D23,FXIO0_D24,FXIO0_D25,FXIO0_D26,FXIO0_D27,FXIO0_D28,FXIO0_D29,FXIO0_D30,FXIO0_D31" bitfld.long 0x00 7. " PINPOL ,Shifter pin polarity" "Active high,Active low" bitfld.long 0x00 0.--2. " SMOD ,Configures the mode of the shifter" "Disabled,Receive mode,Transmit mode,,Match store,Match continuous,State mode,Logic mode" newline if (((per.l(ad:0x400DF000+0x80+0x18))&0x07)==0x05) group.long (0x18+0x100)++0x03 line.long 0x00 "SHIFTCFG_6,Shifter Configuration 6 Register" bitfld.long 0x00 16.--20. " PWIDTH ,Parallel width" "1-bit shift,4-bit shift,4-bit shift,4-bit shift,8-bit shift,8-bit shift,8-bit shift,8-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift" bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output" group.long (0x18+0x200)++0x03 line.long 0x00 "SHIFTBUF_6,Shifter Buffer 6 Register" hexmask.long.word 0x00 16.--31. 1. " SHIFTBUF[31:16] ,Shift buffer data to match" newline bitfld.long 0x00 15. " SHIFTBUF[15] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 14. " SHIFTBUF[14] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 13. " SHIFTBUF[13] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 12. " SHIFTBUF[12] ,Shift buffer mask" "Not masked,Masked" newline bitfld.long 0x00 11. " SHIFTBUF[11] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 10. " SHIFTBUF[10] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 9. " SHIFTBUF[9] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 8. " SHIFTBUF[8] ,Shift buffer mask" "Not masked,Masked" newline bitfld.long 0x00 7. " SHIFTBUF[7] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 6. " SHIFTBUF[6] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 5. " SHIFTBUF[5] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 4. " SHIFTBUF[4] ,Shift buffer mask" "Not masked,Masked" newline bitfld.long 0x00 3. " SHIFTBUF[3] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 2. " SHIFTBUF[2] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 1. " SHIFTBUF[1] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 0. " SHIFTBUF[0] ,Shift buffer mask" "Not masked,Masked" group.long (0x18+0x280)++0x03 line.long 0x00 "SHIFTBUFBIS_6,Shifter Buffer 6 Bit Swapped Register" group.long (0x18+0x300)++0x03 line.long 0x00 "SHIFTBUFBYS_6,Shifter Buffer 6 Byte Swapped Register" group.long (0x18+0x380)++0x03 line.long 0x00 "SHIFTBUFBBS_6,Shifter Buffer 6 Bit Byte Swapped Register" else group.long (0x18+0x100)++0x03 line.long 0x00 "SHIFTCFG_6,Shifter Configuration 6 Register" bitfld.long 0x00 16.--20. " PWIDTH ,Parallel width" "1-bit shift,4-bit shift,4-bit shift,4-bit shift,8-bit shift,8-bit shift,8-bit shift,8-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift" bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output" bitfld.long 0x00 4.--5. " SSTOP ,Shifter stop bit" "Disabled,,0 on store,1 on store" newline bitfld.long 0x00 0.--1. " SSTART ,Shifter start bit" "Disabled / load on enable,Disabled / load on first shift,0 before first shift,1 before first shift" group.long (0x18+0x200)++0x03 line.long 0x00 "SHIFTBUF_6,Shifter Buffer 6 Register" group.long (0x18+0x280)++0x03 line.long 0x00 "SHIFTBUFBIS_6,Shifter Buffer 6 Bit Swapped Register" group.long (0x18+0x300)++0x03 line.long 0x00 "SHIFTBUFBYS_6,Shifter Buffer 6 Byte Swapped Register" group.long (0x18+0x380)++0x03 line.long 0x00 "SHIFTBUFBBS_6,Shifter Buffer 6 Bit Byte Swapped Register" endif group.long (0x1C+0x80)++0x03 line.long 0x00 "SHIFTCTL_7,Shifter Control 7 Register" bitfld.long 0x00 24.--26. " TIMSEL ,Selects which timer is used for controlling the logic/shift register and generating the shift clock" "Timer 0,Timer 1,Timer 2,Timer 3,Timer 4,Timer 5,Timer 6,Timer 7" bitfld.long 0x00 23. " TIMPOL ,Timer polarity" "Posedge,Negedge" bitfld.long 0x00 16.--17. " PINCFG ,Shifter pin configuration" "Disabled,Open drain or bidir/Out,Bidir/Out data,Output" newline bitfld.long 0x00 8.--12. " PINSEL ,Shifter pin select" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7,FXIO0_D8,FXIO0_D9,FXIO0_D10,FXIO0_D11,FXIO0_D12,FXIO0_D13,FXIO0_D14,FXIO0_D15,FXIO0_D16,FXIO0_D17,FXIO0_D18,FXIO0_D19,FXIO0_D20,FXIO0_D21,FXIO0_D22,FXIO0_D23,FXIO0_D24,FXIO0_D25,FXIO0_D26,FXIO0_D27,FXIO0_D28,FXIO0_D29,FXIO0_D30,FXIO0_D31" bitfld.long 0x00 7. " PINPOL ,Shifter pin polarity" "Active high,Active low" bitfld.long 0x00 0.--2. " SMOD ,Configures the mode of the shifter" "Disabled,Receive mode,Transmit mode,,Match store,Match continuous,State mode,Logic mode" newline if (((per.l(ad:0x400DF000+0x80+0x1C))&0x07)==0x05) group.long (0x1C+0x100)++0x03 line.long 0x00 "SHIFTCFG_7,Shifter Configuration 7 Register" bitfld.long 0x00 16.--20. " PWIDTH ,Parallel width" "1-bit shift,4-bit shift,4-bit shift,4-bit shift,8-bit shift,8-bit shift,8-bit shift,8-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift" bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output" group.long (0x1C+0x200)++0x03 line.long 0x00 "SHIFTBUF_7,Shifter Buffer 7 Register" hexmask.long.word 0x00 16.--31. 1. " SHIFTBUF[31:16] ,Shift buffer data to match" newline bitfld.long 0x00 15. " SHIFTBUF[15] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 14. " SHIFTBUF[14] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 13. " SHIFTBUF[13] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 12. " SHIFTBUF[12] ,Shift buffer mask" "Not masked,Masked" newline bitfld.long 0x00 11. " SHIFTBUF[11] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 10. " SHIFTBUF[10] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 9. " SHIFTBUF[9] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 8. " SHIFTBUF[8] ,Shift buffer mask" "Not masked,Masked" newline bitfld.long 0x00 7. " SHIFTBUF[7] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 6. " SHIFTBUF[6] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 5. " SHIFTBUF[5] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 4. " SHIFTBUF[4] ,Shift buffer mask" "Not masked,Masked" newline bitfld.long 0x00 3. " SHIFTBUF[3] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 2. " SHIFTBUF[2] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 1. " SHIFTBUF[1] ,Shift buffer mask" "Not masked,Masked" bitfld.long 0x00 0. " SHIFTBUF[0] ,Shift buffer mask" "Not masked,Masked" group.long (0x1C+0x280)++0x03 line.long 0x00 "SHIFTBUFBIS_7,Shifter Buffer 7 Bit Swapped Register" group.long (0x1C+0x300)++0x03 line.long 0x00 "SHIFTBUFBYS_7,Shifter Buffer 7 Byte Swapped Register" group.long (0x1C+0x380)++0x03 line.long 0x00 "SHIFTBUFBBS_7,Shifter Buffer 7 Bit Byte Swapped Register" else group.long (0x1C+0x100)++0x03 line.long 0x00 "SHIFTCFG_7,Shifter Configuration 7 Register" bitfld.long 0x00 16.--20. " PWIDTH ,Parallel width" "1-bit shift,4-bit shift,4-bit shift,4-bit shift,8-bit shift,8-bit shift,8-bit shift,8-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,16-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift,32-bit shift" bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output" bitfld.long 0x00 4.--5. " SSTOP ,Shifter stop bit" "Disabled,,0 on store,1 on store" newline bitfld.long 0x00 0.--1. " SSTART ,Shifter start bit" "Disabled / load on enable,Disabled / load on first shift,0 before first shift,1 before first shift" group.long (0x1C+0x200)++0x03 line.long 0x00 "SHIFTBUF_7,Shifter Buffer 7 Register" group.long (0x1C+0x280)++0x03 line.long 0x00 "SHIFTBUFBIS_7,Shifter Buffer 7 Bit Swapped Register" group.long (0x1C+0x300)++0x03 line.long 0x00 "SHIFTBUFBYS_7,Shifter Buffer 7 Byte Swapped Register" group.long (0x1C+0x380)++0x03 line.long 0x00 "SHIFTBUFBBS_7,Shifter Buffer 7 Bit Byte Swapped Register" endif tree.end width 10. tree "Timer Registers" if (((per.l(ad:0x400DF000+0x400+0x0))&0x400000)==0x400000) group.long (0x0+0x400)++0x03 line.long 0x00 "TIMCTL_0,Timer Control 0 Register" bitfld.long 0x00 24.--29. " TRGSEL ,Trigger select" "EXTRG_IN,CMP_0,CMP_1,,PIT_0,PIT_1,PIT_2,PIT_3,FTM_0,FTM_1,FTM_2,FTM_3,RTC alarm,RTC seconds,LPTMR,?..." bitfld.long 0x00 23. " TRGPOL ,Trigger polarity" "Active high,Active low" newline bitfld.long 0x00 22. " TRGSRC ,Trigger source" "External,Internal" bitfld.long 0x00 16.--17. " PINCFG ,Timer pin configuration" "Disabled,Open drain or bidir out,Bidir out data,Output" newline bitfld.long 0x00 8.--10. " PINSEL ,Selects which pin is used by the timer input or output" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7" bitfld.long 0x00 7. " PINPOL ,Timer pin polarity" "Active high,Active low" newline bitfld.long 0x00 0.--1. " TMOD ,Timer mode" "Disabled,Dual 8-bit baud/bit,Dual 8-bit PWM,Single 16-bit" else group.long (0x0+0x400)++0x03 line.long 0x00 "TIMCTL_0,Timer Control 0 Register" bitfld.long 0x00 24.--29. " TRGSEL ,Trigger select" "FXIO0_D0,Shifter 0 status flag,FXIO0_D1,Timer 0 trigger output,FXIO0_D2,Shifter 1 status flag,FXIO0_D3,Timer 1 trigger output,FXIO0_D4,Shifter 2 status flag,FXIO0_D5,Timer 2 trigger output,FXIO0_D6,Shifter 3 status flag,FXIO0_D7,Timer 3 trigger output,FXIO0_D8,Shifter 4 status flag,FXIO0_D9,Timer 4 trigger output,FXIO0_D10,Shifter 5 status flag,FXIO0_D11,Timer 5 trigger output,FXIO0_D12,Shifter 6 status flag,FXIO0_D13,Timer 6 trigger output,FXIO0_D14,Shifter 7 status flag,FXIO0_D15,Timer 7 trigger output,FXIO0_D16,,FXIO0_D17,,FXIO0_D18,,FXIO0_D19,,FXIO0_D20,,FXIO0_D21,,FXIO0_D22,,FXIO0_D23,,FXIO0_D24,,FXIO0_D25,,FXIO0_D26,,FXIO0_D27,,FXIO0_D28,,FXIO0_D29,,FXIO0_D30,,FXIO0_D31,?..." bitfld.long 0x00 23. " TRGPOL ,Trigger polarity" "Active high,Active low" newline bitfld.long 0x00 22. " TRGSRC ,Trigger source" "External,Internal" bitfld.long 0x00 16.--17. " PINCFG ,Timer pin configuration" "Disabled,Open drain or bidir out,Bidir out data,Output" newline bitfld.long 0x00 8.--10. " PINSEL ,Selects which pin is used by the timer input or output" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7" bitfld.long 0x00 7. " PINPOL ,Timer pin polarity" "Active high,Active low" newline bitfld.long 0x00 0.--1. " TMOD ,Timer mode" "Disabled,Dual 8-bit baud/bit,Dual 8-bit PWM,Single 16-bit" endif group.long (0x0+0x480)++0x03 line.long 0x00 "TIMCFG_0,Timer Configuration 0 Register" bitfld.long 0x00 24.--25. " TIMOUT ,Configures the initial state of the timer output and whether it is affected by the timer reset" "1 not affected,0 not affected,1 on reset,0 on reset" bitfld.long 0x00 20.--21. " TIMDEC ,Configures the source of the timer decrement and the source of the shift clock" "Flexio clk / shift clk = timer out,Trigger input / shift clk = timer out,Pin input / shift clk = pin input,Trigger input / shift clk = trigger input" newline bitfld.long 0x00 16.--18. " TIMRST ,Configures the condition that causes the timer counter (and optionally the timer output) to be reset" "Never,,Pin == timer output,Trigger == timer output,Pin rising,,Trigger rising,Trigger rising or falling" bitfld.long 0x00 12.--14. " TIMDIS ,Configures the condition that causes the timer to be disabled and stop decrementing" "Never,Timer N+1 dis.,Timer cmp.,Timer cmp. & trigger low,Pin both edges,Pin both edges & trigger high,Trigger falling,?..." newline bitfld.long 0x00 8.--10. " TIMENA ,Configures the condition that causes the timer to be enabled and start decrementing" "Always enabled,Timer N-1 enable,Trigger high,Trigger & pin high,Pin rising,Pin rising & trigger high,Trigger rising,Trigger both edges" bitfld.long 0x00 4.--5. " TSTOP ,Timer stop bit" "Disabled,On timer cmp.,On timer disable,On timer cmp. & disable" newline bitfld.long 0x00 1. " TSTART ,Timer start bit enable" "Disabled,Enabled" if (((per.l(ad:0x400DF000+0x400+0x0))&0x3)==0x1) group.long (0x0+0x500)++0x03 line.long 0x00 "TIMCMP_0,Timer Compare 0 Register" hexmask.long.byte 0x00 8.--15. 1. " CMP[15:8] ,Configures the number of bits in each word equal to (CMP[15:8] + 1)/2" newline hexmask.long.byte 0x00 0.--7. 1. " CMP[7:0] ,Configures the baud rate divider equal to (CMP[7:0] + 1) * 2" elif (((per.l(ad:0x400DF000+0x400+0x0))&0x3)==0x2) group.long (0x0+0x500)++0x03 line.long 0x00 "TIMCMP_0,Timer Compare 0 Register" hexmask.long.byte 0x00 8.--15. 1. " CMP[15:8] ,Configures the low period of the output to (CMP[15:8] + 1) * 2" newline hexmask.long.byte 0x00 0.--7. 1. " CMP[7:0] ,Configures the high period of the output to (CMP[7:0] + 1) * 2" elif (((per.l(ad:0x400DF000+0x400+0x0))&0x3)==0x3) group.long (0x0+0x500)++0x03 line.long 0x00 "TIMCMP_0,Timer Compare 0 Register" hexmask.long.word 0x00 0.--15. 1. " CMP[15:0] ,Baud rate divider (If shift clock source is timer output) to equal (CMP[15:0] + 1)*2 or" else group.long (0x0+0x500)++0x03 line.long 0x00 "TIMCMP_0,Timer Compare 0 Register" hexmask.long.word 0x00 0.--15. 1. " CMP[15:0] ,Timer compare value" endif if (((per.l(ad:0x400DF000+0x400+0x4))&0x400000)==0x400000) group.long (0x4+0x400)++0x03 line.long 0x00 "TIMCTL_1,Timer Control 1 Register" bitfld.long 0x00 24.--29. " TRGSEL ,Trigger select" "EXTRG_IN,CMP_0,CMP_1,,PIT_0,PIT_1,PIT_2,PIT_3,FTM_0,FTM_1,FTM_2,FTM_3,RTC alarm,RTC seconds,LPTMR,?..." bitfld.long 0x00 23. " TRGPOL ,Trigger polarity" "Active high,Active low" newline bitfld.long 0x00 22. " TRGSRC ,Trigger source" "External,Internal" bitfld.long 0x00 16.--17. " PINCFG ,Timer pin configuration" "Disabled,Open drain or bidir out,Bidir out data,Output" newline bitfld.long 0x00 8.--10. " PINSEL ,Selects which pin is used by the timer input or output" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7" bitfld.long 0x00 7. " PINPOL ,Timer pin polarity" "Active high,Active low" newline bitfld.long 0x00 0.--1. " TMOD ,Timer mode" "Disabled,Dual 8-bit baud/bit,Dual 8-bit PWM,Single 16-bit" else group.long (0x4+0x400)++0x03 line.long 0x00 "TIMCTL_1,Timer Control 1 Register" bitfld.long 0x00 24.--29. " TRGSEL ,Trigger select" "FXIO0_D0,Shifter 0 status flag,FXIO0_D1,Timer 0 trigger output,FXIO0_D2,Shifter 1 status flag,FXIO0_D3,Timer 1 trigger output,FXIO0_D4,Shifter 2 status flag,FXIO0_D5,Timer 2 trigger output,FXIO0_D6,Shifter 3 status flag,FXIO0_D7,Timer 3 trigger output,FXIO0_D8,Shifter 4 status flag,FXIO0_D9,Timer 4 trigger output,FXIO0_D10,Shifter 5 status flag,FXIO0_D11,Timer 5 trigger output,FXIO0_D12,Shifter 6 status flag,FXIO0_D13,Timer 6 trigger output,FXIO0_D14,Shifter 7 status flag,FXIO0_D15,Timer 7 trigger output,FXIO0_D16,,FXIO0_D17,,FXIO0_D18,,FXIO0_D19,,FXIO0_D20,,FXIO0_D21,,FXIO0_D22,,FXIO0_D23,,FXIO0_D24,,FXIO0_D25,,FXIO0_D26,,FXIO0_D27,,FXIO0_D28,,FXIO0_D29,,FXIO0_D30,,FXIO0_D31,?..." bitfld.long 0x00 23. " TRGPOL ,Trigger polarity" "Active high,Active low" newline bitfld.long 0x00 22. " TRGSRC ,Trigger source" "External,Internal" bitfld.long 0x00 16.--17. " PINCFG ,Timer pin configuration" "Disabled,Open drain or bidir out,Bidir out data,Output" newline bitfld.long 0x00 8.--10. " PINSEL ,Selects which pin is used by the timer input or output" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7" bitfld.long 0x00 7. " PINPOL ,Timer pin polarity" "Active high,Active low" newline bitfld.long 0x00 0.--1. " TMOD ,Timer mode" "Disabled,Dual 8-bit baud/bit,Dual 8-bit PWM,Single 16-bit" endif group.long (0x4+0x480)++0x03 line.long 0x00 "TIMCFG_1,Timer Configuration 1 Register" bitfld.long 0x00 24.--25. " TIMOUT ,Configures the initial state of the timer output and whether it is affected by the timer reset" "1 not affected,0 not affected,1 on reset,0 on reset" bitfld.long 0x00 20.--21. " TIMDEC ,Configures the source of the timer decrement and the source of the shift clock" "Flexio clk / shift clk = timer out,Trigger input / shift clk = timer out,Pin input / shift clk = pin input,Trigger input / shift clk = trigger input" newline bitfld.long 0x00 16.--18. " TIMRST ,Configures the condition that causes the timer counter (and optionally the timer output) to be reset" "Never,,Pin == timer output,Trigger == timer output,Pin rising,,Trigger rising,Trigger rising or falling" bitfld.long 0x00 12.--14. " TIMDIS ,Configures the condition that causes the timer to be disabled and stop decrementing" "Never,Timer N+1 dis.,Timer cmp.,Timer cmp. & trigger low,Pin both edges,Pin both edges & trigger high,Trigger falling,?..." newline bitfld.long 0x00 8.--10. " TIMENA ,Configures the condition that causes the timer to be enabled and start decrementing" "Always enabled,Timer N-1 enable,Trigger high,Trigger & pin high,Pin rising,Pin rising & trigger high,Trigger rising,Trigger both edges" bitfld.long 0x00 4.--5. " TSTOP ,Timer stop bit" "Disabled,On timer cmp.,On timer disable,On timer cmp. & disable" newline bitfld.long 0x00 1. " TSTART ,Timer start bit enable" "Disabled,Enabled" if (((per.l(ad:0x400DF000+0x400+0x4))&0x3)==0x1) group.long (0x4+0x500)++0x03 line.long 0x00 "TIMCMP_1,Timer Compare 1 Register" hexmask.long.byte 0x00 8.--15. 1. " CMP[15:8] ,Configures the number of bits in each word equal to (CMP[15:8] + 1)/2" newline hexmask.long.byte 0x00 0.--7. 1. " CMP[7:0] ,Configures the baud rate divider equal to (CMP[7:0] + 1) * 2" elif (((per.l(ad:0x400DF000+0x400+0x4))&0x3)==0x2) group.long (0x4+0x500)++0x03 line.long 0x00 "TIMCMP_1,Timer Compare 1 Register" hexmask.long.byte 0x00 8.--15. 1. " CMP[15:8] ,Configures the low period of the output to (CMP[15:8] + 1) * 2" newline hexmask.long.byte 0x00 0.--7. 1. " CMP[7:0] ,Configures the high period of the output to (CMP[7:0] + 1) * 2" elif (((per.l(ad:0x400DF000+0x400+0x4))&0x3)==0x3) group.long (0x4+0x500)++0x03 line.long 0x00 "TIMCMP_1,Timer Compare 1 Register" hexmask.long.word 0x00 0.--15. 1. " CMP[15:0] ,Baud rate divider (If shift clock source is timer output) to equal (CMP[15:0] + 1)*2 or" else group.long (0x4+0x500)++0x03 line.long 0x00 "TIMCMP_1,Timer Compare 1 Register" hexmask.long.word 0x00 0.--15. 1. " CMP[15:0] ,Timer compare value" endif if (((per.l(ad:0x400DF000+0x400+0x8))&0x400000)==0x400000) group.long (0x8+0x400)++0x03 line.long 0x00 "TIMCTL_2,Timer Control 2 Register" bitfld.long 0x00 24.--29. " TRGSEL ,Trigger select" "EXTRG_IN,CMP_0,CMP_1,,PIT_0,PIT_1,PIT_2,PIT_3,FTM_0,FTM_1,FTM_2,FTM_3,RTC alarm,RTC seconds,LPTMR,?..." bitfld.long 0x00 23. " TRGPOL ,Trigger polarity" "Active high,Active low" newline bitfld.long 0x00 22. " TRGSRC ,Trigger source" "External,Internal" bitfld.long 0x00 16.--17. " PINCFG ,Timer pin configuration" "Disabled,Open drain or bidir out,Bidir out data,Output" newline bitfld.long 0x00 8.--10. " PINSEL ,Selects which pin is used by the timer input or output" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7" bitfld.long 0x00 7. " PINPOL ,Timer pin polarity" "Active high,Active low" newline bitfld.long 0x00 0.--1. " TMOD ,Timer mode" "Disabled,Dual 8-bit baud/bit,Dual 8-bit PWM,Single 16-bit" else group.long (0x8+0x400)++0x03 line.long 0x00 "TIMCTL_2,Timer Control 2 Register" bitfld.long 0x00 24.--29. " TRGSEL ,Trigger select" "FXIO0_D0,Shifter 0 status flag,FXIO0_D1,Timer 0 trigger output,FXIO0_D2,Shifter 1 status flag,FXIO0_D3,Timer 1 trigger output,FXIO0_D4,Shifter 2 status flag,FXIO0_D5,Timer 2 trigger output,FXIO0_D6,Shifter 3 status flag,FXIO0_D7,Timer 3 trigger output,FXIO0_D8,Shifter 4 status flag,FXIO0_D9,Timer 4 trigger output,FXIO0_D10,Shifter 5 status flag,FXIO0_D11,Timer 5 trigger output,FXIO0_D12,Shifter 6 status flag,FXIO0_D13,Timer 6 trigger output,FXIO0_D14,Shifter 7 status flag,FXIO0_D15,Timer 7 trigger output,FXIO0_D16,,FXIO0_D17,,FXIO0_D18,,FXIO0_D19,,FXIO0_D20,,FXIO0_D21,,FXIO0_D22,,FXIO0_D23,,FXIO0_D24,,FXIO0_D25,,FXIO0_D26,,FXIO0_D27,,FXIO0_D28,,FXIO0_D29,,FXIO0_D30,,FXIO0_D31,?..." bitfld.long 0x00 23. " TRGPOL ,Trigger polarity" "Active high,Active low" newline bitfld.long 0x00 22. " TRGSRC ,Trigger source" "External,Internal" bitfld.long 0x00 16.--17. " PINCFG ,Timer pin configuration" "Disabled,Open drain or bidir out,Bidir out data,Output" newline bitfld.long 0x00 8.--10. " PINSEL ,Selects which pin is used by the timer input or output" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7" bitfld.long 0x00 7. " PINPOL ,Timer pin polarity" "Active high,Active low" newline bitfld.long 0x00 0.--1. " TMOD ,Timer mode" "Disabled,Dual 8-bit baud/bit,Dual 8-bit PWM,Single 16-bit" endif group.long (0x8+0x480)++0x03 line.long 0x00 "TIMCFG_2,Timer Configuration 2 Register" bitfld.long 0x00 24.--25. " TIMOUT ,Configures the initial state of the timer output and whether it is affected by the timer reset" "1 not affected,0 not affected,1 on reset,0 on reset" bitfld.long 0x00 20.--21. " TIMDEC ,Configures the source of the timer decrement and the source of the shift clock" "Flexio clk / shift clk = timer out,Trigger input / shift clk = timer out,Pin input / shift clk = pin input,Trigger input / shift clk = trigger input" newline bitfld.long 0x00 16.--18. " TIMRST ,Configures the condition that causes the timer counter (and optionally the timer output) to be reset" "Never,,Pin == timer output,Trigger == timer output,Pin rising,,Trigger rising,Trigger rising or falling" bitfld.long 0x00 12.--14. " TIMDIS ,Configures the condition that causes the timer to be disabled and stop decrementing" "Never,Timer N+1 dis.,Timer cmp.,Timer cmp. & trigger low,Pin both edges,Pin both edges & trigger high,Trigger falling,?..." newline bitfld.long 0x00 8.--10. " TIMENA ,Configures the condition that causes the timer to be enabled and start decrementing" "Always enabled,Timer N-1 enable,Trigger high,Trigger & pin high,Pin rising,Pin rising & trigger high,Trigger rising,Trigger both edges" bitfld.long 0x00 4.--5. " TSTOP ,Timer stop bit" "Disabled,On timer cmp.,On timer disable,On timer cmp. & disable" newline bitfld.long 0x00 1. " TSTART ,Timer start bit enable" "Disabled,Enabled" if (((per.l(ad:0x400DF000+0x400+0x8))&0x3)==0x1) group.long (0x8+0x500)++0x03 line.long 0x00 "TIMCMP_2,Timer Compare 2 Register" hexmask.long.byte 0x00 8.--15. 1. " CMP[15:8] ,Configures the number of bits in each word equal to (CMP[15:8] + 1)/2" newline hexmask.long.byte 0x00 0.--7. 1. " CMP[7:0] ,Configures the baud rate divider equal to (CMP[7:0] + 1) * 2" elif (((per.l(ad:0x400DF000+0x400+0x8))&0x3)==0x2) group.long (0x8+0x500)++0x03 line.long 0x00 "TIMCMP_2,Timer Compare 2 Register" hexmask.long.byte 0x00 8.--15. 1. " CMP[15:8] ,Configures the low period of the output to (CMP[15:8] + 1) * 2" newline hexmask.long.byte 0x00 0.--7. 1. " CMP[7:0] ,Configures the high period of the output to (CMP[7:0] + 1) * 2" elif (((per.l(ad:0x400DF000+0x400+0x8))&0x3)==0x3) group.long (0x8+0x500)++0x03 line.long 0x00 "TIMCMP_2,Timer Compare 2 Register" hexmask.long.word 0x00 0.--15. 1. " CMP[15:0] ,Baud rate divider (If shift clock source is timer output) to equal (CMP[15:0] + 1)*2 or" else group.long (0x8+0x500)++0x03 line.long 0x00 "TIMCMP_2,Timer Compare 2 Register" hexmask.long.word 0x00 0.--15. 1. " CMP[15:0] ,Timer compare value" endif if (((per.l(ad:0x400DF000+0x400+0xC))&0x400000)==0x400000) group.long (0xC+0x400)++0x03 line.long 0x00 "TIMCTL_3,Timer Control 3 Register" bitfld.long 0x00 24.--29. " TRGSEL ,Trigger select" "EXTRG_IN,CMP_0,CMP_1,,PIT_0,PIT_1,PIT_2,PIT_3,FTM_0,FTM_1,FTM_2,FTM_3,RTC alarm,RTC seconds,LPTMR,?..." bitfld.long 0x00 23. " TRGPOL ,Trigger polarity" "Active high,Active low" newline bitfld.long 0x00 22. " TRGSRC ,Trigger source" "External,Internal" bitfld.long 0x00 16.--17. " PINCFG ,Timer pin configuration" "Disabled,Open drain or bidir out,Bidir out data,Output" newline bitfld.long 0x00 8.--10. " PINSEL ,Selects which pin is used by the timer input or output" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7" bitfld.long 0x00 7. " PINPOL ,Timer pin polarity" "Active high,Active low" newline bitfld.long 0x00 0.--1. " TMOD ,Timer mode" "Disabled,Dual 8-bit baud/bit,Dual 8-bit PWM,Single 16-bit" else group.long (0xC+0x400)++0x03 line.long 0x00 "TIMCTL_3,Timer Control 3 Register" bitfld.long 0x00 24.--29. " TRGSEL ,Trigger select" "FXIO0_D0,Shifter 0 status flag,FXIO0_D1,Timer 0 trigger output,FXIO0_D2,Shifter 1 status flag,FXIO0_D3,Timer 1 trigger output,FXIO0_D4,Shifter 2 status flag,FXIO0_D5,Timer 2 trigger output,FXIO0_D6,Shifter 3 status flag,FXIO0_D7,Timer 3 trigger output,FXIO0_D8,Shifter 4 status flag,FXIO0_D9,Timer 4 trigger output,FXIO0_D10,Shifter 5 status flag,FXIO0_D11,Timer 5 trigger output,FXIO0_D12,Shifter 6 status flag,FXIO0_D13,Timer 6 trigger output,FXIO0_D14,Shifter 7 status flag,FXIO0_D15,Timer 7 trigger output,FXIO0_D16,,FXIO0_D17,,FXIO0_D18,,FXIO0_D19,,FXIO0_D20,,FXIO0_D21,,FXIO0_D22,,FXIO0_D23,,FXIO0_D24,,FXIO0_D25,,FXIO0_D26,,FXIO0_D27,,FXIO0_D28,,FXIO0_D29,,FXIO0_D30,,FXIO0_D31,?..." bitfld.long 0x00 23. " TRGPOL ,Trigger polarity" "Active high,Active low" newline bitfld.long 0x00 22. " TRGSRC ,Trigger source" "External,Internal" bitfld.long 0x00 16.--17. " PINCFG ,Timer pin configuration" "Disabled,Open drain or bidir out,Bidir out data,Output" newline bitfld.long 0x00 8.--10. " PINSEL ,Selects which pin is used by the timer input or output" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7" bitfld.long 0x00 7. " PINPOL ,Timer pin polarity" "Active high,Active low" newline bitfld.long 0x00 0.--1. " TMOD ,Timer mode" "Disabled,Dual 8-bit baud/bit,Dual 8-bit PWM,Single 16-bit" endif group.long (0xC+0x480)++0x03 line.long 0x00 "TIMCFG_3,Timer Configuration 3 Register" bitfld.long 0x00 24.--25. " TIMOUT ,Configures the initial state of the timer output and whether it is affected by the timer reset" "1 not affected,0 not affected,1 on reset,0 on reset" bitfld.long 0x00 20.--21. " TIMDEC ,Configures the source of the timer decrement and the source of the shift clock" "Flexio clk / shift clk = timer out,Trigger input / shift clk = timer out,Pin input / shift clk = pin input,Trigger input / shift clk = trigger input" newline bitfld.long 0x00 16.--18. " TIMRST ,Configures the condition that causes the timer counter (and optionally the timer output) to be reset" "Never,,Pin == timer output,Trigger == timer output,Pin rising,,Trigger rising,Trigger rising or falling" bitfld.long 0x00 12.--14. " TIMDIS ,Configures the condition that causes the timer to be disabled and stop decrementing" "Never,Timer N+1 dis.,Timer cmp.,Timer cmp. & trigger low,Pin both edges,Pin both edges & trigger high,Trigger falling,?..." newline bitfld.long 0x00 8.--10. " TIMENA ,Configures the condition that causes the timer to be enabled and start decrementing" "Always enabled,Timer N-1 enable,Trigger high,Trigger & pin high,Pin rising,Pin rising & trigger high,Trigger rising,Trigger both edges" bitfld.long 0x00 4.--5. " TSTOP ,Timer stop bit" "Disabled,On timer cmp.,On timer disable,On timer cmp. & disable" newline bitfld.long 0x00 1. " TSTART ,Timer start bit enable" "Disabled,Enabled" if (((per.l(ad:0x400DF000+0x400+0xC))&0x3)==0x1) group.long (0xC+0x500)++0x03 line.long 0x00 "TIMCMP_3,Timer Compare 3 Register" hexmask.long.byte 0x00 8.--15. 1. " CMP[15:8] ,Configures the number of bits in each word equal to (CMP[15:8] + 1)/2" newline hexmask.long.byte 0x00 0.--7. 1. " CMP[7:0] ,Configures the baud rate divider equal to (CMP[7:0] + 1) * 2" elif (((per.l(ad:0x400DF000+0x400+0xC))&0x3)==0x2) group.long (0xC+0x500)++0x03 line.long 0x00 "TIMCMP_3,Timer Compare 3 Register" hexmask.long.byte 0x00 8.--15. 1. " CMP[15:8] ,Configures the low period of the output to (CMP[15:8] + 1) * 2" newline hexmask.long.byte 0x00 0.--7. 1. " CMP[7:0] ,Configures the high period of the output to (CMP[7:0] + 1) * 2" elif (((per.l(ad:0x400DF000+0x400+0xC))&0x3)==0x3) group.long (0xC+0x500)++0x03 line.long 0x00 "TIMCMP_3,Timer Compare 3 Register" hexmask.long.word 0x00 0.--15. 1. " CMP[15:0] ,Baud rate divider (If shift clock source is timer output) to equal (CMP[15:0] + 1)*2 or" else group.long (0xC+0x500)++0x03 line.long 0x00 "TIMCMP_3,Timer Compare 3 Register" hexmask.long.word 0x00 0.--15. 1. " CMP[15:0] ,Timer compare value" endif if (((per.l(ad:0x400DF000+0x400+0x10))&0x400000)==0x400000) group.long (0x10+0x400)++0x03 line.long 0x00 "TIMCTL_4,Timer Control 4 Register" bitfld.long 0x00 24.--29. " TRGSEL ,Trigger select" "EXTRG_IN,CMP_0,CMP_1,,PIT_0,PIT_1,PIT_2,PIT_3,FTM_0,FTM_1,FTM_2,FTM_3,RTC alarm,RTC seconds,LPTMR,?..." bitfld.long 0x00 23. " TRGPOL ,Trigger polarity" "Active high,Active low" newline bitfld.long 0x00 22. " TRGSRC ,Trigger source" "External,Internal" bitfld.long 0x00 16.--17. " PINCFG ,Timer pin configuration" "Disabled,Open drain or bidir out,Bidir out data,Output" newline bitfld.long 0x00 8.--10. " PINSEL ,Selects which pin is used by the timer input or output" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7" bitfld.long 0x00 7. " PINPOL ,Timer pin polarity" "Active high,Active low" newline bitfld.long 0x00 0.--1. " TMOD ,Timer mode" "Disabled,Dual 8-bit baud/bit,Dual 8-bit PWM,Single 16-bit" else group.long (0x10+0x400)++0x03 line.long 0x00 "TIMCTL_4,Timer Control 4 Register" bitfld.long 0x00 24.--29. " TRGSEL ,Trigger select" "FXIO0_D0,Shifter 0 status flag,FXIO0_D1,Timer 0 trigger output,FXIO0_D2,Shifter 1 status flag,FXIO0_D3,Timer 1 trigger output,FXIO0_D4,Shifter 2 status flag,FXIO0_D5,Timer 2 trigger output,FXIO0_D6,Shifter 3 status flag,FXIO0_D7,Timer 3 trigger output,FXIO0_D8,Shifter 4 status flag,FXIO0_D9,Timer 4 trigger output,FXIO0_D10,Shifter 5 status flag,FXIO0_D11,Timer 5 trigger output,FXIO0_D12,Shifter 6 status flag,FXIO0_D13,Timer 6 trigger output,FXIO0_D14,Shifter 7 status flag,FXIO0_D15,Timer 7 trigger output,FXIO0_D16,,FXIO0_D17,,FXIO0_D18,,FXIO0_D19,,FXIO0_D20,,FXIO0_D21,,FXIO0_D22,,FXIO0_D23,,FXIO0_D24,,FXIO0_D25,,FXIO0_D26,,FXIO0_D27,,FXIO0_D28,,FXIO0_D29,,FXIO0_D30,,FXIO0_D31,?..." bitfld.long 0x00 23. " TRGPOL ,Trigger polarity" "Active high,Active low" newline bitfld.long 0x00 22. " TRGSRC ,Trigger source" "External,Internal" bitfld.long 0x00 16.--17. " PINCFG ,Timer pin configuration" "Disabled,Open drain or bidir out,Bidir out data,Output" newline bitfld.long 0x00 8.--10. " PINSEL ,Selects which pin is used by the timer input or output" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7" bitfld.long 0x00 7. " PINPOL ,Timer pin polarity" "Active high,Active low" newline bitfld.long 0x00 0.--1. " TMOD ,Timer mode" "Disabled,Dual 8-bit baud/bit,Dual 8-bit PWM,Single 16-bit" endif group.long (0x10+0x480)++0x03 line.long 0x00 "TIMCFG_4,Timer Configuration 4 Register" bitfld.long 0x00 24.--25. " TIMOUT ,Configures the initial state of the timer output and whether it is affected by the timer reset" "1 not affected,0 not affected,1 on reset,0 on reset" bitfld.long 0x00 20.--21. " TIMDEC ,Configures the source of the timer decrement and the source of the shift clock" "Flexio clk / shift clk = timer out,Trigger input / shift clk = timer out,Pin input / shift clk = pin input,Trigger input / shift clk = trigger input" newline bitfld.long 0x00 16.--18. " TIMRST ,Configures the condition that causes the timer counter (and optionally the timer output) to be reset" "Never,,Pin == timer output,Trigger == timer output,Pin rising,,Trigger rising,Trigger rising or falling" bitfld.long 0x00 12.--14. " TIMDIS ,Configures the condition that causes the timer to be disabled and stop decrementing" "Never,Timer N+1 dis.,Timer cmp.,Timer cmp. & trigger low,Pin both edges,Pin both edges & trigger high,Trigger falling,?..." newline bitfld.long 0x00 8.--10. " TIMENA ,Configures the condition that causes the timer to be enabled and start decrementing" "Always enabled,Timer N-1 enable,Trigger high,Trigger & pin high,Pin rising,Pin rising & trigger high,Trigger rising,Trigger both edges" bitfld.long 0x00 4.--5. " TSTOP ,Timer stop bit" "Disabled,On timer cmp.,On timer disable,On timer cmp. & disable" newline bitfld.long 0x00 1. " TSTART ,Timer start bit enable" "Disabled,Enabled" if (((per.l(ad:0x400DF000+0x400+0x10))&0x3)==0x1) group.long (0x10+0x500)++0x03 line.long 0x00 "TIMCMP_4,Timer Compare 4 Register" hexmask.long.byte 0x00 8.--15. 1. " CMP[15:8] ,Configures the number of bits in each word equal to (CMP[15:8] + 1)/2" newline hexmask.long.byte 0x00 0.--7. 1. " CMP[7:0] ,Configures the baud rate divider equal to (CMP[7:0] + 1) * 2" elif (((per.l(ad:0x400DF000+0x400+0x10))&0x3)==0x2) group.long (0x10+0x500)++0x03 line.long 0x00 "TIMCMP_4,Timer Compare 4 Register" hexmask.long.byte 0x00 8.--15. 1. " CMP[15:8] ,Configures the low period of the output to (CMP[15:8] + 1) * 2" newline hexmask.long.byte 0x00 0.--7. 1. " CMP[7:0] ,Configures the high period of the output to (CMP[7:0] + 1) * 2" elif (((per.l(ad:0x400DF000+0x400+0x10))&0x3)==0x3) group.long (0x10+0x500)++0x03 line.long 0x00 "TIMCMP_4,Timer Compare 4 Register" hexmask.long.word 0x00 0.--15. 1. " CMP[15:0] ,Baud rate divider (If shift clock source is timer output) to equal (CMP[15:0] + 1)*2 or" else group.long (0x10+0x500)++0x03 line.long 0x00 "TIMCMP_4,Timer Compare 4 Register" hexmask.long.word 0x00 0.--15. 1. " CMP[15:0] ,Timer compare value" endif if (((per.l(ad:0x400DF000+0x400+0x14))&0x400000)==0x400000) group.long (0x14+0x400)++0x03 line.long 0x00 "TIMCTL_5,Timer Control 5 Register" bitfld.long 0x00 24.--29. " TRGSEL ,Trigger select" "EXTRG_IN,CMP_0,CMP_1,,PIT_0,PIT_1,PIT_2,PIT_3,FTM_0,FTM_1,FTM_2,FTM_3,RTC alarm,RTC seconds,LPTMR,?..." bitfld.long 0x00 23. " TRGPOL ,Trigger polarity" "Active high,Active low" newline bitfld.long 0x00 22. " TRGSRC ,Trigger source" "External,Internal" bitfld.long 0x00 16.--17. " PINCFG ,Timer pin configuration" "Disabled,Open drain or bidir out,Bidir out data,Output" newline bitfld.long 0x00 8.--10. " PINSEL ,Selects which pin is used by the timer input or output" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7" bitfld.long 0x00 7. " PINPOL ,Timer pin polarity" "Active high,Active low" newline bitfld.long 0x00 0.--1. " TMOD ,Timer mode" "Disabled,Dual 8-bit baud/bit,Dual 8-bit PWM,Single 16-bit" else group.long (0x14+0x400)++0x03 line.long 0x00 "TIMCTL_5,Timer Control 5 Register" bitfld.long 0x00 24.--29. " TRGSEL ,Trigger select" "FXIO0_D0,Shifter 0 status flag,FXIO0_D1,Timer 0 trigger output,FXIO0_D2,Shifter 1 status flag,FXIO0_D3,Timer 1 trigger output,FXIO0_D4,Shifter 2 status flag,FXIO0_D5,Timer 2 trigger output,FXIO0_D6,Shifter 3 status flag,FXIO0_D7,Timer 3 trigger output,FXIO0_D8,Shifter 4 status flag,FXIO0_D9,Timer 4 trigger output,FXIO0_D10,Shifter 5 status flag,FXIO0_D11,Timer 5 trigger output,FXIO0_D12,Shifter 6 status flag,FXIO0_D13,Timer 6 trigger output,FXIO0_D14,Shifter 7 status flag,FXIO0_D15,Timer 7 trigger output,FXIO0_D16,,FXIO0_D17,,FXIO0_D18,,FXIO0_D19,,FXIO0_D20,,FXIO0_D21,,FXIO0_D22,,FXIO0_D23,,FXIO0_D24,,FXIO0_D25,,FXIO0_D26,,FXIO0_D27,,FXIO0_D28,,FXIO0_D29,,FXIO0_D30,,FXIO0_D31,?..." bitfld.long 0x00 23. " TRGPOL ,Trigger polarity" "Active high,Active low" newline bitfld.long 0x00 22. " TRGSRC ,Trigger source" "External,Internal" bitfld.long 0x00 16.--17. " PINCFG ,Timer pin configuration" "Disabled,Open drain or bidir out,Bidir out data,Output" newline bitfld.long 0x00 8.--10. " PINSEL ,Selects which pin is used by the timer input or output" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7" bitfld.long 0x00 7. " PINPOL ,Timer pin polarity" "Active high,Active low" newline bitfld.long 0x00 0.--1. " TMOD ,Timer mode" "Disabled,Dual 8-bit baud/bit,Dual 8-bit PWM,Single 16-bit" endif group.long (0x14+0x480)++0x03 line.long 0x00 "TIMCFG_5,Timer Configuration 5 Register" bitfld.long 0x00 24.--25. " TIMOUT ,Configures the initial state of the timer output and whether it is affected by the timer reset" "1 not affected,0 not affected,1 on reset,0 on reset" bitfld.long 0x00 20.--21. " TIMDEC ,Configures the source of the timer decrement and the source of the shift clock" "Flexio clk / shift clk = timer out,Trigger input / shift clk = timer out,Pin input / shift clk = pin input,Trigger input / shift clk = trigger input" newline bitfld.long 0x00 16.--18. " TIMRST ,Configures the condition that causes the timer counter (and optionally the timer output) to be reset" "Never,,Pin == timer output,Trigger == timer output,Pin rising,,Trigger rising,Trigger rising or falling" bitfld.long 0x00 12.--14. " TIMDIS ,Configures the condition that causes the timer to be disabled and stop decrementing" "Never,Timer N+1 dis.,Timer cmp.,Timer cmp. & trigger low,Pin both edges,Pin both edges & trigger high,Trigger falling,?..." newline bitfld.long 0x00 8.--10. " TIMENA ,Configures the condition that causes the timer to be enabled and start decrementing" "Always enabled,Timer N-1 enable,Trigger high,Trigger & pin high,Pin rising,Pin rising & trigger high,Trigger rising,Trigger both edges" bitfld.long 0x00 4.--5. " TSTOP ,Timer stop bit" "Disabled,On timer cmp.,On timer disable,On timer cmp. & disable" newline bitfld.long 0x00 1. " TSTART ,Timer start bit enable" "Disabled,Enabled" if (((per.l(ad:0x400DF000+0x400+0x14))&0x3)==0x1) group.long (0x14+0x500)++0x03 line.long 0x00 "TIMCMP_5,Timer Compare 5 Register" hexmask.long.byte 0x00 8.--15. 1. " CMP[15:8] ,Configures the number of bits in each word equal to (CMP[15:8] + 1)/2" newline hexmask.long.byte 0x00 0.--7. 1. " CMP[7:0] ,Configures the baud rate divider equal to (CMP[7:0] + 1) * 2" elif (((per.l(ad:0x400DF000+0x400+0x14))&0x3)==0x2) group.long (0x14+0x500)++0x03 line.long 0x00 "TIMCMP_5,Timer Compare 5 Register" hexmask.long.byte 0x00 8.--15. 1. " CMP[15:8] ,Configures the low period of the output to (CMP[15:8] + 1) * 2" newline hexmask.long.byte 0x00 0.--7. 1. " CMP[7:0] ,Configures the high period of the output to (CMP[7:0] + 1) * 2" elif (((per.l(ad:0x400DF000+0x400+0x14))&0x3)==0x3) group.long (0x14+0x500)++0x03 line.long 0x00 "TIMCMP_5,Timer Compare 5 Register" hexmask.long.word 0x00 0.--15. 1. " CMP[15:0] ,Baud rate divider (If shift clock source is timer output) to equal (CMP[15:0] + 1)*2 or" else group.long (0x14+0x500)++0x03 line.long 0x00 "TIMCMP_5,Timer Compare 5 Register" hexmask.long.word 0x00 0.--15. 1. " CMP[15:0] ,Timer compare value" endif if (((per.l(ad:0x400DF000+0x400+0x18))&0x400000)==0x400000) group.long (0x18+0x400)++0x03 line.long 0x00 "TIMCTL_6,Timer Control 6 Register" bitfld.long 0x00 24.--29. " TRGSEL ,Trigger select" "EXTRG_IN,CMP_0,CMP_1,,PIT_0,PIT_1,PIT_2,PIT_3,FTM_0,FTM_1,FTM_2,FTM_3,RTC alarm,RTC seconds,LPTMR,?..." bitfld.long 0x00 23. " TRGPOL ,Trigger polarity" "Active high,Active low" newline bitfld.long 0x00 22. " TRGSRC ,Trigger source" "External,Internal" bitfld.long 0x00 16.--17. " PINCFG ,Timer pin configuration" "Disabled,Open drain or bidir out,Bidir out data,Output" newline bitfld.long 0x00 8.--10. " PINSEL ,Selects which pin is used by the timer input or output" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7" bitfld.long 0x00 7. " PINPOL ,Timer pin polarity" "Active high,Active low" newline bitfld.long 0x00 0.--1. " TMOD ,Timer mode" "Disabled,Dual 8-bit baud/bit,Dual 8-bit PWM,Single 16-bit" else group.long (0x18+0x400)++0x03 line.long 0x00 "TIMCTL_6,Timer Control 6 Register" bitfld.long 0x00 24.--29. " TRGSEL ,Trigger select" "FXIO0_D0,Shifter 0 status flag,FXIO0_D1,Timer 0 trigger output,FXIO0_D2,Shifter 1 status flag,FXIO0_D3,Timer 1 trigger output,FXIO0_D4,Shifter 2 status flag,FXIO0_D5,Timer 2 trigger output,FXIO0_D6,Shifter 3 status flag,FXIO0_D7,Timer 3 trigger output,FXIO0_D8,Shifter 4 status flag,FXIO0_D9,Timer 4 trigger output,FXIO0_D10,Shifter 5 status flag,FXIO0_D11,Timer 5 trigger output,FXIO0_D12,Shifter 6 status flag,FXIO0_D13,Timer 6 trigger output,FXIO0_D14,Shifter 7 status flag,FXIO0_D15,Timer 7 trigger output,FXIO0_D16,,FXIO0_D17,,FXIO0_D18,,FXIO0_D19,,FXIO0_D20,,FXIO0_D21,,FXIO0_D22,,FXIO0_D23,,FXIO0_D24,,FXIO0_D25,,FXIO0_D26,,FXIO0_D27,,FXIO0_D28,,FXIO0_D29,,FXIO0_D30,,FXIO0_D31,?..." bitfld.long 0x00 23. " TRGPOL ,Trigger polarity" "Active high,Active low" newline bitfld.long 0x00 22. " TRGSRC ,Trigger source" "External,Internal" bitfld.long 0x00 16.--17. " PINCFG ,Timer pin configuration" "Disabled,Open drain or bidir out,Bidir out data,Output" newline bitfld.long 0x00 8.--10. " PINSEL ,Selects which pin is used by the timer input or output" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7" bitfld.long 0x00 7. " PINPOL ,Timer pin polarity" "Active high,Active low" newline bitfld.long 0x00 0.--1. " TMOD ,Timer mode" "Disabled,Dual 8-bit baud/bit,Dual 8-bit PWM,Single 16-bit" endif group.long (0x18+0x480)++0x03 line.long 0x00 "TIMCFG_6,Timer Configuration 6 Register" bitfld.long 0x00 24.--25. " TIMOUT ,Configures the initial state of the timer output and whether it is affected by the timer reset" "1 not affected,0 not affected,1 on reset,0 on reset" bitfld.long 0x00 20.--21. " TIMDEC ,Configures the source of the timer decrement and the source of the shift clock" "Flexio clk / shift clk = timer out,Trigger input / shift clk = timer out,Pin input / shift clk = pin input,Trigger input / shift clk = trigger input" newline bitfld.long 0x00 16.--18. " TIMRST ,Configures the condition that causes the timer counter (and optionally the timer output) to be reset" "Never,,Pin == timer output,Trigger == timer output,Pin rising,,Trigger rising,Trigger rising or falling" bitfld.long 0x00 12.--14. " TIMDIS ,Configures the condition that causes the timer to be disabled and stop decrementing" "Never,Timer N+1 dis.,Timer cmp.,Timer cmp. & trigger low,Pin both edges,Pin both edges & trigger high,Trigger falling,?..." newline bitfld.long 0x00 8.--10. " TIMENA ,Configures the condition that causes the timer to be enabled and start decrementing" "Always enabled,Timer N-1 enable,Trigger high,Trigger & pin high,Pin rising,Pin rising & trigger high,Trigger rising,Trigger both edges" bitfld.long 0x00 4.--5. " TSTOP ,Timer stop bit" "Disabled,On timer cmp.,On timer disable,On timer cmp. & disable" newline bitfld.long 0x00 1. " TSTART ,Timer start bit enable" "Disabled,Enabled" if (((per.l(ad:0x400DF000+0x400+0x18))&0x3)==0x1) group.long (0x18+0x500)++0x03 line.long 0x00 "TIMCMP_6,Timer Compare 6 Register" hexmask.long.byte 0x00 8.--15. 1. " CMP[15:8] ,Configures the number of bits in each word equal to (CMP[15:8] + 1)/2" newline hexmask.long.byte 0x00 0.--7. 1. " CMP[7:0] ,Configures the baud rate divider equal to (CMP[7:0] + 1) * 2" elif (((per.l(ad:0x400DF000+0x400+0x18))&0x3)==0x2) group.long (0x18+0x500)++0x03 line.long 0x00 "TIMCMP_6,Timer Compare 6 Register" hexmask.long.byte 0x00 8.--15. 1. " CMP[15:8] ,Configures the low period of the output to (CMP[15:8] + 1) * 2" newline hexmask.long.byte 0x00 0.--7. 1. " CMP[7:0] ,Configures the high period of the output to (CMP[7:0] + 1) * 2" elif (((per.l(ad:0x400DF000+0x400+0x18))&0x3)==0x3) group.long (0x18+0x500)++0x03 line.long 0x00 "TIMCMP_6,Timer Compare 6 Register" hexmask.long.word 0x00 0.--15. 1. " CMP[15:0] ,Baud rate divider (If shift clock source is timer output) to equal (CMP[15:0] + 1)*2 or" else group.long (0x18+0x500)++0x03 line.long 0x00 "TIMCMP_6,Timer Compare 6 Register" hexmask.long.word 0x00 0.--15. 1. " CMP[15:0] ,Timer compare value" endif if (((per.l(ad:0x400DF000+0x400+0x1C))&0x400000)==0x400000) group.long (0x1C+0x400)++0x03 line.long 0x00 "TIMCTL_7,Timer Control 7 Register" bitfld.long 0x00 24.--29. " TRGSEL ,Trigger select" "EXTRG_IN,CMP_0,CMP_1,,PIT_0,PIT_1,PIT_2,PIT_3,FTM_0,FTM_1,FTM_2,FTM_3,RTC alarm,RTC seconds,LPTMR,?..." bitfld.long 0x00 23. " TRGPOL ,Trigger polarity" "Active high,Active low" newline bitfld.long 0x00 22. " TRGSRC ,Trigger source" "External,Internal" bitfld.long 0x00 16.--17. " PINCFG ,Timer pin configuration" "Disabled,Open drain or bidir out,Bidir out data,Output" newline bitfld.long 0x00 8.--10. " PINSEL ,Selects which pin is used by the timer input or output" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7" bitfld.long 0x00 7. " PINPOL ,Timer pin polarity" "Active high,Active low" newline bitfld.long 0x00 0.--1. " TMOD ,Timer mode" "Disabled,Dual 8-bit baud/bit,Dual 8-bit PWM,Single 16-bit" else group.long (0x1C+0x400)++0x03 line.long 0x00 "TIMCTL_7,Timer Control 7 Register" bitfld.long 0x00 24.--29. " TRGSEL ,Trigger select" "FXIO0_D0,Shifter 0 status flag,FXIO0_D1,Timer 0 trigger output,FXIO0_D2,Shifter 1 status flag,FXIO0_D3,Timer 1 trigger output,FXIO0_D4,Shifter 2 status flag,FXIO0_D5,Timer 2 trigger output,FXIO0_D6,Shifter 3 status flag,FXIO0_D7,Timer 3 trigger output,FXIO0_D8,Shifter 4 status flag,FXIO0_D9,Timer 4 trigger output,FXIO0_D10,Shifter 5 status flag,FXIO0_D11,Timer 5 trigger output,FXIO0_D12,Shifter 6 status flag,FXIO0_D13,Timer 6 trigger output,FXIO0_D14,Shifter 7 status flag,FXIO0_D15,Timer 7 trigger output,FXIO0_D16,,FXIO0_D17,,FXIO0_D18,,FXIO0_D19,,FXIO0_D20,,FXIO0_D21,,FXIO0_D22,,FXIO0_D23,,FXIO0_D24,,FXIO0_D25,,FXIO0_D26,,FXIO0_D27,,FXIO0_D28,,FXIO0_D29,,FXIO0_D30,,FXIO0_D31,?..." bitfld.long 0x00 23. " TRGPOL ,Trigger polarity" "Active high,Active low" newline bitfld.long 0x00 22. " TRGSRC ,Trigger source" "External,Internal" bitfld.long 0x00 16.--17. " PINCFG ,Timer pin configuration" "Disabled,Open drain or bidir out,Bidir out data,Output" newline bitfld.long 0x00 8.--10. " PINSEL ,Selects which pin is used by the timer input or output" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7" bitfld.long 0x00 7. " PINPOL ,Timer pin polarity" "Active high,Active low" newline bitfld.long 0x00 0.--1. " TMOD ,Timer mode" "Disabled,Dual 8-bit baud/bit,Dual 8-bit PWM,Single 16-bit" endif group.long (0x1C+0x480)++0x03 line.long 0x00 "TIMCFG_7,Timer Configuration 7 Register" bitfld.long 0x00 24.--25. " TIMOUT ,Configures the initial state of the timer output and whether it is affected by the timer reset" "1 not affected,0 not affected,1 on reset,0 on reset" bitfld.long 0x00 20.--21. " TIMDEC ,Configures the source of the timer decrement and the source of the shift clock" "Flexio clk / shift clk = timer out,Trigger input / shift clk = timer out,Pin input / shift clk = pin input,Trigger input / shift clk = trigger input" newline bitfld.long 0x00 16.--18. " TIMRST ,Configures the condition that causes the timer counter (and optionally the timer output) to be reset" "Never,,Pin == timer output,Trigger == timer output,Pin rising,,Trigger rising,Trigger rising or falling" bitfld.long 0x00 12.--14. " TIMDIS ,Configures the condition that causes the timer to be disabled and stop decrementing" "Never,Timer N+1 dis.,Timer cmp.,Timer cmp. & trigger low,Pin both edges,Pin both edges & trigger high,Trigger falling,?..." newline bitfld.long 0x00 8.--10. " TIMENA ,Configures the condition that causes the timer to be enabled and start decrementing" "Always enabled,Timer N-1 enable,Trigger high,Trigger & pin high,Pin rising,Pin rising & trigger high,Trigger rising,Trigger both edges" bitfld.long 0x00 4.--5. " TSTOP ,Timer stop bit" "Disabled,On timer cmp.,On timer disable,On timer cmp. & disable" newline bitfld.long 0x00 1. " TSTART ,Timer start bit enable" "Disabled,Enabled" if (((per.l(ad:0x400DF000+0x400+0x1C))&0x3)==0x1) group.long (0x1C+0x500)++0x03 line.long 0x00 "TIMCMP_7,Timer Compare 7 Register" hexmask.long.byte 0x00 8.--15. 1. " CMP[15:8] ,Configures the number of bits in each word equal to (CMP[15:8] + 1)/2" newline hexmask.long.byte 0x00 0.--7. 1. " CMP[7:0] ,Configures the baud rate divider equal to (CMP[7:0] + 1) * 2" elif (((per.l(ad:0x400DF000+0x400+0x1C))&0x3)==0x2) group.long (0x1C+0x500)++0x03 line.long 0x00 "TIMCMP_7,Timer Compare 7 Register" hexmask.long.byte 0x00 8.--15. 1. " CMP[15:8] ,Configures the low period of the output to (CMP[15:8] + 1) * 2" newline hexmask.long.byte 0x00 0.--7. 1. " CMP[7:0] ,Configures the high period of the output to (CMP[7:0] + 1) * 2" elif (((per.l(ad:0x400DF000+0x400+0x1C))&0x3)==0x3) group.long (0x1C+0x500)++0x03 line.long 0x00 "TIMCMP_7,Timer Compare 7 Register" hexmask.long.word 0x00 0.--15. 1. " CMP[15:0] ,Baud rate divider (If shift clock source is timer output) to equal (CMP[15:0] + 1)*2 or" else group.long (0x1C+0x500)++0x03 line.long 0x00 "TIMCMP_7,Timer Compare 7 Register" hexmask.long.word 0x00 0.--15. 1. " CMP[15:0] ,Timer compare value" endif tree.end width 15. tree "Shifter Buffers" group.long (0x0+0x680)++0x03 line.long 0x00 "SHIFTBUFNBS_0,Shifter Buffer 0 Nibble Byte Swapped Register" group.long (0x0+0x700)++0x03 line.long 0x00 "SHIFTBUFHWS_0,Shifter Buffer 0 Half Word Swapped Register" group.long (0x0+0x780)++0x03 line.long 0x00 "SHIFTBUFNIS_0,Shifter Buffer 0 Nibble Swapped Register" group.long (0x4+0x680)++0x03 line.long 0x00 "SHIFTBUFNBS_1,Shifter Buffer 1 Nibble Byte Swapped Register" group.long (0x4+0x700)++0x03 line.long 0x00 "SHIFTBUFHWS_1,Shifter Buffer 1 Half Word Swapped Register" group.long (0x4+0x780)++0x03 line.long 0x00 "SHIFTBUFNIS_1,Shifter Buffer 1 Nibble Swapped Register" group.long (0x8+0x680)++0x03 line.long 0x00 "SHIFTBUFNBS_2,Shifter Buffer 2 Nibble Byte Swapped Register" group.long (0x8+0x700)++0x03 line.long 0x00 "SHIFTBUFHWS_2,Shifter Buffer 2 Half Word Swapped Register" group.long (0x8+0x780)++0x03 line.long 0x00 "SHIFTBUFNIS_2,Shifter Buffer 2 Nibble Swapped Register" group.long (0xC+0x680)++0x03 line.long 0x00 "SHIFTBUFNBS_3,Shifter Buffer 3 Nibble Byte Swapped Register" group.long (0xC+0x700)++0x03 line.long 0x00 "SHIFTBUFHWS_3,Shifter Buffer 3 Half Word Swapped Register" group.long (0xC+0x780)++0x03 line.long 0x00 "SHIFTBUFNIS_3,Shifter Buffer 3 Nibble Swapped Register" group.long (0x10+0x680)++0x03 line.long 0x00 "SHIFTBUFNBS_4,Shifter Buffer 4 Nibble Byte Swapped Register" group.long (0x10+0x700)++0x03 line.long 0x00 "SHIFTBUFHWS_4,Shifter Buffer 4 Half Word Swapped Register" group.long (0x10+0x780)++0x03 line.long 0x00 "SHIFTBUFNIS_4,Shifter Buffer 4 Nibble Swapped Register" group.long (0x14+0x680)++0x03 line.long 0x00 "SHIFTBUFNBS_5,Shifter Buffer 5 Nibble Byte Swapped Register" group.long (0x14+0x700)++0x03 line.long 0x00 "SHIFTBUFHWS_5,Shifter Buffer 5 Half Word Swapped Register" group.long (0x14+0x780)++0x03 line.long 0x00 "SHIFTBUFNIS_5,Shifter Buffer 5 Nibble Swapped Register" group.long (0x18+0x680)++0x03 line.long 0x00 "SHIFTBUFNBS_6,Shifter Buffer 6 Nibble Byte Swapped Register" group.long (0x18+0x700)++0x03 line.long 0x00 "SHIFTBUFHWS_6,Shifter Buffer 6 Half Word Swapped Register" group.long (0x18+0x780)++0x03 line.long 0x00 "SHIFTBUFNIS_6,Shifter Buffer 6 Nibble Swapped Register" group.long (0x1C+0x680)++0x03 line.long 0x00 "SHIFTBUFNBS_7,Shifter Buffer 7 Nibble Byte Swapped Register" group.long (0x1C+0x700)++0x03 line.long 0x00 "SHIFTBUFHWS_7,Shifter Buffer 7 Half Word Swapped Register" group.long (0x1C+0x780)++0x03 line.long 0x00 "SHIFTBUFNIS_7,Shifter Buffer 7 Nibble Swapped Register" tree.end else width 15. tree "Shifter 0" group.long (0x0+0x80)++0x03 line.long 0x00 "SHIFTCTL_0,Shifter Control 0 Register" bitfld.long 0x00 24.--25. " TIMSEL ,Selects which timer is used for controlling the logic/shift register and generating the shift clock" "Timer 0,Timer 1,Timer 2,Timer 3" bitfld.long 0x00 23. " TIMPOL ,Timer polarity" "Pos. edge,Neg. edge" bitfld.long 0x00 16.--17. " PINCFG ,Shifter pin configuration" "Disabled,Open drain or bidir/Out,Bidir/Out data,Output" newline sif cpuis("IMXRT1021") bitfld.long 0x00 8.--12. " PINSEL ,Shifter pin select" "FXIO_D0,FXIO_D1,FXIO_D2,FXIO_D3,FXIO_D4,FXIO_D5,FXIO_D6,FXIO_D7,FXIO_D8,FXIO_D9,FXIO_D10,FXIO_D11,FXIO_D12,FXIO_D13,FXIO_D14,FXIO_D15,FXIO_D16,FXIO_D17,FXIO_D18,FXIO_D19,FXIO_D20,FXIO_D21,FXIO_D22,FXIO_D23,FXIO_D24,FXIO_D25,FXIO_D26,FXIO_D27,FXIO_D28,FXIO_D29,FXIO_D30,FXIO_D31" else bitfld.long 0x00 8.--10. " PINSEL ,Shifter pin select" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7" endif bitfld.long 0x00 7. " PINPOL ,Shifter pin polarity" "Active high,Active low" sif cpuis("IMXRT1021") bitfld.long 0x00 0.--2. " SMOD ,Configures the mode of the shifter" "Disabled,Receive,Transmit,,Match store,Match continuous,State,Logic" else bitfld.long 0x00 0.--2. " SMOD ,Configures the mode of the shifter" "Disabled,Receive mode,Transmit mode,,Match store,Match continuous,?..." endif newline sif cpuis("IMXRT1021") if ((((per.l(ad:0x400DF000+0x80+0x0))&0x07)==0x05)||(((per.l(ad:0x400DF000+0x80+0x0))&0x07)==0x00)) group.long (0x0+0x100)++0x03 line.long 0x00 "SHIFTCFG_0,Shifter Configuration 0 Register" bitfld.long 0x00 16.--20. " PWIDTH ,Parallel width" "1-bit,4-bit,4-bit,4-bit,8-bit,8-bit,8-bit,8-bit,16-bit,16-bit,16-bit,16-bit,16-bit,16-bit,16-bit,16-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit" newline bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output" elif (((per.l(ad:0x400DF000+0x80+0x0))&0x07)==0x06) group.long (0x0+0x100)++0x03 line.long 0x00 "SHIFTCFG_0,Shifter Configuration 0 Register" bitfld.long 0x00 19. " PWIDTH[3] ,Pin FXIO_D7 disable" "Enabled,Disabled" bitfld.long 0x00 18. " [2] ,Pin FXIO_D6 disable" "Enabled,Disabled" bitfld.long 0x00 17. " [1] ,Pin FXIO_D5 disable" "Enabled,Disabled" bitfld.long 0x00 16. " [0] ,Pin FXIO_D4 disable" "Enabled,Disabled" newline bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output" newline bitfld.long 0x00 5. " SSTOP[1] ,Pin FXIO_D3 disable" "Enabled,Disabled" bitfld.long 0x00 4. " [0] ,Pin FXIO_D2 disable" "Enabled,Disabled" newline bitfld.long 0x00 1. " SSTART[1] ,Pin FXIO_D1 disable" "Enabled,Disabled" bitfld.long 0x00 0. " [0] ,Pin FXIO_D0 disable" "Enabled,Disabled" elif (((per.l(ad:0x400DF000+0x80+0x0))&0x07)==0x07) group.long (0x0+0x100)++0x03 line.long 0x00 "SHIFTCFG_0,Shifter Configuration 0 Register" bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output" newline bitfld.long 0x00 5. " SSTOP[1] ,Pin FXIO_D3 mask" "Not masked,Masked" bitfld.long 0x00 4. " [0] ,Pin FXIO_D2 mask" "Not masked,Masked" newline bitfld.long 0x00 1. " SSTART[1] ,Pin FXIO_D1 mask" "Not masked,Masked" bitfld.long 0x00 0. " [0] ,Pin FXIO_D0 mask" "Not masked,Masked" elif ((((per.l(ad:0x400DF000+0x80+0x0))&0x07)==0x01)||(((per.l(ad:0x400DF000+0x80+0x0))&0x07)==0x02)||(((per.l(ad:0x400DF000+0x80+0x0))&0x07)==0x04)) group.long (0x0+0x100)++0x03 line.long 0x00 "SHIFTCFG_0,Shifter Configuration 0 Register" bitfld.long 0x00 16.--20. " PWIDTH ,Parallel width" "1-bit,4-bit,4-bit,4-bit,8-bit,8-bit,8-bit,8-bit,16-bit,16-bit,16-bit,16-bit,16-bit,16-bit,16-bit,16-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit" newline bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output" newline bitfld.long 0x00 4.--5. " SSTOP ,Shifter stop bit" "Disabled,,Output 0 / Expect 0,Output 1 / Expect 1" newline bitfld.long 0x00 0.--1. " SSTART ,Shifter start bit" "Load on enable,Load on 1st shift,Output 0 / Expect 0,Output 1 / Expect 1" endif group.long (0x0+0x200)++0x03 line.long 0x00 "SHIFTBUF_0,Shifter Buffer 0 Register" group.long (0x0+0x280)++0x03 line.long 0x00 "SHIFTBUFBIS_0,Shifter Buffer 0 Bit Swapped Register" group.long (0x0+0x300)++0x03 line.long 0x00 "SHIFTBUFBYS_0,Shifter Buffer 0 Byte Swapped Register" group.long (0x0+0x380)++0x03 line.long 0x00 "SHIFTBUFBBS_0,Shifter Buffer 0 Bit Byte Swapped Register" else if (((per.l(ad:0x400DF000+0x80+0x0))&0x07)==0x05) group.long (0x0+0x100)++0x03 line.long 0x00 "SHIFTCFG_0,Shifter Configuration 0 Register" bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output" hgroup.long (0x0+0x200)++0x03 hide.long 0x00 "SHIFTBUF_0,Shifter Buffer 0 Register" in hgroup.long (0x0+0x280)++0x03 hide.long 0x00 "SHIFTBUFBIS_0,Shifter Buffer 0 Bit Swapped Register" in hgroup.long (0x0+0x300)++0x03 hide.long 0x00 "SHIFTBUFBYS_0,Shifter Buffer 0 Byte Swapped Register" in hgroup.long (0x0+0x380)++0x03 hide.long 0x00 "SHIFTBUFBBS_0,Shifter Buffer 0 Bit Byte Swapped Register" in else group.long (0x0+0x100)++0x03 line.long 0x00 "SHIFTCFG_0,Shifter Configuration 0 Register" bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output" newline bitfld.long 0x00 4.--5. " SSTOP ,Shifter stop bit" "Disabled,,0 on store,1 on store" newline bitfld.long 0x00 0.--1. " SSTART ,Shifter start bit" "Disabled / load on enable,Disabled / load on first shift,0 before first shift,1 before first shift" group.long (0x0+0x200)++0x03 line.long 0x00 "SHIFTBUF_0,Shifter Buffer 0 Register" group.long (0x0+0x280)++0x03 line.long 0x00 "SHIFTBUFBIS_0,Shifter Buffer 0 Bit Swapped Register" group.long (0x0+0x300)++0x03 line.long 0x00 "SHIFTBUFBYS_0,Shifter Buffer 0 Byte Swapped Register" group.long (0x0+0x380)++0x03 line.long 0x00 "SHIFTBUFBBS_0,Shifter Buffer 0 Bit Byte Swapped Register" endif endif tree.end tree "Shifter 1" group.long (0x4+0x80)++0x03 line.long 0x00 "SHIFTCTL_1,Shifter Control 1 Register" bitfld.long 0x00 24.--25. " TIMSEL ,Selects which timer is used for controlling the logic/shift register and generating the shift clock" "Timer 0,Timer 1,Timer 2,Timer 3" bitfld.long 0x00 23. " TIMPOL ,Timer polarity" "Pos. edge,Neg. edge" bitfld.long 0x00 16.--17. " PINCFG ,Shifter pin configuration" "Disabled,Open drain or bidir/Out,Bidir/Out data,Output" newline sif cpuis("IMXRT1021") bitfld.long 0x00 8.--12. " PINSEL ,Shifter pin select" "FXIO_D0,FXIO_D1,FXIO_D2,FXIO_D3,FXIO_D4,FXIO_D5,FXIO_D6,FXIO_D7,FXIO_D8,FXIO_D9,FXIO_D10,FXIO_D11,FXIO_D12,FXIO_D13,FXIO_D14,FXIO_D15,FXIO_D16,FXIO_D17,FXIO_D18,FXIO_D19,FXIO_D20,FXIO_D21,FXIO_D22,FXIO_D23,FXIO_D24,FXIO_D25,FXIO_D26,FXIO_D27,FXIO_D28,FXIO_D29,FXIO_D30,FXIO_D31" else bitfld.long 0x00 8.--10. " PINSEL ,Shifter pin select" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7" endif bitfld.long 0x00 7. " PINPOL ,Shifter pin polarity" "Active high,Active low" sif cpuis("IMXRT1021") bitfld.long 0x00 0.--2. " SMOD ,Configures the mode of the shifter" "Disabled,Receive,Transmit,,Match store,Match continuous,State,Logic" else bitfld.long 0x00 0.--2. " SMOD ,Configures the mode of the shifter" "Disabled,Receive mode,Transmit mode,,Match store,Match continuous,?..." endif newline sif cpuis("IMXRT1021") if ((((per.l(ad:0x400DF000+0x80+0x4))&0x07)==0x05)||(((per.l(ad:0x400DF000+0x80+0x4))&0x07)==0x00)) group.long (0x4+0x100)++0x03 line.long 0x00 "SHIFTCFG_1,Shifter Configuration 1 Register" bitfld.long 0x00 16.--20. " PWIDTH ,Parallel width" "1-bit,4-bit,4-bit,4-bit,8-bit,8-bit,8-bit,8-bit,16-bit,16-bit,16-bit,16-bit,16-bit,16-bit,16-bit,16-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit" newline bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output" elif (((per.l(ad:0x400DF000+0x80+0x4))&0x07)==0x06) group.long (0x4+0x100)++0x03 line.long 0x00 "SHIFTCFG_1,Shifter Configuration 1 Register" bitfld.long 0x00 19. " PWIDTH[3] ,Pin FXIO_D7 disable" "Enabled,Disabled" bitfld.long 0x00 18. " [2] ,Pin FXIO_D6 disable" "Enabled,Disabled" bitfld.long 0x00 17. " [1] ,Pin FXIO_D5 disable" "Enabled,Disabled" bitfld.long 0x00 16. " [0] ,Pin FXIO_D4 disable" "Enabled,Disabled" newline bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output" newline bitfld.long 0x00 5. " SSTOP[1] ,Pin FXIO_D3 disable" "Enabled,Disabled" bitfld.long 0x00 4. " [0] ,Pin FXIO_D2 disable" "Enabled,Disabled" newline bitfld.long 0x00 1. " SSTART[1] ,Pin FXIO_D1 disable" "Enabled,Disabled" bitfld.long 0x00 0. " [0] ,Pin FXIO_D0 disable" "Enabled,Disabled" elif (((per.l(ad:0x400DF000+0x80+0x4))&0x07)==0x07) group.long (0x4+0x100)++0x03 line.long 0x00 "SHIFTCFG_1,Shifter Configuration 1 Register" bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output" newline bitfld.long 0x00 5. " SSTOP[1] ,Pin FXIO_D3 mask" "Not masked,Masked" bitfld.long 0x00 4. " [0] ,Pin FXIO_D2 mask" "Not masked,Masked" newline bitfld.long 0x00 1. " SSTART[1] ,Pin FXIO_D1 mask" "Not masked,Masked" bitfld.long 0x00 0. " [0] ,Pin FXIO_D0 mask" "Not masked,Masked" elif ((((per.l(ad:0x400DF000+0x80+0x4))&0x07)==0x01)||(((per.l(ad:0x400DF000+0x80+0x4))&0x07)==0x02)||(((per.l(ad:0x400DF000+0x80+0x4))&0x07)==0x04)) group.long (0x4+0x100)++0x03 line.long 0x00 "SHIFTCFG_1,Shifter Configuration 1 Register" bitfld.long 0x00 16.--20. " PWIDTH ,Parallel width" "1-bit,4-bit,4-bit,4-bit,8-bit,8-bit,8-bit,8-bit,16-bit,16-bit,16-bit,16-bit,16-bit,16-bit,16-bit,16-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit" newline bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output" newline bitfld.long 0x00 4.--5. " SSTOP ,Shifter stop bit" "Disabled,,Output 0 / Expect 0,Output 1 / Expect 1" newline bitfld.long 0x00 0.--1. " SSTART ,Shifter start bit" "Load on enable,Load on 1st shift,Output 0 / Expect 0,Output 1 / Expect 1" endif group.long (0x4+0x200)++0x03 line.long 0x00 "SHIFTBUF_1,Shifter Buffer 1 Register" group.long (0x4+0x280)++0x03 line.long 0x00 "SHIFTBUFBIS_1,Shifter Buffer 1 Bit Swapped Register" group.long (0x4+0x300)++0x03 line.long 0x00 "SHIFTBUFBYS_1,Shifter Buffer 1 Byte Swapped Register" group.long (0x4+0x380)++0x03 line.long 0x00 "SHIFTBUFBBS_1,Shifter Buffer 1 Bit Byte Swapped Register" else if (((per.l(ad:0x400DF000+0x80+0x4))&0x07)==0x05) group.long (0x4+0x100)++0x03 line.long 0x00 "SHIFTCFG_1,Shifter Configuration 1 Register" bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output" hgroup.long (0x4+0x200)++0x03 hide.long 0x00 "SHIFTBUF_1,Shifter Buffer 1 Register" in hgroup.long (0x4+0x280)++0x03 hide.long 0x00 "SHIFTBUFBIS_1,Shifter Buffer 1 Bit Swapped Register" in hgroup.long (0x4+0x300)++0x03 hide.long 0x00 "SHIFTBUFBYS_1,Shifter Buffer 1 Byte Swapped Register" in hgroup.long (0x4+0x380)++0x03 hide.long 0x00 "SHIFTBUFBBS_1,Shifter Buffer 1 Bit Byte Swapped Register" in else group.long (0x4+0x100)++0x03 line.long 0x00 "SHIFTCFG_1,Shifter Configuration 1 Register" bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output" newline bitfld.long 0x00 4.--5. " SSTOP ,Shifter stop bit" "Disabled,,0 on store,1 on store" newline bitfld.long 0x00 0.--1. " SSTART ,Shifter start bit" "Disabled / load on enable,Disabled / load on first shift,0 before first shift,1 before first shift" group.long (0x4+0x200)++0x03 line.long 0x00 "SHIFTBUF_1,Shifter Buffer 1 Register" group.long (0x4+0x280)++0x03 line.long 0x00 "SHIFTBUFBIS_1,Shifter Buffer 1 Bit Swapped Register" group.long (0x4+0x300)++0x03 line.long 0x00 "SHIFTBUFBYS_1,Shifter Buffer 1 Byte Swapped Register" group.long (0x4+0x380)++0x03 line.long 0x00 "SHIFTBUFBBS_1,Shifter Buffer 1 Bit Byte Swapped Register" endif endif tree.end tree "Shifter 2" group.long (0x8+0x80)++0x03 line.long 0x00 "SHIFTCTL_2,Shifter Control 2 Register" bitfld.long 0x00 24.--25. " TIMSEL ,Selects which timer is used for controlling the logic/shift register and generating the shift clock" "Timer 0,Timer 1,Timer 2,Timer 3" bitfld.long 0x00 23. " TIMPOL ,Timer polarity" "Pos. edge,Neg. edge" bitfld.long 0x00 16.--17. " PINCFG ,Shifter pin configuration" "Disabled,Open drain or bidir/Out,Bidir/Out data,Output" newline sif cpuis("IMXRT1021") bitfld.long 0x00 8.--12. " PINSEL ,Shifter pin select" "FXIO_D0,FXIO_D1,FXIO_D2,FXIO_D3,FXIO_D4,FXIO_D5,FXIO_D6,FXIO_D7,FXIO_D8,FXIO_D9,FXIO_D10,FXIO_D11,FXIO_D12,FXIO_D13,FXIO_D14,FXIO_D15,FXIO_D16,FXIO_D17,FXIO_D18,FXIO_D19,FXIO_D20,FXIO_D21,FXIO_D22,FXIO_D23,FXIO_D24,FXIO_D25,FXIO_D26,FXIO_D27,FXIO_D28,FXIO_D29,FXIO_D30,FXIO_D31" else bitfld.long 0x00 8.--10. " PINSEL ,Shifter pin select" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7" endif bitfld.long 0x00 7. " PINPOL ,Shifter pin polarity" "Active high,Active low" sif cpuis("IMXRT1021") bitfld.long 0x00 0.--2. " SMOD ,Configures the mode of the shifter" "Disabled,Receive,Transmit,,Match store,Match continuous,State,Logic" else bitfld.long 0x00 0.--2. " SMOD ,Configures the mode of the shifter" "Disabled,Receive mode,Transmit mode,,Match store,Match continuous,?..." endif newline sif cpuis("IMXRT1021") if ((((per.l(ad:0x400DF000+0x80+0x8))&0x07)==0x05)||(((per.l(ad:0x400DF000+0x80+0x8))&0x07)==0x00)) group.long (0x8+0x100)++0x03 line.long 0x00 "SHIFTCFG_2,Shifter Configuration 2 Register" bitfld.long 0x00 16.--20. " PWIDTH ,Parallel width" "1-bit,4-bit,4-bit,4-bit,8-bit,8-bit,8-bit,8-bit,16-bit,16-bit,16-bit,16-bit,16-bit,16-bit,16-bit,16-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit" newline bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output" elif (((per.l(ad:0x400DF000+0x80+0x8))&0x07)==0x06) group.long (0x8+0x100)++0x03 line.long 0x00 "SHIFTCFG_2,Shifter Configuration 2 Register" bitfld.long 0x00 19. " PWIDTH[3] ,Pin FXIO_D7 disable" "Enabled,Disabled" bitfld.long 0x00 18. " [2] ,Pin FXIO_D6 disable" "Enabled,Disabled" bitfld.long 0x00 17. " [1] ,Pin FXIO_D5 disable" "Enabled,Disabled" bitfld.long 0x00 16. " [0] ,Pin FXIO_D4 disable" "Enabled,Disabled" newline bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output" newline bitfld.long 0x00 5. " SSTOP[1] ,Pin FXIO_D3 disable" "Enabled,Disabled" bitfld.long 0x00 4. " [0] ,Pin FXIO_D2 disable" "Enabled,Disabled" newline bitfld.long 0x00 1. " SSTART[1] ,Pin FXIO_D1 disable" "Enabled,Disabled" bitfld.long 0x00 0. " [0] ,Pin FXIO_D0 disable" "Enabled,Disabled" elif (((per.l(ad:0x400DF000+0x80+0x8))&0x07)==0x07) group.long (0x8+0x100)++0x03 line.long 0x00 "SHIFTCFG_2,Shifter Configuration 2 Register" bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output" newline bitfld.long 0x00 5. " SSTOP[1] ,Pin FXIO_D3 mask" "Not masked,Masked" bitfld.long 0x00 4. " [0] ,Pin FXIO_D2 mask" "Not masked,Masked" newline bitfld.long 0x00 1. " SSTART[1] ,Pin FXIO_D1 mask" "Not masked,Masked" bitfld.long 0x00 0. " [0] ,Pin FXIO_D0 mask" "Not masked,Masked" elif ((((per.l(ad:0x400DF000+0x80+0x8))&0x07)==0x01)||(((per.l(ad:0x400DF000+0x80+0x8))&0x07)==0x02)||(((per.l(ad:0x400DF000+0x80+0x8))&0x07)==0x04)) group.long (0x8+0x100)++0x03 line.long 0x00 "SHIFTCFG_2,Shifter Configuration 2 Register" bitfld.long 0x00 16.--20. " PWIDTH ,Parallel width" "1-bit,4-bit,4-bit,4-bit,8-bit,8-bit,8-bit,8-bit,16-bit,16-bit,16-bit,16-bit,16-bit,16-bit,16-bit,16-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit" newline bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output" newline bitfld.long 0x00 4.--5. " SSTOP ,Shifter stop bit" "Disabled,,Output 0 / Expect 0,Output 1 / Expect 1" newline bitfld.long 0x00 0.--1. " SSTART ,Shifter start bit" "Load on enable,Load on 1st shift,Output 0 / Expect 0,Output 1 / Expect 1" endif group.long (0x8+0x200)++0x03 line.long 0x00 "SHIFTBUF_2,Shifter Buffer 2 Register" group.long (0x8+0x280)++0x03 line.long 0x00 "SHIFTBUFBIS_2,Shifter Buffer 2 Bit Swapped Register" group.long (0x8+0x300)++0x03 line.long 0x00 "SHIFTBUFBYS_2,Shifter Buffer 2 Byte Swapped Register" group.long (0x8+0x380)++0x03 line.long 0x00 "SHIFTBUFBBS_2,Shifter Buffer 2 Bit Byte Swapped Register" else if (((per.l(ad:0x400DF000+0x80+0x8))&0x07)==0x05) group.long (0x8+0x100)++0x03 line.long 0x00 "SHIFTCFG_2,Shifter Configuration 2 Register" bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output" hgroup.long (0x8+0x200)++0x03 hide.long 0x00 "SHIFTBUF_2,Shifter Buffer 2 Register" in hgroup.long (0x8+0x280)++0x03 hide.long 0x00 "SHIFTBUFBIS_2,Shifter Buffer 2 Bit Swapped Register" in hgroup.long (0x8+0x300)++0x03 hide.long 0x00 "SHIFTBUFBYS_2,Shifter Buffer 2 Byte Swapped Register" in hgroup.long (0x8+0x380)++0x03 hide.long 0x00 "SHIFTBUFBBS_2,Shifter Buffer 2 Bit Byte Swapped Register" in else group.long (0x8+0x100)++0x03 line.long 0x00 "SHIFTCFG_2,Shifter Configuration 2 Register" bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output" newline bitfld.long 0x00 4.--5. " SSTOP ,Shifter stop bit" "Disabled,,0 on store,1 on store" newline bitfld.long 0x00 0.--1. " SSTART ,Shifter start bit" "Disabled / load on enable,Disabled / load on first shift,0 before first shift,1 before first shift" group.long (0x8+0x200)++0x03 line.long 0x00 "SHIFTBUF_2,Shifter Buffer 2 Register" group.long (0x8+0x280)++0x03 line.long 0x00 "SHIFTBUFBIS_2,Shifter Buffer 2 Bit Swapped Register" group.long (0x8+0x300)++0x03 line.long 0x00 "SHIFTBUFBYS_2,Shifter Buffer 2 Byte Swapped Register" group.long (0x8+0x380)++0x03 line.long 0x00 "SHIFTBUFBBS_2,Shifter Buffer 2 Bit Byte Swapped Register" endif endif tree.end tree "Shifter 3" group.long (0xC+0x80)++0x03 line.long 0x00 "SHIFTCTL_3,Shifter Control 3 Register" bitfld.long 0x00 24.--25. " TIMSEL ,Selects which timer is used for controlling the logic/shift register and generating the shift clock" "Timer 0,Timer 1,Timer 2,Timer 3" bitfld.long 0x00 23. " TIMPOL ,Timer polarity" "Pos. edge,Neg. edge" bitfld.long 0x00 16.--17. " PINCFG ,Shifter pin configuration" "Disabled,Open drain or bidir/Out,Bidir/Out data,Output" newline sif cpuis("IMXRT1021") bitfld.long 0x00 8.--12. " PINSEL ,Shifter pin select" "FXIO_D0,FXIO_D1,FXIO_D2,FXIO_D3,FXIO_D4,FXIO_D5,FXIO_D6,FXIO_D7,FXIO_D8,FXIO_D9,FXIO_D10,FXIO_D11,FXIO_D12,FXIO_D13,FXIO_D14,FXIO_D15,FXIO_D16,FXIO_D17,FXIO_D18,FXIO_D19,FXIO_D20,FXIO_D21,FXIO_D22,FXIO_D23,FXIO_D24,FXIO_D25,FXIO_D26,FXIO_D27,FXIO_D28,FXIO_D29,FXIO_D30,FXIO_D31" else bitfld.long 0x00 8.--10. " PINSEL ,Shifter pin select" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7" endif bitfld.long 0x00 7. " PINPOL ,Shifter pin polarity" "Active high,Active low" sif cpuis("IMXRT1021") bitfld.long 0x00 0.--2. " SMOD ,Configures the mode of the shifter" "Disabled,Receive,Transmit,,Match store,Match continuous,State,Logic" else bitfld.long 0x00 0.--2. " SMOD ,Configures the mode of the shifter" "Disabled,Receive mode,Transmit mode,,Match store,Match continuous,?..." endif newline sif cpuis("IMXRT1021") if ((((per.l(ad:0x400DF000+0x80+0xC))&0x07)==0x05)||(((per.l(ad:0x400DF000+0x80+0xC))&0x07)==0x00)) group.long (0xC+0x100)++0x03 line.long 0x00 "SHIFTCFG_3,Shifter Configuration 3 Register" bitfld.long 0x00 16.--20. " PWIDTH ,Parallel width" "1-bit,4-bit,4-bit,4-bit,8-bit,8-bit,8-bit,8-bit,16-bit,16-bit,16-bit,16-bit,16-bit,16-bit,16-bit,16-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit" newline bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output" elif (((per.l(ad:0x400DF000+0x80+0xC))&0x07)==0x06) group.long (0xC+0x100)++0x03 line.long 0x00 "SHIFTCFG_3,Shifter Configuration 3 Register" bitfld.long 0x00 19. " PWIDTH[3] ,Pin FXIO_D7 disable" "Enabled,Disabled" bitfld.long 0x00 18. " [2] ,Pin FXIO_D6 disable" "Enabled,Disabled" bitfld.long 0x00 17. " [1] ,Pin FXIO_D5 disable" "Enabled,Disabled" bitfld.long 0x00 16. " [0] ,Pin FXIO_D4 disable" "Enabled,Disabled" newline bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output" newline bitfld.long 0x00 5. " SSTOP[1] ,Pin FXIO_D3 disable" "Enabled,Disabled" bitfld.long 0x00 4. " [0] ,Pin FXIO_D2 disable" "Enabled,Disabled" newline bitfld.long 0x00 1. " SSTART[1] ,Pin FXIO_D1 disable" "Enabled,Disabled" bitfld.long 0x00 0. " [0] ,Pin FXIO_D0 disable" "Enabled,Disabled" elif (((per.l(ad:0x400DF000+0x80+0xC))&0x07)==0x07) group.long (0xC+0x100)++0x03 line.long 0x00 "SHIFTCFG_3,Shifter Configuration 3 Register" bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output" newline bitfld.long 0x00 5. " SSTOP[1] ,Pin FXIO_D3 mask" "Not masked,Masked" bitfld.long 0x00 4. " [0] ,Pin FXIO_D2 mask" "Not masked,Masked" newline bitfld.long 0x00 1. " SSTART[1] ,Pin FXIO_D1 mask" "Not masked,Masked" bitfld.long 0x00 0. " [0] ,Pin FXIO_D0 mask" "Not masked,Masked" elif ((((per.l(ad:0x400DF000+0x80+0xC))&0x07)==0x01)||(((per.l(ad:0x400DF000+0x80+0xC))&0x07)==0x02)||(((per.l(ad:0x400DF000+0x80+0xC))&0x07)==0x04)) group.long (0xC+0x100)++0x03 line.long 0x00 "SHIFTCFG_3,Shifter Configuration 3 Register" bitfld.long 0x00 16.--20. " PWIDTH ,Parallel width" "1-bit,4-bit,4-bit,4-bit,8-bit,8-bit,8-bit,8-bit,16-bit,16-bit,16-bit,16-bit,16-bit,16-bit,16-bit,16-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit,32-bit" newline bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output" newline bitfld.long 0x00 4.--5. " SSTOP ,Shifter stop bit" "Disabled,,Output 0 / Expect 0,Output 1 / Expect 1" newline bitfld.long 0x00 0.--1. " SSTART ,Shifter start bit" "Load on enable,Load on 1st shift,Output 0 / Expect 0,Output 1 / Expect 1" endif group.long (0xC+0x200)++0x03 line.long 0x00 "SHIFTBUF_3,Shifter Buffer 3 Register" group.long (0xC+0x280)++0x03 line.long 0x00 "SHIFTBUFBIS_3,Shifter Buffer 3 Bit Swapped Register" group.long (0xC+0x300)++0x03 line.long 0x00 "SHIFTBUFBYS_3,Shifter Buffer 3 Byte Swapped Register" group.long (0xC+0x380)++0x03 line.long 0x00 "SHIFTBUFBBS_3,Shifter Buffer 3 Bit Byte Swapped Register" else if (((per.l(ad:0x400DF000+0x80+0xC))&0x07)==0x05) group.long (0xC+0x100)++0x03 line.long 0x00 "SHIFTCFG_3,Shifter Configuration 3 Register" bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output" hgroup.long (0xC+0x200)++0x03 hide.long 0x00 "SHIFTBUF_3,Shifter Buffer 3 Register" in hgroup.long (0xC+0x280)++0x03 hide.long 0x00 "SHIFTBUFBIS_3,Shifter Buffer 3 Bit Swapped Register" in hgroup.long (0xC+0x300)++0x03 hide.long 0x00 "SHIFTBUFBYS_3,Shifter Buffer 3 Byte Swapped Register" in hgroup.long (0xC+0x380)++0x03 hide.long 0x00 "SHIFTBUFBBS_3,Shifter Buffer 3 Bit Byte Swapped Register" in else group.long (0xC+0x100)++0x03 line.long 0x00 "SHIFTCFG_3,Shifter Configuration 3 Register" bitfld.long 0x00 8. " INSRC ,Selects the input source for the shifter" "Pin,Shifter N+1 output" newline bitfld.long 0x00 4.--5. " SSTOP ,Shifter stop bit" "Disabled,,0 on store,1 on store" newline bitfld.long 0x00 0.--1. " SSTART ,Shifter start bit" "Disabled / load on enable,Disabled / load on first shift,0 before first shift,1 before first shift" group.long (0xC+0x200)++0x03 line.long 0x00 "SHIFTBUF_3,Shifter Buffer 3 Register" group.long (0xC+0x280)++0x03 line.long 0x00 "SHIFTBUFBIS_3,Shifter Buffer 3 Bit Swapped Register" group.long (0xC+0x300)++0x03 line.long 0x00 "SHIFTBUFBYS_3,Shifter Buffer 3 Byte Swapped Register" group.long (0xC+0x380)++0x03 line.long 0x00 "SHIFTBUFBBS_3,Shifter Buffer 3 Bit Byte Swapped Register" endif endif tree.end width 10. tree "Timer 0" if (((per.l(ad:0x400DF000+0x400+0x0))&0x400000)==0x400000) group.long (0x0+0x400)++0x03 line.long 0x00 "TIMCTL_0,Timer Control N Register" sif cpuis("IMXRT1021") bitfld.long 0x00 24.--29. " TRGSEL ,Trigger select" "FXIO0_D0,Shifter 0 status flag,FXIO0_D1,Timer 0 trigger output,FXIO0_D2,Shifter 1 status flag,FXIO0_D3,Timer 1 trigger output,FXIO0_D4,Shifter 2 status flag,FXIO0_D5,Timer 2 trigger output,FXIO0_D6,Shifter 3 status flag,FXIO0_D7,Timer 3 trigger output,FXIO0_D8,,FXIO0_D9,,FXIO0_D10,,FXIO0_D11,,FXIO0_D12,,FXIO0_D13,,FXIO0_D14,,FXIO0_D15,,FXIO0_D16,,FXIO0_D17,,FXIO0_D18,,FXIO0_D19,,FXIO0_D20,,FXIO0_D21,,FXIO0_D22,,FXIO0_D23,,FXIO0_D24,,FXIO0_D25,,FXIO0_D26,,FXIO0_D27,,FXIO0_D28,,FXIO0_D29,,FXIO0_D30,,FXIO0_D31,?..." else bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "EXTRG_IN,CMP_0,,,PIT_0,PIT_1,,,TMP_0,TMP_1,TMP_2,,RTC alarm,RTC seconds,LPTMR,?..." endif newline bitfld.long 0x00 23. " TRGPOL ,Trigger polarity" "Active high,Active low" newline bitfld.long 0x00 22. " TRGSRC ,Trigger source" "External,Internal" bitfld.long 0x00 16.--17. " PINCFG ,Timer pin configuration" "Disabled,Open drain or bidir out,Bidir out data,Output" newline sif cpuis("IMXRT1021") bitfld.long 0x00 8.--12. " PINSEL ,Selects which pin is used by the timer input or output" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7,FXIO0_D8,FXIO0_D9,FXIO0_D10,FXIO0_D11,FXIO0_D12,FXIO0_D13,FXIO0_D14,FXIO0_D15,FXIO0_D16,FXIO0_D17,FXIO0_D18,FXIO0_D19,FXIO0_D20,FXIO0_D21,FXIO0_D22,FXIO0_D23,FXIO0_D24,FXIO0_D25,FXIO0_D26,FXIO0_D27,FXIO0_D28,FXIO0_D29,FXIO0_D30,FXIO0_D31" else bitfld.long 0x00 8.--10. " PINSEL ,Selects which pin is used by the timer input or output" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7" endif bitfld.long 0x00 7. " PINPOL ,Timer pin polarity" "Active high,Active low" newline sif cpuis("IMXRT1021") bitfld.long 0x00 0.--1. " TIMOD ,Timer mode" "Disabled,Dual 8-bit baud/bit,Dual 8-bit PWM,Single 16-bit" else bitfld.long 0x00 0.--1. " TMOD ,Timer mode" "Disabled,Dual 8-bit baud/bit,Dual 8-bit PWM,Single 16-bit" endif else group.long (0x0+0x400)++0x03 "Timer 0" line.long 0x00 "TIMCTL_0,Timer Control N Register" sif cpuis("IMXRT1021") bitfld.long 0x00 24.--29. " TRGSEL ,Trigger select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "FXIO0_D0,Shifter 0 status flag,FXIO0_D1,Timer 0 trigger output,FXIO0_D2,Shifter 1 status flag,FXIO0_D3,Timer 1 trigger output,FXIO0_D4,Shifter 2 status flag,FXIO0_D5,Timer 2 trigger output,FXIO0_D6,Shifter 3 status flag,FXIO0_D7,Timer 3 trigger output" endif newline bitfld.long 0x00 23. " TRGPOL ,Trigger polarity" "Active high,Active low" newline bitfld.long 0x00 22. " TRGSRC ,Trigger source" "External,Internal" bitfld.long 0x00 16.--17. " PINCFG ,Timer pin configuration" "Disabled,Open drain or bidir out,Bidir out data,Output" newline sif cpuis("IMXRT1021") bitfld.long 0x00 8.--12. " PINSEL ,Selects which pin is used by the timer input or output" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7,FXIO0_D8,FXIO0_D9,FXIO0_D10,FXIO0_D11,FXIO0_D12,FXIO0_D13,FXIO0_D14,FXIO0_D15,FXIO0_D16,FXIO0_D17,FXIO0_D18,FXIO0_D19,FXIO0_D20,FXIO0_D21,FXIO0_D22,FXIO0_D23,FXIO0_D24,FXIO0_D25,FXIO0_D26,FXIO0_D27,FXIO0_D28,FXIO0_D29,FXIO0_D30,FXIO0_D31" else bitfld.long 0x00 8.--10. " PINSEL ,Selects which pin is used by the timer input or output" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7" endif bitfld.long 0x00 7. " PINPOL ,Timer pin polarity" "Active high,Active low" newline sif cpuis("IMXRT1021") bitfld.long 0x00 0.--1. " TIMOD ,Timer mode" "Disabled,Dual 8-bit baud/bit,Dual 8-bit PWM,Single 16-bit" else bitfld.long 0x00 0.--1. " TMOD ,Timer mode" "Disabled,Dual 8-bit baud/bit,Dual 8-bit PWM,Single 16-bit" endif endif group.long (0x0+0x480)++0x03 line.long 0x00 "TIMCFG_0,Timer Configuration 0 Register" bitfld.long 0x00 24.--25. " TIMOUT ,Configures the initial state of the timer output and whether it is affected by the timer reset" "1 not affected,0 not affected,1 on reset,0 on reset" bitfld.long 0x00 20.--21. " TIMDEC ,Configures the source of the timer decrement and the source of the shift clock" "Flexio clk / shift clk = timer out,Trigger input / shift clk = timer out,Pin input / shift clk = pin input,Trigger input / shift clk = trigger input" newline bitfld.long 0x00 16.--18. " TIMRST ,Configures the condition that causes the timer counter (And optionally the timer output) to be reset" "Never,,Pin == timer output,Trigger == timer output,Pin rising,,Trigger rising,Trigger rising or falling" bitfld.long 0x00 12.--14. " TIMDIS ,Configures the condition that causes the timer to be disabled and stop decrementing" "Never,Timer N+1 dis,Timer cmp,Timer cmp & trigger low,Pin both edges,Pin both edges & trigger high,Trigger falling,?..." newline bitfld.long 0x00 8.--10. " TIMENA ,Configures the condition that causes the timer to be enabled and start decrementing" "Always enabled,Timer N-1 enable,Trigger high,Trigger & pin high,Pin rising,Pin rising & trigger high,Trigger rising,Trigger both edges" bitfld.long 0x00 4.--5. " TSTOP ,Timer stop bit" "Disabled,On timer cmp,On timer disable,On timer cmp & disable" newline bitfld.long 0x00 1. " TSTART ,Timer start bit enable" "Disabled,Enabled" if (((per.l(ad:0x400DF000+0x400+0x0))&0x3)==0x1) group.long (0x0+0x500)++0x03 line.long 0x00 "TIMCMP_0,Timer Compare 0 Register" hexmask.long.byte 0x00 8.--15. 1. " CMP[15:8] ,Configures the number of bits in each word equal to (CMP[15:8] + 1)/2" newline hexmask.long.byte 0x00 0.--7. 1. " CMP[7:0] ,Configures the baud rate divider equal to (CMP[7:0] + 1) * 2" elif (((per.l(ad:0x400DF000+0x400+0x0))&0x3)==0x2) group.long (0x0+0x500)++0x03 line.long 0x00 "TIMCMP_0,Timer Compare 0 Register" hexmask.long.byte 0x00 8.--15. 1. " CMP[15:8] ,Configures the low period of the output to (CMP[15:8] + 1) * 2" newline hexmask.long.byte 0x00 0.--7. 1. " CMP[7:0] ,Configures the high period of the output to (CMP[7:0] + 1) * 2" elif (((per.l(ad:0x400DF000+0x400+0x0))&0x3)==0x3) group.long (0x0+0x500)++0x03 line.long 0x00 "TIMCMP_0,Timer Compare 0 Register" sif cpuis("IMXRT1021") hexmask.long.word 0x00 0.--15. 1. " CMP[15:0] ,Baud rate divider to equal (CMP[15:0] + 1)*2 (if shift clock source is timer output) or (CMP[15:0] + 1)/2 (if shift clock source is a pin or trigger input)" else hexmask.long.word 0x00 0.--15. 1. " CMP[15:0] ,Baud rate divider (If shift clock source is timer output) to equal (CMP[15:0] + 1)*2 or" endif else group.long (0x0+0x500)++0x03 line.long 0x00 "TIMCMP_0,Timer Compare 0 Register" hexmask.long.word 0x00 0.--15. 1. " CMP[15:0] ,Timer compare value" endif tree.end tree "Timer 1" if (((per.l(ad:0x400DF000+0x400+0x4))&0x400000)==0x400000) group.long (0x4+0x400)++0x03 line.long 0x00 "TIMCTL_1,Timer Control N Register" sif cpuis("IMXRT1021") bitfld.long 0x00 24.--29. " TRGSEL ,Trigger select" "FXIO0_D0,Shifter 0 status flag,FXIO0_D1,Timer 0 trigger output,FXIO0_D2,Shifter 1 status flag,FXIO0_D3,Timer 1 trigger output,FXIO0_D4,Shifter 2 status flag,FXIO0_D5,Timer 2 trigger output,FXIO0_D6,Shifter 3 status flag,FXIO0_D7,Timer 3 trigger output,FXIO0_D8,,FXIO0_D9,,FXIO0_D10,,FXIO0_D11,,FXIO0_D12,,FXIO0_D13,,FXIO0_D14,,FXIO0_D15,,FXIO0_D16,,FXIO0_D17,,FXIO0_D18,,FXIO0_D19,,FXIO0_D20,,FXIO0_D21,,FXIO0_D22,,FXIO0_D23,,FXIO0_D24,,FXIO0_D25,,FXIO0_D26,,FXIO0_D27,,FXIO0_D28,,FXIO0_D29,,FXIO0_D30,,FXIO0_D31,?..." else bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "EXTRG_IN,CMP_0,,,PIT_0,PIT_1,,,TMP_0,TMP_1,TMP_2,,RTC alarm,RTC seconds,LPTMR,?..." endif newline bitfld.long 0x00 23. " TRGPOL ,Trigger polarity" "Active high,Active low" newline bitfld.long 0x00 22. " TRGSRC ,Trigger source" "External,Internal" bitfld.long 0x00 16.--17. " PINCFG ,Timer pin configuration" "Disabled,Open drain or bidir out,Bidir out data,Output" newline sif cpuis("IMXRT1021") bitfld.long 0x00 8.--12. " PINSEL ,Selects which pin is used by the timer input or output" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7,FXIO0_D8,FXIO0_D9,FXIO0_D10,FXIO0_D11,FXIO0_D12,FXIO0_D13,FXIO0_D14,FXIO0_D15,FXIO0_D16,FXIO0_D17,FXIO0_D18,FXIO0_D19,FXIO0_D20,FXIO0_D21,FXIO0_D22,FXIO0_D23,FXIO0_D24,FXIO0_D25,FXIO0_D26,FXIO0_D27,FXIO0_D28,FXIO0_D29,FXIO0_D30,FXIO0_D31" else bitfld.long 0x00 8.--10. " PINSEL ,Selects which pin is used by the timer input or output" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7" endif bitfld.long 0x00 7. " PINPOL ,Timer pin polarity" "Active high,Active low" newline sif cpuis("IMXRT1021") bitfld.long 0x00 0.--1. " TIMOD ,Timer mode" "Disabled,Dual 8-bit baud/bit,Dual 8-bit PWM,Single 16-bit" else bitfld.long 0x00 0.--1. " TMOD ,Timer mode" "Disabled,Dual 8-bit baud/bit,Dual 8-bit PWM,Single 16-bit" endif else group.long (0x4+0x400)++0x03 "Timer 1" line.long 0x00 "TIMCTL_1,Timer Control N Register" sif cpuis("IMXRT1021") bitfld.long 0x00 24.--29. " TRGSEL ,Trigger select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "FXIO0_D0,Shifter 0 status flag,FXIO0_D1,Timer 0 trigger output,FXIO0_D2,Shifter 1 status flag,FXIO0_D3,Timer 1 trigger output,FXIO0_D4,Shifter 2 status flag,FXIO0_D5,Timer 2 trigger output,FXIO0_D6,Shifter 3 status flag,FXIO0_D7,Timer 3 trigger output" endif newline bitfld.long 0x00 23. " TRGPOL ,Trigger polarity" "Active high,Active low" newline bitfld.long 0x00 22. " TRGSRC ,Trigger source" "External,Internal" bitfld.long 0x00 16.--17. " PINCFG ,Timer pin configuration" "Disabled,Open drain or bidir out,Bidir out data,Output" newline sif cpuis("IMXRT1021") bitfld.long 0x00 8.--12. " PINSEL ,Selects which pin is used by the timer input or output" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7,FXIO0_D8,FXIO0_D9,FXIO0_D10,FXIO0_D11,FXIO0_D12,FXIO0_D13,FXIO0_D14,FXIO0_D15,FXIO0_D16,FXIO0_D17,FXIO0_D18,FXIO0_D19,FXIO0_D20,FXIO0_D21,FXIO0_D22,FXIO0_D23,FXIO0_D24,FXIO0_D25,FXIO0_D26,FXIO0_D27,FXIO0_D28,FXIO0_D29,FXIO0_D30,FXIO0_D31" else bitfld.long 0x00 8.--10. " PINSEL ,Selects which pin is used by the timer input or output" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7" endif bitfld.long 0x00 7. " PINPOL ,Timer pin polarity" "Active high,Active low" newline sif cpuis("IMXRT1021") bitfld.long 0x00 0.--1. " TIMOD ,Timer mode" "Disabled,Dual 8-bit baud/bit,Dual 8-bit PWM,Single 16-bit" else bitfld.long 0x00 0.--1. " TMOD ,Timer mode" "Disabled,Dual 8-bit baud/bit,Dual 8-bit PWM,Single 16-bit" endif endif group.long (0x4+0x480)++0x03 line.long 0x00 "TIMCFG_1,Timer Configuration 1 Register" bitfld.long 0x00 24.--25. " TIMOUT ,Configures the initial state of the timer output and whether it is affected by the timer reset" "1 not affected,0 not affected,1 on reset,0 on reset" bitfld.long 0x00 20.--21. " TIMDEC ,Configures the source of the timer decrement and the source of the shift clock" "Flexio clk / shift clk = timer out,Trigger input / shift clk = timer out,Pin input / shift clk = pin input,Trigger input / shift clk = trigger input" newline bitfld.long 0x00 16.--18. " TIMRST ,Configures the condition that causes the timer counter (And optionally the timer output) to be reset" "Never,,Pin == timer output,Trigger == timer output,Pin rising,,Trigger rising,Trigger rising or falling" bitfld.long 0x00 12.--14. " TIMDIS ,Configures the condition that causes the timer to be disabled and stop decrementing" "Never,Timer N+1 dis,Timer cmp,Timer cmp & trigger low,Pin both edges,Pin both edges & trigger high,Trigger falling,?..." newline bitfld.long 0x00 8.--10. " TIMENA ,Configures the condition that causes the timer to be enabled and start decrementing" "Always enabled,Timer N-1 enable,Trigger high,Trigger & pin high,Pin rising,Pin rising & trigger high,Trigger rising,Trigger both edges" bitfld.long 0x00 4.--5. " TSTOP ,Timer stop bit" "Disabled,On timer cmp,On timer disable,On timer cmp & disable" newline bitfld.long 0x00 1. " TSTART ,Timer start bit enable" "Disabled,Enabled" if (((per.l(ad:0x400DF000+0x400+0x4))&0x3)==0x1) group.long (0x4+0x500)++0x03 line.long 0x00 "TIMCMP_1,Timer Compare 1 Register" hexmask.long.byte 0x00 8.--15. 1. " CMP[15:8] ,Configures the number of bits in each word equal to (CMP[15:8] + 1)/2" newline hexmask.long.byte 0x00 0.--7. 1. " CMP[7:0] ,Configures the baud rate divider equal to (CMP[7:0] + 1) * 2" elif (((per.l(ad:0x400DF000+0x400+0x4))&0x3)==0x2) group.long (0x4+0x500)++0x03 line.long 0x00 "TIMCMP_1,Timer Compare 1 Register" hexmask.long.byte 0x00 8.--15. 1. " CMP[15:8] ,Configures the low period of the output to (CMP[15:8] + 1) * 2" newline hexmask.long.byte 0x00 0.--7. 1. " CMP[7:0] ,Configures the high period of the output to (CMP[7:0] + 1) * 2" elif (((per.l(ad:0x400DF000+0x400+0x4))&0x3)==0x3) group.long (0x4+0x500)++0x03 line.long 0x00 "TIMCMP_1,Timer Compare 1 Register" sif cpuis("IMXRT1021") hexmask.long.word 0x00 0.--15. 1. " CMP[15:0] ,Baud rate divider to equal (CMP[15:0] + 1)*2 (if shift clock source is timer output) or (CMP[15:0] + 1)/2 (if shift clock source is a pin or trigger input)" else hexmask.long.word 0x00 0.--15. 1. " CMP[15:0] ,Baud rate divider (If shift clock source is timer output) to equal (CMP[15:0] + 1)*2 or" endif else group.long (0x4+0x500)++0x03 line.long 0x00 "TIMCMP_1,Timer Compare 1 Register" hexmask.long.word 0x00 0.--15. 1. " CMP[15:0] ,Timer compare value" endif tree.end tree "Timer 2" if (((per.l(ad:0x400DF000+0x400+0x8))&0x400000)==0x400000) group.long (0x8+0x400)++0x03 line.long 0x00 "TIMCTL_2,Timer Control N Register" sif cpuis("IMXRT1021") bitfld.long 0x00 24.--29. " TRGSEL ,Trigger select" "FXIO0_D0,Shifter 0 status flag,FXIO0_D1,Timer 0 trigger output,FXIO0_D2,Shifter 1 status flag,FXIO0_D3,Timer 1 trigger output,FXIO0_D4,Shifter 2 status flag,FXIO0_D5,Timer 2 trigger output,FXIO0_D6,Shifter 3 status flag,FXIO0_D7,Timer 3 trigger output,FXIO0_D8,,FXIO0_D9,,FXIO0_D10,,FXIO0_D11,,FXIO0_D12,,FXIO0_D13,,FXIO0_D14,,FXIO0_D15,,FXIO0_D16,,FXIO0_D17,,FXIO0_D18,,FXIO0_D19,,FXIO0_D20,,FXIO0_D21,,FXIO0_D22,,FXIO0_D23,,FXIO0_D24,,FXIO0_D25,,FXIO0_D26,,FXIO0_D27,,FXIO0_D28,,FXIO0_D29,,FXIO0_D30,,FXIO0_D31,?..." else bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "EXTRG_IN,CMP_0,,,PIT_0,PIT_1,,,TMP_0,TMP_1,TMP_2,,RTC alarm,RTC seconds,LPTMR,?..." endif newline bitfld.long 0x00 23. " TRGPOL ,Trigger polarity" "Active high,Active low" newline bitfld.long 0x00 22. " TRGSRC ,Trigger source" "External,Internal" bitfld.long 0x00 16.--17. " PINCFG ,Timer pin configuration" "Disabled,Open drain or bidir out,Bidir out data,Output" newline sif cpuis("IMXRT1021") bitfld.long 0x00 8.--12. " PINSEL ,Selects which pin is used by the timer input or output" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7,FXIO0_D8,FXIO0_D9,FXIO0_D10,FXIO0_D11,FXIO0_D12,FXIO0_D13,FXIO0_D14,FXIO0_D15,FXIO0_D16,FXIO0_D17,FXIO0_D18,FXIO0_D19,FXIO0_D20,FXIO0_D21,FXIO0_D22,FXIO0_D23,FXIO0_D24,FXIO0_D25,FXIO0_D26,FXIO0_D27,FXIO0_D28,FXIO0_D29,FXIO0_D30,FXIO0_D31" else bitfld.long 0x00 8.--10. " PINSEL ,Selects which pin is used by the timer input or output" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7" endif bitfld.long 0x00 7. " PINPOL ,Timer pin polarity" "Active high,Active low" newline sif cpuis("IMXRT1021") bitfld.long 0x00 0.--1. " TIMOD ,Timer mode" "Disabled,Dual 8-bit baud/bit,Dual 8-bit PWM,Single 16-bit" else bitfld.long 0x00 0.--1. " TMOD ,Timer mode" "Disabled,Dual 8-bit baud/bit,Dual 8-bit PWM,Single 16-bit" endif else group.long (0x8+0x400)++0x03 "Timer 2" line.long 0x00 "TIMCTL_2,Timer Control N Register" sif cpuis("IMXRT1021") bitfld.long 0x00 24.--29. " TRGSEL ,Trigger select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "FXIO0_D0,Shifter 0 status flag,FXIO0_D1,Timer 0 trigger output,FXIO0_D2,Shifter 1 status flag,FXIO0_D3,Timer 1 trigger output,FXIO0_D4,Shifter 2 status flag,FXIO0_D5,Timer 2 trigger output,FXIO0_D6,Shifter 3 status flag,FXIO0_D7,Timer 3 trigger output" endif newline bitfld.long 0x00 23. " TRGPOL ,Trigger polarity" "Active high,Active low" newline bitfld.long 0x00 22. " TRGSRC ,Trigger source" "External,Internal" bitfld.long 0x00 16.--17. " PINCFG ,Timer pin configuration" "Disabled,Open drain or bidir out,Bidir out data,Output" newline sif cpuis("IMXRT1021") bitfld.long 0x00 8.--12. " PINSEL ,Selects which pin is used by the timer input or output" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7,FXIO0_D8,FXIO0_D9,FXIO0_D10,FXIO0_D11,FXIO0_D12,FXIO0_D13,FXIO0_D14,FXIO0_D15,FXIO0_D16,FXIO0_D17,FXIO0_D18,FXIO0_D19,FXIO0_D20,FXIO0_D21,FXIO0_D22,FXIO0_D23,FXIO0_D24,FXIO0_D25,FXIO0_D26,FXIO0_D27,FXIO0_D28,FXIO0_D29,FXIO0_D30,FXIO0_D31" else bitfld.long 0x00 8.--10. " PINSEL ,Selects which pin is used by the timer input or output" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7" endif bitfld.long 0x00 7. " PINPOL ,Timer pin polarity" "Active high,Active low" newline sif cpuis("IMXRT1021") bitfld.long 0x00 0.--1. " TIMOD ,Timer mode" "Disabled,Dual 8-bit baud/bit,Dual 8-bit PWM,Single 16-bit" else bitfld.long 0x00 0.--1. " TMOD ,Timer mode" "Disabled,Dual 8-bit baud/bit,Dual 8-bit PWM,Single 16-bit" endif endif group.long (0x8+0x480)++0x03 line.long 0x00 "TIMCFG_2,Timer Configuration 2 Register" bitfld.long 0x00 24.--25. " TIMOUT ,Configures the initial state of the timer output and whether it is affected by the timer reset" "1 not affected,0 not affected,1 on reset,0 on reset" bitfld.long 0x00 20.--21. " TIMDEC ,Configures the source of the timer decrement and the source of the shift clock" "Flexio clk / shift clk = timer out,Trigger input / shift clk = timer out,Pin input / shift clk = pin input,Trigger input / shift clk = trigger input" newline bitfld.long 0x00 16.--18. " TIMRST ,Configures the condition that causes the timer counter (And optionally the timer output) to be reset" "Never,,Pin == timer output,Trigger == timer output,Pin rising,,Trigger rising,Trigger rising or falling" bitfld.long 0x00 12.--14. " TIMDIS ,Configures the condition that causes the timer to be disabled and stop decrementing" "Never,Timer N+1 dis,Timer cmp,Timer cmp & trigger low,Pin both edges,Pin both edges & trigger high,Trigger falling,?..." newline bitfld.long 0x00 8.--10. " TIMENA ,Configures the condition that causes the timer to be enabled and start decrementing" "Always enabled,Timer N-1 enable,Trigger high,Trigger & pin high,Pin rising,Pin rising & trigger high,Trigger rising,Trigger both edges" bitfld.long 0x00 4.--5. " TSTOP ,Timer stop bit" "Disabled,On timer cmp,On timer disable,On timer cmp & disable" newline bitfld.long 0x00 1. " TSTART ,Timer start bit enable" "Disabled,Enabled" if (((per.l(ad:0x400DF000+0x400+0x8))&0x3)==0x1) group.long (0x8+0x500)++0x03 line.long 0x00 "TIMCMP_2,Timer Compare 2 Register" hexmask.long.byte 0x00 8.--15. 1. " CMP[15:8] ,Configures the number of bits in each word equal to (CMP[15:8] + 1)/2" newline hexmask.long.byte 0x00 0.--7. 1. " CMP[7:0] ,Configures the baud rate divider equal to (CMP[7:0] + 1) * 2" elif (((per.l(ad:0x400DF000+0x400+0x8))&0x3)==0x2) group.long (0x8+0x500)++0x03 line.long 0x00 "TIMCMP_2,Timer Compare 2 Register" hexmask.long.byte 0x00 8.--15. 1. " CMP[15:8] ,Configures the low period of the output to (CMP[15:8] + 1) * 2" newline hexmask.long.byte 0x00 0.--7. 1. " CMP[7:0] ,Configures the high period of the output to (CMP[7:0] + 1) * 2" elif (((per.l(ad:0x400DF000+0x400+0x8))&0x3)==0x3) group.long (0x8+0x500)++0x03 line.long 0x00 "TIMCMP_2,Timer Compare 2 Register" sif cpuis("IMXRT1021") hexmask.long.word 0x00 0.--15. 1. " CMP[15:0] ,Baud rate divider to equal (CMP[15:0] + 1)*2 (if shift clock source is timer output) or (CMP[15:0] + 1)/2 (if shift clock source is a pin or trigger input)" else hexmask.long.word 0x00 0.--15. 1. " CMP[15:0] ,Baud rate divider (If shift clock source is timer output) to equal (CMP[15:0] + 1)*2 or" endif else group.long (0x8+0x500)++0x03 line.long 0x00 "TIMCMP_2,Timer Compare 2 Register" hexmask.long.word 0x00 0.--15. 1. " CMP[15:0] ,Timer compare value" endif tree.end tree "Timer 3" if (((per.l(ad:0x400DF000+0x400+0xC))&0x400000)==0x400000) group.long (0xC+0x400)++0x03 line.long 0x00 "TIMCTL_3,Timer Control N Register" sif cpuis("IMXRT1021") bitfld.long 0x00 24.--29. " TRGSEL ,Trigger select" "FXIO0_D0,Shifter 0 status flag,FXIO0_D1,Timer 0 trigger output,FXIO0_D2,Shifter 1 status flag,FXIO0_D3,Timer 1 trigger output,FXIO0_D4,Shifter 2 status flag,FXIO0_D5,Timer 2 trigger output,FXIO0_D6,Shifter 3 status flag,FXIO0_D7,Timer 3 trigger output,FXIO0_D8,,FXIO0_D9,,FXIO0_D10,,FXIO0_D11,,FXIO0_D12,,FXIO0_D13,,FXIO0_D14,,FXIO0_D15,,FXIO0_D16,,FXIO0_D17,,FXIO0_D18,,FXIO0_D19,,FXIO0_D20,,FXIO0_D21,,FXIO0_D22,,FXIO0_D23,,FXIO0_D24,,FXIO0_D25,,FXIO0_D26,,FXIO0_D27,,FXIO0_D28,,FXIO0_D29,,FXIO0_D30,,FXIO0_D31,?..." else bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "EXTRG_IN,CMP_0,,,PIT_0,PIT_1,,,TMP_0,TMP_1,TMP_2,,RTC alarm,RTC seconds,LPTMR,?..." endif newline bitfld.long 0x00 23. " TRGPOL ,Trigger polarity" "Active high,Active low" newline bitfld.long 0x00 22. " TRGSRC ,Trigger source" "External,Internal" bitfld.long 0x00 16.--17. " PINCFG ,Timer pin configuration" "Disabled,Open drain or bidir out,Bidir out data,Output" newline sif cpuis("IMXRT1021") bitfld.long 0x00 8.--12. " PINSEL ,Selects which pin is used by the timer input or output" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7,FXIO0_D8,FXIO0_D9,FXIO0_D10,FXIO0_D11,FXIO0_D12,FXIO0_D13,FXIO0_D14,FXIO0_D15,FXIO0_D16,FXIO0_D17,FXIO0_D18,FXIO0_D19,FXIO0_D20,FXIO0_D21,FXIO0_D22,FXIO0_D23,FXIO0_D24,FXIO0_D25,FXIO0_D26,FXIO0_D27,FXIO0_D28,FXIO0_D29,FXIO0_D30,FXIO0_D31" else bitfld.long 0x00 8.--10. " PINSEL ,Selects which pin is used by the timer input or output" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7" endif bitfld.long 0x00 7. " PINPOL ,Timer pin polarity" "Active high,Active low" newline sif cpuis("IMXRT1021") bitfld.long 0x00 0.--1. " TIMOD ,Timer mode" "Disabled,Dual 8-bit baud/bit,Dual 8-bit PWM,Single 16-bit" else bitfld.long 0x00 0.--1. " TMOD ,Timer mode" "Disabled,Dual 8-bit baud/bit,Dual 8-bit PWM,Single 16-bit" endif else group.long (0xC+0x400)++0x03 "Timer 3" line.long 0x00 "TIMCTL_3,Timer Control N Register" sif cpuis("IMXRT1021") bitfld.long 0x00 24.--29. " TRGSEL ,Trigger select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else bitfld.long 0x00 24.--27. " TRGSEL ,Trigger select" "FXIO0_D0,Shifter 0 status flag,FXIO0_D1,Timer 0 trigger output,FXIO0_D2,Shifter 1 status flag,FXIO0_D3,Timer 1 trigger output,FXIO0_D4,Shifter 2 status flag,FXIO0_D5,Timer 2 trigger output,FXIO0_D6,Shifter 3 status flag,FXIO0_D7,Timer 3 trigger output" endif newline bitfld.long 0x00 23. " TRGPOL ,Trigger polarity" "Active high,Active low" newline bitfld.long 0x00 22. " TRGSRC ,Trigger source" "External,Internal" bitfld.long 0x00 16.--17. " PINCFG ,Timer pin configuration" "Disabled,Open drain or bidir out,Bidir out data,Output" newline sif cpuis("IMXRT1021") bitfld.long 0x00 8.--12. " PINSEL ,Selects which pin is used by the timer input or output" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7,FXIO0_D8,FXIO0_D9,FXIO0_D10,FXIO0_D11,FXIO0_D12,FXIO0_D13,FXIO0_D14,FXIO0_D15,FXIO0_D16,FXIO0_D17,FXIO0_D18,FXIO0_D19,FXIO0_D20,FXIO0_D21,FXIO0_D22,FXIO0_D23,FXIO0_D24,FXIO0_D25,FXIO0_D26,FXIO0_D27,FXIO0_D28,FXIO0_D29,FXIO0_D30,FXIO0_D31" else bitfld.long 0x00 8.--10. " PINSEL ,Selects which pin is used by the timer input or output" "FXIO0_D0,FXIO0_D1,FXIO0_D2,FXIO0_D3,FXIO0_D4,FXIO0_D5,FXIO0_D6,FXIO0_D7" endif bitfld.long 0x00 7. " PINPOL ,Timer pin polarity" "Active high,Active low" newline sif cpuis("IMXRT1021") bitfld.long 0x00 0.--1. " TIMOD ,Timer mode" "Disabled,Dual 8-bit baud/bit,Dual 8-bit PWM,Single 16-bit" else bitfld.long 0x00 0.--1. " TMOD ,Timer mode" "Disabled,Dual 8-bit baud/bit,Dual 8-bit PWM,Single 16-bit" endif endif group.long (0xC+0x480)++0x03 line.long 0x00 "TIMCFG_3,Timer Configuration 3 Register" bitfld.long 0x00 24.--25. " TIMOUT ,Configures the initial state of the timer output and whether it is affected by the timer reset" "1 not affected,0 not affected,1 on reset,0 on reset" bitfld.long 0x00 20.--21. " TIMDEC ,Configures the source of the timer decrement and the source of the shift clock" "Flexio clk / shift clk = timer out,Trigger input / shift clk = timer out,Pin input / shift clk = pin input,Trigger input / shift clk = trigger input" newline bitfld.long 0x00 16.--18. " TIMRST ,Configures the condition that causes the timer counter (And optionally the timer output) to be reset" "Never,,Pin == timer output,Trigger == timer output,Pin rising,,Trigger rising,Trigger rising or falling" bitfld.long 0x00 12.--14. " TIMDIS ,Configures the condition that causes the timer to be disabled and stop decrementing" "Never,Timer N+1 dis,Timer cmp,Timer cmp & trigger low,Pin both edges,Pin both edges & trigger high,Trigger falling,?..." newline bitfld.long 0x00 8.--10. " TIMENA ,Configures the condition that causes the timer to be enabled and start decrementing" "Always enabled,Timer N-1 enable,Trigger high,Trigger & pin high,Pin rising,Pin rising & trigger high,Trigger rising,Trigger both edges" bitfld.long 0x00 4.--5. " TSTOP ,Timer stop bit" "Disabled,On timer cmp,On timer disable,On timer cmp & disable" newline bitfld.long 0x00 1. " TSTART ,Timer start bit enable" "Disabled,Enabled" if (((per.l(ad:0x400DF000+0x400+0xC))&0x3)==0x1) group.long (0xC+0x500)++0x03 line.long 0x00 "TIMCMP_3,Timer Compare 3 Register" hexmask.long.byte 0x00 8.--15. 1. " CMP[15:8] ,Configures the number of bits in each word equal to (CMP[15:8] + 1)/2" newline hexmask.long.byte 0x00 0.--7. 1. " CMP[7:0] ,Configures the baud rate divider equal to (CMP[7:0] + 1) * 2" elif (((per.l(ad:0x400DF000+0x400+0xC))&0x3)==0x2) group.long (0xC+0x500)++0x03 line.long 0x00 "TIMCMP_3,Timer Compare 3 Register" hexmask.long.byte 0x00 8.--15. 1. " CMP[15:8] ,Configures the low period of the output to (CMP[15:8] + 1) * 2" newline hexmask.long.byte 0x00 0.--7. 1. " CMP[7:0] ,Configures the high period of the output to (CMP[7:0] + 1) * 2" elif (((per.l(ad:0x400DF000+0x400+0xC))&0x3)==0x3) group.long (0xC+0x500)++0x03 line.long 0x00 "TIMCMP_3,Timer Compare 3 Register" sif cpuis("IMXRT1021") hexmask.long.word 0x00 0.--15. 1. " CMP[15:0] ,Baud rate divider to equal (CMP[15:0] + 1)*2 (if shift clock source is timer output) or (CMP[15:0] + 1)/2 (if shift clock source is a pin or trigger input)" else hexmask.long.word 0x00 0.--15. 1. " CMP[15:0] ,Baud rate divider (If shift clock source is timer output) to equal (CMP[15:0] + 1)*2 or" endif else group.long (0xC+0x500)++0x03 line.long 0x00 "TIMCMP_3,Timer Compare 3 Register" hexmask.long.word 0x00 0.--15. 1. " CMP[15:0] ,Timer compare value" endif tree.end endif sif cpuis("IMXRT1021") width 14. newline group.long (0x0+0x680)++0x03 line.long 0x00 "SHIFTBUFNBS0,Shifter Buffer 0 Nibble Byte Swapped" group.long (0x0+0x700)++0x03 line.long 0x00 "SHIFTBUFHWS0,Shifter Buffer 0 Half Word Swapped" group.long (0x0+0x780)++0x03 line.long 0x00 "SHIFTBUFNIS0,Shifter Buffer 0 Nibble Swapped" newline group.long (0x4+0x680)++0x03 line.long 0x00 "SHIFTBUFNBS1,Shifter Buffer 1 Nibble Byte Swapped" group.long (0x4+0x700)++0x03 line.long 0x00 "SHIFTBUFHWS1,Shifter Buffer 1 Half Word Swapped" group.long (0x4+0x780)++0x03 line.long 0x00 "SHIFTBUFNIS1,Shifter Buffer 1 Nibble Swapped" newline group.long (0x8+0x680)++0x03 line.long 0x00 "SHIFTBUFNBS2,Shifter Buffer 2 Nibble Byte Swapped" group.long (0x8+0x700)++0x03 line.long 0x00 "SHIFTBUFHWS2,Shifter Buffer 2 Half Word Swapped" group.long (0x8+0x780)++0x03 line.long 0x00 "SHIFTBUFNIS2,Shifter Buffer 2 Nibble Swapped" newline group.long (0xC+0x680)++0x03 line.long 0x00 "SHIFTBUFNBS3,Shifter Buffer 3 Nibble Byte Swapped" group.long (0xC+0x700)++0x03 line.long 0x00 "SHIFTBUFHWS3,Shifter Buffer 3 Half Word Swapped" group.long (0xC+0x780)++0x03 line.long 0x00 "SHIFTBUFNIS3,Shifter Buffer 3 Nibble Swapped" endif width 0x0B tree.end tree "I2S/SAI (Integrated Interchip Sound/Synchronous Audio Interface)" base ad:0x4002F000 width 11. group.long 0x00++0x07 line.long 0x00 "I2S0_TCSR,SAI Transmit Control Register" bitfld.long 0x00 31. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 30. " STOPE ,Stop enable" "Disabled,Enabled" newline bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " FR ,FIFO reset" "No reset,Reset" bitfld.long 0x00 24. " SR ,Software reset" "No reset,Reset" newline eventfld.long 0x00 20. " WSF ,Word start flag" "Not started,Started" eventfld.long 0x00 19. " SEF ,Sync error flag" "No error,Error" newline eventfld.long 0x00 18. " FEF ,FIFO error flag" "No error,Error" rbitfld.long 0x00 17. " FWF ,FIFO empty warning flag" "Not empty,Empty" newline rbitfld.long 0x00 16. " FRF ,FIFO watermark reach" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" line.long 0x04 "I2S0_TCR1,SAI Transmit Configuration 1 Register" bitfld.long 0x04 0.--2. " TFW ,Transmit FIFO watermark" "0,1,2,3,4,5,6,7" sif cpuis("MK8?FN256V*") if (((per.l(ad:0x4002F000))&0x80000000)==0x80000000) rgroup.long 0x08++0x03 line.long 0x00 "I2S0_TCR2,SAI Transmit Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Receiver,SAI transmitter,SAI receiver" bitfld.long 0x00 29. " BCS ,Bit clock swap" "Normal,Swap" newline bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,External clock" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,I2S0_MCLK1,?..." newline bitfld.long 0x00 25. " BCP ,Bit clock polarity" "Active high,Active low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "External,Internal" newline hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" else group.long 0x08++0x03 line.long 0x00 "I2S0_TCR2,SAI Transmit Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Receiver,SAI transmitter,SAI receiver" bitfld.long 0x00 29. " BCS ,Bit clock swap" "Normal,Swap" newline bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,External clock" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,I2S0_MCLK1,?..." newline bitfld.long 0x00 25. " BCP ,Bit clock polarity" "Active high,Active low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "External,Internal" newline hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" endif else group.long 0x08++0x03 line.long 0x00 "I2S0_TCR2,SAI Transmit Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Receiver,SAI transmitter,SAI receiver" bitfld.long 0x00 29. " BCS ,Bit clock swap" "Normal,Swap" newline bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,External clock" sif cpuis("MK84FN2M0CAU15R") newline bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,I2S0_MCLK,?..." else newline bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,Master clock 1,Master clock 2,Master clock 3" endif newline bitfld.long 0x00 25. " BCP ,Bit clock polarity" "Active high,Active low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "External,Internal" newline hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" endif group.long 0x0C++0x03 line.long 0x00 "I2S0_TCR3,SAI Transmit Configuration 3 Register" sif (cpuis("MK65*")||cpuis("MK66*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")) bitfld.long 0x00 25. " CFR[1] ,Channel 1 FIFO reset" "No effect,Reset" bitfld.long 0x00 24. " CFR[0] ,Channel 0 FIFO reset" "No effect,Reset" newline endif bitfld.long 0x00 17. " TCE1 ,Transmit channel 1 enable" "Disabled,Enabled" bitfld.long 0x00 16. " TCE0 ,Transmit channel 0 enable" "Disabled,Enabled" newline bitfld.long 0x00 0.--4. " WDFL ,Word flag configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" sif cpuis("MK8?FN256V*") if (((per.l(ad:0x4002F000))&0x80000000)==0x80000000) rgroup.long 0x10++0x07 line.long 0x00 "I2S0_TCR4,SAI Transmit Configuration 4 Register" bitfld.long 0x00 28. " FCONT ,FIFO continue on error" "Continue on next frame,Continue on the same word" bitfld.long 0x00 26.--27. " FCOMB ,FIFO combine mode" "Disabled,FIFO reads,FIFO writes,FIFO reads and writes" newline bitfld.long 0x00 24.--25. " FPACK ,FIFO packing mode" "Disabled,,8-bit,16-bit" bitfld.long 0x00 16.--20. " FRSZ ,Frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--12. " SYWD ,Sync width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " MF ,Specify whether the LSB or the MSB is transmitted first" "LSB,MSB" newline bitfld.long 0x00 3. " FSE ,Frame sync assertion" "First bit of frame,Before first bit of frame" bitfld.long 0x00 2. " ONDEM ,On demand mode" "Continuously,When FIFO warning flag cleared" newline bitfld.long 0x00 1. " FSP ,Frame sync polarity" "Active high,Active low" bitfld.long 0x00 0. " FSD ,Frame sync direction" "External,Internal" line.long 0x04 "I2S0_TCR5,SAI Transmit Configuration 5 Register" bitfld.long 0x04 24.--28. " WNW ,Word N width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--20. " W0W ,Word 0 width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 8.--12. " FBT ,First bit shifted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.long 0x10++0x07 line.long 0x00 "I2S0_TCR4,SAI Transmit Configuration 4 Register" bitfld.long 0x00 28. " FCONT ,FIFO continue on error" "Continue on next frame,Continue on the same word" bitfld.long 0x00 26.--27. " FCOMB ,FIFO combine mode" "Disabled,FIFO reads,FIFO writes,FIFO reads and writes" newline bitfld.long 0x00 24.--25. " FPACK ,FIFO packing mode" "Disabled,,8-bit,16-bit" bitfld.long 0x00 16.--20. " FRSZ ,Frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--12. " SYWD ,Sync width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " MF ,Specify whether the LSB or the MSB is transmitted first" "LSB,MSB" newline bitfld.long 0x00 3. " FSE ,Frame sync assertion" "First bit of frame,Before first bit of frame" bitfld.long 0x00 2. " ONDEM ,On demand mode" "Continuously,When FIFO warning flag cleared" newline bitfld.long 0x00 1. " FSP ,Frame sync polarity" "Active high,Active low" bitfld.long 0x00 0. " FSD ,Frame sync direction" "External,Internal" line.long 0x04 "I2S0_TCR5,SAI Transmit Configuration 5 Register" bitfld.long 0x04 24.--28. " WNW ,Word N width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--20. " W0W ,Word 0 width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 8.--12. " FBT ,First bit shifted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif else group.long 0x10++0x07 line.long 0x00 "I2S0_TCR4,SAI Transmit Configuration 4 Register" sif (cpuis("MK65*")||cpuis("MK66*")||cpuis("MK84FN2M0CAU15R"))||cpuis("MK8?FN256V*") bitfld.long 0x00 28. " FCONT ,FIFO continue on error" "Continue on next frame,Continue on the same word" bitfld.long 0x00 26.--27. " FCOMB ,FIFO combine mode" "Disabled,FIFO reads,FIFO writes,FIFO reads and writes" newline bitfld.long 0x00 24.--25. " FPACK ,FIFO packing mode" "Disabled,,8-bit,16-bit" endif newline bitfld.long 0x00 16.--20. " FRSZ ,Frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " SYWD ,Sync width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4. " MF ,Specify whether the LSB or the MSB is transmitted first" "LSB,MSB" bitfld.long 0x00 3. " FSE ,Frame sync assertion" "First bit of frame,Before first bit of frame" newline sif (cpuis("MK65*")||cpuis("MK66*")||cpuis("MK84FN2M0CAU15R"))||cpuis("MK8?FN256V*") bitfld.long 0x00 2. " ONDEM ,On demand mode" "Continuously,When FIFO warning flag cleared" newline endif bitfld.long 0x00 1. " FSP ,Frame sync polarity" "Active high,Active low" bitfld.long 0x00 0. " FSD ,Frame sync direction" "External,Internal" line.long 0x04 "I2S0_TCR5,SAI Transmit Configuration 5 Register" bitfld.long 0x04 24.--28. " WNW ,Word N width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--20. " W0W ,Word 0 width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 8.--12. " FBT ,First bit shifted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif wgroup.long 0x20++0x07 line.long 0x00 "I2S0_TDR0,SAI Transmit Data Register 0" line.long 0x04 "I2S0_TDR1,SAI Transmit Data Register 1" rgroup.long 0x40++0x07 line.long 0x00 "I2S0_TFR0,SAI Transmit FIFO Register 0" sif (cpuis("MK65*")||cpuis("MK66*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")) bitfld.long 0x00 31. " WCP ,Write channel pointer" "No effect,Enabled" newline endif hexmask.long.byte 0x00 16.--19. 0x01 " WFP ,Write FIFO pointer" hexmask.long.byte 0x00 0.--3. 0x01 " RFP ,Read FIFO pointer" line.long 0x04 "I2S0_TFR1,SAI Transmit FIFO Register 1" sif (cpuis("MK65*")||cpuis("MK66*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")) bitfld.long 0x04 31. " WCP ,Write channel pointer" "No effect,Enabled" newline endif hexmask.long.byte 0x04 16.--19. 0x01 " WFP ,Write FIFO pointer" hexmask.long.byte 0x04 0.--3. 0x01 " RFP ,Read FIFO pointer" group.long 0x60++0x03 line.long 0x00 "I2S0_TMR,SAI Transmit Mask Register" bitfld.long 0x00 31. " TWM[31] ,Mask bit[31]" "Not masked,Masked" bitfld.long 0x00 30. " TWM[30] ,Mask bit[30]" "Not masked,Masked" newline bitfld.long 0x00 29. " TWM[29] ,Mask bit[29]" "Not masked,Masked" bitfld.long 0x00 28. " TWM[28] ,Mask bit[28]" "Not masked,Masked" newline bitfld.long 0x00 27. " TWM[27] ,Mask bit[27]" "Not masked,Masked" bitfld.long 0x00 26. " TWM[26] ,Mask bit[26]" "Not masked,Masked" newline bitfld.long 0x00 25. " TWM[25] ,Mask bit[25]" "Not masked,Masked" bitfld.long 0x00 24. " TWM[24] ,Mask bit[24]" "Not masked,Masked" newline bitfld.long 0x00 23. " TWM[23] ,Mask bit[23]" "Not masked,Masked" bitfld.long 0x00 22. " TWM[22] ,Mask bit[22]" "Not masked,Masked" newline bitfld.long 0x00 21. " TWM[21] ,Mask bit[21]" "Not masked,Masked" bitfld.long 0x00 20. " TWM[20] ,Mask bit[20]" "Not masked,Masked" newline bitfld.long 0x00 19. " TWM[19] ,Mask bit[19]" "Not masked,Masked" bitfld.long 0x00 18. " TWM[18] ,Mask bit[18]" "Not masked,Masked" newline bitfld.long 0x00 17. " TWM[17] ,Mask bit[17]" "Not masked,Masked" bitfld.long 0x00 16. " TWM[16] ,Mask bit[16]" "Not masked,Masked" newline bitfld.long 0x00 15. " TWM[15] ,Mask bit[15]" "Not masked,Masked" bitfld.long 0x00 14. " TWM[14] ,Mask bit[14]" "Not masked,Masked" newline bitfld.long 0x00 13. " TWM[13] ,Mask bit[13]" "Not masked,Masked" bitfld.long 0x00 12. " TWM[12] ,Mask bit[12]" "Not masked,Masked" newline bitfld.long 0x00 11. " TWM[11] ,Mask bit[11]" "Not masked,Masked" bitfld.long 0x00 10. " TWM[10] ,Mask bit[10]" "Not masked,Masked" newline bitfld.long 0x00 9. " TWM[9] ,Mask bit[9]" "Not masked,Masked" bitfld.long 0x00 8. " TWM[8] ,Mask bit[8]" "Not masked,Masked" newline bitfld.long 0x00 7. " TWM[7] ,Mask bit[7]" "Not masked,Masked" bitfld.long 0x00 6. " TWM[6] ,Mask bit[6]" "Not masked,Masked" newline bitfld.long 0x00 5. " TWM[5] ,Mask bit[5]" "Not masked,Masked" bitfld.long 0x00 4. " TWM[4] ,Mask bit[4]" "Not masked,Masked" newline bitfld.long 0x00 3. " TWM[3] ,Mask bit[3]" "Not masked,Masked" bitfld.long 0x00 2. " TWM[2] ,Mask bit[2]" "Not masked,Masked" newline bitfld.long 0x00 1. " TWM[1] ,Mask bit[1]" "Not masked,Masked" bitfld.long 0x00 0. " TWM[0] ,Mask bit[0]" "Not masked,Masked" group.long 0x80++0x07 line.long 0x00 "I2S0_RCSR,SAI Receive Control Register" bitfld.long 0x00 31. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 30. " STOPE ,Stop enable" "Disabled,Enabled" newline bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit Clock Enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " FR ,FIFO reset" "No reset,Reset" bitfld.long 0x00 24. " SR ,Software reset" "No reset,Reset" newline eventfld.long 0x00 20. " WSF ,Word start flag" "Not started,Started" eventfld.long 0x00 19. " SEF ,Sync error flag" "No error,Error" newline eventfld.long 0x00 18. " FEF ,FIFO error flag" "No error,Error" rbitfld.long 0x00 17. " FWF ,FIFO warning flag" "Not full,Full" newline rbitfld.long 0x00 16. " FRF ,FIFO watermark reach" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" line.long 0x04 "I2S0_RCR1,SAI Receive Configuration 1 Register" bitfld.long 0x04 0.--2. " RFW ,Receive FIFO watermark" "0,1,2,3,4,5,6,7" sif cpuis("MK8?FN256V*") if (((per.l(ad:0x4002F000+0x80))&0x80000000)==0x80000000) rgroup.long 0x88++0x03 line.long 0x00 "I2S0_RCR2,SAI Receive Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Transmitter,SAI receiver,SAI transmitter" bitfld.long 0x00 29. " BCS ,Bit clock swap" "Normal,Swap" newline bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,External clock" newline bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,I2S0_MCLK,?..." newline bitfld.long 0x00 25. " BCP ,Bit clock polarity" "Active high,Active low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "External,Internal" newline hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" else group.long 0x88++0x03 line.long 0x00 "I2S0_RCR2,SAI Receive Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Transmitter,SAI receiver,SAI transmitter" bitfld.long 0x00 29. " BCS ,Bit clock swap" "Normal,Swap" newline bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,External clock" newline bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,I2S0_MCLK,?..." newline bitfld.long 0x00 25. " BCP ,Bit clock polarity" "Active high,Active low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "External,Internal" newline hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" endif else group.long 0x88++0x03 line.long 0x00 "I2S0_RCR2,SAI Receive Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Transmitter,SAI receiver,SAI transmitter" bitfld.long 0x00 29. " BCS ,Bit clock swap" "Normal,Swap" newline bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,External clock" sif cpuis("MK84FN2M0CAU15R") newline bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,I2S0_MCLK,?..." else newline bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,Master clock 1,Master clock 2,Master clock 3" endif newline bitfld.long 0x00 25. " BCP ,Bit clock polarity" "Active high,Active low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "External,Internal" newline hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" endif group.long 0x8C++0x03 line.long 0x00 "I2S0_RCR3,SAI Receive Configuration 3 Register" sif (cpuis("MK65*")||cpuis("MK66*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")) bitfld.long 0x00 25. " CFR1 ,Channel 1 FIFO reset" "No effect,Reset" bitfld.long 0x00 24. " CFR1 ,Channel 2 FIFO Reset" "No effect,Reset" newline endif bitfld.long 0x00 17. " RCE1 ,Receive channel 1 enable" "Disabled,Enabled" bitfld.long 0x00 16. " RCE0 ,Receive channel 0 enable" "Disabled,Enabled" newline bitfld.long 0x00 0.--4. " WDFL ,Word flag configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" sif cpuis("MK8?FN256V*") if (((per.l(ad:0x4002F000+0x80))&0x80000000)==0x80000000) rgroup.long 0x90++0x07 line.long 0x00 "I2S0_RCR4,SAI Receive Configuration 4 Register" sif (cpuis("MK65*")||cpuis("MK66*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")) bitfld.long 0x00 28. " FCONT ,FIFO continue on error" "Continue on next frame,Continue on the same word" bitfld.long 0x00 26.--27. " FCOMB ,FIFO combine mode" "Disabled,FIFO reads,FIFO writes,FIFO reads and writes" newline bitfld.long 0x00 24.--25. " FPACK ,FIFO packing mode" "Disabled,,8-bit,16-bit" newline endif bitfld.long 0x00 16.--20. " FRSZ ,Frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " SYWD ,Sync width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4. " MF ,Specify whether the LSB or the MSB is received first" "LSB,MSB" bitfld.long 0x00 3. " FSE ,Frame sync assertion" "First bit of frame,Before first bit of frame" newline sif (cpuis("MK65*")||cpuis("MK66*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")) bitfld.long 0x00 2. " ONDEM ,On demand mode" "Continuously,When FIFO warning flag cleared" newline endif bitfld.long 0x00 1. " FSP ,Frame sync polarity" "Active high,Active low" bitfld.long 0x00 0. " FSD ,Frame sync direction" "External,Internal" line.long 0x04 "I2S0_RCR5,SAI Receive Configuration 5 Register" bitfld.long 0x04 24.--28. " WNW ,Word N width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--20. " W0W ,Word 0 width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 8.--12. " FBT ,First bit shifted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.long 0x90++0x07 line.long 0x00 "I2S0_RCR4,SAI Receive Configuration 4 Register" sif (cpuis("MK65*")||cpuis("MK66*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")) bitfld.long 0x00 28. " FCONT ,FIFO continue on error" "Continue on next frame,Continue on the same word" bitfld.long 0x00 26.--27. " FCOMB ,FIFO combine mode" "Disabled,FIFO reads,FIFO writes,FIFO reads and writes" newline bitfld.long 0x00 24.--25. " FPACK ,FIFO packing mode" "Disabled,,8-bit,16-bit" newline endif bitfld.long 0x00 16.--20. " FRSZ ,Frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " SYWD ,Sync width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4. " MF ,Specify whether the LSB or the MSB is received first" "LSB,MSB" bitfld.long 0x00 3. " FSE ,Frame sync assertion" "First bit of frame,Before first bit of frame" newline sif (cpuis("MK65*")||cpuis("MK66*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")) bitfld.long 0x00 2. " ONDEM ,On demand mode" "Continuously,When FIFO warning flag cleared" newline endif bitfld.long 0x00 1. " FSP ,Frame sync polarity" "Active high,Active low" bitfld.long 0x00 0. " FSD ,Frame sync direction" "External,Internal" line.long 0x04 "I2S0_RCR5,SAI Receive Configuration 5 Register" bitfld.long 0x04 24.--28. " WNW ,Word N width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--20. " W0W ,Word 0 width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 8.--12. " FBT ,First bit shifted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif else group.long 0x90++0x07 line.long 0x00 "I2S0_RCR4,SAI Receive Configuration 4 Register" sif (cpuis("MK65*")||cpuis("MK66*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")) bitfld.long 0x00 28. " FCONT ,FIFO continue on error" "Continue on next frame,Continue on the same word" bitfld.long 0x00 26.--27. " FCOMB ,FIFO combine mode" "Disabled,FIFO reads,FIFO writes,FIFO reads and writes" newline bitfld.long 0x00 24.--25. " FPACK ,FIFO packing mode" "Disabled,,8-bit,16-bit" newline endif bitfld.long 0x00 16.--20. " FRSZ ,Frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " SYWD ,Sync width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4. " MF ,Specify whether the LSB or the MSB is received first" "LSB,MSB" bitfld.long 0x00 3. " FSE ,Frame sync assertion" "First bit of frame,Before first bit of frame" newline sif (cpuis("MK65*")||cpuis("MK66*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")) bitfld.long 0x00 2. " ONDEM ,On demand mode" "Continuously,When FIFO warning flag cleared" newline endif bitfld.long 0x00 1. " FSP ,Frame sync polarity" "Active high,Active low" bitfld.long 0x00 0. " FSD ,Frame sync direction" "External,Internal" line.long 0x04 "I2S0_RCR5,SAI Receive Configuration 5 Register" bitfld.long 0x04 24.--28. " WNW ,Word N width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--20. " W0W ,Word 0 width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 8.--12. " FBT ,First bit shifted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif hgroup.long 0xA0++0x03 hide.long 0x00 "I2S0_RDR0,SAI Receive Data 0 Register" in hgroup.long 0xA4++0x03 hide.long 0x00 "I2S0_RDR1,SAI Receive Data 1 Register" in rgroup.long 0xC0++0x07 line.long 0x00 "I2S0_RFR0,SAI Receive FIFO 0 Register" bitfld.long 0x00 16.--19. " WFP ,Write FIFO pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline sif (cpuis("MK65*")||cpuis("MK66*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")) bitfld.long 0x00 15. " RCP ,Receive channel pointer" "No effect,Enabled" newline endif bitfld.long 0x00 0.--3. " RFP ,Read FIFO pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "I2S0_RFR1,SAI Receive FIFO 1 Register" bitfld.long 0x04 16.--19. " WFP ,Write FIFO pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline sif (cpuis("MK65*")||cpuis("MK66*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")) bitfld.long 0x04 15. " RCP ,Receive channel pointer" "No effect,Enabled" newline endif bitfld.long 0x04 0.--3. " RFP ,Read FIFO pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xE0++0x03 line.long 0x00 "I2S0_RMR,SAI Receive Mask Register" bitfld.long 0x00 31. " RWM31 ,Receive mask bit 31" "Not masked,Masked" bitfld.long 0x00 30. " RWM30 ,Receive mask bit 30" "Not masked,Masked" newline bitfld.long 0x00 29. " RWM29 ,Receive mask bit 29" "Not masked,Masked" bitfld.long 0x00 28. " RWM28 ,Receive mask bit 28" "Not masked,Masked" newline bitfld.long 0x00 27. " RWM27 ,Receive mask bit 27" "Not masked,Masked" bitfld.long 0x00 26. " RWM26 ,Receive mask bit 26" "Not masked,Masked" newline bitfld.long 0x00 25. " RWM25 ,Receive mask bit 25" "Not masked,Masked" bitfld.long 0x00 24. " RWM24 ,Receive mask bit 24" "Not masked,Masked" newline bitfld.long 0x00 23. " RWM23 ,Receive mask bit 23" "Not masked,Masked" bitfld.long 0x00 22. " RWM22 ,Receive mask bit 22" "Not masked,Masked" newline bitfld.long 0x00 21. " RWM21 ,Receive mask bit 21" "Not masked,Masked" bitfld.long 0x00 20. " RWM20 ,Receive mask bit 20" "Not masked,Masked" newline bitfld.long 0x00 19. " RWM19 ,Receive mask bit 19" "Not masked,Masked" bitfld.long 0x00 18. " RWM18 ,Receive mask bit 18" "Not masked,Masked" newline bitfld.long 0x00 17. " RWM17 ,Receive mask bit 17" "Not masked,Masked" bitfld.long 0x00 16. " RWM16 ,Receive mask bit 16" "Not masked,Masked" newline bitfld.long 0x00 15. " RWM15 ,Receive mask bit 15" "Not masked,Masked" bitfld.long 0x00 14. " RWM14 ,Receive mask bit 14" "Not masked,Masked" newline bitfld.long 0x00 13. " RWM13 ,Receive mask bit 13" "Not masked,Masked" bitfld.long 0x00 12. " RWM12 ,Receive mask bit 12" "Not masked,Masked" newline bitfld.long 0x00 11. " RWM11 ,Receive mask bit 11" "Not masked,Masked" bitfld.long 0x00 10. " RWM10 ,Receive mask bit 10" "Not masked,Masked" newline bitfld.long 0x00 9. " RWM9 ,Receive mask bit 9" "Not masked,Masked" bitfld.long 0x00 8. " RWM8 ,Receive mask bit 8" "Not masked,Masked" newline bitfld.long 0x00 7. " RWM7 ,Receive mask bit 7" "Not masked,Masked" bitfld.long 0x00 6. " RWM6 ,Receive mask bit 6" "Not masked,Masked" newline bitfld.long 0x00 5. " RWM5 ,Receive mask bit 5" "Not masked,Masked" bitfld.long 0x00 4. " RWM4 ,Receive mask bit 4" "Not masked,Masked" newline bitfld.long 0x00 3. " RWM3 ,Receive mask bit 3" "Not masked,Masked" bitfld.long 0x00 2. " RWM2 ,Receive mask bit 2" "Not masked,Masked" newline bitfld.long 0x00 1. " RWM1 ,Receive mask bit 1" "Not masked,Masked" bitfld.long 0x00 0. " RWM0 ,Receive mask bit 0" "Not masked,Masked" group.long 0x100++0x07 line.long 0x00 "I2S0_MCR,SAI MCLK Control Register" rbitfld.long 0x00 31. " DUF ,Divider update flag" "Not updated,Updated" bitfld.long 0x00 30. " MOE ,MCLK output enable" "Disabled,Enabled" sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*") newline bitfld.long 0x00 24.--25. " MICS ,MCLK input clock select" "System clock,OSC0ERCLK,,MCGPLLCLK/MCGFLLCLK" else newline bitfld.long 0x00 24.--25. " MICS ,MCLK input clock select" "MCLK divider input clock 0,MCLK divider input clock 1,MCLK divider input clock 2,MCLK divider input clock 3" endif line.long 0x04 "I2S0_MDR,SAI MCLK Divide Register" hexmask.long.byte 0x04 12.--19. 1. " FRACT ,MCLK fraction" hexmask.long.word 0x04 0.--11. 1. " DIVIDE ,MCLK divide" width 0x0B tree.end tree "SDHC (Secured Digital Host Controller)" base ad:0x400B1000 width 12. group.long 0x00++0x0F line.long 0x00 "DSADDR,DMA System Address Register" sif !cpuis("K32W0?2S1M*") hexmask.long 0x00 2.--31. 0x04 " DSADDR ,DMA system address" endif line.long 0x04 "BLKATTR,Block Attributes Register" hexmask.long.word 0x04 16.--31. 1. " BLKCNT ,Blocks count for current transfer" hexmask.long.word 0x04 0.--12. 1. " BLKSIZE ,Transfer block size" line.long 0x08 "CMDARG,Command Argument Register" line.long 0x0C "XFERTYP,Transfer Type Register" bitfld.long 0x0C 24.--29. " CMDINX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 22.--23. " CMDTYP ,Command type" "Normal,Suspend,Resume,Abort" bitfld.long 0x0C 21. " DPSEL ,Data present select" "Not present,Present" newline bitfld.long 0x0C 20. " CICEN ,Command index check enable" "Disabled,Enabled" bitfld.long 0x0C 19. " CCCEN ,Command crc check enable" "Disabled,Enabled" bitfld.long 0x0C 16.--17. " RSPTYP ,Response type select" "No response,Response length 136,Response length 48,Response length 48/check busy" sif !cpuis("K32W0?2S1M*") newline bitfld.long 0x0C 5. " MSBSEL ,Multi/Single block select" "Single,Multi" bitfld.long 0x0C 4. " DTDSEL ,Data transfer direction select" "Write,Read" bitfld.long 0x0C 2. " AC12EN ,Auto CMD12 enable" "Disabled,Enabled" newline bitfld.long 0x0C 1. " BCEN ,Block count enable" "Disabled,Enabled" bitfld.long 0x0C 0. " DMAEN ,DMA enable" "Disabled,Enabled" endif rgroup.long 0x10++0x03 line.long 0x00 "CMDRSP0,Command Response 0" rgroup.long 0x14++0x03 line.long 0x00 "CMDRSP1,Command Response 1" rgroup.long 0x18++0x03 line.long 0x00 "CMDRSP2,Command Response 2" rgroup.long 0x1C++0x03 line.long 0x00 "CMDRSP3,Command Response 3" group.long 0x20++0x03 line.long 0x00 "DATPORT,Buffer Data Port Register" rgroup.long 0x24++0x03 line.long 0x00 "PRSSTAT,Present State Register" bitfld.long 0x00 31. " DLSL[7] ,Data 7 line signal level" "Low,High" bitfld.long 0x00 30. " [6] ,Data 6 line signal level" "Low,High" bitfld.long 0x00 29. " [5] ,Data 5 line signal level" "Low,High" newline bitfld.long 0x00 28. " [4] ,Data 4 line signal level" "Low,High" bitfld.long 0x00 27. " [3] ,Data 3 line signal level" "Low,High" bitfld.long 0x00 26. " [2] ,Data 2 line signal level" "Low,High" newline bitfld.long 0x00 25. " [1] ,Data 1 line signal level" "Low,High" bitfld.long 0x00 24. " [0] ,Data 0 line signal level" "Low,High" bitfld.long 0x00 23. " CLSL ,CMD line signal level" "Low,High" newline sif cpuis("K32W0?2S1M*") bitfld.long 0x00 19. " WPSPL ,Write protect switch pin level" "Disabled,Enabled" bitfld.long 0x00 18. " CDPL ,Card detect pin level" "Not detected,Detected" newline endif bitfld.long 0x00 16. " CINS ,Card inserted" "Not inserted,Inserted" bitfld.long 0x00 11. " BREN ,Buffer read enable" "Disabled,Enabled" bitfld.long 0x00 10. " BWEN ,Buffer write enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " RTA ,Read transfer active" "Not active,Active" bitfld.long 0x00 8. " WTA ,Write transfer active" "Not active,Active" bitfld.long 0x00 7. " SDOFF ,SD clock gated off internally" "Active,Gated off" newline bitfld.long 0x00 6. " PEROFF ,Ipg_perclk gated off internally" "Active,Gated off" bitfld.long 0x00 5. " HCKOFF ,Hclk gated off internally" "Active,Gated off" bitfld.long 0x00 4. " IPGOFF ,Lpg_clk gated off internally" "Active,Gated off" newline bitfld.long 0x00 3. " SDSTB ,SD clock stable" "Not stable,Stable" bitfld.long 0x00 2. " DLA ,Data line active" "Not active,Active" bitfld.long 0x00 1. " CDIHB ,Command inhibit (DAT)" "Not generated,Generated" newline bitfld.long 0x00 0. " CIHB ,Command inhibit (CMD)" "Not generated,Generated" group.long 0x28++0x13 line.long 0x00 "PROCTL,Protocol Control Register" sif cpuis("K32W0?2S1M*") bitfld.long 0x00 29. " BURST_LEN_EN ,BURST length enable for INCR" "Disabled,Enabled" bitfld.long 0x00 28. " BURST_LEN_EN ,BURST length enable for INCR4 / INCR8 / INCR16" "Disabled,Enable" bitfld.long 0x00 27. " BURST_LEN_EN ,BURST length enable for INCR4-WRAP / INCR8-WRAP / INCR16-WRAP" "Disabled,Enabled" endif bitfld.long 0x00 26. " WECRM ,Wakeup event enable on SD card removal" "Disabled,Enabled" bitfld.long 0x00 25. " WECINS ,Wakeup event enable on SD card insertion" "Disabled,Enabled" bitfld.long 0x00 24. " WECINT ,Wakeup event enable on card interrupt" "Disabled,Enabled" newline bitfld.long 0x00 19. " IABG ,Interrupt at block gap" "Disabled,Enabled" bitfld.long 0x00 18. " RWCTL ,Read wait control" "Disabled,Enabled" bitfld.long 0x00 17. " CREQ ,Continue request" "No effect,Restart" newline bitfld.long 0x00 16. " SABGREQ ,Stop at block gap request" "Transfer,Stopped" bitfld.long 0x00 8.--9. " DMAS ,DMA select" "No DMA/Simple DMA,ADMA1,ADMA2,?..." bitfld.long 0x00 7. " CDSS ,Card detect signal selection" "Level,Test" newline bitfld.long 0x00 6. " CDTL ,Card detect test level" "Low,High" bitfld.long 0x00 4.--5. " EMODE ,Endian mode" "Big endian,Half word big endian,Little endian,?..." bitfld.long 0x00 3. " D3CD ,DAT3 as card detection pin" "Not act,Act" newline bitfld.long 0x00 1.--2. " DTW ,Data transfer width" "1-bit,4-bit,8-bit,?..." bitfld.long 0x00 0. " LCTL ,LED control" "Off,On" line.long 0x04 "SYSCTL,System Control Register" bitfld.long 0x04 27. " INITA ,Initialization active" "Not active,Active" bitfld.long 0x04 26. " RSTD ,Software reset for data line" "No reset,Reset" bitfld.long 0x04 25. " RSTC ,Software reset for cmd line" "No reset,Reset" newline bitfld.long 0x04 24. " RSTA ,Software reset for all" "No reset,Reset" bitfld.long 0x04 16.--19. " DTOCV ,Data timeout counter value" "SDCLK x (2^13),SDCLK x (2^14),SDCLK x (2^15),SDCLK x (2^16),SDCLK x (2^17),SDCLK x (2^18),SDCLK x (2^19),SDCLK x (2^20),SDCLK x (2^21),SDCLK x (2^22),SDCLK x (2^23),SDCLK x (2^24),SDCLK x (2^25),SDCLK x (2^26),SDCLK x (2^27),?..." hexmask.long.byte 0x04 8.--15. 1. " SDCLKFS ,SDCLK frequency select" newline bitfld.long 0x04 4.--7. " DVS ,Divisor" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" sif !cpuis("K32W0?2S1M*") newline bitfld.long 0x04 3. " SDCLKEN ,SD clock enable" "Disabled,Enabled" bitfld.long 0x04 2. " PEREN ,Peripheral clock enable" "Disabled,Enabled" bitfld.long 0x04 1. " HCKEN ,System clock enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " IPGEN ,IPG clock enable" "Disabled,Enabled" endif line.long 0x08 "IRQSTAT,Interrupt Status Register" eventfld.long 0x08 28. " DMAE ,DMA error" "No error,Error" eventfld.long 0x08 24. " AC12E ,Auto CMD12 error" "No error,Error" eventfld.long 0x08 22. " DEBE ,Data end bit error" "No error,Error" newline eventfld.long 0x08 21. " DCE ,Data CRC error" "No error,Error" eventfld.long 0x08 20. " DTOE ,Data timeout error" "No error,Error" eventfld.long 0x08 19. " CIE ,Command index error" "No error,Error" newline eventfld.long 0x08 18. " CEBE ,Command end bit error" "No error,Error" eventfld.long 0x08 17. " CCE ,Command CRC error" "No error,Error" eventfld.long 0x08 16. " CTOE ,Command timeout error" "No error,Error" newline eventfld.long 0x08 8. " CINT ,Card interrupt" "No interrupt,Interrupt" eventfld.long 0x08 7. " CRM ,Card removal" "Not removed,Removed" eventfld.long 0x08 6. " CINS ,Card insertion" "Not inserted,Inserted" newline eventfld.long 0x08 5. " BRR ,Buffer read ready" "Not ready,Ready" eventfld.long 0x08 4. " BWR ,Buffer write ready" "Not ready,Ready" eventfld.long 0x08 3. " DINT ,DMA interrupt" "No interrupt,Interrupt" newline eventfld.long 0x08 2. " BGE ,Block gap event" "Not stopped,Stopped" eventfld.long 0x08 1. " TC ,Transfer complete" "Not completed,Completed" eventfld.long 0x08 0. " CC ,Command complete" "Not completed,Completed" line.long 0x0C "IRQSTATEN,Interrupt Status Enable Register" bitfld.long 0x0C 28. " DMAESEN ,DMA error status enable" "Disabled,Enabled" bitfld.long 0x0C 24. " AC12ESEN ,Auto CMD12 error status enable" "Disabled,Enabled" bitfld.long 0x0C 22. " DEBESEN ,Data end bit error status enable" "Disabled,Enabled" newline bitfld.long 0x0C 21. " DCESEN ,Data CRC error status enable" "Disabled,Enabled" bitfld.long 0x0C 20. " DTOESEN ,Data timeout error status enable" "Disabled,Enabled" bitfld.long 0x0C 19. " CIESEN ,Command index error status enable" "Disabled,Enabled" newline bitfld.long 0x0C 18. " CEBESEN ,Command end bit error status enable" "Disabled,Enabled" bitfld.long 0x0C 17. " CCESEN ,Command CRC error status enable" "Disabled,Enabled" bitfld.long 0x0C 16. " CTOESEN ,Command timeout error status enable" "Disabled,Enabled" newline bitfld.long 0x0C 8. " CINTSEN ,Card interrupt status enable" "Disabled,Enabled" bitfld.long 0x0C 7. " CRMSEN ,Card removal status enable" "Disabled,Enabled" bitfld.long 0x0C 6. " CINSEN ,Card insertion status enable" "Disabled,Enabled" newline bitfld.long 0x0C 5. " BRRSEN ,Buffer read ready status enable" "Disabled,Enabled" bitfld.long 0x0C 4. " BWRSEN ,Buffer write ready status enable" "Disabled,Enabled" bitfld.long 0x0C 3. " DINTSEN ,DMA interrupt status enable" "Disabled,Enabled" newline bitfld.long 0x0C 2. " BGESEN ,Block gap event status enable" "Disabled,Enabled" bitfld.long 0x0C 1. " TCSEN ,Transfer complete status enable" "Disabled,Enabled" bitfld.long 0x0C 0. " CCSEN ,Command complete status enable" "Disabled,Enabled" line.long 0x10 "IRQSIGEN,Interrupt Signal Enable Register" bitfld.long 0x10 28. " DMAEIEN ,DMA error interrupt enable" "Disabled,Enabled" bitfld.long 0x10 24. " AC12EIEN ,Auto CMD12 error interrupt enable" "Disabled,Enabled" bitfld.long 0x10 22. " DEBEIEN ,Data end bit error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x10 21. " DCEIEN ,Data CRC error interrupt enable" "Disabled,Enabled" bitfld.long 0x10 20. " DTOEIEN ,Data timeout error interrupt enable" "Disabled,Enabled" bitfld.long 0x10 19. " CIEIEN ,Command index error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x10 18. " CEBEIEN ,Command end bit error interrupt enable" "Disabled,Enabled" bitfld.long 0x10 17. " CCEIEN ,Command CRC error interrupt enable" "Disabled,Enabled" bitfld.long 0x10 16. " CTOEIEN ,Command timeout error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x10 8. " CINTIEN ,Card interrupt enable" "Disabled,Enabled" bitfld.long 0x10 7. " CRMIEN ,Card removal interrupt enable" "Disabled,Enabled" bitfld.long 0x10 6. " CINSIEN ,Card insertion interrupt enable" "Disabled,Enabled" newline bitfld.long 0x10 5. " BRRIEN ,Buffer read ready interrupt enable" "Disabled,Enabled" bitfld.long 0x10 4. " BWRIEN ,Buffer write ready interrupt enable" "Disabled,Enabled" bitfld.long 0x10 3. " DINTIEN ,DMA interrupt enable" "Disabled,Enabled" newline bitfld.long 0x10 2. " BGEIEN ,Block gap event interrupt enable" "Disabled,Enabled" bitfld.long 0x10 1. " TCIEN ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x10 0. " CCIEN ,Command complete interrupt enable" "Disabled,Enabled" if ((per.l(ad:0x400B1000+0x30)&0x1000000)==0x00) hgroup.long 0x3C++0x03 hide.long 0x00 "AC12ERR,Auto CMD12 Error Status Register" else rgroup.long 0x3C++0x03 line.long 0x00 "AC12ERR,Auto CMD12 Error Status Register" bitfld.long 0x00 7. " CNIBAC12E ,Command not issued by auto CMD12 error" "No error,Not issued" bitfld.long 0x00 4. " AC12IE ,Auto CMD12 index error" "No error,Error" bitfld.long 0x00 3. " AC12CE ,Auto CMD12 CRC error" "No error,Error" newline bitfld.long 0x00 2. " AC12EBE ,Auto CMD12 end bit error" "No error,Error" bitfld.long 0x00 1. " AC12TOE ,Auto CMD12 timeout error" "No error,Error" bitfld.long 0x00 0. " AC12NE ,Auto CMD12 not executed" "Executed,Not executed" endif rgroup.long 0x40++0x03 line.long 0x00 "HTCAPBLT,Host Controller Capabilities" sif cpuis("MK?0F*")||cpuis("MK?0D*10")||cpuis("MK20DN512*AB10R")||cpuis("MK5*10")||cpuis("MK6*")||cpuis("MK7*")||cpuis("MK20DX256VLQ10R")||cpuis("MK20DX256VLK10R")||cpuis("K32W0?2S1M*")||cpuis("MK10DN512ZVLL10")||cpuis("MK10DN512ZVLL10R")||cpuis("MK10DN512ZVMC10")||cpuis("MK10DN512ZVLQ10")||cpuis("MK10DN512ZVMD10")||cpuis("MK10DX256ZVLQ10")||cpuis("MK10DX256ZVLQ10R")||cpuis("MK10DX256ZVMD10")||cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*")||cpuis("MK30DX256VLL7*")||cpuis("MK40DN512ZVLL10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10")||cpuis("MK20DX256ZVLQ10R")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R") sif !cpuis("MK8?FN256V*")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 26. " VS18 ,Voltage support 1.8 V" "Not supported,Supported" bitfld.long 0x00 25. " VS30 ,Voltage support 3.0 V" "Not supported,Supported" newline endif endif bitfld.long 0x00 24. " VS33 ,Voltage support 3.3 V" "Not supported,Supported" bitfld.long 0x00 23. " SRS ,Suspend/Resume support" "Not supported,Supported" bitfld.long 0x00 22. " DMAS ,DMA support" "Not supported,Supported" newline bitfld.long 0x00 21. " HSS ,High speed support" "Not supported,Supported" bitfld.long 0x00 20. " ADMAS ,ADMA support" "Not supported,Supported" bitfld.long 0x00 16.--18. " MBL ,Max block length" "512 bytes,1024 bytes,2048 bytes,4096 bytes,?..." group.long 0x44++0x03 line.long 0x00 "WML,Watermark Level Register" sif cpuis("MK63FN1M0VLQ12R")||cpuis("K32W0?2S1M*") bitfld.long 0x00 24.--28. " WRBRSTLEN ,Write Burst Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." endif newline hexmask.long.byte 0x00 16.--23. 1. " WRWML ,Write watermark level" sif cpuis("MK63FN1M0VLQ12R")||cpuis("K32W0?2S1M*") bitfld.long 0x00 8.--12. " RDBRSTLEN ,Read burst length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." endif newline hexmask.long.byte 0x00 0.--7. 1. " RDWML ,Read watermark level" sif cpuis("K32W0?2S1M*") group.long 0x48++0x03 line.long 0x00 "MIX_CTRL,Mixer Control Register" bitfld.long 0x00 7. " AC23EN ,Auto CMD23 enable" "Disabled,Enabled" bitfld.long 0x00 6. " NIBBLE_POS ,Nibble position indication" "Low,High" bitfld.long 0x00 5. " MSBSEL ,Multi/Single block select" "Single,Multi" newline bitfld.long 0x00 4. " DTDSEL ,Data transfer direction select" "Write,Read" bitfld.long 0x00 3. " DDR_EN ,Dual data rate mode selection enable" "Disabled,Enabled" bitfld.long 0x00 2. " AC12EN ,Auto CMD12 enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " BCEN ,Block count enable" "Disabled,Enabled" bitfld.long 0x00 0. " DMAEN ,DMA enable" "Disabled,Enabled" endif wgroup.long 0x50++0x03 line.long 0x00 "FEVT,Force Event Register" bitfld.long 0x00 31. " CINT ,Force event card interrupt" "No effect,Force" bitfld.long 0x00 28. " DMAE ,Force event DMA error" "No effect,Force" bitfld.long 0x00 24. " AC12E ,Force event auto command 12 error" "No effect,Force" newline bitfld.long 0x00 22. " DEBE ,Force event data end bit error" "No effect,Force" bitfld.long 0x00 21. " DCE ,Force event data crc error" "No effect,Force" bitfld.long 0x00 20. " DTOE ,Force event data time out error" "No effect,Force" newline bitfld.long 0x00 19. " CIE ,Force event command index error" "No effect,Force" bitfld.long 0x00 18. " CEBE ,Force event command end bit error" "No effect,Force" bitfld.long 0x00 17. " CCE ,Force event command crc error" "No effect,Force" newline bitfld.long 0x00 16. " CTOE ,Force event command time out error" "No effect,Force" bitfld.long 0x00 7. " CNIBAC12E ,Force event command not executed by auto command 12 error" "No effect,Force" bitfld.long 0x00 4. " AC12IE ,Force event auto command 12 index error" "No effect,Force" newline bitfld.long 0x00 3. " AC12EBE ,Force event auto command 12 end bit error" "No effect,Force" bitfld.long 0x00 2. " AC12CE ,Force event auto command 12 crc error" "No effect,Force" bitfld.long 0x00 1. " AC12TOE ,Force event auto command 12 time out error" "No effect,Force" newline bitfld.long 0x00 0. " AC12NE ,Force event auto command 12 not executed" "No effect,Force" rgroup.long 0x54++0x03 line.long 0x00 "ADMAES,ADMA Error Status Register" bitfld.long 0x00 3. " ADMADCE ,ADMA descriptor error" "No error,Error" bitfld.long 0x00 2. " ADMALME ,ADMA length mismatch error" "No error,Error" bitfld.long 0x00 0.--1. " ADMAES ,ADMA error state" "ST_STOP,ST_FDS,ST_CADR,ST_TFR" group.long 0x58++0x03 line.long 0x00 "ADSADDR,ADMA System Address Register" hexmask.long 0x00 2.--31. 0x04 " ADSADDR ,ADMA system address" group.long 0xC0++0x07 line.long 0x00 "VENDOR,Vendor Specific Register" sif cpuis("K32W0?2S1M*") bitfld.long 0x00 31. " CMD_BYTE_EN ,Byte access enable" "Disabled,Enabled" bitfld.long 0x00 15. " CRC_CHK_DIS ,CRC check disable" "Enabled,Disabled" bitfld.long 0x00 8. " FRC_SDCLK_ON ,Force CLK output active" "Not forced,Forced" newline bitfld.long 0x00 3. " AC12_WR_CHKBUSY_EN ,Check busy enable after auto CMD12 for write data packet" "Not checked,Checked" bitfld.long 0x00 2. " CONFLICT_CHK_EN ,Conflict check enable" "Disabled,Enabled" bitfld.long 0x00 1. " VSELECT ,Voltage selection" "3.0V,1.8V" newline else hexmask.long.byte 0x00 16.--23. 1. " INTSTVAL ,Internal state value" bitfld.long 0x00 1. " EXBLKNU ,Exact block number block read enable" "Disabled,Enabled" sif !cpuis("MK65*")&&!cpuis("MK66*")&&!cpuis("MK26FN*")&&!cpuis("MK84FN2M0CAU15R")&&!cpuis("MK8?FN256V*")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("KK26FN2M0CAC18R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("MK66FN2M0VLQ18R")&&!cpuis("KK65FN2M0CAC18R") newline bitfld.long 0x00 0. " EXTDMAEN ,External DMA request enable" "Disabled,Enabled" endif endif line.long 0x04 "MMCBOOT,MMC Boot Register" hexmask.long.word 0x04 16.--31. 1. " BOOTBLKCNT ,Boot block counter" newline sif cpuis("K32W0?2S1M*") bitfld.long 0x04 8. " DISABLE_TIME_OUT ,Disable time out" "Enabled,Disabled" newline endif bitfld.long 0x04 7. " AUTOSABGEN ,Auto stop at boost gap enable" "Disabled,Enabled" bitfld.long 0x04 6. " BOOTEN ,Fast boot mode enable" "Disabled,Enabled" bitfld.long 0x04 5. " BOOTMODE ,Boot ACK mode select" "Normal,Alternative" newline bitfld.long 0x04 4. " BOOTACK ,Boot ACK mode select" "No ACK,ACK" newline sif cpuis("K32W0?2S1M*") bitfld.long 0x04 0.--3. " DTOCVACK ,Boot ACK time out counter value" "2^14,2^15,2^16,2^17,2^18,2^19,2^20,2^21,,,,,,,2^28,2^29" else bitfld.long 0x04 0.--3. " DTOCVACK ,Boot ACK time out counter value" "2^8,2^9,2^10,2^11,2^12,2^13,2^14,2^15,2^16,2^17,2^18,2^19,2^20,2^21,2^22,?..." endif sif cpuis("K32W0?2S1M*") group.long 0xC8++0x03 line.long 0x00 "VEND_SPEC2,Vendor Specific 2 Register" bitfld.long 0x00 14. " AHB_RST ,AHB BUS reset" "No reset,Reset" bitfld.long 0x00 12. " ACMD23_ARGU2_EN ,Argument2 register enable for ACMD23" "Disabled,Enabled" bitfld.long 0x00 3. " CARD_INT_D3_TEST ,Card interrupt detection test" "Check when DATA3 is high,Ignore DATA3 status" else rgroup.long 0xFC++0x03 line.long 0x00 "HOSTVER,Host Controller Version" hexmask.long.byte 0x00 8.--15. 1. " VVN ,Vendor version number" hexmask.long.byte 0x00 0.--7. 1. " SVN ,Specification version number" endif width 0x0B tree.end tree "TSI (Touch Sensing Input)" base ad:0x40045000 width 11. group.long 0x00++0x0B line.long 0x00 "GENCS,TSI General Control and Status Register" eventfld.long 0x00 31. " OUTRGF ,Out of range flag" "Not occurred,Occurred" bitfld.long 0x00 28. " ESOR ,End-of-scan or out-of-range interrupt selection" "Out-of-range,End-of-scan" bitfld.long 0x00 24.--27. " MODE ,TSI analog modes setup and status bits" "Capacitive sensing mode,,,,Single threshold noise detection mode/frequency limitation disabled,,,,Single threshold noise detection mode/frequency limitation enabled,,,,Automatic noise detection mode,?..." newline bitfld.long 0x00 21.--23. " REFCHRG ,Indicates the reference oscillator charge and discharge current value" "500 nA,1 uA,2 uA,4 uA,8 uA,16 uA,32 uA,64 uA" bitfld.long 0x00 19.--20. " DVOLT ,Indicates the oscillator's voltage rails as below" "DV = 1.026 V / Vp = 1.328 V / Vm = 0.302 V,DV = 0.592 V / Vp = 1.111 V / Vm = 0.519 V,DV = 0.342 V / Vp = 0.986 V / Vm = 0.644 V,DV = 0.197 V / Vp = 0.914 V / Vm = 0.716 V" bitfld.long 0x00 16.--18. " EXTCHRG ,Indicates the electrode oscillator charge and discharge current value" "500 nA,1 uA,2 uA,4 uA,8 uA,16 uA,32 uA,64 uA" newline bitfld.long 0x00 13.--15. " PS ,Indicates the prescaler of the output of electrode oscillator" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.long 0x00 8.--12. " NSCN ,Indicates the scan number for each electrode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 7. " TSIEN ,Touch sensing input module enable" "Disabled,Enabled" newline bitfld.long 0x00 6. " TSIIEN ,Touch sensing input interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " STPE ,TSI STOP enable" "Disabled,Enabled" bitfld.long 0x00 4. " STM ,Scan trigger mode" "Software,Hardware" newline rbitfld.long 0x00 3. " SCNIP ,Scan in progress status" "No scan,Scan" eventfld.long 0x00 2. " EOSF ,End of scan flag" "Not completed,Completed" newline bitfld.long 0x00 1. " CURSW ,Specifies if the current sources of electrode oscillator and reference oscillator are swapped" "Not swapped,Swapped" bitfld.long 0x00 0. " EOSDMEO ,End-of-scan DMA transfer request enable only" "Disabled,Enabled" line.long 0x04 "DATA,TSI DATA Register" bitfld.long 0x04 28.--31. " TSICH ,These bits specify current channel to be measured" "Ch. 0,Ch. 1,Ch. 2,Ch. 3,Ch. 4,Ch. 5,Ch. 6,Ch. 7,Ch. 8,Ch. 9,Ch. 10,Ch. 11,Ch. 12,Ch. 13,Ch. 14,Ch. 15" bitfld.long 0x04 23. " DMAEN ,DMA transfer enabled" "Disabled,Enabled" newline bitfld.long 0x04 22. " SWTS ,Software trigger start" "No effect,Scan" hexmask.long.word 0x04 0.--15. 1. " TSICNT ,TSI conversion counter value" line.long 0x08 "TSHD,TSI Threshold Register" hexmask.long.word 0x08 16.--31. 1. " THRESH ,TSI wakeup channel high-threshold" hexmask.long.word 0x08 0.--15. 1. " THRESL ,TSI wakeup channel low-threshold" width 0x0B tree.end tree.open "GPIO (General-Purpose Input/Output)" tree "GPIO_A" base ad:0x400FF000 width 20. group.long 0x00++0x03 line.long 0x00 "GPIOA_PDOR_SET/CLR,Port Data Output Register" setclrfld.long 0x00 29. 0x04 29. 0x08 29. " PDO[29] ,Port Data Output" "Low level,High level" sif !cpuis("MK8?FN256V*") setclrfld.long 0x00 28. 0x04 28. 0x08 28. " PDO[28] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 27. 0x04 27. 0x08 27. " PDO[27] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 26. 0x04 26. 0x08 26. " PDO[26] ,Port Data Output" "Low level,High level" newline setclrfld.long 0x00 25. 0x04 25. 0x08 25. " PDO[25] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 24. 0x04 24. 0x08 24. " PDO[24] ,Port Data Output" "Low level,High level" endif setclrfld.long 0x00 21. 0x04 21. 0x08 21. " PDO[21] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20] ,Port Data Output" "Low level,High level" newline setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16] ,Port Data Output" "Low level,High level" newline setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PDO[15] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PDO[14] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PDO[13] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PDO[12] ,Port Data Output" "Low level,High level" newline setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO[10] ,Port Data Output" "Low level,High level" sif !cpuis("MK8?FN256V*") setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO[9] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8] ,Port Data Output" "Low level,High level" newline setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6] ,Port Data Output" "Low level,High level" endif setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4] ,Port Data Output" "Low level,High level" newline setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0] ,Port Data Output" "Low level,High level" wgroup.long 0x0C++0x03 line.long 0x00 "GPIOA_PTOR,Port Toggle Output Register" bitfld.long 0x00 29. " PTTO[29] ,Port Toggle Output" "No effect,Toggle" sif !cpuis("MK8?FN256V*") bitfld.long 0x00 28. " PTTO[28] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 27. " PTTO[27] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 26. " PTTO[26] ,Port Toggle Output" "No effect,Toggle" newline bitfld.long 0x00 25. " PTTO[25] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 24. " PTTO[24] ,Port Toggle Output" "No effect,Toggle" endif bitfld.long 0x00 21. " PTTO[21] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 20. " PTTO[20] ,Port Toggle Output" "No effect,Toggle" newline bitfld.long 0x00 19. " PTTO[19] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 18. " PTTO[18] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 17. " PTTO[17] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 16. " PTTO[16] ,Port Toggle Output" "No effect,Toggle" newline bitfld.long 0x00 15. " PTTO[15] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 14. " PTTO[14] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 13. " PTTO[13] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 12. " PTTO[12] ,Port Toggle Output" "No effect,Toggle" newline bitfld.long 0x00 11. " PTTO[11] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 10. " PTTO[10] ,Port Toggle Output" "No effect,Toggle" sif !cpuis("MK8?FN256V*") bitfld.long 0x00 9. " PTTO[9] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 8. " PTTO[8] ,Port Toggle Output" "No effect,Toggle" newline bitfld.long 0x00 7. " PTTO[7] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 6. " PTTO[6] ,Port Toggle Output" "No effect,Toggle" endif bitfld.long 0x00 5. " PTTO[5] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 4. " PTTO[4] ,Port Toggle Output" "No effect,Toggle" newline bitfld.long 0x00 3. " PTTO[3] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 2. " PTTO[2] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 1. " PTTO[1] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 0. " PTTO[0] ,Port Toggle Output" "No effect,Toggle" rgroup.long 0x10++0x03 line.long 0x00 "GPIOA_PDIR,Port Data Input Register" bitfld.long 0x00 29. " PDI[29] ,Port Data Input" "Low level,High level" sif !cpuis("MK8?FN256V*") bitfld.long 0x00 28. " PDI[28] ,Port Data Input" "Low level,High level" bitfld.long 0x00 27. " PDI[27] ,Port Data Input" "Low level,High level" bitfld.long 0x00 26. " PDI[26] ,Port Data Input" "Low level,High level" newline bitfld.long 0x00 25. " PDI[25] ,Port Data Input" "Low level,High level" bitfld.long 0x00 24. " PDI[24] ,Port Data Input" "Low level,High level" endif bitfld.long 0x00 21. " PDI[21] ,Port Data Input" "Low level,High level" bitfld.long 0x00 20. " PDI[20] ,Port Data Input" "Low level,High level" newline bitfld.long 0x00 19. " PDI[19] ,Port Data Input" "Low level,High level" bitfld.long 0x00 18. " PDI[18] ,Port Data Input" "Low level,High level" bitfld.long 0x00 17. " PDI[17] ,Port Data Input" "Low level,High level" bitfld.long 0x00 16. " PDI[16] ,Port Data Input" "Low level,High level" newline bitfld.long 0x00 15. " PDI[15] ,Port Data Input" "Low level,High level" bitfld.long 0x00 14. " PDI[14] ,Port Data Input" "Low level,High level" bitfld.long 0x00 13. " PDI[13] ,Port Data Input" "Low level,High level" bitfld.long 0x00 12. " PDI[12] ,Port Data Input" "Low level,High level" newline bitfld.long 0x00 11. " PDI[11] ,Port Data Input" "Low level,High level" bitfld.long 0x00 10. " PDI[10] ,Port Data Input" "Low level,High level" sif !cpuis("MK8?FN256V*") bitfld.long 0x00 9. " PDI[9] ,Port Data Input" "Low level,High level" bitfld.long 0x00 8. " PDI[8] ,Port Data Input" "Low level,High level" newline bitfld.long 0x00 7. " PDI[7] ,Port Data Input" "Low level,High level" bitfld.long 0x00 6. " PDI[6] ,Port Data Input" "Low level,High level" endif bitfld.long 0x00 5. " PDI[5] ,Port Data Input" "Low level,High level" bitfld.long 0x00 4. " PDI[4] ,Port Data Input" "Low level,High level" newline bitfld.long 0x00 3. " PDI[3] ,Port Data Input" "Low level,High level" bitfld.long 0x00 2. " PDI[2] ,Port Data Input" "Low level,High level" bitfld.long 0x00 1. " PDI[1] ,Port Data Input" "Low level,High level" bitfld.long 0x00 0. " PDI[0] ,Port Data Input" "Low level,High level" group.long 0x14++0x03 line.long 0x00 "GPIOA_PDDR,Port Data Direction Register" bitfld.long 0x00 29. " PDD[29] ,Port Data Direction" "Input,Output" sif !cpuis("MK8?FN256V*") bitfld.long 0x00 28. " PDD[28] ,Port Data Direction" "Input,Output" bitfld.long 0x00 27. " PDD[27] ,Port Data Direction" "Input,Output" bitfld.long 0x00 26. " PDD[26] ,Port Data Direction" "Input,Output" newline bitfld.long 0x00 25. " PDD[25] ,Port Data Direction" "Input,Output" bitfld.long 0x00 24. " PDD[24] ,Port Data Direction" "Input,Output" endif bitfld.long 0x00 21. " PDD[21] ,Port Data Direction" "Input,Output" bitfld.long 0x00 20. " PDD[20] ,Port Data Direction" "Input,Output" newline bitfld.long 0x00 19. " PDD[19] ,Port Data Direction" "Input,Output" bitfld.long 0x00 18. " PDD[18] ,Port Data Direction" "Input,Output" bitfld.long 0x00 17. " PDD[17] ,Port Data Direction" "Input,Output" bitfld.long 0x00 16. " PDD[16] ,Port Data Direction" "Input,Output" newline bitfld.long 0x00 15. " PDD[15] ,Port Data Direction" "Input,Output" bitfld.long 0x00 14. " PDD[14] ,Port Data Direction" "Input,Output" bitfld.long 0x00 13. " PDD[13] ,Port Data Direction" "Input,Output" bitfld.long 0x00 12. " PDD[12] ,Port Data Direction" "Input,Output" newline bitfld.long 0x00 11. " PDD[11] ,Port Data Direction" "Input,Output" bitfld.long 0x00 10. " PDD[10] ,Port Data Direction" "Input,Output" sif !cpuis("MK8?FN256V*") bitfld.long 0x00 9. " PDD[9] ,Port Data Direction" "Input,Output" bitfld.long 0x00 8. " PDD[8] ,Port Data Direction" "Input,Output" newline bitfld.long 0x00 7. " PDD[7] ,Port Data Direction" "Input,Output" bitfld.long 0x00 6. " PDD[6] ,Port Data Direction" "Input,Output" endif bitfld.long 0x00 5. " PDD[5] ,Port Data Direction" "Input,Output" bitfld.long 0x00 4. " PDD[4] ,Port Data Direction" "Input,Output" newline bitfld.long 0x00 3. " PDD[3] ,Port Data Direction" "Input,Output" bitfld.long 0x00 2. " PDD[2] ,Port Data Direction" "Input,Output" bitfld.long 0x00 1. " PDD[1] ,Port Data Direction" "Input,Output" bitfld.long 0x00 0. " PDD[0] ,Port Data Direction" "Input,Output" width 0x0B tree.end tree "GPIO_B" base ad:0x400FF040 width 20. group.long 0x00++0x03 line.long 0x00 "GPIOB_PDOR_SET/CLR,Port Data Output Register" setclrfld.long 0x00 23. 0x04 23. 0x08 23. " PDO[23] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 22. 0x04 22. 0x08 22. " PDO[22] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 21. 0x04 21. 0x08 21. " PDO[21] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20] ,Port Data Output" "Low level,High level" newline setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16] ,Port Data Output" "Low level,High level" newline setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO[10] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO[9] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8] ,Port Data Output" "Low level,High level" newline setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4] ,Port Data Output" "Low level,High level" newline setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0] ,Port Data Output" "Low level,High level" wgroup.long 0x0C++0x03 line.long 0x00 "GPIOB_PTOR,Port Toggle Output Register" bitfld.long 0x00 23. " PTTO[23] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 22. " PTTO[22] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 21. " PTTO[21] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 20. " PTTO[20] ,Port Toggle Output" "No effect,Toggle" newline bitfld.long 0x00 15. " PTTO[15] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 14. " PTTO[14] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 13. " PTTO[13] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 12. " PTTO[12] ,Port Toggle Output" "No effect,Toggle" newline bitfld.long 0x00 11. " PTTO[11] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 10. " PTTO[10] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 9. " PTTO[9] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 8. " PTTO[8] ,Port Toggle Output" "No effect,Toggle" newline bitfld.long 0x00 7. " PTTO[7] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 6. " PTTO[6] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 5. " PTTO[5] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 4. " PTTO[4] ,Port Toggle Output" "No effect,Toggle" newline bitfld.long 0x00 3. " PTTO[3] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 2. " PTTO[2] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 1. " PTTO[1] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 0. " PTTO[0] ,Port Toggle Output" "No effect,Toggle" rgroup.long 0x10++0x03 line.long 0x00 "GPIOB_PDIR,Port Data Input Register" bitfld.long 0x00 23. " PDI[23] ,Port Data Input" "Low level,High level" bitfld.long 0x00 22. " PDI[22] ,Port Data Input" "Low level,High level" bitfld.long 0x00 21. " PDI[21] ,Port Data Input" "Low level,High level" bitfld.long 0x00 20. " PDI[20] ,Port Data Input" "Low level,High level" newline bitfld.long 0x00 15. " PDI[15] ,Port Data Input" "Low level,High level" bitfld.long 0x00 14. " PDI[14] ,Port Data Input" "Low level,High level" bitfld.long 0x00 13. " PDI[13] ,Port Data Input" "Low level,High level" bitfld.long 0x00 12. " PDI[12] ,Port Data Input" "Low level,High level" newline bitfld.long 0x00 11. " PDI[11] ,Port Data Input" "Low level,High level" bitfld.long 0x00 10. " PDI[10] ,Port Data Input" "Low level,High level" bitfld.long 0x00 9. " PDI[9] ,Port Data Input" "Low level,High level" bitfld.long 0x00 8. " PDI[8] ,Port Data Input" "Low level,High level" newline bitfld.long 0x00 7. " PDI[7] ,Port Data Input" "Low level,High level" bitfld.long 0x00 6. " PDI[6] ,Port Data Input" "Low level,High level" bitfld.long 0x00 5. " PDI[5] ,Port Data Input" "Low level,High level" bitfld.long 0x00 4. " PDI[4] ,Port Data Input" "Low level,High level" newline bitfld.long 0x00 3. " PDI[3] ,Port Data Input" "Low level,High level" bitfld.long 0x00 2. " PDI[2] ,Port Data Input" "Low level,High level" bitfld.long 0x00 1. " PDI[1] ,Port Data Input" "Low level,High level" bitfld.long 0x00 0. " PDI[0] ,Port Data Input" "Low level,High level" group.long 0x14++0x03 line.long 0x00 "GPIOB_PDDR,Port Data Direction Register" bitfld.long 0x00 23. " PDD[23] ,Port Data Direction" "Input,Output" bitfld.long 0x00 22. " PDD[22] ,Port Data Direction" "Input,Output" bitfld.long 0x00 21. " PDD[21] ,Port Data Direction" "Input,Output" bitfld.long 0x00 20. " PDD[20] ,Port Data Direction" "Input,Output" newline bitfld.long 0x00 15. " PDD[15] ,Port Data Direction" "Input,Output" bitfld.long 0x00 14. " PDD[14] ,Port Data Direction" "Input,Output" bitfld.long 0x00 13. " PDD[13] ,Port Data Direction" "Input,Output" bitfld.long 0x00 12. " PDD[12] ,Port Data Direction" "Input,Output" newline bitfld.long 0x00 11. " PDD[11] ,Port Data Direction" "Input,Output" bitfld.long 0x00 10. " PDD[10] ,Port Data Direction" "Input,Output" bitfld.long 0x00 9. " PDD[9] ,Port Data Direction" "Input,Output" bitfld.long 0x00 8. " PDD[8] ,Port Data Direction" "Input,Output" newline bitfld.long 0x00 7. " PDD[7] ,Port Data Direction" "Input,Output" bitfld.long 0x00 6. " PDD[6] ,Port Data Direction" "Input,Output" bitfld.long 0x00 5. " PDD[5] ,Port Data Direction" "Input,Output" bitfld.long 0x00 4. " PDD[4] ,Port Data Direction" "Input,Output" newline bitfld.long 0x00 3. " PDD[3] ,Port Data Direction" "Input,Output" bitfld.long 0x00 2. " PDD[2] ,Port Data Direction" "Input,Output" bitfld.long 0x00 1. " PDD[1] ,Port Data Direction" "Input,Output" bitfld.long 0x00 0. " PDD[0] ,Port Data Direction" "Input,Output" width 0x0B tree.end tree "GPIO_C" base ad:0x400FF080 width 20. sif cpuis("MK8?FN256V*") group.long 0x00++0x03 line.long 0x00 "GPIOC_PDOR_SET/CLR,Port Data Output Register" setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16] ,Port Data Output" "Low level,High level" newline setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PDO[15] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PDO[14] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PDO[13] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PDO[12] ,Port Data Output" "Low level,High level" newline setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO[10] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO[9] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8] ,Port Data Output" "Low level,High level" newline setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4] ,Port Data Output" "Low level,High level" newline setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0] ,Port Data Output" "Low level,High level" wgroup.long 0x0C++0x03 line.long 0x00 "GPIOC_PTOR,Port Toggle Output Register" bitfld.long 0x00 19. " PTTO[19] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 18. " PTTO[18] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 17. " PTTO[17] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 16. " PTTO[16] ,Port Toggle Output" "No effect,Toggle" newline bitfld.long 0x00 15. " PTTO[15] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 14. " PTTO[14] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 13. " PTTO[13] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 12. " PTTO[12] ,Port Toggle Output" "No effect,Toggle" newline bitfld.long 0x00 11. " PTTO[11] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 10. " PTTO[10] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 9. " PTTO[9] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 8. " PTTO[8] ,Port Toggle Output" "No effect,Toggle" newline bitfld.long 0x00 7. " PTTO[7] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 6. " PTTO[6] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 5. " PTTO[5] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 4. " PTTO[4] ,Port Toggle Output" "No effect,Toggle" newline bitfld.long 0x00 3. " PTTO[3] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 2. " PTTO[2] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 1. " PTTO[1] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 0. " PTTO[0] ,Port Toggle Output" "No effect,Toggle" rgroup.long 0x10++0x03 line.long 0x00 "GPIOC_PDIR,Port Data Input Register" bitfld.long 0x00 19. " PDI[19] ,Port Data Input" "Low level,High level" bitfld.long 0x00 18. " PDI[18] ,Port Data Input" "Low level,High level" bitfld.long 0x00 17. " PDI[17] ,Port Data Input" "Low level,High level" bitfld.long 0x00 16. " PDI[16] ,Port Data Input" "Low level,High level" newline bitfld.long 0x00 15. " PDI[15] ,Port Data Input" "Low level,High level" bitfld.long 0x00 14. " PDI[14] ,Port Data Input" "Low level,High level" bitfld.long 0x00 13. " PDI[13] ,Port Data Input" "Low level,High level" bitfld.long 0x00 12. " PDI[12] ,Port Data Input" "Low level,High level" newline bitfld.long 0x00 11. " PDI[11] ,Port Data Input" "Low level,High level" bitfld.long 0x00 10. " PDI[10] ,Port Data Input" "Low level,High level" bitfld.long 0x00 9. " PDI[9] ,Port Data Input" "Low level,High level" bitfld.long 0x00 8. " PDI[8] ,Port Data Input" "Low level,High level" newline bitfld.long 0x00 7. " PDI[7] ,Port Data Input" "Low level,High level" bitfld.long 0x00 6. " PDI[6] ,Port Data Input" "Low level,High level" bitfld.long 0x00 5. " PDI[5] ,Port Data Input" "Low level,High level" bitfld.long 0x00 4. " PDI[4] ,Port Data Input" "Low level,High level" newline bitfld.long 0x00 3. " PDI[3] ,Port Data Input" "Low level,High level" bitfld.long 0x00 2. " PDI[2] ,Port Data Input" "Low level,High level" bitfld.long 0x00 1. " PDI[1] ,Port Data Input" "Low level,High level" bitfld.long 0x00 0. " PDI[0] ,Port Data Input" "Low level,High level" group.long 0x14++0x03 line.long 0x00 "GPIOC_PDDR,Port Data Direction Register" bitfld.long 0x00 19. " PDD[19] ,Port Data Direction" "Input,Output" bitfld.long 0x00 18. " PDD[18] ,Port Data Direction" "Input,Output" bitfld.long 0x00 17. " PDD[17] ,Port Data Direction" "Input,Output" bitfld.long 0x00 16. " PDD[16] ,Port Data Direction" "Input,Output" newline bitfld.long 0x00 15. " PDD[15] ,Port Data Direction" "Input,Output" bitfld.long 0x00 14. " PDD[14] ,Port Data Direction" "Input,Output" bitfld.long 0x00 13. " PDD[13] ,Port Data Direction" "Input,Output" bitfld.long 0x00 12. " PDD[12] ,Port Data Direction" "Input,Output" newline bitfld.long 0x00 11. " PDD[11] ,Port Data Direction" "Input,Output" bitfld.long 0x00 10. " PDD[10] ,Port Data Direction" "Input,Output" bitfld.long 0x00 9. " PDD[9] ,Port Data Direction" "Input,Output" bitfld.long 0x00 8. " PDD[8] ,Port Data Direction" "Input,Output" newline bitfld.long 0x00 7. " PDD[7] ,Port Data Direction" "Input,Output" bitfld.long 0x00 6. " PDD[6] ,Port Data Direction" "Input,Output" bitfld.long 0x00 5. " PDD[5] ,Port Data Direction" "Input,Output" bitfld.long 0x00 4. " PDD[4] ,Port Data Direction" "Input,Output" newline bitfld.long 0x00 3. " PDD[3] ,Port Data Direction" "Input,Output" bitfld.long 0x00 2. " PDD[2] ,Port Data Direction" "Input,Output" bitfld.long 0x00 1. " PDD[1] ,Port Data Direction" "Input,Output" bitfld.long 0x00 0. " PDD[0] ,Port Data Direction" "Input,Output" else group.long 0x00++0x03 line.long 0x00 "GPIOC_PDOR_SET/CLR,Port Data Output Register" setclrfld.long 0x00 29. 0x04 29. 0x08 29. " PDO[29] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 28. 0x04 28. 0x08 28. " PDO[28] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 27. 0x04 27. 0x08 27. " PDO[27] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 26. 0x04 26. 0x08 26. " PDO[26] ,Port Data Output" "Low level,High level" newline setclrfld.long 0x00 25. 0x04 25. 0x08 25. " PDO[25] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 24. 0x04 24. 0x08 24. " PDO[24] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18] ,Port Data Output" "Low level,High level" newline setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PDO[15] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PDO[14] ,Port Data Output" "Low level,High level" newline setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PDO[13] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PDO[12] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO[10] ,Port Data Output" "Low level,High level" newline setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO[9] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6] ,Port Data Output" "Low level,High level" newline setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2] ,Port Data Output" "Low level,High level" newline setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0] ,Port Data Output" "Low level,High level" wgroup.long 0x0C++0x03 line.long 0x00 "GPIOC_PTOR,Port Toggle Output Register" bitfld.long 0x00 29. " PTTO[29] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 28. " PTTO[28] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 27. " PTTO[27] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 26. " PTTO[26] ,Port Toggle Output" "No effect,Toggle" newline bitfld.long 0x00 25. " PTTO[25] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 24. " PTTO[24] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 19. " PTTO[19] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 18. " PTTO[18] ,Port Toggle Output" "No effect,Toggle" newline bitfld.long 0x00 17. " PTTO[17] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 16. " PTTO[16] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 15. " PTTO[15] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 14. " PTTO[14] ,Port Toggle Output" "No effect,Toggle" newline bitfld.long 0x00 13. " PTTO[13] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 12. " PTTO[12] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 11. " PTTO[11] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 10. " PTTO[10] ,Port Toggle Output" "No effect,Toggle" newline bitfld.long 0x00 9. " PTTO[9] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 8. " PTTO[8] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 7. " PTTO[7] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 6. " PTTO[6] ,Port Toggle Output" "No effect,Toggle" newline bitfld.long 0x00 5. " PTTO[5] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 4. " PTTO[4] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 3. " PTTO[3] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 2. " PTTO[2] ,Port Toggle Output" "No effect,Toggle" newline bitfld.long 0x00 1. " PTTO[1] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 0. " PTTO[0] ,Port Toggle Output" "No effect,Toggle" rgroup.long 0x10++0x03 line.long 0x00 "GPIOC_PDIR,Port Data Input Register" bitfld.long 0x00 29. " PDI[29] ,Port Data Input" "Low level,High level" bitfld.long 0x00 28. " PDI[28] ,Port Data Input" "Low level,High level" bitfld.long 0x00 27. " PDI[27] ,Port Data Input" "Low level,High level" bitfld.long 0x00 26. " PDI[26] ,Port Data Input" "Low level,High level" newline bitfld.long 0x00 25. " PDI[25] ,Port Data Input" "Low level,High level" bitfld.long 0x00 24. " PDI[24] ,Port Data Input" "Low level,High level" bitfld.long 0x00 19. " PDI[19] ,Port Data Input" "Low level,High level" bitfld.long 0x00 18. " PDI[18] ,Port Data Input" "Low level,High level" newline bitfld.long 0x00 17. " PDI[17] ,Port Data Input" "Low level,High level" bitfld.long 0x00 16. " PDI[16] ,Port Data Input" "Low level,High level" bitfld.long 0x00 15. " PDI[15] ,Port Data Input" "Low level,High level" bitfld.long 0x00 14. " PDI[14] ,Port Data Input" "Low level,High level" newline bitfld.long 0x00 13. " PDI[13] ,Port Data Input" "Low level,High level" bitfld.long 0x00 12. " PDI[12] ,Port Data Input" "Low level,High level" bitfld.long 0x00 11. " PDI[11] ,Port Data Input" "Low level,High level" bitfld.long 0x00 10. " PDI[10] ,Port Data Input" "Low level,High level" newline bitfld.long 0x00 9. " PDI[9] ,Port Data Input" "Low level,High level" bitfld.long 0x00 8. " PDI[8] ,Port Data Input" "Low level,High level" bitfld.long 0x00 7. " PDI[7] ,Port Data Input" "Low level,High level" bitfld.long 0x00 6. " PDI[6] ,Port Data Input" "Low level,High level" newline bitfld.long 0x00 5. " PDI[5] ,Port Data Input" "Low level,High level" bitfld.long 0x00 4. " PDI[4] ,Port Data Input" "Low level,High level" bitfld.long 0x00 3. " PDI[3] ,Port Data Input" "Low level,High level" bitfld.long 0x00 2. " PDI[2] ,Port Data Input" "Low level,High level" newline bitfld.long 0x00 1. " PDI[1] ,Port Data Input" "Low level,High level" bitfld.long 0x00 0. " PDI[0] ,Port Data Input" "Low level,High level" group.long 0x14++0x03 line.long 0x00 "GPIOC_PDDR,Port Data Direction Register" bitfld.long 0x00 29. " PDD[29] ,Port Data Direction" "Input,Output" bitfld.long 0x00 28. " PDD[28] ,Port Data Direction" "Input,Output" bitfld.long 0x00 27. " PDD[27] ,Port Data Direction" "Input,Output" bitfld.long 0x00 26. " PDD[26] ,Port Data Direction" "Input,Output" newline bitfld.long 0x00 25. " PDD[25] ,Port Data Direction" "Input,Output" bitfld.long 0x00 24. " PDD[24] ,Port Data Direction" "Input,Output" bitfld.long 0x00 19. " PDD[19] ,Port Data Direction" "Input,Output" bitfld.long 0x00 18. " PDD[18] ,Port Data Direction" "Input,Output" newline bitfld.long 0x00 17. " PDD[17] ,Port Data Direction" "Input,Output" bitfld.long 0x00 16. " PDD[16] ,Port Data Direction" "Input,Output" bitfld.long 0x00 15. " PDD[15] ,Port Data Direction" "Input,Output" bitfld.long 0x00 14. " PDD[14] ,Port Data Direction" "Input,Output" newline bitfld.long 0x00 13. " PDD[13] ,Port Data Direction" "Input,Output" bitfld.long 0x00 12. " PDD[12] ,Port Data Direction" "Input,Output" bitfld.long 0x00 11. " PDD[11] ,Port Data Direction" "Input,Output" bitfld.long 0x00 10. " PDD[10] ,Port Data Direction" "Input,Output" newline bitfld.long 0x00 9. " PDD[9] ,Port Data Direction" "Input,Output" bitfld.long 0x00 8. " PDD[8] ,Port Data Direction" "Input,Output" bitfld.long 0x00 7. " PDD[7] ,Port Data Direction" "Input,Output" bitfld.long 0x00 6. " PDD[6] ,Port Data Direction" "Input,Output" newline bitfld.long 0x00 5. " PDD[5] ,Port Data Direction" "Input,Output" bitfld.long 0x00 4. " PDD[4] ,Port Data Direction" "Input,Output" bitfld.long 0x00 3. " PDD[3] ,Port Data Direction" "Input,Output" bitfld.long 0x00 2. " PDD[2] ,Port Data Direction" "Input,Output" newline bitfld.long 0x00 1. " PDD[1] ,Port Data Direction" "Input,Output" bitfld.long 0x00 0. " PDD[0] ,Port Data Direction" "Input,Output" endif width 0x0B tree.end tree "GPIO_D" base ad:0x400FF0C0 width 20. group.long 0x00++0x03 line.long 0x00 "GPIOD_PDOR_SET/CLR,Port Data Output Register" setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PDO[15] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PDO[14] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PDO[13] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PDO[12] ,Port Data Output" "Low level,High level" newline setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO[10] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO[9] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8] ,Port Data Output" "Low level,High level" newline setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4] ,Port Data Output" "Low level,High level" newline setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0] ,Port Data Output" "Low level,High level" wgroup.long 0x0C++0x03 line.long 0x00 "GPIOD_PTOR,Port Toggle Output Register" bitfld.long 0x00 15. " PTTO[15] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 14. " PTTO[14] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 13. " PTTO[13] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 12. " PTTO[12] ,Port Toggle Output" "No effect,Toggle" newline bitfld.long 0x00 11. " PTTO[11] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 10. " PTTO[10] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 9. " PTTO[9] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 8. " PTTO[8] ,Port Toggle Output" "No effect,Toggle" newline bitfld.long 0x00 7. " PTTO[7] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 6. " PTTO[6] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 5. " PTTO[5] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 4. " PTTO[4] ,Port Toggle Output" "No effect,Toggle" newline bitfld.long 0x00 3. " PTTO[3] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 2. " PTTO[2] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 1. " PTTO[1] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 0. " PTTO[0] ,Port Toggle Output" "No effect,Toggle" rgroup.long 0x10++0x03 line.long 0x00 "GPIOD_PDIR,Port Data Input Register" bitfld.long 0x00 15. " PDI[15] ,Port Data Input" "Low level,High level" bitfld.long 0x00 14. " PDI[14] ,Port Data Input" "Low level,High level" bitfld.long 0x00 13. " PDI[13] ,Port Data Input" "Low level,High level" bitfld.long 0x00 12. " PDI[12] ,Port Data Input" "Low level,High level" newline bitfld.long 0x00 11. " PDI[11] ,Port Data Input" "Low level,High level" bitfld.long 0x00 10. " PDI[10] ,Port Data Input" "Low level,High level" bitfld.long 0x00 9. " PDI[9] ,Port Data Input" "Low level,High level" bitfld.long 0x00 8. " PDI[8] ,Port Data Input" "Low level,High level" newline bitfld.long 0x00 7. " PDI[7] ,Port Data Input" "Low level,High level" bitfld.long 0x00 6. " PDI[6] ,Port Data Input" "Low level,High level" bitfld.long 0x00 5. " PDI[5] ,Port Data Input" "Low level,High level" bitfld.long 0x00 4. " PDI[4] ,Port Data Input" "Low level,High level" newline bitfld.long 0x00 3. " PDI[3] ,Port Data Input" "Low level,High level" bitfld.long 0x00 2. " PDI[2] ,Port Data Input" "Low level,High level" bitfld.long 0x00 1. " PDI[1] ,Port Data Input" "Low level,High level" bitfld.long 0x00 0. " PDI[0] ,Port Data Input" "Low level,High level" group.long 0x14++0x03 line.long 0x00 "GPIOD_PDDR,Port Data Direction Register" bitfld.long 0x00 15. " PDD[15] ,Port Data Direction" "Input,Output" bitfld.long 0x00 14. " PDD[14] ,Port Data Direction" "Input,Output" bitfld.long 0x00 13. " PDD[13] ,Port Data Direction" "Input,Output" bitfld.long 0x00 12. " PDD[12] ,Port Data Direction" "Input,Output" newline bitfld.long 0x00 11. " PDD[11] ,Port Data Direction" "Input,Output" bitfld.long 0x00 10. " PDD[10] ,Port Data Direction" "Input,Output" bitfld.long 0x00 9. " PDD[9] ,Port Data Direction" "Input,Output" bitfld.long 0x00 8. " PDD[8] ,Port Data Direction" "Input,Output" newline bitfld.long 0x00 7. " PDD[7] ,Port Data Direction" "Input,Output" bitfld.long 0x00 6. " PDD[6] ,Port Data Direction" "Input,Output" bitfld.long 0x00 5. " PDD[5] ,Port Data Direction" "Input,Output" bitfld.long 0x00 4. " PDD[4] ,Port Data Direction" "Input,Output" newline bitfld.long 0x00 3. " PDD[3] ,Port Data Direction" "Input,Output" bitfld.long 0x00 2. " PDD[2] ,Port Data Direction" "Input,Output" bitfld.long 0x00 1. " PDD[1] ,Port Data Direction" "Input,Output" bitfld.long 0x00 0. " PDD[0] ,Port Data Direction" "Input,Output" width 0x0B tree.end tree "GPIO_E" base ad:0x400FF100 width 20. group.long 0x00++0x03 line.long 0x00 "GPIOE_PDOR_SET/CLR,Port Data Output Register" sif !cpuis("MK8?FN256V*") setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16] ,Port Data Output" "Low level,High level" newline setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PDO[13] ,Port Data Output" "Low level,High level" endif setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PDO[12] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO[10] ,Port Data Output" "Low level,High level" newline setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO[9] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6] ,Port Data Output" "Low level,High level" newline setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2] ,Port Data Output" "Low level,High level" newline setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0] ,Port Data Output" "Low level,High level" wgroup.long 0x0C++0x03 line.long 0x00 "GPIOE_PTOR,Port Toggle Output Register" sif !cpuis("MK8?FN256V*") bitfld.long 0x00 19. " PTTO[19] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 18. " PTTO[18] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 17. " PTTO[17] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 16. " PTTO[16] ,Port Toggle Output" "No effect,Toggle" newline bitfld.long 0x00 13. " PTTO[13] ,Port Toggle Output" "No effect,Toggle" endif bitfld.long 0x00 12. " PTTO[12] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 11. " PTTO[11] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 10. " PTTO[10] ,Port Toggle Output" "No effect,Toggle" newline bitfld.long 0x00 9. " PTTO[9] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 8. " PTTO[8] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 7. " PTTO[7] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 6. " PTTO[6] ,Port Toggle Output" "No effect,Toggle" newline bitfld.long 0x00 5. " PTTO[5] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 4. " PTTO[4] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 3. " PTTO[3] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 2. " PTTO[2] ,Port Toggle Output" "No effect,Toggle" newline bitfld.long 0x00 1. " PTTO[1] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 0. " PTTO[0] ,Port Toggle Output" "No effect,Toggle" rgroup.long 0x10++0x03 line.long 0x00 "GPIOE_PDIR,Port Data Input Register" sif !cpuis("MK8?FN256V*") bitfld.long 0x00 19. " PDI[19] ,Port Data Input" "Low level,High level" bitfld.long 0x00 18. " PDI[18] ,Port Data Input" "Low level,High level" bitfld.long 0x00 17. " PDI[17] ,Port Data Input" "Low level,High level" bitfld.long 0x00 16. " PDI[16] ,Port Data Input" "Low level,High level" newline bitfld.long 0x00 13. " PDI[13] ,Port Data Input" "Low level,High level" endif bitfld.long 0x00 12. " PDI[12] ,Port Data Input" "Low level,High level" bitfld.long 0x00 11. " PDI[11] ,Port Data Input" "Low level,High level" bitfld.long 0x00 10. " PDI[10] ,Port Data Input" "Low level,High level" newline bitfld.long 0x00 9. " PDI[9] ,Port Data Input" "Low level,High level" bitfld.long 0x00 8. " PDI[8] ,Port Data Input" "Low level,High level" bitfld.long 0x00 7. " PDI[7] ,Port Data Input" "Low level,High level" bitfld.long 0x00 6. " PDI[6] ,Port Data Input" "Low level,High level" newline bitfld.long 0x00 5. " PDI[5] ,Port Data Input" "Low level,High level" bitfld.long 0x00 4. " PDI[4] ,Port Data Input" "Low level,High level" bitfld.long 0x00 3. " PDI[3] ,Port Data Input" "Low level,High level" bitfld.long 0x00 2. " PDI[2] ,Port Data Input" "Low level,High level" newline bitfld.long 0x00 1. " PDI[1] ,Port Data Input" "Low level,High level" bitfld.long 0x00 0. " PDI[0] ,Port Data Input" "Low level,High level" group.long 0x14++0x03 line.long 0x00 "GPIOE_PDDR,Port Data Direction Register" sif !cpuis("MK8?FN256V*") bitfld.long 0x00 19. " PDD[19] ,Port Data Direction" "Input,Output" bitfld.long 0x00 18. " PDD[18] ,Port Data Direction" "Input,Output" bitfld.long 0x00 17. " PDD[17] ,Port Data Direction" "Input,Output" bitfld.long 0x00 16. " PDD[16] ,Port Data Direction" "Input,Output" newline bitfld.long 0x00 13. " PDD[13] ,Port Data Direction" "Input,Output" endif bitfld.long 0x00 12. " PDD[12] ,Port Data Direction" "Input,Output" bitfld.long 0x00 11. " PDD[11] ,Port Data Direction" "Input,Output" bitfld.long 0x00 10. " PDD[10] ,Port Data Direction" "Input,Output" newline bitfld.long 0x00 9. " PDD[9] ,Port Data Direction" "Input,Output" bitfld.long 0x00 8. " PDD[8] ,Port Data Direction" "Input,Output" bitfld.long 0x00 7. " PDD[7] ,Port Data Direction" "Input,Output" bitfld.long 0x00 6. " PDD[6] ,Port Data Direction" "Input,Output" newline bitfld.long 0x00 5. " PDD[5] ,Port Data Direction" "Input,Output" bitfld.long 0x00 4. " PDD[4] ,Port Data Direction" "Input,Output" bitfld.long 0x00 3. " PDD[3] ,Port Data Direction" "Input,Output" bitfld.long 0x00 2. " PDD[2] ,Port Data Direction" "Input,Output" newline bitfld.long 0x00 1. " PDD[1] ,Port Data Direction" "Input,Output" bitfld.long 0x00 0. " PDD[0] ,Port Data Direction" "Input,Output" width 0x0B tree.end tree.end newline