; -------------------------------------------------------------------------------- ; @Title: TDA3x Specific Menu ; @Props: Released ; @Author: ASK, KMB, PIW ; @Changelog: 2016-03-29 ASK ; 2021-09-02 KMB ; 2022-04-27 PIW ; @Manufacturer: TI - Texas Instruments ; @Core: Cortex-M4, C66x ; @Chip: TDA3XIPU-CORE0, TDA3XIPU-CORE1, TDA3XDSP*, TDA3XEVE ; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: mentda3x.men 16339 2023-07-03 13:30:14Z pegold $ add menu ( if (CPUFAMILY()=="C6000") ( popup "&CPU" ( after "FPU Registers" separator popup "[:cache]Cache" ( menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC" menuitem "[:cache]ICACHE List" "CACHE.List IC" menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC" separator menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC" menuitem "[:cache]DCACHE List" "CACHE.List DC" menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC" separator menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2" menuitem "[:cache]L2CACHE List" "CACHE.List L2" menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2" ) ) popup "&Trace" ( IF COMPonent.AVAILable("TPIU") ( menuitem "[:oconfig]TPIU settings..." "TPIU.state" ) IF COMPonent.AVAILable("AET") ( menuitem "[:oconfig]AET settings..." "AET.state" ) ) popup "&Perf" ( before "Reset" menuitem "[:bmc]Benchmark Counters" "BMC.state" before "Reset" separator ) ) else ( IF SOFTWARE.BUILD.BASE()>=69655. ( popup "&CPU" ( separator IF CPU.FEATURE(MMU) ( popup "[:mmu]MMU" ( menuitem "[:mmureg]MMU Control" "MMU.view" separator menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable" menuitem "[:mmu]MMU Table List" "MMU.List.PageTable" separator IF CPU.FEATURE(ITLBDUMP) ( menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB" ) IF CPU.FEATURE(DTLBDUMP) ( menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB" ) IF CPU.FEATURE(TLB0DUMP) ( menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0" ) IF CPU.FEATURE(TLB1DUMP) ( menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1" ) ) ) IF COMPonent.AVAILable("SMMU") ( popup "[:mmu]SMMU" ( menuitem "[:chip]SMMU1 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU1 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.)) SMMU.StreamMapTable &(name) ) IF COMPonent.AVAILable("SMMU2") ( separator menuitem "[:chip]SMMU2 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU2 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU3") ( separator menuitem "[:chip]SMMU3 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU3 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU4") ( separator menuitem "[:chip]SMMU4 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU4 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU5") ( separator menuitem "[:chip]SMMU5 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU5 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU6") ( separator menuitem "[:chip]SMMU6 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU6 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.)) SMMU.StreamMapTable &(name) ) ) ) ) IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE) ( popup "[:cache]Cache" ( IF CPU.FEATURE(L1ICACHEDUMP) ( menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC" menuitem "[:cache]ICACHE List" "CACHE.List IC" menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC" ) IF CPU.FEATURE(L1DCACHEDUMP) ( separator menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC" menuitem "[:cache]DCACHE List" "CACHE.List DC" menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC" ) IF CPU.FEATURE(L2CACHEDUMP) ( separator menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2" menuitem "[:cache]L2CACHE List" "CACHE.List L2" menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2" ) ) ) ) popup "&Trace" ( separator IF COMPonent.AVAILable("ITM") ( popup "ITM" ( default menuitem "[:oconfig]ITM settings..." "ITM.state" separator menuitem "[:alist]ITMTrace List" "ITMTrace.List" ) ) IF COMPonent.AVAILable("STM") ( popup "STM" ( default menuitem "[:oconfig]STM settings..." "STM.state" separator menuitem "[:alist]STMTrace List" "STMTrace.List" ) ) IF COMPonent.AVAILable("HTM") ( popup "HTM" ( default menuitem "[:oconfig]HTM settings..." "HTM.state" separator menuitem "[:alist]HTMTrace List" "HTMTrace.List" ) ) IF COMPonent.AVAILable("TPIU") ( menuitem "[:oconfig]TPIU settings..." "TPIU.state" ) IF COMPonent.AVAILable("ETR") ( menuitem "[:oconfig]ETR settings..." ( PRIVATE &pdd &pdd=OS.PDD() DO "&pdd/etc/embedded_trace_router/etr_utility.cmm" ) ) ) popup "&Misc" ( popup "Tools" ( IF CPUIS64BIT()||CPU.FEATURE("SPR") ( menuitem "ARM System Register Converter" ( DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm" ) ) IF CPU.FEATURE("C15") ( menuitem "ARM Coprocessor Converter" ( DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm" ) ) ) ) popup "&Perf" ( IF CPU.FEATURE(BMC) ( before "Reset" menuitem "[:bmc]Benchmark Counters" "BMC.state" before "Reset" separator ) ) ) ) popup "Peripherals" ( if (CORENAME()=="CORTEXM4") ( popup "[:chip]Core Registers (Cortex-M4)" ( menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M4),System Control""" menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M4),Memory Protection Unit""" menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M4),Nested Vectored Interrupt Controller""" popup "[:chip]Debug" ( menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M4),Debug,Core Debug""" menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit" "per , ""Core Registers (Cortex-M4),Debug,Flash Patch and Breakpoint Unit (FPB)""" menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M4),Debug,Data Watchpoint and Trace Unit (DWT)""" ) ) ) else ( popup "[:chip]Core Registers (c66x)" ( menuitem "[:chip]L1P;L1P Registers" "per , ""Core Registers (c66x),Cache,L1P Cache""" menuitem "[:chip]L1D;L1D Registers" "per , ""Core Registers (c66x),Cache,L1D Cache""" menuitem "[:chip]L2;L2 Registers" "per , ""Core Registers (c66x),Cache,L2 Cache""" menuitem "[:chip]IDMA;IDMA Registers" "per , ""Core Registers (c66x),IDMA (Internal Direct Memory Access Controller)""" menuitem "[:chip]XMC;XMC Registers" "per , ""Core Registers (c66x),XMC (Extended Memory Controller)""" menuitem "[:chip]BM;BM Registers" "per , ""Core Registers (c66x),Bandwith Management""" menuitem "[:chip]IC;IC Registers" "per , ""Core Registers (c66x),Interrupt Controller""" menuitem "[:chip]PD;PD Registers" "per , ""Core Registers (c66x),Power-Down Controller""" ) ) separator if (cpuis("TDA3XIPU*")) ( menuitem "ADC" "per , ""ADC""" menuitem "ALE" "per , ""ALE""" menuitem "CAL_A" "per , ""CAL_A""" menuitem "CAL_B" "per , ""CAL_B""" menuitem "CAM_CM_CORE" "per , ""CAM_CM_CORE""" menuitem "CAM_PRM" "per , ""CAM_PRM""" menuitem "CAMERARX_CORE_0" "per , ""CAMERARX_CORE_0""" menuitem "CKGEN_CM_CORE" "per , ""CKGEN_CM_CORE""" menuitem "CKGEN_CM_CORE_AON" "per , ""CKGEN_CM_CORE_AON""" menuitem "CKGEN_PRM" "per , ""CKGEN_PRM""" menuitem "CLK1_DSP1_EDMA_BW_LIMITER" "per , ""CLK1_DSP1_EDMA_BW_LIMITER""" menuitem "CLK1_DSP1_MDMA_BW_LIMITER" "per , ""CLK1_DSP1_MDMA_BW_LIMITER""" menuitem "CLK1_DSP1_MDMA_BW_REGULATOR" "per , ""CLK1_DSP1_MDMA_BW_REGULATOR""" menuitem "CLK1_DSP2_EDMA_BW_LIMITER" "per , ""CLK1_DSP2_EDMA_BW_LIMITER""" menuitem "CLK1_DSP2_MDMA_BW_LIMITER" "per , ""CLK1_DSP2_MDMA_BW_LIMITER""" menuitem "CLK1_DSP2_MDMA_BW_REGULATOR" "per , ""CLK1_DSP2_MDMA_BW_REGULATOR""" menuitem "CLK1_EVE_TC0_BW_LIMITER" "per , ""CLK1_EVE_TC0_BW_LIMITER""" menuitem "CLK1_EVE_TC0_BW_REGULATOR" "per , ""CLK1_EVE_TC0_BW_REGULATOR""" menuitem "CLK1_EVE_TC1_BW_LIMITER" "per , ""CLK1_EVE_TC1_BW_LIMITER""" menuitem "CLK1_EVE_TC1_BW_REGULATOR" "per , ""CLK1_EVE_TC1_BW_REGULATOR""" menuitem "CLK1_FLAGMUX_CLK1" "per , ""CLK1_FLAGMUX_CLK1""" menuitem "CLK1_FLAGMUX_CLK1_1" "per , ""CLK1_FLAGMUX_CLK1_1""" menuitem "CLK1_FLAGMUX_CLK1_2" "per , ""CLK1_FLAGMUX_CLK1_2""" menuitem "CLK1_FLAGMUX_CLK1MERGE" "per , ""CLK1_FLAGMUX_CLK1MERGE""" menuitem "CLK1_GMAC_SW_BW_REGULATOR" "per , ""CLK1_GMAC_SW_BW_REGULATOR""" menuitem "CLK1_HOST_CLK1_1" "per , ""CLK1_HOST_CLK1_1""" menuitem "CLK1_HOST_CLK1_2" "per , ""CLK1_HOST_CLK1_2""" menuitem "CLK1_IPU_BW_LIMITER" "per , ""CLK1_IPU_BW_LIMITER""" menuitem "CLK1_IPU_BW_REGULATOR" "per , ""CLK1_IPU_BW_REGULATOR""" menuitem "CLK1_ISS_NRT1_BW_LIMITER" "per , ""CLK1_ISS_NRT1_BW_LIMITER""" menuitem "CLK1_ISS_NRT2_BW_LIMITER" "per , ""CLK1_ISS_NRT2_BW_LIMITER""" menuitem "CLK1_MMU_BW_LIMITER" "per , ""CLK1_MMU_BW_LIMITER""" menuitem "CLK1_TPTC1_RD_BW_LIMITER" "per , ""CLK1_TPTC1_RD_BW_LIMITER""" menuitem "CLK1_TPTC1_WR_BW_LIMITER" "per , ""CLK1_TPTC1_WR_BW_LIMITER""" menuitem "CLK1_TPTC2_RD_BW_LIMITER" "per , ""CLK1_TPTC2_RD_BW_LIMITER""" menuitem "CLK1_TPTC2_WR_BW_LIMITER" "per , ""CLK1_TPTC2_WR_BW_LIMITER""" menuitem "CLK2_FLAGMUX_CLK2" "per , ""CLK2_FLAGMUX_CLK2""" menuitem "CLK2_FLAGMUX_CLK2_1" "per , ""CLK2_FLAGMUX_CLK2_1""" menuitem "CLK2_FLAGMUX_STATCOLL" "per , ""CLK2_FLAGMUX_STATCOLL""" menuitem "CLK2_HOST_CLK2_1" "per , ""CLK2_HOST_CLK2_1""" menuitem "CLK2_STATCOLL1" "per , ""CLK2_STATCOLL1""" menuitem "CLK2_STATCOLL2" "per , ""CLK2_STATCOLL2""" menuitem "CLK2_STATCOLL3" "per , ""CLK2_STATCOLL3""" menuitem "CLK2_STATCOLL4" "per , ""CLK2_STATCOLL4""" menuitem "CM_CORE_AON_TARG" "per , ""CM_CORE_AON_TARG""" menuitem "CM_CORE_TARG" "per , ""CM_CORE_TARG""" menuitem "CORE_CM_CORE" "per , ""CORE_CM_CORE""" menuitem "CORE_PRM" "per , ""CORE_PRM""" menuitem "COREAON_CM_CORE" "per , ""COREAON_CM_CORE""" menuitem "COREAON_PRM" "per , ""COREAON_PRM""" menuitem "COUNTER_32K_TARG" "per , ""COUNTER_32K_TARG""" menuitem "CPDMA" "per , ""CPDMA""" menuitem "CPTS" "per , ""CPTS""" menuitem "CRC_CFG_TARG" "per , ""CRC_CFG_TARG""" menuitem "CRC_FW" "per , ""CRC_FW""" menuitem "CRC_FW_CFG_TARG" "per , ""CRC_FW_CFG_TARG""" menuitem "CRC_TARG" "per , ""CRC_TARG""" menuitem "CTRL_MODULE_CORE" "per , ""CTRL_MODULE_CORE""" menuitem "CTRL_MODULE_CORE_TARG" "per , ""CTRL_MODULE_CORE_TARG""" menuitem "CTRL_MODULE_WKUP" "per , ""CTRL_MODULE_WKUP""" menuitem "CTRL_MODULE_WKUP_TARG" "per , ""CTRL_MODULE_WKUP_TARG""" menuitem "CUSTEFUSE_CM_CORE" "per , ""CUSTEFUSE_CM_CORE""" menuitem "CUSTEFUSE_PRM" "per , ""CUSTEFUSE_PRM""" menuitem "DCAN1" "per , ""DCAN1""" menuitem "DCAN2" "per , ""DCAN2""" menuitem "DCAN1_TARG" "per , ""DCAN1_TARG""" menuitem "DCAN2_TARG" "per , ""DCAN2_TARG""" menuitem "DCC1" "per , ""DCC1""" menuitem "DCC2" "per , ""DCC2""" menuitem "DCC3" "per , ""DCC3""" menuitem "DCC4" "per , ""DCC4""" menuitem "DCC5" "per , ""DCC5""" menuitem "DCC6" "per , ""DCC6""" menuitem "DCC7" "per , ""DCC7""" menuitem "DCC1_SR2" "per , ""DCC1_SR2""" menuitem "DCC1_TARG" "per , ""DCC1_TARG""" menuitem "DCC1_TARG_SR2" "per , ""DCC1_TARG_SR2""" menuitem "DCC2_SR2" "per , ""DCC2_SR2""" menuitem "DCC2_TARG" "per , ""DCC2_TARG""" menuitem "DCC2_TARG_SR2" "per , ""DCC2_TARG_SR2""" menuitem "DCC3_SR2" "per , ""DCC3_SR2""" menuitem "DCC3_TARG" "per , ""DCC3_TARG""" menuitem "DCC3_TARG_SR2" "per , ""DCC3_TARG_SR2""" menuitem "DCC4_SR2" "per , ""DCC4_SR2""" menuitem "DCC4_TARG" "per , ""DCC4_TARG""" menuitem "DCC4_TARG_SR2" "per , ""DCC4_TARG_SR2""" menuitem "DCC5_SR2" "per , ""DCC5_SR2""" menuitem "DCC5_TARG" "per , ""DCC5_TARG""" menuitem "DCC5_TARG_SR2" "per , ""DCC5_TARG_SR2""" menuitem "DCC6_SR2" "per , ""DCC6_SR2""" menuitem "DCC6_TARG" "per , ""DCC6_TARG""" menuitem "DCC6_TARG_SR2" "per , ""DCC6_TARG_SR2""" menuitem "DCC7_SR2" "per , ""DCC7_SR2""" menuitem "DCC7_TARG" "per , ""DCC7_TARG""" menuitem "DCC7_TARG_SR2" "per , ""DCC7_TARG_SR2""" menuitem "DEBUGSS_CT_TBR_FW" "per , ""DEBUGSS_CT_TBR_FW""" menuitem "DEBUGSS_CT_TBR_FW_CFG_TARG" "per , ""DEBUGSS_CT_TBR_FW_CFG_TARG""" menuitem "DEBUGSS_CT_TBR_TARG" "per , ""DEBUGSS_CT_TBR_TARG""" menuitem "DEVICE_PRM" "per , ""DEVICE_PRM""" menuitem "DISPC_COMMON" "per , ""DISPC_COMMON""" menuitem "DISPC_GFX1" "per , ""DISPC_GFX1""" menuitem "DISPC_OVR1" "per , ""DISPC_OVR1""" menuitem "DISPC_OVR2" "per , ""DISPC_OVR2""" menuitem "DISPC_VID1" "per , ""DISPC_VID1""" menuitem "DISPC_VID2" "per , ""DISPC_VID2""" menuitem "DISPC_VP1" "per , ""DISPC_VP1""" menuitem "DISPC_WB" "per , ""DISPC_WB""" menuitem "DMA" "per , ""DMA""" menuitem "DRM" "per , ""DRM""" menuitem "DSP1_CM_CORE_AON" "per , ""DSP1_CM_CORE_AON""" menuitem "DSP1_EDMA_TPCC" "per , ""DSP1_EDMA_TPCC""" menuitem "DSP1_EDMA_TPTC0" "per , ""DSP1_EDMA_TPTC0""" menuitem "DSP1_EDMA_TPTC1" "per , ""DSP1_EDMA_TPTC1""" menuitem "DSP1_FW_CFG_TARG" "per , ""DSP1_FW_CFG_TARG""" menuitem "DSP1_FW_L2_NOC_CFG" "per , ""DSP1_FW_L2_NOC_CFG""" menuitem "DSP1_MMU0" "per , ""DSP1_MMU0""" menuitem "DSP1_MMU1" "per , ""DSP1_MMU1""" menuitem "DSP1_PRM" "per , ""DSP1_PRM""" menuitem "DSP1_SDMA_FW" "per , ""DSP1_SDMA_FW""" menuitem "DSP1_SDMA_TARG" "per , ""DSP1_SDMA_TARG""" menuitem "DSP1_SYSTEM" "per , ""DSP1_SYSTEM""" menuitem "DSP2_CM_CORE_AON" "per , ""DSP2_CM_CORE_AON""" menuitem "DSP2_EDMA_TPCC" "per , ""DSP2_EDMA_TPCC""" menuitem "DSP2_EDMA_TPTC0" "per , ""DSP2_EDMA_TPTC0""" menuitem "DSP2_EDMA_TPTC1" "per , ""DSP2_EDMA_TPTC1""" menuitem "DSP2_FW_CFG_TARG" "per , ""DSP2_FW_CFG_TARG""" menuitem "DSP2_FW_L2_NOC_CFG" "per , ""DSP2_FW_L2_NOC_CFG""" menuitem "DSP2_MMU0" "per , ""DSP2_MMU0""" menuitem "DSP2_MMU1" "per , ""DSP2_MMU1""" menuitem "DSP2_PRM" "per , ""DSP2_PRM""" menuitem "DSP2_SDMA_FW" "per , ""DSP2_SDMA_FW""" menuitem "DSP2_SDMA_TARG" "per , ""DSP2_SDMA_TARG""" menuitem "DSP2_SYSTEM" "per , ""DSP2_SYSTEM""" menuitem "DSP_EDMA_TPCC" "per , ""DSP_EDMA_TPCC""" menuitem "DSP_EDMA_TPTC0" "per , ""DSP_EDMA_TPTC0""" menuitem "DSP_EDMA_TPTC1" "per , ""DSP_EDMA_TPTC1""" menuitem "DSP_FW_L2_NOC_CFG" "per , ""DSP_FW_L2_NOC_CFG""" menuitem "DSP_SYSTEM" "per , ""DSP_SYSTEM""" menuitem "DSS" "per , ""DSS""" menuitem "DSS_CM_CORE" "per , ""DSS_CM_CORE""" menuitem "DSS_FW" "per , ""DSS_FW""" menuitem "DSS_FW_CFG_TARG" "per , ""DSS_FW_CFG_TARG""" menuitem "DSS_PRM" "per , ""DSS_PRM""" menuitem "DSS_TARG" "per , ""DSS_TARG""" menuitem "EDMA_TC0_FW_CFG_TARG" "per , ""EDMA_TC0_FW_CFG_TARG""" menuitem "EDMA_TPCC_FW" "per , ""EDMA_TPCC_FW""" menuitem "EDMA_TPCC_FW_CFG_TARG" "per , ""EDMA_TPCC_FW_CFG_TARG""" menuitem "EDMA_TPCC_TARG" "per , ""EDMA_TPCC_TARG""" menuitem "ELM" "per , ""ELM""" menuitem "ELM_TARG" "per , ""ELM_TARG""" menuitem "EMIF" "per , ""EMIF""" menuitem "EMIF_FW" "per , ""EMIF_FW""" menuitem "EMIF_FW_CFG_TARG" "per , ""EMIF_FW_CFG_TARG""" menuitem "EMIF_P1_TARG" "per , ""EMIF_P1_TARG""" menuitem "EMU_CM" "per , ""EMU_CM""" menuitem "EMU_PRM" "per , ""EMU_PRM""" menuitem "ESM" "per , ""ESM""" menuitem "ESM_TARG" "per , ""ESM_TARG""" menuitem "EVE" "per , ""EVE""" menuitem "EVE1_CM_CORE_AON" "per , ""EVE1_CM_CORE_AON""" menuitem "EVE1_PRM" "per , ""EVE1_PRM""" menuitem "EVE2_CM_CORE_AON" "per , ""EVE2_CM_CORE_AON""" menuitem "EVE2_PRM" "per , ""EVE2_PRM""" menuitem "EVE3_CM_CORE_AON" "per , ""EVE3_CM_CORE_AON""" menuitem "EVE3_PRM" "per , ""EVE3_PRM""" menuitem "EVE4_CM_CORE_AON" "per , ""EVE4_CM_CORE_AON""" menuitem "EVE4_PRM" "per , ""EVE4_PRM""" menuitem "EVE_DSP" "per , ""EVE_DSP""" menuitem "EVE_EDMA_TPCC" "per , ""EVE_EDMA_TPCC""" menuitem "EVE_EDMA_TPTC0" "per , ""EVE_EDMA_TPTC0""" menuitem "EVE_EDMA_TPTC1" "per , ""EVE_EDMA_TPTC1""" menuitem "EVE_FW" "per , ""EVE_FW""" menuitem "EVE_FW_CFG_TARG" "per , ""EVE_FW_CFG_TARG""" menuitem "EVE_L2_FNOC" "per , ""EVE_L2_FNOC""" menuitem "EVE_MMU0" "per , ""EVE_MMU0""" menuitem "EVE_MMU1" "per , ""EVE_MMU1""" menuitem "EVE_SCTM" "per , ""EVE_SCTM""" menuitem "EVE_SMSET" "per , ""EVE_SMSET""" menuitem "EVE_TARG" "per , ""EVE_TARG""" menuitem "EVE_VCOP" "per , ""EVE_VCOP""" menuitem "GMAC_SW_TARG" "per , ""GMAC_SW_TARG""" menuitem "GPIO1" "per , ""GPIO1""" menuitem "GPIO2" "per , ""GPIO2""" menuitem "GPIO3" "per , ""GPIO3""" menuitem "GPIO4" "per , ""GPIO4""" menuitem "GPIO1_TARG" "per , ""GPIO1_TARG""" menuitem "GPIO2_TARG" "per , ""GPIO2_TARG""" menuitem "GPIO3_TARG" "per , ""GPIO3_TARG""" menuitem "GPIO4_TARG" "per , ""GPIO4_TARG""" menuitem "GPMC" "per , ""GPMC""" menuitem "GPMC_FW" "per , ""GPMC_FW""" menuitem "GPMC_FW_CFG_TARG" "per , ""GPMC_FW_CFG_TARG""" menuitem "GPMC_TARG" "per , ""GPMC_TARG""" menuitem "GPU_CM_CORE" "per , ""GPU_CM_CORE""" menuitem "GPU_PRM" "per , ""GPU_PRM""" menuitem "HWSEQ" "per , ""HWSEQ""" menuitem "I2C1" "per , ""I2C1""" menuitem "I2C2" "per , ""I2C2""" menuitem "I2C1_TARG" "per , ""I2C1_TARG""" menuitem "I2C2_TARG" "per , ""I2C2_TARG""" menuitem "IEEE1500_2_OCP_TARG" "per , ""IEEE1500_2_OCP_TARG""" menuitem "INSTR_CM_CORE_AON" "per , ""INSTR_CM_CORE_AON""" menuitem "INSTR_PRM" "per , ""INSTR_PRM""" menuitem "IPU_C0_RW_TABLE" "per , ""IPU_C0_RW_TABLE""" menuitem "IPU_C1_RW_TABLE" "per , ""IPU_C1_RW_TABLE""" menuitem "IPU_CM_CORE_AON" "per , ""IPU_CM_CORE_AON""" menuitem "IPU_FW" "per , ""IPU_FW""" menuitem "IPU_FW_CFG_TARG" "per , ""IPU_FW_CFG_TARG""" menuitem "IPU_MMU" "per , ""IPU_MMU""" menuitem "IPU_PRM" "per , ""IPU_PRM""" menuitem "IPU_TARG" "per , ""IPU_TARG""" menuitem "IPU_UNICACHE_CFG" "per , ""IPU_UNICACHE_CFG""" menuitem "IPU_UNICACHE_MMU" "per , ""IPU_UNICACHE_MMU""" menuitem "IPU_UNICACHE_SCTM" "per , ""IPU_UNICACHE_SCTM""" menuitem "IPU_WUGEN" "per , ""IPU_WUGEN""" menuitem "ISP6P5_CNF1" "per , ""ISP6P5_CNF1""" menuitem "ISP6P5_GLBCE" "per , ""ISP6P5_GLBCE""" menuitem "ISP6P5_H3A" "per , ""ISP6P5_H3A""" menuitem "ISP6P5_IPIPE" "per , ""ISP6P5_IPIPE""" menuitem "ISP6P5_IPIPEIF" "per , ""ISP6P5_IPIPEIF""" menuitem "ISP6P5_ISIF" "per , ""ISP6P5_ISIF""" menuitem "ISP6P5_NSF3V" "per , ""ISP6P5_NSF3V""" menuitem "ISP6P5_RESIZER" "per , ""ISP6P5_RESIZER""" menuitem "ISP6P5_SYS1" "per , ""ISP6P5_SYS1""" menuitem "ISP6P5_SYS2" "per , ""ISP6P5_SYS2""" menuitem "ISP6P5_SYS3" "per , ""ISP6P5_SYS3""" menuitem "ISS_CM_CORE_AON" "per , ""ISS_CM_CORE_AON""" menuitem "ISS_CTSET" "per , ""ISS_CTSET""" menuitem "ISS_FW" "per , ""ISS_FW""" menuitem "ISS_FW_CFG_TARG" "per , ""ISS_FW_CFG_TARG""" menuitem "ISS_PRM" "per , ""ISS_PRM""" menuitem "ISS_TARG" "per , ""ISS_TARG""" menuitem "ISS_TCTRL" "per , ""ISS_TCTRL""" menuitem "ISS_TOP" "per , ""ISS_TOP""" menuitem "IVA_CM_CORE" "per , ""IVA_CM_CORE""" menuitem "IVA_PRM" "per , ""IVA_PRM""" menuitem "L3_INSTR" "per , ""L3_INSTR""" menuitem "L3_INSTR_FW" "per , ""L3_INSTR_FW""" menuitem "L3_INSTR_FW_CFG_TARG" "per , ""L3_INSTR_FW_CFG_TARG""" menuitem "L3INIT_CM_CORE" "per , ""L3INIT_CM_CORE""" menuitem "L3INIT_PRM" "per , ""L3INIT_PRM""" menuitem "L4_CFG_AP" "per , ""L4_CFG_AP""" menuitem "L4_CFG_IA_IP0" "per , ""L4_CFG_IA_IP0""" menuitem "L4_CFG_LA" "per , ""L4_CFG_LA""" menuitem "L4_CFG_TARG" "per , ""L4_CFG_TARG""" menuitem "L4_PER1_AP" "per , ""L4_PER1_AP""" menuitem "L4_PER1_IA_IP0" "per , ""L4_PER1_IA_IP0""" menuitem "L4_PER1_IA_IP1" "per , ""L4_PER1_IA_IP1""" menuitem "L4_PER1_LA" "per , ""L4_PER1_LA""" menuitem "L4_PER1_P1_TARG" "per , ""L4_PER1_P1_TARG""" menuitem "L4_PER1_P2_TARG" "per , ""L4_PER1_P2_TARG""" menuitem "L4_PER2_AP" "per , ""L4_PER2_AP""" menuitem "L4_PER2_IA_IP0" "per , ""L4_PER2_IA_IP0""" menuitem "L4_PER2_LA" "per , ""L4_PER2_LA""" menuitem "L4_PER2_P1_TARG" "per , ""L4_PER2_P1_TARG""" menuitem "L4_PER3_AP" "per , ""L4_PER3_AP""" menuitem "L4_PER3_IA_IP1" "per , ""L4_PER3_IA_IP1""" menuitem "L4_PER3_IA_IP2" "per , ""L4_PER3_IA_IP2""" menuitem "L4_PER3_LA" "per , ""L4_PER3_LA""" menuitem "L4_PER3_P1_TARG" "per , ""L4_PER3_P1_TARG""" menuitem "L4_PER3_P2_TARG" "per , ""L4_PER3_P2_TARG""" menuitem "L4_WKUP_AP" "per , ""L4_WKUP_AP""" menuitem "L4_WKUP_COUNTER_32K" "per , ""L4_WKUP_COUNTER_32K""" menuitem "L4_WKUP_IA_IP0" "per , ""L4_WKUP_IA_IP0""" menuitem "L4_WKUP_LA" "per , ""L4_WKUP_LA""" menuitem "L4_WKUP_TARG" "per , ""L4_WKUP_TARG""" menuitem "L4PER_CM_CORE" "per , ""L4PER_CM_CORE""" menuitem "L4PER_PRM" "per , ""L4PER_PRM""" menuitem "LDC" "per , ""LDC""" menuitem "LVDSRX" "per , ""LVDSRX""" menuitem "MAILBOX1_TARG" "per , ""MAILBOX1_TARG""" menuitem "MAILBOX2_TARG" "per , ""MAILBOX2_TARG""" menuitem "MCAN" "per , ""MCAN""" menuitem "MCAN_TARG" "per , ""MCAN_TARG""" menuitem "MCASP1_AFIFO" "per , ""MCASP1_AFIFO""" menuitem "MCASP1_CFG" "per , ""MCASP1_CFG""" menuitem "MCASP1_DAT" "per , ""MCASP1_DAT""" menuitem "MCASP1_FW" "per , ""MCASP1_FW""" menuitem "MCASP1_FW_CFG_TARG" "per , ""MCASP1_FW_CFG_TARG""" menuitem "MCASP1_TARG" "per , ""MCASP1_TARG""" menuitem "MCASP2_AFIFO" "per , ""MCASP2_AFIFO""" menuitem "MCASP2_CFG" "per , ""MCASP2_CFG""" menuitem "MCASP2_DAT" "per , ""MCASP2_DAT""" menuitem "MCASP3_AFIFO" "per , ""MCASP3_AFIFO""" menuitem "MCASP3_CFG" "per , ""MCASP3_CFG""" menuitem "MCASP3_DAT" "per , ""MCASP3_DAT""" menuitem "MCASP_CFG_TARG" "per , ""MCASP_CFG_TARG""" menuitem "MCRC" "per , ""MCRC""" menuitem "MCSPI2" "per , ""MCSPI2""" menuitem "MCSPI3" "per , ""MCSPI3""" menuitem "MCSPI1" "per , ""MCSPI1""" menuitem "MCSPI1_TARG" "per , ""MCSPI1_TARG""" menuitem "MCSPI2_TARG" "per , ""MCSPI2_TARG""" menuitem "MCSPI3_TARG" "per , ""MCSPI3_TARG""" menuitem "MCSPI4" "per , ""MCSPI4""" menuitem "MCSPI4_TARG" "per , ""MCSPI4_TARG""" menuitem "MDIO" "per , ""MDIO""" menuitem "MMC" "per , ""MMC""" menuitem "MMC_TARG" "per , ""MMC_TARG""" menuitem "MMU_TARG" "per , ""MMU_TARG""" menuitem "MMU_TARG" "per , ""MMU_TARG""" menuitem "MPU_CM_CORE_AON" "per , ""MPU_CM_CORE_AON""" menuitem "MPU_PRM" "per , ""MPU_PRM""" menuitem "OCMC_RAM" "per , ""OCMC_RAM""" menuitem "OCMC_RAM_CFG_TARG" "per , ""OCMC_RAM_CFG_TARG""" menuitem "OCMC_RAM_FW" "per , ""OCMC_RAM_FW""" menuitem "OCMC_RAM_FW_CFG_TARG" "per , ""OCMC_RAM_FW_CFG_TARG""" menuitem "OCMC_RAM_TARG" "per , ""OCMC_RAM_TARG""" menuitem "OCP_SOCKET_CM_CORE" "per , ""OCP_SOCKET_CM_CORE""" menuitem "OCP_SOCKET_CM_CORE_AON" "per , ""OCP_SOCKET_CM_CORE_AON""" menuitem "OCP_SOCKET_PRM" "per , ""OCP_SOCKET_PRM""" menuitem "OCP_WP_NOC_TARG" "per , ""OCP_WP_NOC_TARG""" menuitem "PORT" "per , ""PORT""" menuitem "PRM_TARG" "per , ""PRM_TARG""" menuitem "PWMSS_CFG" "per , ""PWMSS_CFG""" menuitem "PWMSS_ECAP" "per , ""PWMSS_ECAP""" menuitem "PWMSS_EPWM" "per , ""PWMSS_EPWM""" menuitem "PWMSS_EQEP" "per , ""PWMSS_EQEP""" menuitem "PWMSS_TARG" "per , ""PWMSS_TARG""" menuitem "QSPI" "per , ""QSPI""" menuitem "QSPI_FW" "per , ""QSPI_FW""" menuitem "QSPI_FW_CFG_TARG" "per , ""QSPI_FW_CFG_TARG""" menuitem "QSPI_TARG" "per , ""QSPI_TARG""" menuitem "RESTORE_CM_CORE" "per , ""RESTORE_CM_CORE""" menuitem "RESTORE_CM_CORE_AON" "per , ""RESTORE_CM_CORE_AON""" menuitem "RTC_CM_CORE_AON" "per , ""RTC_CM_CORE_AON""" menuitem "RTC_PRM" "per , ""RTC_PRM""" menuitem "RTI1" "per , ""RTI1""" menuitem "RTI2" "per , ""RTI2""" menuitem "RTI3" "per , ""RTI3""" menuitem "RTI4" "per , ""RTI4""" menuitem "RTI5" "per , ""RTI5""" menuitem "RTI1_TARG" "per , ""RTI1_TARG""" menuitem "RTI2_TARG" "per , ""RTI2_TARG""" menuitem "RTI3_TARG" "per , ""RTI3_TARG""" menuitem "RTI4_TARG" "per , ""RTI4_TARG""" menuitem "RTI5_TARG" "per , ""RTI5_TARG""" menuitem "SIMCOP" "per , ""SIMCOP""" menuitem "SL1" "per , ""SL1""" menuitem "SL2" "per , ""SL2""" menuitem "SMARTREFLEX_CORE" "per , ""SMARTREFLEX_CORE""" menuitem "SMARTREFLEX_DSPEVE" "per , ""SMARTREFLEX_DSPEVE""" menuitem "SPF1" "per , ""SPF1""" menuitem "SPF2" "per , ""SPF2""" menuitem "Spinlock" "per , ""Spinlock""" menuitem "SPINLOCK_TARG" "per , ""SPINLOCK_TARG""" menuitem "SS" "per , ""SS""" menuitem "STATERAM" "per , ""STATERAM""" menuitem "STATS" "per , ""STATS""" menuitem "SYS_EDMA_TPCC" "per , ""SYS_EDMA_TPCC""" menuitem "SYS_EDMA_TPTC0" "per , ""SYS_EDMA_TPTC0""" menuitem "SYS_EDMA_TPTC1" "per , ""SYS_EDMA_TPTC1""" menuitem "System_MMU" "per , ""System_MMU""" menuitem "TESOC" "per , ""TESOC""" menuitem "TESOC_FW" "per , ""TESOC_FW""" menuitem "TESOC_FW_CFG_TARG" "per , ""TESOC_FW_CFG_TARG""" menuitem "TESOC_TARG" "per , ""TESOC_TARG""" menuitem "TIMER1_L4_WKUPInterconnect" "per , ""TIMER1_L4_WKUPInterconnect""" menuitem "TIMER1_TARG" "per , ""TIMER1_TARG""" menuitem "TIMER2_L4_PER1Interconnect" "per , ""TIMER2_L4_PER1Interconnect""" menuitem "TIMER2_TARG" "per , ""TIMER2_TARG""" menuitem "TIMER3_L4_PER1Interconnect" "per , ""TIMER3_L4_PER1Interconnect""" menuitem "TIMER3_TARG" "per , ""TIMER3_TARG""" menuitem "TIMER4_L4_PER1Interconnect" "per , ""TIMER4_L4_PER1Interconnect""" menuitem "TIMER4_TARG" "per , ""TIMER4_TARG""" menuitem "TIMER5_L4_PER3Interconnect" "per , ""TIMER5_L4_PER3Interconnect""" menuitem "TIMER5_TARG" "per , ""TIMER5_TARG""" menuitem "TIMER6_L4_PER3Interconnect" "per , ""TIMER6_L4_PER3Interconnect""" menuitem "TIMER6_TARG" "per , ""TIMER6_TARG""" menuitem "TIMER7_L4_PER3Interconnect" "per , ""TIMER7_L4_PER3Interconnect""" menuitem "TIMER7_TARG" "per , ""TIMER7_TARG""" menuitem "TIMER8_L4_PER3Interconnect" "per , ""TIMER8_L4_PER3Interconnect""" menuitem "TIMER8_TARG" "per , ""TIMER8_TARG""" menuitem "TPTC1_TARG" "per , ""TPTC1_TARG""" menuitem "TPTC2_TARG" "per , ""TPTC2_TARG""" menuitem "TPTC_FW" "per , ""TPTC_FW""" menuitem "TSC_ADC_CFG_TARG" "per , ""TSC_ADC_CFG_TARG""" menuitem "TSC_ADC_FW_CFG_TARG" "per , ""TSC_ADC_FW_CFG_TARG""" menuitem "UART1" "per , ""UART1""" menuitem "UART2" "per , ""UART2""" menuitem "UART3" "per , ""UART3""" menuitem "UART1_TARG" "per , ""UART1_TARG""" menuitem "UART2_TARG" "per , ""UART2_TARG""" menuitem "UART3_TARG" "per , ""UART3_TARG""" menuitem "VENC" "per , ""VENC""" menuitem "VIP_Slice0_csc" "per , ""VIP_Slice0_csc""" menuitem "VIP_Slice0_parser" "per , ""VIP_Slice0_parser""" menuitem "VIP_Slice0_sc" "per , ""VIP_Slice0_sc""" menuitem "VIP_Slice1_csc" "per , ""VIP_Slice1_csc""" menuitem "VIP_Slice1_parser" "per , ""VIP_Slice1_parser""" menuitem "VIP_Slice1_sc" "per , ""VIP_Slice1_sc""" menuitem "VIP_TARG" "per , ""VIP_TARG""" menuitem "VIP_top_level" "per , ""VIP_top_level""" menuitem "VIP_VPDMA" "per , ""VIP_VPDMA""" menuitem "VTNF" "per , ""VTNF""" menuitem "WKUPAON_CM" "per , ""WKUPAON_CM""" menuitem "WKUPAON_PRM" "per , ""WKUPAON_PRM""" menuitem "WR" "per , ""WR""" ) if (cpuis("TDA3XDSP*")) ( menuitem "ADC" "per , ""ADC""" menuitem "ALE" "per , ""ALE""" menuitem "CAM_CM_CORE" "per , ""CAM_CM_CORE""" menuitem "CAM_PRM" "per , ""CAM_PRM""" menuitem "CKGEN_CM_CORE" "per , ""CKGEN_CM_CORE""" menuitem "CKGEN_CM_CORE_AON" "per , ""CKGEN_CM_CORE_AON""" menuitem "CKGEN_PRM" "per , ""CKGEN_PRM""" menuitem "CLK1_DSP1_EDMA_BW_LIMITER" "per , ""CLK1_DSP1_EDMA_BW_LIMITER""" menuitem "CLK1_DSP1_MDMA_BW_LIMITER" "per , ""CLK1_DSP1_MDMA_BW_LIMITER""" menuitem "CLK1_DSP1_MDMA_BW_REGULATOR" "per , ""CLK1_DSP1_MDMA_BW_REGULATOR""" menuitem "CLK1_DSP2_EDMA_BW_LIMITER" "per , ""CLK1_DSP2_EDMA_BW_LIMITER""" menuitem "CLK1_DSP2_MDMA_BW_LIMITER" "per , ""CLK1_DSP2_MDMA_BW_LIMITER""" menuitem "CLK1_DSP2_MDMA_BW_REGULATOR" "per , ""CLK1_DSP2_MDMA_BW_REGULATOR""" menuitem "CLK1_EVE_TC0_BW_LIMITER" "per , ""CLK1_EVE_TC0_BW_LIMITER""" menuitem "CLK1_EVE_TC0_BW_REGULATOR" "per , ""CLK1_EVE_TC0_BW_REGULATOR""" menuitem "CLK1_EVE_TC1_BW_LIMITER" "per , ""CLK1_EVE_TC1_BW_LIMITER""" menuitem "CLK1_EVE_TC1_BW_REGULATOR" "per , ""CLK1_EVE_TC1_BW_REGULATOR""" menuitem "CLK1_FLAGMUX_CLK1" "per , ""CLK1_FLAGMUX_CLK1""" menuitem "CLK1_FLAGMUX_CLK1_1" "per , ""CLK1_FLAGMUX_CLK1_1""" menuitem "CLK1_FLAGMUX_CLK1_2" "per , ""CLK1_FLAGMUX_CLK1_2""" menuitem "CLK1_FLAGMUX_CLK1MERGE" "per , ""CLK1_FLAGMUX_CLK1MERGE""" menuitem "CLK1_GMAC_SW_BW_REGULATOR" "per , ""CLK1_GMAC_SW_BW_REGULATOR""" menuitem "CLK1_HOST_CLK1_1" "per , ""CLK1_HOST_CLK1_1""" menuitem "CLK1_HOST_CLK1_2" "per , ""CLK1_HOST_CLK1_2""" menuitem "CLK1_IPU_BW_LIMITER" "per , ""CLK1_IPU_BW_LIMITER""" menuitem "CLK1_IPU_BW_REGULATOR" "per , ""CLK1_IPU_BW_REGULATOR""" menuitem "CLK1_ISS_NRT1_BW_LIMITER" "per , ""CLK1_ISS_NRT1_BW_LIMITER""" menuitem "CLK1_ISS_NRT2_BW_LIMITER" "per , ""CLK1_ISS_NRT2_BW_LIMITER""" menuitem "CLK1_MMU_BW_LIMITER" "per , ""CLK1_MMU_BW_LIMITER""" menuitem "CLK1_TPTC1_RD_BW_LIMITER" "per , ""CLK1_TPTC1_RD_BW_LIMITER""" menuitem "CLK1_TPTC1_WR_BW_LIMITER" "per , ""CLK1_TPTC1_WR_BW_LIMITER""" menuitem "CLK1_TPTC2_RD_BW_LIMITER" "per , ""CLK1_TPTC2_RD_BW_LIMITER""" menuitem "CLK1_TPTC2_WR_BW_LIMITER" "per , ""CLK1_TPTC2_WR_BW_LIMITER""" menuitem "CLK2_FLAGMUX_CLK2" "per , ""CLK2_FLAGMUX_CLK2""" menuitem "CLK2_FLAGMUX_CLK2_1" "per , ""CLK2_FLAGMUX_CLK2_1""" menuitem "CLK2_FLAGMUX_STATCOLL" "per , ""CLK2_FLAGMUX_STATCOLL""" menuitem "CLK2_HOST_CLK2_1" "per , ""CLK2_HOST_CLK2_1""" menuitem "CLK2_STATCOLL1" "per , ""CLK2_STATCOLL1""" menuitem "CLK2_STATCOLL2" "per , ""CLK2_STATCOLL2""" menuitem "CLK2_STATCOLL3" "per , ""CLK2_STATCOLL3""" menuitem "CLK2_STATCOLL4" "per , ""CLK2_STATCOLL4""" menuitem "CM_CORE_AON_TARG" "per , ""CM_CORE_AON_TARG""" menuitem "CM_CORE_TARG" "per , ""CM_CORE_TARG""" menuitem "CORE_CM_CORE" "per , ""CORE_CM_CORE""" menuitem "CORE_PRM" "per , ""CORE_PRM""" menuitem "COREAON_CM_CORE" "per , ""COREAON_CM_CORE""" menuitem "COREAON_PRM" "per , ""COREAON_PRM""" menuitem "COUNTER_32K_TARG" "per , ""COUNTER_32K_TARG""" menuitem "CPDMA" "per , ""CPDMA""" menuitem "CPTS" "per , ""CPTS""" menuitem "CRC_CFG_TARG" "per , ""CRC_CFG_TARG""" menuitem "CRC_FW" "per , ""CRC_FW""" menuitem "CRC_FW_CFG_TARG" "per , ""CRC_FW_CFG_TARG""" menuitem "CRC_TARG" "per , ""CRC_TARG""" menuitem "CTRL_MODULE_CORE" "per , ""CTRL_MODULE_CORE""" menuitem "CTRL_MODULE_CORE_TARG" "per , ""CTRL_MODULE_CORE_TARG""" menuitem "CTRL_MODULE_WKUP" "per , ""CTRL_MODULE_WKUP""" menuitem "CTRL_MODULE_WKUP_TARG" "per , ""CTRL_MODULE_WKUP_TARG""" menuitem "CUSTEFUSE_CM_CORE" "per , ""CUSTEFUSE_CM_CORE""" menuitem "CUSTEFUSE_PRM" "per , ""CUSTEFUSE_PRM""" menuitem "DCAN1" "per , ""DCAN1""" menuitem "DCAN2" "per , ""DCAN2""" menuitem "DCAN1_TARG" "per , ""DCAN1_TARG""" menuitem "DCAN2_TARG" "per , ""DCAN2_TARG""" menuitem "DCC1" "per , ""DCC1""" menuitem "DCC2" "per , ""DCC2""" menuitem "DCC3" "per , ""DCC3""" menuitem "DCC4" "per , ""DCC4""" menuitem "DCC5" "per , ""DCC5""" menuitem "DCC6" "per , ""DCC6""" menuitem "DCC7" "per , ""DCC7""" menuitem "DCC1_SR2" "per , ""DCC1_SR2""" menuitem "DCC1_TARG" "per , ""DCC1_TARG""" menuitem "DCC1_TARG_SR2" "per , ""DCC1_TARG_SR2""" menuitem "DCC2_SR2" "per , ""DCC2_SR2""" menuitem "DCC2_TARG" "per , ""DCC2_TARG""" menuitem "DCC2_TARG_SR2" "per , ""DCC2_TARG_SR2""" menuitem "DCC3_SR2" "per , ""DCC3_SR2""" menuitem "DCC3_TARG" "per , ""DCC3_TARG""" menuitem "DCC3_TARG_SR2" "per , ""DCC3_TARG_SR2""" menuitem "DCC4_SR2" "per , ""DCC4_SR2""" menuitem "DCC4_TARG" "per , ""DCC4_TARG""" menuitem "DCC4_TARG_SR2" "per , ""DCC4_TARG_SR2""" menuitem "DCC5_SR2" "per , ""DCC5_SR2""" menuitem "DCC5_TARG" "per , ""DCC5_TARG""" menuitem "DCC5_TARG_SR2" "per , ""DCC5_TARG_SR2""" menuitem "DCC6_SR2" "per , ""DCC6_SR2""" menuitem "DCC6_TARG" "per , ""DCC6_TARG""" menuitem "DCC6_TARG_SR2" "per , ""DCC6_TARG_SR2""" menuitem "DCC7_SR2" "per , ""DCC7_SR2""" menuitem "DCC7_TARG" "per , ""DCC7_TARG""" menuitem "DCC7_TARG_SR2" "per , ""DCC7_TARG_SR2""" menuitem "DEBUGSS_CT_TBR_FW" "per , ""DEBUGSS_CT_TBR_FW""" menuitem "DEBUGSS_CT_TBR_FW_CFG_TARG" "per , ""DEBUGSS_CT_TBR_FW_CFG_TARG""" menuitem "DEBUGSS_CT_TBR_TARG" "per , ""DEBUGSS_CT_TBR_TARG""" menuitem "DEVICE_PRM" "per , ""DEVICE_PRM""" menuitem "DISPC_COMMON" "per , ""DISPC_COMMON""" menuitem "DISPC_GFX1" "per , ""DISPC_GFX1""" menuitem "DISPC_OVR1" "per , ""DISPC_OVR1""" menuitem "DISPC_OVR2" "per , ""DISPC_OVR2""" menuitem "DISPC_VID1" "per , ""DISPC_VID1""" menuitem "DISPC_VID2" "per , ""DISPC_VID2""" menuitem "DISPC_VP1" "per , ""DISPC_VP1""" menuitem "DISPC_WB" "per , ""DISPC_WB""" menuitem "DRM" "per , ""DRM""" menuitem "DSP1_CM_CORE_AON" "per , ""DSP1_CM_CORE_AON""" menuitem "DSP1_EDMA_TPCC" "per , ""DSP1_EDMA_TPCC""" menuitem "DSP1_EDMA_TPTC0" "per , ""DSP1_EDMA_TPTC0""" menuitem "DSP1_EDMA_TPTC1" "per , ""DSP1_EDMA_TPTC1""" menuitem "DSP1_FW_CFG_TARG" "per , ""DSP1_FW_CFG_TARG""" menuitem "DSP1_FW_L2_NOC_CFG" "per , ""DSP1_FW_L2_NOC_CFG""" menuitem "DSP1_MMU0" "per , ""DSP1_MMU0""" menuitem "DSP1_MMU1" "per , ""DSP1_MMU1""" menuitem "DSP1_PRM" "per , ""DSP1_PRM""" menuitem "DSP1_SDMA_FW" "per , ""DSP1_SDMA_FW""" menuitem "DSP1_SDMA_TARG" "per , ""DSP1_SDMA_TARG""" menuitem "DSP1_SYSTEM" "per , ""DSP1_SYSTEM""" menuitem "DSP2_CM_CORE_AON" "per , ""DSP2_CM_CORE_AON""" menuitem "DSP2_EDMA_TPCC" "per , ""DSP2_EDMA_TPCC""" menuitem "DSP2_EDMA_TPTC0" "per , ""DSP2_EDMA_TPTC0""" menuitem "DSP2_EDMA_TPTC1" "per , ""DSP2_EDMA_TPTC1""" menuitem "DSP2_FW_CFG_TARG" "per , ""DSP2_FW_CFG_TARG""" menuitem "DSP2_FW_L2_NOC_CFG" "per , ""DSP2_FW_L2_NOC_CFG""" menuitem "DSP2_MMU0" "per , ""DSP2_MMU0""" menuitem "DSP2_MMU1" "per , ""DSP2_MMU1""" menuitem "DSP2_PRM" "per , ""DSP2_PRM""" menuitem "DSP2_SDMA_FW" "per , ""DSP2_SDMA_FW""" menuitem "DSP2_SDMA_TARG" "per , ""DSP2_SDMA_TARG""" menuitem "DSP2_SYSTEM" "per , ""DSP2_SYSTEM""" menuitem "DSP_EDMA_TPCC" "per , ""DSP_EDMA_TPCC""" menuitem "DSP_EDMA_TPTC0" "per , ""DSP_EDMA_TPTC0""" menuitem "DSP_EDMA_TPTC1" "per , ""DSP_EDMA_TPTC1""" menuitem "DSP_FW_L2_NOC_CFG" "per , ""DSP_FW_L2_NOC_CFG""" menuitem "DSP_SYSTEM" "per , ""DSP_SYSTEM""" menuitem "DSS" "per , ""DSS""" menuitem "DSS_CM_CORE" "per , ""DSS_CM_CORE""" menuitem "DSS_FW" "per , ""DSS_FW""" menuitem "DSS_FW_CFG_TARG" "per , ""DSS_FW_CFG_TARG""" menuitem "DSS_PRM" "per , ""DSS_PRM""" menuitem "DSS_TARG" "per , ""DSS_TARG""" menuitem "EDMA_TC0_FW_CFG_TARG" "per , ""EDMA_TC0_FW_CFG_TARG""" menuitem "EDMA_TPCC_FW" "per , ""EDMA_TPCC_FW""" menuitem "EDMA_TPCC_FW_CFG_TARG" "per , ""EDMA_TPCC_FW_CFG_TARG""" menuitem "EDMA_TPCC_TARG" "per , ""EDMA_TPCC_TARG""" menuitem "ELM" "per , ""ELM""" menuitem "ELM_TARG" "per , ""ELM_TARG""" menuitem "EMIF" "per , ""EMIF""" menuitem "EMIF_FW" "per , ""EMIF_FW""" menuitem "EMIF_FW_CFG_TARG" "per , ""EMIF_FW_CFG_TARG""" menuitem "EMIF_P1_TARG" "per , ""EMIF_P1_TARG""" menuitem "EMU_CM" "per , ""EMU_CM""" menuitem "EMU_PRM" "per , ""EMU_PRM""" menuitem "ESM" "per , ""ESM""" menuitem "ESM_TARG" "per , ""ESM_TARG""" menuitem "EVE" "per , ""EVE""" menuitem "EVE1_CM_CORE_AON" "per , ""EVE1_CM_CORE_AON""" menuitem "EVE1_PRM" "per , ""EVE1_PRM""" menuitem "EVE2_CM_CORE_AON" "per , ""EVE2_CM_CORE_AON""" menuitem "EVE2_PRM" "per , ""EVE2_PRM""" menuitem "EVE3_CM_CORE_AON" "per , ""EVE3_CM_CORE_AON""" menuitem "EVE3_PRM" "per , ""EVE3_PRM""" menuitem "EVE4_CM_CORE_AON" "per , ""EVE4_CM_CORE_AON""" menuitem "EVE4_PRM" "per , ""EVE4_PRM""" menuitem "EVE_DSP" "per , ""EVE_DSP""" menuitem "EVE_EDMA_TPCC" "per , ""EVE_EDMA_TPCC""" menuitem "EVE_EDMA_TPTC0" "per , ""EVE_EDMA_TPTC0""" menuitem "EVE_EDMA_TPTC1" "per , ""EVE_EDMA_TPTC1""" menuitem "EVE_FW" "per , ""EVE_FW""" menuitem "EVE_FW_CFG_TARG" "per , ""EVE_FW_CFG_TARG""" menuitem "EVE_L2_FNOC" "per , ""EVE_L2_FNOC""" menuitem "EVE_MMU0" "per , ""EVE_MMU0""" menuitem "EVE_MMU1" "per , ""EVE_MMU1""" menuitem "EVE_SCTM" "per , ""EVE_SCTM""" menuitem "EVE_SMSET" "per , ""EVE_SMSET""" menuitem "EVE_TARG" "per , ""EVE_TARG""" menuitem "EVE_VCOP" "per , ""EVE_VCOP""" menuitem "GMAC_SW_TARG" "per , ""GMAC_SW_TARG""" menuitem "GPIO1" "per , ""GPIO1""" menuitem "GPIO2" "per , ""GPIO2""" menuitem "GPIO3" "per , ""GPIO3""" menuitem "GPIO4" "per , ""GPIO4""" menuitem "GPIO1_TARG" "per , ""GPIO1_TARG""" menuitem "GPIO2_TARG" "per , ""GPIO2_TARG""" menuitem "GPIO3_TARG" "per , ""GPIO3_TARG""" menuitem "GPIO4_TARG" "per , ""GPIO4_TARG""" menuitem "GPMC" "per , ""GPMC""" menuitem "GPMC_FW" "per , ""GPMC_FW""" menuitem "GPMC_FW_CFG_TARG" "per , ""GPMC_FW_CFG_TARG""" menuitem "GPMC_TARG" "per , ""GPMC_TARG""" menuitem "GPU_CM_CORE" "per , ""GPU_CM_CORE""" menuitem "GPU_PRM" "per , ""GPU_PRM""" menuitem "I2C1" "per , ""I2C1""" menuitem "I2C2" "per , ""I2C2""" menuitem "I2C1_TARG" "per , ""I2C1_TARG""" menuitem "I2C2_TARG" "per , ""I2C2_TARG""" menuitem "IEEE1500_2_OCP_TARG" "per , ""IEEE1500_2_OCP_TARG""" menuitem "INSTR_CM_CORE_AON" "per , ""INSTR_CM_CORE_AON""" menuitem "INSTR_PRM" "per , ""INSTR_PRM""" menuitem "IPU_C0_RW_TABLE" "per , ""IPU_C0_RW_TABLE""" menuitem "IPU_C1_RW_TABLE" "per , ""IPU_C1_RW_TABLE""" menuitem "IPU_CM_CORE_AON" "per , ""IPU_CM_CORE_AON""" menuitem "IPU_FW" "per , ""IPU_FW""" menuitem "IPU_FW_CFG_TARG" "per , ""IPU_FW_CFG_TARG""" menuitem "IPU_MMU" "per , ""IPU_MMU""" menuitem "IPU_PRM" "per , ""IPU_PRM""" menuitem "IPU_TARG" "per , ""IPU_TARG""" menuitem "IPU_UNICACHE_CFG" "per , ""IPU_UNICACHE_CFG""" menuitem "IPU_UNICACHE_MMU" "per , ""IPU_UNICACHE_MMU""" menuitem "IPU_UNICACHE_SCTM" "per , ""IPU_UNICACHE_SCTM""" menuitem "IPU_WUGEN" "per , ""IPU_WUGEN""" menuitem "ISS_CM_CORE_AON" "per , ""ISS_CM_CORE_AON""" menuitem "ISS_FW" "per , ""ISS_FW""" menuitem "ISS_FW_CFG_TARG" "per , ""ISS_FW_CFG_TARG""" menuitem "ISS_PRM" "per , ""ISS_PRM""" menuitem "ISS_TARG" "per , ""ISS_TARG""" menuitem "IVA_CM_CORE" "per , ""IVA_CM_CORE""" menuitem "IVA_PRM" "per , ""IVA_PRM""" menuitem "L3_INSTR" "per , ""L3_INSTR""" menuitem "L3_INSTR_FW" "per , ""L3_INSTR_FW""" menuitem "L3_INSTR_FW_CFG_TARG" "per , ""L3_INSTR_FW_CFG_TARG""" menuitem "L3INIT_CM_CORE" "per , ""L3INIT_CM_CORE""" menuitem "L3INIT_PRM" "per , ""L3INIT_PRM""" menuitem "L4_CFG_AP" "per , ""L4_CFG_AP""" menuitem "L4_CFG_IA_IP0" "per , ""L4_CFG_IA_IP0""" menuitem "L4_CFG_LA" "per , ""L4_CFG_LA""" menuitem "L4_CFG_TARG" "per , ""L4_CFG_TARG""" menuitem "L4_PER1_AP" "per , ""L4_PER1_AP""" menuitem "L4_PER1_IA_IP0" "per , ""L4_PER1_IA_IP0""" menuitem "L4_PER1_IA_IP1" "per , ""L4_PER1_IA_IP1""" menuitem "L4_PER1_LA" "per , ""L4_PER1_LA""" menuitem "L4_PER1_P1_TARG" "per , ""L4_PER1_P1_TARG""" menuitem "L4_PER1_P2_TARG" "per , ""L4_PER1_P2_TARG""" menuitem "L4_PER2_AP" "per , ""L4_PER2_AP""" menuitem "L4_PER2_IA_IP0" "per , ""L4_PER2_IA_IP0""" menuitem "L4_PER2_LA" "per , ""L4_PER2_LA""" menuitem "L4_PER2_P1_TARG" "per , ""L4_PER2_P1_TARG""" menuitem "L4_PER3_AP" "per , ""L4_PER3_AP""" menuitem "L4_PER3_IA_IP1" "per , ""L4_PER3_IA_IP1""" menuitem "L4_PER3_IA_IP2" "per , ""L4_PER3_IA_IP2""" menuitem "L4_PER3_LA" "per , ""L4_PER3_LA""" menuitem "L4_PER3_P1_TARG" "per , ""L4_PER3_P1_TARG""" menuitem "L4_PER3_P2_TARG" "per , ""L4_PER3_P2_TARG""" menuitem "L4_WKUP_AP" "per , ""L4_WKUP_AP""" menuitem "L4_WKUP_COUNTER_32K" "per , ""L4_WKUP_COUNTER_32K""" menuitem "L4_WKUP_IA_IP0" "per , ""L4_WKUP_IA_IP0""" menuitem "L4_WKUP_LA" "per , ""L4_WKUP_LA""" menuitem "L4_WKUP_TARG" "per , ""L4_WKUP_TARG""" menuitem "L4PER_CM_CORE" "per , ""L4PER_CM_CORE""" menuitem "L4PER_PRM" "per , ""L4PER_PRM""" menuitem "MAILBOX1_TARG" "per , ""MAILBOX1_TARG""" menuitem "MAILBOX2_TARG" "per , ""MAILBOX2_TARG""" menuitem "MCAN" "per , ""MCAN""" menuitem "MCAN_TARG" "per , ""MCAN_TARG""" menuitem "MCASP1_AFIFO" "per , ""MCASP1_AFIFO""" menuitem "MCASP1_CFG" "per , ""MCASP1_CFG""" menuitem "MCASP1_DAT" "per , ""MCASP1_DAT""" menuitem "MCASP1_FW" "per , ""MCASP1_FW""" menuitem "MCASP1_FW_CFG_TARG" "per , ""MCASP1_FW_CFG_TARG""" menuitem "MCASP1_TARG" "per , ""MCASP1_TARG""" menuitem "MCASP2_AFIFO" "per , ""MCASP2_AFIFO""" menuitem "MCASP2_CFG" "per , ""MCASP2_CFG""" menuitem "MCASP2_DAT" "per , ""MCASP2_DAT""" menuitem "MCASP3_AFIFO" "per , ""MCASP3_AFIFO""" menuitem "MCASP3_CFG" "per , ""MCASP3_CFG""" menuitem "MCASP3_DAT" "per , ""MCASP3_DAT""" menuitem "MCASP_CFG_TARG" "per , ""MCASP_CFG_TARG""" menuitem "MCRC" "per , ""MCRC""" menuitem "MCSPI2" "per , ""MCSPI2""" menuitem "MCSPI3" "per , ""MCSPI3""" menuitem "MCSPI1" "per , ""MCSPI1""" menuitem "MCSPI1_TARG" "per , ""MCSPI1_TARG""" menuitem "MCSPI2_TARG" "per , ""MCSPI2_TARG""" menuitem "MCSPI3_TARG" "per , ""MCSPI3_TARG""" menuitem "MCSPI4" "per , ""MCSPI4""" menuitem "MCSPI4_TARG" "per , ""MCSPI4_TARG""" menuitem "MDIO" "per , ""MDIO""" menuitem "MMC" "per , ""MMC""" menuitem "MMC_TARG" "per , ""MMC_TARG""" menuitem "MMU_TARG" "per , ""MMU_TARG""" menuitem "MMU_TARG" "per , ""MMU_TARG""" menuitem "MPU_CM_CORE_AON" "per , ""MPU_CM_CORE_AON""" menuitem "MPU_PRM" "per , ""MPU_PRM""" menuitem "OCMC_RAM" "per , ""OCMC_RAM""" menuitem "OCMC_RAM_CFG_TARG" "per , ""OCMC_RAM_CFG_TARG""" menuitem "OCMC_RAM_FW" "per , ""OCMC_RAM_FW""" menuitem "OCMC_RAM_FW_CFG_TARG" "per , ""OCMC_RAM_FW_CFG_TARG""" menuitem "OCMC_RAM_TARG" "per , ""OCMC_RAM_TARG""" menuitem "OCP_SOCKET_CM_CORE" "per , ""OCP_SOCKET_CM_CORE""" menuitem "OCP_SOCKET_CM_CORE_AON" "per , ""OCP_SOCKET_CM_CORE_AON""" menuitem "OCP_SOCKET_PRM" "per , ""OCP_SOCKET_PRM""" menuitem "OCP_WP_NOC_TARG" "per , ""OCP_WP_NOC_TARG""" menuitem "PORT" "per , ""PORT""" menuitem "PRM_TARG" "per , ""PRM_TARG""" menuitem "PWMSS_CFG" "per , ""PWMSS_CFG""" menuitem "PWMSS_ECAP" "per , ""PWMSS_ECAP""" menuitem "PWMSS_EPWM" "per , ""PWMSS_EPWM""" menuitem "PWMSS_EQEP" "per , ""PWMSS_EQEP""" menuitem "PWMSS_TARG" "per , ""PWMSS_TARG""" menuitem "QSPI" "per , ""QSPI""" menuitem "QSPI_FW" "per , ""QSPI_FW""" menuitem "QSPI_FW_CFG_TARG" "per , ""QSPI_FW_CFG_TARG""" menuitem "QSPI_TARG" "per , ""QSPI_TARG""" menuitem "RESTORE_CM_CORE" "per , ""RESTORE_CM_CORE""" menuitem "RESTORE_CM_CORE_AON" "per , ""RESTORE_CM_CORE_AON""" menuitem "RTC_CM_CORE_AON" "per , ""RTC_CM_CORE_AON""" menuitem "RTC_PRM" "per , ""RTC_PRM""" menuitem "RTI1" "per , ""RTI1""" menuitem "RTI2" "per , ""RTI2""" menuitem "RTI3" "per , ""RTI3""" menuitem "RTI4" "per , ""RTI4""" menuitem "RTI5" "per , ""RTI5""" menuitem "RTI1_TARG" "per , ""RTI1_TARG""" menuitem "RTI2_TARG" "per , ""RTI2_TARG""" menuitem "RTI3_TARG" "per , ""RTI3_TARG""" menuitem "RTI4_TARG" "per , ""RTI4_TARG""" menuitem "RTI5_TARG" "per , ""RTI5_TARG""" menuitem "SL1" "per , ""SL1""" menuitem "SL2" "per , ""SL2""" menuitem "SMARTREFLEX_CORE" "per , ""SMARTREFLEX_CORE""" menuitem "SMARTREFLEX_DSPEVE" "per , ""SMARTREFLEX_DSPEVE""" menuitem "SPF1" "per , ""SPF1""" menuitem "SPF2" "per , ""SPF2""" menuitem "Spinlock" "per , ""Spinlock""" menuitem "SPINLOCK_TARG" "per , ""SPINLOCK_TARG""" menuitem "SS" "per , ""SS""" menuitem "STATERAM" "per , ""STATERAM""" menuitem "STATS" "per , ""STATS""" menuitem "SYS_EDMA_TPCC" "per , ""SYS_EDMA_TPCC""" menuitem "SYS_EDMA_TPTC0" "per , ""SYS_EDMA_TPTC0""" menuitem "SYS_EDMA_TPTC1" "per , ""SYS_EDMA_TPTC1""" menuitem "System_MMU" "per , ""System_MMU""" menuitem "TESOC" "per , ""TESOC""" menuitem "TESOC_FW" "per , ""TESOC_FW""" menuitem "TESOC_FW_CFG_TARG" "per , ""TESOC_FW_CFG_TARG""" menuitem "TESOC_TARG" "per , ""TESOC_TARG""" menuitem "TIMER1_L4_WKUPInterconnect" "per , ""TIMER1_L4_WKUPInterconnect""" menuitem "TIMER1_TARG" "per , ""TIMER1_TARG""" menuitem "TIMER2_L4_PER1Interconnect" "per , ""TIMER2_L4_PER1Interconnect""" menuitem "TIMER2_TARG" "per , ""TIMER2_TARG""" menuitem "TIMER3_L4_PER1Interconnect" "per , ""TIMER3_L4_PER1Interconnect""" menuitem "TIMER3_TARG" "per , ""TIMER3_TARG""" menuitem "TIMER4_L4_PER1Interconnect" "per , ""TIMER4_L4_PER1Interconnect""" menuitem "TIMER4_TARG" "per , ""TIMER4_TARG""" menuitem "TIMER5_L4_PER3Interconnect" "per , ""TIMER5_L4_PER3Interconnect""" menuitem "TIMER5_TARG" "per , ""TIMER5_TARG""" menuitem "TIMER6_L4_PER3Interconnect" "per , ""TIMER6_L4_PER3Interconnect""" menuitem "TIMER6_TARG" "per , ""TIMER6_TARG""" menuitem "TIMER7_L4_PER3Interconnect" "per , ""TIMER7_L4_PER3Interconnect""" menuitem "TIMER7_TARG" "per , ""TIMER7_TARG""" menuitem "TIMER8_L4_PER3Interconnect" "per , ""TIMER8_L4_PER3Interconnect""" menuitem "TIMER8_TARG" "per , ""TIMER8_TARG""" menuitem "TPTC1_TARG" "per , ""TPTC1_TARG""" menuitem "TPTC2_TARG" "per , ""TPTC2_TARG""" menuitem "TPTC_FW" "per , ""TPTC_FW""" menuitem "TSC_ADC_CFG_TARG" "per , ""TSC_ADC_CFG_TARG""" menuitem "TSC_ADC_FW_CFG_TARG" "per , ""TSC_ADC_FW_CFG_TARG""" menuitem "UART1" "per , ""UART1""" menuitem "UART2" "per , ""UART2""" menuitem "UART3" "per , ""UART3""" menuitem "UART1_TARG" "per , ""UART1_TARG""" menuitem "UART2_TARG" "per , ""UART2_TARG""" menuitem "UART3_TARG" "per , ""UART3_TARG""" menuitem "VENC" "per , ""VENC""" menuitem "VIP_Slice0_csc" "per , ""VIP_Slice0_csc""" menuitem "VIP_Slice0_parser" "per , ""VIP_Slice0_parser""" menuitem "VIP_Slice0_sc" "per , ""VIP_Slice0_sc""" menuitem "VIP_Slice1_csc" "per , ""VIP_Slice1_csc""" menuitem "VIP_Slice1_parser" "per , ""VIP_Slice1_parser""" menuitem "VIP_Slice1_sc" "per , ""VIP_Slice1_sc""" menuitem "VIP_TARG" "per , ""VIP_TARG""" menuitem "VIP_top_level" "per , ""VIP_top_level""" menuitem "VIP_VPDMA" "per , ""VIP_VPDMA""" menuitem "WKUPAON_CM" "per , ""WKUPAON_CM""" menuitem "WKUPAON_PRM" "per , ""WKUPAON_PRM""" menuitem "WR" "per , ""WR""" ) ) )