; -------------------------------------------------------------------------------- ; @Title: RZN1 On-Chip Peripherals ; @Props: Released ; @Author: DRE, BCA, DPR ; @Changelog: 2018-09-24 DRE ; @Manufacturer: RENESAS - Renesas Technology, Corp. ; @Core: Cortex-A7, Cortex-M3 ; @Copyright: (C) 1989-2018 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: menrzn1.men 16339 2023-07-03 13:30:14Z pegold $ add menu ( IF SOFTWARE.BUILD.BASE()>=69655. ( popup "&CPU" ( separator IF CPU.FEATURE(MMU) ( popup "[:mmu]MMU" ( menuitem "[:mmureg]MMU Control" "MMU.view" separator menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable" menuitem "[:mmu]MMU Table List" "MMU.List.PageTable" separator IF CPU.FEATURE(ITLBDUMP) ( menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB" ) IF CPU.FEATURE(DTLBDUMP) ( menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB" ) IF CPU.FEATURE(TLB0DUMP) ( menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0" ) IF CPU.FEATURE(TLB1DUMP) ( menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1" ) ) ) IF COMPonent.AVAILable("SMMU") ( popup "[:mmu]SMMU" ( menuitem "[:chip]SMMU1 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU1 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.)) SMMU.StreamMapTable &(name) ) IF COMPonent.AVAILable("SMMU2") ( separator menuitem "[:chip]SMMU2 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU2 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU3") ( separator menuitem "[:chip]SMMU3 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU3 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU4") ( separator menuitem "[:chip]SMMU4 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU4 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU5") ( separator menuitem "[:chip]SMMU5 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU5 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU6") ( separator menuitem "[:chip]SMMU6 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU6 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.)) SMMU.StreamMapTable &(name) ) ) ) ) IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE) ( popup "[:cache]Cache" ( IF CPU.FEATURE(L1ICACHEDUMP) ( menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC" menuitem "[:cache]ICACHE List" "CACHE.List IC" menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC" ) IF CPU.FEATURE(L1DCACHEDUMP) ( separator menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC" menuitem "[:cache]DCACHE List" "CACHE.List DC" menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC" ) IF CPU.FEATURE(L2CACHEDUMP) ( separator menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2" menuitem "[:cache]L2CACHE List" "CACHE.List L2" menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2" ) ) ) ) popup "&Trace" ( separator IF COMPonent.AVAILable("ITM") ( popup "ITM" ( default menuitem "[:oconfig]ITM settings..." "ITM.state" separator menuitem "[:alist]ITMTrace List" "ITMTrace.List" ) ) IF COMPonent.AVAILable("STM") ( popup "STM" ( default menuitem "[:oconfig]STM settings..." "STM.state" separator menuitem "[:alist]STMTrace List" "STMTrace.List" ) ) IF COMPonent.AVAILable("HTM") ( popup "HTM" ( default menuitem "[:oconfig]HTM settings..." "HTM.state" separator menuitem "[:alist]HTMTrace List" "HTMTrace.List" ) ) IF COMPonent.AVAILable("TPIU") ( menuitem "[:oconfig]TPIU settings..." "TPIU.state" ) IF COMPonent.AVAILable("ETR") ( menuitem "[:oconfig]ETR settings..." ( PRIVATE &pdd &pdd=OS.PDD() DO "&pdd/etc/embedded_trace_router/etr_utility.cmm" ) ) ) popup "&Misc" ( popup "Tools" ( IF CPUIS64BIT()||CPU.FEATURE("SPR") ( menuitem "ARM System Register Converter" ( DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm" ) ) IF CPU.FEATURE("C15") ( menuitem "ARM Coprocessor Converter" ( DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm" ) ) ) ) popup "&Perf" ( IF CPU.FEATURE(BMC) ( before "Reset" menuitem "[:bmc]Benchmark Counters" "BMC.state" before "Reset" separator ) ) ) popup "Peripherals" ( if CORENAME()=="CORTEXA7MPCORE" ( popup "[:chip]Core Registers (Cortex-A7MPCore)" ( menuitem "[:chip]ID Registers" "per , ""Core Registers (Cortex-A7MPCore),ID Registers""" menuitem "[:chip]System Control and Configuration" "per , ""Core Registers (Cortex-A7MPCore),System Control and Configuration""" menuitem "[:chip]Memory Management Unit" "per , ""Core Registers (Cortex-A7MPCore),Memory Management Unit""" menuitem "[:chip]Virtualization Extensions" "per , ""Core Registers (Cortex-A7MPCore),Virtualization Extensions""" menuitem "[:chip]Cache Control and Configuration" "per , ""Core Registers (Cortex-A7MPCore),Cache Control and Configuration""" menuitem "[:chip]System Performance Monitor" "per , ""Core Registers (Cortex-A7MPCore),System Performance Monitor""" menuitem "[:chip]System Timer Register" "per , ""Core Registers (Cortex-A7MPCore),System Timer Register""" separator menuitem "[:chip]Debug Registers" "per , ""Core Registers (Cortex-A7MPCore),Debug Registers""" menuitem "[:chip]Breakpoint Registers" "per , ""Core Registers (Cortex-A7MPCore),Breakpoint Registers""" menuitem "[:chip]Watchpoint Control Registers" "per , ""Core Registers (Cortex-A7MPCore),Watchpoint Control Registers""" separator menuitem "[:chip]Interrupt Controller" "per , ""Core Registers (Cortex-A7MPCore),Interrupt Controller""" ) ) else if CORENAME()=="CORTEXM3" ( popup "[:chip]Core Registers (Cortex-M3)" ( menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M3),System Control""" menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M3),Memory Protection Unit""" menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M3),Nested Vectored Interrupt Controller""" popup "[:chip]Debug" ( menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M3),Debug,Core Debug""" menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit" "per , ""Core Registers (Cortex-M3),Debug,Flash Patch and Breakpoint Unit (FPB)""" menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M3),Debug,Data Watchpoint and Trace Unit (DWT)""" ) ) ) separator menuitem "IO Multiplexing" " per , ""IO Multiplexing""" menuitem "System Control" " per , ""System Control""" menuitem "2MB SRAM" " per , ""2MB SRAM""" if (cpu()!="R9A06G032-CA7") ( menuitem "4MB SRAM" " per , ""4MB SRAM""" ) if (cpuis("R9A06G032-*")) ( menuitem "DDR2/3" " per , ""DDR2/3 (DDR2/3 Controller)""" ) menuitem "NANDC" " per , ""NAND (NAND Flash Controller)""" popup "Quad IO SPI" ( menuitem "QSPI1" " per , ""Quad IO SPI,QSPI1""" if (cpu()=="R9A06G033-CM3") ( menuitem "QSPI2" " per , ""Quad IO SPI,QSPI2""" ) ) popup "SDIO" ( menuitem "SDIO1" " per , ""SDIO (SD/SDIO/eMMC Controller),SDIO1""" menuitem "SDIO2" " per , ""SDIO (SD/SDIO/eMMC Controller),SDIO2""" ) popup "USB 2.0" ( menuitem "OHCI" " per , ""USB 2.0,OHCI""" menuitem "EHCI" " per , ""USB 2.0,EHCI""" popup "PCI Configuration/Communication" ( menuitem "OHCI" " per , ""USB 2.0,PCI Configuration/Communication Space,OHCI""" menuitem "EHCI" " per , ""USB 2.0,PCI Configuration/Communication Space,EHCI""" menuitem "AHB-PCI Bridge Configuration" " per , ""USB 2.0,PCI Configuration/Communication Space,AHB-PCI Bridge Configuration""" menuitem "AHB-PCI Bridge Communication " " per , ""USB 2.0,PCI Configuration/Communication Space,AHB-PCI Bridge Communication""" ) menuitem "EPC" " per , ""USB 2.0,EPC""" menuitem "AHB-EPC" " per , ""USB 2.0,AHB-EPC""" ) popup "DMA" ( menuitem "DMAC1" " per , ""DMA (DMA Controller),DMAC1""" menuitem "DMAC2" " per , ""DMA (DMA Controller),DMAC2""" ) if (cpu()!="R9A06G034-CM3") ( menuitem "RTC" " per , ""RTC (Real-Time Clock)""" ) popup "Watchdog" ( if (cpu()=="R9A06G032-CA7") ( menuitem "WDOGA7_1" " per , ""Watchdog,WDOGA7_1 (Watchdog for CA7 processor0)""" menuitem "WDOGA7_2" " per , ""Watchdog,WDOGA7_2 (Watchdog for CA7 processor1)""" ) if cpuis("R9A06G0??-CM3") ( menuitem "WDOGCM3" " per , ""Watchdog,WDOGCM3 (Watchdog for CM3)""" ) ) menuitem "IPCM" " per , ""IPCM (Mailbox)""" menuitem "UART" " per , ""UART,UART""" menuitem "SPI" " per , ""SPI,SPI""" popup "I2C" ( menuitem "I2C1" " per , ""I2C,I2C1""" menuitem "I2C2" " per , ""I2C,I2C2""" ) popup "Basic GPIO" ( menuitem "BGPIO1" " per , ""Basic GPIO,BGPIO1""" menuitem "BGPIO2" " per , ""Basic GPIO,BGPIO2""" if (cpu()!="RZN1S-CM3")&&(cpu()!="RZN1L-CM3") ( menuitem "BGPIO3" " per , ""Basic GPIO,BGPIO3""" ) ) popup "Timer Block" ( menuitem "TIMER1" " per , ""Timer Block,TIMER1""" menuitem "TIMER2" " per , ""Timer Block,TIMER2""" ) popup "CAN" ( menuitem "CAN1" " per , ""CAN,CAN1""" menuitem "CAN2" " per , ""CAN,CAN2""" ) menuitem "ADC Controller and 12bit A/D Converters" " per , ""ADC Controller and 12bit A/D Converters""" menuitem "LCD Controller" " per , ""LCD Controller""" menuitem "Semaphore" " per , ""Semaphore""" popup "MSEBI" ( menuitem "MSEBI Master CPU" " per , ""MSEBI (Medium Speed External Bus Interface),MSEBI Master CPU""" menuitem "MSEBI Master DMA" " per , ""MSEBI (Medium Speed External Bus Interface),MSEBI Master DMA""" menuitem "MSEBI Slave CPU" " per , ""MSEBI (Medium Speed External Bus Interface),MSEBI Slave CPU""" menuitem "MSEBI Slave DMA" " per , ""MSEBI (Medium Speed External Bus Interface),MSEBI Slave DMA""" ) if !cpuis("R9A06G03?-CA7") ( popup "HW-RTOS GMAC" ( menuitem "HW-RTOS HWFC" " per , ""HW-RTOS GMAC (Gigabit Ethernet MAC),HW-RTOS HWFC (Hardware Function Call)""" menuitem "HW-RTOS GMAC" " per , ""HW-RTOS GMAC (Gigabit Ethernet MAC),HW-RTOS GMAC (Gigabit Ethernet MAC)""" ) ) menuitem "A5PSW" " per , ""A5PSW (Advanced 5port Switch)""" menuitem "ETHCAT" " per , ""ETHCAT (EtherCAT Slave Controller)""" menuitem "GMAC" " per , ""GMAC (Ethernet MAC 10/100/1000)""" if cpu()=="R9A06G032*" ( menuitem "HSRS" " per , ""HSRS (HSR Switch)""" ) menuitem "Sercos III Slave Controller" " per , ""Sercos III Slave Controller""" menuitem "R-IN Engine Accessory Register" " per , ""R-IN Engine Accessory Register""" menuitem "Ethernet Accessory Register" " per , ""Ethernet Accessory Register""" ) )