; --------------------------------------------------------------------------------
; @Title: RCARV3U Specific Menu
; @Props: Released
; @Author: KWI, PIW
; @Changelog: 2020-09-17 KWI
;             2022-05-23 PIW
; @Manufacturer: RENESAS - Renesas Technology, Corp.
; @Core: Cortex-A76, Cortex-R52
; @Chip: R8A779A0, R8A779A0-R52
; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: menrcarv3u.men 16339 2023-07-03 13:30:14Z pegold $

add
menu
(
IF SOFTWARE.BUILD.BASE()>=69655.
(
popup "&CPU"
(
separator
IF CPU.FEATURE(MMU)
(
popup "[:mmu]MMU"
(
menuitem "[:mmureg]MMU Control" "MMU.view"
separator
menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
separator
IF CPU.FEATURE(ITLBDUMP)
(
menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
)
IF CPU.FEATURE(DTLBDUMP)
(
menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
)
IF CPU.FEATURE(TLB0DUMP)
(
menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
)
IF CPU.FEATURE(TLB1DUMP)
(
menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
)
)
)
IF COMPonent.AVAILable("SMMU")
(
popup "[:mmu]SMMU"
(
menuitem "[:chip]SMMU1 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU1 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.StreamMapTable &(name)
)
IF COMPonent.AVAILable("SMMU2")
(
separator
menuitem "[:chip]SMMU2 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU2 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU3")
(
separator
menuitem "[:chip]SMMU3 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU3 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU4")
(
separator
menuitem "[:chip]SMMU4 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU4 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU5")
(
separator
menuitem "[:chip]SMMU5 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU5 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU6")
(
separator
menuitem "[:chip]SMMU6 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU6 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.StreamMapTable &(name)
)
)
)
)
IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
(
popup "[:cache]Cache"
(
IF CPU.FEATURE(L1ICACHEDUMP)
(
menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
menuitem "[:cache]ICACHE List" "CACHE.List IC"
menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
)
IF CPU.FEATURE(L1DCACHEDUMP)
(
separator
menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
menuitem "[:cache]DCACHE List" "CACHE.List DC"
menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
)
IF CPU.FEATURE(L2CACHEDUMP)
(
separator
menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
menuitem "[:cache]L2CACHE List" "CACHE.List L2"
menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
)
)
)
)
popup "&Trace"
(
separator
IF COMPonent.AVAILable("ITM")
(
popup "ITM"
(
default
menuitem "[:oconfig]ITM settings..." "ITM.state"
separator
menuitem "[:alist]ITMTrace List" "ITMTrace.List"
)
)
IF COMPonent.AVAILable("STM")
(
popup "STM"
(
default
menuitem "[:oconfig]STM settings..." "STM.state"
separator
menuitem "[:alist]STMTrace List" "STMTrace.List"
)
)
IF COMPonent.AVAILable("HTM")
(
popup "HTM"
(
default
menuitem "[:oconfig]HTM settings..." "HTM.state"
separator
menuitem "[:alist]HTMTrace List" "HTMTrace.List"
)
)
IF COMPonent.AVAILable("TPIU")
(
menuitem "[:oconfig]TPIU settings..." "TPIU.state"
)
IF COMPonent.AVAILable("ETR")
(
menuitem "[:oconfig]ETR settings..."
(
PRIVATE &pdd
&pdd=OS.PDD()
DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
)
)
)
popup "&Misc"
(
popup "Tools"
(
IF CPUIS64BIT()||CPU.FEATURE("SPR")
(
menuitem "ARM System Register Converter"
(
DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
)
)
IF CPU.FEATURE("C15")
(
menuitem "ARM Coprocessor Converter"
(
DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
)
)
)
)
popup "&Perf"
(
IF CPU.FEATURE(BMC)
(
before "Reset"
menuitem "[:bmc]Benchmark Counters" "BMC.state"
before "Reset"
separator
)
)
)
popup "Peripherals"
(
if (CORENAME()=="CORTEXR52")
(
popup "[:chip]Core Registers (Cortex-R52)"
(
menuitem "[:chip]ID Registers"                                                    "per , ""Core Registers (Cortex-R52),ID Registers"""
menuitem "[:chip]System Control and Configuration"                                "per , ""Core Registers (Cortex-R52),System Control and Configuration"""
menuitem "[:chip]MPU Control and Configuration"                                   "per , ""Core Registers (Cortex-R52),MPU Control and Configuration"""
menuitem "[:chip]Memory Protection Unit PL1"                                      "per , ""Core Registers (Cortex-R52),Memory Protection Unit PL1"""
menuitem "[:chip]Memory Protection Unit PL2"                                      "per , ""Core Registers (Cortex-R52),Memory Protection Unit PL2"""
menuitem "[:chip]Virtualization Extensions"                                       "per , ""Core Registers (Cortex-R52),Virtualization Extensions"""
menuitem "[:chip]Cache Control and Configuration"                                 "per , ""Core Registers (Cortex-R52),Cache Control and Configuration"""
menuitem "[:chip]System Performance Monitor"                                      "per , ""Core Registers (Cortex-R52),System Performance Monitor"""
menuitem "[:chip]System Timer Registers"                                          "per , ""Core Registers (Cortex-R52),System Timer Registers"""
menuitem "[:chip]Generic Interrupt Controller CPU Interface"                      "per , ""Core Registers (Cortex-R52),Generic Interrupt Controller CPU Interface"""
separator
menuitem "[:chip]Debug Registers"                                                 "per , ""Core Registers (Cortex-R52),Debug Registers"""
separator
menuitem "[:chip]Breakpoint Registers"                                            "per , ""Core Registers (Cortex-R52),Breakpoint Registers"""
menuitem "[:chip]Watchpoint Registers"                                            "per , ""Core Registers (Cortex-R52),Watchpoint Registers"""
separator
menuitem "[:chip]Interrupt Controller (GIC-500)"                                  "per , ""Core Registers (Cortex-R52),Interrupt Controller (GIC-500)"""
)
)
if (CORENAME()=="CORTEXA76")
(
popup "[:chip]Core Registers (Cortex-A76)"
(
menuitem "[:chip]ID Registers[AArch64]"                                                  "per , ""Core Registers (Cortex-A76),AArch64,ID Registers"""
menuitem "[:chip]System Control And Configuration[AArch64]"                              "per , ""Core Registers (Cortex-A76),AArch64,System Control And Configuration"""
menuitem "[:chip]System Instructions[AArch64]"                                           "per , ""Core Registers (Cortex-A76),AArch64,System Instructions"""
menuitem "[:chip]Memory Management Unit[AArch64]"                                        "per , ""Core Registers (Cortex-A76),AArch64,Memory Management Unit"""
menuitem "[:chip]Virtualization Extensions[AArch64]"                                     "per , ""Core Registers (Cortex-A76),AArch64,Virtualization Extensions"""
menuitem "[:chip]Cache Control And Configuration[AArch64]"                               "per , ""Core Registers (Cortex-A76),AArch64,Cache Control And Configuration"""
menuitem "[:chip]System Performance Monitor[AArch64]"                                    "per , ""Core Registers (Cortex-A76),AArch64,System Performance Monitor"""
menuitem "[:chip]System Timer Registers[AArch64]"                                        "per , ""Core Registers (Cortex-A76),AArch64,System Timer Registers"""
menuitem "[:chip]Generic Interrupt Controller CPU Interface[AArch64]"                    "per , ""Core Registers (Cortex-A76),AArch64,Generic Interrupt Controller CPU Interface"""
separator
menuitem "[:chip]Debug Registers[AArch64]"                                               "per , ""Core Registers (Cortex-A76),AArch64,Debug Registers"""
separator
menuitem "[:chip]Activity Monitors Unit[AArch64]"                                        "per , ""Core Registers (Cortex-A76),AArch64,Activity Monitors Unit"""
menuitem "[:chip]Breakpoint Registers[AArch64]"                                          "per , ""Core Registers (Cortex-A76),AArch64,Breakpoint Registers"""
menuitem "[:chip]Watchpoint Registers[AArch64]"                                          "per , ""Core Registers (Cortex-A76),AArch64,Watchpoint Registers"""
separator
menuitem "[:chip]LORegions Registers[AArch64]"                                           "per , ""Core Registers (Cortex-A76),AArch64,LORegions Registers"""
separator
menuitem "[:chip]DynamIQ Shared Unit[AArch64]"                                           "per , ""Core Registers (Cortex-A76),AArch64,DynamIQ Shared Unit"""
separator
menuitem "[:chip]System Control And Configuration[AArch32]"                              "per , ""Core Registers (Cortex-A76),AArch32,System Control And Configuration"""
menuitem "[:chip]System Instructions[AArch32]"                                           "per , ""AArch32,System Instructions"""
menuitem "[:chip]Virtualization Extensions[AArch32]"                                     "per , ""Core Registers (Cortex-A76),AArch32,Virtualization Extensions"""
menuitem "[:chip]System Performance Monitor[AArch32]"                                    "per , ""Core Registers (Cortex-A76),AArch32,System Performance Monitor"""
menuitem "[:chip]System Timer Registers[AArch32]"                                        "per , ""Core Registers (Cortex-A76),AArch32,System Timer Registers"""
separator
menuitem "[:chip]Debug Registers[AArch32]"                                               "per , ""Core Registers (Cortex-A76),AArch32,Debug Registers"""
separator
menuitem "[:chip]Interrupt Controller (GIC-500)"                                         "per , ""Core Registers (Cortex-A76),Interrupt Controller (GIC-500)"""
)
)
separator
popup "PFC"
(
menuitem "PFC_0"                "per , ""PFC,PFC_0"""
menuitem "PFC_1"                "per , ""PFC,PFC_1"""
menuitem "PFC_2"                "per , ""PFC,PFC_2"""
menuitem "PFC_3"                "per , ""PFC,PFC_3"""
)
menuitem "PFC_SYS"                  "per , ""PFC_SYS"""
menuitem "CPG"                      "per , ""CPG"""
menuitem "MSTPCR"                   "per , ""MSTPCR"""
menuitem "MSTPSR"                   "per , ""MSTPSR"""
menuitem "SRCR"                     "per , ""SRCR"""
popup "APMU_Domain"
(
menuitem "APMU_Domain_0"        "per , ""APMU_Domain,APMU_Domain_0"""
menuitem "APMU_Domain_1"        "per , ""APMU_Domain,APMU_Domain_1"""
menuitem "APMU_Domain_2"        "per , ""APMU_Domain,APMU_Domain_2"""
menuitem "APMU_Domain_3"        "per , ""APMU_Domain,APMU_Domain_3"""
)
popup "SYSC"
(
menuitem "SYSC_0"               "per , ""SYSC,SYSC_0"""
menuitem "SYSC_1"               "per , ""SYSC,SYSC_1"""
menuitem "SYSC_2"               "per , ""SYSC,SYSC_2"""
menuitem "SYSC_3"               "per , ""SYSC,SYSC_3"""
)
popup "TSC"
(
menuitem "TSC_0"                "per , ""TSC,TSC_0"""
menuitem "TSC_1"                "per , ""TSC,TSC_1"""
menuitem "TSC_2"                "per , ""TSC,TSC_2"""
menuitem "TSC_3"                "per , ""TSC,TSC_3"""
menuitem "TSC_4"                "per , ""TSC,TSC_4"""
)
popup "INTC"
(
menuitem "INTC"                 "per , ""INTC,INTC"""
menuitem "INTC-EX"              "per , ""INTC,INTC-EX"""
)
menuitem "MFIS"                     "per , ""MFIS"""
menuitem "ECM"                      "per , ""ECM"""
menuitem "AXI"                      "per , ""AXI"""
menuitem "AXMM"                     "per , ""AXMM"""
menuitem "QOS"                      "per , ""QOS"""
menuitem "RT_SRAM"                  "per , ""RT_SRAM"""
menuitem "BKBUF"                    "per , ""BKBUF"""
menuitem "VCP"                      "per , ""VCP"""
popup "SCIF"
(
menuitem "SCIF_0"               "per , ""SCIF,SCIF_0"""
menuitem "SCIF_1"               "per , ""SCIF,SCIF_1"""
menuitem "SCIF_2"               "per , ""SCIF,SCIF_2"""
menuitem "SCIF_3"               "per , ""SCIF,SCIF_3"""
)
popup "HSCIF"
(
menuitem "HSCIF_0"              "per , ""HSCIF,HSCIF_0"""
menuitem "HSCIF_1"              "per , ""HSCIF,HSCIF_1"""
menuitem "HSCIF_2"              "per , ""HSCIF,HSCIF_2"""
menuitem "HSCIF_3"              "per , ""HSCIF,HSCIF_3"""
)
popup "I2C"
(
menuitem "I2C_0"                "per , ""I2C,I2C_0"""
menuitem "I2C_1"                "per , ""I2C,I2C_1"""
menuitem "I2C_2"                "per , ""I2C,I2C_2"""
menuitem "I2C_3"                "per , ""I2C,I2C_3"""
menuitem "I2C_4"                "per , ""I2C,I2C_4"""
menuitem "I2C_5"                "per , ""I2C,I2C_5"""
menuitem "I2C_6"                "per , ""I2C,I2C_6"""
)
popup "MSIOF"
(
menuitem "MSIOF_0"             "per , ""MSIOF,MSIOF_0"""
menuitem "MSIOF_1"             "per , ""MSIOF,MSIOF_1"""
menuitem "MSIOF_2"             "per , ""MSIOF,MSIOF_2"""
menuitem "MSIOF_3"             "per , ""MSIOF,MSIOF_3"""
menuitem "MSIOF_4"             "per , ""MSIOF,MSIOF_4"""
menuitem "MSIOF_5"             "per , ""MSIOF,MSIOF_5"""
)
popup "PWM"
(
menuitem "PWM_0"                "per , ""PWM,PWM_0"""
menuitem "PWM_1"                "per , ""PWM,PWM_1"""
menuitem "PWM_2"                "per , ""PWM,PWM_2"""
menuitem "PWM_3"                "per , ""PWM,PWM_3"""
menuitem "PWM_4"                "per , ""PWM,PWM_4"""
)
menuitem "LIFEC"                    "per , ""LIFEC"""
popup "CRC"
(
menuitem "CRC_0"               "per , ""CRC,CRC_0"""
menuitem "CRC_1"               "per , ""CRC,CRC_1"""
menuitem "CRC_2"               "per , ""CRC,CRC_2"""
menuitem "CRC_3"               "per , ""CRC,CRC_3"""
menuitem "CRC_4"               "per , ""CRC,CRC_4"""
)
popup "KCRC"
(
menuitem "KCRC_0"              "per , ""KCRC,KCRC_0"""
menuitem "KCRC_1"              "per , ""KCRC,KCRC_1"""
menuitem "KCRC_2"              "per , ""KCRC,KCRC_2"""
menuitem "KCRC_3"              "per , ""KCRC,KCRC_3"""
)
popup "WCRC"
(
menuitem "WCRC_0"              "per , ""WCRC,WCRC_0"""
menuitem "WCRC_1"              "per , ""WCRC,WCRC_1"""
menuitem "WCRC_2"              "per , ""WCRC,WCRC_2"""
menuitem "WCRC_3"              "per , ""WCRC,WCRC_3"""
)
popup "RFSO"
(
menuitem "RFSO_0"              "per , ""RFSO,RFSO_0"""
menuitem "RFSO_1"              "per , ""RFSO,RFSO_1"""
menuitem "RFSO_2"              "per , ""RFSO,RFSO_2"""
menuitem "RFSO_3"              "per , ""RFSO,RFSO_3"""
menuitem "RFSO_4"              "per , ""RFSO,RFSO_4"""
menuitem "RFSO_5"              "per , ""RFSO,RFSO_5"""
menuitem "RFSO_6"              "per , ""RFSO,RFSO_6"""
menuitem "RFSO_7"              "per , ""RFSO,RFSO_7"""
menuitem "RFSO_8"              "per , ""RFSO,RFSO_8"""
menuitem "RFSO_9"              "per , ""RFSO,RFSO_9"""
menuitem "RFSO_10"              "per , ""RFSO,RFSO_10"""
)
menuitem "RWDT"                     "per , ""RWDT"""
popup "WWDT"
(
menuitem "WWDT_0"              "per , ""WWDT,WWDT_0"""
menuitem "WWDT_1"              "per , ""WWDT,WWDT_1"""
menuitem "WWDT_2"              "per , ""WWDT,WWDT_2"""
menuitem "WWDT_3"              "per , ""WWDT,WWDT_3"""
menuitem "WWDT_4"              "per , ""WWDT,WWDT_4"""
menuitem "WWDT_5"              "per , ""WWDT,WWDT_5"""
menuitem "WWDT_6"              "per , ""WWDT,WWDT_6"""
menuitem "WWDT_7"              "per , ""WWDT,WWDT_7"""
menuitem "WWDT_8"              "per , ""WWDT,WWDT_8"""
menuitem "WWDT_9"              "per , ""WWDT,WWDT_9"""
)
menuitem "SWDT"                     "per , ""SWDT"""
menuitem "TPU"                      "per , ""TPU"""
popup "CMT"
(
menuitem "CMT_0"                "per , ""CMT,CMT_0"""
menuitem "CMT_1"               "per , ""CMT,CMT_1"""
menuitem "CMT_2"               "per , ""CMT,CMT_2"""
menuitem "CMT_3"               "per , ""CMT,CMT_3"""
)
popup "TMU"
(
menuitem "TMU_0"                "per , ""TMU,TMU_0"""
menuitem "TMU_1"                "per , ""TMU,TMU_1"""
menuitem "TMU_2"                "per , ""TMU,TMU_2"""
menuitem "TMU_3"                "per , ""TMU,TMU_3"""
menuitem "TMU_4"                "per , ""TMU,TMU_4"""
menuitem "TMU_5"                "per , ""TMU,TMU_5"""
menuitem "TMU_6"                "per , ""TMU,TMU_6"""
menuitem "TMU_7"                "per , ""TMU,TMU_7"""
menuitem "TMU_8"                "per , ""TMU,TMU_8"""
menuitem "TMU_9"                "per , ""TMU,TMU_9"""
menuitem "TMU_10"               "per , ""TMU,TMU_10"""
menuitem "TMU_11"               "per , ""TMU,TMU_11"""
menuitem "TMU_12"               "per , ""TMU,TMU_12"""
menuitem "TMU_13"               "per , ""TMU,TMU_13"""
menuitem "TMU_14"               "per , ""TMU,TMU_14"""
)
menuitem "AppA"                     "per , ""AppA"""
menuitem "IPC_DataLink"             "per , ""IPC_DataLink"""
menuitem "IPC_HSSL"                 "per , ""IPC_HSSL"""
popup "Domain"
(
menuitem "Domain_0"             "per , ""Domain,Domain_0"""
menuitem "Domain_1"             "per , ""Domain,Domain_1"""
menuitem "Domain_2"             "per , ""Domain,Domain_2"""
menuitem "Domain_3"             "per , ""Domain,Domain_3"""
)
popup "DBSC"
(
menuitem "DBSC_0"               "per , ""DBSC,DBSC_0"""
menuitem "DBSC_1"               "per , ""DBSC,DBSC_1"""
)
)
)