; -------------------------------------------------------------------------------- ; @Title: OMAP3430 Specific Menu ; @Props: Released ; @Author: FIL, ZUB ; @Changelog: ; 2007-12-17 ; 2008-07-30 ; @Manufacturer: TI - Texas Instruments ; @Core: Cortex-A8 ; @Chip: OMAP3430 ; @Copyright: (C) 1989-2016 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: menomap3430.men 16339 2023-07-03 13:30:14Z pegold $ add menu ( IF SOFTWARE.BUILD.BASE()>=69655. ( popup "&CPU" ( separator IF CPU.FEATURE(MMU) ( popup "[:mmu]MMU" ( menuitem "[:mmureg]MMU Control" "MMU.view" separator menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable" menuitem "[:mmu]MMU Table List" "MMU.List.PageTable" separator IF CPU.FEATURE(ITLBDUMP) ( menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB" ) IF CPU.FEATURE(DTLBDUMP) ( menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB" ) IF CPU.FEATURE(TLB0DUMP) ( menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0" ) IF CPU.FEATURE(TLB1DUMP) ( menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1" ) ) ) IF COMPonent.AVAILable("SMMU") ( popup "[:mmu]SMMU" ( menuitem "[:chip]SMMU1 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU1 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.)) SMMU.StreamMapTable &(name) ) IF COMPonent.AVAILable("SMMU2") ( separator menuitem "[:chip]SMMU2 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU2 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU3") ( separator menuitem "[:chip]SMMU3 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU3 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU4") ( separator menuitem "[:chip]SMMU4 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU4 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU5") ( separator menuitem "[:chip]SMMU5 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU5 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU6") ( separator menuitem "[:chip]SMMU6 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU6 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.)) SMMU.StreamMapTable &(name) ) ) ) ) IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE) ( popup "[:cache]Cache" ( IF CPU.FEATURE(L1ICACHEDUMP) ( menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC" menuitem "[:cache]ICACHE List" "CACHE.List IC" menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC" ) IF CPU.FEATURE(L1DCACHEDUMP) ( separator menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC" menuitem "[:cache]DCACHE List" "CACHE.List DC" menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC" ) IF CPU.FEATURE(L2CACHEDUMP) ( separator menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2" menuitem "[:cache]L2CACHE List" "CACHE.List L2" menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2" ) ) ) ) popup "&Trace" ( separator IF COMPonent.AVAILable("ITM") ( popup "ITM" ( default menuitem "[:oconfig]ITM settings..." "ITM.state" separator menuitem "[:alist]ITMTrace List" "ITMTrace.List" ) ) IF COMPonent.AVAILable("STM") ( popup "STM" ( default menuitem "[:oconfig]STM settings..." "STM.state" separator menuitem "[:alist]STMTrace List" "STMTrace.List" ) ) IF COMPonent.AVAILable("HTM") ( popup "HTM" ( default menuitem "[:oconfig]HTM settings..." "HTM.state" separator menuitem "[:alist]HTMTrace List" "HTMTrace.List" ) ) IF COMPonent.AVAILable("TPIU") ( menuitem "[:oconfig]TPIU settings..." "TPIU.state" ) IF COMPonent.AVAILable("ETR") ( menuitem "[:oconfig]ETR settings..." ( PRIVATE &pdd &pdd=OS.PDD() DO "&pdd/etc/embedded_trace_router/etr_utility.cmm" ) ) ) popup "&Misc" ( popup "Tools" ( IF CPUIS64BIT()||CPU.FEATURE("SPR") ( menuitem "ARM System Register Converter" ( DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm" ) ) IF CPU.FEATURE("C15") ( menuitem "ARM Coprocessor Converter" ( DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm" ) ) ) ) popup "&Perf" ( IF CPU.FEATURE(BMC) ( before "Reset" menuitem "[:bmc]Benchmark Counters" "BMC.state" before "Reset" separator ) ) ) popup "Peripherals" ( popup "[:chip]Core Registers (Cortex-A8)" ( menuitem "[:chip]ID Registers" "per , ""Core Registers (Cortex-A8),ID Registers""" menuitem "[:chip]System Control and Configuration" "per , ""Core Registers (Cortex-A8),System Control and Configuration""" menuitem "[:chip]Memory Management Unit" "per , ""Core Registers (Cortex-A8),Memory Management Unit""" menuitem "[:chip]Cache Control and Configuration" "per , ""Core Registers (Cortex-A8),Cache Control and Configuration""" menuitem "[:chip]L2 Cache Control and Configuration" "per , ""Core Registers (Cortex-A8),L2 Cache Control and Configuration""" menuitem "[:chip]System Performance Monitor" "per , ""Core Registers (Cortex-A8),System Performance Monitor""" menuitem "[:chip]Debug Registers" "per , ""Core Registers (Cortex-A8),Debug Registers""" menuitem "[:chip]Breakpoint Registers" "per , ""Core Registers (Cortex-A8),Breakpoint Registers""" menuitem "[:chip]Watchpoint Control Registers" "per , ""Core Registers (Cortex-A8),Watchpoint Control Registers""" ) separator menuitem "General Registers" "per , ""General Registers""" popup "Power Reset and Clock Management" ( menuitem "Clock Management" "per , ""Power Reset and Clock Management,Clock Management""" menuitem "Power Reset Management" "per , ""Power Reset and Clock Management,Power Reset Management""" ) popup "L3 Interconnect" ( menuitem "Initiator Agent" "per , ""L3 Interconnect,Initiator Agent Registers""" menuitem "Target Agent" "per , ""L3 Interconnect,Target Agent Registers""" menuitem "Register Target" "per , ""L3 Interconnect,Register Target Registers""" menuitem "Protection Mechanism Common" "per , ""L3 Interconnect,Protection Mechanism Common Registers""" menuitem "Sideband Interconnect" "per , ""L3 Interconnect,Sideband Interconnect Registers""" ) popup "L4 Interconnect" ( menuitem "L4-Core" "per , ""L4 Interconnect,L4-Core""" menuitem "L4-Per" "per , ""L4 Interconnect,L4-Per""" menuitem "L4-Emu" "per , ""L4 Interconnect,L4-Emu""" menuitem "L4-Wakeup" "per , ""L4 Interconnect,L4-Wakeup""" ) menuitem "Interprocessor Communication" "per , ""Interprocessor Communication""" popup "System Control Registers" ( menuitem "INTERFACE" "per , ""System Control Registers,INTERFACE""" menuitem "PADCONFS" "per , ""System Control Registers,PADCONFS""" menuitem "GENERAL" "per , ""System Control Registers,GENERAL""" menuitem "PADCONFS_WKUP" "per , ""System Control Registers,PADCONFS_WKUP""" menuitem "GENERAL_WKUP" "per , ""System Control Registers,GENERAL_WKUP""" ) popup "MMU" ( menuitem "Camera MMU" "per , ""MMU (Memory Management Unit),Camera MMU""" menuitem "IVA2.2 MMU" "per , ""MMU (Memory Management Unit),IVA2.2 MMU""" ) popup "DMA" ( menuitem "Common" "per , ""DMA,Common Registers""" menuitem "Channels" "per , ""DMA,Channels Registers""" ) popup "Interrupt Controller" ( menuitem "MPU subsystem INTC" "per , ""Interrupt Controller Registers,MPU subsystem INTC""" menuitem "Modem INTC" "per , ""Interrupt Controller Registers,Modem INTC""" ) popup "Memory Subsystem" ( menuitem "GPMC" "per , ""Memory Subsystem,GPMC (General Purpose Memory Controller)""" menuitem "SDRAM Controller Subsystem" "per , ""Memory Subsystem,SDRAM Controller Subsystem""" ) popup "Camera ISP" ( menuitem "ISP" "per , ""Camera ISP,ISP""" menuitem "ISP_CBUFF" "per , ""Camera ISP,ISP_CBUFF""" menuitem "CSI1_RECEIVER" "per , ""Camera ISP,CSI1_RECEIVER""" menuitem "ISP_CCDC" "per , ""Camera ISP,ISP_CCDC""" menuitem "ISP_HIST" "per , ""Camera ISP,ISP_HIST""" menuitem "ISP_H3A" "per , ""Camera ISP,ISP_H3A""" menuitem "ISP_PREVIEW" "per , ""Camera ISP,ISP_PREVIEW""" menuitem "ISP_RESIZER" "per , ""Camera ISP,ISP_RESIZER""" menuitem "ISP_SBL" "per , ""Camera ISP,ISP_SBL""" menuitem "ISP_CSI2A" "per , ""Camera ISP,ISP_CSI2A""" menuitem "CSI2PHY_SCP" "per , ""Camera ISP,CSI2PHY_SCP""" ) popup "Display Subsystem" ( menuitem "DISS" "per , ""Display Subsystem,DISS""" menuitem "DISPC" "per , ""Display Subsystem,DISPC""" menuitem "RFBI" "per , ""Display Subsystem,RFBI""" menuitem "VENC" "per , ""Display Subsystem,VENC""" menuitem "DSI" "per , ""Display Subsystem,DSI""" ) popup "Timers" ( menuitem "GPT" "per , ""Timers,GPT""" menuitem "WDT" "per , ""Timers,WDT""" menuitem "32-kHz Sync" "per , ""Timers,32-kHz Sync""" ) popup "UART/IrDA/CIR" ( menuitem "UART1" "per , ""UART/IrDA/CIR,UART1""" menuitem "UART2" "per , ""UART/IrDA/CIR,UART2""" menuitem "UART3/IrDA/CIR" "per , ""UART/IrDA/CIR,UART3/IrDA/CIR""" ) popup "I2C" ( menuitem "I2C1" "per , ""High-Speed I2C Controller,I2C1""" menuitem "I2C2" "per , ""High-Speed I2C Controller,I2C2""" menuitem "I2C3" "per , ""High-Speed I2C Controller,I2C3""" ) popup "MCSPI" ( menuitem "MCSPI1" "per , ""Multichannel SPI,MCSPI1""" menuitem "MCSPI2" "per , ""Multichannel SPI,MCSPI2""" menuitem "MCSPI3" "per , ""Multichannel SPI,MCSPI3""" menuitem "MCSPI4" "per , ""Multichannel SPI,MCSPI4""" ) menuitem "HDQ/1-Wire" "per , ""HDQ/1-Wire""" popup "Multi-Channel Buffered Serial Port" ( menuitem "McBSP1" "per , ""Multi-Channel Buffered Serial Port,McBSP1""" menuitem "McBSP2" "per , ""Multi-Channel Buffered Serial Port,McBSP2""" menuitem "SIDETONE_McBSP2" "per , ""Multi-Channel Buffered Serial Port,SIDETONE_McBSP2""" menuitem "McBSP3" "per , ""Multi-Channel Buffered Serial Port,McBSP3""" menuitem "SIDETONE_McBSP3" "per , ""Multi-Channel Buffered Serial Port,SIDETONE_McBSP3""" menuitem "McBSP4" "per , ""Multi-Channel Buffered Serial Port,McBSP4""" menuitem "McBSP5" "per , ""Multi-Channel Buffered Serial Port,McBSP5""" ) popup "MMC/SD/SDIO Card Interface" ( menuitem "MMCHS1" "per , ""MMC/SD/SDIO Card Interface,MMCHS1""" menuitem "MMCHS2" "per , ""MMC/SD/SDIO Card Interface,MMCHS2""" menuitem "MMCHS3" "per , ""MMC/SD/SDIO Card Interface,MMCHS3""" ) popup "USB" ( menuitem "High-Speed USB Host Subsystem" "per , ""High-Speed USB Host Subsystem/On-The-Go Controller,High-Speed USB Host Subsystem""" menuitem "High-Speed USB OTG Controller" "per , ""High-Speed USB Host Subsystem/On-The-Go Controller,High-Speed USB OTG Controller""" ) menuitem "GPIO" "per , ""GPIO""" ) )