; --------------------------------------------------------------------------------
; @Title: LS20XX Specific Menu
; @Props: Released
; @Author: ADP, BCA, JAS, MRD, DAM, RAJ, KOF, PID, DAS, TRJ
; @Changelog: 2016-04-25 ADP
;             2018-09-25 BCA
;             2019-02-13 JAS
;             2020-04-07 RAJ
;             2021-05-11 TRJ
; @Manufacturer: NXP - NXP Semiconductors
; @Core: Cortex-A57, Cortex-A72
; @Chip: LS2044A, LS2048A, LS2084A, LS2088A
; @Copyright: (C) 1989-2021 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: menls20xx.men 16339 2023-07-03 13:30:14Z pegold $

add
menu
(
IF SOFTWARE.BUILD.BASE()>=69655.
(
popup "&CPU"
(
separator
IF CPU.FEATURE(MMU)
(
popup "[:mmu]MMU"
(
menuitem "[:mmureg]MMU Control" "MMU.view"
separator
menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
separator
IF CPU.FEATURE(ITLBDUMP)
(
menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
)
IF CPU.FEATURE(DTLBDUMP)
(
menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
)
IF CPU.FEATURE(TLB0DUMP)
(
menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
)
IF CPU.FEATURE(TLB1DUMP)
(
menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
)
)
)
IF COMPonent.AVAILable("SMMU")
(
popup "[:mmu]SMMU"
(
menuitem "[:chip]SMMU1 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU1 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.StreamMapTable &(name)
)
IF COMPonent.AVAILable("SMMU2")
(
separator
menuitem "[:chip]SMMU2 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU2 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU3")
(
separator
menuitem "[:chip]SMMU3 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU3 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU4")
(
separator
menuitem "[:chip]SMMU4 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU4 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU5")
(
separator
menuitem "[:chip]SMMU5 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU5 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU6")
(
separator
menuitem "[:chip]SMMU6 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU6 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.StreamMapTable &(name)
)
)
)
)
IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
(
popup "[:cache]Cache"
(
IF CPU.FEATURE(L1ICACHEDUMP)
(
menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
menuitem "[:cache]ICACHE List" "CACHE.List IC"
menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
)
IF CPU.FEATURE(L1DCACHEDUMP)
(
separator
menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
menuitem "[:cache]DCACHE List" "CACHE.List DC"
menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
)
IF CPU.FEATURE(L2CACHEDUMP)
(
separator
menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
menuitem "[:cache]L2CACHE List" "CACHE.List L2"
menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
)
)
)
)
popup "&Trace"
(
separator
IF COMPonent.AVAILable("ITM")
(
popup "ITM"
(
default
menuitem "[:oconfig]ITM settings..." "ITM.state"
separator
menuitem "[:alist]ITMTrace List" "ITMTrace.List"
)
)
IF COMPonent.AVAILable("STM")
(
popup "STM"
(
default
menuitem "[:oconfig]STM settings..." "STM.state"
separator
menuitem "[:alist]STMTrace List" "STMTrace.List"
)
)
IF COMPonent.AVAILable("HTM")
(
popup "HTM"
(
default
menuitem "[:oconfig]HTM settings..." "HTM.state"
separator
menuitem "[:alist]HTMTrace List" "HTMTrace.List"
)
)
IF COMPonent.AVAILable("TPIU")
(
menuitem "[:oconfig]TPIU settings..." "TPIU.state"
)
IF COMPonent.AVAILable("ETR")
(
menuitem "[:oconfig]ETR settings..."
(
PRIVATE &pdd
&pdd=OS.PDD()
DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
)
)
)
popup "&Misc"
(
popup "Tools"
(
IF CPUIS64BIT()||CPU.FEATURE("SPR")
(
menuitem "ARM System Register Converter"
(
DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
)
)
IF CPU.FEATURE("C15")
(
menuitem "ARM Coprocessor Converter"
(
DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
)
)
)
)
popup "&Perf"
(
IF CPU.FEATURE(BMC)
(
before "Reset"
menuitem "[:bmc]Benchmark Counters" "BMC.state"
before "Reset"
separator
)
)
)
popup "Peripherals"
(
if (CORENAME()=="CORTEXA72")
(
popup "[:chip]Core Registers (Cortex-A72)"
(
menuitem "[:chip]ID Registers[AArch64]"                               "per , ""Core Registers (Cortex-A72),AArch64,ID Registers"""
menuitem "[:chip]System Control and Configuration[AArch64]"           "per , ""Core Registers (Cortex-A72),AArch64,System Control and Configuration"""
menuitem "[:chip]Memory Management Unit[AArch64]"                     "per , ""Core Registers (Cortex-A72),AArch64,Memory Management Unit"""
menuitem "[:chip]Virtualization Extensions[AArch64]"                  "per , ""Core Registers (Cortex-A72),AArch64,Virtualization Extensions"""
menuitem "[:chip]Cache Control and Configuration[AArch64]"            "per , ""Core Registers (Cortex-A72),AArch64,Cache Control and Configuration"""
menuitem "[:chip]System Performance Monitor[AArch64]"                 "per , ""Core Registers (Cortex-A72),AArch64,System Performance Monitor"""
menuitem "[:chip]System Timer Registers[AArch64]"                     "per , ""Core Registers (Cortex-A72),AArch64,System Timer Registers"""
menuitem "[:chip]Generic Interrupt Controller CPU Interface[AArch64]" "per , ""Core Registers (Cortex-A72),AArch64,Generic Interrupt Controller CPU Interface"""
separator
menuitem "[:chip]Debug Registers[AArch64]"                            "per , ""Core Registers (Cortex-A72),AArch64,Debug Registers"""
separator
menuitem "[:chip]Breakpoint Registers[AArch64]"                       "per , ""Core Registers (Cortex-A72),AArch64,Breakpoint Registers"""
menuitem "[:chip]Watchpoint Registers[AArch64]"                       "per , ""Core Registers (Cortex-A72),AArch64,Watchpoint Control Registers"""
separator
menuitem "[:chip]ID Registers[AArch32]"                               "per , ""Core Registers (Cortex-A72),AArch32,ID Registers"""
menuitem "[:chip]System Control and Configuration[AArch32]"           "per , ""Core Registers (Cortex-A72),AArch32,System Control and Configuration"""
menuitem "[:chip]Memory Management Unit[AArch32]"                     "per , ""Core Registers (Cortex-A72),AArch32,Memory Management Unit"""
menuitem "[:chip]Virtualization Extensions[AArch32]"                  "per , ""Core Registers (Cortex-A72),AArch32,Virtualization Extensions"""
menuitem "[:chip]Cache Control and Configuration[AArch32]"            "per , ""Core Registers (Cortex-A72),AArch32,Cache Control and Configuration"""
menuitem "[:chip]System Performance Monitor[AArch32]"                 "per , ""Core Registers (Cortex-A72),AArch32,System Performance Monitor"""
menuitem "[:chip]System Timer Registers[AArch32]"                     "per , ""Core Registers (Cortex-A72),AArch32,System Timer Registers"""
menuitem "[:chip]Generic Interrupt Controller CPU Interface[AArch32]" "per , ""Core Registers (Cortex-A72),AArch32,Generic Interrupt Controller CPU Interface"""
separator
menuitem "[:chip]Debug Registers[AArch32]"                            "per , ""Core Registers (Cortex-A72),AArch32,Debug Registers"""
separator
menuitem "[:chip]Breakpoint Registers[AArch32]"                       "per , ""Core Registers (Cortex-A72),AArch32,Breakpoint Registers"""
menuitem "[:chip]Watchpoint Registers[AArch32]"                       "per , ""Core Registers (Cortex-A72),AArch32,Watchpoint Control Registers"""
separator
menuitem "[:chip]Interrupt Controller (GIC-500)"                      "per , ""Core Registers (Cortex-A72),Interrupt Controller (GIC-500)"""
)
)
else
(
popup "[:chip]Core Registers (Cortex-A57)"
(
menuitem "[:chip]ID Registers[AArch64]"                               "per , ""Core Registers (Cortex-A57),AArch64,ID Registers"""
menuitem "[:chip]System Control and Configuration[AArch64]"           "per , ""Core Registers (Cortex-A57),AArch64,System Control and Configuration"""
menuitem "[:chip]Memory Management Unit[AArch64]"                     "per , ""Core Registers (Cortex-A57),AArch64,Memory Management Unit"""
menuitem "[:chip]Virtualization Extensions[AArch64]"                  "per , ""Core Registers (Cortex-A57),AArch64,Virtualization Extensions"""
menuitem "[:chip]Cache Control and Configuration[AArch64]"            "per , ""Core Registers (Cortex-A57),AArch64,Cache Control and Configuration"""
menuitem "[:chip]System Performance Monitor[AArch64]"                 "per , ""Core Registers (Cortex-A57),AArch64,System Performance Monitor"""
menuitem "[:chip]System Timer Registers[AArch64]"                     "per , ""Core Registers (Cortex-A57),AArch64,System Timer Registers"""
menuitem "[:chip]Generic Interrupt Controller CPU Interface[AArch64]" "per , ""Core Registers (Cortex-A57),AArch64,Generic Interrupt Controller CPU Interface"""
separator
menuitem "[:chip]Debug Registers[AArch64]"                            "per , ""Core Registers (Cortex-A57),AArch64,Debug Registers"""
separator
menuitem "[:chip]Breakpoint Registers[AArch64]"                       "per , ""Core Registers (Cortex-A57),AArch64,Breakpoint Registers"""
menuitem "[:chip]Watchpoint Control Registers[AArch64]"               "per , ""Core Registers (Cortex-A57),AArch64,Watchpoint Control Registers"""
separator
menuitem "[:chip]ID Registers[AArch32]"                               "per , ""Core Registers (Cortex-A57),AArch32,ID Registers"""
menuitem "[:chip]System Control and Configuration[AArch32]"           "per , ""Core Registers (Cortex-A57),AArch32,System Control and Configuration"""
menuitem "[:chip]Memory Management Unit[AArch32]"                     "per , ""Core Registers (Cortex-A57),AArch32,Memory Management Unit"""
menuitem "[:chip]Virtualization Extensions[AArch32]"                  "per , ""Core Registers (Cortex-A57),AArch32,Virtualization Extensions"""
menuitem "[:chip]Cache Control and Configuration[AArch32]"            "per , ""Core Registers (Cortex-A57),AArch32,Cache Control and Configuration"""
menuitem "[:chip]System Performance Monitor[AArch32]"                 "per , ""Core Registers (Cortex-A57),AArch32,System Performance Monitor"""
menuitem "[:chip]System Timer Registers[AArch32]"                     "per , ""Core Registers (Cortex-A57),AArch32,System Timer Registers"""
menuitem "[:chip]Generic Interrupt Controller CPU Interface[AArch32]" "per , ""Core Registers (Cortex-A57),AArch32,Generic Interrupt Controller CPU Interface"""
separator
menuitem "[:chip]Debug Registers[AArch32]"                            "per , ""Core Registers (Cortex-A57),AArch32,Debug Registers"""
separator
menuitem "[:chip]Breakpoint Registers[AArch32]"                       "per , ""Core Registers (Cortex-A57),AArch32,Breakpoint Registers"""
menuitem "[:chip]Watchpoint Control Registers[AArch32]"               "per , ""Core Registers (Cortex-A57),AArch32,Watchpoint Control Registers"""
separator
menuitem "[:chip]Interrupt Controller (GIC-500)"                      "per , ""Core Registers (Cortex-A57),Interrupt Controller (GIC-500)"""
)
)
separator
popup "RST/CLK;Reset Clocking and Initialization"
(
menuitem "Reset"                                                "per , ""RST/CLK (Reset Clocking and Initialization),Reset"""
popup "Clock"
(
menuitem "CGU Platform"                                     "per , ""RST/CLK (Reset Clocking and Initialization),Clock,CGU Platform"""
menuitem "CGU1 CGA"                                         "per , ""RST/CLK (Reset Clocking and Initialization),Clock,CGU1 CGA"""
menuitem "CGU2 CGB"                                         "per , ""RST/CLK (Reset Clocking and Initialization),Clock,CGU2 CGB"""
menuitem "CGU DDR Unit 1"                                   "per , ""RST/CLK (Reset Clocking and Initialization),Clock,CGU DDR Unit 1"""
menuitem "CGU DDR Unit 2"                                   "per , ""RST/CLK (Reset Clocking and Initialization),Clock,CGU DDR Unit 2"""
menuitem "CGU Core Cluster Unit"                            "per , ""RST/CLK (Reset Clocking and Initialization),Clock,CGU Core Cluster Unit"""
)
)
menuitem "ISC;Interrupt Sampling"                                   "per , ""ISC (Interrupt Sampling)"""
menuitem "DCFG;Device Configuration"                                "per , ""DCFG (Device Configuration)"""
menuitem "SCFG;Supplemental Configuration Unit"                     "per , ""SCFG (Supplemental Configuration Unit)"""
popup "DPAA2;Data Path Acceleration Architecture"
(
popup "QBMAN;Queue/Buffer Manager"
(
menuitem "QMAN_CCSR"                                        "per , ""DPAA2 (Data Path Acceleration Architecture),QBMAN (Queue/Buffer Manager),QMAN_CCSR"""
; popup "QMAN_SWP"
; (
; menuitem "Software Portal $2"                           "per , ""DPAA2 (Data Path Acceleration Architecture),QBMAN (Queue/Buffer Manager),QMAN_SWP,Software Portal $2"""
; menuitem "Software Portal $2 Alias"                     "per , ""DPAA2 (Data Path Acceleration Architecture),QBMAN (Queue/Buffer Manager),QMAN_SWP,Software Portal $2 Alias"""
; )
)
menuitem "MC;Management Complex"                                "per , ""DPAA2 (Data Path Acceleration Architecture),MC (Management Complex)"""
popup "WRIOP;Wire Rate IO Processor"
(
; popup "Interface Profile Record Registers"
; (
; menuitem "Ingress"                                      "per , ""DPAA2 (Data Path Acceleration Architecture),WRIOP (Wire Rate IO Processor),Interface Profile Record Registers,Ingress"""
; menuitem "Egress"                                       "per , ""DPAA2 (Data Path Acceleration Architecture),WRIOP (Wire Rate IO Processor),Interface Profile Record Registers,Egress"""
; )
; menuitem "Interface Profile Special Functions Registers"    "per , ""DPAA2 (Data Path Acceleration Architecture),WRIOP (Wire Rate IO Processor),Interface Profile Special Functions Registers"""
menuitem "Global Registers"                                 "per , ""DPAA2 (Data Path Acceleration Architecture),WRIOP (Wire Rate IO Processor),Global Registers"""
menuitem "Port Registers"                                   "per , ""DPAA2 (Data Path Acceleration Architecture),WRIOP (Wire Rate IO Processor),Port Registers"""
popup "CTLU"
(
menuitem "Ingress"                                      "per , ""DPAA2 (Data Path Acceleration Architecture),WRIOP (Wire Rate IO Processor),CTLU,Ingress"""
menuitem "Egress"                                       "per , ""DPAA2 (Data Path Acceleration Architecture),WRIOP (Wire Rate IO Processor),CTLU,Egress"""
)
)
menuitem "1588 TIM IP;1588 Timer IP Module"                     "per , ""DPAA2 (Data Path Acceleration Architecture),1588 TIM IP (1588 Timer IP Module)"""
menuitem "PEBM;Packet Express Buffer Memory"                    "per , ""DPAA2 (Data Path Acceleration Architecture),PEBM (Packet Express Buffer Memory)"""
; menuitem "CTLU_QOS;CTLU QoS Mapping and Policer"                "per , ""DPAA2 (Data Path Acceleration Architecture),CTLU_QOS (CTLU QoS Mapping and Policer)"""
menuitem "mEMAC;Multirate Ethernet Media Access Controller"     "per , ""DPAA2 (Data Path Acceleration Architecture),mEMAC (Multirate Ethernet Media Access Controller)"""
menuitem "MACSec"                                               "per , ""DPAA2 (Data Path Acceleration Architecture),MACSec"""
if cpuis("LS2088A")
(
popup "AIOP;Advanced IO Processor"
(
menuitem "CTLU"                                         "per , ""DPAA2 (Data Path Acceleration Architecture),AIOP (Advanced IO Processor),CTLU"""
)
)
menuitem "SEC;Security and Encryption"                          "per , ""DPAA2 (Data Path Acceleration Architecture),SEC (Security and Encryption)"""
menuitem "qDMA;Queue Direct Memory Access Controller"           "per , ""DPAA2 (Data Path Acceleration Architecture),qDMA (Queue Direct Memory Access Controller)"""
menuitem "PME;Pattern Matching Engine"                          "per , ""DPAA2 (Data Path Acceleration Architecture),PME (Pattern Matching Engine)"""
menuitem "DCE;Decompression/Compression Engine"                 "per , ""DPAA2 (Data Path Acceleration Architecture),DCE (Decompression/Compression Engine)"""
popup "PMU;Power Management Unit"
(
menuitem "COP_PMU_CCSR"                                     "per , ""DPAA2 (Data Path Acceleration Architecture),PMU (Power Management Unit),COP_PMU_CCSR"""
; menuitem "COP_PMU_DCSR"                                     "per , ""DPAA2 (Data Path Acceleration Architecture),PMU (Power Management Unit),COP_PMU_DCSR"""
)
)
popup "CCI;Cache Coherent Interconnect"
(
menuitem "MN Registers"                                         "per , ""CCI (Cache Coherent Interconnect),MN Registers"""
popup "XP Registers"
(
menuitem "XP ID 0;region 64"                                "per , ""CCI (Cache Coherent Interconnect),XP Registers,XP ID 0 (region 64)"""
menuitem "XP ID 1;region 65"                                "per , ""CCI (Cache Coherent Interconnect),XP Registers,XP ID 1 (region 65)"""
menuitem "XP ID 2;region 66"                                "per , ""CCI (Cache Coherent Interconnect),XP Registers,XP ID 2 (region 66)"""
menuitem "XP ID 3;region 67"                                "per , ""CCI (Cache Coherent Interconnect),XP Registers,XP ID 3 (region 67)"""
menuitem "XP ID 4;region 68"                                "per , ""CCI (Cache Coherent Interconnect),XP Registers,XP ID 4 (region 68)"""
menuitem "XP ID 5;region 69"                                "per , ""CCI (Cache Coherent Interconnect),XP Registers,XP ID 5 (region 69)"""
menuitem "XP ID 6;region 70"                                "per , ""CCI (Cache Coherent Interconnect),XP Registers,XP ID 6 (region 70)"""
menuitem "XP ID 7;region 71"                                "per , ""CCI (Cache Coherent Interconnect),XP Registers,XP ID 7 (region 71)"""
menuitem "XP ID 8;region 72"                                "per , ""CCI (Cache Coherent Interconnect),XP Registers,XP ID 8 (region 72)"""
menuitem "XP ID 9;region 73"                                "per , ""CCI (Cache Coherent Interconnect),XP Registers,XP ID 9 (region 73)"""
menuitem "XP ID 10;region 74"                               "per , ""CCI (Cache Coherent Interconnect),XP Registers,XP ID 10 (region 74)"""
)
popup "HN-F Registers"
(
menuitem "Node ID 3;region 32"                              "per , ""CCI (Cache Coherent Interconnect),HN-F Registers,Node ID 3 (region 32)"""
menuitem "Node ID 5;region 33"                              "per , ""CCI (Cache Coherent Interconnect),HN-F Registers,Node ID 5 (region 33)"""
menuitem "Node ID 7;region 34"                              "per , ""CCI (Cache Coherent Interconnect),HN-F Registers,Node ID 7 (region 34)"""
menuitem "Node ID 8;region 35"                              "per , ""CCI (Cache Coherent Interconnect),HN-F Registers,Node ID 8 (region 35)"""
menuitem "Node ID 13;region 36"                             "per , ""CCI (Cache Coherent Interconnect),HN-F Registers,Node ID 13 (region 36)"""
menuitem "Node ID 15;region 37"                             "per , ""CCI (Cache Coherent Interconnect),HN-F Registers,Node ID 15 (region 37)"""
menuitem "Node ID 17;region 38"                             "per , ""CCI (Cache Coherent Interconnect),HN-F Registers,Node ID 17 (region 38)"""
menuitem "Node ID 18;region 39"                             "per , ""CCI (Cache Coherent Interconnect),HN-F Registers,Node ID 18 (region 39)"""
)
menuitem "HN-I Registers"                                       "per , ""CCI (Cache Coherent Interconnect),HN-I Registers"""
popup "RN-I Bridge Register"
(
menuitem "Node ID 0;region 128"                             "per , ""CCI (Cache Coherent Interconnect),RN-I Bridge Register,Node ID 0 (region 128)"""
menuitem "Node ID 2;region 130"                             "per , ""CCI (Cache Coherent Interconnect),RN-I Bridge Register,Node ID 2 (region 130)"""
menuitem "Node ID 6;region 134"                             "per , ""CCI (Cache Coherent Interconnect),RN-I Bridge Register,Node ID 6 (region 134)"""
menuitem "Node ID 12;region 140"                            "per , ""CCI (Cache Coherent Interconnect),RN-I Bridge Register,Node ID 12 (region 140)"""
menuitem "Node ID 16;region 144"                            "per , ""CCI (Cache Coherent Interconnect),RN-I Bridge Register,Node ID 16 (region 144)"""
menuitem "Node ID 20;region 148"                            "per , ""CCI (Cache Coherent Interconnect),RN-I Bridge Register,Node ID 20 (region 148)"""
)
popup "SBSX Registers"
(
menuitem "Node ID 4;region 16"                              "per , ""CCI (Cache Coherent Interconnect),SBSX Registers,Node ID 4 (region 16)"""
menuitem "Node ID 14;region 17"                             "per , ""CCI (Cache Coherent Interconnect),SBSX Registers,Node ID 14 (region 17)"""
)
)
popup "DDR;DDR Memory Controllers"
(
menuitem "DDR1"                                                 "per , ""DDR (DDR Memory Controllers),DDR1"""
menuitem "DDR2"                                                 "per , ""DDR (DDR Memory Controllers),DDR2"""
)
popup "DUART;Dual Universal Asynchronous Receiver/Transmitter"
(
popup "DUART 1"
(
menuitem "UART 1"                                           "per , ""DUART (Dual Universal Asynchronous Receiver/Transmitter),DUART 1,UART 1"""
menuitem "UART 2"                                           "per , ""DUART (Dual Universal Asynchronous Receiver/Transmitter),DUART 1,UART 2"""
)
popup "DUART 2"
(
menuitem "UART 3"                                           "per , ""DUART (Dual Universal Asynchronous Receiver/Transmitter),DUART 2,UART 3"""
menuitem "UART 4"                                           "per , ""DUART (Dual Universal Asynchronous Receiver/Transmitter),DUART 2,UART 4"""
)
)
menuitem "eSDHC;Enhanced Secured Digital Host Controller"           "per , ""eSDHC (Enhanced Secured Digital Host Controller)"""
popup "FTM;FlexTimer Module"
(
menuitem "FlexTimer 1"                                          "per , ""FTM (FlexTimer Module),FlexTimer 1"""
menuitem "FlexTimer 2"                                          "per , ""FTM (FlexTimer Module),FlexTimer 2"""
menuitem "FlexTimer 3"                                          "per , ""FTM (FlexTimer Module),FlexTimer 3"""
menuitem "FlexTimer 4"                                          "per , ""FTM (FlexTimer Module),FlexTimer 4"""
)
popup "GPIO;General Purpose I/O"
(
menuitem "GPIO 1"                                               "per , ""GPIO (General Purpose I/O),GPIO 1"""
menuitem "GPIO 2"                                               "per , ""GPIO (General Purpose I/O),GPIO 2"""
menuitem "GPIO 3"                                               "per , ""GPIO (General Purpose I/O),GPIO 3"""
menuitem "GPIO 4"                                               "per , ""GPIO (General Purpose I/O),GPIO 4"""
)
menuitem "IFC;Integrated Flash Controller"                          "per , ""IFC (Integrated Flash Controller)"""
popup "I2C;Inter-Integrated Circuit"
(
menuitem "I2C 1"                                                "per , ""I2C (Inter-Integrated Circuit),I2C 1"""
menuitem "I2C 2"                                                "per , ""I2C (Inter-Integrated Circuit),I2C 2"""
menuitem "I2C 3"                                                "per , ""I2C (Inter-Integrated Circuit),I2C 3"""
menuitem "I2C 4"                                                "per , ""I2C (Inter-Integrated Circuit),I2C 4"""
)
popup "PEX;PCI Express Interface Controller"
(
menuitem "PEX 1"                                                "per , ""PEX (PCI Express Interface Controller),PEX 1"""
menuitem "PEX 2"                                                "per , ""PEX (PCI Express Interface Controller),PEX 2"""
menuitem "PEX 3"                                                "per , ""PEX (PCI Express Interface Controller),PEX 3"""
menuitem "PEX 4"                                                "per , ""PEX (PCI Express Interface Controller),PEX 4"""
)
menuitem "PMU;Power Management Unit"                                "per , ""PMU (Power Management Unit)"""
menuitem "QuadSPI;Quad Serial Peripheral Interface"                 "per , ""QuadSPI (Quad Serial Peripheral Interface)"""
popup "SATA 3.0;Serial ATA 3.0"
(
menuitem "SATA 1"                                               "per , ""SATA 3.0 (Serial ATA 3.0),SATA 1"""
menuitem "SATA 2"                                               "per , ""SATA 3.0 (Serial ATA 3.0),SATA 2"""
)
popup "SerDes;SerDes Module"
(
menuitem "Serdes 1"                                             "per , ""SerDes (SerDes Module),Serdes 1"""
menuitem "Serdes 2"                                             "per , ""SerDes (SerDes Module),Serdes 2"""
; menuitem "MDIO;Management Data In/Out"                          "per , ""SerDes (SerDes Module),MDIO (Management Data In/Out)"""
)
menuitem "SPI;Serial Peripheral Interface"                          "per , ""SPI (Serial Peripheral Interface)"""
popup "TZM;TrustZone Modules"
(
popup "TZC-400;TrustZone Address Space Controller"
(
menuitem "TZC 1"                                            "per , ""TZM (TrustZone Modules),TZC-400 (TrustZone Address Space Controller),TZC 1"""
menuitem "TZC 2"                                            "per , ""TZM (TrustZone Modules),TZC-400 (TrustZone Address Space Controller),TZC 2"""
)
menuitem "TZPC;TrustZone Protection Controller"                 "per , ""TZM (TrustZone Modules),TZPC (TrustZone Protection Controller)"""
)
menuitem "TMU;Thermal Monitoring Unit"                              "per , ""TMU (Thermal Monitoring Unit)"""
popup "USB;Universal Serial Bus Interface 3.0"
(
menuitem "USB 1"                                                "per , ""USB (Universal Serial Bus Interface 3.0),USB 1"""
menuitem "USB 2"                                                "per , ""USB (Universal Serial Bus Interface 3.0),USB 2"""
menuitem "USB PHY SS 1"                                         "per , ""USB (Universal Serial Bus Interface 3.0),USB PHY SS 1"""
menuitem "USB PHY SS 2"                                         "per , ""USB (Universal Serial Bus Interface 3.0),USB PHY SS 2"""
)
popup "WDOG;Watchdog Timer Unit"
(
menuitem "TrustZone WDOG"                                       "per , ""WDOG (Watchdog Timer Unit),TrustZone WDOG"""
menuitem "WDOG 1"                                               "per , ""WDOG (Watchdog Timer Unit),WDOG 1"""
menuitem "WDOG 2"                                               "per , ""WDOG (Watchdog Timer Unit),WDOG 2"""
menuitem "WDOG 3"                                               "per , ""WDOG (Watchdog Timer Unit),WDOG 3"""
menuitem "WDOG 4"                                               "per , ""WDOG (Watchdog Timer Unit),WDOG 4"""
if !cpuis("LS2048A*")&&!cpuis("LS2044A*")
(
menuitem "WDOG 5"                                           "per , ""WDOG (Watchdog Timer Unit),WDOG 5"""
menuitem "WDOG 6"                                           "per , ""WDOG (Watchdog Timer Unit),WDOG 6"""
menuitem "WDOG 7"                                           "per , ""WDOG (Watchdog Timer Unit),WDOG 7"""
menuitem "WDOG 8"                                           "per , ""WDOG (Watchdog Timer Unit),WDOG 8"""
)
)
menuitem "EPU;Event Processing Unit"                                "per , ""EPU (Event Processing Unit)"""
)
)