; -------------------------------------------------------------------------------- ; @Title: Halo specific menu (Cortex-M0) ; @Props: Released ; @Author: KAO, WIL, KMB ; @Changelog: ; 2016-04-20 WIL ; 2017-01-26 KMB ; @Manufacturer: NXP ; @Core: Cortex-M0 ; @Chip: MAC57D54H-CM0 ; @Copyright: (C) 1989-2016 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: menhalocm0.men 16339 2023-07-03 13:30:14Z pegold $ add menu ( IF SOFTWARE.BUILD.BASE()>=69655. ( popup "&CPU" ( separator IF CPU.FEATURE(MMU) ( popup "[:mmu]MMU" ( menuitem "[:mmureg]MMU Control" "MMU.view" separator menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable" menuitem "[:mmu]MMU Table List" "MMU.List.PageTable" separator IF CPU.FEATURE(ITLBDUMP) ( menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB" ) IF CPU.FEATURE(DTLBDUMP) ( menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB" ) IF CPU.FEATURE(TLB0DUMP) ( menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0" ) IF CPU.FEATURE(TLB1DUMP) ( menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1" ) ) ) IF COMPonent.AVAILable("SMMU") ( popup "[:mmu]SMMU" ( menuitem "[:chip]SMMU1 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU1 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.)) SMMU.StreamMapTable &(name) ) IF COMPonent.AVAILable("SMMU2") ( separator menuitem "[:chip]SMMU2 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU2 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU3") ( separator menuitem "[:chip]SMMU3 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU3 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU4") ( separator menuitem "[:chip]SMMU4 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU4 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU5") ( separator menuitem "[:chip]SMMU5 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU5 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU6") ( separator menuitem "[:chip]SMMU6 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU6 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.)) SMMU.StreamMapTable &(name) ) ) ) ) IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE) ( popup "[:cache]Cache" ( IF CPU.FEATURE(L1ICACHEDUMP) ( menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC" menuitem "[:cache]ICACHE List" "CACHE.List IC" menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC" ) IF CPU.FEATURE(L1DCACHEDUMP) ( separator menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC" menuitem "[:cache]DCACHE List" "CACHE.List DC" menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC" ) IF CPU.FEATURE(L2CACHEDUMP) ( separator menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2" menuitem "[:cache]L2CACHE List" "CACHE.List L2" menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2" ) ) ) ) popup "&Trace" ( separator IF COMPonent.AVAILable("ITM") ( popup "ITM" ( default menuitem "[:oconfig]ITM settings..." "ITM.state" separator menuitem "[:alist]ITMTrace List" "ITMTrace.List" ) ) IF COMPonent.AVAILable("STM") ( popup "STM" ( default menuitem "[:oconfig]STM settings..." "STM.state" separator menuitem "[:alist]STMTrace List" "STMTrace.List" ) ) IF COMPonent.AVAILable("HTM") ( popup "HTM" ( default menuitem "[:oconfig]HTM settings..." "HTM.state" separator menuitem "[:alist]HTMTrace List" "HTMTrace.List" ) ) IF COMPonent.AVAILable("TPIU") ( menuitem "[:oconfig]TPIU settings..." "TPIU.state" ) IF COMPonent.AVAILable("ETR") ( menuitem "[:oconfig]ETR settings..." ( PRIVATE &pdd &pdd=OS.PDD() DO "&pdd/etc/embedded_trace_router/etr_utility.cmm" ) ) ) popup "&Misc" ( popup "Tools" ( IF CPUIS64BIT()||CPU.FEATURE("SPR") ( menuitem "ARM System Register Converter" ( DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm" ) ) IF CPU.FEATURE("C15") ( menuitem "ARM Coprocessor Converter" ( DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm" ) ) ) ) popup "&Perf" ( IF CPU.FEATURE(BMC) ( before "Reset" menuitem "[:bmc]Benchmark Counters" "BMC.state" before "Reset" separator ) ) ) popup "Peripherals" ( popup "[:chip]Core Registers (Cortex-M0+)" ( menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M0+),System Control""" menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M0+),Memory Protection Unit (MPU)""" menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M0+),Nested Vectored Interrupt Controller (NVIC)""" popup "[:chip]Debug" ( menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M0+),Debug,Core Debug""" menuitem "[:chip]BPU;Breakpoint Unit" "per , ""Core Registers (Cortex-M0+),Debug,Breakpoint Unit (BPU)""" menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M0+),Debug,Data Watchpoint and Trace Unit (DWT)""" ) ) separator menuitem "IOP" "per , ""IO Processor (IOP)""" menuitem "SIUL2" "per , ""System Integration Unit Lite2 (SIUL2)""" popup "AIPS" ( menuitem "AIPS 0" "per , ""Peripheral Bridge (AIPS),AIPS 0""" menuitem "AIPS 1" "per , ""Peripheral Bridge (AIPS),AIPS 1""" ) menuitem "AXBS" "per , ""AHB Crossbar Switch (AXBS)""" menuitem "QoS301" "per , ""QoS301""" menuitem "SEMA42" "per , ""Semaphores2 (SEMA42)""" popup "MSCM" ( menuitem "MSCM CPU" "per , ""Miscellaneous System Control Module (MSCM),MSCM CPU""" menuitem "MSCM On-Chip Memory" "per , ""Miscellaneous System Control Module (MSCM),MSCM On-Chip Memory""" menuitem "MSCM Interrupts" "per , ""Miscellaneous System Control Module (MSCM),MSCM Interrupts""" ) menuitem "XRDC" "per , ""Extended Resource Domain Controller (XRDC)""" menuitem "WKPU" "per , ""Wake-up Unit (WKPU)""" menuitem "EIM" "per , ""Error Injection Module (EIM)""" menuitem "ERM" "per , ""Error Reporting Module (ERM)""" menuitem "MPR" "per , ""Multi Purpose Register Bank (MPR)""" popup "PLLDIG" ( menuitem "PLL0" "per , ""PLL Digital Interface (PLLDIG),PLL0""" menuitem "PLL1" "per , ""PLL Digital Interface (PLLDIG),PLL1""" menuitem "PLL2" "per , ""PLL Digital Interface (PLLDIG),PLL2""" menuitem "PLL3" "per , ""PLL Digital Interface (PLLDIG),PLL3""" ) menuitem "FIRC" "per , ""Fast internal 16 MHz RC oscillator (FIRC)""" menuitem "SIRC" "per , ""Slow internal 128 kHz oscillator (SIRC)""" menuitem "SXOSC" "per , ""Slow external 32 KHz oscillator (SXOSC)""" menuitem "FXOSC_CTL" "per , ""FXOSC Control Register (FXOSC_CTL)""" menuitem "CMU" "per , ""Clock Monitor Unit (CMU)""" menuitem "MC_CGM" "per , ""Clock Generation Module (MC_CGM)""" popup "TCON" ( menuitem "TCON" "per , ""Timing Controller (TCON),TCON""" menuitem "TCON_1" "per , ""Timing Controller (TCON),TCON_1""" ) popup "DCU" ( menuitem "DCU_0" "per , ""Display Controller Unit (DCU),DCU_0""" menuitem "DCU_1" "per , ""Display Controller Unit (DCU),DCU_1""" ) menuitem "GPU2D Memory Map/Register Definition" "per , ""GC355 Vector Graphics Processing Unit (GC355)""" menuitem "RLE_DEC" "per , ""Run Length Encoding Decoder (RLE_DEC)""" menuitem "LVDS Display Bridge" "per , ""LDB (LVDS Display Bridge)""" menuitem "VIU4" "per , ""Video-In (VIU4)""" menuitem "LCD64F6B" "per , ""LCD Driver (LCD64F6B)""" menuitem "ADC" "per , ""Analog-to-Digital Converted (ADC)""" popup "CMP" ( menuitem "CMP0" "per , ""Analogue Comparator (CMP),CMP0""" menuitem "CMP1" "per , ""Analogue Comparator (CMP),CMP1""" ) popup "FTM" ( menuitem "FTM0" "per , ""FlexTimer Module (FTM),FTM0""" menuitem "FTM1" "per , ""FlexTimer Module (FTM),FTM1""" menuitem "FTM2" "per , ""FlexTimer Module (FTM),FTM2""" menuitem "FTM3" "per , ""FlexTimer Module (FTM),FTM3""" ) popup "SWT" ( menuitem "SWT0" "per , ""Software Watchdog (SWT),SWT0""" menuitem "SWT1" "per , ""Software Watchdog (SWT),SWT1""" menuitem "SWT2" "per , ""Software Watchdog (SWT),SWT2""" ) popup "STM" ( menuitem "STM0" "per , ""System Timer Module (STM),STM0""" menuitem "STM1" "per , ""System Timer Module (STM),STM1""" ) menuitem "PIT" "per , ""Periodic Interrupt Timer (PIT)""" menuitem "RTC" "per , ""Real Time Clock (RTC)""" menuitem "MC_PCU" "per , ""Power Control Unit (MC_PCU)""" menuitem "MC_ME" "per , ""Mode Entry Module (MC_ME)""" menuitem "PMCDIG" "per , ""Power Management Controller digital interface (PMCDIG)""" menuitem "MLB" "per , ""Media Local Bus Block (MLB)""" popup "FlexCAN" ( menuitem "CAN0" "per , ""FlexCAN,CAN0""" menuitem "CAN1" "per , ""FlexCAN,CAN1""" menuitem "CAN2" "per , ""FlexCAN,CAN2""" ) popup "I2C" ( menuitem "I2C_0" "per , ""Inter-Integrated Circuit (I2C),I2C_0""" menuitem "I2C_1" "per , ""Inter-Integrated Circuit (I2C),I2C_1""" ) popup "SPI" ( menuitem "SPI_0" "per , ""Serial Peripheral Interface (SPI),SPI_0""" menuitem "SPI_1" "per , ""Serial Peripheral Interface (SPI),SPI_1""" menuitem "SPI_2" "per , ""Serial Peripheral Interface (SPI),SPI_2""" menuitem "SPI_3" "per , ""Serial Peripheral Interface (SPI),SPI_3""" menuitem "SPI_4" "per , ""Serial Peripheral Interface (SPI),SPI_4""" ) popup "LINFlex" ( menuitem "LINFlex_0" "per , ""LIN CONTROLLER (LINFlex),LINFlex_0""" menuitem "LINFlex_1" "per , ""LIN CONTROLLER (LINFlex),LINFlex_1""" menuitem "LINFlex_2" "per , ""LIN CONTROLLER (LINFlex),LINFlex_2""" ) menuitem "ENET" "per , ""10/100-Mbps Ethernet MAC (ENET)""" menuitem "SGM" "per , ""Sound Generator Module (SGM)""" popup "SSD" ( menuitem "SSD 0" "per , ""Stepper Stall Detect (SSD),SSD 0""" menuitem "SSD 1" "per , ""Stepper Stall Detect (SSD),SSD 1""" menuitem "SSD 2" "per , ""Stepper Stall Detect (SSD),SSD 2""" menuitem "SSD 3" "per , ""Stepper Stall Detect (SSD),SSD 3""" menuitem "SSD 4" "per , ""Stepper Stall Detect (SSD),SSD 4""" menuitem "SSD 5" "per , ""Stepper Stall Detect (SSD),SSD 5""" ) menuitem "SMC" "per , ""Stepper Motor Controller (SMC)""" menuitem "SSCM" "per , ""System Status and Configuration Module (SSCM)""" menuitem "MC_RGM" "per , ""Reset Generation Module (MC_RGM)""" popup "EDMA" ( menuitem "DMA0" "per , ""Enhanced Direct Memory Access (EDMA),DMA0""" menuitem "DMA1" "per , ""Enhanced Direct Memory Access (EDMA),DMA1""" ) menuitem "DMA_MUX" "per , ""Direct Memory Access Multiplexer (DMA_MUX)""" menuitem "PFLASH" "per , ""Flash memory controller (PFLASH)""" popup "PRAMC" ( menuitem "PRAMC_0" "per , ""RAM Controller (PRAMC),PRAMC_0""" menuitem "PRAMC_1" "per , ""RAM Controller (PRAMC),PRAMC_1""" ) menuitem "c55fmc" "per , ""Embedded Flash Memory (c55fmc)""" menuitem "MDDRC" "per , ""Multi-Port DRAM Controller (MDDRC)""" menuitem "DDRC_PRIOMAN" "per , ""DRAM Controller Priority Manager (DDRC_PRIOMAN)""" popup "QuadSPI" ( menuitem "QSPI0" "per , ""Quad Serial Peripheral Interface (QuadSPI),QSPI0""" menuitem "QSPI1" "per , ""Quad Serial Peripheral Interface (QuadSPI),QSPI1""" ) menuitem "LMEM" "per , ""Local Memory Controller (LMEM)""" menuitem "JDC" "per , ""JTAG Data Communication (JDC)""" menuitem "FCCU" "per , ""Fault Collection and Control Unit (FCCU)""" menuitem "STCU2" "per , ""Self Test Control Unit (STCU2)""" menuitem "CRC" "per , ""Cyclic Redundancy Check (CRC)""" menuitem "TDM" "per , ""Tamper Detection Module (TDM)""" menuitem "PASS" "per , ""Password and Device Security Module (PASS)""" menuitem "CSE" "per , ""Cryptographic Services Engine (CSE)""" ) )