; --------------------------------------------------------------------------------
; @Title: AWR2944 Specific Menu
; @Props: Released
; @Author: KMB, ADR, KRZ, NEJ
; @Changelog: 2021-08-30 KMB
;             2021-12-14 ADR
;             2022-04-26 KRZ
;             2023-11-14 NEJ
; @Manufacturer: TI - Texas Instruments
; @Core: Cortex-M4, Cortex-R5F, C66x
; @Chip: AWR2944, AWR2944-HSM, AWR2944-HWA, AWR2944DSP
; @Copyright: (C) 1989-2023 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: menawr2944.men 17044 2023-11-21 16:23:45Z kwisniewski $

add
menu
(
if (CPUFAMILY()=="C6000")
(
popup "&CPU"
(
after "FPU Registers"
separator
popup "[:cache]Cache"
(
menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
menuitem "[:cache]ICACHE List" "CACHE.List IC"
menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
separator
menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
menuitem "[:cache]DCACHE List" "CACHE.List DC"
menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
separator
menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
menuitem "[:cache]L2CACHE List" "CACHE.List L2"
menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
)
)
popup "&Trace"
(
IF COMPonent.AVAILable("TPIU")
(
menuitem "[:oconfig]TPIU settings..." "TPIU.state"
)
IF COMPonent.AVAILable("AET")
(
menuitem "[:oconfig]AET settings..." "AET.state"
)
)
popup "&Perf"
(
before "Reset"
menuitem "[:bmc]Benchmark Counters" "BMC.state"
before "Reset"
separator
)
)
else
(
IF SOFTWARE.BUILD.BASE()>=69655.
(
popup "&CPU"
(
separator
IF CPU.FEATURE(MMU)
(
popup "[:mmu]MMU"
(
menuitem "[:mmureg]MMU Control" "MMU.view"
separator
menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
separator
IF CPU.FEATURE(ITLBDUMP)
(
menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
)
IF CPU.FEATURE(DTLBDUMP)
(
menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
)
IF CPU.FEATURE(TLB0DUMP)
(
menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
)
IF CPU.FEATURE(TLB1DUMP)
(
menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
)
)
)
IF COMPonent.AVAILable("SMMU")
(
popup "[:mmu]SMMU"
(
menuitem "[:chip]SMMU1 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU1 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.StreamMapTable &(name)
)
IF COMPonent.AVAILable("SMMU2")
(
separator
menuitem "[:chip]SMMU2 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU2 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU3")
(
separator
menuitem "[:chip]SMMU3 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU3 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU4")
(
separator
menuitem "[:chip]SMMU4 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU4 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU5")
(
separator
menuitem "[:chip]SMMU5 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU5 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU6")
(
separator
menuitem "[:chip]SMMU6 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU6 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.StreamMapTable &(name)
)
)
)
)
IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
(
popup "[:cache]Cache"
(
IF CPU.FEATURE(L1ICACHEDUMP)
(
menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
menuitem "[:cache]ICACHE List" "CACHE.List IC"
menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
)
IF CPU.FEATURE(L1DCACHEDUMP)
(
separator
menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
menuitem "[:cache]DCACHE List" "CACHE.List DC"
menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
)
IF CPU.FEATURE(L2CACHEDUMP)
(
separator
menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
menuitem "[:cache]L2CACHE List" "CACHE.List L2"
menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
)
)
)
)
popup "&Trace"
(
separator
IF COMPonent.AVAILable("ITM")
(
popup "ITM"
(
default
menuitem "[:oconfig]ITM settings..." "ITM.state"
separator
menuitem "[:alist]ITMTrace List" "ITMTrace.List"
)
)
IF COMPonent.AVAILable("STM")
(
popup "STM"
(
default
menuitem "[:oconfig]STM settings..." "STM.state"
separator
menuitem "[:alist]STMTrace List" "STMTrace.List"
)
)
IF COMPonent.AVAILable("HTM")
(
popup "HTM"
(
default
menuitem "[:oconfig]HTM settings..." "HTM.state"
separator
menuitem "[:alist]HTMTrace List" "HTMTrace.List"
)
)
IF COMPonent.AVAILable("TPIU")
(
menuitem "[:oconfig]TPIU settings..." "TPIU.state"
)
IF COMPonent.AVAILable("ETR")
(
menuitem "[:oconfig]ETR settings..."
(
PRIVATE &pdd
&pdd=OS.PDD()
DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
)
)
)
popup "&Misc"
(
popup "Tools"
(
IF CPUIS64BIT()||CPU.FEATURE("SPR")
(
menuitem "ARM System Register Converter"
(
DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
)
)
IF CPU.FEATURE("C15")
(
menuitem "ARM Coprocessor Converter"
(
DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
)
)
)
)
popup "&Perf"
(
IF CPU.FEATURE(BMC)
(
before "Reset"
menuitem "[:bmc]Benchmark Counters" "BMC.state"
before "Reset"
separator
)
)
)
)
popup "Peripherals"
(
if (CORENAME()=="CORTEXM4")
(
popup "[:chip]Core Registers (Cortex-M4)"
(
menuitem "[:chip]System Control"                                "per , ""Core Registers (Cortex-M4),System Control"""
menuitem "[:chip]MPU;Memory Protection Unit"                    "per , ""Core Registers (Cortex-M4),Memory Protection Unit"""
menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller"     "per , ""Core Registers (Cortex-M4),Nested Vectored Interrupt Controller"""
popup "[:chip]Debug"
(
menuitem "[:chip]Core Debug"                                "per , ""Core Registers (Cortex-M4),Debug,Core Debug"""
menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit"       "per , ""Core Registers (Cortex-M4),Debug,Flash Patch and Breakpoint Unit (FPB)"""
menuitem "[:chip]DWT;Data Watchpoint and Trace Unit"        "per , ""Core Registers (Cortex-M4),Debug,Data Watchpoint and Trace Unit (DWT)"""
)
)
)
else if (CORENAME()=="CORTEXR5F")
(
popup "[:chip]Core Registers (Cortex-R5F)"
(
menuitem "[:chip]ID Registers"                      "per , ""Core Registers (Cortex-R5F),ID Registers"""
menuitem "[:chip]System Control and Configuration"  "per , ""Core Registers (Cortex-R5F),System Control and Configuration"""
menuitem "[:chip]MPU Control and Configuration"     "per , ""Core Registers (Cortex-R5F),MPU Control and Configuration"""
menuitem "[:chip]Cache Control and Configuration"   "per , ""Core Registers (Cortex-R5F),Cache Control and Configuration"""
menuitem "[:chip]TCM Control and Configuration"     "per , ""Core Registers (Cortex-R5F),TCM Control and Configuration"""
menuitem "[:chip]System Performance Monitor"        "per , ""Core Registers (Cortex-R5F),System Performance Monitor"""
separator
menuitem "[:chip]Debug Registers"                   "per , ""Core Registers (Cortex-R5F),Debug Registers"""
menuitem "[:chip]Breakpoint Registers"              "per , ""Core Registers (Cortex-R5F),Breakpoint Registers"""
menuitem "[:chip]Watchpoint Control Registers"      "per , ""Core Registers (Cortex-R5F),Watchpoint Control Registers"""
)
)
else
(
popup "[:chip]Core Registers (c66x)"
(
menuitem "[:chip]L1P;L1P Registers"                    "per , ""Core Registers (c66x),Cache,L1P Cache"""
menuitem "[:chip]L1D;L1D Registers"                    "per , ""Core Registers (c66x),Cache,L1D Cache"""
menuitem "[:chip]L2;L2 Registers"                      "per , ""Core Registers (c66x),Cache,L2 Cache"""
menuitem "[:chip]IDMA;IDMA Registers"                  "per , ""Core Registers (c66x),IDMA (Internal Direct Memory Access Controller)"""
menuitem "[:chip]XMC;XMC Registers"                    "per , ""Core Registers (c66x),XMC (Extended Memory Controller)"""
menuitem "[:chip]BM;BM Registers"                      "per , ""Core Registers (c66x),Bandwith Management"""
menuitem "[:chip]IC;IC Registers"                      "per , ""Core Registers (c66x),Interrupt Controller"""
menuitem "[:chip]PD;PD Registers"                      "per , ""Core Registers (c66x),Power-Down Controller"""
)
)
separator
if (cpuis("AWR2944DSP"))
(
menuitem "DSP_ICFG"                     "per , ""DSP_ICFG"""
)
menuitem "DSS_CBUFF"                        "per , ""DSS_CBUFF"""
menuitem "DSS_CTRL"                         "per , ""DSS_CTRL"""
menuitem "DSS_DCCA"                         "per , ""DSS_DCCA"""
menuitem "DSS_DCCB"                         "per , ""DSS_DCCB"""
menuitem "DSS_DSP_PBIST"                    "per , ""DSS_DSP_PBIST"""
menuitem "DSS_DSP_STC"                      "per , ""DSS_DSP_STC"""
menuitem "DSS_ECC_AGG"                      "per , ""DSS_ECC_AGG"""
menuitem "DSS_ESM"                          "per , ""DSS_ESM"""
menuitem "DSS_HWA_CFG"                      "per , ""DSS_HWA_CFG"""
menuitem "DSS_MCRC"                         "per , ""DSS_MCRC"""
menuitem "DSS_PCR"                          "per , ""DSS_PCR"""
menuitem "DSS_RCM"                          "per , ""DSS_RCM"""
menuitem "DSS_RTIA"                         "per , ""DSS_RTIA"""
menuitem "DSS_RTIB"                         "per , ""DSS_RTIB"""
menuitem "DSS_SCIA"                         "per , ""DSS_SCIA"""
menuitem "DSS_TPCC_A"                       "per , ""DSS_TPCC_A"""
menuitem "DSS_TPCC_B"                       "per , ""DSS_TPCC_B"""
menuitem "DSS_TPCC_C"                       "per , ""DSS_TPCC_C"""
menuitem "DSS_TPTC_A0"                      "per , ""DSS_TPTC_A0"""
menuitem "DSS_TPTC_A1"                      "per , ""DSS_TPTC_A1"""
menuitem "DSS_TPTC_B0"                      "per , ""DSS_TPTC_B0"""
menuitem "DSS_TPTC_B1"                      "per , ""DSS_TPTC_B1"""
menuitem "DSS_TPTC_C0"                      "per , ""DSS_TPTC_C0"""
menuitem "DSS_TPTC_C1"                      "per , ""DSS_TPTC_C1"""
menuitem "DSS_TPTC_C2"                      "per , ""DSS_TPTC_C2"""
menuitem "DSS_TPTC_C3"                      "per , ""DSS_TPTC_C3"""
menuitem "DSS_TPTC_C4"                      "per , ""DSS_TPTC_C4"""
menuitem "DSS_TPTC_C5"                      "per , ""DSS_TPTC_C5"""
menuitem "DSS_WDT"                          "per , ""DSS_WDT"""
menuitem "MPU_DSS_HWA_DMA0"                 "per , ""MPU_DSS_HWA_DMA0"""
menuitem "MPU_DSS_HWA_DMA1"                 "per , ""MPU_DSS_HWA_DMA1"""
menuitem "MPU_DSS_HWA_PROC"                 "per , ""MPU_DSS_HWA_PROC"""
menuitem "MPU_DSS_L3_BANKA"                 "per , ""MPU_DSS_L3_BANKA"""
menuitem "MPU_DSS_L3_BANKB"                 "per , ""MPU_DSS_L3_BANKB"""
menuitem "MPU_DSS_L3_BANKC"                 "per , ""MPU_DSS_L3_BANKC"""
menuitem "MPU_DSS_L3_BANKD"                 "per , ""MPU_DSS_L3_BANKD"""
menuitem "MPU_DSS_MBOX"                     "per , ""MPU_DSS_MBOX"""
menuitem "MPU_MSS_CR5A_AXIS"                "per , ""MPU_MSS_CR5A_AXIS"""
menuitem "MPU_MSS_CR5B_AXIS"                "per , ""MPU_MSS_CR5B_AXIS"""
menuitem "MPU_MSS_L2_BANKA"                 "per , ""MPU_MSS_L2_BANKA"""
menuitem "MPU_MSS_L2_BANKB"                 "per , ""MPU_MSS_L2_BANKB"""
menuitem "MPU_MSS_MBOX"                     "per , ""MPU_MSS_MBOX"""
menuitem "MPU_MSS_PCRA"                     "per , ""MPU_MSS_PCRA"""
menuitem "MPU_MSS_QSPI"                     "per , ""MPU_MSS_QSPI"""
menuitem "MSS_CCMR"                         "per , ""MSS_CCMR"""
menuitem "MSS_CPSW"                         "per , ""MSS_CPSW"""
menuitem "MSS_CTRL"                         "per , ""MSS_CTRL"""
menuitem "MSS_DCCA"                         "per , ""MSS_DCCA"""
menuitem "MSS_DCCB"                         "per , ""MSS_DCCB"""
menuitem "MSS_DCCC"                         "per , ""MSS_DCCC"""
menuitem "MSS_DCCD"                         "per , ""MSS_DCCD"""
menuitem "MSS_DMM_A"                        "per , ""MSS_DMM_A"""
menuitem "MSS_DMM_B"                        "per , ""MSS_DMM_B"""
menuitem "MSS_ECC_AGG_MSS"                  "per , ""MSS_ECC_AGG_MSS"""
menuitem "MSS_ECC_AGG_R5A"                  "per , ""MSS_ECC_AGG_R5A"""
menuitem "MSS_ECC_AGG_R5B"                  "per , ""MSS_ECC_AGG_R5B"""
menuitem "MSS_ESM"                          "per , ""MSS_ESM"""
menuitem "MSS_ETPWMA"                       "per , ""MSS_ETPWMA"""
menuitem "MSS_ETPWMB"                       "per , ""MSS_ETPWMB"""
menuitem "MSS_ETPWMC"                       "per , ""MSS_ETPWMC"""
menuitem "MSS_GIO"                          "per , ""MSS_GIO"""
menuitem "MSS_GPADC_DATA_RAM"               "per , ""MSS_GPADC_DATA_RAM"""
menuitem "MSS_GPADC_PKT_RAM"                "per , ""MSS_GPADC_PKT_RAM"""
menuitem "MSS_GPADC_REG"                    "per , ""MSS_GPADC_REG"""
menuitem "MSS_I2C"                          "per , ""MSS_I2C"""
menuitem "MSS_IOMUX"                        "per , ""MSS_IOMUX"""
menuitem "MSS_MCANA_CFG"                    "per , ""MSS_MCANA_CFG"""
menuitem "MSS_MCANA_ECC"                    "per , ""MSS_MCANA_ECC"""
menuitem "MSS_MCANB_CFG"                    "per , ""MSS_MCANB_CFG"""
menuitem "MSS_MCANB_ECC"                    "per , ""MSS_MCANB_ECC"""
menuitem "MSS_MCRC"                         "per , ""MSS_MCRC"""
menuitem "MSS_PCR1"                         "per , ""MSS_PCR1"""
menuitem "MSS_PCR2"                         "per , ""MSS_PCR2"""
menuitem "MSS_QSPI"                         "per , ""MSS_QSPI"""
menuitem "MSS_R5SS_STC"                     "per , ""MSS_R5SS_STC"""
menuitem "MSS_RCM"                          "per , ""MSS_RCM"""
menuitem "MSS_RTIA"                         "per , ""MSS_RTIA"""
menuitem "MSS_RTIB"                         "per , ""MSS_RTIB"""
menuitem "MSS_RTIC"                         "per , ""MSS_RTIC"""
menuitem "MSS_SCIA"                         "per , ""MSS_SCIA"""
menuitem "MSS_SCIB"                         "per , ""MSS_SCIB"""
menuitem "MSS_SPIA"                         "per , ""MSS_SPIA"""
menuitem "MSS_SPIB"                         "per , ""MSS_SPIB"""
menuitem "MSS_TOPRCM"                       "per , ""MSS_TOPRCM"""
menuitem "MSS_TPCC_A"                       "per , ""MSS_TPCC_A"""
menuitem "MSS_TPCC_B"                       "per , ""MSS_TPCC_B"""
menuitem "MSS_TPTC_A0"                      "per , ""MSS_TPTC_A0"""
menuitem "MSS_TPTC_A1"                      "per , ""MSS_TPTC_A1"""
menuitem "MSS_TPTC_B0"                      "per , ""MSS_TPTC_B0"""
menuitem "MSS_VIM_R5A"                      "per , ""MSS_VIM_R5A"""
menuitem "MSS_VIM_R5B"                      "per , ""MSS_VIM_R5B"""
menuitem "MSS_WDT"                          "per , ""MSS_WDT"""
menuitem "RSS_CSI2A"                        "per , ""RSS_CSI2A"""
menuitem "RSS_CTRL"                         "per , ""RSS_CTRL"""
menuitem "RSS_RCM"                          "per , ""RSS_RCM"""
menuitem "RSS_TPCC_A"                       "per , ""RSS_TPCC_A"""
menuitem "RSS_TPTC_A0"                      "per , ""RSS_TPTC_A0"""
menuitem "TOP_AURORA_TX"                    "per , ""TOP_AURORA_TX"""
menuitem "TOP_CTRL"                         "per , ""TOP_CTRL"""
menuitem "TOP_MDO_INFRA"                    "per , ""TOP_MDO_INFRA"""
menuitem "TOP_PBIST"                        "per , ""TOP_PBIST"""
)
)