; -------------------------------------------------------------------------------- ; @Title: TMS570LS20216 On-Chip Peripherals ; @Props: Released ; @Author: ADI ; @Changelog: 2008-10-22 ADI ; @Manufacturer: TI - Texas Instruments ; @Doc: TMS570PSFC66_design_specification_26.pdf; AWM.pdf; DCAN.pdf; GIO.pdf ; NHET.pdf; HTU.pdf; EMIF.pdf; CCM-R4.pdf; BLIN.pdf; DMA.pdf; FWM.pdf; ESM.pdf ; RTI.pdf; RTP.pdf; DMM.pdf; VIM.pdf; MibSPI.pdf; POM.pdf; Platform_AS_4.pdf ; TCRAMW.pdf; MCRC.pdf; FMzPLL.pdf ; @Core: Cortex-R4F ; @Copyright: (C) 1989-2017 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: pertms570ls20216.per 13224 2021-04-28 12:54:48Z kwitkowski $ config 16. 8. tree "Core Registers (Cortex-R4F)" AUTOINDENT.PUSH AUTOINDENT.OFF width 0x8 ; -------------------------------------------------------------------------------- ; Identification registers ; -------------------------------------------------------------------------------- tree "ID Registers" rgroup c15:0x0--0x0 line.long 0x0 "MIDR,Main ID Register" hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code" bitfld.long 0x0 20.--23. " VAR ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16.--19. " ARCH , Architecture" "Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,ARMv7" textline " " hexmask.long.word 0x0 4.--15. 0x1 " PART ,Primary Part Number" bitfld.long 0x0 0.--3. " REV ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup c15:0x100--0x100 line.long 0x0 "CTR,Cache Type Register" bitfld.long 0x0 29.--31. " FORMAT ,Format" "Not ARMv7,Not ARMv7,Not ARMv7,Not ARMv7,ARMv7,Not ARMv7,Not ARMv7,Not ARMv7" bitfld.long 0x0 16.--19. " DMINLINE ,D-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words" bitfld.long 0x0 14.--15. " L1POLICY ,L1 Instruction cache policy" "Reserved,ASID,Virtual,Physical" textline " " bitfld.long 0x0 0.--3. " IMINLINE ,I-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words" rgroup c15:0x200--0x200 line.long 0x0 "TCMSR,Tighly-Coupled Memory Status Register" bitfld.long 0x0 16.--19. " DTCMS ,Data Banks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 0.--3. " ITCMS ,Instruction Banks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup c15:0x400--0x400 line.long 0x0 "MPUIR,MPU type register" hexmask.long.byte 0x00 8.--15. 1. " REGNUM ,Number of regions" bitfld.long 0x00 0. " TYPE ,Type of MPU regions" "Unified,Seperated" rgroup c15:0x500--0x500 line.long 0x0 "MPIDR,Multiprocessor Affinity Register" hexmask.long.byte 0x00 16.--23. 1. " AFFL2 ,Affitnity Level 2" hexmask.long.byte 0x00 8.--15. 1. " AFFL1 ,Affitnity Level 1" hexmask.long.byte 0x00 0.--7. 1. " AFFL0 ,Affitnity Level 0" textline " " rgroup c15:0x0410++0x00 line.long 0x00 "MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 28.--31. " IT ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " ACR ,Auxiliary Control Register Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..." textline " " bitfld.long 0x00 12.--15. " CC_PLEA ,Cache Coherency With PLE Agent/Shared Memory Support" "Not supported,?..." bitfld.long 0x00 8.--11. " CC_CPUA ,Cache Coherency Support With CPU Agent/Shared Memory Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..." bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..." rgroup c15:0x0510++0x00 line.long 0x00 "MMFR1,Memory Model Feature Register 1" bitfld.long 0x00 28.--31. " BTB ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..." bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..." textline " " bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..." textline " " bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..." rgroup c15:0x0610++0x00 line.long 0x00 "MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..." bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." rgroup c15:0x0710++0x00 line.long 0x00 "MMFR3,Memory Model Feature Register 3" bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..." rgroup c15:0x0020++0x00 line.long 0x00 "ISAR0,Instruction Set Attribute Register 0" bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,?..." bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..." bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " AI ,Atomic Load and Store Instructions Support" "Reserved,Supported,?..." rgroup c15:0x0120++0x00 line.long 0x00 "ISAR1,Instruction Set Attribute Register 1" bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. " INTI ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " EXTI ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " ENDI ,Endianness Control Instructions Support" "Reserved,Supported,?..." rgroup c15:0x0220++0x00 line.long 0x00 "ISAR2,Instruction Set Attribute Register 2" bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Supported,?..." textline " " bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,Supported,?..." rgroup c15:0x0320++0x00 line.long 0x00 "ISAR3,Instruction Set Attribute Register 3" bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " SWII ,SWI Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..." rgroup c15:0x0420++0x00 line.long 0x00 "ISAR4,Instruction Set Attribute Register 4" bitfld.long 0x00 20.--23. " EI ,Exclusive Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " SMII ,SMI Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..." rgroup c15:0x0520++0x00 line.long 0x00 "ISAR5,Instruction Set Attribute Registers 5 (Reserved)" rgroup c15:0x0620++0x00 line.long 0x00 "ISAR6,Instruction Set Attribute Registers 6 (Reserved)" rgroup c15:0x0720++0x00 line.long 0x00 "ISAR7,Instruction Set Attribute Registers 7 (Reserved)" rgroup c15:0x0010++0x00 line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 12.--15. " STATE3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. " STATE2 ,Java Extension Interface Support" "Not supported,?..." bitfld.long 0x00 4.--7. " STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..." rgroup c15:0x0110++0x00 line.long 0x00 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Supported,?..." bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..." textline " " rgroup c15:0x0210++0x00 line.long 0x00 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..." bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..." textline " " bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,?..." bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,?..." rgroup c15:0x0310++0x00 line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" tree.end width 0x8 tree "System Control and Configuration" group c15:0x1--0x1 line.long 0x0 "SCTLR,Control Register" bitfld.long 0x0 31. " IE ,Instruction endianness" "Little,Big" bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disable,Enable" bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disable,Enable" bitfld.long 0x0 27. " NMFI ,Nonmaskable Fast Interrupt enable" "Disable,Enable" textline " " bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big" bitfld.long 0x0 24. " VE ,Vector Enable" "Disable,Vectored" bitfld.long 0x0 21. " FI ,Fast Interrupts enable" "Disable,Enable" bitfld.long 0x0 19. " DZ ,Divide by Zero exception bit" "Disable,Enable" bitfld.long 0x0 14. " RR ,Round-Robin bit" "Random,RRobin" bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000" textline " " bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disable,Enable" bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disable,Enable" bitfld.long 0x0 2. " C ,Enable data cache" "Disable,Enable" bitfld.long 0x0 1. " A ,Strict Alignment" "Disable,Enable" bitfld.long 0x0 0. " M ,MPU Enable" "Disable,Enable" textline " " group c15:0x101--0x101 line.long 0x0 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 31. " DICDI ,Disable Case C dual issue control" "Enable,Disable" bitfld.long 0x00 30. " DIB2DI ,Disable Case B2 dual issue control" "Enable,Disable" bitfld.long 0x00 29. " DIB1DI ,Disable Case B1 dual issue control" "Enable,Disable" textline " " bitfld.long 0x00 28. " DIADI ,Disable Case A dual issue control" "Enable,Disable" bitfld.long 0x00 27. " B1TCMPCEN ,B1TCM parity or ECC check enable" "Disable,Enable" bitfld.long 0x00 26. " B0TCMPCEN ,B1TCM parity or ECC check enable" "Disable,Enable" textline " " bitfld.long 0x00 25. " ATCMPCEN ,B1TCM parity or ECC check enable" "Disable,Enable" bitfld.long 0x00 24. " AXISCEN ,AXI slave cache access enable" "Disable,Enable" bitfld.long 0x00 23. " AXISCUEN ,AXI slave cache User mode access enable" "Disable,Enable" textline " " bitfld.long 0x00 22. " DILSM ,Disable LIL on load/store multiples" "Disable,Enable" bitfld.long 0x00 21. " DEOLP ,Disable end of loop prediction" "Disable,Enable" bitfld.long 0x00 20. " DBHE ,Disable BH extension" "Enable,Disable" textline " " bitfld.long 0x00 19. " FRCDIS ,Fetch rate control disable" "Enable,Disable" bitfld.long 0x00 17. " RSDIS ,Return stack disable" "Enable,Disable" bitfld.long 0x00 15.--16. " BP ,Control of the branch prediction policy" "Normal,Taken,Not taken,?..." textline " " bitfld.long 0x00 14. " DBWR ,Disable write_burst on AXI master" "Enable,Disable" bitfld.long 0x00 13. " DSWT ,Disable should_wait on AXI master" "Enable,Disable" bitfld.long 0x00 12. " ERPEG ,Enable random parity error generation" "Disable,Enable" textline " " bitfld.long 0x00 11. " DOLT ,Disable outstanding line fill on AXI master" "Enable,Disable" bitfld.long 0x00 10. " FORA ,Force outer read allocate (ORA) for outer write allocate (OWA) regions" "Not forced,Forced" bitfld.long 0x00 9. " FWT ,Force write-through (WT) for write-back (WB) regions" "Not forced,Forced" textline " " bitfld.long 0x00 8. " FDSnS ,Force D-side to not-shared when MPU is off" "Not forced,Forced" bitfld.long 0x00 7. " sMOV ,sMOV disabled" "Enabled,Disabled" bitfld.long 0x0 6. " DILS ,Disable low interrupt latency on all load/store instructions" "Enable,Disable" textline " " bitfld.long 0x00 5. " DA ,DA Disable abort on cache parity error" "Enable,Disable" bitfld.long 0x00 4. " EHR ,Enable hardware recovery from cache parity errors" "Disable,Enable" bitfld.long 0x00 2. " I1TCMECEN ,Instruction 1 TCM error check enable" "Disable,Enable" textline " " bitfld.long 0x00 1. " I0TCMECEN ,Instruction 1 TCM error check enable" "Disable,Enable" bitfld.long 0x00 0. " ITCMECEN ,Instruction TCM error check enable" "Disable,Enable" textline " " group c15:0x0f--0x0f line.long 0x0 "SACTLR,Secondary Auxiliary Control Register" bitfld.long 0x00 22. " DCHE ,Disable hard-error support in the caches" "Enable,Disable" bitfld.long 0x00 21. " DR2B ,Enable random 2-bit error genration in cache RAMs" "Disable,Enable" bitfld.long 0x00 20. " DF6DI ,F6 dual issue control" "Enable,Disable" textline " " bitfld.long 0x00 19. " DF2DI ,F2 dual issue control" "Enable,Disable" bitfld.long 0x00 18. " DDI ,F1/F3/F4 dual issue control" "Enable,Disable" bitfld.long 0x00 17. " DOODPFP ,Out-of-order Double Precision Floating-point control" "Enable,Disable" textline " " bitfld.long 0x00 16. " DOOFMACS ,Out-of-order FMACS control" "Enable,Disable" bitfld.long 0x00 13. " IXC ,Floating-point inexact exception output mask" "Mask,Propagate" bitfld.long 0x00 12. " OFC ,Floating-point overflow exception output mask" "Mask,Propagate" textline " " bitfld.long 0x00 11. " UFC ,Floating-point underflow exception output mask" "Mask,Propagate" bitfld.long 0x00 10. " IOC ,Floating-point invalid operation exception output mask" "Mask,Propagate" bitfld.long 0x00 9. " DZC ,Floating-point divide-by-zero exception output mask" "Mask,Propagate" textline " " bitfld.long 0x00 8. " IDC ,Floating-point input denormal exception output mask" "Mask,Propagate" bitfld.long 0x00 3. " BTCMECC ,Correction for internal ECC logic on BTCM ports" "Enable,Disable" bitfld.long 0x00 2. " ATCMECC ,Correction for internal ECC logic on ATCM port" "Enable,Disable" textline " " bitfld.long 0x00 1. " BTCMRMW ,Enable 64-bit stores on BTCMs" "Disable,Enable" bitfld.long 0x00 0. " ATCMRMW ,Enable 64-bit stores on ATCM" "Disable,Enable" textline " " group c15:0x201--0x201 line.long 0x0 "CPACR,Coprocessor Access Control Register" bitfld.long 0x0 26.--27. " CP13 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 24.--25. " CP12 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 22.--23. " CP11 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 20.--21. " CP10 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 18.--19. " CP9 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 16.--17. " CP8 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 14.--15. " CP7 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 12.--13. " CP6 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 10.--11. " CP5 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 8.--9. " CP4 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 6.--7. " CP3 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 4.--5. " CP2 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 2.--3. " CP1 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 0.--1. " CP0 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " group.long c15:0x0b--0x0b line.long 0x00 "SPC,Slave Port Control" bitfld.long 0x00 1. " PRIV ,Privilege access only" "User/Privilege,Privilege only" bitfld.long 0x00 0. " AXISLEN ,AXI slave port disable" "Enabled,Disabled" tree.end width 0x8 tree "MPU Control and Configuration" group c15:0x0001--0x0001 line.long 0x0 "SCTLR,Control Register" bitfld.long 0x0 31. " IE ,Instruction endianness" "Little,Big" bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disable,Enable" bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disable,Enable" bitfld.long 0x0 27. " NMFI ,Nonmaskable Fast Interrupt enable" "Disable,Enable" textline " " bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big" bitfld.long 0x0 24. " VE ,Vector Enable" "Disable,Vectored" bitfld.long 0x0 21. " FI ,Fast Interrupts enable" "Disable,Enable" bitfld.long 0x0 19. " DZ ,Divide by Zero exception bit" "Disable,Enable" bitfld.long 0x0 14. " RR ,Round-Robin bit" "Random,RRobin" bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000" textline " " bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disable,Enable" bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disable,Enable" bitfld.long 0x0 2. " C ,Enable data cache" "Disable,Enable" bitfld.long 0x0 1. " A ,Strict Alignment" "Disable,Enable" bitfld.long 0x0 0. " M ,MPU Enable" "Disable,Enable" textline " " group.long c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR" bitfld.long 0x00 11. " RW ,Access Caused an Abort Type" "Read,Write" textline " " bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15" bitfld.long 0x00 0.--3. 10. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..." group.long c15:0x0015++0x00 line.long 0x00 "ADFSR,Auxiliary Data Fault Status Register" group.long c15:0x0006++0x00 line.long 0x00 "DFAR,Data Fault Address Register" group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR" bitfld.long 0x00 0.--3. 10. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..." group.long c15:0x0115++0x00 line.long 0x00 "AIFSR,Auxiliary Instruction Fault Status Register" group.long c15:0x0206++0x00 line.long 0x00 "IFAR,Instruction Fault Address Register" textline " " group c15:0x0016++0x00 line.long 0x00 "RBAR,Region Base Address Register" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 line.long 0x00 "RSER,Region Size and Enable Register" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 line.long 0x00 "RACR,Region Access Control Register" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " TYPE ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" group c15:0x0026++0x00 line.long 0x00 "MRNR,Memory Region Number Register" bitfld.long 0x00 0.--3. " REGION ,Defines the group of registers to be accessed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " group c15:0x010d++0x00 line.long 0x00 "CIDR,Context ID Register" group.long c15:0x20d++0x00 line.long 0x00 "TIDRURW,User read/write Thread and Process ID Register" group.long c15:0x30d++0x00 line.long 0x00 "TIDRURO,User read only Thread and Process ID Register" group.long c15:0x40d++0x00 line.long 0x00 "TIDRPRW,Privileged Only Thread and Process ID Register" tree "MPU regions" group c15:0x0016++0x00 saveout c15:0x26 %l 0x0 line.long 0x00 "RBAR0,Region Base Address Register 0" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x0 line.long 0x00 "RSER0,Region Size and Enable Register 0" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x0 line.long 0x00 "RACR0,Region Access Control Register 0" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x1 line.long 0x00 "RBAR1,Region Base Address Register 1" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x1 line.long 0x00 "RSER1,Region Size and Enable Register 1" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x1 line.long 0x00 "RACR1,Region Access Control Register 1" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x2 line.long 0x00 "RBAR2,Region Base Address Register 2" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x2 line.long 0x00 "RSER2,Region Size and Enable Register 2" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x2 line.long 0x00 "RACR2,Region Access Control Register 2" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x3 line.long 0x00 "RBAR3,Region Base Address Register 3" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x3 line.long 0x00 "RSER3,Region Size and Enable Register 3" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x3 line.long 0x00 "RACR3,Region Access Control Register 3" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x4 line.long 0x00 "RBAR4,Region Base Address Register 4" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x4 line.long 0x00 "RSER4,Region Size and Enable Register 4" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x4 line.long 0x00 "RACR4,Region Access Control Register 4" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x5 line.long 0x00 "RBAR5,Region Base Address Register 5" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x5 line.long 0x00 "RSER5,Region Size and Enable Register 5" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x5 line.long 0x00 "RACR5,Region Access Control Register 5" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x6 line.long 0x00 "RBAR6,Region Base Address Register 6" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x6 line.long 0x00 "RSER6,Region Size and Enable Register 6" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x6 line.long 0x00 "RACR6,Region Access Control Register 6" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x7 line.long 0x00 "RBAR7,Region Base Address Register 7" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x7 line.long 0x00 "RSER7,Region Size and Enable Register 7" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x7 line.long 0x00 "RACR7,Region Access Control Register 7" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x8 line.long 0x00 "RBAR8,Region Base Address Register 8" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x8 line.long 0x00 "RSER8,Region Size and Enable Register 8" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x8 line.long 0x00 "RACR8,Region Access Control Register 8" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x9 line.long 0x00 "RBAR9,Region Base Address Register 9" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x9 line.long 0x00 "RSER9,Region Size and Enable Register 9" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x9 line.long 0x00 "RACR9,Region Access Control Register 9" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0xA line.long 0x00 "RBAR10,Region Base Address Register 10" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0xA line.long 0x00 "RSER10,Region Size and Enable Register 10" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0xA line.long 0x00 "RACR10,Region Access Control Register 10" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0xB line.long 0x00 "RBAR11,Region Base Address Register 11" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0xB line.long 0x00 "RSER11,Region Size and Enable Register 11" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0xB line.long 0x00 "RACR11,Region Access Control Register 11" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " tree.end tree.end width 0x9 tree "TCM Control and Configuration" rgroup.long c15:0x200++0x00 line.long 0x00 "TCMTR,TCM Type Register" bitfld.long 0x00 16.--18. " BTCM ,Number of BTCMs implemented" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " ATCM ,Number of ATCMs implemented" "0,1,2,3,4,5,6,7" group.long c15:0x019++0x00 line.long 0x00 "BTCMRR,BTCM Region Register" hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address (physical address)" bitfld.long 0x00 2.--6. " SIZE ,Size of instruction TCM on reads" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,?..." bitfld.long 0x00 0. " EN ,Enable instruction TCM" "Disabled,Enabled" group.long c15:0x119++0x00 line.long 0x00 "ATCMRR,ATCM Region Register" hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address (physical address)" bitfld.long 0x00 2.--6. " SIZE ,Size of instruction TCM on reads" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,?..." bitfld.long 0x00 0. " EN ,Enable instruction TCM" "Disabled,Enabled" rgroup.long c15:0x29++0x00 line.long 0x00 "TCMSEL,TCM Selection Register" tree.end width 0xC tree "Cache Control and Configuration" rgroup.long c15:0x1100--0x1100 line.long 0x0 "CLIDR,Cache Level ID Register" bitfld.long 0x00 27.--29. " LoU ,Level of Unification" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " LoC ,Level of Coherency" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8" textline " " bitfld.long 0x00 21.--23. " CL8 ,Cache Level (CL) 8" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--20. " CL7 ,Cache Level (CL) 7" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 15.--17. " CL6 ,Cache Level (CL) 6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. " CL5 ,Cache Level (CL) 5" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 9.--11. " CL4 ,Cache Level (CL) 4" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--8. " CL3 ,Cache Level (CL) 3" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 3.--5. " CL2 ,Cache Level (CL) 2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " CL1 ,Cache Level (CL) 1" "0,1,2,3,4,5,6,7" rgroup.long c15:0x1000++0x00 line.long 0x00 "CCSIDR,Cache Size ID Register" bitfld.long 0x00 31. " WT ,Write-Through" "Not supported,Supported" bitfld.long 0x00 30. " WB ,Write-Back" "Not supported,Supported" textline " " bitfld.long 0x00 29. " RA ,Read-Allocate" "Not supported,Supported" bitfld.long 0x00 28. " WA ,Write-Allocate" "Not supported,Supported" textline " " hexmask.long.word 0x00 13.--27. 1. " NUMSETS ,Number of sets" hexmask.long.word 0x00 3.--12. 1. " ASSOCIATIVITY ,Associativity" textline " " bitfld.long 0x00 0.--2. " LINESIZE ,Number of words in each cache line" "0,1,2,3,4,5,6,7" group.long c15:0x2000--0x2000 line.long 0x0 "CSSELR,Cache Size Selection Register" bitfld.long 0x00 1.--3. " Level ,Cache level to select" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " InD ,Instruction or data or unified cache to use" "Data/unified,Instruction" group.long c15:0x03f++0x00 line.long 0x00 "CFLR,Correctable Fault Location Register" bitfld.long 0x00 26.--29. " WAY ,Way of the error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--25. " SIDE ,Source of the error" "0,1,2,3" textline " " hexmask.long.word 0x00 5.--13. 1. " INDEX ,index of the location where the error occurred" bitfld.long 0x00 0.--1. " TYPE ,Type of access that caused the error" "Instruction cache,Data cache,Reserved,ACP" rgroup.long c15:0x0ef++0x0 line.long 0x00 "CSOR,Cache Size Override Register" bitfld.long 0x00 4.--6. " Dcache ,Validation data cache size" "Not presented,Reserved,Reserved,4k,8k,16k,32k,64k" bitfld.long 0x00 0.--2. " Icache ,Validation instruction cache size" "Not presented,Reserved,Reserved,4k,8k,16k,32k,64k" tree.end width 8. tree "System Performance Monitor" group c15:0xC9--0xC9 line.long 0x0 "PMNC,Performance Monitor Control Register" hexmask.long.byte 0x00 24.--31. 1. " IMP ,Implementer code" hexmask.long.byte 0x00 16.--23. 1. " IDCODE ,Identification code" bitfld.long 0x00 11.--15. " N ,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5. " DP ,Disable CCNT when prohibited" "Enabled,Disabled" textline " " bitfld.long 0x00 4. " X ,Export Enabled" "Disabled,Enabled" bitfld.long 0x00 3. " D ,Clock Divider" "Every cycle,64th cycle" bitfld.long 0x00 2. " C ,Clock Counter Reset" "No action,Reset" bitfld.long 0x00 1. " P ,Performance Counter Reset" "No action,Reset" textline " " bitfld.long 0x00 0. " E ,Counters Enable" "Disabled,Enabled" group c15:0x1C9--0x1C9 line.long 0x0 "CNTENS,Count Enable Set Register" eventfld.long 0x00 31. " C ,CCNT Enabled / Enable / Disable CCNT" "Disabled,Enabled" eventfld.long 0x00 3. " P3 ,PMN3 Enabled / Enable / Disable counter" "Disabled,Enabled" eventfld.long 0x00 2. " P2 ,PMN2 Enabled / Enable / Disable counter" "Disabled,Enabled" eventfld.long 0x00 1. " P1 ,PMN1 Enabled / Enable / Disable counter" "Disabled,Enabled" eventfld.long 0x00 0. " P0 ,PMN0 Enabled / Enable / Disable counter" "Disabled,Enabled" group c15:0x2C9--0x2C9 line.long 0x0 "CNTENC,Count Enable Clear Register" eventfld.long 0x00 31. " C ,CCNT Enabled / Enable / Disable CCNT" "Disabled,Enabled" eventfld.long 0x00 3. " P3 ,PMN3 Enabled / Enable / Disable counter" "Disabled,Enabled" eventfld.long 0x00 2. " P2 ,PMN2 Enabled / Enable / Disable counter" "Disabled,Enabled" eventfld.long 0x00 1. " P1 ,PMN1 Enabled / Enable / Disable counter" "Disabled,Enabled" eventfld.long 0x00 0. " P0 ,PMN0 Enabled / Enable / Disable counter" "Disabled,Enabled" group c15:0x3C9--0x3C9 line.long 0x0 "FLAG,Overflow Flag Status Register" eventfld.long 0x00 31. " C ,CCNT overflowed" "No overflow,Overflow" eventfld.long 0x00 3. " P3 ,PMN3 overflowed" "No overflow,Overflow" eventfld.long 0x00 2. " P2 ,PMN2 overflowed" "No overflow,Overflow" eventfld.long 0x00 1. " P1 ,PMN1 overflowed" "No overflow,Overflow" eventfld.long 0x00 0. " P0 ,PMN0 overflowed" "No overflow,Overflow" group c15:0x4C9--0x4C9 line.long 0x0 "SWINCR,Software Increment Register" eventfld.long 0x00 3. " P3 ,Increment PMN3" "No action,Increment" eventfld.long 0x00 2. " P2 ,Increment PMN2" "No action,Increment" eventfld.long 0x00 1. " P1 ,Increment PMN1" "No action,Increment" eventfld.long 0x00 0. " P0 ,Increment PMN0" "No action,Increment" group c15:0x5C9--0x5C9 line.long 0x0 "PMNXSEL,Performance Counter Selection Register" bitfld.long 0x00 0.--4. " SEL ,Selection value" "CNT0,CNT1,CNT2,CNT3,?..." group c15:0xD9--0xD9 line.long 0x0 "CCNT,Cycle Count Register" group c15:0x01d9++0x00 line.long 0x00 "ESR,Event Selection Register" hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection" group c15:0x02d9++0x00 line.long 0x00 "PMCR,Performance Monitor Count Register" group c15:0x01d9++0x00 saveout c15:0x5C9 %l 0x0 line.long 0x00 "ESR0,Event Selection Register 0" hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection" group c15:0x02d9++0x00 saveout c15:0x5C9 %l 0x0 line.long 0x00 "PMCR0,Performance Monitor Count Register 0" hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count" group c15:0x01d9++0x00 saveout c15:0x5C9 %l 0x1 line.long 0x00 "ESR1,Event Selection Register 1" hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection" group c15:0x02d9++0x00 saveout c15:0x5C9 %l 0x1 line.long 0x00 "PMCR1,Performance Monitor Count Register 1" hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count" group c15:0x01d9++0x00 saveout c15:0x5C9 %l 0x2 line.long 0x00 "ESR2,Event Selection Register 2" hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection" group c15:0x02d9++0x00 saveout c15:0x5C9 %l 0x2 line.long 0x00 "PMCR2,Performance Monitor Count Register 2" hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count" group c15:0xE9--0xE9 line.long 0x0 "USEREN,User Enable Register" bitfld.long 0x00 0. " EN ,User Mode Enable" "Disabled,Enabled" group c15:0x1E9--0x1E9 line.long 0x0 "INTENS,Interrupt Enable Set Register" eventfld.long 0x00 31. " C ,Interrupt on CCNT Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 3. " P3 ,Interrupt on PMN3 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 2. " P2 ,Interrupt on PMN2 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 1. " P1 ,Interrupt on PMN1 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 0. " P0 ,Interrupt on PMN0 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" group c15:0x2E9--0x2E9 line.long 0x0 "INTENC,Interrupt Enable Clear Register" eventfld.long 0x00 31. " C ,Interrupt on CCNT Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 3. " P3 ,Interrupt on PMN3 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 2. " P2 ,Interrupt on PMN2 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 1. " P1 ,Interrupt on PMN1 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 0. " P0 ,Interrupt on PMN0 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" tree.end width 8. tree "Debug Registers" width 11. tree "Processor Identifier Registers" rgroup c14:0x340--0x340 line.long 0x00 "MIDR,Main ID Register" hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code" hexmask.long.byte 0x0 20.--23. 0x1 " SPECREV ,Variant number" textline " " hexmask.long.byte 0x0 16.--19. 0x1 " ARCH , Architecture" hexmask.long.word 0x0 4.--15. 0x1 " PARTNUM ,Part Number" textline " " hexmask.long.byte 0x0 0.--3. 0x1 " REV ,Layout Revision" rgroup c14:0x341--0x341 line.long 0x00 "CACHETYPE,Cache Type Register" bitfld.long 0x00 16.--19. " DMINLINE ,Words of Smallest Line Length in L1 or L2 Data Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..." bitfld.long 0x00 14.--15. " L1_IPOLICY ,VIPT Instruction Cache Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " IMINLINE ,Words of Smallest Line Length in L1 or L2 Instruction Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..." rgroup c14:0x343--0x343 line.long 0x00 "TLBTYPE,TLB Type Register" hexmask.long.byte 0x0 16.--23. 0x1 " ILSIZE ,Specifies the number of instruction TLB lockable entries" hexmask.long.byte 0x0 8.--15. 0x1 " DLSIZE ,Specifies the number of unified or data TLB lockable entries" textline " " bitfld.long 0x0 0. " U ,Unified or separate instruction TLBs" "Unified,Separate" rgroup c14:0x348--0x348 line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 12.--15. " STATE3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. " STATE2 ,Java Extension Interface Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..." rgroup c14:0x349--0x349 line.long 0x00 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Supported,?..." bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..." rgroup c14:0x34a--0x34a line.long 0x00 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..." bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..." bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,?..." bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,?..." rgroup c14:0x34b--0x34b line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" hexmask.long 0x00 0.--31. 1. " AF ,Auxiliary Feature" rgroup c14:0x34c--0x34c line.long 0x00 "ID_MMFR0,Processor Feature Register 0" bitfld.long 0x00 28.--31. " IT ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " ACR ,Auxiliary Control Register Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..." textline " " bitfld.long 0x00 12.--15. " CC_PLEA ,Cache Coherency With PLE Agent/Shared Memory Support" "Not supported,?..." bitfld.long 0x00 8.--11. " CC_CPUA ,Cache Coherency Support With CPU Agent/Shared Memory Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..." bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..." rgroup c14:0x34d--0x34d line.long 0x00 "ID_MMFR1,Processor Feature Register 1" bitfld.long 0x00 28.--31. " BTB ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..." bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..." textline " " bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..." textline " " bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..." rgroup c14:0x34e--0x34e line.long 0x00 "ID_MMFR2,Processor Feature Register 2" bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..." bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." rgroup c14:0x34f--0x34f line.long 0x00 "ID_MMFR3,Processor Feature Register 3" bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..." rgroup c14:0x350--0x350 line.long 0x00 "ID_ISAR0,ISA Feature Register 0" bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,?..." bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..." bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " AI ,Atomic Load and Store Instructions Support" "Reserved,Supported,?..." rgroup c14:0x351--0x351 line.long 0x00 "ID_ISAR1,ISA Feature Register 1" bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. " INTI ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " EXTI ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " ENDI ,Endianness Control Instructions Support" "Reserved,Supported,?..." rgroup c14:0x352--0x352 line.long 0x00 "ID_ISAR2,ISA Feature Register 2" bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Supported,?..." textline " " bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,Supported,?..." rgroup c14:0x353--0x353 line.long 0x00 "ID_ISAR3,ISA Feature Register 3" bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " SWII ,SWI Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..." rgroup c14:0x354--0x354 line.long 0x00 "ID_ISAR4,ISA Feature Register 4" bitfld.long 0x00 20.--23. " EI ,Exclusive Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " SMII ,SMI Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..." rgroup c14:0x355--0x355 line.long 0x00 "ID_ISAR5,ISA Feature Register 5" tree.end tree "Coresight Management Registers" width 0xC textline " " group c14:0x03bd++0x00 line.long 0x00 "ITCTRL_IOC,Integration Internal Output Control Register" bitfld.long 0x00 5. " I_DBGTRIGGER ,Internal DBGTRIGGER" "0,1" bitfld.long 0x00 4. " I_DBGRESTARTED ,Internal DBGRESTARTED" "0,1" textline " " bitfld.long 0x00 3. " I_NPMUIRQ ,Internal nPMUIRQ" "0,1" bitfld.long 0x00 2. " InternalCOMMTX ,Internal COMMTX" "0,1" textline " " bitfld.long 0x00 1. " I_COMMRX ,Internal COMMRX" "0,1" bitfld.long 0x00 0. " I_DBGACK ,Internal DBGACK" "0,1" group c14:0x03be++0x00 line.long 0x00 "ITCTRL_EOC,Integration External Output Control Register" bitfld.long 0x00 7. " NDMAEXTERRIQ ,External nDMAEXTERRIRQ" "0,1" bitfld.long 0x00 6. " NDMASIRQ ,External nDMASIRQ" "0,1" textline " " bitfld.long 0x00 5. " NDMAIRQ ,External nDMAIRQ" "0,1" bitfld.long 0x00 4. " NPMUIRQ ,External nPMUIRQ" "0,1" textline " " bitfld.long 0x00 3. " STANDBYWFI ,External STANDBYWFI" "0,1" bitfld.long 0x00 2. " COMMTX ,External COMMTX" "0,1" textline " " bitfld.long 0x00 1. " COMMRX ,External COMMRX" "0,1" bitfld.long 0x00 0. " DBGACK ,External DBGACK" "0,1" rgroup c14:0x03bf++0x00 line.long 0x00 "ITCTRL_IS,Integration Input Status Register" bitfld.long 0x00 11. " CTI_DBGRESTART ,CTI Debug Restart" "0,1" bitfld.long 0x00 10. " CTI_EDBGRQ ,CTI Debug Request" "0,1" textline " " bitfld.long 0x00 9. " CTI_PMUEXTIN[1] ,CTI PMUEXTIN[1] Signal" "0,1" bitfld.long 0x00 8. " CTI_PMUEXTIN[0] ,CTI PMUEXTIN[0] Signal" "0,1" textline " " bitfld.long 0x00 2. " NFIQ ,nFIQ Input" "0,1" bitfld.long 0x00 1. " NIRQ ,nIRQ Input" "0,1" textline " " bitfld.long 0x00 0. " EDBGRQ ,EDBGRQ Input" "0,1" group c14:0x3c0--0x3c0 line.long 0x0 "ITCTRL,Integration Mode Control Register" bitfld.long 0x0 0. " IME ,Integration Mode Enable" "Disabled,Enabled" group c14:0x3e8--0x3e8 line.long 0x0 "CLAIMSET,Claim Tag Set Register" bitfld.long 0x0 7. " CT7 ,Claim Tag 7" "No Effect,Set" bitfld.long 0x0 6. " CT6 ,Claim Tag 6" "No Effect,Set" textline " " bitfld.long 0x0 5. " CT5 ,Claim Tag 5" "No Effect,Set" bitfld.long 0x0 4. " CT4 ,Claim Tag 4" "No Effect,Set" textline " " bitfld.long 0x0 3. " CT3 ,Claim Tag 3" "No Effect,Set" bitfld.long 0x0 2. " CT2 ,Claim Tag 2" "No Effect,Set" textline " " bitfld.long 0x0 1. " CT1 ,Claim Tag 1" "No Effect,Set" bitfld.long 0x0 0. " CT0 ,Claim Tag 0" "No Effect,Set" group c14:0x3e9--0x3e9 line.long 0x0 "CLAIMCLR,Claim Tag Clear Register" bitfld.long 0x0 7. " CT7 ,Claim Tag 7" "No Effect,Cleared" bitfld.long 0x0 6. " CT6 ,Claim Tag 6" "No Effect,Cleared" textline " " bitfld.long 0x0 5. " CT5 ,Claim Tag 5" "No Effect,Cleared" bitfld.long 0x0 4. " CT4 ,Claim Tag 4" "No Effect,Cleared" textline " " bitfld.long 0x0 3. " CT3 ,Claim Tag 3" "No Effect,Cleared" bitfld.long 0x0 2. " CT2 ,Claim Tag 2" "No Effect,Cleared" textline " " bitfld.long 0x0 1. " CT1 ,Claim Tag 1" "No Effect,Cleared" bitfld.long 0x0 0. " CT0 ,Claim Tag 0" "No Effect,Cleared" wgroup c14:0x3ec--0x3ec line.long 0x0 "LAR,Lock Access Register" hexmask.long.long 0x0 0.--31. 1. " LACK ,Lock Access Control Key" rgroup c14:0x3ed--0x3ed line.long 0x0 "LSR,Lock Status Register" bitfld.long 0x0 2. " 32ACND ,32-bit Access Needed" "Needed,Not needed" bitfld.long 0x0 1. " WLCK ,Writes Lock" "Permitted,Ignored" textline " " bitfld.long 0x0 0. " LI ,Lock Implementation" "Lock ignored,Unlock required" rgroup c14:0x3ee--0x3ee line.long 0x0 "AUTHSTATUS,Authentication Status Register" bitfld.long 0x0 7. " SNIDFI ,Secure Non-invasive Debug Features Implemented" "Not Implemented,Implemented" bitfld.long 0x0 6. " SNIDE ,Secure Non-invasive Debug Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 5. " SIDFI ,Secure Invasive Debug Feauter Implemented" "Not Implemented,Implemented" bitfld.long 0x0 4. " SIDE ,Secure Invasive Debug Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 3. " NSNIDFI ,Non-secure Non-invasive Debug Feature Implemented" "Not Implemented,Implemented" bitfld.long 0x0 2. " NSNIDE ,Non-secure Non-invasive Debug Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 1. " NSIDFI ,Non-secure Invasive Debug Implemented" "Not Implemented,Implemented" bitfld.long 0x0 0. " NSIDE ,Non-secure Invasive Debug Enable" "Disabled,Enabled" hgroup c14:0x3f2--0x3f2 hide.long 0x0 "DEVID,Device Identifier (RESERVED)" rgroup c14:0x3f3--0x3f3 line.long 0x0 "DEVTYPE,Device Type" hexmask.long.byte 0x00 4.--7. 1. " SUBTYPE ,Subtype" hexmask.long.byte 0x00 0.--3. 1. " MAIN_CLASS ,Main class" rgroup c14:0x3f8--0x3f8 line.long 0x0 "PID0,Peripherial ID0" hexmask.long.byte 0x0 0.--7. 1. " PN ,Part Number [7:0]" rgroup c14:0x3f9--0x3f9 line.long 0x0 "PID1,Peripherial ID1" hexmask.long.byte 0x0 4.--7. 1. " JEP106 ,JEP106 Identity Code [3:0]" hexmask.long.byte 0x0 0.--3. 1. " PN ,Part Number [11:8]" rgroup c14:0x3fa--0x3fa line.long 0x0 "PID2,Peripherial ID2" hexmask.long.byte 0x0 4.--7. 1. " REV ,Revision" hexmask.long.byte 0x0 0.--2. 1. " JEP106 ,JEP106 Identity Code [6:4]" rgroup c14:0x3fb--0x3fb line.long 0x0 "PID3,Peripherial ID3" hexmask.long.byte 0x0 4.--7. 1. " REVA ,RevAnd" hexmask.long.byte 0x0 0.--3. 1. " CMOD ,Customer Modified" rgroup c14:0x3f4--0x3f4 line.long 0x0 "PID4,Peripherial ID4" bitfld.long 0x0 4.--7. " 4KBC ,Number of 4KB Blocks Occupied" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" bitfld.long 0x0 0.--3. " JEP106 ,JEP106 Continuation Code" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111" rgroup c14:0x3fc--0x3fc line.long 0x0 "COMPONENTID0,Component ID0" hexmask.long.byte 0x0 0.--7. 1. " PRBL ,Preamble" rgroup c14:0x3fd--0x3fd line.long 0x0 "COMPONENTID1,Component ID1" hexmask.long.byte 0x0 4.--7. 1. " CCLASS ,Component Class (CoreSight Component)" hexmask.long.byte 0x0 0.--3. 1. " PRBL ,Preamble" rgroup c14:0x3fe--0x3fe line.long 0x0 "COMPONENTID2,Component ID2" hexmask.long.byte 0x0 0.--7. 1. " PRBL ,Preamble" rgroup c14:0x3ff--0x3ff line.long 0x0 "COMPONENTID3,Component ID3" hexmask.long.byte 0x0 0.--7. 1. " PRBL ,Preamble" tree.end textline " " width 0x7 rgroup c14:0x000--0x000 line.long 0x0 "DIDR,Debug ID Register" bitfld.long 0x0 28.--31. " WRP ,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x0 24.--27. " BRP ,Number of Breakpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x0 20.--23. " CTX_CMP ,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" textline " " bitfld.long 0x0 16.--19. " VERSION ,Debug Architecture Version" "Reserved,ARMv6,ARMv6.1,ARMv7,?..." textline " " bitfld.long 0x0 13. " PCSAMPLE ,PC Sample register implemented" "Low,High" bitfld.long 0x0 12. " SECURITY ,Security Extensions implemented" "Not implemented,Implemented" textline " " bitfld.long 0x0 4.--7. " VARIANT ,Implementation-defined Variant Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 0.--3. " REVISION ,Implementation-defined Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group c14:0x22--0x22 line.long 0x0 "DSCR,Debug Status and Control Register" bitfld.long 0x0 30. " DTRRXFULL ,The DTRRX Full Flag" "Empty,Full" bitfld.long 0x0 29. " DTRTXfull ,The DTRTX Full Flag" "Empty,Full" textline " " bitfld.long 0x00 27. " DTRRXFULL_L ,The DTRRX Full Flag 1" "Empty,Full" bitfld.long 0x00 26. " DTRTXFULL_L ,The DTRTX Full Flag 1" "Empty,Full" textline " " bitfld.long 0x0 25. " SPA ,Sticky Pipeline Advance" "No effect,Instruction retired" bitfld.long 0x0 24. " IC ,Instruction Complete" "Executing,Not executing" textline " " bitfld.long 0x0 20.--21. " DTR ,DTR Access Mode" "Non-blocking,Stall,Fast,?..." bitfld.long 0x0 19. " NSWS ,Imprecise Data Aborts discarded" "Not discarded,Discarded" textline " " bitfld.long 0x0 18. " NS ,Non-secure World Status" "Secured,Not secured" bitfld.long 0x0 17. " NSPNIDEN ,Secure Non-invasive Debug Disabled" "Enabled,Disabled" textline " " bitfld.long 0x0 16. " NSPIDEN ,Secure Invasive Debug Disabled" "Enabled,Disabled" bitfld.long 0x0 15. " MONITOR ,Monitor Debug-mode enable" "Disabled,Enabled" textline " " bitfld.long 0x0 14. " HDEN ,Halting Debug-mode enable" "Disabled,Enabled" bitfld.long 0x0 13. " EXECUTE ,Execute instruction enable" "Disabled,Enabled" textline " " bitfld.long 0x0 12. " COMMS ,User mode access to Comms Channel disable" "Enabled,Disabled" bitfld.long 0x0 11. " INTDIS ,Disable Interrupts" "Enabled,Disabled" textline " " bitfld.long 0x0 10. " DBGACK ,Force Debug Acknowledge" "Not forced,Forced" bitfld.long 0x0 8. " UEXT ,Sticky Undefined Exception" "No exception,Exception" textline " " bitfld.long 0x0 7. " IABORT ,Sticky Imprecise Abort" "Not aborted,Aborted" bitfld.long 0x0 6. " PABORT ,Sticky Precise Abort" "Not aborted,Aborted" textline " " bitfld.long 0x0 2.--5. " MOE ,Method of Debug Entry" "Debug Entry,Breakpoint,Imprecise Watchpoint,BKPT instruction,External debug,Vector catch,Reserved,Reserved,OS Unlock,?..." bitfld.long 0x0 1. " RESTARTED ,Core Restarted" "Debug not exited,Debug exited" textline " " bitfld.long 0x0 0. " HALTED ,Core Halted" "Normal state,Debug state" if (((data.long(c14:0x00))&0x01000)==0x00000) group c14:0x007--0x007 line.long 0x0 "VCR,Vector Catch Register" bitfld.long 0x0 7. " FIQ ,Vector Catch Enable FIQ" "Disabled,Enabled" bitfld.long 0x0 6. " IRQ ,Vector Catch Enable IRQ" "Disabled,Enabled" textline " " bitfld.long 0x0 4. " DABORT ,Vector Catch Enable Data Abort" "Disabled,Enabled" bitfld.long 0x0 3. " PABORT ,Vector Catch Enable Prefetch Abort" "Disabled,Enabled" textline " " bitfld.long 0x0 2. " SWI ,Vector Catch Enable SWI" "Disabled,Enabled" bitfld.long 0x0 1. " UNDEF ,Vector Catch Enable Undefined Instruction" "Disabled,Enabled" textline " " bitfld.long 0x0 0. " RESET ,Vector Catch Enable Reset" "Disabled,Enabled" else group c14:0x007--0x007 line.long 0x0 "VCR,Vector Catch Register" bitfld.long 0x0 31. " FIQN ,Vector Catch Enable FIQ (Non-secure)" "Disabled,Enabled" bitfld.long 0x0 30. " IRQN ,Vector Catch Enable IRQ (Non-secure)" "Disabled,Enabled" textline " " bitfld.long 0x0 28. " DABORTN ,Vector Catch Enable Data Abort (Non-secure)" "Disabled,Enabled" bitfld.long 0x0 27. " PABORTN ,Vector Catch Enable Prefetch abort (Non-secure)" "Disabled,Enabled" textline " " bitfld.long 0x0 26. " SWIN ,Vector Catch Enable SWI (Non-secure)" "Disabled,Enabled" bitfld.long 0x0 25. " UNDEFS ,Vector Catch Enable Undefined (Non-secure)" "Disabled,Enabled" textline " " bitfld.long 0x0 15. " FIQS ,Vector Catch Enable FIQ (Secure)" "Disabled,Enabled" bitfld.long 0x0 14. " IRQS ,Vector Catch Enable IRQ (Secure)" "Disabled,Enabled" textline " " bitfld.long 0x0 12. " DABORTS ,Vector Catch Enable Data Abort (Secure)" "Disabled,Enabled" bitfld.long 0x00 11. " PABORTS ,Vector Catch Enable Prefetch abort (Secure)" "Disabled,Enabled" textline " " bitfld.long 0x0 10. " SMI ,Vector Catch Enable SMI (Secure)" "Disabled,Enabled" bitfld.long 0x0 7. " FIQ ,Vector Catch Enable FIQ" "Disabled,Enabled" textline " " bitfld.long 0x0 6. " IRQ ,Vector Catch Enable IRQ" "Disabled,Enabled" bitfld.long 0x0 4. " DABORT0 ,Vector Catch Enable Data Abort" "Disabled,Enabled" textline " " bitfld.long 0x0 3. " PABORT ,Vector Catch Enable Prefetch Abort" "Disabled,Enabled" bitfld.long 0x0 2. " SWI ,Vector Catch Enable SWI" "Disabled,Enabled" textline " " bitfld.long 0x0 1. " UNDEF ,Vector Catch Enable Undefined Instruction" "Disabled,Enabled" bitfld.long 0x0 0. " RESET ,Vector Catch Enable Reset" "Disabled,Enabled" endif hgroup c14:0x020--0x020 hide.long 0x0 "DTRRX,Target -> Host Data Transfer Register" in group c14:0x023--0x023 line.long 0x0 "DTRTX,Host -> Target Data Transfer Register" hexmask.long 0x00 0.--31. 1. " HTD ,Host -> target data" group c14:0x09++0x00 line.long 0x00 "ECR,Event Catch Register" bitfld.long 0x00 0. " OSUC ,OS Unlock Catch" "Disabled,Enabled" group c14:0x0a++0x00 line.long 0x00 "DSCCR,Debug State Cache Control Register" bitfld.long 0x00 2. " NWT ,Not Write-Through" "Forced,Normal" bitfld.long 0x00 0. " DUCL ,Data and Unified Cache Linefill" "Disabled,Normal" wgroup c14:0x21++0x00 line.long 0x00 "ITR,Instruction Transfer Register" hexmask.long 0x00 0.--31. 1. " Data ,ARM Instruction for the Processor in Debug State Execute" wgroup c14:0x24++0x00 line.long 0x00 "DRCR,Debug Run Control Register" bitfld.long 0x00 3. " CSPA ,Clear Sticky Pipeline Advance" "Not cleared,Cleared" bitfld.long 0x00 2. " CSE ,Clear Sticky Exceptions" "Not cleared,Cleared" textline " " bitfld.long 0x00 1. " RR ,Restart Request" "Not requested,Requested" bitfld.long 0x00 0. " HR ,Halt Request" "Not requested,Requested" wgroup c14:0xc0++0x00 line.long 0x00 "OSLAR,Operating System Lock Access Register" hexmask.long 0x00 0.--31. 1. " OSLA ,OS Lock Access" rgroup c14:0xc1++0x00 line.long 0x00 "OSLSR,Operating System Lock Status Register" bitfld.long 0x00 2. " 32_BA ,32-Bit Access" "Not required,Required" bitfld.long 0x00 1. " LB ,Locked Bit" "Not locked,Locked" bitfld.long 0x00 0. " LIB ,Lock Implemented Bit" "Not implemented,Implemented" group c14:0xc2++0x00 line.long 0x00 "OSSRR,Operating System Save and Restore Register" hexmask.long 0x00 0.--31. 1. " OSSR ,OS Save and Restore" group c14:0xc4++0x00 line.long 0x00 "PRCR,Device Power-Down and Reset Control Register" bitfld.long 0x00 2. " HIR ,Hold Internal Reset" "Not held,Held" bitfld.long 0x00 1. " FIR ,Force Internal Reset" "Not forced,Forced" bitfld.long 0x00 0. " NPD ,No Power-Down" "DBGNOPWRDWN low,DBGNOPWRDWN high" hgroup c14:0xc5++0x00 hide.long 0x00 "PRSR,Device Power-Down and Reset Status Register" in tree.end tree "Breakpoint Registers" group c14:0x40++0x00 line.long 0x00 "BVR0,Breakpoint Value Register 0" hexmask.long 0x00 0.--31. 1. " BV0 ,Breakpoint Value 0" group c14:0x50++0x00 line.long 0x00 "BCR0,Breakpoint Control Register 0" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Reserved,Reserved,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group c14:0x41++0x00 line.long 0x00 "BVR1,Breakpoint Value Register 1" hexmask.long 0x00 0.--31. 1. " BV1 ,Breakpoint Value 1" group c14:0x51++0x00 line.long 0x00 "BCR1,Breakpoint Control Register 1" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Reserved,Reserved,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group c14:0x42++0x00 line.long 0x00 "BVR2,Breakpoint Value Register 2" hexmask.long 0x00 0.--31. 1. " BV2 ,Breakpoint Value 2" group c14:0x52++0x00 line.long 0x00 "BCR2,Breakpoint Control Register 2" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Reserved,Reserved,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group c14:0x43++0x00 line.long 0x00 "BVR3,Breakpoint Value Register 3" hexmask.long 0x00 0.--31. 1. " BV3 ,Breakpoint Value 3" group c14:0x53++0x00 line.long 0x00 "BCR3,Breakpoint Control Register 3" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Reserved,Reserved,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group c14:0x44++0x00 line.long 0x00 "BVR4,Breakpoint Value Register 4" hexmask.long 0x00 0.--31. 1. " BV4 ,Breakpoint Value 4" group c14:0x54++0x00 line.long 0x00 "BCR4,Breakpoint Control Register 4" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group c14:0x45++0x00 line.long 0x00 "BVR5,Breakpoint Value Register 5" hexmask.long 0x00 0.--31. 1. " BV5 ,Breakpoint Value 5" group c14:0x55++0x00 line.long 0x00 "BCR5,Breakpoint Control Register 5" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group c14:0x46++0x00 line.long 0x00 "BVR6,Breakpoint Value Register 6" hexmask.long 0x00 0.--31. 1. " BV6 ,Breakpoint Value 6" group c14:0x56++0x00 line.long 0x00 "BCR6,Breakpoint Control Register 6" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group c14:0x47++0x00 line.long 0x00 "BVR7,Breakpoint Value Register 7" hexmask.long 0x00 0.--31. 1. " BV7 ,Breakpoint Value 7" group c14:0x57++0x00 line.long 0x00 "BCR7,Breakpoint Control Register 7" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" tree.end tree "Watchpoint Control Registers" group c14:0x60++0x00 line.long 0x00 "WVR0,Watchpoint Value Register 0" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group c14:0x70--0x70 line.long 0x0 "WCR0,Watchpoint Control Register 0" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group c14:0x61++0x00 line.long 0x00 "WVR1,Watchpoint Value Register 1" hexmask.long 0x00 2.--31. 0x04 " WA1 ,Watchpoint Address 1" group c14:0x71--0x71 line.long 0x0 "WCR1,Watchpoint Control Register 1" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group c14:0x62++0x00 line.long 0x00 "WVR2,Watchpoint Value Register 2" hexmask.long 0x00 2.--31. 0x04 " WA2 ,Watchpoint Address 2" group c14:0x72--0x72 line.long 0x0 "WCR2,Watchpoint Control Register 2" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group c14:0x63++0x00 line.long 0x00 "WVR3,Watchpoint Value Register 3" hexmask.long 0x00 2.--31. 0x04 " WA3 ,Watchpoint Address 3" group c14:0x73--0x73 line.long 0x0 "WCR3,Watchpoint Control Register 3" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group c14:0x64++0x00 line.long 0x00 "WVR4,Watchpoint Value Register 4" hexmask.long 0x00 2.--31. 0x04 " WA4 ,Watchpoint Address 4" group c14:0x74--0x74 line.long 0x0 "WCR4,Watchpoint Control Register 4" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group c14:0x65++0x00 line.long 0x00 "WVR5,Watchpoint Value Register 5" hexmask.long 0x00 2.--31. 0x04 " WA5 ,Watchpoint Address 5" group c14:0x75--0x75 line.long 0x0 "WCR5,Watchpoint Control Register 5" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group c14:0x66++0x00 line.long 0x00 "WVR6,Watchpoint Value Register 6" hexmask.long 0x00 2.--31. 0x04 " WA6 ,Watchpoint Address 6" group c14:0x76--0x76 line.long 0x0 "WCR6,Watchpoint Control Register 6" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group c14:0x67++0x00 line.long 0x00 "WVR7,Watchpoint Value Register 7" hexmask.long 0x00 2.--31. 0x04 " WA7 ,Watchpoint Address 7" group c14:0x77--0x77 line.long 0x0 "WCR7,Watchpoint Control Register 7" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group c14:0x006--0x006 line.long 0x0 "WFAR,Watchpoint Fault Address Register" hexmask.long.long 0x00 1.--31. 0x02 " WFAR ,Address of the watchpointed instruction" tree.end AUTOINDENT.POP tree.end ; Periphal Modules Registers tree.open "ADC (Analog to Digital Converter)" tree "MIBADC1" base ad:0xFFF7C000 width 10. group.long 0x00++0x3 line.long 0x0 "RSTCR,Reset Control Register" bitfld.long 0x00 0. " Reset ,ADC Reset" "No reset,Reset" group.long 0x04++0x3 sif (cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")) line.long 0x0 "PWDNCR,Powerdown Control Register" else line.long 0x0 "ADOPMODECR,Operating Mode Control Register" bitfld.long 0x00 24. " COS ,Emulation Operation" "Halts,Continues" bitfld.long 0x00 16. " RAM_TEST_EN ,Enable ADC results" "Disabled,Enabled" bitfld.long 0x00 0. " ADC_EN ,ADC Enable" "Disabled,Enabled" endif group.long 0x08++0x3 line.long 0x0 "CLOCKCR,Clock Prescaler" bitfld.long 0x00 0.--4. " PS[4:0] ,ADC Clock Prescaler" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles" width 10. if (((d.l((ad:0xFFF7C000+0x0c)))&0x01000201)==0x00000001) group.long (0x0c)++0x03 line.long 0x00 "CALCR,Calibration Conversion Register" bitfld.long 0x00 24. " SELF_TEST ,Self-Test Enable" "Disabled,Enabled" bitfld.long 0x00 16. " CAL_ST ,Calibration Conversion Start" "No effect/completed,Started" textline " " bitfld.long 0x00 9. " BRIDGE_EN ,Bridge Enable" "Midpoint,Full" bitfld.long 0x00 0. " CAL_EN ,Calibration Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " HILO ,Test and Reference Source Selection" "(AD_REFHI*R1+AD_REFLO*R2)/(R1+R2),(AD_REFLO*R1+AD_REFHI*R2)/(R1+R2)" elif (((d.l((ad:0xFFF7C000+0x0c)))&0x01000201)==0x01000000) group.long (0x0c)++0x03 line.long 0x00 "CALCR,Calibration Conversion Register" bitfld.long 0x00 24. " SELF_TEST ,Self-Test Enable" "Disabled,Enabled" bitfld.long 0x00 16. " CAL_ST ,Calibration Conversion Start" "No effect/completed,Started" textline " " bitfld.long 0x00 9. " BRIDGE_EN ,Bridge Enable" "Midpoint,Full" bitfld.long 0x00 0. " CAL_EN ,Calibration Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " HILO ,Test and Reference Source Selection" "(AD_REFLO via R1)||(R2 to Vin),(AD_REFHI via R1)||(R2 to Vin)" elif (((d.l((ad:0xFFF7C000+0x0c)))&0x01000201)==0x00000201) group.long (0x0c)++0x03 line.long 0x00 "CALCR,Calibration Conversion Register" bitfld.long 0x00 24. " SELF_TEST ,Self-Test Enable" "Disabled,Enabled" bitfld.long 0x00 16. " CAL_ST ,Calibration Conversion Start" "No effect/completed,Started" textline " " bitfld.long 0x00 9. " BRIDGE_EN ,Bridge Enable" "Midpoint,Full" bitfld.long 0x00 0. " CAL_EN ,Calibration Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " HILO ,Test and Reference Source Selection" "AD_REFLO,AD_REFHI" elif (((d.l((ad:0xFFF7C000+0x0c)))&0x01000201)==0x01000200) group.long (0x0c)++0x03 line.long 0x00 "CALCR,Calibration Conversion Register" bitfld.long 0x00 24. " SELF_TEST ,Self-Test Enable" "Disabled,Enabled" bitfld.long 0x00 16. " CAL_ST ,Calibration Conversion Start" "No effect/completed,Started" textline " " bitfld.long 0x00 9. " BRIDGE_EN ,Bridge Enable" "Midpoint,Full" bitfld.long 0x00 0. " CAL_EN ,Calibration Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " HILO ,Test and Reference Source Selection" "(AD_REFLO via R1)||(R2 to Vin),(AD_REFHI via R1)||(R2 to Vin)" else group.long (0x0c)++0x03 line.long 0x00 "CALCR,Calibration Conversion Register" bitfld.long 0x00 24. " SELF_TEST ,Self-Test Enable" "Disabled,Enabled" bitfld.long 0x00 16. " CAL_ST ,Calibration Conversion Start" "No effect/completed,Started" textline " " bitfld.long 0x00 9. " BRIDGE_EN ,Bridge Enable" "Midpoint,Full" bitfld.long 0x00 0. " CAL_EN ,Calibration Enable" "Disabled,Enabled" endif width 10. group.long 0x10++0x3 line.long 0x0 "EVMODECR,EV MODE Control Register" bitfld.long 0x00 8.--9. " EV_DATA_FMT ,Event Group (Read) Data Format" "12 bit,10 bit,8 bit,?..." bitfld.long 0x00 5. " EV_CHID ,Channel ID Mode for the Event Group" "Forced to 0,ID of A/D channel" textline " " bitfld.long 0x00 4. " OVR_EV_RAM_IGN ,Overrun Event Group RAM Ignore" "Not ignored,Ignored" bitfld.long 0x00 1. " EV_MODE ,Event mode" "Single,Continuous" textline " " bitfld.long 0x00 0. " FRZ_EV ,Freeze conversion event group" "Completed,Frozen" group.long 0x14++0x3 line.long 0x0 "G1MODECR,G1 MODE Control Register" bitfld.long 0x00 8.--9. " G1_DATA_FMT ,Group1 (Read) Data Format" "12 bit,10 bit,8 bit,?..." bitfld.long 0x00 5. " G1_CHID ,Channel ID Mode for the Group 1" "Forced to 0,ID of A/D channel" textline " " bitfld.long 0x00 4. " OVR_G1_RAM_IGN ,Overrun Group 1 RAM Ignore" "Not ignored,Ignored" bitfld.long 0x00 3. " G1_HW_TRIG ,Group 1 Hardware Triggered" "Software,Event" textline " " bitfld.long 0x00 1. " G1_MODE ,Group 1 mode" "Single,Continuous" bitfld.long 0x00 0. " FRZ_G1 ,Freeze Conversion group 1" "Completed,Frozen" group.long 0x18++0x3 line.long 0x0 "G2MODECR,G2 MODE Control Register" bitfld.long 0x00 8.--9. " G2_DATA_FMT ,Group2 (Read) Data Format" "12 bit,10 bit,8 bit,?..." bitfld.long 0x00 5. " G2_CHID ,Channel ID Mode for the Group 2" "Forced to 0,ID of A/D channel" textline " " bitfld.long 0x00 4. " OVR_G2_RAM_IGN ,Overrun Group 2 RAM Ignore" "Not ignored,Ignored" bitfld.long 0x00 3. " G2_HW_TRIG ,Group 2 Hardware Triggered" "Software,Event" textline " " bitfld.long 0x00 1. " G2_MODE ,Group 2 Mode" "Single,Continuous" bitfld.long 0x00 0. " FRZ_G2 ,Freeze Conversion Group 2" "Completed,Frozen" group.long 0x1C++0x3 line.long 0x0 "EVSRC,Event Group Trigger Source Select" bitfld.long 0x00 3. " EV_EDG_SEL ,ADC Event Group Trigger Edge Select" "High/low,Low/high" bitfld.long 0x00 0.--2. " EVSRC[2:0] ,Event Group Trigger Source Select" "AD1EVT,HET[8],HET[10],RTI compare 0,HET[17],HET[19],GIOB[0],GIOB[1]" group.long 0x20++0x3 line.long 0x0 "EVG1SRC,Group 1 Trigger Source Select" bitfld.long 0x00 3. " G1_EDG_SEL ,ADC Group 1 Trigger Edge Select" "High/low,Low/high" bitfld.long 0x00 0.--2. " G1SRC[2:0] ,Group 1 Trigger Source Select" "AD1EVT,HET[8],HET[10],RTI compare 0,HET[17],HET[19],GIOB[0],GIOB[1]" group.long 0x24++0x3 line.long 0x0 "G2SRC,Group 2 Trigger Source Select" bitfld.long 0x00 3. " G2_EDG_SEL ,ADC Group 2 Trigger Edge Select" "High/low,Low/high" bitfld.long 0x00 0.--2. " G2SRC[2:0] ,Group 2 Trigger Source Select" "AD1EVT,HET[8],HET[10],RTI compare 0,HET[17],HET[19],GIOB[0],GIOB[1]" width 10. group.long 0x28++0x3 line.long 0x0 "EVINTENA,Event Group Interrupt Enable" bitfld.long 0x00 3. " EV_END_INT_EN ,Event Group Conversion End Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 1. " EV_OVR_INT_EN ,Event Group Memory Overrun Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " EV_THR_INT_EN ,Event Group Memory Threshold Interrupt Enable" "Disabled,Enabled" group.long 0x2C++0x3 line.long 0x0 "G1INTENA,Group 1 Interrupt Enable" bitfld.long 0x00 3. " G1_END_INT_EN ,Event Group Conversion End Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 1. " G1_OVR_INT_EN ,Group 1 Memory Overrun Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " G1_THR_INT_EN ,Group 1 Memory Threshold Interrupt Enable" "Disabled,Enabled" group.long 0x30++0x3 line.long 0x0 "G2INTENA,Group 2 Interrupt Enable" bitfld.long 0x00 3. " G2_END_INT_EN ,Event Group Conversion End Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 1. " G2_OVR_INT_EN ,Group 2 Memory Overrun Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " G2_THR_INT_EN ,Group 2 Memory Threshold Interrupt Enable" "Disabled,Enabled" width 10. group.long 0x34++0x3 line.long 0x0 "EVINTFLG,Event Group Interrupt Flag" eventfld.long 0x00 3. " EV_END ,Event Group Conversion End" "Not converted,Converted" bitfld.long 0x00 2. " EV_MEM_EMPTY ,Event Group FIFO Empty Status" "Not empty,Empty" textline " " bitfld.long 0x00 1. " EV_MEM_OVERFLOW ,Event Group Memory Overrun Flag" "No overrun,Overrun" eventfld.long 0x00 0. " EV_THR_INT_FLAG ,Event Group Threshold Interrupt Flag" "No interrupt,Interrupt" group.long 0x38++0x3 line.long 0x0 "G1INTFLG,Group 1 Interrupt Flag" eventfld.long 0x00 3. " G1_END ,Group 1 Conversion End" "Not converted,Converted" bitfld.long 0x00 2. " AD_G1_MEM_EMPTY ,Group1 FIFO Empty Status" "Not empty,Empty" textline " " bitfld.long 0x00 1. " G1_MEM_OVERFLOW ,Event Group Memory Overrun Flag" "No overrun,Overrun" eventfld.long 0x00 0. " G1_THR_INT_FLAG ,Group 1 Threshold Interrupt Flag" "No interrupt,Interrupt" group.long 0x3C++0x3 line.long 0x0 "G2INTFLG,Group 2 Interrupt Flag" eventfld.long 0x00 3. " G2_END ,Group 2 Conversion End" "Not converted,Converted" bitfld.long 0x00 2. " AD_G2_MEM_EMPTY ,Group2 FIFO Empty Status" "Not empty,Empty" textline " " bitfld.long 0x00 1. " G2_MEM_OVERFLOW ,Group 2 Memory Overrun Flag" "No overrun,Overrun" eventfld.long 0x00 0. " G2_THR_INT_FLAG ,Group 2 Threshold Interrupt Flag" "No interrupt,Interrupt" group.long 0x40++0x3 line.long 0x0 "EVINTCR,Event Group Interrupt Threshold Counter" hexmask.long.byte 0x00 9.--15. 1. " Sign_Extension ,Sign Extension" hexmask.long.word 0x00 0.--8. 1. " EVTHR[8:0] ,Event Group Interrupt Threshold Counter" group.long 0x44++0x3 line.long 0x0 "G1INTCR,Group 1 Interrupt Threshold Counter" hexmask.long.byte 0x00 9.--15. 1. " Sign_Extension ,Sign Extension" hexmask.long.word 0x00 0.--8. 1. " G1THR[8:0] ,Group 1 Interrupt Threshold Counter" group.long 0x48++0x3 line.long 0x0 "G2INTCR,Group 2 Interrupt Threshold Counter" hexmask.long.byte 0x00 9.--15. 1. " Sign_Extension ,Sign Extension" hexmask.long.word 0x00 0.--8. 1. " G2THR[8:0] ,Group 2 Interrupt Threshold Counter" width 10. group.long 0x4C++0x3 line.long 0x0 "EVDMACR,Event Group DMA Control Register" hexmask.long.word 0x00 16.--24. 1. " EVBLOCKS[8:0] ,Number of Event Group Memory Buffers to be Transferred" bitfld.long 0x00 2. " EV_BLK_XFER ,Event Group Block DMA Transfer Enable" "Disabled,Enabled" bitfld.long 0x00 0. " EV_DMA_EN ,Event Group DMA Transfer Enable" "Disabled,Enabled" group.long 0x50++0x3 line.long 0x0 "G1DMACR,Group 1 DMA Control Register" hexmask.long.word 0x00 16.--24. 1. " G1BLOCKS[8:0] ,Number of Group 1 Memory Buffers to be Transferred" bitfld.long 0x00 2. " G1_BLK_XFER ,Group 1 Block DMA Transfer Enable" "Disabled,Enabled" bitfld.long 0x00 0. " G1_DMA_EN ,Group 1 DMA Transfer Enable" "Disabled,Enabled" group.long 0x54++0x3 line.long 0x0 "G2DMACR,Group 2 DMA Control Register" hexmask.long.word 0x00 16.--24. 1. " G2BLOCKS[8:0] ,Number of Group 2 Memory Buffers to be Transferred" bitfld.long 0x00 2. " G2_BLK_XFER ,Group 2 Block DMA Transfer Enable" "Disabled,Enabled" bitfld.long 0x00 0. " G2_DMA_EN ,Group 2 DMA Transfer Enable" "Disabled,Enabled" group.long 0x58++0x3 line.long 0x0 "BNDCR,Buffer Boundary Control Register" hexmask.long.word 0x00 16.--24. 1. " BNDA[8:0] ,Buffer Boundary A" hexmask.long.word 0x00 0.--8. 1. " BNDB[8:0] ,Buffer Boundary B" width 10. group.long 0x5C++0x3 line.long 0x0 "BNDEND,Buffer End Boundary" bitfld.long 0x00 16. " BUF_Init_Active ,Indicates the Status of the ADC RAM Intialization Process" "Not initialized,Initialized" bitfld.long 0x00 0.--2. " BNDEND[2:0] ,Buffer End Boundary" "16 words,32 words,64 words,128 words,192 words,256 words,512 words,1024 words" width 8. tree "ADC Sample Control Registers" group.long 0x60++0x3 line.long 0x0 "EVSAMP,Event Group Sample Window" hexmask.long.word 0x00 0.--11. 1. " EVACQ[11:0] ,Event Group Acquisition Prescale Bits" group.long 0x64++0x3 line.long 0x0 "G1SAMP,Group 1 Sample Window" hexmask.long.word 0x00 0.--11. 1. " G1ACQ[11:0] ,Group 1 Acquisition Prescale Bits" group.long 0x68++0x3 line.long 0x0 "G2SAMP,Group 2 Sample Window" hexmask.long.word 0x00 0.--11. 1. " G2ACQ[11:0] ,Group 2 Acquisition Prescale Bits" tree.end tree "ADC Status Registers" width 6. group.long 0x6C++0x3 line.long 0x0 "EVSR,Event Group Status Register" bitfld.long 0x00 3. " EV_MEM_EMPTY ,Event Group Memory Empty" "Not empty,Empty" bitfld.long 0x00 2. " EV_BUSY ,Event Group Conversion-Busy Flag" "Not active,Busy" bitfld.long 0x00 1. " EV_STOP ,Event Group Conversion Stopped Flag" "Not frozen,Frozen" textline " " eventfld.long 0x00 0. " EV_END ,Event Conversion-Ended Flag R/W" "Not completed,Completed" group.long 0x70++0x3 line.long 0x0 "G1SR,Group 1 Status Register" bitfld.long 0x00 3. " G1_MEM_EMPTY ,Group 1 Memory Empty" "Not empty,Empty" bitfld.long 0x00 2. " G1_BUSY ,Group 1 Conversion-Busy Flag" "Not active,Busy" bitfld.long 0x00 1. " G1_STOP ,Group 1 Conversion Stopped Flag" "Not frozen,Frozen" textline " " eventfld.long 0x00 0. " G1_END ,Group 1 Conversion-Ended Flag" "Not completed,Completed" group.long 0x74++0x3 line.long 0x0 "G2SR,Group 2 Status Register" bitfld.long 0x00 3. " G2_MEM_EMPTY ,Group 2 Memory Empty" "Not empty,Empty" bitfld.long 0x00 2. " G2_BUSY ,Group 2 Conversion-Busy Flag" "Not active,Busy" bitfld.long 0x00 1. " G2_STOP ,Group 2 Conversion Stopped Flag" "Not frozen,Frozen" textline " " eventfld.long 0x00 0. " G2_END ,Group 2 conversion-ended flag" "Not completed,Completed" tree.end tree "ADC Selection Control Registers" width 7. group.long 0x78++0x3 line.long 0x0 "EVSEL,Event Group select register" sif (cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")) bitfld.long 0x00 31. " EVCHNSEL[31] ,A/D Event Channel 31 Selection Bit" "Not converted,Converted" bitfld.long 0x00 30. " EVCHNSEL[30] ,A/D Event Channel 30 Selection Bit" "Not converted,Converted" textline " " bitfld.long 0x00 29. " EVCHNSEL[29] ,A/D Event Channel 29 Selection Bit" "Not converted,Converted" bitfld.long 0x00 28. " EVCHNSEL[28] ,A/D Event Channel 28 Selection Bit" "Not converted,Converted" textline " " bitfld.long 0x00 27. " EVCHNSEL[27] ,A/D Event Channel 27 Selection Bit" "Not converted,Converted" bitfld.long 0x00 26. " EVCHNSEL[26] ,A/D Event Channel 26 Selection Bit" "Not converted,Converted" textline " " bitfld.long 0x00 25. " EVCHNSEL[25] ,A/D Event Channel 25 Selection Bit" "Not converted,Converted" bitfld.long 0x00 24. " EVCHNSEL[24] ,A/D Event Channel 24 Selection Bit" "Not converted,Converted" textline " " bitfld.long 0x00 23. " EVCHNSEL[23] ,A/D Event Channel 23 Selection Bit" "Not converted,Converted" bitfld.long 0x00 22. " EVCHNSEL[22] ,A/D Event Channel 22 Selection Bit" "Not converted,Converted" textline " " bitfld.long 0x00 21. " EVCHNSEL[21] ,A/D Event Channel 21 Selection Bit" "Not converted,Converted" bitfld.long 0x00 20. " EVCHNSEL[20] ,A/D Event Channel 20 Selection Bit" "Not converted,Converted" textline " " bitfld.long 0x00 19. " EVCHNSEL[19] ,A/D Event Channel 19 Selection Bit" "Not converted,Converted" bitfld.long 0x00 18. " EVCHNSEL[18] ,A/D Event Channel 18 Selection Bit" "Not converted,Converted" textline " " bitfld.long 0x00 17. " EVCHNSEL[17] ,A/D Event Channel 17 Selection Bit" "Not converted,Converted" bitfld.long 0x00 16. " EVCHNSEL[16] ,A/D Event Channel 16 Selection Bit" "Not converted,Converted" textline " " endif bitfld.long 0x00 15. " EVCHNSEL[15] ,A/D Event Channel 15 Selection Bit" "Not converted,Converted" bitfld.long 0x00 14. " EVCHNSEL[14] ,A/D Event Channel 14 Selection Bit" "Not converted,Converted" textline " " bitfld.long 0x00 13. " EVCHNSEL[13] ,A/D Event Channel 13 Selection Bit" "Not converted,Converted" bitfld.long 0x00 12. " EVCHNSEL[12] ,A/D Event Channel 12 Selection Bit" "Not converted,Converted" textline " " bitfld.long 0x00 11. " EVCHNSEL[11] ,A/D Event Channel 11 Selection Bit" "Not converted,Converted" bitfld.long 0x00 10. " EVCHNSEL[10] ,A/D Event Channel 10 Selection Bit" "Not converted,Converted" textline " " bitfld.long 0x00 9. " EVCHNSEL[9] ,A/D Event Channel 9 Selection Bit" "Not converted,Converted" bitfld.long 0x00 8. " EVCHNSEL[8] ,A/D Event Channel 8 Selection Bit" "Not converted,Converted" textline " " bitfld.long 0x00 7. " EVCHNSEL[7] ,A/D Event Channel 7 Selection Bit" "Not converted,Converted" bitfld.long 0x00 6. " EVCHNSEL[6] ,A/D Event Channel 6 Selection Bit" "Not converted,Converted" textline " " bitfld.long 0x00 5. " EVCHNSEL[5] ,A/D Event Channel 5 Selection Bit" "Not converted,Converted" bitfld.long 0x00 4. " EVCHNSEL[4] ,A/D Event Channel 4 Selection Bit" "Not converted,Converted" textline " " bitfld.long 0x00 3. " EVCHNSEL[3] ,A/D Event Channel 3 Selection Bit" "Not converted,Converted" bitfld.long 0x00 2. " EVCHNSEL[2] ,A/D Event Channel 2 Selection Bit" "Not converted,Converted" textline " " bitfld.long 0x00 1. " EVCHNSEL[1] ,A/D Event Channel 1 Selection Bit" "Not converted,Converted" bitfld.long 0x00 0. " EVCHNSEL[0] ,A/D Event Channel 0 Selection Bit" "Not converted,Converted" group.long 0x7C++0x3 line.long 0x0 "G1SEL,Group 1 select register" sif (cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")) bitfld.long 0x00 31. " G1CHNSEL[31] ,A/D Channel 31 Enable Bit" "Not converted,Converted" bitfld.long 0x00 30. " G1CHNSEL[30] ,A/D Channel 30 Enable Bit" "Not converted,Converted" textline " " bitfld.long 0x00 29. " G1CHNSEL[29] ,A/D Channel 29 Enable Bit" "Not converted,Converted" bitfld.long 0x00 28. " G1CHNSEL[28] ,A/D Channel 28 Enable Bit" "Not converted,Converted" textline " " bitfld.long 0x00 27. " G1CHNSEL[27] ,A/D Channel 27 Enable Bit" "Not converted,Converted" bitfld.long 0x00 26. " G1CHNSEL[26] ,A/D Channel 26 Enable Bit" "Not converted,Converted" textline " " bitfld.long 0x00 25. " G1CHNSEL[25] ,A/D Channel 25 Enable Bit" "Not converted,Converted" bitfld.long 0x00 24. " G1CHNSEL[24] ,A/D Channel 24 Enable Bit" "Not converted,Converted" textline " " bitfld.long 0x00 23. " G1CHNSEL[23] ,A/D Channel 23 Enable Bit" "Not converted,Converted" bitfld.long 0x00 22. " G1CHNSEL[22] ,A/D Channel 22 Enable Bit" "Not converted,Converted" textline " " bitfld.long 0x00 21. " G1CHNSEL[21] ,A/D Channel 21 Enable Bit" "Not converted,Converted" bitfld.long 0x00 20. " G1CHNSEL[20] ,A/D Channel 20 Enable Bit" "Not converted,Converted" textline " " bitfld.long 0x00 19. " G1CHNSEL[19] ,A/D Channel 19 Enable Bit" "Not converted,Converted" bitfld.long 0x00 18. " G1CHNSEL[18] ,A/D Channel 18 Enable Bit" "Not converted,Converted" textline " " bitfld.long 0x00 17. " G1CHNSEL[17] ,A/D Channel 17 Enable Bit" "Not converted,Converted" bitfld.long 0x00 16. " G1CHNSEL[16] ,A/D Channel 16 Enable Bit" "Not converted,Converted" textline " " endif bitfld.long 0x00 15. " G1CHNSEL[15] ,A/D Channel 15 Enable Bit" "Not converted,Converted" bitfld.long 0x00 14. " G1CHNSEL[14] ,A/D Channel 14 Enable Bit" "Not converted,Converted" textline " " bitfld.long 0x00 13. " G1CHNSEL[13] ,A/D Channel 13 Enable Bit" "Not converted,Converted" bitfld.long 0x00 12. " G1CHNSEL[12] ,A/D Channel 12 Enable Bit" "Not converted,Converted" textline " " bitfld.long 0x00 11. " G1CHNSEL[11] ,A/D Channel 11 Enable Bit" "Not converted,Converted" bitfld.long 0x00 10. " G1CHNSEL[10] ,A/D Channel 10 Enable Bit" "Not converted,Converted" textline " " bitfld.long 0x00 9. " G1CHNSEL[9] ,A/D Channel 9 Enable Bit" "Not converted,Converted" bitfld.long 0x00 8. " G1CHNSEL[8] ,A/D Channel 8 Enable Bit" "Not converted,Converted" textline " " bitfld.long 0x00 7. " G1CHNSEL[7] ,A/D Channel 7 Enable Bit" "Not converted,Converted" bitfld.long 0x00 6. " G1CHNSEL[6] ,A/D Channel 6 Enable Bit" "Not converted,Converted" textline " " bitfld.long 0x00 5. " G1CHNSEL[5] ,A/D Channel 5 Enable Bit" "Not converted,Converted" bitfld.long 0x00 4. " G1CHNSEL[4] ,A/D Channel 4 Enable Bit" "Not converted,Converted" textline " " bitfld.long 0x00 3. " G1CHNSEL[3] ,A/D Channel 3 Enable Bit" "Not converted,Converted" bitfld.long 0x00 2. " G1CHNSEL[2] ,A/D Channel 2 Enable Bit" "Not converted,Converted" textline " " bitfld.long 0x00 1. " G1CHNSEL[1] ,A/D Channel 1 Enable Bit" "Not converted,Converted" bitfld.long 0x00 0. " G1CHNSEL[0] ,A/D Channel 0 Enable Bit" "Not converted,Converted" group.long 0x80++0x3 line.long 0x0 "G2SEL,Group 2 select register" sif (cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")) bitfld.long 0x00 31. " G2CHNSEL[31] ,A/D Channel 31 Enable Bit" "Not converted,Converted" bitfld.long 0x00 30. " G2CHNSEL[30] ,A/D Channel 30 Enable Bit" "Not converted,Converted" textline " " bitfld.long 0x00 29. " G2CHNSEL[29] ,A/D Channel 29 Enable Bit" "Not converted,Converted" bitfld.long 0x00 28. " G2CHNSEL[28] ,A/D Channel 28 Enable Bit" "Not converted,Converted" textline " " bitfld.long 0x00 27. " G2CHNSEL[27] ,A/D Channel 27 Enable Bit" "Not converted,Converted" bitfld.long 0x00 26. " G2CHNSEL[26] ,A/D Channel 26 Enable Bit" "Not converted,Converted" textline " " bitfld.long 0x00 25. " G2CHNSEL[25] ,A/D Channel 25 Enable Bit" "Not converted,Converted" bitfld.long 0x00 24. " G2CHNSEL[24] ,A/D Channel 24 Enable Bit" "Not converted,Converted" textline " " bitfld.long 0x00 23. " G2CHNSEL[23] ,A/D Channel 23 Enable Bit" "Not converted,Converted" bitfld.long 0x00 22. " G2CHNSEL[22] ,A/D Channel 22 Enable Bit" "Not converted,Converted" textline " " bitfld.long 0x00 21. " G2CHNSEL[21] ,A/D Channel 21 Enable Bit" "Not converted,Converted" bitfld.long 0x00 20. " G2CHNSEL[20] ,A/D Channel 20 Enable Bit" "Not converted,Converted" textline " " bitfld.long 0x00 19. " G2CHNSEL[19] ,A/D Channel 19 Enable Bit" "Not converted,Converted" bitfld.long 0x00 18. " G2CHNSEL[18] ,A/D Channel 18 Enable Bit" "Not converted,Converted" textline " " bitfld.long 0x00 17. " G2CHNSEL[17] ,A/D Channel 17 Enable Bit" "Not converted,Converted" bitfld.long 0x00 16. " G2CHNSEL[16] ,A/D Channel 16 Enable Bit" "Not converted,Converted" textline " " endif bitfld.long 0x00 15. " G2CHNSEL[15] ,A/D Channel 15 Enable Bit" "Not converted,Converted" bitfld.long 0x00 14. " G2CHNSEL[14] ,A/D Channel 14 Enable Bit" "Not converted,Converted" textline " " bitfld.long 0x00 13. " G2CHNSEL[13] ,A/D Channel 13 Enable Bit" "Not converted,Converted" bitfld.long 0x00 12. " G2CHNSEL[12] ,A/D Channel 12 Enable Bit" "Not converted,Converted" textline " " bitfld.long 0x00 11. " G2CHNSEL[11] ,A/D Channel 11 Enable Bit" "Not converted,Converted" bitfld.long 0x00 10. " G2CHNSEL[10] ,A/D Channel 10 Enable Bit" "Not converted,Converted" textline " " bitfld.long 0x00 9. " G2CHNSEL[9] ,A/D Channel 9 Enable Bit" "Not converted,Converted" bitfld.long 0x00 8. " G2CHNSEL[8] ,A/D Channel 8 Enable Bit" "Not converted,Converted" textline " " bitfld.long 0x00 7. " G2CHNSEL[7] ,A/D Channel 7 Enable Bit" "Not converted,Converted" bitfld.long 0x00 6. " G2CHNSEL[6] ,A/D Channel 6 Enable Bit" "Not converted,Converted" textline " " bitfld.long 0x00 5. " G2CHNSEL[5] ,A/D Channel 5 Enable Bit" "Not converted,Converted" bitfld.long 0x00 4. " G2CHNSEL[4] ,A/D Channel 4 Enable Bit" "Not converted,Converted" textline " " bitfld.long 0x00 3. " G2CHNSEL[3] ,A/D Channel 3 Enable Bit" "Not converted,Converted" bitfld.long 0x00 2. " G2CHNSEL[2] ,A/D Channel 2 Enable Bit" "Not converted,Converted" textline " " bitfld.long 0x00 1. " G2CHNSEL[1] ,A/D Channel 1 Enable Bit" "Not converted,Converted" bitfld.long 0x00 0. " G2CHNSEL[0] ,A/D Channel 0 Enable Bit" "Not converted,Converted" tree.end width 10. textline " " group.long 0x84++0x3 line.long 0x0 "CALR,Calibration Register" hexmask.long.word 0x00 0.--11. 1. " CALR[11:0] ,Calibration Bits" sif (cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")) rgroup.long 0x88++0x3 line.long 0x0 "SMSTATE,State Macine Current State" bitfld.long 0x00 0.--3. " SMSTATE[3:0] ,ADC State Macine Current State" "Idle,Conv_EV,Conv_SW1,Conv_SW2,Conv_Cal,Start_EV,Start_SW1,Start_SW2,Start_Cal,Wait_EV,Wait_SW1,Wait_SW2,Wait_CAL,?..." endif width 10. rgroup.long 0x8C++0x3 line.long 0x0 "LASTCONV,Last Conversion" bitfld.long 0x00 31. " IN[31] ,Digital input pin 31" "Low,High" bitfld.long 0x00 30. " IN[30] ,Digital input pin 30" "Low,High" bitfld.long 0x00 29. " IN[29] ,Digital input pin 29" "Low,High" bitfld.long 0x00 28. " IN[28] ,Digital input pin 28" "Low,High" textline " " bitfld.long 0x00 27. " IN[27] ,Digital input pin 27" "Low,High" bitfld.long 0x00 26. " IN[26] ,Digital input pin 26" "Low,High" bitfld.long 0x00 25. " IN[25] ,Digital input pin 25" "Low,High" bitfld.long 0x00 24. " IN[24] ,Digital input pin 24" "Low,High" textline " " bitfld.long 0x00 23. " IN[23] ,Digital input pin 23" "Low,High" bitfld.long 0x00 22. " IN[22] ,Digital input pin 22" "Low,High" bitfld.long 0x00 21. " IN[21] ,Digital input pin 21" "Low,High" bitfld.long 0x00 20. " IN[20] ,Digital input pin 20" "Low,High" textline " " bitfld.long 0x00 19. " IN[19] ,Digital input pin 19" "Low,High" bitfld.long 0x00 18. " IN[18] ,Digital input pin 18" "Low,High" bitfld.long 0x00 17. " IN[17] ,Digital input pin 17" "Low,High" bitfld.long 0x00 16. " IN[16] ,Digital input pin 16" "Low,High" textline " " bitfld.long 0x00 15. " IN[15] ,Digital input pin 15" "Low,High" bitfld.long 0x00 14. " IN[14] ,Digital input pin 14" "Low,High" bitfld.long 0x00 13. " IN[13] ,Digital input pin 13" "Low,High" bitfld.long 0x00 12. " IN[12] ,Digital input pin 12" "Low,High" textline " " bitfld.long 0x00 11. " IN[11] ,Digital input pin 11" "Low,High" bitfld.long 0x00 10. " IN[10] ,Digital input pin 10" "Low,High" bitfld.long 0x00 9. " IN[9] ,Digital input pin 9" "Low,High" bitfld.long 0x00 8. " IN[8] ,Digital input pin 8" "Low,High" textline " " bitfld.long 0x00 7. " IN[7] ,Digital input pin 7" "Low,High" bitfld.long 0x00 6. " IN[6] ,Digital input pin 6" "Low,High" bitfld.long 0x00 5. " IN[5] ,Digital input pin 5" "Low,High" bitfld.long 0x00 4. " IN[4] ,Digital input pin 4" "Low,High" textline " " bitfld.long 0x00 3. " IN[3] ,Digital input pin 3" "Low,High" bitfld.long 0x00 2. " IN[2] ,Digital input pin 2" "Low,High" bitfld.long 0x00 1. " IN[1] ,Digital input pin 1" "Low,High" bitfld.long 0x00 0. " IN[0] ,Digital input pin 0" "Low,High" tree "ADC Buffer Control Registers" width 13. hgroup.long 0x90++0x3 hide.long 0x0 "EVBUFFER0,Event Group Buffer 0" in hgroup.long 0x94++0x3 hide.long 0x0 "EVBUFFER1,Event Group Buffer 1" in hgroup.long 0x98++0x3 hide.long 0x0 "EVBUFFER2,Event Group Buffer 2" in hgroup.long 0x9C++0x3 hide.long 0x0 "EVBUFFER3,Event Group Buffer 3" in hgroup.long 0xA0++0x3 hide.long 0x0 "EVBUFFER4,Event Group Buffer 4" in hgroup.long 0xA4++0x3 hide.long 0x0 "EVBUFFER5,Event Group Buffer 5" in hgroup.long 0xA8++0x3 hide.long 0x0 "EVBUFFER6,Event Group Buffer 6" in hgroup.long 0xAC++0x3 hide.long 0x0 "EVBUFFER7,Event Group Buffer 7" in hgroup.long 0xB0++0x3 hide.long 0x0 "G1BUFFER0,Group 1 Buffer 0" in hgroup.long 0xB4++0x3 hide.long 0x0 "G1BUFFER1,Group 1 Buffer 1" in hgroup.long 0xB8++0x3 hide.long 0x0 "G1BUFFER2,Group 1 Buffer 2" in hgroup.long 0xBC++0x3 hide.long 0x0 "G1BUFFER3,Group 1 Buffer 3" in hgroup.long 0xC0++0x3 hide.long 0x0 "G1BUFFER4,Group 1 Buffer 4" in hgroup.long 0xC4++0x3 hide.long 0x0 "G1BUFFER5,Group 1 Buffer 5" in hgroup.long 0xC8++0x3 hide.long 0x0 "G1BUFFER6,Group 1 Buffer 6" in hgroup.long 0xCC++0x3 hide.long 0x0 "G1BUFFER7,Group 1 Buffer 7" in hgroup.long 0xD0++0x3 hide.long 0x0 "G2BUFFER0,Group 2 Buffer 0" in hgroup.long 0xD4++0x3 hide.long 0x0 "G2BUFFER1,Group 2 Buffer 1" in hgroup.long 0xD8++0x3 hide.long 0x0 "G2BUFFER2,Group 2 Buffer 2" in hgroup.long 0xDC++0x3 hide.long 0x0 "G2BUFFER3,Group 2 Buffer 3" in hgroup.long 0xE0++0x3 hide.long 0x0 "G2BUFFER4,Group 2 Buffer 4" in hgroup.long 0xE4++0x3 hide.long 0x0 "G2BUFFER5,Group 2 Buffer 5" in hgroup.long 0xE8++0x3 hide.long 0x0 "G2BUFFER6,Group 2 Buffer 6" in hgroup.long 0xEC++0x3 hide.long 0x0 "G2BUFFER7,Group 2 Buffer 7" in if (((d.l((ad:0xFFF7C000+0x10)))&0x300)==0x100) group.long 0xF0++0x3 line.long 0x0 "EVEMUBUFFER,Event Group EMU Buffer" bitfld.long 0x00 31. " EV_EMPTY ,Event Group FIFO Empty" "Not empty,Empty" bitfld.long 0x00 16.--20. " EVCHID[4:0] ,EVCHID" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31" hexmask.long.word 0x00 0.--9. 1. " EVDR[9:0] ,Event Group Digital Result" elif (((d.l((ad:0xFFF7C000+0x10)))&0x300)==0x200) group.long 0xF0++0x3 line.long 0x0 "EVEMUBUFFER,Event Group EMU Buffer" bitfld.long 0x00 31. " EV_EMPTY ,Event Group FIFO Empty" "Not empty,Empty" bitfld.long 0x00 16.--20. " EVCHID[4:0] ,EVCHID" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31" hexmask.long.byte 0x00 0.--7. 1. " EVDR[7:0] ,Event Group Digital Result" elif (((d.l((ad:0xFFF7C000+0x10)))&0x300)==0x300) group.long 0xF0++0x3 line.long 0x0 "EVEMUBUFFER,Event Group EMU Buffer" bitfld.long 0x00 31. " EV_EMPTY ,Event Group FIFO Empty" "Not empty,Empty" bitfld.long 0x00 16.--20. " EVCHID[4:0] ,EVCHID" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31" hexmask.long.word 0x00 0.--11. 1. " EVDR[11:0] ,Event Group Digital Result" else group.long 0xF0++0x3 line.long 0x0 "EVEMUBUFFER,Event Group EMU Buffer" bitfld.long 0x00 31. " EV_EMPTY ,Event Group FIFO Empty" "Not empty,Empty" bitfld.long 0x00 16.--20. " EVCHID[4:0] ,EVCHID" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31" endif if (((d.l((ad:0xFFF7C000+0x14)))&0x300)==0x100) group.long 0xF4++0x3 line.long 0x0 "G1BUFFER,Group 1 EMU Buffer" bitfld.long 0x00 31. " G1_EMPTY ,Group 1 FIFO Empty" "Not empty,Empty" bitfld.long 0x00 16.--20. " G1CHID[4:0] ,G1CHID" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31" hexmask.long.word 0x00 0.--9. 1. " G1DR[9:0] ,Group 1 Digital Result" elif (((d.l((ad:0xFFF7C000+0x14)))&0x300)==0x200) group.long 0xF4++0x3 line.long 0x0 "G1BUFFER,Group 1 EMU Buffer" bitfld.long 0x00 31. " G1_EMPTY ,Group 1 FIFO Empty" "Not empty,Empty" bitfld.long 0x00 16.--20. " G1CHID[4:0] ,G1CHID" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31" hexmask.long.byte 0x00 0.--7. 1. " G1DR[7:0] ,Group 1 Digital Result" elif (((d.l((ad:0xFFF7C000+0x14)))&0x300)==0x300) group.long 0xF4++0x3 line.long 0x0 "G1BUFFER,Group 1 EMU Buffer" bitfld.long 0x00 31. " G1_EMPTY ,Group 1 FIFO Empty" "Not empty,Empty" bitfld.long 0x00 16.--20. " G1CHID[4:0] ,G1CHID" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31" hexmask.long.word 0x00 0.--11. 1. " G1DR[11:0] ,Group 1 Digital Result" else group.long 0xF4++0x3 line.long 0x0 "G1BUFFER,Group 1 EMU Buffer" bitfld.long 0x00 31. " G1_EMPTY ,Group 1 FIFO Empty" "Not empty,Empty" bitfld.long 0x00 16.--20. " G1CHID[4:0] ,G1CHID" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31" endif if (((d.l((ad:0xFFF7C000+0x18)))&0x300)==0x100) group.long 0xF8++0x3 line.long 0x0 "G2BUFFER,Group 2 EMU Buffer" bitfld.long 0x00 31. " G2_EMPTY ,Group 2 FIFO Empty" "Not empty,Empty" bitfld.long 0x00 16.--20. " G2CHID[4:0] ,G2CHID" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31" hexmask.long.word 0x00 0.--9. 1. " G2DR[9:0] ,Group 2 Digital Result" elif (((d.l((ad:0xFFF7C000+0x18)))&0x300)==0x200) group.long 0xF8++0x3 line.long 0x0 "G2BUFFER,Group 2 EMU Buffer" bitfld.long 0x00 31. " G2_EMPTY ,Group 2 FIFO Empty" "Not empty,Empty" bitfld.long 0x00 16.--20. " G2CHID[4:0] ,G2CHID" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31" hexmask.long.byte 0x00 0.--7. 1. " G2DR[7:0] ,Group 2 Digital Result" elif (((d.l((ad:0xFFF7C000+0x18)))&0x300)==0x300) group.long 0xF8++0x3 line.long 0x0 "G2BUFFER,Group 2 EMU Buffer" bitfld.long 0x00 31. " G2_EMPTY ,Group 2 FIFO Empty" "Not empty,Empty" bitfld.long 0x00 16.--20. " G2CHID[4:0] ,G2CHID" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31" hexmask.long.word 0x00 0.--11. 1. " G2DR[11:0] ,Group 2 Digital Result" else group.long 0xF8++0x3 line.long 0x0 "G2BUFFER,Group 2 EMU Buffer" bitfld.long 0x00 31. " G2_EMPTY ,Group 2 FIFO Empty" "Not empty,Empty" bitfld.long 0x00 16.--20. " G2CHID[4:0] ,G2CHID" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31" endif tree.end width 9. tree "ADC ADEVT Pin Control Registers" group.long 0xFC++0x3 line.long 0x0 "EVTDIR,Event Group pin direction selection" bitfld.long 0x00 0. " EVT_DIR ,ADEVT Pin Direction Selection" "Output disabled,Output enabled" if (((d.l((ad:0xFFF7C000+0xfc)))&0x01)==0x01) group.long 0x100++0x3 line.long 0x0 "EVTOUT,Event Group pin data output" bitfld.long 0x00 0. " EVT_OUT ,ADEVT Pin Data Output" "Low,High" else hgroup.long 0x100++0x3 hide.long 0x0 "EVTOUT,Event Group pin data output" endif group.long 0x104++0x3 line.long 0x0 "EVTIN,Event Group pin input value" bitfld.long 0x00 0. " EVT_IN ,ADEVT Pin Input Value" "Low,High" group.long 0x108++0x3 line.long 0x0 "EVTSET,Event Group pin set" bitfld.long 0x00 0. " ADEVT_SET ,ADEVT Pin Set" "Low/No effect,High/Set" group.long 0x10C++0x3 line.long 0x0 "EVTCLR,Event Group pin clear" eventfld.long 0x00 0. " ADEVT_CLR ,ADEVT Pin Clear" "Low/No effect,High/CLear" if ((((d.l((ad:0xFFF7C000+0xfc)))&0x01)==0x01)&&(((d.l((ad:0xFFF7C000+0x0100)))&0x01)==0x01)) group.long 0x110++0x3 line.long 0x0 "EVTPDR,Event Group pin open-drain enable" bitfld.long 0x00 0. " ADEVT_PDR ,ADEVT Pin Open-Drain Enable" "High,Tri-state" else hgroup.long 0x110++0x3 hide.long 0x0 "EVTPDR,Event Group pin open-drain enable" endif if (((d.l((ad:0xFFF7C000+0xfc)))&0x01)==0x00) group.long 0x114++0x3 line.long 0x0 "EVTPDIS,Event Group pin pull control enable" bitfld.long 0x00 0. " ADEVT_PDIS ,ADEVT Pin Pull Control Enable" "Enabled,Disabled" else hgroup.long 0x114++0x3 hide.long 0x0 "EVTPDIS,Event Group pin pull control enable" endif group.long 0x118++0x3 line.long 0x0 "EVTPSEL,Event Group pull select" bitfld.long 0x00 0. " ADEVT_PSEL ,ADEVT Pull Select" "Pull-down,Pull-up" tree.end width 13. tree "ADC Sampling Capacitor Discharge Mode Control Registers" group.long 0x11C++0x3 line.long 0x0 "EVSAMPDISEN,Event Group Sampling Capacitor Discharge Mode" hexmask.long.byte 0x00 8.--15. 1. " EV_SAMP_DIS_CYC[7:0] ,ADC Sampling Capacitor is Dicharged Cycles" bitfld.long 0x00 0. " EV_SAMP_DIS_EN ,Sampling Capacitor Discharge Mode" "Disabled,Enabled" group.long 0x120++0x3 line.long 0x0 "G1SAMPDISEN,Group 1 Sampling Capacitor Discharge Mode" hexmask.long.byte 0x00 8.--15. 1. " G1_SAMP_DIS_CYC[7:0] ,ADC Sampling Capacitor is Dicharged Cycles" bitfld.long 0x00 0. " G1_SAMP_DIS_EN ,Sampling Capacitor Discharge Mode" "Disabled,Enabled" group.long 0x124++0x3 line.long 0x0 "G2SAMPDISEN,Group 2 Sampling Capacitor Discharge Mode" hexmask.long.byte 0x00 8.--15. 1. " G2_SAMP_DIS_CYC[7:0] ,ADC Sampling Capacitor is Dicharged Cycles" bitfld.long 0x00 0. " G2_SAMP_DIS_EN ,Sampling Capacitor Discharge Mode" "Disabled,Enabled" tree.end width tree "ADC Interrupt Control Registers" width 17. group.long 0x128++0x3 line.long 0x0 "MAGINTCR1,Magnitude Interrupt Control Register 1" hexmask.long.word 0x00 16.--27. 1. " MAG_THRESHOLD1 ,Magnitude Threshold 1" textline " " bitfld.long 0x00 15. " CHN/THR_COMP1 ,CHN/THR COMP1" "MAG THRESHOLD1,MAG CHID1" bitfld.long 0x00 14. " CMP_GE/LT1 ,CMP GE/LT1 Interrupt Result" "Lower,Greater" textline " " bitfld.long 0x00 8.--12. " COMP_CHID1 ,COMP CHID1 [4:0]" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31" bitfld.long 0x00 0.--4. " MAG_CHID1 ,MAG CHID1 [4:0]" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31" width 17. group.long 0x12C++0x3 line.long 0x0 "MAGINT1MASK,Magnitude Interrupt Mask 1" bitfld.long 0x00 11. " MAG_INT1_MASK[11] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 11" "Not masked,Masked" bitfld.long 0x00 10. " MAG_INT1_MASK[10] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 10" "Not masked,Masked" textline " " bitfld.long 0x00 9. " MAG_INT1_MASK[9] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 9" "Not masked,Masked" bitfld.long 0x00 8. " MAG_INT1_MASK[8] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " MAG_INT1_MASK[7] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 7" "Not masked,Masked" bitfld.long 0x00 6. " MAG_INT1_MASK[6] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 6" "Not masked,Masked" textline " " bitfld.long 0x00 5. " MAG_INT1_MASK[5] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 5" "Not masked,Masked" bitfld.long 0x00 4. " MAG_INT1_MASK[4] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " MAG_INT1_MASK[3] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 3" "Not masked,Masked" bitfld.long 0x00 2. " MAG_INT1_MASK[2] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 2" "Not masked,Masked" textline " " bitfld.long 0x00 1. " MAG_INT1_MASK[1] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 1" "Not masked,Masked" bitfld.long 0x00 0. " MAG_INT1_MASK[0] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 0" "Not masked,Masked" width 17. group.long 0x130++0x3 line.long 0x0 "MAGINTCR2,Magnitude Interrupt Control Register 2" hexmask.long.word 0x00 16.--27. 1. " MAG_THRESHOLD2 ,Magnitude Threshold 2" textline " " bitfld.long 0x00 15. " CHN/THR_COMP2 ,CHN/THR COMP2" "MAG THRESHOLD2,MAG CHID2" bitfld.long 0x00 14. " CMP_GE/LT2 ,CMP GE/LT2 Interrupt Result" "Lower,Greater" textline " " bitfld.long 0x00 8.--12. " COMP_CHID2 ,COMP CHID2 [4:0]" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31" bitfld.long 0x00 0.--4. " MAG_CHID2 ,MAG CHID2 [4:0]" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31" width 17. group.long 0x134++0x3 line.long 0x0 "MAGINT2MASK,Magnitude Interrupt Mask 2" bitfld.long 0x00 11. " MAG_INT2_MASK[11] ,Comparison for the Magnitude Threshold Interrupt 2 Mask 11" "Not masked,Masked" bitfld.long 0x00 10. " MAG_INT2_MASK[10] ,Comparison for the Magnitude Threshold Interrupt 2 Mask 10" "Not masked,Masked" textline " " bitfld.long 0x00 9. " MAG_INT2_MASK[9] ,Comparison for the Magnitude Threshold Interrupt 2 Mask 9" "Not masked,Masked" bitfld.long 0x00 8. " MAG_INT2_MASK[8] ,Comparison for the Magnitude Threshold Interrupt 2 Mask 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " MAG_INT2_MASK[7] ,Comparison for the Magnitude Threshold Interrupt 2 Mask 7" "Not masked,Masked" bitfld.long 0x00 6. " MAG_INT2_MASK[6] ,Comparison for the Magnitude Threshold Interrupt 2 Mask 6" "Not masked,Masked" textline " " bitfld.long 0x00 5. " MAG_INT2_MASK[5] ,Comparison for the Magnitude Threshold Interrupt 2 Mask 5" "Not masked,Masked" bitfld.long 0x00 4. " MAG_INT2_MASK[4] ,Comparison for the Magnitude Threshold Interrupt 2 Mask 4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " MAG_INT2_MASK[3] ,Comparison for the Magnitude Threshold Interrupt 2 Mask 3" "Not masked,Masked" bitfld.long 0x00 2. " MAG_INT2_MASK[2] ,Comparison for the Magnitude Threshold Interrupt 2 Mask 2" "Not masked,Masked" textline " " bitfld.long 0x00 1. " MAG_INT2_MASK[1] ,Comparison for the Magnitude Threshold Interrupt 2 Mask 1" "Not masked,Masked" bitfld.long 0x00 0. " MAG_INT2_MASK[0] ,Comparison for the Magnitude Threshold Interrupt 2 Mask 0" "Not masked,Masked" width 17. group.long 0x138++0x3 line.long 0x0 "MAGINTCR3,Magnitude Interrupt Control Register 3" hexmask.long.word 0x00 16.--27. 1. " MAG_THRESHOLD3 ,Magnitude Threshold 3" textline " " bitfld.long 0x00 15. " CHN/THR_COMP3 ,CHN/THR COMP3" "MAG THRESHOLD3,MAG CHID3" bitfld.long 0x00 14. " CMP_GE/LT3 ,CMP GE/LT3 Interrupt Result" "Lower,Greater" textline " " bitfld.long 0x00 8.--12. " COMP_CHID3 ,COMP CHID3 [4:0]" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31" bitfld.long 0x00 0.--4. " MAG_CHID3 ,MAG CHID3 [4:0]" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31" width 17. group.long 0x13C++0x3 line.long 0x0 "MAGINT3MASK,Magnitude Interrupt Mask 3" bitfld.long 0x00 11. " MAG_INT3_MASK[11] ,Comparison for the Magnitude Threshold Interrupt 3 Mask 11" "Not masked,Masked" bitfld.long 0x00 10. " MAG_INT3_MASK[10] ,Comparison for the Magnitude Threshold Interrupt 3 Mask 10" "Not masked,Masked" textline " " bitfld.long 0x00 9. " MAG_INT3_MASK[9] ,Comparison for the Magnitude Threshold Interrupt 3 Mask 9" "Not masked,Masked" bitfld.long 0x00 8. " MAG_INT3_MASK[8] ,Comparison for the Magnitude Threshold Interrupt 3 Mask 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " MAG_INT3_MASK[7] ,Comparison for the Magnitude Threshold Interrupt 3 Mask 7" "Not masked,Masked" bitfld.long 0x00 6. " MAG_INT3_MASK[6] ,Comparison for the Magnitude Threshold Interrupt 3 Mask 6" "Not masked,Masked" textline " " bitfld.long 0x00 5. " MAG_INT3_MASK[5] ,Comparison for the Magnitude Threshold Interrupt 3 Mask 5" "Not masked,Masked" bitfld.long 0x00 4. " MAG_INT3_MASK[4] ,Comparison for the Magnitude Threshold Interrupt 3 Mask 4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " MAG_INT3_MASK[3] ,Comparison for the Magnitude Threshold Interrupt 3 Mask 3" "Not masked,Masked" bitfld.long 0x00 2. " MAG_INT3_MASK[2] ,Comparison for the Magnitude Threshold Interrupt 3 Mask 2" "Not masked,Masked" textline " " bitfld.long 0x00 1. " MAG_INT3_MASK[1] ,Comparison for the Magnitude Threshold Interrupt 3 Mask 1" "Not masked,Masked" bitfld.long 0x00 0. " MAG_INT3_MASK[0] ,Comparison for the Magnitude Threshold Interrupt 3 Mask 0" "Not masked,Masked" width 17. group.long 0x140++0x3 line.long 0x0 "MAGINTCR4,Magnitude Interrupt Control Register 4" hexmask.long.word 0x00 16.--27. 1. " MAG_THRESHOLD4 ,Magnitude Threshold 4" textline " " bitfld.long 0x00 15. " CHN/THR_COMP4 ,CHN/THR COMP4" "MAG THRESHOLD4,MAG CHID4" bitfld.long 0x00 14. " CMP_GE/LT4 ,CMP GE/LT4 Interrupt Result" "Lower,Greater" textline " " bitfld.long 0x00 8.--12. " COMP_CHID4 ,COMP CHID4 [4:0]" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31" bitfld.long 0x00 0.--4. " MAG_CHID4 ,MAG CHID4 [4:0]" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31" width 17. group.long 0x144++0x3 line.long 0x0 "MAGINT4MASK,Magnitude Interrupt Mask 4" bitfld.long 0x00 11. " MAG_INT4_MASK[11] ,Comparison for the Magnitude Threshold Interrupt 4 Mask 11" "Not masked,Masked" bitfld.long 0x00 10. " MAG_INT4_MASK[10] ,Comparison for the Magnitude Threshold Interrupt 4 Mask 10" "Not masked,Masked" textline " " bitfld.long 0x00 9. " MAG_INT4_MASK[9] ,Comparison for the Magnitude Threshold Interrupt 4 Mask 9" "Not masked,Masked" bitfld.long 0x00 8. " MAG_INT4_MASK[8] ,Comparison for the Magnitude Threshold Interrupt 4 Mask 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " MAG_INT4_MASK[7] ,Comparison for the Magnitude Threshold Interrupt 4 Mask 7" "Not masked,Masked" bitfld.long 0x00 6. " MAG_INT4_MASK[6] ,Comparison for the Magnitude Threshold Interrupt 4 Mask 6" "Not masked,Masked" textline " " bitfld.long 0x00 5. " MAG_INT4_MASK[5] ,Comparison for the Magnitude Threshold Interrupt 4 Mask 5" "Not masked,Masked" bitfld.long 0x00 4. " MAG_INT4_MASK[4] ,Comparison for the Magnitude Threshold Interrupt 4 Mask 4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " MAG_INT4_MASK[3] ,Comparison for the Magnitude Threshold Interrupt 4 Mask 3" "Not masked,Masked" bitfld.long 0x00 2. " MAG_INT4_MASK[2] ,Comparison for the Magnitude Threshold Interrupt 4 Mask 2" "Not masked,Masked" textline " " bitfld.long 0x00 1. " MAG_INT4_MASK[1] ,Comparison for the Magnitude Threshold Interrupt 4 Mask 1" "Not masked,Masked" bitfld.long 0x00 0. " MAG_INT4_MASK[0] ,Comparison for the Magnitude Threshold Interrupt 4 Mask 0" "Not masked,Masked" width 17. group.long 0x148++0x3 line.long 0x0 "MAGINTCR5,Magnitude Interrupt Control Register 5" hexmask.long.word 0x00 16.--27. 1. " MAG_THRESHOLD5 ,Magnitude Threshold 5" textline " " bitfld.long 0x00 15. " CHN/THR_COMP5 ,CHN/THR COMP5" "MAG THRESHOLD5,MAG CHID5" bitfld.long 0x00 14. " CMP_GE/LT5 ,CMP GE/LT5 Interrupt Result" "Lower,Greater" textline " " bitfld.long 0x00 8.--12. " COMP_CHID5 ,COMP CHID5 [4:0]" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31" bitfld.long 0x00 0.--4. " MAG_CHID5 ,MAG CHID5 [4:0]" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31" width 17. group.long 0x14C++0x3 line.long 0x0 "MAGINT5MASK,Magnitude Interrupt Mask 5" bitfld.long 0x00 11. " MAG_INT5_MASK[11] ,Comparison for the Magnitude Threshold Interrupt 5 Mask 11" "Not masked,Masked" bitfld.long 0x00 10. " MAG_INT5_MASK[10] ,Comparison for the Magnitude Threshold Interrupt 5 Mask 10" "Not masked,Masked" textline " " bitfld.long 0x00 9. " MAG_INT5_MASK[9] ,Comparison for the Magnitude Threshold Interrupt 5 Mask 9" "Not masked,Masked" bitfld.long 0x00 8. " MAG_INT5_MASK[8] ,Comparison for the Magnitude Threshold Interrupt 5 Mask 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " MAG_INT5_MASK[7] ,Comparison for the Magnitude Threshold Interrupt 5 Mask 7" "Not masked,Masked" bitfld.long 0x00 6. " MAG_INT5_MASK[6] ,Comparison for the Magnitude Threshold Interrupt 5 Mask 6" "Not masked,Masked" textline " " bitfld.long 0x00 5. " MAG_INT5_MASK[5] ,Comparison for the Magnitude Threshold Interrupt 5 Mask 5" "Not masked,Masked" bitfld.long 0x00 4. " MAG_INT5_MASK[4] ,Comparison for the Magnitude Threshold Interrupt 5 Mask 4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " MAG_INT5_MASK[3] ,Comparison for the Magnitude Threshold Interrupt 5 Mask 3" "Not masked,Masked" bitfld.long 0x00 2. " MAG_INT5_MASK[2] ,Comparison for the Magnitude Threshold Interrupt 5 Mask 2" "Not masked,Masked" textline " " bitfld.long 0x00 1. " MAG_INT5_MASK[1] ,Comparison for the Magnitude Threshold Interrupt 5 Mask 1" "Not masked,Masked" bitfld.long 0x00 0. " MAG_INT5_MASK[0] ,Comparison for the Magnitude Threshold Interrupt 5 Mask 0" "Not masked,Masked" width 17. group.long 0x150++0x3 line.long 0x0 "MAGINTCR6,Magnitude Interrupt Control Register 6" hexmask.long.word 0x00 16.--27. 1. " MAG_THRESHOLD6 ,Magnitude Threshold 6" textline " " bitfld.long 0x00 15. " CHN/THR_COMP6 ,CHN/THR COMP6" "MAG THRESHOLD6,MAG CHID6" bitfld.long 0x00 14. " CMP_GE/LT6 ,CMP GE/LT6 Interrupt Result" "Lower,Greater" textline " " bitfld.long 0x00 8.--12. " COMP_CHID6 ,COMP CHID6 [4:0]" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31" bitfld.long 0x00 0.--4. " MAG_CHID6 ,MAG CHID6 [4:0]" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31" width 17. group.long 0x154++0x3 line.long 0x0 "MAGINT6MASK,Magnitude Interrupt Mask 6" bitfld.long 0x00 11. " MAG_INT6_MASK[11] ,Comparison for the Magnitude Threshold Interrupt 6 Mask 11" "Not masked,Masked" bitfld.long 0x00 10. " MAG_INT6_MASK[10] ,Comparison for the Magnitude Threshold Interrupt 6 Mask 10" "Not masked,Masked" textline " " bitfld.long 0x00 9. " MAG_INT6_MASK[9] ,Comparison for the Magnitude Threshold Interrupt 6 Mask 9" "Not masked,Masked" bitfld.long 0x00 8. " MAG_INT6_MASK[8] ,Comparison for the Magnitude Threshold Interrupt 6 Mask 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " MAG_INT6_MASK[7] ,Comparison for the Magnitude Threshold Interrupt 6 Mask 7" "Not masked,Masked" bitfld.long 0x00 6. " MAG_INT6_MASK[6] ,Comparison for the Magnitude Threshold Interrupt 6 Mask 6" "Not masked,Masked" textline " " bitfld.long 0x00 5. " MAG_INT6_MASK[5] ,Comparison for the Magnitude Threshold Interrupt 6 Mask 5" "Not masked,Masked" bitfld.long 0x00 4. " MAG_INT6_MASK[4] ,Comparison for the Magnitude Threshold Interrupt 6 Mask 4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " MAG_INT6_MASK[3] ,Comparison for the Magnitude Threshold Interrupt 6 Mask 3" "Not masked,Masked" bitfld.long 0x00 2. " MAG_INT6_MASK[2] ,Comparison for the Magnitude Threshold Interrupt 6 Mask 2" "Not masked,Masked" textline " " bitfld.long 0x00 1. " MAG_INT6_MASK[1] ,Comparison for the Magnitude Threshold Interrupt 6 Mask 1" "Not masked,Masked" bitfld.long 0x00 0. " MAG_INT6_MASK[0] ,Comparison for the Magnitude Threshold Interrupt 6 Mask 0" "Not masked,Masked" width 17. group.long 0x160++0x3 line.long 0x0 "MAGTHRINTFLG,Magnitude Threshold Interrupt Flag" sif (cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")) setclrfld.long 0x00 5. -0x08 5. -0x04 5. " MAG_THR_INT5_set/clr ,Magnitude Threshold Interrupt Flag Bit[5]" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 4. -0x08 4. -0x04 4. " MAG_THR_INT4_set/clr ,Magnitude Threshold Interrupt Flag Bit[4]" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 3. -0x08 3. -0x04 3. " MAG_THR_INT3_set/clr ,Magnitude Threshold Interrupt Flag Bit[3]" "No interrupt,Interrupt" textline " " endif setclrfld.long 0x00 2. -0x08 2. -0x04 2. " MAG_THR_INT2_set/clr ,Magnitude Threshold Interrupt Flag Bit[2]" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 1. -0x08 1. -0x04 1. " MAG_THR_INT1_set/clr ,Magnitude Threshold Interrupt Flag Bit[1]" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 0. -0x08 0. -0x04 0. " MAG_THR_INT0_set/clr ,Magnitude Threshold Interrupt Flag Bit[0]" "No interrupt,Interrupt" group.long 0x164++0x3 line.long 0x0 "MAGTHRINTOFFSET,Magnitude Threshold Interrupt Offset" bitfld.long 0x00 0.--2. " INT_OFF[2:0] ,Magnitude Threshold Interrupt Offset" "No interrupt,Interrupt 1,Interrupt 2,Interrupt 3,Interrupt 4,Interrupt 5,Interrupt 6,Invalid" tree.end width 15. tree "ADC RAM Control Registers" group.long 0x168++0x3 line.long 0x0 "EVFIFORESETCR,Event Group FIFO Reset" bitfld.long 0x00 0. " EV_FIFO_RESET ,Reset the ADC Event Group FIFO" "No reset,Reset" group.long 0x16C++0x3 line.long 0x0 "G1FIFORESETCR,Group 2 FIFO Reset" bitfld.long 0x00 0. " G1_FIFO_RESET ,Reset the ADC Group 1 FIFO" "No reset,Reset" group.long 0x170++0x3 line.long 0x0 "G2FIFORESETCR,Group 2 FIFO Reset" bitfld.long 0x00 0. " G2_FIFO_RESET ,Reset the ADC Group 2 FIFO" "No reset,Reset" rgroup.long 0x174++0x3 line.long 0x0 "EVRAMADDR,Event Group ADC RAM Pointer" hexmask.long.word 0x00 0.--8. 1. " EV_RAM_ADDR ,Event Group ADC RAM Pointer" rgroup.long 0x178++0x3 line.long 0x0 "G1RAMADDR,Group 1 ADC RAM Pointer" hexmask.long.word 0x00 0.--8. 1. " G1_RAM_ADDR ,Group 1 ADC RAM Pointer" rgroup.long 0x17C++0x3 line.long 0x0 "G2RAMADDR,Group 2 ADC RAM Pointer" hexmask.long.word 0x00 0.--8. 1. " G2_RAM_ADDR ,Group 2 ADC RAM Pointer" tree.end tree "ADC Parity Control Registers" width 9. group.long 0x180++0x3 line.long 0x0 "PARCR,Parity Control Register" bitfld.long 0x00 8. " TEST ,Parity Bits Map" "Not mapped,Mapped" bitfld.long 0x00 0.--3. " PARITY_ENA[3:0] ,Enable/Disable Parity Checking" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" rgroup.long 0x184++0x3 line.long 0x0 "PARADDR,Parity Address" hexmask.long.word 0x00 2.--11. 0x4 " Error_Address ,ERROR ADDRESS" tree.end width 0xb tree.end tree "MIBADC2" base ad:0xFFF7C200 width 10. group.long 0x00++0x3 line.long 0x0 "RSTCR,Reset Control Register" bitfld.long 0x00 0. " Reset ,ADC Reset" "No reset,Reset" group.long 0x04++0x3 sif (cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")) line.long 0x0 "PWDNCR,Powerdown Control Register" else line.long 0x0 "ADOPMODECR,Operating Mode Control Register" bitfld.long 0x00 24. " COS ,Emulation Operation" "Halts,Continues" bitfld.long 0x00 16. " RAM_TEST_EN ,Enable ADC results" "Disabled,Enabled" bitfld.long 0x00 0. " ADC_EN ,ADC Enable" "Disabled,Enabled" endif group.long 0x08++0x3 line.long 0x0 "CLOCKCR,Clock Prescaler" bitfld.long 0x00 0.--4. " PS[4:0] ,ADC Clock Prescaler" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles" width 10. if (((d.l((ad:0xFFF7C200+0x0c)))&0x01000201)==0x00000001) group.long (0x0c)++0x03 line.long 0x00 "CALCR,Calibration Conversion Register" bitfld.long 0x00 24. " SELF_TEST ,Self-Test Enable" "Disabled,Enabled" bitfld.long 0x00 16. " CAL_ST ,Calibration Conversion Start" "No effect/completed,Started" textline " " bitfld.long 0x00 9. " BRIDGE_EN ,Bridge Enable" "Midpoint,Full" bitfld.long 0x00 0. " CAL_EN ,Calibration Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " HILO ,Test and Reference Source Selection" "(AD_REFHI*R1+AD_REFLO*R2)/(R1+R2),(AD_REFLO*R1+AD_REFHI*R2)/(R1+R2)" elif (((d.l((ad:0xFFF7C200+0x0c)))&0x01000201)==0x01000000) group.long (0x0c)++0x03 line.long 0x00 "CALCR,Calibration Conversion Register" bitfld.long 0x00 24. " SELF_TEST ,Self-Test Enable" "Disabled,Enabled" bitfld.long 0x00 16. " CAL_ST ,Calibration Conversion Start" "No effect/completed,Started" textline " " bitfld.long 0x00 9. " BRIDGE_EN ,Bridge Enable" "Midpoint,Full" bitfld.long 0x00 0. " CAL_EN ,Calibration Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " HILO ,Test and Reference Source Selection" "(AD_REFLO via R1)||(R2 to Vin),(AD_REFHI via R1)||(R2 to Vin)" elif (((d.l((ad:0xFFF7C200+0x0c)))&0x01000201)==0x00000201) group.long (0x0c)++0x03 line.long 0x00 "CALCR,Calibration Conversion Register" bitfld.long 0x00 24. " SELF_TEST ,Self-Test Enable" "Disabled,Enabled" bitfld.long 0x00 16. " CAL_ST ,Calibration Conversion Start" "No effect/completed,Started" textline " " bitfld.long 0x00 9. " BRIDGE_EN ,Bridge Enable" "Midpoint,Full" bitfld.long 0x00 0. " CAL_EN ,Calibration Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " HILO ,Test and Reference Source Selection" "AD_REFLO,AD_REFHI" elif (((d.l((ad:0xFFF7C200+0x0c)))&0x01000201)==0x01000200) group.long (0x0c)++0x03 line.long 0x00 "CALCR,Calibration Conversion Register" bitfld.long 0x00 24. " SELF_TEST ,Self-Test Enable" "Disabled,Enabled" bitfld.long 0x00 16. " CAL_ST ,Calibration Conversion Start" "No effect/completed,Started" textline " " bitfld.long 0x00 9. " BRIDGE_EN ,Bridge Enable" "Midpoint,Full" bitfld.long 0x00 0. " CAL_EN ,Calibration Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " HILO ,Test and Reference Source Selection" "(AD_REFLO via R1)||(R2 to Vin),(AD_REFHI via R1)||(R2 to Vin)" else group.long (0x0c)++0x03 line.long 0x00 "CALCR,Calibration Conversion Register" bitfld.long 0x00 24. " SELF_TEST ,Self-Test Enable" "Disabled,Enabled" bitfld.long 0x00 16. " CAL_ST ,Calibration Conversion Start" "No effect/completed,Started" textline " " bitfld.long 0x00 9. " BRIDGE_EN ,Bridge Enable" "Midpoint,Full" bitfld.long 0x00 0. " CAL_EN ,Calibration Enable" "Disabled,Enabled" endif width 10. group.long 0x10++0x3 line.long 0x0 "EVMODECR,EV MODE Control Register" bitfld.long 0x00 8.--9. " EV_DATA_FMT ,Event Group (Read) Data Format" "12 bit,10 bit,8 bit,?..." bitfld.long 0x00 5. " EV_CHID ,Channel ID Mode for the Event Group" "Forced to 0,ID of A/D channel" textline " " bitfld.long 0x00 4. " OVR_EV_RAM_IGN ,Overrun Event Group RAM Ignore" "Not ignored,Ignored" bitfld.long 0x00 1. " EV_MODE ,Event mode" "Single,Continuous" textline " " bitfld.long 0x00 0. " FRZ_EV ,Freeze conversion event group" "Completed,Frozen" group.long 0x14++0x3 line.long 0x0 "G1MODECR,G1 MODE Control Register" bitfld.long 0x00 8.--9. " G1_DATA_FMT ,Group1 (Read) Data Format" "12 bit,10 bit,8 bit,?..." bitfld.long 0x00 5. " G1_CHID ,Channel ID Mode for the Group 1" "Forced to 0,ID of A/D channel" textline " " bitfld.long 0x00 4. " OVR_G1_RAM_IGN ,Overrun Group 1 RAM Ignore" "Not ignored,Ignored" bitfld.long 0x00 3. " G1_HW_TRIG ,Group 1 Hardware Triggered" "Software,Event" textline " " bitfld.long 0x00 1. " G1_MODE ,Group 1 mode" "Single,Continuous" bitfld.long 0x00 0. " FRZ_G1 ,Freeze Conversion group 1" "Completed,Frozen" group.long 0x18++0x3 line.long 0x0 "G2MODECR,G2 MODE Control Register" bitfld.long 0x00 8.--9. " G2_DATA_FMT ,Group2 (Read) Data Format" "12 bit,10 bit,8 bit,?..." bitfld.long 0x00 5. " G2_CHID ,Channel ID Mode for the Group 2" "Forced to 0,ID of A/D channel" textline " " bitfld.long 0x00 4. " OVR_G2_RAM_IGN ,Overrun Group 2 RAM Ignore" "Not ignored,Ignored" bitfld.long 0x00 3. " G2_HW_TRIG ,Group 2 Hardware Triggered" "Software,Event" textline " " bitfld.long 0x00 1. " G2_MODE ,Group 2 Mode" "Single,Continuous" bitfld.long 0x00 0. " FRZ_G2 ,Freeze Conversion Group 2" "Completed,Frozen" group.long 0x1C++0x3 line.long 0x0 "EVSRC,Event Group Trigger Source Select" bitfld.long 0x00 3. " EV_EDG_SEL ,ADC Event Group Trigger Edge Select" "High/low,Low/high" bitfld.long 0x00 0.--2. " EVSRC[2:0] ,Event Group Trigger Source Select" "AD2EVT,HET[8],HET[10],RTI compare 0,HET[17],HET[19],GIOB[0],GIOB[1]" group.long 0x20++0x3 line.long 0x0 "EVG1SRC,Group 1 Trigger Source Select" bitfld.long 0x00 3. " G1_EDG_SEL ,ADC Group 1 Trigger Edge Select" "High/low,Low/high" bitfld.long 0x00 0.--2. " G1SRC[2:0] ,Group 1 Trigger Source Select" "AD2EVT,HET[8],HET[10],RTI compare 0,HET[17],HET[19],GIOB[0],GIOB[1]" group.long 0x24++0x3 line.long 0x0 "G2SRC,Group 2 Trigger Source Select" bitfld.long 0x00 3. " G2_EDG_SEL ,ADC Group 2 Trigger Edge Select" "High/low,Low/high" bitfld.long 0x00 0.--2. " G2SRC[2:0] ,Group 2 Trigger Source Select" "AD2EVT,HET[8],HET[10],RTI compare 0,HET[17],HET[19],GIOB[0],GIOB[1]" width 10. group.long 0x28++0x3 line.long 0x0 "EVINTENA,Event Group Interrupt Enable" bitfld.long 0x00 3. " EV_END_INT_EN ,Event Group Conversion End Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 1. " EV_OVR_INT_EN ,Event Group Memory Overrun Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " EV_THR_INT_EN ,Event Group Memory Threshold Interrupt Enable" "Disabled,Enabled" group.long 0x2C++0x3 line.long 0x0 "G1INTENA,Group 1 Interrupt Enable" bitfld.long 0x00 3. " G1_END_INT_EN ,Event Group Conversion End Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 1. " G1_OVR_INT_EN ,Group 1 Memory Overrun Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " G1_THR_INT_EN ,Group 1 Memory Threshold Interrupt Enable" "Disabled,Enabled" group.long 0x30++0x3 line.long 0x0 "G2INTENA,Group 2 Interrupt Enable" bitfld.long 0x00 3. " G2_END_INT_EN ,Event Group Conversion End Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 1. " G2_OVR_INT_EN ,Group 2 Memory Overrun Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " G2_THR_INT_EN ,Group 2 Memory Threshold Interrupt Enable" "Disabled,Enabled" width 10. group.long 0x34++0x3 line.long 0x0 "EVINTFLG,Event Group Interrupt Flag" eventfld.long 0x00 3. " EV_END ,Event Group Conversion End" "Not converted,Converted" bitfld.long 0x00 2. " EV_MEM_EMPTY ,Event Group FIFO Empty Status" "Not empty,Empty" textline " " bitfld.long 0x00 1. " EV_MEM_OVERFLOW ,Event Group Memory Overrun Flag" "No overrun,Overrun" eventfld.long 0x00 0. " EV_THR_INT_FLAG ,Event Group Threshold Interrupt Flag" "No interrupt,Interrupt" group.long 0x38++0x3 line.long 0x0 "G1INTFLG,Group 1 Interrupt Flag" eventfld.long 0x00 3. " G1_END ,Group 1 Conversion End" "Not converted,Converted" bitfld.long 0x00 2. " AD_G1_MEM_EMPTY ,Group1 FIFO Empty Status" "Not empty,Empty" textline " " bitfld.long 0x00 1. " G1_MEM_OVERFLOW ,Event Group Memory Overrun Flag" "No overrun,Overrun" eventfld.long 0x00 0. " G1_THR_INT_FLAG ,Group 1 Threshold Interrupt Flag" "No interrupt,Interrupt" group.long 0x3C++0x3 line.long 0x0 "G2INTFLG,Group 2 Interrupt Flag" eventfld.long 0x00 3. " G2_END ,Group 2 Conversion End" "Not converted,Converted" bitfld.long 0x00 2. " AD_G2_MEM_EMPTY ,Group2 FIFO Empty Status" "Not empty,Empty" textline " " bitfld.long 0x00 1. " G2_MEM_OVERFLOW ,Group 2 Memory Overrun Flag" "No overrun,Overrun" eventfld.long 0x00 0. " G2_THR_INT_FLAG ,Group 2 Threshold Interrupt Flag" "No interrupt,Interrupt" group.long 0x40++0x3 line.long 0x0 "EVINTCR,Event Group Interrupt Threshold Counter" hexmask.long.byte 0x00 9.--15. 1. " Sign_Extension ,Sign Extension" hexmask.long.word 0x00 0.--8. 1. " EVTHR[8:0] ,Event Group Interrupt Threshold Counter" group.long 0x44++0x3 line.long 0x0 "G1INTCR,Group 1 Interrupt Threshold Counter" hexmask.long.byte 0x00 9.--15. 1. " Sign_Extension ,Sign Extension" hexmask.long.word 0x00 0.--8. 1. " G1THR[8:0] ,Group 1 Interrupt Threshold Counter" group.long 0x48++0x3 line.long 0x0 "G2INTCR,Group 2 Interrupt Threshold Counter" hexmask.long.byte 0x00 9.--15. 1. " Sign_Extension ,Sign Extension" hexmask.long.word 0x00 0.--8. 1. " G2THR[8:0] ,Group 2 Interrupt Threshold Counter" width 10. group.long 0x4C++0x3 line.long 0x0 "EVDMACR,Event Group DMA Control Register" hexmask.long.word 0x00 16.--24. 1. " EVBLOCKS[8:0] ,Number of Event Group Memory Buffers to be Transferred" bitfld.long 0x00 2. " EV_BLK_XFER ,Event Group Block DMA Transfer Enable" "Disabled,Enabled" bitfld.long 0x00 0. " EV_DMA_EN ,Event Group DMA Transfer Enable" "Disabled,Enabled" group.long 0x50++0x3 line.long 0x0 "G1DMACR,Group 1 DMA Control Register" hexmask.long.word 0x00 16.--24. 1. " G1BLOCKS[8:0] ,Number of Group 1 Memory Buffers to be Transferred" bitfld.long 0x00 2. " G1_BLK_XFER ,Group 1 Block DMA Transfer Enable" "Disabled,Enabled" bitfld.long 0x00 0. " G1_DMA_EN ,Group 1 DMA Transfer Enable" "Disabled,Enabled" group.long 0x54++0x3 line.long 0x0 "G2DMACR,Group 2 DMA Control Register" hexmask.long.word 0x00 16.--24. 1. " G2BLOCKS[8:0] ,Number of Group 2 Memory Buffers to be Transferred" bitfld.long 0x00 2. " G2_BLK_XFER ,Group 2 Block DMA Transfer Enable" "Disabled,Enabled" bitfld.long 0x00 0. " G2_DMA_EN ,Group 2 DMA Transfer Enable" "Disabled,Enabled" group.long 0x58++0x3 line.long 0x0 "BNDCR,Buffer Boundary Control Register" hexmask.long.word 0x00 16.--24. 1. " BNDA[8:0] ,Buffer Boundary A" hexmask.long.word 0x00 0.--8. 1. " BNDB[8:0] ,Buffer Boundary B" width 10. group.long 0x5C++0x3 line.long 0x0 "BNDEND,Buffer End Boundary" bitfld.long 0x00 16. " BUF_Init_Active ,Indicates the Status of the ADC RAM Intialization Process" "Not initialized,Initialized" bitfld.long 0x00 0.--2. " BNDEND[2:0] ,Buffer End Boundary" "16 words,32 words,64 words,128 words,192 words,256 words,512 words,1024 words" width 8. tree "ADC Sample Control Registers" group.long 0x60++0x3 line.long 0x0 "EVSAMP,Event Group Sample Window" hexmask.long.word 0x00 0.--11. 1. " EVACQ[11:0] ,Event Group Acquisition Prescale Bits" group.long 0x64++0x3 line.long 0x0 "G1SAMP,Group 1 Sample Window" hexmask.long.word 0x00 0.--11. 1. " G1ACQ[11:0] ,Group 1 Acquisition Prescale Bits" group.long 0x68++0x3 line.long 0x0 "G2SAMP,Group 2 Sample Window" hexmask.long.word 0x00 0.--11. 1. " G2ACQ[11:0] ,Group 2 Acquisition Prescale Bits" tree.end tree "ADC Status Registers" width 6. group.long 0x6C++0x3 line.long 0x0 "EVSR,Event Group Status Register" bitfld.long 0x00 3. " EV_MEM_EMPTY ,Event Group Memory Empty" "Not empty,Empty" bitfld.long 0x00 2. " EV_BUSY ,Event Group Conversion-Busy Flag" "Not active,Busy" bitfld.long 0x00 1. " EV_STOP ,Event Group Conversion Stopped Flag" "Not frozen,Frozen" textline " " eventfld.long 0x00 0. " EV_END ,Event Conversion-Ended Flag R/W" "Not completed,Completed" group.long 0x70++0x3 line.long 0x0 "G1SR,Group 1 Status Register" bitfld.long 0x00 3. " G1_MEM_EMPTY ,Group 1 Memory Empty" "Not empty,Empty" bitfld.long 0x00 2. " G1_BUSY ,Group 1 Conversion-Busy Flag" "Not active,Busy" bitfld.long 0x00 1. " G1_STOP ,Group 1 Conversion Stopped Flag" "Not frozen,Frozen" textline " " eventfld.long 0x00 0. " G1_END ,Group 1 Conversion-Ended Flag" "Not completed,Completed" group.long 0x74++0x3 line.long 0x0 "G2SR,Group 2 Status Register" bitfld.long 0x00 3. " G2_MEM_EMPTY ,Group 2 Memory Empty" "Not empty,Empty" bitfld.long 0x00 2. " G2_BUSY ,Group 2 Conversion-Busy Flag" "Not active,Busy" bitfld.long 0x00 1. " G2_STOP ,Group 2 Conversion Stopped Flag" "Not frozen,Frozen" textline " " eventfld.long 0x00 0. " G2_END ,Group 2 conversion-ended flag" "Not completed,Completed" tree.end tree "ADC Selection Control Registers" width 7. group.long 0x78++0x3 line.long 0x0 "EVSEL,Event Group select register" sif (cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")) bitfld.long 0x00 31. " EVCHNSEL[31] ,A/D Event Channel 31 Selection Bit" "Not converted,Converted" bitfld.long 0x00 30. " EVCHNSEL[30] ,A/D Event Channel 30 Selection Bit" "Not converted,Converted" textline " " bitfld.long 0x00 29. " EVCHNSEL[29] ,A/D Event Channel 29 Selection Bit" "Not converted,Converted" bitfld.long 0x00 28. " EVCHNSEL[28] ,A/D Event Channel 28 Selection Bit" "Not converted,Converted" textline " " bitfld.long 0x00 27. " EVCHNSEL[27] ,A/D Event Channel 27 Selection Bit" "Not converted,Converted" bitfld.long 0x00 26. " EVCHNSEL[26] ,A/D Event Channel 26 Selection Bit" "Not converted,Converted" textline " " bitfld.long 0x00 25. " EVCHNSEL[25] ,A/D Event Channel 25 Selection Bit" "Not converted,Converted" bitfld.long 0x00 24. " EVCHNSEL[24] ,A/D Event Channel 24 Selection Bit" "Not converted,Converted" textline " " bitfld.long 0x00 23. " EVCHNSEL[23] ,A/D Event Channel 23 Selection Bit" "Not converted,Converted" bitfld.long 0x00 22. " EVCHNSEL[22] ,A/D Event Channel 22 Selection Bit" "Not converted,Converted" textline " " bitfld.long 0x00 21. " EVCHNSEL[21] ,A/D Event Channel 21 Selection Bit" "Not converted,Converted" bitfld.long 0x00 20. " EVCHNSEL[20] ,A/D Event Channel 20 Selection Bit" "Not converted,Converted" textline " " bitfld.long 0x00 19. " EVCHNSEL[19] ,A/D Event Channel 19 Selection Bit" "Not converted,Converted" bitfld.long 0x00 18. " EVCHNSEL[18] ,A/D Event Channel 18 Selection Bit" "Not converted,Converted" textline " " bitfld.long 0x00 17. " EVCHNSEL[17] ,A/D Event Channel 17 Selection Bit" "Not converted,Converted" bitfld.long 0x00 16. " EVCHNSEL[16] ,A/D Event Channel 16 Selection Bit" "Not converted,Converted" textline " " endif bitfld.long 0x00 15. " EVCHNSEL[15] ,A/D Event Channel 15 Selection Bit" "Not converted,Converted" bitfld.long 0x00 14. " EVCHNSEL[14] ,A/D Event Channel 14 Selection Bit" "Not converted,Converted" textline " " bitfld.long 0x00 13. " EVCHNSEL[13] ,A/D Event Channel 13 Selection Bit" "Not converted,Converted" bitfld.long 0x00 12. " EVCHNSEL[12] ,A/D Event Channel 12 Selection Bit" "Not converted,Converted" textline " " bitfld.long 0x00 11. " EVCHNSEL[11] ,A/D Event Channel 11 Selection Bit" "Not converted,Converted" bitfld.long 0x00 10. " EVCHNSEL[10] ,A/D Event Channel 10 Selection Bit" "Not converted,Converted" textline " " bitfld.long 0x00 9. " EVCHNSEL[9] ,A/D Event Channel 9 Selection Bit" "Not converted,Converted" bitfld.long 0x00 8. " EVCHNSEL[8] ,A/D Event Channel 8 Selection Bit" "Not converted,Converted" textline " " bitfld.long 0x00 7. " EVCHNSEL[7] ,A/D Event Channel 7 Selection Bit" "Not converted,Converted" bitfld.long 0x00 6. " EVCHNSEL[6] ,A/D Event Channel 6 Selection Bit" "Not converted,Converted" textline " " bitfld.long 0x00 5. " EVCHNSEL[5] ,A/D Event Channel 5 Selection Bit" "Not converted,Converted" bitfld.long 0x00 4. " EVCHNSEL[4] ,A/D Event Channel 4 Selection Bit" "Not converted,Converted" textline " " bitfld.long 0x00 3. " EVCHNSEL[3] ,A/D Event Channel 3 Selection Bit" "Not converted,Converted" bitfld.long 0x00 2. " EVCHNSEL[2] ,A/D Event Channel 2 Selection Bit" "Not converted,Converted" textline " " bitfld.long 0x00 1. " EVCHNSEL[1] ,A/D Event Channel 1 Selection Bit" "Not converted,Converted" bitfld.long 0x00 0. " EVCHNSEL[0] ,A/D Event Channel 0 Selection Bit" "Not converted,Converted" group.long 0x7C++0x3 line.long 0x0 "G1SEL,Group 1 select register" sif (cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")) bitfld.long 0x00 31. " G1CHNSEL[31] ,A/D Channel 31 Enable Bit" "Not converted,Converted" bitfld.long 0x00 30. " G1CHNSEL[30] ,A/D Channel 30 Enable Bit" "Not converted,Converted" textline " " bitfld.long 0x00 29. " G1CHNSEL[29] ,A/D Channel 29 Enable Bit" "Not converted,Converted" bitfld.long 0x00 28. " G1CHNSEL[28] ,A/D Channel 28 Enable Bit" "Not converted,Converted" textline " " bitfld.long 0x00 27. " G1CHNSEL[27] ,A/D Channel 27 Enable Bit" "Not converted,Converted" bitfld.long 0x00 26. " G1CHNSEL[26] ,A/D Channel 26 Enable Bit" "Not converted,Converted" textline " " bitfld.long 0x00 25. " G1CHNSEL[25] ,A/D Channel 25 Enable Bit" "Not converted,Converted" bitfld.long 0x00 24. " G1CHNSEL[24] ,A/D Channel 24 Enable Bit" "Not converted,Converted" textline " " bitfld.long 0x00 23. " G1CHNSEL[23] ,A/D Channel 23 Enable Bit" "Not converted,Converted" bitfld.long 0x00 22. " G1CHNSEL[22] ,A/D Channel 22 Enable Bit" "Not converted,Converted" textline " " bitfld.long 0x00 21. " G1CHNSEL[21] ,A/D Channel 21 Enable Bit" "Not converted,Converted" bitfld.long 0x00 20. " G1CHNSEL[20] ,A/D Channel 20 Enable Bit" "Not converted,Converted" textline " " bitfld.long 0x00 19. " G1CHNSEL[19] ,A/D Channel 19 Enable Bit" "Not converted,Converted" bitfld.long 0x00 18. " G1CHNSEL[18] ,A/D Channel 18 Enable Bit" "Not converted,Converted" textline " " bitfld.long 0x00 17. " G1CHNSEL[17] ,A/D Channel 17 Enable Bit" "Not converted,Converted" bitfld.long 0x00 16. " G1CHNSEL[16] ,A/D Channel 16 Enable Bit" "Not converted,Converted" textline " " endif bitfld.long 0x00 15. " G1CHNSEL[15] ,A/D Channel 15 Enable Bit" "Not converted,Converted" bitfld.long 0x00 14. " G1CHNSEL[14] ,A/D Channel 14 Enable Bit" "Not converted,Converted" textline " " bitfld.long 0x00 13. " G1CHNSEL[13] ,A/D Channel 13 Enable Bit" "Not converted,Converted" bitfld.long 0x00 12. " G1CHNSEL[12] ,A/D Channel 12 Enable Bit" "Not converted,Converted" textline " " bitfld.long 0x00 11. " G1CHNSEL[11] ,A/D Channel 11 Enable Bit" "Not converted,Converted" bitfld.long 0x00 10. " G1CHNSEL[10] ,A/D Channel 10 Enable Bit" "Not converted,Converted" textline " " bitfld.long 0x00 9. " G1CHNSEL[9] ,A/D Channel 9 Enable Bit" "Not converted,Converted" bitfld.long 0x00 8. " G1CHNSEL[8] ,A/D Channel 8 Enable Bit" "Not converted,Converted" textline " " bitfld.long 0x00 7. " G1CHNSEL[7] ,A/D Channel 7 Enable Bit" "Not converted,Converted" bitfld.long 0x00 6. " G1CHNSEL[6] ,A/D Channel 6 Enable Bit" "Not converted,Converted" textline " " bitfld.long 0x00 5. " G1CHNSEL[5] ,A/D Channel 5 Enable Bit" "Not converted,Converted" bitfld.long 0x00 4. " G1CHNSEL[4] ,A/D Channel 4 Enable Bit" "Not converted,Converted" textline " " bitfld.long 0x00 3. " G1CHNSEL[3] ,A/D Channel 3 Enable Bit" "Not converted,Converted" bitfld.long 0x00 2. " G1CHNSEL[2] ,A/D Channel 2 Enable Bit" "Not converted,Converted" textline " " bitfld.long 0x00 1. " G1CHNSEL[1] ,A/D Channel 1 Enable Bit" "Not converted,Converted" bitfld.long 0x00 0. " G1CHNSEL[0] ,A/D Channel 0 Enable Bit" "Not converted,Converted" group.long 0x80++0x3 line.long 0x0 "G2SEL,Group 2 select register" sif (cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")) bitfld.long 0x00 31. " G2CHNSEL[31] ,A/D Channel 31 Enable Bit" "Not converted,Converted" bitfld.long 0x00 30. " G2CHNSEL[30] ,A/D Channel 30 Enable Bit" "Not converted,Converted" textline " " bitfld.long 0x00 29. " G2CHNSEL[29] ,A/D Channel 29 Enable Bit" "Not converted,Converted" bitfld.long 0x00 28. " G2CHNSEL[28] ,A/D Channel 28 Enable Bit" "Not converted,Converted" textline " " bitfld.long 0x00 27. " G2CHNSEL[27] ,A/D Channel 27 Enable Bit" "Not converted,Converted" bitfld.long 0x00 26. " G2CHNSEL[26] ,A/D Channel 26 Enable Bit" "Not converted,Converted" textline " " bitfld.long 0x00 25. " G2CHNSEL[25] ,A/D Channel 25 Enable Bit" "Not converted,Converted" bitfld.long 0x00 24. " G2CHNSEL[24] ,A/D Channel 24 Enable Bit" "Not converted,Converted" textline " " bitfld.long 0x00 23. " G2CHNSEL[23] ,A/D Channel 23 Enable Bit" "Not converted,Converted" bitfld.long 0x00 22. " G2CHNSEL[22] ,A/D Channel 22 Enable Bit" "Not converted,Converted" textline " " bitfld.long 0x00 21. " G2CHNSEL[21] ,A/D Channel 21 Enable Bit" "Not converted,Converted" bitfld.long 0x00 20. " G2CHNSEL[20] ,A/D Channel 20 Enable Bit" "Not converted,Converted" textline " " bitfld.long 0x00 19. " G2CHNSEL[19] ,A/D Channel 19 Enable Bit" "Not converted,Converted" bitfld.long 0x00 18. " G2CHNSEL[18] ,A/D Channel 18 Enable Bit" "Not converted,Converted" textline " " bitfld.long 0x00 17. " G2CHNSEL[17] ,A/D Channel 17 Enable Bit" "Not converted,Converted" bitfld.long 0x00 16. " G2CHNSEL[16] ,A/D Channel 16 Enable Bit" "Not converted,Converted" textline " " endif bitfld.long 0x00 15. " G2CHNSEL[15] ,A/D Channel 15 Enable Bit" "Not converted,Converted" bitfld.long 0x00 14. " G2CHNSEL[14] ,A/D Channel 14 Enable Bit" "Not converted,Converted" textline " " bitfld.long 0x00 13. " G2CHNSEL[13] ,A/D Channel 13 Enable Bit" "Not converted,Converted" bitfld.long 0x00 12. " G2CHNSEL[12] ,A/D Channel 12 Enable Bit" "Not converted,Converted" textline " " bitfld.long 0x00 11. " G2CHNSEL[11] ,A/D Channel 11 Enable Bit" "Not converted,Converted" bitfld.long 0x00 10. " G2CHNSEL[10] ,A/D Channel 10 Enable Bit" "Not converted,Converted" textline " " bitfld.long 0x00 9. " G2CHNSEL[9] ,A/D Channel 9 Enable Bit" "Not converted,Converted" bitfld.long 0x00 8. " G2CHNSEL[8] ,A/D Channel 8 Enable Bit" "Not converted,Converted" textline " " bitfld.long 0x00 7. " G2CHNSEL[7] ,A/D Channel 7 Enable Bit" "Not converted,Converted" bitfld.long 0x00 6. " G2CHNSEL[6] ,A/D Channel 6 Enable Bit" "Not converted,Converted" textline " " bitfld.long 0x00 5. " G2CHNSEL[5] ,A/D Channel 5 Enable Bit" "Not converted,Converted" bitfld.long 0x00 4. " G2CHNSEL[4] ,A/D Channel 4 Enable Bit" "Not converted,Converted" textline " " bitfld.long 0x00 3. " G2CHNSEL[3] ,A/D Channel 3 Enable Bit" "Not converted,Converted" bitfld.long 0x00 2. " G2CHNSEL[2] ,A/D Channel 2 Enable Bit" "Not converted,Converted" textline " " bitfld.long 0x00 1. " G2CHNSEL[1] ,A/D Channel 1 Enable Bit" "Not converted,Converted" bitfld.long 0x00 0. " G2CHNSEL[0] ,A/D Channel 0 Enable Bit" "Not converted,Converted" tree.end width 10. textline " " group.long 0x84++0x3 line.long 0x0 "CALR,Calibration Register" hexmask.long.word 0x00 0.--11. 1. " CALR[11:0] ,Calibration Bits" sif (cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")) rgroup.long 0x88++0x3 line.long 0x0 "SMSTATE,State Macine Current State" bitfld.long 0x00 0.--3. " SMSTATE[3:0] ,ADC State Macine Current State" "Idle,Conv_EV,Conv_SW1,Conv_SW2,Conv_Cal,Start_EV,Start_SW1,Start_SW2,Start_Cal,Wait_EV,Wait_SW1,Wait_SW2,Wait_CAL,?..." endif width 10. rgroup.long 0x8C++0x3 line.long 0x0 "LASTCONV,Last Conversion" bitfld.long 0x00 31. " IN[31] ,Digital input pin 31" "Low,High" bitfld.long 0x00 30. " IN[30] ,Digital input pin 30" "Low,High" bitfld.long 0x00 29. " IN[29] ,Digital input pin 29" "Low,High" bitfld.long 0x00 28. " IN[28] ,Digital input pin 28" "Low,High" textline " " bitfld.long 0x00 27. " IN[27] ,Digital input pin 27" "Low,High" bitfld.long 0x00 26. " IN[26] ,Digital input pin 26" "Low,High" bitfld.long 0x00 25. " IN[25] ,Digital input pin 25" "Low,High" bitfld.long 0x00 24. " IN[24] ,Digital input pin 24" "Low,High" textline " " bitfld.long 0x00 23. " IN[23] ,Digital input pin 23" "Low,High" bitfld.long 0x00 22. " IN[22] ,Digital input pin 22" "Low,High" bitfld.long 0x00 21. " IN[21] ,Digital input pin 21" "Low,High" bitfld.long 0x00 20. " IN[20] ,Digital input pin 20" "Low,High" textline " " bitfld.long 0x00 19. " IN[19] ,Digital input pin 19" "Low,High" bitfld.long 0x00 18. " IN[18] ,Digital input pin 18" "Low,High" bitfld.long 0x00 17. " IN[17] ,Digital input pin 17" "Low,High" bitfld.long 0x00 16. " IN[16] ,Digital input pin 16" "Low,High" textline " " bitfld.long 0x00 15. " IN[15] ,Digital input pin 15" "Low,High" bitfld.long 0x00 14. " IN[14] ,Digital input pin 14" "Low,High" bitfld.long 0x00 13. " IN[13] ,Digital input pin 13" "Low,High" bitfld.long 0x00 12. " IN[12] ,Digital input pin 12" "Low,High" textline " " bitfld.long 0x00 11. " IN[11] ,Digital input pin 11" "Low,High" bitfld.long 0x00 10. " IN[10] ,Digital input pin 10" "Low,High" bitfld.long 0x00 9. " IN[9] ,Digital input pin 9" "Low,High" bitfld.long 0x00 8. " IN[8] ,Digital input pin 8" "Low,High" textline " " bitfld.long 0x00 7. " IN[7] ,Digital input pin 7" "Low,High" bitfld.long 0x00 6. " IN[6] ,Digital input pin 6" "Low,High" bitfld.long 0x00 5. " IN[5] ,Digital input pin 5" "Low,High" bitfld.long 0x00 4. " IN[4] ,Digital input pin 4" "Low,High" textline " " bitfld.long 0x00 3. " IN[3] ,Digital input pin 3" "Low,High" bitfld.long 0x00 2. " IN[2] ,Digital input pin 2" "Low,High" bitfld.long 0x00 1. " IN[1] ,Digital input pin 1" "Low,High" bitfld.long 0x00 0. " IN[0] ,Digital input pin 0" "Low,High" tree "ADC Buffer Control Registers" width 13. hgroup.long 0x90++0x3 hide.long 0x0 "EVBUFFER0,Event Group Buffer 0" in hgroup.long 0x94++0x3 hide.long 0x0 "EVBUFFER1,Event Group Buffer 1" in hgroup.long 0x98++0x3 hide.long 0x0 "EVBUFFER2,Event Group Buffer 2" in hgroup.long 0x9C++0x3 hide.long 0x0 "EVBUFFER3,Event Group Buffer 3" in hgroup.long 0xA0++0x3 hide.long 0x0 "EVBUFFER4,Event Group Buffer 4" in hgroup.long 0xA4++0x3 hide.long 0x0 "EVBUFFER5,Event Group Buffer 5" in hgroup.long 0xA8++0x3 hide.long 0x0 "EVBUFFER6,Event Group Buffer 6" in hgroup.long 0xAC++0x3 hide.long 0x0 "EVBUFFER7,Event Group Buffer 7" in hgroup.long 0xB0++0x3 hide.long 0x0 "G1BUFFER0,Group 1 Buffer 0" in hgroup.long 0xB4++0x3 hide.long 0x0 "G1BUFFER1,Group 1 Buffer 1" in hgroup.long 0xB8++0x3 hide.long 0x0 "G1BUFFER2,Group 1 Buffer 2" in hgroup.long 0xBC++0x3 hide.long 0x0 "G1BUFFER3,Group 1 Buffer 3" in hgroup.long 0xC0++0x3 hide.long 0x0 "G1BUFFER4,Group 1 Buffer 4" in hgroup.long 0xC4++0x3 hide.long 0x0 "G1BUFFER5,Group 1 Buffer 5" in hgroup.long 0xC8++0x3 hide.long 0x0 "G1BUFFER6,Group 1 Buffer 6" in hgroup.long 0xCC++0x3 hide.long 0x0 "G1BUFFER7,Group 1 Buffer 7" in hgroup.long 0xD0++0x3 hide.long 0x0 "G2BUFFER0,Group 2 Buffer 0" in hgroup.long 0xD4++0x3 hide.long 0x0 "G2BUFFER1,Group 2 Buffer 1" in hgroup.long 0xD8++0x3 hide.long 0x0 "G2BUFFER2,Group 2 Buffer 2" in hgroup.long 0xDC++0x3 hide.long 0x0 "G2BUFFER3,Group 2 Buffer 3" in hgroup.long 0xE0++0x3 hide.long 0x0 "G2BUFFER4,Group 2 Buffer 4" in hgroup.long 0xE4++0x3 hide.long 0x0 "G2BUFFER5,Group 2 Buffer 5" in hgroup.long 0xE8++0x3 hide.long 0x0 "G2BUFFER6,Group 2 Buffer 6" in hgroup.long 0xEC++0x3 hide.long 0x0 "G2BUFFER7,Group 2 Buffer 7" in if (((d.l((ad:0xFFF7C200+0x10)))&0x300)==0x100) group.long 0xF0++0x3 line.long 0x0 "EVEMUBUFFER,Event Group EMU Buffer" bitfld.long 0x00 31. " EV_EMPTY ,Event Group FIFO Empty" "Not empty,Empty" bitfld.long 0x00 16.--20. " EVCHID[4:0] ,EVCHID" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31" hexmask.long.word 0x00 0.--9. 1. " EVDR[9:0] ,Event Group Digital Result" elif (((d.l((ad:0xFFF7C200+0x10)))&0x300)==0x200) group.long 0xF0++0x3 line.long 0x0 "EVEMUBUFFER,Event Group EMU Buffer" bitfld.long 0x00 31. " EV_EMPTY ,Event Group FIFO Empty" "Not empty,Empty" bitfld.long 0x00 16.--20. " EVCHID[4:0] ,EVCHID" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31" hexmask.long.byte 0x00 0.--7. 1. " EVDR[7:0] ,Event Group Digital Result" elif (((d.l((ad:0xFFF7C200+0x10)))&0x300)==0x300) group.long 0xF0++0x3 line.long 0x0 "EVEMUBUFFER,Event Group EMU Buffer" bitfld.long 0x00 31. " EV_EMPTY ,Event Group FIFO Empty" "Not empty,Empty" bitfld.long 0x00 16.--20. " EVCHID[4:0] ,EVCHID" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31" hexmask.long.word 0x00 0.--11. 1. " EVDR[11:0] ,Event Group Digital Result" else group.long 0xF0++0x3 line.long 0x0 "EVEMUBUFFER,Event Group EMU Buffer" bitfld.long 0x00 31. " EV_EMPTY ,Event Group FIFO Empty" "Not empty,Empty" bitfld.long 0x00 16.--20. " EVCHID[4:0] ,EVCHID" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31" endif if (((d.l((ad:0xFFF7C200+0x14)))&0x300)==0x100) group.long 0xF4++0x3 line.long 0x0 "G1BUFFER,Group 1 EMU Buffer" bitfld.long 0x00 31. " G1_EMPTY ,Group 1 FIFO Empty" "Not empty,Empty" bitfld.long 0x00 16.--20. " G1CHID[4:0] ,G1CHID" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31" hexmask.long.word 0x00 0.--9. 1. " G1DR[9:0] ,Group 1 Digital Result" elif (((d.l((ad:0xFFF7C200+0x14)))&0x300)==0x200) group.long 0xF4++0x3 line.long 0x0 "G1BUFFER,Group 1 EMU Buffer" bitfld.long 0x00 31. " G1_EMPTY ,Group 1 FIFO Empty" "Not empty,Empty" bitfld.long 0x00 16.--20. " G1CHID[4:0] ,G1CHID" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31" hexmask.long.byte 0x00 0.--7. 1. " G1DR[7:0] ,Group 1 Digital Result" elif (((d.l((ad:0xFFF7C200+0x14)))&0x300)==0x300) group.long 0xF4++0x3 line.long 0x0 "G1BUFFER,Group 1 EMU Buffer" bitfld.long 0x00 31. " G1_EMPTY ,Group 1 FIFO Empty" "Not empty,Empty" bitfld.long 0x00 16.--20. " G1CHID[4:0] ,G1CHID" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31" hexmask.long.word 0x00 0.--11. 1. " G1DR[11:0] ,Group 1 Digital Result" else group.long 0xF4++0x3 line.long 0x0 "G1BUFFER,Group 1 EMU Buffer" bitfld.long 0x00 31. " G1_EMPTY ,Group 1 FIFO Empty" "Not empty,Empty" bitfld.long 0x00 16.--20. " G1CHID[4:0] ,G1CHID" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31" endif if (((d.l((ad:0xFFF7C200+0x18)))&0x300)==0x100) group.long 0xF8++0x3 line.long 0x0 "G2BUFFER,Group 2 EMU Buffer" bitfld.long 0x00 31. " G2_EMPTY ,Group 2 FIFO Empty" "Not empty,Empty" bitfld.long 0x00 16.--20. " G2CHID[4:0] ,G2CHID" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31" hexmask.long.word 0x00 0.--9. 1. " G2DR[9:0] ,Group 2 Digital Result" elif (((d.l((ad:0xFFF7C200+0x18)))&0x300)==0x200) group.long 0xF8++0x3 line.long 0x0 "G2BUFFER,Group 2 EMU Buffer" bitfld.long 0x00 31. " G2_EMPTY ,Group 2 FIFO Empty" "Not empty,Empty" bitfld.long 0x00 16.--20. " G2CHID[4:0] ,G2CHID" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31" hexmask.long.byte 0x00 0.--7. 1. " G2DR[7:0] ,Group 2 Digital Result" elif (((d.l((ad:0xFFF7C200+0x18)))&0x300)==0x300) group.long 0xF8++0x3 line.long 0x0 "G2BUFFER,Group 2 EMU Buffer" bitfld.long 0x00 31. " G2_EMPTY ,Group 2 FIFO Empty" "Not empty,Empty" bitfld.long 0x00 16.--20. " G2CHID[4:0] ,G2CHID" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31" hexmask.long.word 0x00 0.--11. 1. " G2DR[11:0] ,Group 2 Digital Result" else group.long 0xF8++0x3 line.long 0x0 "G2BUFFER,Group 2 EMU Buffer" bitfld.long 0x00 31. " G2_EMPTY ,Group 2 FIFO Empty" "Not empty,Empty" bitfld.long 0x00 16.--20. " G2CHID[4:0] ,G2CHID" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31" endif tree.end width 9. tree "ADC ADEVT Pin Control Registers" group.long 0xFC++0x3 line.long 0x0 "EVTDIR,Event Group pin direction selection" bitfld.long 0x00 0. " EVT_DIR ,ADEVT Pin Direction Selection" "Output disabled,Output enabled" if (((d.l((ad:0xFFF7C200+0xfc)))&0x01)==0x01) group.long 0x100++0x3 line.long 0x0 "EVTOUT,Event Group pin data output" bitfld.long 0x00 0. " EVT_OUT ,ADEVT Pin Data Output" "Low,High" else hgroup.long 0x100++0x3 hide.long 0x0 "EVTOUT,Event Group pin data output" endif group.long 0x104++0x3 line.long 0x0 "EVTIN,Event Group pin input value" bitfld.long 0x00 0. " EVT_IN ,ADEVT Pin Input Value" "Low,High" group.long 0x108++0x3 line.long 0x0 "EVTSET,Event Group pin set" bitfld.long 0x00 0. " ADEVT_SET ,ADEVT Pin Set" "Low/No effect,High/Set" group.long 0x10C++0x3 line.long 0x0 "EVTCLR,Event Group pin clear" eventfld.long 0x00 0. " ADEVT_CLR ,ADEVT Pin Clear" "Low/No effect,High/CLear" if ((((d.l((ad:0xFFF7C200+0xfc)))&0x01)==0x01)&&(((d.l((ad:0xFFF7C200+0x0100)))&0x01)==0x01)) group.long 0x110++0x3 line.long 0x0 "EVTPDR,Event Group pin open-drain enable" bitfld.long 0x00 0. " ADEVT_PDR ,ADEVT Pin Open-Drain Enable" "High,Tri-state" else hgroup.long 0x110++0x3 hide.long 0x0 "EVTPDR,Event Group pin open-drain enable" endif if (((d.l((ad:0xFFF7C200+0xfc)))&0x01)==0x00) group.long 0x114++0x3 line.long 0x0 "EVTPDIS,Event Group pin pull control enable" bitfld.long 0x00 0. " ADEVT_PDIS ,ADEVT Pin Pull Control Enable" "Enabled,Disabled" else hgroup.long 0x114++0x3 hide.long 0x0 "EVTPDIS,Event Group pin pull control enable" endif group.long 0x118++0x3 line.long 0x0 "EVTPSEL,Event Group pull select" bitfld.long 0x00 0. " ADEVT_PSEL ,ADEVT Pull Select" "Pull-down,Pull-up" tree.end width 13. tree "ADC Sampling Capacitor Discharge Mode Control Registers" group.long 0x11C++0x3 line.long 0x0 "EVSAMPDISEN,Event Group Sampling Capacitor Discharge Mode" hexmask.long.byte 0x00 8.--15. 1. " EV_SAMP_DIS_CYC[7:0] ,ADC Sampling Capacitor is Dicharged Cycles" bitfld.long 0x00 0. " EV_SAMP_DIS_EN ,Sampling Capacitor Discharge Mode" "Disabled,Enabled" group.long 0x120++0x3 line.long 0x0 "G1SAMPDISEN,Group 1 Sampling Capacitor Discharge Mode" hexmask.long.byte 0x00 8.--15. 1. " G1_SAMP_DIS_CYC[7:0] ,ADC Sampling Capacitor is Dicharged Cycles" bitfld.long 0x00 0. " G1_SAMP_DIS_EN ,Sampling Capacitor Discharge Mode" "Disabled,Enabled" group.long 0x124++0x3 line.long 0x0 "G2SAMPDISEN,Group 2 Sampling Capacitor Discharge Mode" hexmask.long.byte 0x00 8.--15. 1. " G2_SAMP_DIS_CYC[7:0] ,ADC Sampling Capacitor is Dicharged Cycles" bitfld.long 0x00 0. " G2_SAMP_DIS_EN ,Sampling Capacitor Discharge Mode" "Disabled,Enabled" tree.end width tree "ADC Interrupt Control Registers" width 17. group.long 0x128++0x3 line.long 0x0 "MAGINTCR1,Magnitude Interrupt Control Register 1" hexmask.long.word 0x00 16.--27. 1. " MAG_THRESHOLD1 ,Magnitude Threshold 1" textline " " bitfld.long 0x00 15. " CHN/THR_COMP1 ,CHN/THR COMP1" "MAG THRESHOLD1,MAG CHID1" bitfld.long 0x00 14. " CMP_GE/LT1 ,CMP GE/LT1 Interrupt Result" "Lower,Greater" textline " " bitfld.long 0x00 8.--12. " COMP_CHID1 ,COMP CHID1 [4:0]" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31" bitfld.long 0x00 0.--4. " MAG_CHID1 ,MAG CHID1 [4:0]" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31" width 17. group.long 0x12C++0x3 line.long 0x0 "MAGINT1MASK,Magnitude Interrupt Mask 1" bitfld.long 0x00 11. " MAG_INT1_MASK[11] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 11" "Not masked,Masked" bitfld.long 0x00 10. " MAG_INT1_MASK[10] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 10" "Not masked,Masked" textline " " bitfld.long 0x00 9. " MAG_INT1_MASK[9] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 9" "Not masked,Masked" bitfld.long 0x00 8. " MAG_INT1_MASK[8] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " MAG_INT1_MASK[7] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 7" "Not masked,Masked" bitfld.long 0x00 6. " MAG_INT1_MASK[6] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 6" "Not masked,Masked" textline " " bitfld.long 0x00 5. " MAG_INT1_MASK[5] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 5" "Not masked,Masked" bitfld.long 0x00 4. " MAG_INT1_MASK[4] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " MAG_INT1_MASK[3] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 3" "Not masked,Masked" bitfld.long 0x00 2. " MAG_INT1_MASK[2] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 2" "Not masked,Masked" textline " " bitfld.long 0x00 1. " MAG_INT1_MASK[1] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 1" "Not masked,Masked" bitfld.long 0x00 0. " MAG_INT1_MASK[0] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 0" "Not masked,Masked" width 17. group.long 0x130++0x3 line.long 0x0 "MAGINTCR2,Magnitude Interrupt Control Register 2" hexmask.long.word 0x00 16.--27. 1. " MAG_THRESHOLD2 ,Magnitude Threshold 2" textline " " bitfld.long 0x00 15. " CHN/THR_COMP2 ,CHN/THR COMP2" "MAG THRESHOLD2,MAG CHID2" bitfld.long 0x00 14. " CMP_GE/LT2 ,CMP GE/LT2 Interrupt Result" "Lower,Greater" textline " " bitfld.long 0x00 8.--12. " COMP_CHID2 ,COMP CHID2 [4:0]" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31" bitfld.long 0x00 0.--4. " MAG_CHID2 ,MAG CHID2 [4:0]" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31" width 17. group.long 0x134++0x3 line.long 0x0 "MAGINT2MASK,Magnitude Interrupt Mask 2" bitfld.long 0x00 11. " MAG_INT2_MASK[11] ,Comparison for the Magnitude Threshold Interrupt 2 Mask 11" "Not masked,Masked" bitfld.long 0x00 10. " MAG_INT2_MASK[10] ,Comparison for the Magnitude Threshold Interrupt 2 Mask 10" "Not masked,Masked" textline " " bitfld.long 0x00 9. " MAG_INT2_MASK[9] ,Comparison for the Magnitude Threshold Interrupt 2 Mask 9" "Not masked,Masked" bitfld.long 0x00 8. " MAG_INT2_MASK[8] ,Comparison for the Magnitude Threshold Interrupt 2 Mask 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " MAG_INT2_MASK[7] ,Comparison for the Magnitude Threshold Interrupt 2 Mask 7" "Not masked,Masked" bitfld.long 0x00 6. " MAG_INT2_MASK[6] ,Comparison for the Magnitude Threshold Interrupt 2 Mask 6" "Not masked,Masked" textline " " bitfld.long 0x00 5. " MAG_INT2_MASK[5] ,Comparison for the Magnitude Threshold Interrupt 2 Mask 5" "Not masked,Masked" bitfld.long 0x00 4. " MAG_INT2_MASK[4] ,Comparison for the Magnitude Threshold Interrupt 2 Mask 4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " MAG_INT2_MASK[3] ,Comparison for the Magnitude Threshold Interrupt 2 Mask 3" "Not masked,Masked" bitfld.long 0x00 2. " MAG_INT2_MASK[2] ,Comparison for the Magnitude Threshold Interrupt 2 Mask 2" "Not masked,Masked" textline " " bitfld.long 0x00 1. " MAG_INT2_MASK[1] ,Comparison for the Magnitude Threshold Interrupt 2 Mask 1" "Not masked,Masked" bitfld.long 0x00 0. " MAG_INT2_MASK[0] ,Comparison for the Magnitude Threshold Interrupt 2 Mask 0" "Not masked,Masked" width 17. group.long 0x138++0x3 line.long 0x0 "MAGINTCR3,Magnitude Interrupt Control Register 3" hexmask.long.word 0x00 16.--27. 1. " MAG_THRESHOLD3 ,Magnitude Threshold 3" textline " " bitfld.long 0x00 15. " CHN/THR_COMP3 ,CHN/THR COMP3" "MAG THRESHOLD3,MAG CHID3" bitfld.long 0x00 14. " CMP_GE/LT3 ,CMP GE/LT3 Interrupt Result" "Lower,Greater" textline " " bitfld.long 0x00 8.--12. " COMP_CHID3 ,COMP CHID3 [4:0]" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31" bitfld.long 0x00 0.--4. " MAG_CHID3 ,MAG CHID3 [4:0]" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31" width 17. group.long 0x13C++0x3 line.long 0x0 "MAGINT3MASK,Magnitude Interrupt Mask 3" bitfld.long 0x00 11. " MAG_INT3_MASK[11] ,Comparison for the Magnitude Threshold Interrupt 3 Mask 11" "Not masked,Masked" bitfld.long 0x00 10. " MAG_INT3_MASK[10] ,Comparison for the Magnitude Threshold Interrupt 3 Mask 10" "Not masked,Masked" textline " " bitfld.long 0x00 9. " MAG_INT3_MASK[9] ,Comparison for the Magnitude Threshold Interrupt 3 Mask 9" "Not masked,Masked" bitfld.long 0x00 8. " MAG_INT3_MASK[8] ,Comparison for the Magnitude Threshold Interrupt 3 Mask 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " MAG_INT3_MASK[7] ,Comparison for the Magnitude Threshold Interrupt 3 Mask 7" "Not masked,Masked" bitfld.long 0x00 6. " MAG_INT3_MASK[6] ,Comparison for the Magnitude Threshold Interrupt 3 Mask 6" "Not masked,Masked" textline " " bitfld.long 0x00 5. " MAG_INT3_MASK[5] ,Comparison for the Magnitude Threshold Interrupt 3 Mask 5" "Not masked,Masked" bitfld.long 0x00 4. " MAG_INT3_MASK[4] ,Comparison for the Magnitude Threshold Interrupt 3 Mask 4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " MAG_INT3_MASK[3] ,Comparison for the Magnitude Threshold Interrupt 3 Mask 3" "Not masked,Masked" bitfld.long 0x00 2. " MAG_INT3_MASK[2] ,Comparison for the Magnitude Threshold Interrupt 3 Mask 2" "Not masked,Masked" textline " " bitfld.long 0x00 1. " MAG_INT3_MASK[1] ,Comparison for the Magnitude Threshold Interrupt 3 Mask 1" "Not masked,Masked" bitfld.long 0x00 0. " MAG_INT3_MASK[0] ,Comparison for the Magnitude Threshold Interrupt 3 Mask 0" "Not masked,Masked" width 17. group.long 0x140++0x3 line.long 0x0 "MAGINTCR4,Magnitude Interrupt Control Register 4" hexmask.long.word 0x00 16.--27. 1. " MAG_THRESHOLD4 ,Magnitude Threshold 4" textline " " bitfld.long 0x00 15. " CHN/THR_COMP4 ,CHN/THR COMP4" "MAG THRESHOLD4,MAG CHID4" bitfld.long 0x00 14. " CMP_GE/LT4 ,CMP GE/LT4 Interrupt Result" "Lower,Greater" textline " " bitfld.long 0x00 8.--12. " COMP_CHID4 ,COMP CHID4 [4:0]" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31" bitfld.long 0x00 0.--4. " MAG_CHID4 ,MAG CHID4 [4:0]" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31" width 17. group.long 0x144++0x3 line.long 0x0 "MAGINT4MASK,Magnitude Interrupt Mask 4" bitfld.long 0x00 11. " MAG_INT4_MASK[11] ,Comparison for the Magnitude Threshold Interrupt 4 Mask 11" "Not masked,Masked" bitfld.long 0x00 10. " MAG_INT4_MASK[10] ,Comparison for the Magnitude Threshold Interrupt 4 Mask 10" "Not masked,Masked" textline " " bitfld.long 0x00 9. " MAG_INT4_MASK[9] ,Comparison for the Magnitude Threshold Interrupt 4 Mask 9" "Not masked,Masked" bitfld.long 0x00 8. " MAG_INT4_MASK[8] ,Comparison for the Magnitude Threshold Interrupt 4 Mask 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " MAG_INT4_MASK[7] ,Comparison for the Magnitude Threshold Interrupt 4 Mask 7" "Not masked,Masked" bitfld.long 0x00 6. " MAG_INT4_MASK[6] ,Comparison for the Magnitude Threshold Interrupt 4 Mask 6" "Not masked,Masked" textline " " bitfld.long 0x00 5. " MAG_INT4_MASK[5] ,Comparison for the Magnitude Threshold Interrupt 4 Mask 5" "Not masked,Masked" bitfld.long 0x00 4. " MAG_INT4_MASK[4] ,Comparison for the Magnitude Threshold Interrupt 4 Mask 4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " MAG_INT4_MASK[3] ,Comparison for the Magnitude Threshold Interrupt 4 Mask 3" "Not masked,Masked" bitfld.long 0x00 2. " MAG_INT4_MASK[2] ,Comparison for the Magnitude Threshold Interrupt 4 Mask 2" "Not masked,Masked" textline " " bitfld.long 0x00 1. " MAG_INT4_MASK[1] ,Comparison for the Magnitude Threshold Interrupt 4 Mask 1" "Not masked,Masked" bitfld.long 0x00 0. " MAG_INT4_MASK[0] ,Comparison for the Magnitude Threshold Interrupt 4 Mask 0" "Not masked,Masked" width 17. group.long 0x148++0x3 line.long 0x0 "MAGINTCR5,Magnitude Interrupt Control Register 5" hexmask.long.word 0x00 16.--27. 1. " MAG_THRESHOLD5 ,Magnitude Threshold 5" textline " " bitfld.long 0x00 15. " CHN/THR_COMP5 ,CHN/THR COMP5" "MAG THRESHOLD5,MAG CHID5" bitfld.long 0x00 14. " CMP_GE/LT5 ,CMP GE/LT5 Interrupt Result" "Lower,Greater" textline " " bitfld.long 0x00 8.--12. " COMP_CHID5 ,COMP CHID5 [4:0]" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31" bitfld.long 0x00 0.--4. " MAG_CHID5 ,MAG CHID5 [4:0]" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31" width 17. group.long 0x14C++0x3 line.long 0x0 "MAGINT5MASK,Magnitude Interrupt Mask 5" bitfld.long 0x00 11. " MAG_INT5_MASK[11] ,Comparison for the Magnitude Threshold Interrupt 5 Mask 11" "Not masked,Masked" bitfld.long 0x00 10. " MAG_INT5_MASK[10] ,Comparison for the Magnitude Threshold Interrupt 5 Mask 10" "Not masked,Masked" textline " " bitfld.long 0x00 9. " MAG_INT5_MASK[9] ,Comparison for the Magnitude Threshold Interrupt 5 Mask 9" "Not masked,Masked" bitfld.long 0x00 8. " MAG_INT5_MASK[8] ,Comparison for the Magnitude Threshold Interrupt 5 Mask 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " MAG_INT5_MASK[7] ,Comparison for the Magnitude Threshold Interrupt 5 Mask 7" "Not masked,Masked" bitfld.long 0x00 6. " MAG_INT5_MASK[6] ,Comparison for the Magnitude Threshold Interrupt 5 Mask 6" "Not masked,Masked" textline " " bitfld.long 0x00 5. " MAG_INT5_MASK[5] ,Comparison for the Magnitude Threshold Interrupt 5 Mask 5" "Not masked,Masked" bitfld.long 0x00 4. " MAG_INT5_MASK[4] ,Comparison for the Magnitude Threshold Interrupt 5 Mask 4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " MAG_INT5_MASK[3] ,Comparison for the Magnitude Threshold Interrupt 5 Mask 3" "Not masked,Masked" bitfld.long 0x00 2. " MAG_INT5_MASK[2] ,Comparison for the Magnitude Threshold Interrupt 5 Mask 2" "Not masked,Masked" textline " " bitfld.long 0x00 1. " MAG_INT5_MASK[1] ,Comparison for the Magnitude Threshold Interrupt 5 Mask 1" "Not masked,Masked" bitfld.long 0x00 0. " MAG_INT5_MASK[0] ,Comparison for the Magnitude Threshold Interrupt 5 Mask 0" "Not masked,Masked" width 17. group.long 0x150++0x3 line.long 0x0 "MAGINTCR6,Magnitude Interrupt Control Register 6" hexmask.long.word 0x00 16.--27. 1. " MAG_THRESHOLD6 ,Magnitude Threshold 6" textline " " bitfld.long 0x00 15. " CHN/THR_COMP6 ,CHN/THR COMP6" "MAG THRESHOLD6,MAG CHID6" bitfld.long 0x00 14. " CMP_GE/LT6 ,CMP GE/LT6 Interrupt Result" "Lower,Greater" textline " " bitfld.long 0x00 8.--12. " COMP_CHID6 ,COMP CHID6 [4:0]" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31" bitfld.long 0x00 0.--4. " MAG_CHID6 ,MAG CHID6 [4:0]" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31" width 17. group.long 0x154++0x3 line.long 0x0 "MAGINT6MASK,Magnitude Interrupt Mask 6" bitfld.long 0x00 11. " MAG_INT6_MASK[11] ,Comparison for the Magnitude Threshold Interrupt 6 Mask 11" "Not masked,Masked" bitfld.long 0x00 10. " MAG_INT6_MASK[10] ,Comparison for the Magnitude Threshold Interrupt 6 Mask 10" "Not masked,Masked" textline " " bitfld.long 0x00 9. " MAG_INT6_MASK[9] ,Comparison for the Magnitude Threshold Interrupt 6 Mask 9" "Not masked,Masked" bitfld.long 0x00 8. " MAG_INT6_MASK[8] ,Comparison for the Magnitude Threshold Interrupt 6 Mask 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " MAG_INT6_MASK[7] ,Comparison for the Magnitude Threshold Interrupt 6 Mask 7" "Not masked,Masked" bitfld.long 0x00 6. " MAG_INT6_MASK[6] ,Comparison for the Magnitude Threshold Interrupt 6 Mask 6" "Not masked,Masked" textline " " bitfld.long 0x00 5. " MAG_INT6_MASK[5] ,Comparison for the Magnitude Threshold Interrupt 6 Mask 5" "Not masked,Masked" bitfld.long 0x00 4. " MAG_INT6_MASK[4] ,Comparison for the Magnitude Threshold Interrupt 6 Mask 4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " MAG_INT6_MASK[3] ,Comparison for the Magnitude Threshold Interrupt 6 Mask 3" "Not masked,Masked" bitfld.long 0x00 2. " MAG_INT6_MASK[2] ,Comparison for the Magnitude Threshold Interrupt 6 Mask 2" "Not masked,Masked" textline " " bitfld.long 0x00 1. " MAG_INT6_MASK[1] ,Comparison for the Magnitude Threshold Interrupt 6 Mask 1" "Not masked,Masked" bitfld.long 0x00 0. " MAG_INT6_MASK[0] ,Comparison for the Magnitude Threshold Interrupt 6 Mask 0" "Not masked,Masked" width 17. group.long 0x160++0x3 line.long 0x0 "MAGTHRINTFLG,Magnitude Threshold Interrupt Flag" sif (cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")) setclrfld.long 0x00 5. -0x08 5. -0x04 5. " MAG_THR_INT5_set/clr ,Magnitude Threshold Interrupt Flag Bit[5]" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 4. -0x08 4. -0x04 4. " MAG_THR_INT4_set/clr ,Magnitude Threshold Interrupt Flag Bit[4]" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 3. -0x08 3. -0x04 3. " MAG_THR_INT3_set/clr ,Magnitude Threshold Interrupt Flag Bit[3]" "No interrupt,Interrupt" textline " " endif setclrfld.long 0x00 2. -0x08 2. -0x04 2. " MAG_THR_INT2_set/clr ,Magnitude Threshold Interrupt Flag Bit[2]" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 1. -0x08 1. -0x04 1. " MAG_THR_INT1_set/clr ,Magnitude Threshold Interrupt Flag Bit[1]" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 0. -0x08 0. -0x04 0. " MAG_THR_INT0_set/clr ,Magnitude Threshold Interrupt Flag Bit[0]" "No interrupt,Interrupt" group.long 0x164++0x3 line.long 0x0 "MAGTHRINTOFFSET,Magnitude Threshold Interrupt Offset" bitfld.long 0x00 0.--2. " INT_OFF[2:0] ,Magnitude Threshold Interrupt Offset" "No interrupt,Interrupt 1,Interrupt 2,Interrupt 3,Interrupt 4,Interrupt 5,Interrupt 6,Invalid" tree.end width 15. tree "ADC RAM Control Registers" group.long 0x168++0x3 line.long 0x0 "EVFIFORESETCR,Event Group FIFO Reset" bitfld.long 0x00 0. " EV_FIFO_RESET ,Reset the ADC Event Group FIFO" "No reset,Reset" group.long 0x16C++0x3 line.long 0x0 "G1FIFORESETCR,Group 2 FIFO Reset" bitfld.long 0x00 0. " G1_FIFO_RESET ,Reset the ADC Group 1 FIFO" "No reset,Reset" group.long 0x170++0x3 line.long 0x0 "G2FIFORESETCR,Group 2 FIFO Reset" bitfld.long 0x00 0. " G2_FIFO_RESET ,Reset the ADC Group 2 FIFO" "No reset,Reset" rgroup.long 0x174++0x3 line.long 0x0 "EVRAMADDR,Event Group ADC RAM Pointer" hexmask.long.word 0x00 0.--8. 1. " EV_RAM_ADDR ,Event Group ADC RAM Pointer" rgroup.long 0x178++0x3 line.long 0x0 "G1RAMADDR,Group 1 ADC RAM Pointer" hexmask.long.word 0x00 0.--8. 1. " G1_RAM_ADDR ,Group 1 ADC RAM Pointer" rgroup.long 0x17C++0x3 line.long 0x0 "G2RAMADDR,Group 2 ADC RAM Pointer" hexmask.long.word 0x00 0.--8. 1. " G2_RAM_ADDR ,Group 2 ADC RAM Pointer" tree.end tree "ADC Parity Control Registers" width 9. group.long 0x180++0x3 line.long 0x0 "PARCR,Parity Control Register" bitfld.long 0x00 8. " TEST ,Parity Bits Map" "Not mapped,Mapped" bitfld.long 0x00 0.--3. " PARITY_ENA[3:0] ,Enable/Disable Parity Checking" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" rgroup.long 0x184++0x3 line.long 0x0 "PARADDR,Parity Address" hexmask.long.word 0x00 2.--11. 0x4 " Error_Address ,ERROR ADDRESS" tree.end width 0xb tree.end tree.end tree.open "DCAN (Controller Area Network)" tree "DCAN1" base ad:0xFFF7DC00 sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*") endian.be endif width 12. group.long 0x00++0x3 line.long 0x0 "CTRL,Config Register" bitfld.long 0x00 25. " WUBA ,Automatic Wake Up on Bus Activity When in Local Power Down Mode" "Not detected,Detected" bitfld.long 0x00 24. " PDR ,Request for Local Low Power Down Mode" "Not requested,Power down" sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS0232")) newline bitfld.long 0x00 20. " DE3 ,DMA Enable for IF3" "Disabled,Enabled" newline bitfld.long 0x00 19. " DE2 ,DMA Enable for IF2" "Disabled,Enabled" bitfld.long 0x00 18. " DE1 ,DMA Enable for IF1" "Disabled,Enabled" endif newline bitfld.long 0x00 17. " IE1 ,DCAN1INT Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " INITDBG ,Internal Init State While Debug Access Mode" "No debug,Debug" bitfld.long 0x00 15. " SWR ,SW Reset Enable" "No reset,Reset" bitfld.long 0x00 10.--13. " PMD ,Parity on/off" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" newline bitfld.long 0x00 9. " ABO ,Auto Bus On Enable" "Disabled,Enabled" bitfld.long 0x00 8. " IDS ,Interruption Debug Support Enable" "Disabled,Enabled" bitfld.long 0x00 7. " TEST ,Test Mode Enable" "Disabled,Enabled" newline bitfld.long 0x00 6. " CCE ,Configuration Change Enable" "Disabled,Enabled" bitfld.long 0x00 5. " DAR ,Disable Automatic Retransmission" "No,Yes" bitfld.long 0x00 3. " EIE ,Error Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " SIE ,Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 1. " IE ,DCAN0INT Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. " INIT ,Initialization" "Disabled,Enabled" sif (cpu()=="TMS470MF031"||cpu()=="TMS470MF042"||cpu()=="TMS470MF066"||cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10206-PGE")||cpu()==("TMS570LC4357")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")) group.long 0x04++0x3 line.long 0x0 "ES,Error and Status Register" rbitfld.long 0x00 10. " PDA ,Local Power Down Mode Acknowledge" "Not in,Is in" rbitfld.long 0x00 9. " WAKEUPPND ,Wake Up Pending" "No requested,Requested" rbitfld.long 0x00 8. " PER ,Parity Error Detected" "No error,Error" newline rbitfld.long 0x00 7. " BOFF ,Bus-Off State" "Not in,In" rbitfld.long 0x00 6. " EWARN ,Warning state" "<96,>96" rbitfld.long 0x00 5. " EPASS ,Error Passive State" "CAN Bus,Passive" newline bitfld.long 0x00 4. " RXOK ,Received a Message successfully" "No,Yes" bitfld.long 0x00 3. " TXOK ,Transmitted a Message successfully" "No,Yes" bitfld.long 0x00 0.--2. " LEC ,Last Error Code" "No error,Stuff,Form,Ack,Bit1,Bit0,CRC,No CAN" elif !cpuis("TMS570LS3137-EP") hgroup.long 0x04++0x3 hide.long 0x0 "STAT,Status Register" in else if (((per.l.be(ad:0xFFF7DC00))&0x100)==0x100) group.long 0x04++0x3 line.long 0x0 "ES,Error and Status Register" rbitfld.long 0x00 10. " PDA ,Local Power Down Mode Acknowledge" "Not in,Is in" rbitfld.long 0x00 9. " WAKEUPPND ,Wake Up Pending" "No requested,Requested" rbitfld.long 0x00 8. " PER ,Parity Error Detected" "No error,Error" newline rbitfld.long 0x00 7. " BOFF ,Bus-Off State" "Not in,In" rbitfld.long 0x00 6. " EWARN ,Warning state" "<96,>96" rbitfld.long 0x00 5. " EPASS ,Error Passive State" "CAN Bus,Passive" newline bitfld.long 0x00 4. " RXOK ,Received a Message successfully" "No,Yes" bitfld.long 0x00 3. " TXOK ,Transmitted a Message successfully" "No,Yes" bitfld.long 0x00 0.--2. " LEC ,Last Error Code" "No error,Stuff,Form,Ack,Bit1,Bit0,CRC,No CAN" else hgroup.long 0x04++0x3 hide.long 0x0 "ES,Error and Status Register" in endif endif rgroup.long 0x08++0x3 line.long 0x0 "ERRC,Error Counter Register" bitfld.long 0x00 15. " RP ,Receive Error Passive" "Below,Reached" hexmask.long.byte 0x00 8.--14. 1. " REC ,Receive Error Counter" hexmask.long.byte 0x00 0.--7. 1. " TEC ,Transmit Error Counter" sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*") if (((per.l.be(ad:0xFFF7DC00))&0x41)==0x41) group.long 0x0C++0x3 line.long 0x0 "BTBRP,Bit Timing_BRP Extension Register" bitfld.long 0x00 16.--19. " BRPE ,Baud Rate Prescaler Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--14. " TSEG2 ,The Time Segment After the Sample Point" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--11. " TSEG1 ,The Time Segment Before the Sample Point" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 6.--7. " SJW ,Synchronization Jump Width" "0,1,2,3" bitfld.long 0x00 0.--5. " BRP ,Baud Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.long 0x0C++0x3 line.long 0x0 "BTBRP,Bit Timing_BRP Extension Register" bitfld.long 0x00 16.--19. " BRPE ,Baud Rate Prescaler Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--14. " TSEG2 ,The Time Segment After the Sample Point" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--11. " TSEG1 ,The Time Segment Before the Sample Point" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 6.--7. " SJW ,Synchronization Jump Width" "0,1,2,3" bitfld.long 0x00 0.--5. " BRP ,Baud Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif else group.long 0x0C++0x3 line.long 0x0 "BTBRP,Bit Timing_BRP Extension Register" bitfld.long 0x00 16.--19. " BRPE ,Baud Rate Prescaler Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--14. " TSEG2 ,The Time Segment After the Sample Point" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--11. " TSEG1 ,The Time Segment Before the Sample Point" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 6.--7. " SJW ,Synchronization Jump Width" "0,1,2,3" bitfld.long 0x00 0.--5. " BRP ,Baud Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif rgroup.long 0x10++0x3 line.long 0x0 "INTR,Interrupt Register" hexmask.long.byte 0x00 16.--23. 1. " INT1ID[7-0] ,Interrupt 1 Identifier" hexmask.long.word 0x00 0.--15. 1. " INTID[15-0] ,Interrupt Identifier" sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*") if (((per.l.be(ad:0xFFF7DC00))&0x41)==0x41) group.long 0x14++0x3 line.long 0x0 "TEST,Test Register" bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable" "Normal,Enabled" bitfld.long 0x00 8. " EXL ,External Loop Back Mode" "Normal,Enabled" bitfld.long 0x00 7. " RX ,Receive Pin" "Dominant,Recessive" newline bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Normal,Sample point,Dominant,Recessive" bitfld.long 0x00 4. " LBACK ,Loop Back Mode" "Disabled,Enabled" bitfld.long 0x00 3. " SILENT ,Silent Mode" "Normal,Enabled" else rgroup.long 0x14++0x3 line.long 0x0 "TEST,Test Register" bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable" "Normal,Enabled" bitfld.long 0x00 8. " EXL ,External Loop Back Mode" "Normal,Enabled" bitfld.long 0x00 7. " RX ,Receive Pin" "Dominant,Recessive" newline bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Normal,Sample point,Dominant,Recessive" bitfld.long 0x00 4. " LBACK ,Loop Back Mode" "Disabled,Enabled" bitfld.long 0x00 3. " SILENT ,Silent Mode" "Normal,Enabled" endif elif !cpuis("TMS570LS3137-EP") group.long 0x14++0x3 line.long 0x0 "TEST,Test Register" bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable" "Normal,Enabled" bitfld.long 0x00 8. " EXL ,External Loop Back Mode" "Normal,Enabled" bitfld.long 0x00 7. " RX ,Receive Pin" "Dominant,Recessive" newline sif (cpu()=="TMS470MF031"||cpu()=="TMS470MF042"||cpu()=="TMS470MF066"||cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10206-PGE")||cpu()==("TMS570LC4357")||cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS21*")||cpuis("TMS570LS31*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")) bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Normal,Sample point,Dominant,Recessive" else bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Reset,Sample point,Dominant,Recessive" endif bitfld.long 0x00 4. " LBACK ,Loop Back Mode" "Disabled,Enabled" bitfld.long 0x00 3. " SILENT ,Silent Mode" "Normal,Enabled" else if (((per.l.be(ad:0xFFF7DC00))&0x80)==0x80) group.long 0x14++0x3 line.long 0x0 "TEST,Test Register" bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable" "Normal,Enabled" bitfld.long 0x00 8. " EXL ,External Loop Back Mode" "Normal,Enabled" bitfld.long 0x00 7. " RX ,Receive Pin" "Dominant,Recessive" newline bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Normal,Sample point,Dominant,Recessive" bitfld.long 0x00 4. " LBACK ,Loop Back Mode" "Disabled,Enabled" bitfld.long 0x00 3. " SILENT ,Silent Mode" "Normal,Enabled" else rgroup.long 0x14++0x3 line.long 0x0 "TEST,Test Register" bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable" "Normal,Enabled" bitfld.long 0x00 8. " EXL ,External Loop Back Mode" "Normal,Enabled" bitfld.long 0x00 7. " RX ,Receive Pin" "Dominant,Recessive" newline bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Normal,Sample point,Dominant,Recessive" bitfld.long 0x00 4. " LBACK ,Loop Back Mode" "Disabled,Enabled" bitfld.long 0x00 3. " SILENT ,Silent Mode" "Normal,Enabled" endif endif rgroup.long 0x1C++0x3 line.long 0x0 "PERR,Parity Error Code Register" bitfld.long 0x00 8.--10. " WORD_NUMBER ,Word Number" ",1,2,3,4,5,?..." hexmask.long.byte 0x00 0.--7. 1. " MESSAGE_NUMBER ,Message Number" sif (cpu()=="TMS470MF031"||cpu()=="TMS470MF042"||cpu()=="TMS470MF066"||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")) rgroup.long 0x20++0x3 line.long 0x00 "REL,DCAN Core Release Register" bitfld.long 0x00 28.--31. " REL ,Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " STEP ,Step of Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " SUBSTEP ,Substep of Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " YEAR ,Design Time Stamp - Year" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " MON ,Design Time Stamp - Month" hexmask.long.byte 0x00 0.--7. 1. " DAY ,Design Time Stamp - Day" endif width 19. sif (cpu()=="TMS570LC4357") group.long 0x24++0x0B line.long 0x00 "DCAN_ECCDIAG,ECC Diagnostic Register" bitfld.long 0x00 0.--3. " ECCDIAG , SECDED diagnostic mode enable/disable" ",,,,,Enabled,,,,,Disabled,?..." line.long 0x04 "DCAN_ECCDIAG_STAT, ECC Diagnostic Status Register" eventfld.long 0x04 8. " DEFLG_DIAG , Double bit error diagnostic" "No error,Error" eventfld.long 0x04 0. " SEFLG_DIAG , Single bit error diagnostic" "No error,Error" line.long 0x08 "DCAN_ECC_CS, ECC Control and Status Register" bitfld.long 0x08 24.--27. " SBE_EVT_EN , Single bit error event" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.long 0x08 16.--19. " ECCMODE , Single bit error correction" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" eventfld.long 0x08 8. " DEFLG , Double bit error flag" "No error,Error" eventfld.long 0x08 0. " SEFLG , Single bit error flag" "No error,Error" rgroup.long 0x30++0x03 line.long 0x00 "DCAN_ECC_SERR, ECC Single Bit Error Code Register" hexmask.long.byte 0x00 0.--7. 1. " Message_Number , Message object number where ECC single bit error has been detected" endif width 12. group.long 0x80++0x03 line.long 0x00 "ABOT,Auto Bus On Time" rgroup.long 0x84++0x4F line.long 0x00 "TRREQ,Transmission Request X" bitfld.long 0x00 14.--15. " TXRQSTREG8 ,Transmission Request 8" "0,1,2,3" bitfld.long 0x00 12.--13. " TXRQSTREG7 ,Transmission Request 7" "0,1,2,3" bitfld.long 0x00 10.--11. " TXRQSTREG6 ,Transmission Request 6" "0,1,2,3" bitfld.long 0x00 8.--9. " TXRQSTREG5 ,Transmission Request 5" "0,1,2,3" newline bitfld.long 0x00 6.--7. " TXRQSTREG4 ,Transmission Request 4" "0,1,2,3" bitfld.long 0x00 4.--5. " TXRQSTREG3 ,Transmission Request 3" "0,1,2,3" bitfld.long 0x00 2.--3. " TXRQSTREG2 ,Transmission Request 2" "0,1,2,3" bitfld.long 0x00 0.--1. " TXRQSTREG1 ,Transmission Request 1" "0,1,2,3" line.long 0x04 "TRREQ12,Transmission Request 1-2" bitfld.long 0x04 31. " TXRQST[32] ,Transmission Request Bits[32]" "Not requested,Requested" bitfld.long 0x04 30. " [31] ,Transmission Request Bits[31]" "Not requested,Requested" newline bitfld.long 0x04 29. " [30] ,Transmission Request Bits[30]" "Not requested,Requested" bitfld.long 0x04 28. " [29] ,Transmission Request Bits[29]" "Not requested,Requested" newline bitfld.long 0x04 27. " [28] ,Transmission Request Bits[28]" "Not requested,Requested" bitfld.long 0x04 26. " [27] ,Transmission Request Bits[27]" "Not requested,Requested" newline bitfld.long 0x04 25. " [26] ,Transmission Request Bits[26]" "Not requested,Requested" bitfld.long 0x04 24. " [25] ,Transmission Request Bits[25]" "Not requested,Requested" newline bitfld.long 0x04 23. " [24] ,Transmission Request Bits[24]" "Not requested,Requested" bitfld.long 0x04 22. " [23] ,Transmission Request Bits[23]" "Not requested,Requested" newline bitfld.long 0x04 21. " [22] ,Transmission Request Bits[22]" "Not requested,Requested" bitfld.long 0x04 20. " [21] ,Transmission Request Bits[21]" "Not requested,Requested" newline bitfld.long 0x04 19. " [20] ,Transmission Request Bits[20]" "Not requested,Requested" bitfld.long 0x04 18. " [19] ,Transmission Request Bits[19]" "Not requested,Requested" newline bitfld.long 0x04 17. " [18] ,Transmission Request Bits[18]" "Not requested,Requested" bitfld.long 0x04 16. " [17] ,Transmission Request Bits[17]" "Not requested,Requested" newline bitfld.long 0x04 15. " [16] ,Transmission Request Bits[16]" "Not requested,Requested" bitfld.long 0x04 14. " [15] ,Transmission Request Bits[15]" "Not requested,Requested" newline bitfld.long 0x04 13. " [14] ,Transmission Request Bits[14]" "Not requested,Requested" bitfld.long 0x04 12. " [13] ,Transmission Request Bits[13]" "Not requested,Requested" newline bitfld.long 0x04 11. " [12] ,Transmission Request Bits[12]" "Not requested,Requested" bitfld.long 0x04 10. " [11] ,Transmission Request Bits[11]" "Not requested,Requested" newline bitfld.long 0x04 9. " [10] ,Transmission Request Bits[10]" "Not requested,Requested" bitfld.long 0x04 8. " [9] ,Transmission Request Bits[9]" "Not requested,Requested" newline bitfld.long 0x04 7. " [8] ,Transmission Request Bits[8]" "Not requested,Requested" bitfld.long 0x04 6. " [7] ,Transmission Request Bits[7]" "Not requested,Requested" newline bitfld.long 0x04 5. " [6] ,Transmission Request Bits[6]" "Not requested,Requested" bitfld.long 0x04 4. " [5] ,Transmission Request Bits[5]" "Not requested,Requested" newline bitfld.long 0x04 3. " [4] ,Transmission Request Bits[4]" "Not requested,Requested" bitfld.long 0x04 2. " [3] ,Transmission Request Bits[3]" "Not requested,Requested" newline bitfld.long 0x04 1. " [2] ,Transmission Request Bits[2]" "Not requested,Requested" bitfld.long 0x04 0. " [1] ,Transmission Request Bits[1]" "Not requested,Requested" line.long 0x08 "TRREQ34,Transmission Request 3-4" bitfld.long 0x08 31. " TXRQST[64] ,Transmission Request Bits[64]" "Not requested,Requested" bitfld.long 0x08 30. " [63] ,Transmission Request Bits[63]" "Not requested,Requested" newline bitfld.long 0x08 29. " [62] ,Transmission Request Bits[62]" "Not requested,Requested" bitfld.long 0x08 28. " [61] ,Transmission Request Bits[61]" "Not requested,Requested" newline bitfld.long 0x08 27. " [60] ,Transmission Request Bits[60]" "Not requested,Requested" bitfld.long 0x08 26. " [59] ,Transmission Request Bits[59]" "Not requested,Requested" newline bitfld.long 0x08 25. " [58] ,Transmission Request Bits[58]" "Not requested,Requested" bitfld.long 0x08 24. " [57] ,Transmission Request Bits[57]" "Not requested,Requested" newline bitfld.long 0x08 23. " [56] ,Transmission Request Bits[56]" "Not requested,Requested" bitfld.long 0x08 22. " [55] ,Transmission Request Bits[55]" "Not requested,Requested" newline bitfld.long 0x08 21. " [54] ,Transmission Request Bits[54]" "Not requested,Requested" bitfld.long 0x08 20. " [53] ,Transmission Request Bits[53]" "Not requested,Requested" newline bitfld.long 0x08 19. " [52] ,Transmission Request Bits[52]" "Not requested,Requested" bitfld.long 0x08 18. " [51] ,Transmission Request Bits[51]" "Not requested,Requested" newline bitfld.long 0x08 17. " [50] ,Transmission Request Bits[50]" "Not requested,Requested" bitfld.long 0x08 16. " [49] ,Transmission Request Bits[49]" "Not requested,Requested" newline bitfld.long 0x08 15. " [48] ,Transmission Request Bits[48]" "Not requested,Requested" bitfld.long 0x08 14. " [47] ,Transmission Request Bits[47]" "Not requested,Requested" newline bitfld.long 0x08 13. " [46] ,Transmission Request Bits[46]" "Not requested,Requested" bitfld.long 0x08 12. " [45] ,Transmission Request Bits[45]" "Not requested,Requested" newline bitfld.long 0x08 11. " [44] ,Transmission Request Bits[44]" "Not requested,Requested" bitfld.long 0x08 10. " [43] ,Transmission Request Bits[43]" "Not requested,Requested" newline bitfld.long 0x08 9. " [42] ,Transmission Request Bits[42]" "Not requested,Requested" bitfld.long 0x08 8. " [41] ,Transmission Request Bits[41]" "Not requested,Requested" newline bitfld.long 0x08 7. " [40] ,Transmission Request Bits[40]" "Not requested,Requested" bitfld.long 0x08 6. " [39] ,Transmission Request Bits[39]" "Not requested,Requested" newline bitfld.long 0x08 5. " [38] ,Transmission Request Bits[38]" "Not requested,Requested" bitfld.long 0x08 4. " [37] ,Transmission Request Bits[37]" "Not requested,Requested" newline bitfld.long 0x08 3. " [36] ,Transmission Request Bits[36]" "Not requested,Requested" bitfld.long 0x08 2. " [35] ,Transmission Request Bits[35]" "Not requested,Requested" newline bitfld.long 0x08 1. " [34] ,Transmission Request Bits[34]" "Not requested,Requested" bitfld.long 0x08 0. " [33] ,Transmission Request Bits[33]" "Not requested,Requested" line.long 0x0C "TRREQ56,Transmission Request 5-6" bitfld.long 0x0C 31. " TXRQST[96] ,Transmission Request Bits[96]" "Not requested,Requested" bitfld.long 0x0C 30. " [95] ,Transmission Request Bits[95]" "Not requested,Requested" newline bitfld.long 0x0C 29. " [94] ,Transmission Request Bits[94]" "Not requested,Requested" bitfld.long 0x0C 28. " [93] ,Transmission Request Bits[93]" "Not requested,Requested" newline bitfld.long 0x0C 27. " [92] ,Transmission Request Bits[92]" "Not requested,Requested" bitfld.long 0x0C 26. " [91] ,Transmission Request Bits[91]" "Not requested,Requested" newline bitfld.long 0x0C 25. " [90] ,Transmission Request Bits[90]" "Not requested,Requested" bitfld.long 0x0C 24. " [89] ,Transmission Request Bits[89]" "Not requested,Requested" newline bitfld.long 0x0C 23. " [88] ,Transmission Request Bits[88]" "Not requested,Requested" bitfld.long 0x0C 22. " [87] ,Transmission Request Bits[87]" "Not requested,Requested" newline bitfld.long 0x0C 21. " [86] ,Transmission Request Bits[86]" "Not requested,Requested" bitfld.long 0x0C 20. " [85] ,Transmission Request Bits[85]" "Not requested,Requested" newline bitfld.long 0x0C 19. " [84] ,Transmission Request Bits[84]" "Not requested,Requested" bitfld.long 0x0C 18. " [83] ,Transmission Request Bits[83]" "Not requested,Requested" newline bitfld.long 0x0C 17. " [82] ,Transmission Request Bits[82]" "Not requested,Requested" bitfld.long 0x0C 16. " [81] ,Transmission Request Bits[81]" "Not requested,Requested" newline bitfld.long 0x0C 15. " [80] ,Transmission Request Bits[80]" "Not requested,Requested" bitfld.long 0x0C 14. " [79] ,Transmission Request Bits[79]" "Not requested,Requested" newline bitfld.long 0x0C 13. " [78] ,Transmission Request Bits[78]" "Not requested,Requested" bitfld.long 0x0C 12. " [77] ,Transmission Request Bits[77]" "Not requested,Requested" newline bitfld.long 0x0C 11. " [76] ,Transmission Request Bits[76]" "Not requested,Requested" bitfld.long 0x0C 10. " [75] ,Transmission Request Bits[75]" "Not requested,Requested" newline bitfld.long 0x0C 9. " [74] ,Transmission Request Bits[74]" "Not requested,Requested" bitfld.long 0x0C 8. " [73] ,Transmission Request Bits[73]" "Not requested,Requested" newline bitfld.long 0x0C 7. " [72] ,Transmission Request Bits[72]" "Not requested,Requested" bitfld.long 0x0C 6. " [71] ,Transmission Request Bits[71]" "Not requested,Requested" newline bitfld.long 0x0C 5. " [70] ,Transmission Request Bits[70]" "Not requested,Requested" bitfld.long 0x0C 4. " [69] ,Transmission Request Bits[69]" "Not requested,Requested" newline bitfld.long 0x0C 3. " [68] ,Transmission Request Bits[68]" "Not requested,Requested" bitfld.long 0x0C 2. " [67] ,Transmission Request Bits[67]" "Not requested,Requested" newline bitfld.long 0x0C 1. " [66] ,Transmission Request Bits[66]" "Not requested,Requested" bitfld.long 0x0C 0. " [65] ,Transmission Request Bits[65]" "Not requested,Requested" line.long 0x10 "TRREQ78,Transmission Request 7-8" bitfld.long 0x10 31. " TXRQST[128] ,Transmission Request Bits[128]" "Not requested,Requested" bitfld.long 0x10 30. " [127] ,Transmission Request Bits[127]" "Not requested,Requested" newline bitfld.long 0x10 29. " [126] ,Transmission Request Bits[126]" "Not requested,Requested" bitfld.long 0x10 28. " [125] ,Transmission Request Bits[125]" "Not requested,Requested" newline bitfld.long 0x10 27. " [124] ,Transmission Request Bits[124]" "Not requested,Requested" bitfld.long 0x10 26. " [123] ,Transmission Request Bits[123]" "Not requested,Requested" newline bitfld.long 0x10 25. " [122] ,Transmission Request Bits[122]" "Not requested,Requested" bitfld.long 0x10 24. " [121] ,Transmission Request Bits[121]" "Not requested,Requested" newline bitfld.long 0x10 23. " [120] ,Transmission Request Bits[120]" "Not requested,Requested" bitfld.long 0x10 22. " [119] ,Transmission Request Bits[119]" "Not requested,Requested" newline bitfld.long 0x10 21. " [118] ,Transmission Request Bits[118]" "Not requested,Requested" bitfld.long 0x10 20. " [117] ,Transmission Request Bits[117]" "Not requested,Requested" newline bitfld.long 0x10 19. " [116] ,Transmission Request Bits[116]" "Not requested,Requested" bitfld.long 0x10 18. " [115] ,Transmission Request Bits[115]" "Not requested,Requested" newline bitfld.long 0x10 17. " [114] ,Transmission Request Bits[114]" "Not requested,Requested" bitfld.long 0x10 16. " [113] ,Transmission Request Bits[113]" "Not requested,Requested" newline bitfld.long 0x10 15. " [112] ,Transmission Request Bits[112]" "Not requested,Requested" bitfld.long 0x10 14. " [111] ,Transmission Request Bits[111]" "Not requested,Requested" newline bitfld.long 0x10 13. " [110] ,Transmission Request Bits[110]" "Not requested,Requested" bitfld.long 0x10 12. " [109] ,Transmission Request Bits[109]" "Not requested,Requested" newline bitfld.long 0x10 11. " [108] ,Transmission Request Bits[108]" "Not requested,Requested" bitfld.long 0x10 10. " [107] ,Transmission Request Bits[107]" "Not requested,Requested" newline bitfld.long 0x10 9. " [106] ,Transmission Request Bits[106]" "Not requested,Requested" bitfld.long 0x10 8. " [105] ,Transmission Request Bits[105]" "Not requested,Requested" newline bitfld.long 0x10 7. " [104] ,Transmission Request Bits[104]" "Not requested,Requested" bitfld.long 0x10 6. " [103] ,Transmission Request Bits[103]" "Not requested,Requested" newline bitfld.long 0x10 5. " [102] ,Transmission Request Bits[102]" "Not requested,Requested" bitfld.long 0x10 4. " [101] ,Transmission Request Bits[101]" "Not requested,Requested" newline bitfld.long 0x10 3. " [100] ,Transmission Request Bits[100]" "Not requested,Requested" bitfld.long 0x10 2. " [99] ,Transmission Request Bits[99]" "Not requested,Requested" newline bitfld.long 0x10 1. " [98] ,Transmission Request Bits[98]" "Not requested,Requested" bitfld.long 0x10 0. " [97] ,Transmission Request Bits[97]" "Not requested,Requested" line.long 0x14 "NEWDAT,New Data X" bitfld.long 0x14 14.--15. " NEWDATREG8 ,New Data 8" "0,1,2,3" bitfld.long 0x14 12.--13. " NEWDATREG7 ,New Data 7" "0,1,2,3" bitfld.long 0x14 10.--11. " NEWDATREG6 ,New Data 6" "0,1,2,3" bitfld.long 0x14 8.--9. " NEWDATREG5 ,New Data 5" "0,1,2,3" newline bitfld.long 0x14 6.--7. " NEWDATREG4 ,NEW DATA 4" "0,1,2,3" bitfld.long 0x14 4.--5. " NEWDATREG3 ,New Data 3" "0,1,2,3" bitfld.long 0x14 2.--3. " NEWDATREG2 ,New Data 2" "0,1,2,3" bitfld.long 0x14 0.--1. " NEWDATREG1 ,New Data 1" "0,1,2,3" line.long 0x18 "NEWDAT12,New Data 1-2" bitfld.long 0x18 31. " NEWDAT[32] ,New Data Bit[32]" "Not requested,Requested" bitfld.long 0x18 30. " [31] ,New Data Bit[31]" "Not requested,Requested" newline bitfld.long 0x18 29. " [30] ,New Data Bit[30]" "Not requested,Requested" bitfld.long 0x18 28. " [29] ,New Data Bit[29]" "Not requested,Requested" newline bitfld.long 0x18 27. " [28] ,New Data Bit[28]" "Not requested,Requested" bitfld.long 0x18 26. " [27] ,New Data Bit[27]" "Not requested,Requested" newline bitfld.long 0x18 25. " [26] ,New Data Bit[26]" "Not requested,Requested" bitfld.long 0x18 24. " [25] ,New Data Bit[25]" "Not requested,Requested" newline bitfld.long 0x18 23. " [24] ,New Data Bit[24]" "Not requested,Requested" bitfld.long 0x18 22. " [23] ,New Data Bit[23]" "Not requested,Requested" newline bitfld.long 0x18 21. " [22] ,New Data Bit[22]" "Not requested,Requested" bitfld.long 0x18 20. " [21] ,New Data Bit[21]" "Not requested,Requested" newline bitfld.long 0x18 19. " [20] ,New Data Bit[20]" "Not requested,Requested" bitfld.long 0x18 18. " [19] ,New Data Bit[19]" "Not requested,Requested" newline bitfld.long 0x18 17. " [18] ,New Data Bit[18]" "Not requested,Requested" bitfld.long 0x18 16. " [17] ,New Data Bit[17]" "Not requested,Requested" newline bitfld.long 0x18 15. " [16] ,New Data Bit[16]" "Not requested,Requested" bitfld.long 0x18 14. " [15] ,New Data Bit[15]" "Not requested,Requested" newline bitfld.long 0x18 13. " [14] ,New Data Bit[14]" "Not requested,Requested" bitfld.long 0x18 12. " [13] ,New Data Bit[13]" "Not requested,Requested" newline bitfld.long 0x18 11. " [12] ,New Data Bit[12]" "Not requested,Requested" bitfld.long 0x18 10. " [11] ,New Data Bit[11]" "Not requested,Requested" newline bitfld.long 0x18 9. " [10] ,New Data Bit[10]" "Not requested,Requested" bitfld.long 0x18 8. " [9] ,New Data Bit[9]" "Not requested,Requested" newline bitfld.long 0x18 7. " [8] ,New Data Bit[8]" "Not requested,Requested" bitfld.long 0x18 6. " [7] ,New Data Bit[7]" "Not requested,Requested" newline bitfld.long 0x18 5. " [6] ,New Data Bit[6]" "Not requested,Requested" bitfld.long 0x18 4. " [5] ,New Data Bit[5]" "Not requested,Requested" newline bitfld.long 0x18 3. " [4] ,New Data Bit[4]" "Not requested,Requested" bitfld.long 0x18 2. " [3] ,New Data Bit[3]" "Not requested,Requested" newline bitfld.long 0x18 1. " [2] ,New Data Bit[2]" "Not requested,Requested" bitfld.long 0x18 0. " [1] ,New Data Bit[1]" "Not requested,Requested" line.long 0x1C "NEWDAT34,New Data 3-4" bitfld.long 0x1C 31. " NEWDAT[64] ,New Data Bit[64]" "Not requested,Requested" bitfld.long 0x1C 30. " [63] ,New Data Bit[63]" "Not requested,Requested" newline bitfld.long 0x1C 29. " [62] ,New Data Bit[62]" "Not requested,Requested" bitfld.long 0x1C 28. " [61] ,New Data Bit[61]" "Not requested,Requested" newline bitfld.long 0x1C 27. " [60] ,New Data Bit[60]" "Not requested,Requested" bitfld.long 0x1C 26. " [59] ,New Data Bit[59]" "Not requested,Requested" newline bitfld.long 0x1C 25. " [58] ,New Data Bit[58]" "Not requested,Requested" bitfld.long 0x1C 24. " [57] ,New Data Bit[57]" "Not requested,Requested" newline bitfld.long 0x1C 23. " [56] ,New Data Bit[56]" "Not requested,Requested" bitfld.long 0x1C 22. " [55] ,New Data Bit[55]" "Not requested,Requested" newline bitfld.long 0x1C 21. " [54] ,New Data Bit[54]" "Not requested,Requested" bitfld.long 0x1C 20. " [53] ,New Data Bit[53]" "Not requested,Requested" newline bitfld.long 0x1C 19. " [52] ,New Data Bit[52]" "Not requested,Requested" bitfld.long 0x1C 18. " [51] ,New Data Bit[51]" "Not requested,Requested" newline bitfld.long 0x1C 17. " [50] ,New Data Bit[50]" "Not requested,Requested" bitfld.long 0x1C 16. " [49] ,New Data Bit[49]" "Not requested,Requested" newline bitfld.long 0x1C 15. " [48] ,New Data Bit[48]" "Not requested,Requested" bitfld.long 0x1C 14. " [47] ,New Data Bit[47]" "Not requested,Requested" newline bitfld.long 0x1C 13. " [46] ,New Data Bit[46]" "Not requested,Requested" bitfld.long 0x1C 12. " [45] ,New Data Bit[45]" "Not requested,Requested" newline bitfld.long 0x1C 11. " [44] ,New Data Bit[44]" "Not requested,Requested" bitfld.long 0x1C 10. " [43] ,New Data Bit[43]" "Not requested,Requested" newline bitfld.long 0x1C 9. " [42] ,New Data Bit[42]" "Not requested,Requested" bitfld.long 0x1C 8. " [41] ,New Data Bit[41]" "Not requested,Requested" newline bitfld.long 0x1C 7. " [40] ,New Data Bit[40]" "Not requested,Requested" bitfld.long 0x1C 6. " [39] ,New Data Bit[39]" "Not requested,Requested" newline bitfld.long 0x1C 5. " [38] ,New Data Bit[38]" "Not requested,Requested" bitfld.long 0x1C 4. " [37] ,New Data Bit[37]" "Not requested,Requested" newline bitfld.long 0x1C 3. " [36] ,New Data Bit[36]" "Not requested,Requested" bitfld.long 0x1C 2. " [35] ,New Data Bit[35]" "Not requested,Requested" newline bitfld.long 0x1C 1. " [34] ,New Data Bit[34]" "Not requested,Requested" bitfld.long 0x1C 0. " [33] ,New Data Bit[33]" "Not requested,Requested" line.long 0x20 "NEWDAT56,New Data 5-6" bitfld.long 0x20 31. " NEWDAT[96] ,New Data Bit[96]" "Not requested,Requested" bitfld.long 0x20 30. " [95] ,New Data Bit[95]" "Not requested,Requested" newline bitfld.long 0x20 29. " [94] ,New Data Bit[94]" "Not requested,Requested" bitfld.long 0x20 28. " [93] ,New Data Bit[93]" "Not requested,Requested" newline bitfld.long 0x20 27. " [92] ,New Data Bit[92]" "Not requested,Requested" bitfld.long 0x20 26. " [91] ,New Data Bit[91]" "Not requested,Requested" newline bitfld.long 0x20 25. " [90] ,New Data Bit[90]" "Not requested,Requested" bitfld.long 0x20 24. " [89] ,New Data Bit[89]" "Not requested,Requested" newline bitfld.long 0x20 23. " [88] ,New Data Bit[88]" "Not requested,Requested" bitfld.long 0x20 22. " [87] ,New Data Bit[87]" "Not requested,Requested" newline bitfld.long 0x20 21. " [86] ,New Data Bit[86]" "Not requested,Requested" bitfld.long 0x20 20. " [85] ,New Data Bit[85]" "Not requested,Requested" newline bitfld.long 0x20 19. " [84] ,New Data Bit[84]" "Not requested,Requested" bitfld.long 0x20 18. " [83] ,New Data Bit[83]" "Not requested,Requested" newline bitfld.long 0x20 17. " [82] ,New Data Bit[82]" "Not requested,Requested" bitfld.long 0x20 16. " [81] ,New Data Bit[81]" "Not requested,Requested" newline bitfld.long 0x20 15. " [80] ,New Data Bit[80]" "Not requested,Requested" bitfld.long 0x20 14. " [79] ,New Data Bit[79]" "Not requested,Requested" newline bitfld.long 0x20 13. " [78] ,New Data Bit[78]" "Not requested,Requested" bitfld.long 0x20 12. " [77] ,New Data Bit[77]" "Not requested,Requested" newline bitfld.long 0x20 11. " [76] ,New Data Bit[76]" "Not requested,Requested" bitfld.long 0x20 10. " [75] ,New Data Bit[75]" "Not requested,Requested" newline bitfld.long 0x20 9. " [74] ,New Data Bit[74]" "Not requested,Requested" bitfld.long 0x20 8. " [73] ,New Data Bit[73]" "Not requested,Requested" newline bitfld.long 0x20 7. " [72] ,New Data Bit[72]" "Not requested,Requested" bitfld.long 0x20 6. " [71] ,New Data Bit[71]" "Not requested,Requested" newline bitfld.long 0x20 5. " [70] ,New Data Bit[70]" "Not requested,Requested" bitfld.long 0x20 4. " [69] ,New Data Bit[69]" "Not requested,Requested" newline bitfld.long 0x20 3. " [68] ,New Data Bit[68]" "Not requested,Requested" bitfld.long 0x20 2. " [67] ,New Data Bit[67]" "Not requested,Requested" newline bitfld.long 0x20 1. " [66] ,New Data Bit[66]" "Not requested,Requested" bitfld.long 0x20 0. " [65] ,New Data Bit[65]" "Not requested,Requested" line.long 0x24 "NEWDAT78,New Data 7-8" bitfld.long 0x24 31. " NEWDAT[128] ,New Data Bit[128]" "Not requested,Requested" bitfld.long 0x24 30. " [127] ,New Data Bit[127]" "Not requested,Requested" newline bitfld.long 0x24 29. " [126] ,New Data Bit[126]" "Not requested,Requested" bitfld.long 0x24 28. " [125] ,New Data Bit[125]" "Not requested,Requested" newline bitfld.long 0x24 27. " [124] ,New Data Bit[124]" "Not requested,Requested" bitfld.long 0x24 26. " [123] ,New Data Bit[123]" "Not requested,Requested" newline bitfld.long 0x24 25. " [122] ,New Data Bit[122]" "Not requested,Requested" bitfld.long 0x24 24. " [121] ,New Data Bit[121]" "Not requested,Requested" newline bitfld.long 0x24 23. " [120] ,New Data Bit[120]" "Not requested,Requested" bitfld.long 0x24 22. " [119] ,New Data Bit[119]" "Not requested,Requested" newline bitfld.long 0x24 21. " [118] ,New Data Bit[118]" "Not requested,Requested" bitfld.long 0x24 20. " [117] ,New Data Bit[117]" "Not requested,Requested" newline bitfld.long 0x24 19. " [116] ,New Data Bit[116]" "Not requested,Requested" bitfld.long 0x24 18. " [115] ,New Data Bit[115]" "Not requested,Requested" newline bitfld.long 0x24 17. " [114] ,New Data Bit[114]" "Not requested,Requested" bitfld.long 0x24 16. " [113] ,New Data Bit[113]" "Not requested,Requested" newline bitfld.long 0x24 15. " [112] ,New Data Bit[112]" "Not requested,Requested" bitfld.long 0x24 14. " [111] ,New Data Bit[111]" "Not requested,Requested" newline bitfld.long 0x24 13. " [110] ,New Data Bit[110]" "Not requested,Requested" bitfld.long 0x24 12. " [109] ,New Data Bit[109]" "Not requested,Requested" newline bitfld.long 0x24 11. " [108] ,New Data Bit[108]" "Not requested,Requested" bitfld.long 0x24 10. " [107] ,New Data Bit[107]" "Not requested,Requested" newline bitfld.long 0x24 9. " [106] ,New Data Bit[106]" "Not requested,Requested" bitfld.long 0x24 8. " [105] ,New Data Bit[105]" "Not requested,Requested" newline bitfld.long 0x24 7. " [104] ,New Data Bit[104]" "Not requested,Requested" bitfld.long 0x24 6. " [103] ,New Data Bit[103]" "Not requested,Requested" newline bitfld.long 0x24 5. " [102] ,New Data Bit[102]" "Not requested,Requested" bitfld.long 0x24 4. " [101] ,New Data Bit[101]" "Not requested,Requested" newline bitfld.long 0x24 3. " [100] ,New Data Bit[100]" "Not requested,Requested" bitfld.long 0x24 2. " [99] ,New Data Bit[99]" "Not requested,Requested" newline bitfld.long 0x24 1. " [98] ,New Data Bit[98]" "Not requested,Requested" bitfld.long 0x24 0. " [97] ,New Data Bit[97]" "Not requested,Requested" line.long 0x28 "INTPEN,Interrupt Pending X" bitfld.long 0x28 14.--15. " INTPENDREG[8] ,Interrupt Pending 8" "0,1,2,3" bitfld.long 0x28 12.--13. " [7] ,Interrupt Pending 7" "0,1,2,3" bitfld.long 0x28 10.--11. " [6] ,Interrupt Pending 6" "0,1,2,3" bitfld.long 0x28 8.--9. " [5] ,Interrupt Pending 5" "0,1,2,3" newline bitfld.long 0x28 6.--7. " [4] ,Interrupt Pending 4" "0,1,2,3" bitfld.long 0x28 4.--5. " [3] ,Interrupt Pending 3" "0,1,2,3" bitfld.long 0x28 2.--3. " [2] ,Interrupt Pending 2" "0,1,2,3" bitfld.long 0x28 0.--1. " [1] ,Interrupt Pending 1" "0,1,2,3" line.long 0x2C "INTPEN12,Interrupt Pending 1-2" bitfld.long 0x2C 31. " IntPnd[32] ,Interrupt Pending Bit[32]" "No interrupt,Interrupt" bitfld.long 0x2C 30. " [31] ,Interrupt Pending Bit[31]" "No interrupt,Interrupt" newline bitfld.long 0x2C 29. " [30] ,Interrupt Pending Bit[30]" "No interrupt,Interrupt" bitfld.long 0x2C 28. " [29] ,Interrupt Pending Bit[29]" "No interrupt,Interrupt" newline bitfld.long 0x2C 27. " [28] ,Interrupt Pending Bit[28]" "No interrupt,Interrupt" bitfld.long 0x2C 26. " [27] ,Interrupt Pending Bit[27]" "No interrupt,Interrupt" newline bitfld.long 0x2C 25. " [26] ,Interrupt Pending Bit[26]" "No interrupt,Interrupt" bitfld.long 0x2C 24. " [25] ,Interrupt Pending Bit[25]" "No interrupt,Interrupt" newline bitfld.long 0x2C 23. " [24] ,Interrupt Pending Bit[24]" "No interrupt,Interrupt" bitfld.long 0x2C 22. " [23] ,Interrupt Pending Bit[23]" "No interrupt,Interrupt" newline bitfld.long 0x2C 21. " [22] ,Interrupt Pending Bit[22]" "No interrupt,Interrupt" bitfld.long 0x2C 20. " [21] ,Interrupt Pending Bit[21]" "No interrupt,Interrupt" newline bitfld.long 0x2C 19. " [20] ,Interrupt Pending Bit[20]" "No interrupt,Interrupt" bitfld.long 0x2C 18. " [19] ,Interrupt Pending Bit[19]" "No interrupt,Interrupt" newline bitfld.long 0x2C 17. " [18] ,Interrupt Pending Bit[18]" "No interrupt,Interrupt" bitfld.long 0x2C 16. " [17] ,Interrupt Pending Bit[17]" "No interrupt,Interrupt" newline bitfld.long 0x2C 15. " [16] ,Interrupt Pending Bit[16]" "No interrupt,Interrupt" bitfld.long 0x2C 14. " [15] ,Interrupt Pending Bit[15]" "No interrupt,Interrupt" newline bitfld.long 0x2C 13. " [14] ,Interrupt Pending Bit[14]" "No interrupt,Interrupt" bitfld.long 0x2C 12. " [13] ,Interrupt Pending Bit[13]" "No interrupt,Interrupt" newline bitfld.long 0x2C 11. " [12] ,Interrupt Pending Bit[12]" "No interrupt,Interrupt" bitfld.long 0x2C 10. " [11] ,Interrupt Pending Bit[11]" "No interrupt,Interrupt" newline bitfld.long 0x2C 9. " [10] ,Interrupt Pending Bit[10]" "No interrupt,Interrupt" bitfld.long 0x2C 8. " [9] ,Interrupt Pending Bit[9]" "No interrupt,Interrupt" newline bitfld.long 0x2C 7. " [8] ,Interrupt Pending Bit[8]" "No interrupt,Interrupt" bitfld.long 0x2C 6. " [7] ,Interrupt Pending Bit[7]" "No interrupt,Interrupt" newline bitfld.long 0x2C 5. " [6] ,Interrupt Pending Bit[6]" "No interrupt,Interrupt" bitfld.long 0x2C 4. " [5] ,Interrupt Pending Bit[5]" "No interrupt,Interrupt" newline bitfld.long 0x2C 3. " [4] ,Interrupt Pending Bit[4]" "No interrupt,Interrupt" bitfld.long 0x2C 2. " [3] ,Interrupt Pending Bit[3]" "No interrupt,Interrupt" newline bitfld.long 0x2C 1. " [2] ,Interrupt Pending Bit[2]" "No interrupt,Interrupt" bitfld.long 0x2C 0. " [1] ,Interrupt Pending Bit[1]" "No interrupt,Interrupt" line.long 0x30 "INTPEN34,Interrupt Pending 3-4" bitfld.long 0x30 31. " INTPND[64] ,Interrupt Pending Bit[64]" "No interrupt,Interrupt" bitfld.long 0x30 30. " [63] ,Interrupt Pending Bit[63]" "No interrupt,Interrupt" newline bitfld.long 0x30 29. " [62] ,Interrupt Pending Bit[62]" "No interrupt,Interrupt" bitfld.long 0x30 28. " [61] ,Interrupt Pending Bit[61]" "No interrupt,Interrupt" newline bitfld.long 0x30 27. " [60] ,Interrupt Pending Bit[60]" "No interrupt,Interrupt" bitfld.long 0x30 26. " [59] ,Interrupt Pending Bit[59]" "No interrupt,Interrupt" newline bitfld.long 0x30 25. " [58] ,Interrupt Pending Bit[58]" "No interrupt,Interrupt" bitfld.long 0x30 24. " [57] ,Interrupt Pending Bit[57]" "No interrupt,Interrupt" newline bitfld.long 0x30 23. " [56] ,Interrupt Pending Bit[56]" "No interrupt,Interrupt" bitfld.long 0x30 22. " [55] ,Interrupt Pending Bit[55]" "No interrupt,Interrupt" newline bitfld.long 0x30 21. " [54] ,Interrupt Pending Bit[54]" "No interrupt,Interrupt" bitfld.long 0x30 20. " [53] ,Interrupt Pending Bit[53]" "No interrupt,Interrupt" newline bitfld.long 0x30 19. " [52] ,Interrupt Pending Bit[52]" "No interrupt,Interrupt" bitfld.long 0x30 18. " [51] ,Interrupt Pending Bit[51]" "No interrupt,Interrupt" newline bitfld.long 0x30 17. " [50] ,Interrupt Pending Bit[50]" "No interrupt,Interrupt" bitfld.long 0x30 16. " [49] ,Interrupt Pending Bit[49]" "No interrupt,Interrupt" newline bitfld.long 0x30 15. " [48] ,Interrupt Pending Bit[48]" "No interrupt,Interrupt" bitfld.long 0x30 14. " [47] ,Interrupt Pending Bit[47]" "No interrupt,Interrupt" newline bitfld.long 0x30 13. " [46] ,Interrupt Pending Bit[46]" "No interrupt,Interrupt" bitfld.long 0x30 12. " [45] ,Interrupt Pending Bit[45]" "No interrupt,Interrupt" newline bitfld.long 0x30 11. " [44] ,Interrupt Pending Bit[44]" "No interrupt,Interrupt" bitfld.long 0x30 10. " [43] ,Interrupt Pending Bit[43]" "No interrupt,Interrupt" newline bitfld.long 0x30 9. " [42] ,Interrupt Pending Bit[42]" "No interrupt,Interrupt" bitfld.long 0x30 8. " [41] ,Interrupt Pending Bit[41]" "No interrupt,Interrupt" newline bitfld.long 0x30 7. " [40] ,Interrupt Pending Bit[40]" "No interrupt,Interrupt" bitfld.long 0x30 6. " [39] ,Interrupt Pending Bit[39]" "No interrupt,Interrupt" newline bitfld.long 0x30 5. " [38] ,Interrupt Pending Bit[38]" "No interrupt,Interrupt" bitfld.long 0x30 4. " [37] ,Interrupt Pending Bit[37]" "No interrupt,Interrupt" newline bitfld.long 0x30 3. " [36] ,Interrupt Pending Bit[36]" "No interrupt,Interrupt" bitfld.long 0x30 2. " [35] ,Interrupt Pending Bit[35]" "No interrupt,Interrupt" newline bitfld.long 0x30 1. " [34] ,Interrupt Pending Bit[34]" "No interrupt,Interrupt" bitfld.long 0x30 0. " [33] ,Interrupt Pending Bit[33]" "No interrupt,Interrupt" line.long 0x34 "INTPEN56,Interrupt Pending 5-6" bitfld.long 0x34 31. " INTPND[96] ,Interrupt Pending Bit[96]" "No interrupt,Interrupt" bitfld.long 0x34 30. " [95] ,Interrupt Pending Bit[95]" "No interrupt,Interrupt" newline bitfld.long 0x34 29. " [94] ,Interrupt Pending Bit[94]" "No interrupt,Interrupt" bitfld.long 0x34 28. " [93] ,Interrupt Pending Bit[93]" "No interrupt,Interrupt" newline bitfld.long 0x34 27. " [92] ,Interrupt Pending Bit[92]" "No interrupt,Interrupt" bitfld.long 0x34 26. " [91] ,Interrupt Pending Bit[91]" "No interrupt,Interrupt" newline bitfld.long 0x34 25. " [90] ,Interrupt Pending Bit[90]" "No interrupt,Interrupt" bitfld.long 0x34 24. " [89] ,Interrupt Pending Bit[89]" "No interrupt,Interrupt" newline bitfld.long 0x34 23. " [88] ,Interrupt Pending Bit[88]" "No interrupt,Interrupt" bitfld.long 0x34 22. " [87] ,Interrupt Pending Bit[87]" "No interrupt,Interrupt" newline bitfld.long 0x34 21. " [86] ,Interrupt Pending Bit[86]" "No interrupt,Interrupt" bitfld.long 0x34 20. " [85] ,Interrupt Pending Bit[85]" "No interrupt,Interrupt" newline bitfld.long 0x34 19. " [84] ,Interrupt Pending Bit[84]" "No interrupt,Interrupt" bitfld.long 0x34 18. " [83] ,Interrupt Pending Bit[83]" "No interrupt,Interrupt" newline bitfld.long 0x34 17. " [82] ,Interrupt Pending Bit[82]" "No interrupt,Interrupt" bitfld.long 0x34 16. " [81] ,Interrupt Pending Bit[81]" "No interrupt,Interrupt" newline bitfld.long 0x34 15. " [80] ,Interrupt Pending Bit[80]" "No interrupt,Interrupt" bitfld.long 0x34 14. " [79] ,Interrupt Pending Bit[79]" "No interrupt,Interrupt" newline bitfld.long 0x34 13. " [78] ,Interrupt Pending Bit[78]" "No interrupt,Interrupt" bitfld.long 0x34 12. " [77] ,Interrupt Pending Bit[77]" "No interrupt,Interrupt" newline bitfld.long 0x34 11. " [76] ,Interrupt Pending Bit[76]" "No interrupt,Interrupt" bitfld.long 0x34 10. " [75] ,Interrupt Pending Bit[75]" "No interrupt,Interrupt" newline bitfld.long 0x34 9. " [74] ,Interrupt Pending Bit[74]" "No interrupt,Interrupt" bitfld.long 0x34 8. " [73] ,Interrupt Pending Bit[73]" "No interrupt,Interrupt" newline bitfld.long 0x34 7. " [72] ,Interrupt Pending Bit[72]" "No interrupt,Interrupt" bitfld.long 0x34 6. " [71] ,Interrupt Pending Bit[71]" "No interrupt,Interrupt" newline bitfld.long 0x34 5. " [70] ,Interrupt Pending Bit[70]" "No interrupt,Interrupt" bitfld.long 0x34 4. " [69] ,Interrupt Pending Bit[69]" "No interrupt,Interrupt" newline bitfld.long 0x34 3. " [68] ,Interrupt Pending Bit[68]" "No interrupt,Interrupt" bitfld.long 0x34 2. " [67] ,Interrupt Pending Bit[67]" "No interrupt,Interrupt" newline bitfld.long 0x34 1. " [66] ,Interrupt Pending Bit[66]" "No interrupt,Interrupt" bitfld.long 0x34 0. " [65] ,Interrupt Pending Bit[65]" "No interrupt,Interrupt" line.long 0x38 "INTPEN78,Interrupt Pending 7-8" bitfld.long 0x38 31. " INTPND[128] ,Interrupt Pending Bit[128]" "No interrupt,Interrupt" bitfld.long 0x38 30. " [127] ,Interrupt Pending Bit[127]" "No interrupt,Interrupt" newline bitfld.long 0x38 29. " [126] ,Interrupt Pending Bit[126]" "No interrupt,Interrupt" bitfld.long 0x38 28. " [125] ,Interrupt Pending Bit[125]" "No interrupt,Interrupt" newline bitfld.long 0x38 27. " [124] ,Interrupt Pending Bit[124]" "No interrupt,Interrupt" bitfld.long 0x38 26. " [123] ,Interrupt Pending Bit[123]" "No interrupt,Interrupt" newline bitfld.long 0x38 25. " [122] ,Interrupt Pending Bit[122]" "No interrupt,Interrupt" bitfld.long 0x38 24. " [121] ,Interrupt Pending Bit[121]" "No interrupt,Interrupt" newline bitfld.long 0x38 23. " [120] ,Interrupt Pending Bit[120]" "No interrupt,Interrupt" bitfld.long 0x38 22. " [119] ,Interrupt Pending Bit[119]" "No interrupt,Interrupt" newline bitfld.long 0x38 21. " [118] ,Interrupt Pending Bit[118]" "No interrupt,Interrupt" bitfld.long 0x38 20. " [117] ,Interrupt Pending Bit[117]" "No interrupt,Interrupt" newline bitfld.long 0x38 19. " [116] ,Interrupt Pending Bit[116]" "No interrupt,Interrupt" bitfld.long 0x38 18. " [115] ,Interrupt Pending Bit[115]" "No interrupt,Interrupt" newline bitfld.long 0x38 17. " [114] ,Interrupt Pending Bit[114]" "No interrupt,Interrupt" bitfld.long 0x38 16. " [113] ,Interrupt Pending Bit[113]" "No interrupt,Interrupt" newline bitfld.long 0x38 15. " [112] ,Interrupt Pending Bit[112]" "No interrupt,Interrupt" bitfld.long 0x38 14. " [111] ,Interrupt Pending Bit[111]" "No interrupt,Interrupt" newline bitfld.long 0x38 13. " [110] ,Interrupt Pending Bit[110]" "No interrupt,Interrupt" bitfld.long 0x38 12. " [109] ,Interrupt Pending Bit[109]" "No interrupt,Interrupt" newline bitfld.long 0x38 11. " [108] ,Interrupt Pending Bit[108]" "No interrupt,Interrupt" bitfld.long 0x38 10. " [107] ,Interrupt Pending Bit[107]" "No interrupt,Interrupt" newline bitfld.long 0x38 9. " [106] ,Interrupt Pending Bit[106]" "No interrupt,Interrupt" bitfld.long 0x38 8. " [105] ,Interrupt Pending Bit[105]" "No interrupt,Interrupt" newline bitfld.long 0x38 7. " [104] ,Interrupt Pending Bit[104]" "No interrupt,Interrupt" bitfld.long 0x38 6. " [103] ,Interrupt Pending Bit[103]" "No interrupt,Interrupt" newline bitfld.long 0x38 5. " [102] ,Interrupt Pending Bit[102]" "No interrupt,Interrupt" bitfld.long 0x38 4. " [101] ,Interrupt Pending Bit[101]" "No interrupt,Interrupt" newline bitfld.long 0x38 3. " [100] ,Interrupt Pending Bit[100]" "No interrupt,Interrupt" bitfld.long 0x38 2. " [99] ,Interrupt Pending Bit[99]" "No interrupt,Interrupt" newline bitfld.long 0x38 1. " [98] ,Interrupt Pending Bit[98]" "No interrupt,Interrupt" bitfld.long 0x38 0. " [97] ,Interrupt Pending Bit[97]" "No interrupt,Interrupt" line.long 0x3C "MVAL,Message Valid X" bitfld.long 0x3C 14.--15. " MSGVALREG8 ,Message Valid Register 8" "0,1,2,3" bitfld.long 0x3C 12.--13. " [7] ,Message Valid Register 7" "0,1,2,3" bitfld.long 0x3C 10.--11. " [6] ,Message Valid Register 6" "0,1,2,3" bitfld.long 0x3C 8.--9. " [5] ,Message Valid Register 5" "0,1,2,3" newline bitfld.long 0x3C 6.--7. " [4] ,Message Valid Register 4" "0,1,2,3" bitfld.long 0x3C 4.--5. " [3] ,Message Valid Register 3" "0,1,2,3" bitfld.long 0x3C 2.--3. " [2] ,Message Valid Register 2" "0,1,2,3" bitfld.long 0x3C 0.--1. " [1] ,Message Valid Register 1" "0,1,2,3" line.long 0x40 "MVAL12,Message Valid 1-2" bitfld.long 0x40 31. " MSGVAL[32] ,Message Valid Bit[32]" "Ignored,Configured" bitfld.long 0x40 30. " [31] ,Message Valid Bit[31]" "Ignored,Configured" newline bitfld.long 0x40 29. " [30] ,Message Valid Bit[30]" "Ignored,Configured" bitfld.long 0x40 28. " [29] ,Message Valid Bit[29]" "Ignored,Configured" newline bitfld.long 0x40 27. " [28] ,Message Valid Bit[28]" "Ignored,Configured" bitfld.long 0x40 26. " [27] ,Message Valid Bit[27]" "Ignored,Configured" newline bitfld.long 0x40 25. " [26] ,Message Valid Bit[26]" "Ignored,Configured" bitfld.long 0x40 24. " [25] ,Message Valid Bit[25]" "Ignored,Configured" newline bitfld.long 0x40 23. " [24] ,Message Valid Bit[24]" "Ignored,Configured" bitfld.long 0x40 22. " [23] ,Message Valid Bit[23]" "Ignored,Configured" newline bitfld.long 0x40 21. " [22] ,Message Valid Bit[22]" "Ignored,Configured" bitfld.long 0x40 20. " [21] ,Message Valid Bit[21]" "Ignored,Configured" newline bitfld.long 0x40 19. " [20] ,Message Valid Bit[20]" "Ignored,Configured" bitfld.long 0x40 18. " [19] ,Message Valid Bit[19]" "Ignored,Configured" newline bitfld.long 0x40 17. " [18] ,Message Valid Bit[18]" "Ignored,Configured" bitfld.long 0x40 16. " [17] ,Message Valid Bit[17]" "Ignored,Configured" newline bitfld.long 0x40 15. " [16] ,Message Valid Bit[16]" "Ignored,Configured" bitfld.long 0x40 14. " [15] ,Message Valid Bit[15]" "Ignored,Configured" newline bitfld.long 0x40 13. " [14] ,Message Valid Bit[14]" "Ignored,Configured" bitfld.long 0x40 12. " [13] ,Message Valid Bit[13]" "Ignored,Configured" newline bitfld.long 0x40 11. " [12] ,Message Valid Bit[12]" "Ignored,Configured" bitfld.long 0x40 10. " [11] ,Message Valid Bit[11]" "Ignored,Configured" newline bitfld.long 0x40 9. " [10] ,Message Valid Bit[10]" "Ignored,Configured" bitfld.long 0x40 8. " [9] ,Message Valid Bit[9]" "Ignored,Configured" newline bitfld.long 0x40 7. " [8] ,Message Valid Bit[8]" "Ignored,Configured" bitfld.long 0x40 6. " [7] ,Message Valid Bit[7]" "Ignored,Configured" newline bitfld.long 0x40 5. " [6] ,Message Valid Bit[6]" "Ignored,Configured" bitfld.long 0x40 4. " [5] ,Message Valid Bit[5]" "Ignored,Configured" newline bitfld.long 0x40 3. " [4] ,Message Valid Bit[4]" "Ignored,Configured" bitfld.long 0x40 2. " [3] ,Message Valid Bit[3]" "Ignored,Configured" newline bitfld.long 0x40 1. " [2] ,Message Valid Bit[2]" "Ignored,Configured" bitfld.long 0x40 0. " [1] ,Message Valid Bit[1]" "Ignored,Configured" line.long 0x44 "MVAL34,Message Valid 3-4" bitfld.long 0x44 31. " MSGVAl[64] ,Message Valid Bit[64]" "Ignored,Configured" bitfld.long 0x44 30. " [63] ,Message Valid Bit[63]" "Ignored,Configured" newline bitfld.long 0x44 29. " [62] ,Message Valid Bit[62]" "Ignored,Configured" bitfld.long 0x44 28. " [61] ,Message Valid Bit[61]" "Ignored,Configured" newline bitfld.long 0x44 27. " [60] ,Message Valid Bit[60]" "Ignored,Configured" bitfld.long 0x44 26. " [59] ,Message Valid Bit[59]" "Ignored,Configured" newline bitfld.long 0x44 25. " [58] ,Message Valid Bit[58]" "Ignored,Configured" bitfld.long 0x44 24. " [57] ,Message Valid Bit[57]" "Ignored,Configured" newline bitfld.long 0x44 23. " [56] ,Message Valid Bit[56]" "Ignored,Configured" bitfld.long 0x44 22. " [55] ,Message Valid Bit[55]" "Ignored,Configured" newline bitfld.long 0x44 21. " [54] ,Message Valid Bit[54]" "Ignored,Configured" bitfld.long 0x44 20. " [53] ,Message Valid Bit[53]" "Ignored,Configured" newline bitfld.long 0x44 19. " [52] ,Message Valid Bit[52]" "Ignored,Configured" bitfld.long 0x44 18. " [51] ,Message Valid Bit[51]" "Ignored,Configured" newline bitfld.long 0x44 17. " [50] ,Message Valid Bit[50]" "Ignored,Configured" bitfld.long 0x44 16. " [49] ,Message Valid Bit[49]" "Ignored,Configured" newline bitfld.long 0x44 15. " [48] ,Message Valid Bit[48]" "Ignored,Configured" bitfld.long 0x44 14. " [47] ,Message Valid Bit[47]" "Ignored,Configured" newline bitfld.long 0x44 13. " [46] ,Message Valid Bit[46]" "Ignored,Configured" bitfld.long 0x44 12. " [45] ,Message Valid Bit[45]" "Ignored,Configured" newline bitfld.long 0x44 11. " [44] ,Message Valid Bit[44]" "Ignored,Configured" bitfld.long 0x44 10. " [43] ,Message Valid Bit[43]" "Ignored,Configured" newline bitfld.long 0x44 9. " [42] ,Message Valid Bit[42]" "Ignored,Configured" bitfld.long 0x44 8. " [41] ,Message Valid Bit[41]" "Ignored,Configured" newline bitfld.long 0x44 7. " [40] ,Message Valid Bit[40]" "Ignored,Configured" bitfld.long 0x44 6. " [39] ,Message Valid Bit[39]" "Ignored,Configured" newline bitfld.long 0x44 5. " [38] ,Message Valid Bit[38]" "Ignored,Configured" bitfld.long 0x44 4. " [37] ,Message Valid Bit[37]" "Ignored,Configured" newline bitfld.long 0x44 3. " [36] ,Message Valid Bit[36]" "Ignored,Configured" bitfld.long 0x44 2. " [35] ,Message Valid Bit[35]" "Ignored,Configured" newline bitfld.long 0x44 1. " [34] ,Message Valid Bit[34]" "Ignored,Configured" bitfld.long 0x44 0. " [33] ,Message Valid Bit[33]" "Ignored,Configured" line.long 0x48 "MVAL56,Message Valid 5-6" bitfld.long 0x48 31. " MSGVAl[96] ,Message Valid Bit[96]" "Ignored,Configured" bitfld.long 0x48 30. " [95] ,Message Valid Bit[95]" "Ignored,Configured" newline bitfld.long 0x48 29. " [94] ,Message Valid Bit[94]" "Ignored,Configured" bitfld.long 0x48 28. " [93] ,Message Valid Bit[93]" "Ignored,Configured" newline bitfld.long 0x48 27. " [92] ,Message Valid Bit[92]" "Ignored,Configured" bitfld.long 0x48 26. " [91] ,Message Valid Bit[91]" "Ignored,Configured" newline bitfld.long 0x48 25. " [90] ,Message Valid Bit[90]" "Ignored,Configured" bitfld.long 0x48 24. " [89] ,Message Valid Bit[89]" "Ignored,Configured" newline bitfld.long 0x48 23. " [88] ,Message Valid Bit[88]" "Ignored,Configured" bitfld.long 0x48 22. " [87] ,Message Valid Bit[87]" "Ignored,Configured" newline bitfld.long 0x48 21. " [86] ,Message Valid Bit[86]" "Ignored,Configured" bitfld.long 0x48 20. " [85] ,Message Valid Bit[85]" "Ignored,Configured" newline bitfld.long 0x48 19. " [84] ,Message Valid Bit[84]" "Ignored,Configured" bitfld.long 0x48 18. " [83] ,Message Valid Bit[83]" "Ignored,Configured" newline bitfld.long 0x48 17. " [82] ,Message Valid Bit[82]" "Ignored,Configured" bitfld.long 0x48 16. " [81] ,Message Valid Bit[81]" "Ignored,Configured" newline bitfld.long 0x48 15. " [80] ,Message Valid Bit[80]" "Ignored,Configured" bitfld.long 0x48 14. " [79] ,Message Valid Bit[79]" "Ignored,Configured" newline bitfld.long 0x48 13. " [78] ,Message Valid Bit[78]" "Ignored,Configured" bitfld.long 0x48 12. " [77] ,Message Valid Bit[77]" "Ignored,Configured" newline bitfld.long 0x48 11. " [76] ,Message Valid Bit[76]" "Ignored,Configured" bitfld.long 0x48 10. " [75] ,Message Valid Bit[75]" "Ignored,Configured" newline bitfld.long 0x48 9. " [74] ,Message Valid Bit[74]" "Ignored,Configured" bitfld.long 0x48 8. " [73] ,Message Valid Bit[73]" "Ignored,Configured" newline bitfld.long 0x48 7. " [72] ,Message Valid Bit[72]" "Ignored,Configured" bitfld.long 0x48 6. " [71] ,Message Valid Bit[71]" "Ignored,Configured" newline bitfld.long 0x48 5. " [70] ,Message Valid Bit[70]" "Ignored,Configured" bitfld.long 0x48 4. " [69] ,Message Valid Bit[69]" "Ignored,Configured" newline bitfld.long 0x48 3. " [68] ,Message Valid Bit[68]" "Ignored,Configured" bitfld.long 0x48 2. " [67] ,Message Valid Bit[67]" "Ignored,Configured" newline bitfld.long 0x48 1. " [66] ,Message Valid Bit[66]" "Ignored,Configured" bitfld.long 0x48 0. " [65] ,Message Valid Bit[65]" "Ignored,Configured" line.long 0x4C "MVAL78,Message Valid 7-8" bitfld.long 0x4C 31. " MSGVAl[128] ,Message Valid Bit[128]" "Ignored,Configured" bitfld.long 0x4C 30. " [127] ,Message Valid Bit[127]" "Ignored,Configured" newline bitfld.long 0x4C 29. " [126] ,Message Valid Bit[126]" "Ignored,Configured" bitfld.long 0x4C 28. " [125] ,Message Valid Bit[125]" "Ignored,Configured" newline bitfld.long 0x4C 27. " [124] ,Message Valid Bit[124]" "Ignored,Configured" bitfld.long 0x4C 26. " [123] ,Message Valid Bit[123]" "Ignored,Configured" newline bitfld.long 0x4C 25. " [122] ,Message Valid Bit[122]" "Ignored,Configured" bitfld.long 0x4C 24. " [121] ,Message Valid Bit[121]" "Ignored,Configured" newline bitfld.long 0x4C 23. " [120] ,Message Valid Bit[120]" "Ignored,Configured" bitfld.long 0x4C 22. " [119] ,Message Valid Bit[119]" "Ignored,Configured" newline bitfld.long 0x4C 21. " [118] ,Message Valid Bit[118]" "Ignored,Configured" bitfld.long 0x4C 20. " [117] ,Message Valid Bit[117]" "Ignored,Configured" newline bitfld.long 0x4C 19. " [116] ,Message Valid Bit[116]" "Ignored,Configured" bitfld.long 0x4C 18. " [115] ,Message Valid Bit[115]" "Ignored,Configured" newline bitfld.long 0x4C 17. " [114] ,Message Valid Bit[114]" "Ignored,Configured" bitfld.long 0x4C 16. " [113] ,Message Valid Bit[113]" "Ignored,Configured" newline bitfld.long 0x4C 15. " [112] ,Message Valid Bit[112]" "Ignored,Configured" bitfld.long 0x4C 14. " [111] ,Message Valid Bit[111]" "Ignored,Configured" newline bitfld.long 0x4C 13. " [110] ,Message Valid Bit[110]" "Ignored,Configured" bitfld.long 0x4C 12. " [109] ,Message Valid Bit[109]" "Ignored,Configured" newline bitfld.long 0x4C 11. " [108] ,Message Valid Bit[108]" "Ignored,Configured" bitfld.long 0x4C 10. " [107] ,Message Valid Bit[107]" "Ignored,Configured" newline bitfld.long 0x4C 9. " [106] ,Message Valid Bit[106]" "Ignored,Configured" bitfld.long 0x4C 8. " [105] ,Message Valid Bit[105]" "Ignored,Configured" newline bitfld.long 0x4C 7. " [104] ,Message Valid Bit[104]" "Ignored,Configured" bitfld.long 0x4C 6. " [103] ,Message Valid Bit[103]" "Ignored,Configured" newline bitfld.long 0x4C 5. " [102] ,Message Valid Bit[102]" "Ignored,Configured" bitfld.long 0x4C 4. " [101] ,Message Valid Bit[101]" "Ignored,Configured" newline bitfld.long 0x4C 3. " [100] ,Message Valid Bit[100]" "Ignored,Configured" bitfld.long 0x4C 2. " [99] ,Message Valid Bit[99]" "Ignored,Configured" newline bitfld.long 0x4C 1. " [98] ,Message Valid Bit[98]" "Ignored,Configured" bitfld.long 0x4C 0. " [97] ,Message Valid Bit[97]" "Ignored,Configured" group.long 0xD8++0x0F line.long 0x00 "INTPMX12,Interrupt Multiplexer 1-2" bitfld.long 0x00 31. " INTPNDMUX[32] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[32]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 30. " [31] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[31]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x00 29. " [30] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[30]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 28. " [29] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[29]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x00 27. " [28] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[28]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 26. " [27] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[27]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x00 25. " [26] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[26]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 24. " [25] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[25]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x00 23. " [24] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[24]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 22. " [23] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[23]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x00 21. " [22] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[22]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 20. " [21] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[21]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x00 19. " [20] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[20]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 18. " [19] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[19]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x00 17. " [18] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[18]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 16. " [17] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[17]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x00 15. " [16] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[16]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 14. " [15] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[15]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x00 13. " [14] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[14]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 12. " [13] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[13]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x00 11. " [12] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[12]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 10. " [11] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[11]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x00 9. " [10] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[10]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 8. " [9] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[9]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x00 7. " [8] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[8]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 6. " [7] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[7]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x00 5. " [6] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[6]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 4. " [5] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[5]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x00 3. " [4] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[4]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 2. " [3] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[3]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x00 1. " [2] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[2]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 0. " [1] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[1]" "DCAN0INT,DCAN1INT" line.long 0x04 "INTPMX34,Interrupt Multiplexer 3-4" bitfld.long 0x04 31. " INTPNDMUX[64] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[64]" "DCAN0INT,DCAN1INT" bitfld.long 0x04 30. " [63] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[63]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x04 29. " [62] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[62]" "DCAN0INT,DCAN1INT" bitfld.long 0x04 28. " [61] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[61]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x04 27. " [60] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[60]" "DCAN0INT,DCAN1INT" bitfld.long 0x04 26. " [59] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[59]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x04 25. " [58] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[58]" "DCAN0INT,DCAN1INT" bitfld.long 0x04 24. " [57] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[57]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x04 23. " [56] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[56]" "DCAN0INT,DCAN1INT" bitfld.long 0x04 22. " [55] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[55]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x04 21. " [54] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[54]" "DCAN0INT,DCAN1INT" bitfld.long 0x04 20. " [53] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[53]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x04 19. " [52] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[52]" "DCAN0INT,DCAN1INT" bitfld.long 0x04 18. " [51] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[51]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x04 17. " [50] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[50]" "DCAN0INT,DCAN1INT" bitfld.long 0x04 16. " [49] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[49]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x04 15. " [48] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[48]" "DCAN0INT,DCAN1INT" bitfld.long 0x04 14. " [47] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[47]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x04 13. " [46] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[46]" "DCAN0INT,DCAN1INT" bitfld.long 0x04 12. " [45] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[45]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x04 11. " [44] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[44]" "DCAN0INT,DCAN1INT" bitfld.long 0x04 10. " [43] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[43]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x04 9. " [42] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[42]" "DCAN0INT,DCAN1INT" bitfld.long 0x04 8. " [41] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[41]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x04 7. " [40] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[40]" "DCAN0INT,DCAN1INT" bitfld.long 0x04 6. " [39] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[39]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x04 5. " [38] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[38]" "DCAN0INT,DCAN1INT" bitfld.long 0x04 4. " [37] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[37]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x04 3. " [36] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[36]" "DCAN0INT,DCAN1INT" bitfld.long 0x04 2. " [35] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[35]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x04 1. " [34] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[34]" "DCAN0INT,DCAN1INT" bitfld.long 0x04 0. " [33] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[33]" "DCAN0INT,DCAN1INT" line.long 0x08 "INTPMX56,Interrupt Multiplexer 5-6" bitfld.long 0x08 31. " INTPNDMUX[96] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[96]" "DCAN0INT,DCAN1INT" bitfld.long 0x08 30. " [95] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[95]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x08 29. " [94] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[94]" "DCAN0INT,DCAN1INT" bitfld.long 0x08 28. " [93] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[93]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x08 27. " [92] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[92]" "DCAN0INT,DCAN1INT" bitfld.long 0x08 26. " [91] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[91]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x08 25. " [90] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[90]" "DCAN0INT,DCAN1INT" bitfld.long 0x08 24. " [89] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[89]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x08 23. " [88] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[88]" "DCAN0INT,DCAN1INT" bitfld.long 0x08 22. " [87] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[87]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x08 21. " [86] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[86]" "DCAN0INT,DCAN1INT" bitfld.long 0x08 20. " [85] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[85]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x08 19. " [84] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[84]" "DCAN0INT,DCAN1INT" bitfld.long 0x08 18. " [83] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[83]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x08 17. " [82] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[82]" "DCAN0INT,DCAN1INT" bitfld.long 0x08 16. " [81] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[81]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x08 15. " [80] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[80]" "DCAN0INT,DCAN1INT" bitfld.long 0x08 14. " [79] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[79]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x08 13. " [78] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[78]" "DCAN0INT,DCAN1INT" bitfld.long 0x08 12. " [77] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[77]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x08 11. " [76] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[76]" "DCAN0INT,DCAN1INT" bitfld.long 0x08 10. " [75] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[75]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x08 9. " [74] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[74]" "DCAN0INT,DCAN1INT" bitfld.long 0x08 8. " [73] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[73]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x08 7. " [72] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[72]" "DCAN0INT,DCAN1INT" bitfld.long 0x08 6. " [71] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[71]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x08 5. " [70] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[70]" "DCAN0INT,DCAN1INT" bitfld.long 0x08 4. " [69] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[69]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x08 3. " [68] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[68]" "DCAN0INT,DCAN1INT" bitfld.long 0x08 2. " [67] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[67]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x08 1. " [66] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[66]" "DCAN0INT,DCAN1INT" bitfld.long 0x08 0. " [65] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[65]" "DCAN0INT,DCAN1INT" line.long 0x0C "INTPMX78,Interrupt Multiplexer 7-8" bitfld.long 0x0C 31. " INTPNDMUX[128] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[128]" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 30. " [127] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[127]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x0C 29. " [126] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[126]" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 28. " [125] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[125]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x0C 27. " [124] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[124]" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 26. " [123] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[123]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x0C 25. " [122] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[122]" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 24. " [121] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[121]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x0C 23. " [120] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[120]" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 22. " [119] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[119]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x0C 21. " [118] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[118]" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 20. " [117] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[117]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x0C 19. " [116] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[116]" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 18. " [115] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[115]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x0C 17. " [114] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[114]" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 16. " [113] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[113]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x0C 15. " [112] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[112]" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 14. " [111] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[111]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x0C 13. " [110] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[110]" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 12. " [109] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[109]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x0C 11. " [108] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[108]" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 10. " [107] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[107]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x0C 9. " [106] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[106]" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 8. " [105] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[105]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x0C 7. " [104] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[104]" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 6. " [103] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[103]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x0C 5. " [102] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[102]" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 4. " [101] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[101]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x0C 3. " [100] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[100]" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 2. " [99] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[99]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x0C 1. " [98] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[98]" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 0. " [97] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[97]" "DCAN0INT,DCAN1INT" group.long 0x100++0x3 "IF1" line.long 0x00 "IF1COM,IF1 Command Mask / Command Request Register" bitfld.long 0x00 23. " WR/RD ,Write / Read direction" "Read,Write" newline bitfld.long 0x00 22. " MASK ,Access Mask Bits" "Unchanged,Identifier Mask+MDir+MXtd" newline bitfld.long 0x00 21. " ARB ,Access Arbitration Bits" "Unchanged,Identifier+Dir+Xtd+MSGVAl" newline bitfld.long 0x00 20. " CONTROL ,Access Control Bits" "Unchanged,Control bits" bitfld.long 0x00 19. " CLRINTPND ,Clear Interrupt Pending Bit" "Low,High" newline bitfld.long 0x00 18. " TXRQST/NEWDAT ,Access Transmission Request Bit" "Not requested,Requested" bitfld.long 0x00 17. " DATA_A ,Access Data Bytes 0-3" "Unchanged,Data bytes 0-3" newline bitfld.long 0x00 16. " DATA_B ,Access Data Bytes 4-7" "Unchanged,Data bytes 4-7" bitfld.long 0x00 15. " BUSY ,Busy Flag" "Not busy,Busy" newline sif (!cpuis("TMS570LS0332")&&!cpuis("TMS570LS0432")) bitfld.long 0x00 14. " DMAACTIVE ,Activation of DMA Feature for Subsequent Internal IF1 Update" "No active,Active" newline endif hexmask.long.byte 0x00 0.--7. 1. " MESSAGE_NUMBER ,Message Number" sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS3137-EP") if (((per.l.be(((ad:0xFFF7DC00+0x100+0x08))))&0x40000000)==0x0) group.long (0x100+0x04)++0x07 line.long 0x0 "IF1MASK,IF1 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering" newline bitfld.long 0x00 28. " ID ,Message Identifier bit[10]" "0,1" bitfld.long 0x00 27. ",Message Identifier bit[9]" "0,1" bitfld.long 0x00 26. ",Message Identifier bit[8]" "0,1" bitfld.long 0x00 25. ",Message Identifier bit[7]" "0,1" bitfld.long 0x00 24. ",Message Identifier bit[6]" "0,1" bitfld.long 0x00 23. ",Message Identifier bit[5]" "0,1" bitfld.long 0x00 22. ",Message Identifier bit[4]" "0,1" bitfld.long 0x00 21. ",Message Identifier bit[3]" "0,1" bitfld.long 0x00 20. ",Message Identifier bit[2]" "0,1" bitfld.long 0x00 19. ",Message Identifier bit[1]" "0,1" bitfld.long 0x00 18. ",Message Identifier bit[0]" "0,1" line.long 0x04 "IF1ARB,IF1 Arbitration Register" bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure" bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit" bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit" hexmask.long.word 0x04 18.--28. 1. " ID ,Message Identifier" else group.long (0x100+0x04)++0x07 line.long 0x00 "IF1MASK,IF1 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering" newline bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1" bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1" bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1" bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1" bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1" bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1" bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1" bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1" bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1" bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1" bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1" bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1" bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1" bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1" bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1" bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1" bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1" bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1" bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1" bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1" bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1" bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1" bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1" bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1" bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1" bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1" bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1" bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1" bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1" line.long 0x04 "IF1ARB,IF1 Arbitation Register" bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure" bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit" bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit" hexmask.long 0x04 0.--28. 1. " ID ,Message Identifier" endif else if (((per.l(((ad:0xFFF7DC00+0x100+0x08))))&0x40000000)==0x0) group.long (0x100+0x04)++0x07 line.long 0x0 "IF1MASK,IF1 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering" newline bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1" bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1" bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1" bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1" bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1" bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1" bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1" bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1" bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1" bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1" bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1" line.long 0x04 "IF1ARB,IF1 Arbitation Register" bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure" bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit" bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit" hexmask.long.word 0x04 18.--28. 1. " ID ,Message Identifier" else group.long (0x100+0x04)++0x07 line.long 0x0 "IF1MASK,IF1 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering" newline bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1" bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1" bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1" bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1" bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1" bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1" bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1" bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1" bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1" bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1" bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1" bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1" bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1" bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1" bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1" bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1" bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1" bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1" bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1" bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1" bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1" bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1" bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1" bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1" bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1" bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1" bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1" bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1" bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1" line.long 0x04 "IF1ARB,IF1 Arbitation Register" bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure" bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit" bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit" hexmask.long 0x04 0.--28. 1. " ID ,Message Identifier" endif endif group.long (0x100+0x0C)++0x0B line.long 0x00 "IF1MCTRL,IF1 Message Control Register" bitfld.long 0x00 15. " NEWDAT ,New Data" "No new data,New data" bitfld.long 0x00 14. " MSGLST ,Message Lost" "Not lost,Lost" bitfld.long 0x00 13. " INTPND ,Interrupt Pending" "No interrupt,Interrupt" newline bitfld.long 0x00 12. " UMASK ,Use Acceptance Mask" "Ignored,Masked" bitfld.long 0x00 11. " TXIE ,Transmit Interrupt Enable" "Unchanged,Set" bitfld.long 0x00 10. " RXIE ,Receive Interrupt Enable" "Unchanged,Set" newline bitfld.long 0x00 9. " RMTEN ,Remote Enable" "Disabled,Enabled" bitfld.long 0x00 8. " TXRQST ,Transmit Request" "Not requested,Requested" bitfld.long 0x00 7. " EOB ,End of Block" "Single/Last,Not last" newline bitfld.long 0x00 0.--3. " DLC[3-0] ,Data Length Code" "0 byte,1 bytes,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes" line.long 0x04 "IF1DATA,IF1 Data A Register" hexmask.long.byte 0x04 24.--31. 1. " DATA[3] ,4th data byte of a CAN Data Frame" hexmask.long.byte 0x04 16.--23. 1. " [2] ,3rd data byte of a CAN Data Frame" hexmask.long.byte 0x04 8.--15. 1. " [1] ,2nd data byte of a CAN Data Frame" hexmask.long.byte 0x04 0.--7. 1. " [0] ,1st data byte of a CAN Data Frame" line.long 0x08 "IF1DATB,IF1 Data B Register" hexmask.long.byte 0x08 24.--31. 1. " DATA[7] ,8th data byte of a CAN Data Frame" hexmask.long.byte 0x08 16.--23. 1. " [6] ,7th data byte of a CAN Data Frame" hexmask.long.byte 0x08 8.--15. 1. " [5] ,6th data byte of a CAN Data Frame" hexmask.long.byte 0x08 0.--7. 1. " [4] ,5th data byte of a CAN Data Frame" group.long 0x120++0x3 "IF2" line.long 0x00 "IF2COM,IF2 Command Mask / Command Request Register" bitfld.long 0x00 23. " WR/RD ,Write / Read direction" "Read,Write" newline bitfld.long 0x00 22. " MASK ,Access Mask Bits" "Unchanged,Identifier Mask+MDir+MXtd" newline bitfld.long 0x00 21. " ARB ,Access Arbitration Bits" "Unchanged,Identifier+Dir+Xtd+MSGVAl" newline bitfld.long 0x00 20. " CONTROL ,Access Control Bits" "Unchanged,Control bits" bitfld.long 0x00 19. " CLRINTPND ,Clear Interrupt Pending Bit" "Low,High" newline bitfld.long 0x00 18. " TXRQST/NEWDAT ,Access Transmission Request Bit" "Not requested,Requested" bitfld.long 0x00 17. " DATA_A ,Access Data Bytes 0-3" "Unchanged,Data bytes 0-3" newline bitfld.long 0x00 16. " DATA_B ,Access Data Bytes 4-7" "Unchanged,Data bytes 4-7" bitfld.long 0x00 15. " BUSY ,Busy Flag" "Not busy,Busy" newline sif (!cpuis("TMS570LS0332")&&!cpuis("TMS570LS0432")) bitfld.long 0x00 14. " DMAACTIVE ,Activation of DMA Feature for Subsequent Internal IF1 Update" "No active,Active" newline endif hexmask.long.byte 0x00 0.--7. 1. " MESSAGE_NUMBER ,Message Number" sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS3137-EP") if (((per.l.be(((ad:0xFFF7DC00+0x120+0x08))))&0x40000000)==0x0) group.long (0x120+0x04)++0x07 line.long 0x0 "IF2MASK,IF2 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering" newline bitfld.long 0x00 28. " ID ,Message Identifier bit[10]" "0,1" bitfld.long 0x00 27. ",Message Identifier bit[9]" "0,1" bitfld.long 0x00 26. ",Message Identifier bit[8]" "0,1" bitfld.long 0x00 25. ",Message Identifier bit[7]" "0,1" bitfld.long 0x00 24. ",Message Identifier bit[6]" "0,1" bitfld.long 0x00 23. ",Message Identifier bit[5]" "0,1" bitfld.long 0x00 22. ",Message Identifier bit[4]" "0,1" bitfld.long 0x00 21. ",Message Identifier bit[3]" "0,1" bitfld.long 0x00 20. ",Message Identifier bit[2]" "0,1" bitfld.long 0x00 19. ",Message Identifier bit[1]" "0,1" bitfld.long 0x00 18. ",Message Identifier bit[0]" "0,1" line.long 0x04 "IF2ARB,IF2 Arbitration Register" bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure" bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit" bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit" hexmask.long.word 0x04 18.--28. 1. " ID ,Message Identifier" else group.long (0x120+0x04)++0x07 line.long 0x00 "IF2MASK,IF2 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering" newline bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1" bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1" bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1" bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1" bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1" bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1" bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1" bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1" bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1" bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1" bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1" bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1" bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1" bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1" bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1" bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1" bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1" bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1" bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1" bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1" bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1" bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1" bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1" bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1" bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1" bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1" bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1" bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1" bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1" line.long 0x04 "IF2ARB,IF2 Arbitation Register" bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure" bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit" bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit" hexmask.long 0x04 0.--28. 1. " ID ,Message Identifier" endif else if (((per.l(((ad:0xFFF7DC00+0x120+0x08))))&0x40000000)==0x0) group.long (0x120+0x04)++0x07 line.long 0x0 "IF2MASK,IF2 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering" newline bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1" bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1" bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1" bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1" bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1" bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1" bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1" bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1" bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1" bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1" bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1" line.long 0x04 "IF2ARB,IF2 Arbitation Register" bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure" bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit" bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit" hexmask.long.word 0x04 18.--28. 1. " ID ,Message Identifier" else group.long (0x120+0x04)++0x07 line.long 0x0 "IF2MASK,IF2 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering" newline bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1" bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1" bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1" bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1" bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1" bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1" bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1" bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1" bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1" bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1" bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1" bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1" bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1" bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1" bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1" bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1" bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1" bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1" bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1" bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1" bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1" bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1" bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1" bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1" bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1" bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1" bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1" bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1" bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1" line.long 0x04 "IF2ARB,IF2 Arbitation Register" bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure" bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit" bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit" hexmask.long 0x04 0.--28. 1. " ID ,Message Identifier" endif endif group.long (0x120+0x0C)++0x0B line.long 0x00 "IF2MCTRL,IF2 Message Control Register" bitfld.long 0x00 15. " NEWDAT ,New Data" "No new data,New data" bitfld.long 0x00 14. " MSGLST ,Message Lost" "Not lost,Lost" bitfld.long 0x00 13. " INTPND ,Interrupt Pending" "No interrupt,Interrupt" newline bitfld.long 0x00 12. " UMASK ,Use Acceptance Mask" "Ignored,Masked" bitfld.long 0x00 11. " TXIE ,Transmit Interrupt Enable" "Unchanged,Set" bitfld.long 0x00 10. " RXIE ,Receive Interrupt Enable" "Unchanged,Set" newline bitfld.long 0x00 9. " RMTEN ,Remote Enable" "Disabled,Enabled" bitfld.long 0x00 8. " TXRQST ,Transmit Request" "Not requested,Requested" bitfld.long 0x00 7. " EOB ,End of Block" "Single/Last,Not last" newline bitfld.long 0x00 0.--3. " DLC[3-0] ,Data Length Code" "0 byte,1 bytes,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes" line.long 0x04 "IF2DATA,IF2 Data A Register" hexmask.long.byte 0x04 24.--31. 1. " DATA[3] ,4th data byte of a CAN Data Frame" hexmask.long.byte 0x04 16.--23. 1. " [2] ,3rd data byte of a CAN Data Frame" hexmask.long.byte 0x04 8.--15. 1. " [1] ,2nd data byte of a CAN Data Frame" hexmask.long.byte 0x04 0.--7. 1. " [0] ,1st data byte of a CAN Data Frame" line.long 0x08 "IF2DATB,IF2 Data B Register" hexmask.long.byte 0x08 24.--31. 1. " DATA[7] ,8th data byte of a CAN Data Frame" hexmask.long.byte 0x08 16.--23. 1. " [6] ,7th data byte of a CAN Data Frame" hexmask.long.byte 0x08 8.--15. 1. " [5] ,6th data byte of a CAN Data Frame" hexmask.long.byte 0x08 0.--7. 1. " [4] ,5th data byte of a CAN Data Frame" group.long 0x140++0x3 "IF3" line.long 0x00 "IF3OB,IF3 Observation Register" sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS21*")||cpuis("TMS570LS31*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")) rbitfld.long 0x00 15. " IF3UPD ,IF3 Updata Data" "Not loaded,Loaded" rbitfld.long 0x00 12. " IF3SDB ,IF3 Status of Data B Read Access" "Low,High" rbitfld.long 0x00 11. " IF3SDA ,IF3 Status of Data A Read Access" "Low,High" newline rbitfld.long 0x00 10. " IF3SC ,IF3 Status of Control Bits Read Access" "Low,High" rbitfld.long 0x00 9. " IF3SA ,IF3 Status of Arbitration Data Read Access" "Low,High" rbitfld.long 0x00 8. " IF3SM ,IF3 Status of Mask Data Read Access" "Low,High" else bitfld.long 0x00 15. " IF3UPD ,IF3 Updata Data" "Not loaded,Loaded" bitfld.long 0x00 12. " IF3SDB ,IF3 Status of Data B Read Access" "Low,High" bitfld.long 0x00 11. " IF3SDA ,IF3 Status of Data A Read Access" "Low,High" newline bitfld.long 0x00 10. " IF3SC ,IF3 Status of Control Bits Read Access" "Low,High" bitfld.long 0x00 9. " IF3SA ,IF3 Status of Arbitration Data Read Access" "Low,High" bitfld.long 0x00 8. " IF3SM ,IF3 Status of Mask Data Read Access" "Low,High" endif newline bitfld.long 0x00 4. " DATA_B ,Data B Read Observation" "Not read,Read" bitfld.long 0x00 3. " DATA_A ,Data A Read Observation" "Not read,Read" bitfld.long 0x00 2. " CTRL ,Ctrl Read Observation" "Not read,Read" newline bitfld.long 0x00 1. " ARB ,Arbitration Data Read Observation" "Not read,Read" bitfld.long 0x00 0. " MASK ,Mask Data Read Observation" "Not read,Read" sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*") if (((per.l.be((ad:0xFFF7DC00+0x148)))&0x40000000)==0x0) rgroup.long 0x144++0x07 line.long 0x00 "IF3MASK,IF3 Mask Register" bitfld.long 0x00 31. " MXtd ,Mask Extended Identifier" "No effect,Filtering" bitfld.long 0x00 30. " MDir ,Mask Message Direction" "No effect,Filtering" newline bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1" bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1" bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1" bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1" bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1" bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1" bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1" bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1" bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1" bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1" bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1" line.long 0x04 "IF3ARB,IF3 Arbitation Register" bitfld.long 0x04 31. " MSGVAl ,Message Valid" "Ignored,Configured" bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit" bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit" newline hexmask.long.word 0x04 18.--28. 1. " ID ,Message Identifier" else rgroup.long 0x144++0x07 line.long 0x0 "IF3MASK,IF3 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering" newline bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1" bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1" bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1" bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1" bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1" bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1" bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1" bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1" bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1" bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1" bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1" bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1" bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1" bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1" bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1" bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1" bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1" bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1" bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1" bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1" bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1" bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1" bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1" bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1" bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1" bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1" bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1" bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1" bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1" line.long 0x04 "IF3ARB,IF3 Arbitation Register" bitfld.long 0x04 31. " MSGVAl ,Message Valid" "Ignored,Configured" bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit" bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit" newline hexmask.long 0x04 0.--28. 1. " ID ,Message Identifier" endif else if (((per.l((ad:0xFFF7DC00+0x148)))&0x40000000)==0x0) rgroup.long 0x144++0x07 line.long 0x0 "IF3MASK,IF3 Mask Register" bitfld.long 0x00 31. " MXtd ,Mask Extended Identifier" "No effect,Filtering" bitfld.long 0x00 30. " MDir ,Mask Message Direction" "No effect,Filtering" newline bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1" bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1" bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1" bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1" bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1" bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1" bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1" bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1" bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1" bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1" bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1" line.long 0x04 "IF3ARB,IF3 Arbitation Register" bitfld.long 0x04 31. " MSGVAl ,Message Valid" "Ignored,Configured" bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit" bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit" newline hexmask.long.word 0x04 18.--28. 1. " ID ,Message Identifier" else rgroup.long 0x144++0x07 line.long 0x0 "IF3MASK,IF3 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering" newline bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1" bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1" bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1" bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1" bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1" bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1" bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1" bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1" bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1" bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1" bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1" bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1" bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1" bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1" bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1" bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1" bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1" bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1" bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1" bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1" bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1" bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1" bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1" bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1" bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1" bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1" bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1" bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1" bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1" line.long 0x04 "IF3ARB,IF3 Arbitation Register" bitfld.long 0x04 31. " MSGVAl ,Message Valid" "Ignored,Configured" bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit" bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit" newline hexmask.long 0x04 0.--28. 1. " ID ,Message Identifier" endif endif group.long 0x14C++0x0B line.long 0x00 "IF3MCTRL,IF3 Message Control Register" bitfld.long 0x00 15. " NEWDAT ,New Data" "No new data,New data" bitfld.long 0x00 14. " MSGLST ,Message Lost" "Not lost,Lost" bitfld.long 0x00 13. " INTPND ,Interrupt Pending" "No interrupt,Interrupt" newline bitfld.long 0x00 12. " UMASK ,Use Acceptance Mask" "Ignored,Masked" bitfld.long 0x00 11. " TXIE ,Transmit Interrupt Enable" "Unchanged,Enabled" bitfld.long 0x00 10. " RXIE ,Receive Interrupt Enable" "Unchanged,Enabled" newline bitfld.long 0x00 9. " RMTEN ,Remote Enable" "Unchanged,Enabled" bitfld.long 0x00 8. " TXRQST ,Transmit Request" "Not requested,Requested" bitfld.long 0x00 7. " EOB ,End of Block" "Not last,Single/Last" newline bitfld.long 0x00 0.--3. " DLC[3-0] ,Data Length Code" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes" line.long 0x04 "IF3DATA,IF3 Data A Register" hexmask.long.byte 0x04 24.--31. 1. " DATA[3] ,4th data byte of a CAN Data Frame" hexmask.long.byte 0x04 16.--23. 1. " [2] ,3rd data byte of a CAN Data Frame" hexmask.long.byte 0x04 8.--15. 1. " [1] ,2nd data byte of a CAN Data Frame" hexmask.long.byte 0x04 0.--7. 1. " [0] ,1st data byte of a CAN Data Frame" line.long 0x08 "IF3DATB,IF3 Data B Register" hexmask.long.byte 0x08 24.--31. 1. " DATA[7] ,8th data byte of a CAN Data Frame" hexmask.long.byte 0x08 16.--23. 1. " [6] ,7th data byte of a CAN Data Frame" hexmask.long.byte 0x08 8.--15. 1. " [5] ,6th data byte of a CAN Data Frame" hexmask.long.byte 0x08 0.--7. 1. " [4] ,5th data byte of a CAN Data Frame" group.long 0x160++0x0F line.long 0x0 "IF3UENA2_1,Update Enable 2_1 Register" bitfld.long 0x00 31. " IF3UPDATEEN[32] ,IF3 Update Enabled Bit[32]" "Disabled,Enabled" bitfld.long 0x00 30. " [31] ,IF3 Update Enabled Bit[31]" "Disabled,Enabled" newline bitfld.long 0x00 29. " [30] ,IF3 Update Enabled Bit[30]" "Disabled,Enabled" bitfld.long 0x00 28. " [29] ,IF3 Update Enabled Bit[29]" "Disabled,Enabled" newline bitfld.long 0x00 27. " [28] ,IF3 Update Enabled Bit[28]" "Disabled,Enabled" bitfld.long 0x00 26. " [27] ,IF3 Update Enabled Bit[27]" "Disabled,Enabled" newline bitfld.long 0x00 25. " [26] ,IF3 Update Enabled Bit[26]" "Disabled,Enabled" bitfld.long 0x00 24. " [25] ,IF3 Update Enabled Bit[25]" "Disabled,Enabled" newline bitfld.long 0x00 23. " [24] ,IF3 Update Enabled Bit[24]" "Disabled,Enabled" bitfld.long 0x00 22. " [23] ,IF3 Update Enabled Bit[23]" "Disabled,Enabled" newline bitfld.long 0x00 21. " [22] ,IF3 Update Enabled Bit[22]" "Disabled,Enabled" bitfld.long 0x00 20. " [21] ,IF3 Update Enabled Bit[21]" "Disabled,Enabled" newline bitfld.long 0x00 19. " [20] ,IF3 Update Enabled Bit[20]" "Disabled,Enabled" bitfld.long 0x00 18. " [19] ,IF3 Update Enabled Bit[19]" "Disabled,Enabled" newline bitfld.long 0x00 17. " [18] ,IF3 Update Enabled Bit[18]" "Disabled,Enabled" bitfld.long 0x00 16. " [17] ,IF3 Update Enabled Bit[17]" "Disabled,Enabled" newline bitfld.long 0x00 15. " [16] ,IF3 Update Enabled Bit[16]" "Disabled,Enabled" bitfld.long 0x00 14. " [15] ,IF3 Update Enabled Bit[15]" "Disabled,Enabled" newline bitfld.long 0x00 13. " [14] ,IF3 Update Enabled Bit[14]" "Disabled,Enabled" bitfld.long 0x00 12. " [13] ,IF3 Update Enabled Bit[13]" "Disabled,Enabled" newline bitfld.long 0x00 11. " [12] ,IF3 Update Enabled Bit[12]" "Disabled,Enabled" bitfld.long 0x00 10. " [11] ,IF3 Update Enabled Bit[11]" "Disabled,Enabled" newline bitfld.long 0x00 9. " [10] ,IF3 Update Enabled Bit[10]" "Disabled,Enabled" bitfld.long 0x00 8. " [9] ,IF3 Update Enabled Bit[9]" "Disabled,Enabled" newline bitfld.long 0x00 7. " [8] ,IF3 Update Enabled Bit[8]" "Disabled,Enabled" bitfld.long 0x00 6. " [7] ,IF3 Update Enabled Bit[7]" "Disabled,Enabled" newline bitfld.long 0x00 5. " [6] ,IF3 Update Enabled Bit[6]" "Disabled,Enabled" bitfld.long 0x00 4. " [5] ,IF3 Update Enabled Bit[5]" "Disabled,Enabled" newline bitfld.long 0x00 3. " [4] ,IF3 Update Enabled Bit[4]" "Disabled,Enabled" bitfld.long 0x00 2. " [3] ,IF3 Update Enabled Bit[3]" "Disabled,Enabled" newline bitfld.long 0x00 1. " [2] ,IF3 Update Enabled Bit[2]" "Disabled,Enabled" bitfld.long 0x00 0. " [1] ,IF3 Update Enabled Bit[1]" "Disabled,Enabled" line.long 0x04 "IF3UENA4_3,Update Enable 4_3 Register" bitfld.long 0x04 31. " IF3UPDATEEN[64] ,IF3 Update Enabled Bit[64]" "Disabled,Enabled" bitfld.long 0x04 30. " [63] ,IF3 Update Enabled Bit[63]" "Disabled,Enabled" newline bitfld.long 0x04 29. " [62] ,IF3 Update Enabled Bit[62]" "Disabled,Enabled" bitfld.long 0x04 28. " [61] ,IF3 Update Enabled Bit[61]" "Disabled,Enabled" newline bitfld.long 0x04 27. " [60] ,IF3 Update Enabled Bit[60]" "Disabled,Enabled" bitfld.long 0x04 26. " [59] ,IF3 Update Enabled Bit[59]" "Disabled,Enabled" newline bitfld.long 0x04 25. " [58] ,IF3 Update Enabled Bit[58]" "Disabled,Enabled" bitfld.long 0x04 24. " [57] ,IF3 Update Enabled Bit[57]" "Disabled,Enabled" newline bitfld.long 0x04 23. " [56] ,IF3 Update Enabled Bit[56]" "Disabled,Enabled" bitfld.long 0x04 22. " [55] ,IF3 Update Enabled Bit[55]" "Disabled,Enabled" newline bitfld.long 0x04 21. " [54] ,IF3 Update Enabled Bit[54]" "Disabled,Enabled" bitfld.long 0x04 20. " [53] ,IF3 Update Enabled Bit[53]" "Disabled,Enabled" newline bitfld.long 0x04 19. " [52] ,IF3 Update Enabled Bit[52]" "Disabled,Enabled" bitfld.long 0x04 18. " [51] ,IF3 Update Enabled Bit[51]" "Disabled,Enabled" newline bitfld.long 0x04 17. " [50] ,IF3 Update Enabled Bit[50]" "Disabled,Enabled" bitfld.long 0x04 16. " [49] ,IF3 Update Enabled Bit[49]" "Disabled,Enabled" newline bitfld.long 0x04 15. " [48] ,IF3 Update Enabled Bit[48]" "Disabled,Enabled" bitfld.long 0x04 14. " [47] ,IF3 Update Enabled Bit[47]" "Disabled,Enabled" newline bitfld.long 0x04 13. " [46] ,IF3 Update Enabled Bit[46]" "Disabled,Enabled" bitfld.long 0x04 12. " [45] ,IF3 Update Enabled Bit[45]" "Disabled,Enabled" newline bitfld.long 0x04 11. " [44] ,IF3 Update Enabled Bit[44]" "Disabled,Enabled" bitfld.long 0x04 10. " [43] ,IF3 Update Enabled Bit[43]" "Disabled,Enabled" newline bitfld.long 0x04 9. " [42] ,IF3 Update Enabled Bit[42]" "Disabled,Enabled" bitfld.long 0x04 8. " [41] ,IF3 Update Enabled Bit[41]" "Disabled,Enabled" newline bitfld.long 0x04 7. " [40] ,IF3 Update Enabled Bit[40]" "Disabled,Enabled" bitfld.long 0x04 6. " [39] ,IF3 Update Enabled Bit[39]" "Disabled,Enabled" newline bitfld.long 0x04 5. " [38] ,IF3 Update Enabled Bit[38]" "Disabled,Enabled" bitfld.long 0x04 4. " [37] ,IF3 Update Enabled Bit[37]" "Disabled,Enabled" newline bitfld.long 0x04 3. " [36] ,IF3 Update Enabled Bit[36]" "Disabled,Enabled" bitfld.long 0x04 2. " [35] ,IF3 Update Enabled Bit[35]" "Disabled,Enabled" newline bitfld.long 0x04 1. " [34] ,IF3 Update Enabled Bit[34]" "Disabled,Enabled" bitfld.long 0x04 0. " [33] ,IF3 Update Enabled Bit[33]" "Disabled,Enabled" line.long 0x08 "IF3UENA6_5,Update Enable 6_5 Register" bitfld.long 0x08 31. " IF3UPDATEEN[96] ,IF3 Update Enabled Bit[96]" "Disabled,Enabled" bitfld.long 0x08 30. " [95] ,IF3 Update Enabled Bit[95]" "Disabled,Enabled" newline bitfld.long 0x08 29. " [94] ,IF3 Update Enabled Bit[94]" "Disabled,Enabled" bitfld.long 0x08 28. " [93] ,IF3 Update Enabled Bit[93]" "Disabled,Enabled" newline bitfld.long 0x08 27. " [92] ,IF3 Update Enabled Bit[92]" "Disabled,Enabled" bitfld.long 0x08 26. " [91] ,IF3 Update Enabled Bit[91]" "Disabled,Enabled" newline bitfld.long 0x08 25. " [90] ,IF3 Update Enabled Bit[90]" "Disabled,Enabled" bitfld.long 0x08 24. " [89] ,IF3 Update Enabled Bit[89]" "Disabled,Enabled" newline bitfld.long 0x08 23. " [88] ,IF3 Update Enabled Bit[88]" "Disabled,Enabled" bitfld.long 0x08 22. " [87] ,IF3 Update Enabled Bit[87]" "Disabled,Enabled" newline bitfld.long 0x08 21. " [86] ,IF3 Update Enabled Bit[86]" "Disabled,Enabled" bitfld.long 0x08 20. " [85] ,IF3 Update Enabled Bit[85]" "Disabled,Enabled" newline bitfld.long 0x08 19. " [84] ,IF3 Update Enabled Bit[84]" "Disabled,Enabled" bitfld.long 0x08 18. " [83] ,IF3 Update Enabled Bit[83]" "Disabled,Enabled" newline bitfld.long 0x08 17. " [82] ,IF3 Update Enabled Bit[82]" "Disabled,Enabled" bitfld.long 0x08 16. " [81] ,IF3 Update Enabled Bit[81]" "Disabled,Enabled" newline bitfld.long 0x08 15. " [80] ,IF3 Update Enabled Bit[80]" "Disabled,Enabled" bitfld.long 0x08 14. " [79] ,IF3 Update Enabled Bit[79]" "Disabled,Enabled" newline bitfld.long 0x08 13. " [78] ,IF3 Update Enabled Bit[78]" "Disabled,Enabled" bitfld.long 0x08 12. " [77] ,IF3 Update Enabled Bit[77]" "Disabled,Enabled" newline bitfld.long 0x08 11. " [76] ,IF3 Update Enabled Bit[76]" "Disabled,Enabled" bitfld.long 0x08 10. " [75] ,IF3 Update Enabled Bit[75]" "Disabled,Enabled" newline bitfld.long 0x08 9. " [74] ,IF3 Update Enabled Bit[74]" "Disabled,Enabled" bitfld.long 0x08 8. " [73] ,IF3 Update Enabled Bit[73]" "Disabled,Enabled" newline bitfld.long 0x08 7. " [72] ,IF3 Update Enabled Bit[72]" "Disabled,Enabled" bitfld.long 0x08 6. " [71] ,IF3 Update Enabled Bit[71]" "Disabled,Enabled" newline bitfld.long 0x08 5. " [70] ,IF3 Update Enabled Bit[70]" "Disabled,Enabled" bitfld.long 0x08 4. " [69] ,IF3 Update Enabled Bit[69]" "Disabled,Enabled" newline bitfld.long 0x08 3. " [68] ,IF3 Update Enabled Bit[68]" "Disabled,Enabled" bitfld.long 0x08 2. " [67] ,IF3 Update Enabled Bit[67]" "Disabled,Enabled" newline bitfld.long 0x08 1. " [66] ,IF3 Update Enabled Bit[66]" "Disabled,Enabled" bitfld.long 0x08 0. " [65] ,IF3 Update Enabled Bit[65]" "Disabled,Enabled" line.long 0x0C "IF3UENA8_7,Update Enable 8_7 Register" bitfld.long 0x0C 31. " IF3UPDATEEN[128] ,IF3 Update Enabled Bit[128]" "Disabled,Enabled" bitfld.long 0x0C 30. " [127] ,IF3 Update Enabled Bit[127]" "Disabled,Enabled" newline bitfld.long 0x0C 29. " [126] ,IF3 Update Enabled Bit[126]" "Disabled,Enabled" bitfld.long 0x0C 28. " [125] ,IF3 Update Enabled Bit[125]" "Disabled,Enabled" newline bitfld.long 0x0C 27. " [124] ,IF3 Update Enabled Bit[124]" "Disabled,Enabled" bitfld.long 0x0C 26. " [123] ,IF3 Update Enabled Bit[123]" "Disabled,Enabled" newline bitfld.long 0x0C 25. " [122] ,IF3 Update Enabled Bit[122]" "Disabled,Enabled" bitfld.long 0x0C 24. " [121] ,IF3 Update Enabled Bit[121]" "Disabled,Enabled" newline bitfld.long 0x0C 23. " [120] ,IF3 Update Enabled Bit[120]" "Disabled,Enabled" bitfld.long 0x0C 22. " [119] ,IF3 Update Enabled Bit[119]" "Disabled,Enabled" newline bitfld.long 0x0C 21. " [118] ,IF3 Update Enabled Bit[118]" "Disabled,Enabled" bitfld.long 0x0C 20. " [117] ,IF3 Update Enabled Bit[117]" "Disabled,Enabled" newline bitfld.long 0x0C 19. " [116] ,IF3 Update Enabled Bit[116]" "Disabled,Enabled" bitfld.long 0x0C 18. " [115] ,IF3 Update Enabled Bit[115]" "Disabled,Enabled" newline bitfld.long 0x0C 17. " [114] ,IF3 Update Enabled Bit[114]" "Disabled,Enabled" bitfld.long 0x0C 16. " [113] ,IF3 Update Enabled Bit[113]" "Disabled,Enabled" newline bitfld.long 0x0C 15. " [112] ,IF3 Update Enabled Bit[112]" "Disabled,Enabled" bitfld.long 0x0C 14. " [111] ,IF3 Update Enabled Bit[111]" "Disabled,Enabled" newline bitfld.long 0x0C 13. " [110] ,IF3 Update Enabled Bit[110]" "Disabled,Enabled" bitfld.long 0x0C 12. " [109] ,IF3 Update Enabled Bit[109]" "Disabled,Enabled" newline bitfld.long 0x0C 11. " [108] ,IF3 Update Enabled Bit[108]" "Disabled,Enabled" bitfld.long 0x0C 10. " [107] ,IF3 Update Enabled Bit[107]" "Disabled,Enabled" newline bitfld.long 0x0C 9. " [106] ,IF3 Update Enabled Bit[106]" "Disabled,Enabled" bitfld.long 0x0C 8. " [105] ,IF3 Update Enabled Bit[105]" "Disabled,Enabled" newline bitfld.long 0x0C 7. " [104] ,IF3 Update Enabled Bit[104]" "Disabled,Enabled" bitfld.long 0x0C 6. " [103] ,IF3 Update Enabled Bit[103]" "Disabled,Enabled" newline bitfld.long 0x0C 5. " [102] ,IF3 Update Enabled Bit[102]" "Disabled,Enabled" bitfld.long 0x0C 4. " [101] ,IF3 Update Enabled Bit[101]" "Disabled,Enabled" newline bitfld.long 0x0C 3. " [100] ,IF3 Update Enabled Bit[100]" "Disabled,Enabled" bitfld.long 0x0C 2. " [99] ,IF3 Update Enabled Bit[99]" "Disabled,Enabled" newline bitfld.long 0x0C 1. " [98] ,IF3 Update Enabled Bit[98]" "Disabled,Enabled" bitfld.long 0x0C 0. " [97] ,IF3 Update Enabled Bit[97]" "Disabled,Enabled" newline group.long 0x1E0++0x03 line.long 0x0 "IOCTRLTX,TX IO Control Register" sif (cpu()!="TMS470MF031"&&cpu()!="TMS470MF042"&&cpu()!="TMS470MF066"&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!=("TMS570LC4357")&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*")&&!cpuis("TMS570LS0232")&&!cpuis("TMS570LS0714*")&&!cpuis("TMS570LS0914*")) bitfld.long 0x00 19. " SR ,Slew Rate Selection of Output Driver" "Normal,Slow" newline endif bitfld.long 0x00 18. " PU ,Selection of Pull Direction" "Pull down,Pull up" bitfld.long 0x00 17. " PD ,Pull Functionality Disable" "No,Yes" bitfld.long 0x00 16. " OD ,Open Drain Mode" "Push pull,Open Drain" bitfld.long 0x00 3. " FUNC ,Functionality of Pin" "General,CAN" newline bitfld.long 0x00 2. " DIR ,Direction of Pin" "Input,Output" bitfld.long 0x00 1. " OUT ,Value to Drive to Pin if Configured for I/O" "Low,High" bitfld.long 0x00 0. " IN ,Value of Pin" "Low,High" group.long 0x1E4++0x03 line.long 0x0 "IOCTRLRX,RX IO Control Register" sif (cpu()!="TMS470MF031"&&cpu()!="TMS470MF042"&&cpu()!="TMS470MF066"&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!=("TMS570LC4357")&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*")&&!cpuis("TMS570LS0232")&&!cpuis("TMS570LS0714*")&&!cpuis("TMS570LS0914*")) bitfld.long 0x00 19. " SR ,Slew Rate Selection of Output Driver" "Normal,Slow" newline endif bitfld.long 0x00 18. " PU ,Selection of Pull Direction" "Pull down,Pull up" bitfld.long 0x00 17. " PD ,Pull Functionality Disable" "No,Yes" bitfld.long 0x00 16. " OD ,Open Drain Mode" "Push pull,Open Drain" bitfld.long 0x00 3. " FUNC ,Functionality of Pin" "General,CAN" newline bitfld.long 0x00 2. " DIR ,Direction of Pin" "Input,Output" bitfld.long 0x00 1. " OUT ,Value to Drive to Pin if Configured for I/O" "Low,High" bitfld.long 0x00 0. " IN ,Value of Pin" "Low,High" sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*") endian.le endif width 0x0B tree.end tree "DCAN2" base ad:0xFFF7DE00 sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*") endian.be endif width 12. group.long 0x00++0x3 line.long 0x0 "CTRL,Config Register" bitfld.long 0x00 25. " WUBA ,Automatic Wake Up on Bus Activity When in Local Power Down Mode" "Not detected,Detected" bitfld.long 0x00 24. " PDR ,Request for Local Low Power Down Mode" "Not requested,Power down" sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS0232")) newline bitfld.long 0x00 20. " DE3 ,DMA Enable for IF3" "Disabled,Enabled" newline bitfld.long 0x00 19. " DE2 ,DMA Enable for IF2" "Disabled,Enabled" bitfld.long 0x00 18. " DE1 ,DMA Enable for IF1" "Disabled,Enabled" endif newline bitfld.long 0x00 17. " IE1 ,DCAN1INT Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " INITDBG ,Internal Init State While Debug Access Mode" "No debug,Debug" bitfld.long 0x00 15. " SWR ,SW Reset Enable" "No reset,Reset" bitfld.long 0x00 10.--13. " PMD ,Parity on/off" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" newline bitfld.long 0x00 9. " ABO ,Auto Bus On Enable" "Disabled,Enabled" bitfld.long 0x00 8. " IDS ,Interruption Debug Support Enable" "Disabled,Enabled" bitfld.long 0x00 7. " TEST ,Test Mode Enable" "Disabled,Enabled" newline bitfld.long 0x00 6. " CCE ,Configuration Change Enable" "Disabled,Enabled" bitfld.long 0x00 5. " DAR ,Disable Automatic Retransmission" "No,Yes" bitfld.long 0x00 3. " EIE ,Error Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " SIE ,Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 1. " IE ,DCAN0INT Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. " INIT ,Initialization" "Disabled,Enabled" sif (cpu()=="TMS470MF031"||cpu()=="TMS470MF042"||cpu()=="TMS470MF066"||cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10206-PGE")||cpu()==("TMS570LC4357")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")) group.long 0x04++0x3 line.long 0x0 "ES,Error and Status Register" rbitfld.long 0x00 10. " PDA ,Local Power Down Mode Acknowledge" "Not in,Is in" rbitfld.long 0x00 9. " WAKEUPPND ,Wake Up Pending" "No requested,Requested" rbitfld.long 0x00 8. " PER ,Parity Error Detected" "No error,Error" newline rbitfld.long 0x00 7. " BOFF ,Bus-Off State" "Not in,In" rbitfld.long 0x00 6. " EWARN ,Warning state" "<96,>96" rbitfld.long 0x00 5. " EPASS ,Error Passive State" "CAN Bus,Passive" newline bitfld.long 0x00 4. " RXOK ,Received a Message successfully" "No,Yes" bitfld.long 0x00 3. " TXOK ,Transmitted a Message successfully" "No,Yes" bitfld.long 0x00 0.--2. " LEC ,Last Error Code" "No error,Stuff,Form,Ack,Bit1,Bit0,CRC,No CAN" elif !cpuis("TMS570LS3137-EP") hgroup.long 0x04++0x3 hide.long 0x0 "STAT,Status Register" in else if (((per.l.be(ad:0xFFF7DE00))&0x100)==0x100) group.long 0x04++0x3 line.long 0x0 "ES,Error and Status Register" rbitfld.long 0x00 10. " PDA ,Local Power Down Mode Acknowledge" "Not in,Is in" rbitfld.long 0x00 9. " WAKEUPPND ,Wake Up Pending" "No requested,Requested" rbitfld.long 0x00 8. " PER ,Parity Error Detected" "No error,Error" newline rbitfld.long 0x00 7. " BOFF ,Bus-Off State" "Not in,In" rbitfld.long 0x00 6. " EWARN ,Warning state" "<96,>96" rbitfld.long 0x00 5. " EPASS ,Error Passive State" "CAN Bus,Passive" newline bitfld.long 0x00 4. " RXOK ,Received a Message successfully" "No,Yes" bitfld.long 0x00 3. " TXOK ,Transmitted a Message successfully" "No,Yes" bitfld.long 0x00 0.--2. " LEC ,Last Error Code" "No error,Stuff,Form,Ack,Bit1,Bit0,CRC,No CAN" else hgroup.long 0x04++0x3 hide.long 0x0 "ES,Error and Status Register" in endif endif rgroup.long 0x08++0x3 line.long 0x0 "ERRC,Error Counter Register" bitfld.long 0x00 15. " RP ,Receive Error Passive" "Below,Reached" hexmask.long.byte 0x00 8.--14. 1. " REC ,Receive Error Counter" hexmask.long.byte 0x00 0.--7. 1. " TEC ,Transmit Error Counter" sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*") if (((per.l.be(ad:0xFFF7DE00))&0x41)==0x41) group.long 0x0C++0x3 line.long 0x0 "BTBRP,Bit Timing_BRP Extension Register" bitfld.long 0x00 16.--19. " BRPE ,Baud Rate Prescaler Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--14. " TSEG2 ,The Time Segment After the Sample Point" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--11. " TSEG1 ,The Time Segment Before the Sample Point" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 6.--7. " SJW ,Synchronization Jump Width" "0,1,2,3" bitfld.long 0x00 0.--5. " BRP ,Baud Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.long 0x0C++0x3 line.long 0x0 "BTBRP,Bit Timing_BRP Extension Register" bitfld.long 0x00 16.--19. " BRPE ,Baud Rate Prescaler Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--14. " TSEG2 ,The Time Segment After the Sample Point" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--11. " TSEG1 ,The Time Segment Before the Sample Point" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 6.--7. " SJW ,Synchronization Jump Width" "0,1,2,3" bitfld.long 0x00 0.--5. " BRP ,Baud Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif else group.long 0x0C++0x3 line.long 0x0 "BTBRP,Bit Timing_BRP Extension Register" bitfld.long 0x00 16.--19. " BRPE ,Baud Rate Prescaler Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--14. " TSEG2 ,The Time Segment After the Sample Point" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--11. " TSEG1 ,The Time Segment Before the Sample Point" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 6.--7. " SJW ,Synchronization Jump Width" "0,1,2,3" bitfld.long 0x00 0.--5. " BRP ,Baud Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif rgroup.long 0x10++0x3 line.long 0x0 "INTR,Interrupt Register" hexmask.long.byte 0x00 16.--23. 1. " INT1ID[7-0] ,Interrupt 1 Identifier" hexmask.long.word 0x00 0.--15. 1. " INTID[15-0] ,Interrupt Identifier" sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*") if (((per.l.be(ad:0xFFF7DE00))&0x41)==0x41) group.long 0x14++0x3 line.long 0x0 "TEST,Test Register" bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable" "Normal,Enabled" bitfld.long 0x00 8. " EXL ,External Loop Back Mode" "Normal,Enabled" bitfld.long 0x00 7. " RX ,Receive Pin" "Dominant,Recessive" newline bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Normal,Sample point,Dominant,Recessive" bitfld.long 0x00 4. " LBACK ,Loop Back Mode" "Disabled,Enabled" bitfld.long 0x00 3. " SILENT ,Silent Mode" "Normal,Enabled" else rgroup.long 0x14++0x3 line.long 0x0 "TEST,Test Register" bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable" "Normal,Enabled" bitfld.long 0x00 8. " EXL ,External Loop Back Mode" "Normal,Enabled" bitfld.long 0x00 7. " RX ,Receive Pin" "Dominant,Recessive" newline bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Normal,Sample point,Dominant,Recessive" bitfld.long 0x00 4. " LBACK ,Loop Back Mode" "Disabled,Enabled" bitfld.long 0x00 3. " SILENT ,Silent Mode" "Normal,Enabled" endif elif !cpuis("TMS570LS3137-EP") group.long 0x14++0x3 line.long 0x0 "TEST,Test Register" bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable" "Normal,Enabled" bitfld.long 0x00 8. " EXL ,External Loop Back Mode" "Normal,Enabled" bitfld.long 0x00 7. " RX ,Receive Pin" "Dominant,Recessive" newline sif (cpu()=="TMS470MF031"||cpu()=="TMS470MF042"||cpu()=="TMS470MF066"||cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10206-PGE")||cpu()==("TMS570LC4357")||cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS21*")||cpuis("TMS570LS31*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")) bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Normal,Sample point,Dominant,Recessive" else bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Reset,Sample point,Dominant,Recessive" endif bitfld.long 0x00 4. " LBACK ,Loop Back Mode" "Disabled,Enabled" bitfld.long 0x00 3. " SILENT ,Silent Mode" "Normal,Enabled" else if (((per.l.be(ad:0xFFF7DE00))&0x80)==0x80) group.long 0x14++0x3 line.long 0x0 "TEST,Test Register" bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable" "Normal,Enabled" bitfld.long 0x00 8. " EXL ,External Loop Back Mode" "Normal,Enabled" bitfld.long 0x00 7. " RX ,Receive Pin" "Dominant,Recessive" newline bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Normal,Sample point,Dominant,Recessive" bitfld.long 0x00 4. " LBACK ,Loop Back Mode" "Disabled,Enabled" bitfld.long 0x00 3. " SILENT ,Silent Mode" "Normal,Enabled" else rgroup.long 0x14++0x3 line.long 0x0 "TEST,Test Register" bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable" "Normal,Enabled" bitfld.long 0x00 8. " EXL ,External Loop Back Mode" "Normal,Enabled" bitfld.long 0x00 7. " RX ,Receive Pin" "Dominant,Recessive" newline bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Normal,Sample point,Dominant,Recessive" bitfld.long 0x00 4. " LBACK ,Loop Back Mode" "Disabled,Enabled" bitfld.long 0x00 3. " SILENT ,Silent Mode" "Normal,Enabled" endif endif rgroup.long 0x1C++0x3 line.long 0x0 "PERR,Parity Error Code Register" bitfld.long 0x00 8.--10. " WORD_NUMBER ,Word Number" ",1,2,3,4,5,?..." hexmask.long.byte 0x00 0.--7. 1. " MESSAGE_NUMBER ,Message Number" sif (cpu()=="TMS470MF031"||cpu()=="TMS470MF042"||cpu()=="TMS470MF066"||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")) rgroup.long 0x20++0x3 line.long 0x00 "REL,DCAN Core Release Register" bitfld.long 0x00 28.--31. " REL ,Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " STEP ,Step of Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " SUBSTEP ,Substep of Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " YEAR ,Design Time Stamp - Year" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " MON ,Design Time Stamp - Month" hexmask.long.byte 0x00 0.--7. 1. " DAY ,Design Time Stamp - Day" endif width 19. sif (cpu()=="TMS570LC4357") group.long 0x24++0x0B line.long 0x00 "DCAN_ECCDIAG,ECC Diagnostic Register" bitfld.long 0x00 0.--3. " ECCDIAG , SECDED diagnostic mode enable/disable" ",,,,,Enabled,,,,,Disabled,?..." line.long 0x04 "DCAN_ECCDIAG_STAT, ECC Diagnostic Status Register" eventfld.long 0x04 8. " DEFLG_DIAG , Double bit error diagnostic" "No error,Error" eventfld.long 0x04 0. " SEFLG_DIAG , Single bit error diagnostic" "No error,Error" line.long 0x08 "DCAN_ECC_CS, ECC Control and Status Register" bitfld.long 0x08 24.--27. " SBE_EVT_EN , Single bit error event" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.long 0x08 16.--19. " ECCMODE , Single bit error correction" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" eventfld.long 0x08 8. " DEFLG , Double bit error flag" "No error,Error" eventfld.long 0x08 0. " SEFLG , Single bit error flag" "No error,Error" rgroup.long 0x30++0x03 line.long 0x00 "DCAN_ECC_SERR, ECC Single Bit Error Code Register" hexmask.long.byte 0x00 0.--7. 1. " Message_Number , Message object number where ECC single bit error has been detected" endif width 12. group.long 0x80++0x03 line.long 0x00 "ABOT,Auto Bus On Time" rgroup.long 0x84++0x4F line.long 0x00 "TRREQ,Transmission Request X" bitfld.long 0x00 14.--15. " TXRQSTREG8 ,Transmission Request 8" "0,1,2,3" bitfld.long 0x00 12.--13. " TXRQSTREG7 ,Transmission Request 7" "0,1,2,3" bitfld.long 0x00 10.--11. " TXRQSTREG6 ,Transmission Request 6" "0,1,2,3" bitfld.long 0x00 8.--9. " TXRQSTREG5 ,Transmission Request 5" "0,1,2,3" newline bitfld.long 0x00 6.--7. " TXRQSTREG4 ,Transmission Request 4" "0,1,2,3" bitfld.long 0x00 4.--5. " TXRQSTREG3 ,Transmission Request 3" "0,1,2,3" bitfld.long 0x00 2.--3. " TXRQSTREG2 ,Transmission Request 2" "0,1,2,3" bitfld.long 0x00 0.--1. " TXRQSTREG1 ,Transmission Request 1" "0,1,2,3" line.long 0x04 "TRREQ12,Transmission Request 1-2" bitfld.long 0x04 31. " TXRQST[32] ,Transmission Request Bits[32]" "Not requested,Requested" bitfld.long 0x04 30. " [31] ,Transmission Request Bits[31]" "Not requested,Requested" newline bitfld.long 0x04 29. " [30] ,Transmission Request Bits[30]" "Not requested,Requested" bitfld.long 0x04 28. " [29] ,Transmission Request Bits[29]" "Not requested,Requested" newline bitfld.long 0x04 27. " [28] ,Transmission Request Bits[28]" "Not requested,Requested" bitfld.long 0x04 26. " [27] ,Transmission Request Bits[27]" "Not requested,Requested" newline bitfld.long 0x04 25. " [26] ,Transmission Request Bits[26]" "Not requested,Requested" bitfld.long 0x04 24. " [25] ,Transmission Request Bits[25]" "Not requested,Requested" newline bitfld.long 0x04 23. " [24] ,Transmission Request Bits[24]" "Not requested,Requested" bitfld.long 0x04 22. " [23] ,Transmission Request Bits[23]" "Not requested,Requested" newline bitfld.long 0x04 21. " [22] ,Transmission Request Bits[22]" "Not requested,Requested" bitfld.long 0x04 20. " [21] ,Transmission Request Bits[21]" "Not requested,Requested" newline bitfld.long 0x04 19. " [20] ,Transmission Request Bits[20]" "Not requested,Requested" bitfld.long 0x04 18. " [19] ,Transmission Request Bits[19]" "Not requested,Requested" newline bitfld.long 0x04 17. " [18] ,Transmission Request Bits[18]" "Not requested,Requested" bitfld.long 0x04 16. " [17] ,Transmission Request Bits[17]" "Not requested,Requested" newline bitfld.long 0x04 15. " [16] ,Transmission Request Bits[16]" "Not requested,Requested" bitfld.long 0x04 14. " [15] ,Transmission Request Bits[15]" "Not requested,Requested" newline bitfld.long 0x04 13. " [14] ,Transmission Request Bits[14]" "Not requested,Requested" bitfld.long 0x04 12. " [13] ,Transmission Request Bits[13]" "Not requested,Requested" newline bitfld.long 0x04 11. " [12] ,Transmission Request Bits[12]" "Not requested,Requested" bitfld.long 0x04 10. " [11] ,Transmission Request Bits[11]" "Not requested,Requested" newline bitfld.long 0x04 9. " [10] ,Transmission Request Bits[10]" "Not requested,Requested" bitfld.long 0x04 8. " [9] ,Transmission Request Bits[9]" "Not requested,Requested" newline bitfld.long 0x04 7. " [8] ,Transmission Request Bits[8]" "Not requested,Requested" bitfld.long 0x04 6. " [7] ,Transmission Request Bits[7]" "Not requested,Requested" newline bitfld.long 0x04 5. " [6] ,Transmission Request Bits[6]" "Not requested,Requested" bitfld.long 0x04 4. " [5] ,Transmission Request Bits[5]" "Not requested,Requested" newline bitfld.long 0x04 3. " [4] ,Transmission Request Bits[4]" "Not requested,Requested" bitfld.long 0x04 2. " [3] ,Transmission Request Bits[3]" "Not requested,Requested" newline bitfld.long 0x04 1. " [2] ,Transmission Request Bits[2]" "Not requested,Requested" bitfld.long 0x04 0. " [1] ,Transmission Request Bits[1]" "Not requested,Requested" line.long 0x08 "TRREQ34,Transmission Request 3-4" bitfld.long 0x08 31. " TXRQST[64] ,Transmission Request Bits[64]" "Not requested,Requested" bitfld.long 0x08 30. " [63] ,Transmission Request Bits[63]" "Not requested,Requested" newline bitfld.long 0x08 29. " [62] ,Transmission Request Bits[62]" "Not requested,Requested" bitfld.long 0x08 28. " [61] ,Transmission Request Bits[61]" "Not requested,Requested" newline bitfld.long 0x08 27. " [60] ,Transmission Request Bits[60]" "Not requested,Requested" bitfld.long 0x08 26. " [59] ,Transmission Request Bits[59]" "Not requested,Requested" newline bitfld.long 0x08 25. " [58] ,Transmission Request Bits[58]" "Not requested,Requested" bitfld.long 0x08 24. " [57] ,Transmission Request Bits[57]" "Not requested,Requested" newline bitfld.long 0x08 23. " [56] ,Transmission Request Bits[56]" "Not requested,Requested" bitfld.long 0x08 22. " [55] ,Transmission Request Bits[55]" "Not requested,Requested" newline bitfld.long 0x08 21. " [54] ,Transmission Request Bits[54]" "Not requested,Requested" bitfld.long 0x08 20. " [53] ,Transmission Request Bits[53]" "Not requested,Requested" newline bitfld.long 0x08 19. " [52] ,Transmission Request Bits[52]" "Not requested,Requested" bitfld.long 0x08 18. " [51] ,Transmission Request Bits[51]" "Not requested,Requested" newline bitfld.long 0x08 17. " [50] ,Transmission Request Bits[50]" "Not requested,Requested" bitfld.long 0x08 16. " [49] ,Transmission Request Bits[49]" "Not requested,Requested" newline bitfld.long 0x08 15. " [48] ,Transmission Request Bits[48]" "Not requested,Requested" bitfld.long 0x08 14. " [47] ,Transmission Request Bits[47]" "Not requested,Requested" newline bitfld.long 0x08 13. " [46] ,Transmission Request Bits[46]" "Not requested,Requested" bitfld.long 0x08 12. " [45] ,Transmission Request Bits[45]" "Not requested,Requested" newline bitfld.long 0x08 11. " [44] ,Transmission Request Bits[44]" "Not requested,Requested" bitfld.long 0x08 10. " [43] ,Transmission Request Bits[43]" "Not requested,Requested" newline bitfld.long 0x08 9. " [42] ,Transmission Request Bits[42]" "Not requested,Requested" bitfld.long 0x08 8. " [41] ,Transmission Request Bits[41]" "Not requested,Requested" newline bitfld.long 0x08 7. " [40] ,Transmission Request Bits[40]" "Not requested,Requested" bitfld.long 0x08 6. " [39] ,Transmission Request Bits[39]" "Not requested,Requested" newline bitfld.long 0x08 5. " [38] ,Transmission Request Bits[38]" "Not requested,Requested" bitfld.long 0x08 4. " [37] ,Transmission Request Bits[37]" "Not requested,Requested" newline bitfld.long 0x08 3. " [36] ,Transmission Request Bits[36]" "Not requested,Requested" bitfld.long 0x08 2. " [35] ,Transmission Request Bits[35]" "Not requested,Requested" newline bitfld.long 0x08 1. " [34] ,Transmission Request Bits[34]" "Not requested,Requested" bitfld.long 0x08 0. " [33] ,Transmission Request Bits[33]" "Not requested,Requested" line.long 0x0C "TRREQ56,Transmission Request 5-6" bitfld.long 0x0C 31. " TXRQST[96] ,Transmission Request Bits[96]" "Not requested,Requested" bitfld.long 0x0C 30. " [95] ,Transmission Request Bits[95]" "Not requested,Requested" newline bitfld.long 0x0C 29. " [94] ,Transmission Request Bits[94]" "Not requested,Requested" bitfld.long 0x0C 28. " [93] ,Transmission Request Bits[93]" "Not requested,Requested" newline bitfld.long 0x0C 27. " [92] ,Transmission Request Bits[92]" "Not requested,Requested" bitfld.long 0x0C 26. " [91] ,Transmission Request Bits[91]" "Not requested,Requested" newline bitfld.long 0x0C 25. " [90] ,Transmission Request Bits[90]" "Not requested,Requested" bitfld.long 0x0C 24. " [89] ,Transmission Request Bits[89]" "Not requested,Requested" newline bitfld.long 0x0C 23. " [88] ,Transmission Request Bits[88]" "Not requested,Requested" bitfld.long 0x0C 22. " [87] ,Transmission Request Bits[87]" "Not requested,Requested" newline bitfld.long 0x0C 21. " [86] ,Transmission Request Bits[86]" "Not requested,Requested" bitfld.long 0x0C 20. " [85] ,Transmission Request Bits[85]" "Not requested,Requested" newline bitfld.long 0x0C 19. " [84] ,Transmission Request Bits[84]" "Not requested,Requested" bitfld.long 0x0C 18. " [83] ,Transmission Request Bits[83]" "Not requested,Requested" newline bitfld.long 0x0C 17. " [82] ,Transmission Request Bits[82]" "Not requested,Requested" bitfld.long 0x0C 16. " [81] ,Transmission Request Bits[81]" "Not requested,Requested" newline bitfld.long 0x0C 15. " [80] ,Transmission Request Bits[80]" "Not requested,Requested" bitfld.long 0x0C 14. " [79] ,Transmission Request Bits[79]" "Not requested,Requested" newline bitfld.long 0x0C 13. " [78] ,Transmission Request Bits[78]" "Not requested,Requested" bitfld.long 0x0C 12. " [77] ,Transmission Request Bits[77]" "Not requested,Requested" newline bitfld.long 0x0C 11. " [76] ,Transmission Request Bits[76]" "Not requested,Requested" bitfld.long 0x0C 10. " [75] ,Transmission Request Bits[75]" "Not requested,Requested" newline bitfld.long 0x0C 9. " [74] ,Transmission Request Bits[74]" "Not requested,Requested" bitfld.long 0x0C 8. " [73] ,Transmission Request Bits[73]" "Not requested,Requested" newline bitfld.long 0x0C 7. " [72] ,Transmission Request Bits[72]" "Not requested,Requested" bitfld.long 0x0C 6. " [71] ,Transmission Request Bits[71]" "Not requested,Requested" newline bitfld.long 0x0C 5. " [70] ,Transmission Request Bits[70]" "Not requested,Requested" bitfld.long 0x0C 4. " [69] ,Transmission Request Bits[69]" "Not requested,Requested" newline bitfld.long 0x0C 3. " [68] ,Transmission Request Bits[68]" "Not requested,Requested" bitfld.long 0x0C 2. " [67] ,Transmission Request Bits[67]" "Not requested,Requested" newline bitfld.long 0x0C 1. " [66] ,Transmission Request Bits[66]" "Not requested,Requested" bitfld.long 0x0C 0. " [65] ,Transmission Request Bits[65]" "Not requested,Requested" line.long 0x10 "TRREQ78,Transmission Request 7-8" bitfld.long 0x10 31. " TXRQST[128] ,Transmission Request Bits[128]" "Not requested,Requested" bitfld.long 0x10 30. " [127] ,Transmission Request Bits[127]" "Not requested,Requested" newline bitfld.long 0x10 29. " [126] ,Transmission Request Bits[126]" "Not requested,Requested" bitfld.long 0x10 28. " [125] ,Transmission Request Bits[125]" "Not requested,Requested" newline bitfld.long 0x10 27. " [124] ,Transmission Request Bits[124]" "Not requested,Requested" bitfld.long 0x10 26. " [123] ,Transmission Request Bits[123]" "Not requested,Requested" newline bitfld.long 0x10 25. " [122] ,Transmission Request Bits[122]" "Not requested,Requested" bitfld.long 0x10 24. " [121] ,Transmission Request Bits[121]" "Not requested,Requested" newline bitfld.long 0x10 23. " [120] ,Transmission Request Bits[120]" "Not requested,Requested" bitfld.long 0x10 22. " [119] ,Transmission Request Bits[119]" "Not requested,Requested" newline bitfld.long 0x10 21. " [118] ,Transmission Request Bits[118]" "Not requested,Requested" bitfld.long 0x10 20. " [117] ,Transmission Request Bits[117]" "Not requested,Requested" newline bitfld.long 0x10 19. " [116] ,Transmission Request Bits[116]" "Not requested,Requested" bitfld.long 0x10 18. " [115] ,Transmission Request Bits[115]" "Not requested,Requested" newline bitfld.long 0x10 17. " [114] ,Transmission Request Bits[114]" "Not requested,Requested" bitfld.long 0x10 16. " [113] ,Transmission Request Bits[113]" "Not requested,Requested" newline bitfld.long 0x10 15. " [112] ,Transmission Request Bits[112]" "Not requested,Requested" bitfld.long 0x10 14. " [111] ,Transmission Request Bits[111]" "Not requested,Requested" newline bitfld.long 0x10 13. " [110] ,Transmission Request Bits[110]" "Not requested,Requested" bitfld.long 0x10 12. " [109] ,Transmission Request Bits[109]" "Not requested,Requested" newline bitfld.long 0x10 11. " [108] ,Transmission Request Bits[108]" "Not requested,Requested" bitfld.long 0x10 10. " [107] ,Transmission Request Bits[107]" "Not requested,Requested" newline bitfld.long 0x10 9. " [106] ,Transmission Request Bits[106]" "Not requested,Requested" bitfld.long 0x10 8. " [105] ,Transmission Request Bits[105]" "Not requested,Requested" newline bitfld.long 0x10 7. " [104] ,Transmission Request Bits[104]" "Not requested,Requested" bitfld.long 0x10 6. " [103] ,Transmission Request Bits[103]" "Not requested,Requested" newline bitfld.long 0x10 5. " [102] ,Transmission Request Bits[102]" "Not requested,Requested" bitfld.long 0x10 4. " [101] ,Transmission Request Bits[101]" "Not requested,Requested" newline bitfld.long 0x10 3. " [100] ,Transmission Request Bits[100]" "Not requested,Requested" bitfld.long 0x10 2. " [99] ,Transmission Request Bits[99]" "Not requested,Requested" newline bitfld.long 0x10 1. " [98] ,Transmission Request Bits[98]" "Not requested,Requested" bitfld.long 0x10 0. " [97] ,Transmission Request Bits[97]" "Not requested,Requested" line.long 0x14 "NEWDAT,New Data X" bitfld.long 0x14 14.--15. " NEWDATREG8 ,New Data 8" "0,1,2,3" bitfld.long 0x14 12.--13. " NEWDATREG7 ,New Data 7" "0,1,2,3" bitfld.long 0x14 10.--11. " NEWDATREG6 ,New Data 6" "0,1,2,3" bitfld.long 0x14 8.--9. " NEWDATREG5 ,New Data 5" "0,1,2,3" newline bitfld.long 0x14 6.--7. " NEWDATREG4 ,NEW DATA 4" "0,1,2,3" bitfld.long 0x14 4.--5. " NEWDATREG3 ,New Data 3" "0,1,2,3" bitfld.long 0x14 2.--3. " NEWDATREG2 ,New Data 2" "0,1,2,3" bitfld.long 0x14 0.--1. " NEWDATREG1 ,New Data 1" "0,1,2,3" line.long 0x18 "NEWDAT12,New Data 1-2" bitfld.long 0x18 31. " NEWDAT[32] ,New Data Bit[32]" "Not requested,Requested" bitfld.long 0x18 30. " [31] ,New Data Bit[31]" "Not requested,Requested" newline bitfld.long 0x18 29. " [30] ,New Data Bit[30]" "Not requested,Requested" bitfld.long 0x18 28. " [29] ,New Data Bit[29]" "Not requested,Requested" newline bitfld.long 0x18 27. " [28] ,New Data Bit[28]" "Not requested,Requested" bitfld.long 0x18 26. " [27] ,New Data Bit[27]" "Not requested,Requested" newline bitfld.long 0x18 25. " [26] ,New Data Bit[26]" "Not requested,Requested" bitfld.long 0x18 24. " [25] ,New Data Bit[25]" "Not requested,Requested" newline bitfld.long 0x18 23. " [24] ,New Data Bit[24]" "Not requested,Requested" bitfld.long 0x18 22. " [23] ,New Data Bit[23]" "Not requested,Requested" newline bitfld.long 0x18 21. " [22] ,New Data Bit[22]" "Not requested,Requested" bitfld.long 0x18 20. " [21] ,New Data Bit[21]" "Not requested,Requested" newline bitfld.long 0x18 19. " [20] ,New Data Bit[20]" "Not requested,Requested" bitfld.long 0x18 18. " [19] ,New Data Bit[19]" "Not requested,Requested" newline bitfld.long 0x18 17. " [18] ,New Data Bit[18]" "Not requested,Requested" bitfld.long 0x18 16. " [17] ,New Data Bit[17]" "Not requested,Requested" newline bitfld.long 0x18 15. " [16] ,New Data Bit[16]" "Not requested,Requested" bitfld.long 0x18 14. " [15] ,New Data Bit[15]" "Not requested,Requested" newline bitfld.long 0x18 13. " [14] ,New Data Bit[14]" "Not requested,Requested" bitfld.long 0x18 12. " [13] ,New Data Bit[13]" "Not requested,Requested" newline bitfld.long 0x18 11. " [12] ,New Data Bit[12]" "Not requested,Requested" bitfld.long 0x18 10. " [11] ,New Data Bit[11]" "Not requested,Requested" newline bitfld.long 0x18 9. " [10] ,New Data Bit[10]" "Not requested,Requested" bitfld.long 0x18 8. " [9] ,New Data Bit[9]" "Not requested,Requested" newline bitfld.long 0x18 7. " [8] ,New Data Bit[8]" "Not requested,Requested" bitfld.long 0x18 6. " [7] ,New Data Bit[7]" "Not requested,Requested" newline bitfld.long 0x18 5. " [6] ,New Data Bit[6]" "Not requested,Requested" bitfld.long 0x18 4. " [5] ,New Data Bit[5]" "Not requested,Requested" newline bitfld.long 0x18 3. " [4] ,New Data Bit[4]" "Not requested,Requested" bitfld.long 0x18 2. " [3] ,New Data Bit[3]" "Not requested,Requested" newline bitfld.long 0x18 1. " [2] ,New Data Bit[2]" "Not requested,Requested" bitfld.long 0x18 0. " [1] ,New Data Bit[1]" "Not requested,Requested" line.long 0x1C "NEWDAT34,New Data 3-4" bitfld.long 0x1C 31. " NEWDAT[64] ,New Data Bit[64]" "Not requested,Requested" bitfld.long 0x1C 30. " [63] ,New Data Bit[63]" "Not requested,Requested" newline bitfld.long 0x1C 29. " [62] ,New Data Bit[62]" "Not requested,Requested" bitfld.long 0x1C 28. " [61] ,New Data Bit[61]" "Not requested,Requested" newline bitfld.long 0x1C 27. " [60] ,New Data Bit[60]" "Not requested,Requested" bitfld.long 0x1C 26. " [59] ,New Data Bit[59]" "Not requested,Requested" newline bitfld.long 0x1C 25. " [58] ,New Data Bit[58]" "Not requested,Requested" bitfld.long 0x1C 24. " [57] ,New Data Bit[57]" "Not requested,Requested" newline bitfld.long 0x1C 23. " [56] ,New Data Bit[56]" "Not requested,Requested" bitfld.long 0x1C 22. " [55] ,New Data Bit[55]" "Not requested,Requested" newline bitfld.long 0x1C 21. " [54] ,New Data Bit[54]" "Not requested,Requested" bitfld.long 0x1C 20. " [53] ,New Data Bit[53]" "Not requested,Requested" newline bitfld.long 0x1C 19. " [52] ,New Data Bit[52]" "Not requested,Requested" bitfld.long 0x1C 18. " [51] ,New Data Bit[51]" "Not requested,Requested" newline bitfld.long 0x1C 17. " [50] ,New Data Bit[50]" "Not requested,Requested" bitfld.long 0x1C 16. " [49] ,New Data Bit[49]" "Not requested,Requested" newline bitfld.long 0x1C 15. " [48] ,New Data Bit[48]" "Not requested,Requested" bitfld.long 0x1C 14. " [47] ,New Data Bit[47]" "Not requested,Requested" newline bitfld.long 0x1C 13. " [46] ,New Data Bit[46]" "Not requested,Requested" bitfld.long 0x1C 12. " [45] ,New Data Bit[45]" "Not requested,Requested" newline bitfld.long 0x1C 11. " [44] ,New Data Bit[44]" "Not requested,Requested" bitfld.long 0x1C 10. " [43] ,New Data Bit[43]" "Not requested,Requested" newline bitfld.long 0x1C 9. " [42] ,New Data Bit[42]" "Not requested,Requested" bitfld.long 0x1C 8. " [41] ,New Data Bit[41]" "Not requested,Requested" newline bitfld.long 0x1C 7. " [40] ,New Data Bit[40]" "Not requested,Requested" bitfld.long 0x1C 6. " [39] ,New Data Bit[39]" "Not requested,Requested" newline bitfld.long 0x1C 5. " [38] ,New Data Bit[38]" "Not requested,Requested" bitfld.long 0x1C 4. " [37] ,New Data Bit[37]" "Not requested,Requested" newline bitfld.long 0x1C 3. " [36] ,New Data Bit[36]" "Not requested,Requested" bitfld.long 0x1C 2. " [35] ,New Data Bit[35]" "Not requested,Requested" newline bitfld.long 0x1C 1. " [34] ,New Data Bit[34]" "Not requested,Requested" bitfld.long 0x1C 0. " [33] ,New Data Bit[33]" "Not requested,Requested" line.long 0x20 "NEWDAT56,New Data 5-6" bitfld.long 0x20 31. " NEWDAT[96] ,New Data Bit[96]" "Not requested,Requested" bitfld.long 0x20 30. " [95] ,New Data Bit[95]" "Not requested,Requested" newline bitfld.long 0x20 29. " [94] ,New Data Bit[94]" "Not requested,Requested" bitfld.long 0x20 28. " [93] ,New Data Bit[93]" "Not requested,Requested" newline bitfld.long 0x20 27. " [92] ,New Data Bit[92]" "Not requested,Requested" bitfld.long 0x20 26. " [91] ,New Data Bit[91]" "Not requested,Requested" newline bitfld.long 0x20 25. " [90] ,New Data Bit[90]" "Not requested,Requested" bitfld.long 0x20 24. " [89] ,New Data Bit[89]" "Not requested,Requested" newline bitfld.long 0x20 23. " [88] ,New Data Bit[88]" "Not requested,Requested" bitfld.long 0x20 22. " [87] ,New Data Bit[87]" "Not requested,Requested" newline bitfld.long 0x20 21. " [86] ,New Data Bit[86]" "Not requested,Requested" bitfld.long 0x20 20. " [85] ,New Data Bit[85]" "Not requested,Requested" newline bitfld.long 0x20 19. " [84] ,New Data Bit[84]" "Not requested,Requested" bitfld.long 0x20 18. " [83] ,New Data Bit[83]" "Not requested,Requested" newline bitfld.long 0x20 17. " [82] ,New Data Bit[82]" "Not requested,Requested" bitfld.long 0x20 16. " [81] ,New Data Bit[81]" "Not requested,Requested" newline bitfld.long 0x20 15. " [80] ,New Data Bit[80]" "Not requested,Requested" bitfld.long 0x20 14. " [79] ,New Data Bit[79]" "Not requested,Requested" newline bitfld.long 0x20 13. " [78] ,New Data Bit[78]" "Not requested,Requested" bitfld.long 0x20 12. " [77] ,New Data Bit[77]" "Not requested,Requested" newline bitfld.long 0x20 11. " [76] ,New Data Bit[76]" "Not requested,Requested" bitfld.long 0x20 10. " [75] ,New Data Bit[75]" "Not requested,Requested" newline bitfld.long 0x20 9. " [74] ,New Data Bit[74]" "Not requested,Requested" bitfld.long 0x20 8. " [73] ,New Data Bit[73]" "Not requested,Requested" newline bitfld.long 0x20 7. " [72] ,New Data Bit[72]" "Not requested,Requested" bitfld.long 0x20 6. " [71] ,New Data Bit[71]" "Not requested,Requested" newline bitfld.long 0x20 5. " [70] ,New Data Bit[70]" "Not requested,Requested" bitfld.long 0x20 4. " [69] ,New Data Bit[69]" "Not requested,Requested" newline bitfld.long 0x20 3. " [68] ,New Data Bit[68]" "Not requested,Requested" bitfld.long 0x20 2. " [67] ,New Data Bit[67]" "Not requested,Requested" newline bitfld.long 0x20 1. " [66] ,New Data Bit[66]" "Not requested,Requested" bitfld.long 0x20 0. " [65] ,New Data Bit[65]" "Not requested,Requested" line.long 0x24 "NEWDAT78,New Data 7-8" bitfld.long 0x24 31. " NEWDAT[128] ,New Data Bit[128]" "Not requested,Requested" bitfld.long 0x24 30. " [127] ,New Data Bit[127]" "Not requested,Requested" newline bitfld.long 0x24 29. " [126] ,New Data Bit[126]" "Not requested,Requested" bitfld.long 0x24 28. " [125] ,New Data Bit[125]" "Not requested,Requested" newline bitfld.long 0x24 27. " [124] ,New Data Bit[124]" "Not requested,Requested" bitfld.long 0x24 26. " [123] ,New Data Bit[123]" "Not requested,Requested" newline bitfld.long 0x24 25. " [122] ,New Data Bit[122]" "Not requested,Requested" bitfld.long 0x24 24. " [121] ,New Data Bit[121]" "Not requested,Requested" newline bitfld.long 0x24 23. " [120] ,New Data Bit[120]" "Not requested,Requested" bitfld.long 0x24 22. " [119] ,New Data Bit[119]" "Not requested,Requested" newline bitfld.long 0x24 21. " [118] ,New Data Bit[118]" "Not requested,Requested" bitfld.long 0x24 20. " [117] ,New Data Bit[117]" "Not requested,Requested" newline bitfld.long 0x24 19. " [116] ,New Data Bit[116]" "Not requested,Requested" bitfld.long 0x24 18. " [115] ,New Data Bit[115]" "Not requested,Requested" newline bitfld.long 0x24 17. " [114] ,New Data Bit[114]" "Not requested,Requested" bitfld.long 0x24 16. " [113] ,New Data Bit[113]" "Not requested,Requested" newline bitfld.long 0x24 15. " [112] ,New Data Bit[112]" "Not requested,Requested" bitfld.long 0x24 14. " [111] ,New Data Bit[111]" "Not requested,Requested" newline bitfld.long 0x24 13. " [110] ,New Data Bit[110]" "Not requested,Requested" bitfld.long 0x24 12. " [109] ,New Data Bit[109]" "Not requested,Requested" newline bitfld.long 0x24 11. " [108] ,New Data Bit[108]" "Not requested,Requested" bitfld.long 0x24 10. " [107] ,New Data Bit[107]" "Not requested,Requested" newline bitfld.long 0x24 9. " [106] ,New Data Bit[106]" "Not requested,Requested" bitfld.long 0x24 8. " [105] ,New Data Bit[105]" "Not requested,Requested" newline bitfld.long 0x24 7. " [104] ,New Data Bit[104]" "Not requested,Requested" bitfld.long 0x24 6. " [103] ,New Data Bit[103]" "Not requested,Requested" newline bitfld.long 0x24 5. " [102] ,New Data Bit[102]" "Not requested,Requested" bitfld.long 0x24 4. " [101] ,New Data Bit[101]" "Not requested,Requested" newline bitfld.long 0x24 3. " [100] ,New Data Bit[100]" "Not requested,Requested" bitfld.long 0x24 2. " [99] ,New Data Bit[99]" "Not requested,Requested" newline bitfld.long 0x24 1. " [98] ,New Data Bit[98]" "Not requested,Requested" bitfld.long 0x24 0. " [97] ,New Data Bit[97]" "Not requested,Requested" line.long 0x28 "INTPEN,Interrupt Pending X" bitfld.long 0x28 14.--15. " INTPENDREG[8] ,Interrupt Pending 8" "0,1,2,3" bitfld.long 0x28 12.--13. " [7] ,Interrupt Pending 7" "0,1,2,3" bitfld.long 0x28 10.--11. " [6] ,Interrupt Pending 6" "0,1,2,3" bitfld.long 0x28 8.--9. " [5] ,Interrupt Pending 5" "0,1,2,3" newline bitfld.long 0x28 6.--7. " [4] ,Interrupt Pending 4" "0,1,2,3" bitfld.long 0x28 4.--5. " [3] ,Interrupt Pending 3" "0,1,2,3" bitfld.long 0x28 2.--3. " [2] ,Interrupt Pending 2" "0,1,2,3" bitfld.long 0x28 0.--1. " [1] ,Interrupt Pending 1" "0,1,2,3" line.long 0x2C "INTPEN12,Interrupt Pending 1-2" bitfld.long 0x2C 31. " IntPnd[32] ,Interrupt Pending Bit[32]" "No interrupt,Interrupt" bitfld.long 0x2C 30. " [31] ,Interrupt Pending Bit[31]" "No interrupt,Interrupt" newline bitfld.long 0x2C 29. " [30] ,Interrupt Pending Bit[30]" "No interrupt,Interrupt" bitfld.long 0x2C 28. " [29] ,Interrupt Pending Bit[29]" "No interrupt,Interrupt" newline bitfld.long 0x2C 27. " [28] ,Interrupt Pending Bit[28]" "No interrupt,Interrupt" bitfld.long 0x2C 26. " [27] ,Interrupt Pending Bit[27]" "No interrupt,Interrupt" newline bitfld.long 0x2C 25. " [26] ,Interrupt Pending Bit[26]" "No interrupt,Interrupt" bitfld.long 0x2C 24. " [25] ,Interrupt Pending Bit[25]" "No interrupt,Interrupt" newline bitfld.long 0x2C 23. " [24] ,Interrupt Pending Bit[24]" "No interrupt,Interrupt" bitfld.long 0x2C 22. " [23] ,Interrupt Pending Bit[23]" "No interrupt,Interrupt" newline bitfld.long 0x2C 21. " [22] ,Interrupt Pending Bit[22]" "No interrupt,Interrupt" bitfld.long 0x2C 20. " [21] ,Interrupt Pending Bit[21]" "No interrupt,Interrupt" newline bitfld.long 0x2C 19. " [20] ,Interrupt Pending Bit[20]" "No interrupt,Interrupt" bitfld.long 0x2C 18. " [19] ,Interrupt Pending Bit[19]" "No interrupt,Interrupt" newline bitfld.long 0x2C 17. " [18] ,Interrupt Pending Bit[18]" "No interrupt,Interrupt" bitfld.long 0x2C 16. " [17] ,Interrupt Pending Bit[17]" "No interrupt,Interrupt" newline bitfld.long 0x2C 15. " [16] ,Interrupt Pending Bit[16]" "No interrupt,Interrupt" bitfld.long 0x2C 14. " [15] ,Interrupt Pending Bit[15]" "No interrupt,Interrupt" newline bitfld.long 0x2C 13. " [14] ,Interrupt Pending Bit[14]" "No interrupt,Interrupt" bitfld.long 0x2C 12. " [13] ,Interrupt Pending Bit[13]" "No interrupt,Interrupt" newline bitfld.long 0x2C 11. " [12] ,Interrupt Pending Bit[12]" "No interrupt,Interrupt" bitfld.long 0x2C 10. " [11] ,Interrupt Pending Bit[11]" "No interrupt,Interrupt" newline bitfld.long 0x2C 9. " [10] ,Interrupt Pending Bit[10]" "No interrupt,Interrupt" bitfld.long 0x2C 8. " [9] ,Interrupt Pending Bit[9]" "No interrupt,Interrupt" newline bitfld.long 0x2C 7. " [8] ,Interrupt Pending Bit[8]" "No interrupt,Interrupt" bitfld.long 0x2C 6. " [7] ,Interrupt Pending Bit[7]" "No interrupt,Interrupt" newline bitfld.long 0x2C 5. " [6] ,Interrupt Pending Bit[6]" "No interrupt,Interrupt" bitfld.long 0x2C 4. " [5] ,Interrupt Pending Bit[5]" "No interrupt,Interrupt" newline bitfld.long 0x2C 3. " [4] ,Interrupt Pending Bit[4]" "No interrupt,Interrupt" bitfld.long 0x2C 2. " [3] ,Interrupt Pending Bit[3]" "No interrupt,Interrupt" newline bitfld.long 0x2C 1. " [2] ,Interrupt Pending Bit[2]" "No interrupt,Interrupt" bitfld.long 0x2C 0. " [1] ,Interrupt Pending Bit[1]" "No interrupt,Interrupt" line.long 0x30 "INTPEN34,Interrupt Pending 3-4" bitfld.long 0x30 31. " INTPND[64] ,Interrupt Pending Bit[64]" "No interrupt,Interrupt" bitfld.long 0x30 30. " [63] ,Interrupt Pending Bit[63]" "No interrupt,Interrupt" newline bitfld.long 0x30 29. " [62] ,Interrupt Pending Bit[62]" "No interrupt,Interrupt" bitfld.long 0x30 28. " [61] ,Interrupt Pending Bit[61]" "No interrupt,Interrupt" newline bitfld.long 0x30 27. " [60] ,Interrupt Pending Bit[60]" "No interrupt,Interrupt" bitfld.long 0x30 26. " [59] ,Interrupt Pending Bit[59]" "No interrupt,Interrupt" newline bitfld.long 0x30 25. " [58] ,Interrupt Pending Bit[58]" "No interrupt,Interrupt" bitfld.long 0x30 24. " [57] ,Interrupt Pending Bit[57]" "No interrupt,Interrupt" newline bitfld.long 0x30 23. " [56] ,Interrupt Pending Bit[56]" "No interrupt,Interrupt" bitfld.long 0x30 22. " [55] ,Interrupt Pending Bit[55]" "No interrupt,Interrupt" newline bitfld.long 0x30 21. " [54] ,Interrupt Pending Bit[54]" "No interrupt,Interrupt" bitfld.long 0x30 20. " [53] ,Interrupt Pending Bit[53]" "No interrupt,Interrupt" newline bitfld.long 0x30 19. " [52] ,Interrupt Pending Bit[52]" "No interrupt,Interrupt" bitfld.long 0x30 18. " [51] ,Interrupt Pending Bit[51]" "No interrupt,Interrupt" newline bitfld.long 0x30 17. " [50] ,Interrupt Pending Bit[50]" "No interrupt,Interrupt" bitfld.long 0x30 16. " [49] ,Interrupt Pending Bit[49]" "No interrupt,Interrupt" newline bitfld.long 0x30 15. " [48] ,Interrupt Pending Bit[48]" "No interrupt,Interrupt" bitfld.long 0x30 14. " [47] ,Interrupt Pending Bit[47]" "No interrupt,Interrupt" newline bitfld.long 0x30 13. " [46] ,Interrupt Pending Bit[46]" "No interrupt,Interrupt" bitfld.long 0x30 12. " [45] ,Interrupt Pending Bit[45]" "No interrupt,Interrupt" newline bitfld.long 0x30 11. " [44] ,Interrupt Pending Bit[44]" "No interrupt,Interrupt" bitfld.long 0x30 10. " [43] ,Interrupt Pending Bit[43]" "No interrupt,Interrupt" newline bitfld.long 0x30 9. " [42] ,Interrupt Pending Bit[42]" "No interrupt,Interrupt" bitfld.long 0x30 8. " [41] ,Interrupt Pending Bit[41]" "No interrupt,Interrupt" newline bitfld.long 0x30 7. " [40] ,Interrupt Pending Bit[40]" "No interrupt,Interrupt" bitfld.long 0x30 6. " [39] ,Interrupt Pending Bit[39]" "No interrupt,Interrupt" newline bitfld.long 0x30 5. " [38] ,Interrupt Pending Bit[38]" "No interrupt,Interrupt" bitfld.long 0x30 4. " [37] ,Interrupt Pending Bit[37]" "No interrupt,Interrupt" newline bitfld.long 0x30 3. " [36] ,Interrupt Pending Bit[36]" "No interrupt,Interrupt" bitfld.long 0x30 2. " [35] ,Interrupt Pending Bit[35]" "No interrupt,Interrupt" newline bitfld.long 0x30 1. " [34] ,Interrupt Pending Bit[34]" "No interrupt,Interrupt" bitfld.long 0x30 0. " [33] ,Interrupt Pending Bit[33]" "No interrupt,Interrupt" line.long 0x34 "INTPEN56,Interrupt Pending 5-6" bitfld.long 0x34 31. " INTPND[96] ,Interrupt Pending Bit[96]" "No interrupt,Interrupt" bitfld.long 0x34 30. " [95] ,Interrupt Pending Bit[95]" "No interrupt,Interrupt" newline bitfld.long 0x34 29. " [94] ,Interrupt Pending Bit[94]" "No interrupt,Interrupt" bitfld.long 0x34 28. " [93] ,Interrupt Pending Bit[93]" "No interrupt,Interrupt" newline bitfld.long 0x34 27. " [92] ,Interrupt Pending Bit[92]" "No interrupt,Interrupt" bitfld.long 0x34 26. " [91] ,Interrupt Pending Bit[91]" "No interrupt,Interrupt" newline bitfld.long 0x34 25. " [90] ,Interrupt Pending Bit[90]" "No interrupt,Interrupt" bitfld.long 0x34 24. " [89] ,Interrupt Pending Bit[89]" "No interrupt,Interrupt" newline bitfld.long 0x34 23. " [88] ,Interrupt Pending Bit[88]" "No interrupt,Interrupt" bitfld.long 0x34 22. " [87] ,Interrupt Pending Bit[87]" "No interrupt,Interrupt" newline bitfld.long 0x34 21. " [86] ,Interrupt Pending Bit[86]" "No interrupt,Interrupt" bitfld.long 0x34 20. " [85] ,Interrupt Pending Bit[85]" "No interrupt,Interrupt" newline bitfld.long 0x34 19. " [84] ,Interrupt Pending Bit[84]" "No interrupt,Interrupt" bitfld.long 0x34 18. " [83] ,Interrupt Pending Bit[83]" "No interrupt,Interrupt" newline bitfld.long 0x34 17. " [82] ,Interrupt Pending Bit[82]" "No interrupt,Interrupt" bitfld.long 0x34 16. " [81] ,Interrupt Pending Bit[81]" "No interrupt,Interrupt" newline bitfld.long 0x34 15. " [80] ,Interrupt Pending Bit[80]" "No interrupt,Interrupt" bitfld.long 0x34 14. " [79] ,Interrupt Pending Bit[79]" "No interrupt,Interrupt" newline bitfld.long 0x34 13. " [78] ,Interrupt Pending Bit[78]" "No interrupt,Interrupt" bitfld.long 0x34 12. " [77] ,Interrupt Pending Bit[77]" "No interrupt,Interrupt" newline bitfld.long 0x34 11. " [76] ,Interrupt Pending Bit[76]" "No interrupt,Interrupt" bitfld.long 0x34 10. " [75] ,Interrupt Pending Bit[75]" "No interrupt,Interrupt" newline bitfld.long 0x34 9. " [74] ,Interrupt Pending Bit[74]" "No interrupt,Interrupt" bitfld.long 0x34 8. " [73] ,Interrupt Pending Bit[73]" "No interrupt,Interrupt" newline bitfld.long 0x34 7. " [72] ,Interrupt Pending Bit[72]" "No interrupt,Interrupt" bitfld.long 0x34 6. " [71] ,Interrupt Pending Bit[71]" "No interrupt,Interrupt" newline bitfld.long 0x34 5. " [70] ,Interrupt Pending Bit[70]" "No interrupt,Interrupt" bitfld.long 0x34 4. " [69] ,Interrupt Pending Bit[69]" "No interrupt,Interrupt" newline bitfld.long 0x34 3. " [68] ,Interrupt Pending Bit[68]" "No interrupt,Interrupt" bitfld.long 0x34 2. " [67] ,Interrupt Pending Bit[67]" "No interrupt,Interrupt" newline bitfld.long 0x34 1. " [66] ,Interrupt Pending Bit[66]" "No interrupt,Interrupt" bitfld.long 0x34 0. " [65] ,Interrupt Pending Bit[65]" "No interrupt,Interrupt" line.long 0x38 "INTPEN78,Interrupt Pending 7-8" bitfld.long 0x38 31. " INTPND[128] ,Interrupt Pending Bit[128]" "No interrupt,Interrupt" bitfld.long 0x38 30. " [127] ,Interrupt Pending Bit[127]" "No interrupt,Interrupt" newline bitfld.long 0x38 29. " [126] ,Interrupt Pending Bit[126]" "No interrupt,Interrupt" bitfld.long 0x38 28. " [125] ,Interrupt Pending Bit[125]" "No interrupt,Interrupt" newline bitfld.long 0x38 27. " [124] ,Interrupt Pending Bit[124]" "No interrupt,Interrupt" bitfld.long 0x38 26. " [123] ,Interrupt Pending Bit[123]" "No interrupt,Interrupt" newline bitfld.long 0x38 25. " [122] ,Interrupt Pending Bit[122]" "No interrupt,Interrupt" bitfld.long 0x38 24. " [121] ,Interrupt Pending Bit[121]" "No interrupt,Interrupt" newline bitfld.long 0x38 23. " [120] ,Interrupt Pending Bit[120]" "No interrupt,Interrupt" bitfld.long 0x38 22. " [119] ,Interrupt Pending Bit[119]" "No interrupt,Interrupt" newline bitfld.long 0x38 21. " [118] ,Interrupt Pending Bit[118]" "No interrupt,Interrupt" bitfld.long 0x38 20. " [117] ,Interrupt Pending Bit[117]" "No interrupt,Interrupt" newline bitfld.long 0x38 19. " [116] ,Interrupt Pending Bit[116]" "No interrupt,Interrupt" bitfld.long 0x38 18. " [115] ,Interrupt Pending Bit[115]" "No interrupt,Interrupt" newline bitfld.long 0x38 17. " [114] ,Interrupt Pending Bit[114]" "No interrupt,Interrupt" bitfld.long 0x38 16. " [113] ,Interrupt Pending Bit[113]" "No interrupt,Interrupt" newline bitfld.long 0x38 15. " [112] ,Interrupt Pending Bit[112]" "No interrupt,Interrupt" bitfld.long 0x38 14. " [111] ,Interrupt Pending Bit[111]" "No interrupt,Interrupt" newline bitfld.long 0x38 13. " [110] ,Interrupt Pending Bit[110]" "No interrupt,Interrupt" bitfld.long 0x38 12. " [109] ,Interrupt Pending Bit[109]" "No interrupt,Interrupt" newline bitfld.long 0x38 11. " [108] ,Interrupt Pending Bit[108]" "No interrupt,Interrupt" bitfld.long 0x38 10. " [107] ,Interrupt Pending Bit[107]" "No interrupt,Interrupt" newline bitfld.long 0x38 9. " [106] ,Interrupt Pending Bit[106]" "No interrupt,Interrupt" bitfld.long 0x38 8. " [105] ,Interrupt Pending Bit[105]" "No interrupt,Interrupt" newline bitfld.long 0x38 7. " [104] ,Interrupt Pending Bit[104]" "No interrupt,Interrupt" bitfld.long 0x38 6. " [103] ,Interrupt Pending Bit[103]" "No interrupt,Interrupt" newline bitfld.long 0x38 5. " [102] ,Interrupt Pending Bit[102]" "No interrupt,Interrupt" bitfld.long 0x38 4. " [101] ,Interrupt Pending Bit[101]" "No interrupt,Interrupt" newline bitfld.long 0x38 3. " [100] ,Interrupt Pending Bit[100]" "No interrupt,Interrupt" bitfld.long 0x38 2. " [99] ,Interrupt Pending Bit[99]" "No interrupt,Interrupt" newline bitfld.long 0x38 1. " [98] ,Interrupt Pending Bit[98]" "No interrupt,Interrupt" bitfld.long 0x38 0. " [97] ,Interrupt Pending Bit[97]" "No interrupt,Interrupt" line.long 0x3C "MVAL,Message Valid X" bitfld.long 0x3C 14.--15. " MSGVALREG8 ,Message Valid Register 8" "0,1,2,3" bitfld.long 0x3C 12.--13. " [7] ,Message Valid Register 7" "0,1,2,3" bitfld.long 0x3C 10.--11. " [6] ,Message Valid Register 6" "0,1,2,3" bitfld.long 0x3C 8.--9. " [5] ,Message Valid Register 5" "0,1,2,3" newline bitfld.long 0x3C 6.--7. " [4] ,Message Valid Register 4" "0,1,2,3" bitfld.long 0x3C 4.--5. " [3] ,Message Valid Register 3" "0,1,2,3" bitfld.long 0x3C 2.--3. " [2] ,Message Valid Register 2" "0,1,2,3" bitfld.long 0x3C 0.--1. " [1] ,Message Valid Register 1" "0,1,2,3" line.long 0x40 "MVAL12,Message Valid 1-2" bitfld.long 0x40 31. " MSGVAL[32] ,Message Valid Bit[32]" "Ignored,Configured" bitfld.long 0x40 30. " [31] ,Message Valid Bit[31]" "Ignored,Configured" newline bitfld.long 0x40 29. " [30] ,Message Valid Bit[30]" "Ignored,Configured" bitfld.long 0x40 28. " [29] ,Message Valid Bit[29]" "Ignored,Configured" newline bitfld.long 0x40 27. " [28] ,Message Valid Bit[28]" "Ignored,Configured" bitfld.long 0x40 26. " [27] ,Message Valid Bit[27]" "Ignored,Configured" newline bitfld.long 0x40 25. " [26] ,Message Valid Bit[26]" "Ignored,Configured" bitfld.long 0x40 24. " [25] ,Message Valid Bit[25]" "Ignored,Configured" newline bitfld.long 0x40 23. " [24] ,Message Valid Bit[24]" "Ignored,Configured" bitfld.long 0x40 22. " [23] ,Message Valid Bit[23]" "Ignored,Configured" newline bitfld.long 0x40 21. " [22] ,Message Valid Bit[22]" "Ignored,Configured" bitfld.long 0x40 20. " [21] ,Message Valid Bit[21]" "Ignored,Configured" newline bitfld.long 0x40 19. " [20] ,Message Valid Bit[20]" "Ignored,Configured" bitfld.long 0x40 18. " [19] ,Message Valid Bit[19]" "Ignored,Configured" newline bitfld.long 0x40 17. " [18] ,Message Valid Bit[18]" "Ignored,Configured" bitfld.long 0x40 16. " [17] ,Message Valid Bit[17]" "Ignored,Configured" newline bitfld.long 0x40 15. " [16] ,Message Valid Bit[16]" "Ignored,Configured" bitfld.long 0x40 14. " [15] ,Message Valid Bit[15]" "Ignored,Configured" newline bitfld.long 0x40 13. " [14] ,Message Valid Bit[14]" "Ignored,Configured" bitfld.long 0x40 12. " [13] ,Message Valid Bit[13]" "Ignored,Configured" newline bitfld.long 0x40 11. " [12] ,Message Valid Bit[12]" "Ignored,Configured" bitfld.long 0x40 10. " [11] ,Message Valid Bit[11]" "Ignored,Configured" newline bitfld.long 0x40 9. " [10] ,Message Valid Bit[10]" "Ignored,Configured" bitfld.long 0x40 8. " [9] ,Message Valid Bit[9]" "Ignored,Configured" newline bitfld.long 0x40 7. " [8] ,Message Valid Bit[8]" "Ignored,Configured" bitfld.long 0x40 6. " [7] ,Message Valid Bit[7]" "Ignored,Configured" newline bitfld.long 0x40 5. " [6] ,Message Valid Bit[6]" "Ignored,Configured" bitfld.long 0x40 4. " [5] ,Message Valid Bit[5]" "Ignored,Configured" newline bitfld.long 0x40 3. " [4] ,Message Valid Bit[4]" "Ignored,Configured" bitfld.long 0x40 2. " [3] ,Message Valid Bit[3]" "Ignored,Configured" newline bitfld.long 0x40 1. " [2] ,Message Valid Bit[2]" "Ignored,Configured" bitfld.long 0x40 0. " [1] ,Message Valid Bit[1]" "Ignored,Configured" line.long 0x44 "MVAL34,Message Valid 3-4" bitfld.long 0x44 31. " MSGVAl[64] ,Message Valid Bit[64]" "Ignored,Configured" bitfld.long 0x44 30. " [63] ,Message Valid Bit[63]" "Ignored,Configured" newline bitfld.long 0x44 29. " [62] ,Message Valid Bit[62]" "Ignored,Configured" bitfld.long 0x44 28. " [61] ,Message Valid Bit[61]" "Ignored,Configured" newline bitfld.long 0x44 27. " [60] ,Message Valid Bit[60]" "Ignored,Configured" bitfld.long 0x44 26. " [59] ,Message Valid Bit[59]" "Ignored,Configured" newline bitfld.long 0x44 25. " [58] ,Message Valid Bit[58]" "Ignored,Configured" bitfld.long 0x44 24. " [57] ,Message Valid Bit[57]" "Ignored,Configured" newline bitfld.long 0x44 23. " [56] ,Message Valid Bit[56]" "Ignored,Configured" bitfld.long 0x44 22. " [55] ,Message Valid Bit[55]" "Ignored,Configured" newline bitfld.long 0x44 21. " [54] ,Message Valid Bit[54]" "Ignored,Configured" bitfld.long 0x44 20. " [53] ,Message Valid Bit[53]" "Ignored,Configured" newline bitfld.long 0x44 19. " [52] ,Message Valid Bit[52]" "Ignored,Configured" bitfld.long 0x44 18. " [51] ,Message Valid Bit[51]" "Ignored,Configured" newline bitfld.long 0x44 17. " [50] ,Message Valid Bit[50]" "Ignored,Configured" bitfld.long 0x44 16. " [49] ,Message Valid Bit[49]" "Ignored,Configured" newline bitfld.long 0x44 15. " [48] ,Message Valid Bit[48]" "Ignored,Configured" bitfld.long 0x44 14. " [47] ,Message Valid Bit[47]" "Ignored,Configured" newline bitfld.long 0x44 13. " [46] ,Message Valid Bit[46]" "Ignored,Configured" bitfld.long 0x44 12. " [45] ,Message Valid Bit[45]" "Ignored,Configured" newline bitfld.long 0x44 11. " [44] ,Message Valid Bit[44]" "Ignored,Configured" bitfld.long 0x44 10. " [43] ,Message Valid Bit[43]" "Ignored,Configured" newline bitfld.long 0x44 9. " [42] ,Message Valid Bit[42]" "Ignored,Configured" bitfld.long 0x44 8. " [41] ,Message Valid Bit[41]" "Ignored,Configured" newline bitfld.long 0x44 7. " [40] ,Message Valid Bit[40]" "Ignored,Configured" bitfld.long 0x44 6. " [39] ,Message Valid Bit[39]" "Ignored,Configured" newline bitfld.long 0x44 5. " [38] ,Message Valid Bit[38]" "Ignored,Configured" bitfld.long 0x44 4. " [37] ,Message Valid Bit[37]" "Ignored,Configured" newline bitfld.long 0x44 3. " [36] ,Message Valid Bit[36]" "Ignored,Configured" bitfld.long 0x44 2. " [35] ,Message Valid Bit[35]" "Ignored,Configured" newline bitfld.long 0x44 1. " [34] ,Message Valid Bit[34]" "Ignored,Configured" bitfld.long 0x44 0. " [33] ,Message Valid Bit[33]" "Ignored,Configured" line.long 0x48 "MVAL56,Message Valid 5-6" bitfld.long 0x48 31. " MSGVAl[96] ,Message Valid Bit[96]" "Ignored,Configured" bitfld.long 0x48 30. " [95] ,Message Valid Bit[95]" "Ignored,Configured" newline bitfld.long 0x48 29. " [94] ,Message Valid Bit[94]" "Ignored,Configured" bitfld.long 0x48 28. " [93] ,Message Valid Bit[93]" "Ignored,Configured" newline bitfld.long 0x48 27. " [92] ,Message Valid Bit[92]" "Ignored,Configured" bitfld.long 0x48 26. " [91] ,Message Valid Bit[91]" "Ignored,Configured" newline bitfld.long 0x48 25. " [90] ,Message Valid Bit[90]" "Ignored,Configured" bitfld.long 0x48 24. " [89] ,Message Valid Bit[89]" "Ignored,Configured" newline bitfld.long 0x48 23. " [88] ,Message Valid Bit[88]" "Ignored,Configured" bitfld.long 0x48 22. " [87] ,Message Valid Bit[87]" "Ignored,Configured" newline bitfld.long 0x48 21. " [86] ,Message Valid Bit[86]" "Ignored,Configured" bitfld.long 0x48 20. " [85] ,Message Valid Bit[85]" "Ignored,Configured" newline bitfld.long 0x48 19. " [84] ,Message Valid Bit[84]" "Ignored,Configured" bitfld.long 0x48 18. " [83] ,Message Valid Bit[83]" "Ignored,Configured" newline bitfld.long 0x48 17. " [82] ,Message Valid Bit[82]" "Ignored,Configured" bitfld.long 0x48 16. " [81] ,Message Valid Bit[81]" "Ignored,Configured" newline bitfld.long 0x48 15. " [80] ,Message Valid Bit[80]" "Ignored,Configured" bitfld.long 0x48 14. " [79] ,Message Valid Bit[79]" "Ignored,Configured" newline bitfld.long 0x48 13. " [78] ,Message Valid Bit[78]" "Ignored,Configured" bitfld.long 0x48 12. " [77] ,Message Valid Bit[77]" "Ignored,Configured" newline bitfld.long 0x48 11. " [76] ,Message Valid Bit[76]" "Ignored,Configured" bitfld.long 0x48 10. " [75] ,Message Valid Bit[75]" "Ignored,Configured" newline bitfld.long 0x48 9. " [74] ,Message Valid Bit[74]" "Ignored,Configured" bitfld.long 0x48 8. " [73] ,Message Valid Bit[73]" "Ignored,Configured" newline bitfld.long 0x48 7. " [72] ,Message Valid Bit[72]" "Ignored,Configured" bitfld.long 0x48 6. " [71] ,Message Valid Bit[71]" "Ignored,Configured" newline bitfld.long 0x48 5. " [70] ,Message Valid Bit[70]" "Ignored,Configured" bitfld.long 0x48 4. " [69] ,Message Valid Bit[69]" "Ignored,Configured" newline bitfld.long 0x48 3. " [68] ,Message Valid Bit[68]" "Ignored,Configured" bitfld.long 0x48 2. " [67] ,Message Valid Bit[67]" "Ignored,Configured" newline bitfld.long 0x48 1. " [66] ,Message Valid Bit[66]" "Ignored,Configured" bitfld.long 0x48 0. " [65] ,Message Valid Bit[65]" "Ignored,Configured" line.long 0x4C "MVAL78,Message Valid 7-8" bitfld.long 0x4C 31. " MSGVAl[128] ,Message Valid Bit[128]" "Ignored,Configured" bitfld.long 0x4C 30. " [127] ,Message Valid Bit[127]" "Ignored,Configured" newline bitfld.long 0x4C 29. " [126] ,Message Valid Bit[126]" "Ignored,Configured" bitfld.long 0x4C 28. " [125] ,Message Valid Bit[125]" "Ignored,Configured" newline bitfld.long 0x4C 27. " [124] ,Message Valid Bit[124]" "Ignored,Configured" bitfld.long 0x4C 26. " [123] ,Message Valid Bit[123]" "Ignored,Configured" newline bitfld.long 0x4C 25. " [122] ,Message Valid Bit[122]" "Ignored,Configured" bitfld.long 0x4C 24. " [121] ,Message Valid Bit[121]" "Ignored,Configured" newline bitfld.long 0x4C 23. " [120] ,Message Valid Bit[120]" "Ignored,Configured" bitfld.long 0x4C 22. " [119] ,Message Valid Bit[119]" "Ignored,Configured" newline bitfld.long 0x4C 21. " [118] ,Message Valid Bit[118]" "Ignored,Configured" bitfld.long 0x4C 20. " [117] ,Message Valid Bit[117]" "Ignored,Configured" newline bitfld.long 0x4C 19. " [116] ,Message Valid Bit[116]" "Ignored,Configured" bitfld.long 0x4C 18. " [115] ,Message Valid Bit[115]" "Ignored,Configured" newline bitfld.long 0x4C 17. " [114] ,Message Valid Bit[114]" "Ignored,Configured" bitfld.long 0x4C 16. " [113] ,Message Valid Bit[113]" "Ignored,Configured" newline bitfld.long 0x4C 15. " [112] ,Message Valid Bit[112]" "Ignored,Configured" bitfld.long 0x4C 14. " [111] ,Message Valid Bit[111]" "Ignored,Configured" newline bitfld.long 0x4C 13. " [110] ,Message Valid Bit[110]" "Ignored,Configured" bitfld.long 0x4C 12. " [109] ,Message Valid Bit[109]" "Ignored,Configured" newline bitfld.long 0x4C 11. " [108] ,Message Valid Bit[108]" "Ignored,Configured" bitfld.long 0x4C 10. " [107] ,Message Valid Bit[107]" "Ignored,Configured" newline bitfld.long 0x4C 9. " [106] ,Message Valid Bit[106]" "Ignored,Configured" bitfld.long 0x4C 8. " [105] ,Message Valid Bit[105]" "Ignored,Configured" newline bitfld.long 0x4C 7. " [104] ,Message Valid Bit[104]" "Ignored,Configured" bitfld.long 0x4C 6. " [103] ,Message Valid Bit[103]" "Ignored,Configured" newline bitfld.long 0x4C 5. " [102] ,Message Valid Bit[102]" "Ignored,Configured" bitfld.long 0x4C 4. " [101] ,Message Valid Bit[101]" "Ignored,Configured" newline bitfld.long 0x4C 3. " [100] ,Message Valid Bit[100]" "Ignored,Configured" bitfld.long 0x4C 2. " [99] ,Message Valid Bit[99]" "Ignored,Configured" newline bitfld.long 0x4C 1. " [98] ,Message Valid Bit[98]" "Ignored,Configured" bitfld.long 0x4C 0. " [97] ,Message Valid Bit[97]" "Ignored,Configured" group.long 0xD8++0x0F line.long 0x00 "INTPMX12,Interrupt Multiplexer 1-2" bitfld.long 0x00 31. " INTPNDMUX[32] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[32]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 30. " [31] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[31]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x00 29. " [30] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[30]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 28. " [29] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[29]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x00 27. " [28] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[28]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 26. " [27] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[27]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x00 25. " [26] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[26]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 24. " [25] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[25]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x00 23. " [24] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[24]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 22. " [23] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[23]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x00 21. " [22] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[22]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 20. " [21] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[21]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x00 19. " [20] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[20]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 18. " [19] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[19]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x00 17. " [18] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[18]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 16. " [17] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[17]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x00 15. " [16] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[16]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 14. " [15] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[15]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x00 13. " [14] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[14]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 12. " [13] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[13]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x00 11. " [12] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[12]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 10. " [11] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[11]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x00 9. " [10] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[10]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 8. " [9] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[9]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x00 7. " [8] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[8]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 6. " [7] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[7]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x00 5. " [6] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[6]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 4. " [5] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[5]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x00 3. " [4] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[4]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 2. " [3] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[3]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x00 1. " [2] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[2]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 0. " [1] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[1]" "DCAN0INT,DCAN1INT" line.long 0x04 "INTPMX34,Interrupt Multiplexer 3-4" bitfld.long 0x04 31. " INTPNDMUX[64] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[64]" "DCAN0INT,DCAN1INT" bitfld.long 0x04 30. " [63] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[63]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x04 29. " [62] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[62]" "DCAN0INT,DCAN1INT" bitfld.long 0x04 28. " [61] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[61]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x04 27. " [60] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[60]" "DCAN0INT,DCAN1INT" bitfld.long 0x04 26. " [59] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[59]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x04 25. " [58] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[58]" "DCAN0INT,DCAN1INT" bitfld.long 0x04 24. " [57] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[57]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x04 23. " [56] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[56]" "DCAN0INT,DCAN1INT" bitfld.long 0x04 22. " [55] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[55]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x04 21. " [54] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[54]" "DCAN0INT,DCAN1INT" bitfld.long 0x04 20. " [53] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[53]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x04 19. " [52] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[52]" "DCAN0INT,DCAN1INT" bitfld.long 0x04 18. " [51] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[51]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x04 17. " [50] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[50]" "DCAN0INT,DCAN1INT" bitfld.long 0x04 16. " [49] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[49]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x04 15. " [48] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[48]" "DCAN0INT,DCAN1INT" bitfld.long 0x04 14. " [47] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[47]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x04 13. " [46] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[46]" "DCAN0INT,DCAN1INT" bitfld.long 0x04 12. " [45] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[45]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x04 11. " [44] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[44]" "DCAN0INT,DCAN1INT" bitfld.long 0x04 10. " [43] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[43]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x04 9. " [42] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[42]" "DCAN0INT,DCAN1INT" bitfld.long 0x04 8. " [41] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[41]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x04 7. " [40] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[40]" "DCAN0INT,DCAN1INT" bitfld.long 0x04 6. " [39] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[39]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x04 5. " [38] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[38]" "DCAN0INT,DCAN1INT" bitfld.long 0x04 4. " [37] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[37]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x04 3. " [36] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[36]" "DCAN0INT,DCAN1INT" bitfld.long 0x04 2. " [35] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[35]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x04 1. " [34] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[34]" "DCAN0INT,DCAN1INT" bitfld.long 0x04 0. " [33] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[33]" "DCAN0INT,DCAN1INT" line.long 0x08 "INTPMX56,Interrupt Multiplexer 5-6" bitfld.long 0x08 31. " INTPNDMUX[96] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[96]" "DCAN0INT,DCAN1INT" bitfld.long 0x08 30. " [95] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[95]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x08 29. " [94] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[94]" "DCAN0INT,DCAN1INT" bitfld.long 0x08 28. " [93] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[93]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x08 27. " [92] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[92]" "DCAN0INT,DCAN1INT" bitfld.long 0x08 26. " [91] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[91]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x08 25. " [90] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[90]" "DCAN0INT,DCAN1INT" bitfld.long 0x08 24. " [89] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[89]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x08 23. " [88] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[88]" "DCAN0INT,DCAN1INT" bitfld.long 0x08 22. " [87] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[87]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x08 21. " [86] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[86]" "DCAN0INT,DCAN1INT" bitfld.long 0x08 20. " [85] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[85]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x08 19. " [84] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[84]" "DCAN0INT,DCAN1INT" bitfld.long 0x08 18. " [83] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[83]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x08 17. " [82] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[82]" "DCAN0INT,DCAN1INT" bitfld.long 0x08 16. " [81] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[81]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x08 15. " [80] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[80]" "DCAN0INT,DCAN1INT" bitfld.long 0x08 14. " [79] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[79]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x08 13. " [78] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[78]" "DCAN0INT,DCAN1INT" bitfld.long 0x08 12. " [77] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[77]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x08 11. " [76] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[76]" "DCAN0INT,DCAN1INT" bitfld.long 0x08 10. " [75] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[75]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x08 9. " [74] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[74]" "DCAN0INT,DCAN1INT" bitfld.long 0x08 8. " [73] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[73]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x08 7. " [72] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[72]" "DCAN0INT,DCAN1INT" bitfld.long 0x08 6. " [71] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[71]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x08 5. " [70] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[70]" "DCAN0INT,DCAN1INT" bitfld.long 0x08 4. " [69] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[69]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x08 3. " [68] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[68]" "DCAN0INT,DCAN1INT" bitfld.long 0x08 2. " [67] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[67]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x08 1. " [66] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[66]" "DCAN0INT,DCAN1INT" bitfld.long 0x08 0. " [65] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[65]" "DCAN0INT,DCAN1INT" line.long 0x0C "INTPMX78,Interrupt Multiplexer 7-8" bitfld.long 0x0C 31. " INTPNDMUX[128] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[128]" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 30. " [127] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[127]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x0C 29. " [126] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[126]" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 28. " [125] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[125]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x0C 27. " [124] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[124]" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 26. " [123] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[123]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x0C 25. " [122] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[122]" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 24. " [121] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[121]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x0C 23. " [120] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[120]" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 22. " [119] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[119]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x0C 21. " [118] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[118]" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 20. " [117] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[117]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x0C 19. " [116] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[116]" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 18. " [115] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[115]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x0C 17. " [114] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[114]" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 16. " [113] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[113]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x0C 15. " [112] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[112]" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 14. " [111] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[111]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x0C 13. " [110] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[110]" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 12. " [109] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[109]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x0C 11. " [108] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[108]" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 10. " [107] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[107]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x0C 9. " [106] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[106]" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 8. " [105] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[105]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x0C 7. " [104] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[104]" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 6. " [103] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[103]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x0C 5. " [102] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[102]" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 4. " [101] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[101]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x0C 3. " [100] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[100]" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 2. " [99] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[99]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x0C 1. " [98] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[98]" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 0. " [97] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[97]" "DCAN0INT,DCAN1INT" group.long 0x100++0x3 "IF1" line.long 0x00 "IF1COM,IF1 Command Mask / Command Request Register" bitfld.long 0x00 23. " WR/RD ,Write / Read direction" "Read,Write" newline bitfld.long 0x00 22. " MASK ,Access Mask Bits" "Unchanged,Identifier Mask+MDir+MXtd" newline bitfld.long 0x00 21. " ARB ,Access Arbitration Bits" "Unchanged,Identifier+Dir+Xtd+MSGVAl" newline bitfld.long 0x00 20. " CONTROL ,Access Control Bits" "Unchanged,Control bits" bitfld.long 0x00 19. " CLRINTPND ,Clear Interrupt Pending Bit" "Low,High" newline bitfld.long 0x00 18. " TXRQST/NEWDAT ,Access Transmission Request Bit" "Not requested,Requested" bitfld.long 0x00 17. " DATA_A ,Access Data Bytes 0-3" "Unchanged,Data bytes 0-3" newline bitfld.long 0x00 16. " DATA_B ,Access Data Bytes 4-7" "Unchanged,Data bytes 4-7" bitfld.long 0x00 15. " BUSY ,Busy Flag" "Not busy,Busy" newline sif (!cpuis("TMS570LS0332")&&!cpuis("TMS570LS0432")) bitfld.long 0x00 14. " DMAACTIVE ,Activation of DMA Feature for Subsequent Internal IF1 Update" "No active,Active" newline endif hexmask.long.byte 0x00 0.--7. 1. " MESSAGE_NUMBER ,Message Number" sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS3137-EP") if (((per.l.be(((ad:0xFFF7DE00+0x100+0x08))))&0x40000000)==0x0) group.long (0x100+0x04)++0x07 line.long 0x0 "IF1MASK,IF1 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering" newline bitfld.long 0x00 28. " ID ,Message Identifier bit[10]" "0,1" bitfld.long 0x00 27. ",Message Identifier bit[9]" "0,1" bitfld.long 0x00 26. ",Message Identifier bit[8]" "0,1" bitfld.long 0x00 25. ",Message Identifier bit[7]" "0,1" bitfld.long 0x00 24. ",Message Identifier bit[6]" "0,1" bitfld.long 0x00 23. ",Message Identifier bit[5]" "0,1" bitfld.long 0x00 22. ",Message Identifier bit[4]" "0,1" bitfld.long 0x00 21. ",Message Identifier bit[3]" "0,1" bitfld.long 0x00 20. ",Message Identifier bit[2]" "0,1" bitfld.long 0x00 19. ",Message Identifier bit[1]" "0,1" bitfld.long 0x00 18. ",Message Identifier bit[0]" "0,1" line.long 0x04 "IF1ARB,IF1 Arbitration Register" bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure" bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit" bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit" hexmask.long.word 0x04 18.--28. 1. " ID ,Message Identifier" else group.long (0x100+0x04)++0x07 line.long 0x00 "IF1MASK,IF1 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering" newline bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1" bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1" bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1" bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1" bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1" bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1" bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1" bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1" bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1" bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1" bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1" bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1" bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1" bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1" bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1" bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1" bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1" bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1" bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1" bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1" bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1" bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1" bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1" bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1" bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1" bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1" bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1" bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1" bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1" line.long 0x04 "IF1ARB,IF1 Arbitation Register" bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure" bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit" bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit" hexmask.long 0x04 0.--28. 1. " ID ,Message Identifier" endif else if (((per.l(((ad:0xFFF7DE00+0x100+0x08))))&0x40000000)==0x0) group.long (0x100+0x04)++0x07 line.long 0x0 "IF1MASK,IF1 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering" newline bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1" bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1" bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1" bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1" bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1" bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1" bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1" bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1" bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1" bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1" bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1" line.long 0x04 "IF1ARB,IF1 Arbitation Register" bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure" bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit" bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit" hexmask.long.word 0x04 18.--28. 1. " ID ,Message Identifier" else group.long (0x100+0x04)++0x07 line.long 0x0 "IF1MASK,IF1 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering" newline bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1" bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1" bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1" bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1" bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1" bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1" bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1" bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1" bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1" bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1" bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1" bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1" bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1" bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1" bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1" bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1" bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1" bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1" bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1" bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1" bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1" bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1" bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1" bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1" bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1" bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1" bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1" bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1" bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1" line.long 0x04 "IF1ARB,IF1 Arbitation Register" bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure" bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit" bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit" hexmask.long 0x04 0.--28. 1. " ID ,Message Identifier" endif endif group.long (0x100+0x0C)++0x0B line.long 0x00 "IF1MCTRL,IF1 Message Control Register" bitfld.long 0x00 15. " NEWDAT ,New Data" "No new data,New data" bitfld.long 0x00 14. " MSGLST ,Message Lost" "Not lost,Lost" bitfld.long 0x00 13. " INTPND ,Interrupt Pending" "No interrupt,Interrupt" newline bitfld.long 0x00 12. " UMASK ,Use Acceptance Mask" "Ignored,Masked" bitfld.long 0x00 11. " TXIE ,Transmit Interrupt Enable" "Unchanged,Set" bitfld.long 0x00 10. " RXIE ,Receive Interrupt Enable" "Unchanged,Set" newline bitfld.long 0x00 9. " RMTEN ,Remote Enable" "Disabled,Enabled" bitfld.long 0x00 8. " TXRQST ,Transmit Request" "Not requested,Requested" bitfld.long 0x00 7. " EOB ,End of Block" "Single/Last,Not last" newline bitfld.long 0x00 0.--3. " DLC[3-0] ,Data Length Code" "0 byte,1 bytes,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes" line.long 0x04 "IF1DATA,IF1 Data A Register" hexmask.long.byte 0x04 24.--31. 1. " DATA[3] ,4th data byte of a CAN Data Frame" hexmask.long.byte 0x04 16.--23. 1. " [2] ,3rd data byte of a CAN Data Frame" hexmask.long.byte 0x04 8.--15. 1. " [1] ,2nd data byte of a CAN Data Frame" hexmask.long.byte 0x04 0.--7. 1. " [0] ,1st data byte of a CAN Data Frame" line.long 0x08 "IF1DATB,IF1 Data B Register" hexmask.long.byte 0x08 24.--31. 1. " DATA[7] ,8th data byte of a CAN Data Frame" hexmask.long.byte 0x08 16.--23. 1. " [6] ,7th data byte of a CAN Data Frame" hexmask.long.byte 0x08 8.--15. 1. " [5] ,6th data byte of a CAN Data Frame" hexmask.long.byte 0x08 0.--7. 1. " [4] ,5th data byte of a CAN Data Frame" group.long 0x120++0x3 "IF2" line.long 0x00 "IF2COM,IF2 Command Mask / Command Request Register" bitfld.long 0x00 23. " WR/RD ,Write / Read direction" "Read,Write" newline bitfld.long 0x00 22. " MASK ,Access Mask Bits" "Unchanged,Identifier Mask+MDir+MXtd" newline bitfld.long 0x00 21. " ARB ,Access Arbitration Bits" "Unchanged,Identifier+Dir+Xtd+MSGVAl" newline bitfld.long 0x00 20. " CONTROL ,Access Control Bits" "Unchanged,Control bits" bitfld.long 0x00 19. " CLRINTPND ,Clear Interrupt Pending Bit" "Low,High" newline bitfld.long 0x00 18. " TXRQST/NEWDAT ,Access Transmission Request Bit" "Not requested,Requested" bitfld.long 0x00 17. " DATA_A ,Access Data Bytes 0-3" "Unchanged,Data bytes 0-3" newline bitfld.long 0x00 16. " DATA_B ,Access Data Bytes 4-7" "Unchanged,Data bytes 4-7" bitfld.long 0x00 15. " BUSY ,Busy Flag" "Not busy,Busy" newline sif (!cpuis("TMS570LS0332")&&!cpuis("TMS570LS0432")) bitfld.long 0x00 14. " DMAACTIVE ,Activation of DMA Feature for Subsequent Internal IF1 Update" "No active,Active" newline endif hexmask.long.byte 0x00 0.--7. 1. " MESSAGE_NUMBER ,Message Number" sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS3137-EP") if (((per.l.be(((ad:0xFFF7DE00+0x120+0x08))))&0x40000000)==0x0) group.long (0x120+0x04)++0x07 line.long 0x0 "IF2MASK,IF2 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering" newline bitfld.long 0x00 28. " ID ,Message Identifier bit[10]" "0,1" bitfld.long 0x00 27. ",Message Identifier bit[9]" "0,1" bitfld.long 0x00 26. ",Message Identifier bit[8]" "0,1" bitfld.long 0x00 25. ",Message Identifier bit[7]" "0,1" bitfld.long 0x00 24. ",Message Identifier bit[6]" "0,1" bitfld.long 0x00 23. ",Message Identifier bit[5]" "0,1" bitfld.long 0x00 22. ",Message Identifier bit[4]" "0,1" bitfld.long 0x00 21. ",Message Identifier bit[3]" "0,1" bitfld.long 0x00 20. ",Message Identifier bit[2]" "0,1" bitfld.long 0x00 19. ",Message Identifier bit[1]" "0,1" bitfld.long 0x00 18. ",Message Identifier bit[0]" "0,1" line.long 0x04 "IF2ARB,IF2 Arbitration Register" bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure" bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit" bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit" hexmask.long.word 0x04 18.--28. 1. " ID ,Message Identifier" else group.long (0x120+0x04)++0x07 line.long 0x00 "IF2MASK,IF2 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering" newline bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1" bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1" bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1" bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1" bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1" bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1" bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1" bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1" bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1" bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1" bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1" bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1" bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1" bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1" bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1" bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1" bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1" bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1" bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1" bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1" bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1" bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1" bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1" bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1" bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1" bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1" bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1" bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1" bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1" line.long 0x04 "IF2ARB,IF2 Arbitation Register" bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure" bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit" bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit" hexmask.long 0x04 0.--28. 1. " ID ,Message Identifier" endif else if (((per.l(((ad:0xFFF7DE00+0x120+0x08))))&0x40000000)==0x0) group.long (0x120+0x04)++0x07 line.long 0x0 "IF2MASK,IF2 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering" newline bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1" bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1" bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1" bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1" bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1" bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1" bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1" bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1" bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1" bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1" bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1" line.long 0x04 "IF2ARB,IF2 Arbitation Register" bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure" bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit" bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit" hexmask.long.word 0x04 18.--28. 1. " ID ,Message Identifier" else group.long (0x120+0x04)++0x07 line.long 0x0 "IF2MASK,IF2 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering" newline bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1" bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1" bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1" bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1" bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1" bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1" bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1" bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1" bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1" bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1" bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1" bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1" bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1" bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1" bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1" bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1" bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1" bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1" bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1" bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1" bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1" bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1" bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1" bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1" bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1" bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1" bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1" bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1" bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1" line.long 0x04 "IF2ARB,IF2 Arbitation Register" bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure" bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit" bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit" hexmask.long 0x04 0.--28. 1. " ID ,Message Identifier" endif endif group.long (0x120+0x0C)++0x0B line.long 0x00 "IF2MCTRL,IF2 Message Control Register" bitfld.long 0x00 15. " NEWDAT ,New Data" "No new data,New data" bitfld.long 0x00 14. " MSGLST ,Message Lost" "Not lost,Lost" bitfld.long 0x00 13. " INTPND ,Interrupt Pending" "No interrupt,Interrupt" newline bitfld.long 0x00 12. " UMASK ,Use Acceptance Mask" "Ignored,Masked" bitfld.long 0x00 11. " TXIE ,Transmit Interrupt Enable" "Unchanged,Set" bitfld.long 0x00 10. " RXIE ,Receive Interrupt Enable" "Unchanged,Set" newline bitfld.long 0x00 9. " RMTEN ,Remote Enable" "Disabled,Enabled" bitfld.long 0x00 8. " TXRQST ,Transmit Request" "Not requested,Requested" bitfld.long 0x00 7. " EOB ,End of Block" "Single/Last,Not last" newline bitfld.long 0x00 0.--3. " DLC[3-0] ,Data Length Code" "0 byte,1 bytes,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes" line.long 0x04 "IF2DATA,IF2 Data A Register" hexmask.long.byte 0x04 24.--31. 1. " DATA[3] ,4th data byte of a CAN Data Frame" hexmask.long.byte 0x04 16.--23. 1. " [2] ,3rd data byte of a CAN Data Frame" hexmask.long.byte 0x04 8.--15. 1. " [1] ,2nd data byte of a CAN Data Frame" hexmask.long.byte 0x04 0.--7. 1. " [0] ,1st data byte of a CAN Data Frame" line.long 0x08 "IF2DATB,IF2 Data B Register" hexmask.long.byte 0x08 24.--31. 1. " DATA[7] ,8th data byte of a CAN Data Frame" hexmask.long.byte 0x08 16.--23. 1. " [6] ,7th data byte of a CAN Data Frame" hexmask.long.byte 0x08 8.--15. 1. " [5] ,6th data byte of a CAN Data Frame" hexmask.long.byte 0x08 0.--7. 1. " [4] ,5th data byte of a CAN Data Frame" group.long 0x140++0x3 "IF3" line.long 0x00 "IF3OB,IF3 Observation Register" sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS21*")||cpuis("TMS570LS31*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")) rbitfld.long 0x00 15. " IF3UPD ,IF3 Updata Data" "Not loaded,Loaded" rbitfld.long 0x00 12. " IF3SDB ,IF3 Status of Data B Read Access" "Low,High" rbitfld.long 0x00 11. " IF3SDA ,IF3 Status of Data A Read Access" "Low,High" newline rbitfld.long 0x00 10. " IF3SC ,IF3 Status of Control Bits Read Access" "Low,High" rbitfld.long 0x00 9. " IF3SA ,IF3 Status of Arbitration Data Read Access" "Low,High" rbitfld.long 0x00 8. " IF3SM ,IF3 Status of Mask Data Read Access" "Low,High" else bitfld.long 0x00 15. " IF3UPD ,IF3 Updata Data" "Not loaded,Loaded" bitfld.long 0x00 12. " IF3SDB ,IF3 Status of Data B Read Access" "Low,High" bitfld.long 0x00 11. " IF3SDA ,IF3 Status of Data A Read Access" "Low,High" newline bitfld.long 0x00 10. " IF3SC ,IF3 Status of Control Bits Read Access" "Low,High" bitfld.long 0x00 9. " IF3SA ,IF3 Status of Arbitration Data Read Access" "Low,High" bitfld.long 0x00 8. " IF3SM ,IF3 Status of Mask Data Read Access" "Low,High" endif newline bitfld.long 0x00 4. " DATA_B ,Data B Read Observation" "Not read,Read" bitfld.long 0x00 3. " DATA_A ,Data A Read Observation" "Not read,Read" bitfld.long 0x00 2. " CTRL ,Ctrl Read Observation" "Not read,Read" newline bitfld.long 0x00 1. " ARB ,Arbitration Data Read Observation" "Not read,Read" bitfld.long 0x00 0. " MASK ,Mask Data Read Observation" "Not read,Read" sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*") if (((per.l.be((ad:0xFFF7DE00+0x148)))&0x40000000)==0x0) rgroup.long 0x144++0x07 line.long 0x00 "IF3MASK,IF3 Mask Register" bitfld.long 0x00 31. " MXtd ,Mask Extended Identifier" "No effect,Filtering" bitfld.long 0x00 30. " MDir ,Mask Message Direction" "No effect,Filtering" newline bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1" bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1" bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1" bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1" bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1" bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1" bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1" bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1" bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1" bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1" bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1" line.long 0x04 "IF3ARB,IF3 Arbitation Register" bitfld.long 0x04 31. " MSGVAl ,Message Valid" "Ignored,Configured" bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit" bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit" newline hexmask.long.word 0x04 18.--28. 1. " ID ,Message Identifier" else rgroup.long 0x144++0x07 line.long 0x0 "IF3MASK,IF3 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering" newline bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1" bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1" bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1" bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1" bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1" bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1" bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1" bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1" bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1" bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1" bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1" bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1" bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1" bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1" bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1" bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1" bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1" bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1" bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1" bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1" bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1" bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1" bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1" bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1" bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1" bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1" bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1" bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1" bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1" line.long 0x04 "IF3ARB,IF3 Arbitation Register" bitfld.long 0x04 31. " MSGVAl ,Message Valid" "Ignored,Configured" bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit" bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit" newline hexmask.long 0x04 0.--28. 1. " ID ,Message Identifier" endif else if (((per.l((ad:0xFFF7DE00+0x148)))&0x40000000)==0x0) rgroup.long 0x144++0x07 line.long 0x0 "IF3MASK,IF3 Mask Register" bitfld.long 0x00 31. " MXtd ,Mask Extended Identifier" "No effect,Filtering" bitfld.long 0x00 30. " MDir ,Mask Message Direction" "No effect,Filtering" newline bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1" bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1" bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1" bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1" bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1" bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1" bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1" bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1" bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1" bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1" bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1" line.long 0x04 "IF3ARB,IF3 Arbitation Register" bitfld.long 0x04 31. " MSGVAl ,Message Valid" "Ignored,Configured" bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit" bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit" newline hexmask.long.word 0x04 18.--28. 1. " ID ,Message Identifier" else rgroup.long 0x144++0x07 line.long 0x0 "IF3MASK,IF3 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering" newline bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1" bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1" bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1" bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1" bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1" bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1" bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1" bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1" bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1" bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1" bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1" bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1" bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1" bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1" bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1" bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1" bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1" bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1" bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1" bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1" bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1" bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1" bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1" bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1" bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1" bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1" bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1" bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1" bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1" line.long 0x04 "IF3ARB,IF3 Arbitation Register" bitfld.long 0x04 31. " MSGVAl ,Message Valid" "Ignored,Configured" bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit" bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit" newline hexmask.long 0x04 0.--28. 1. " ID ,Message Identifier" endif endif group.long 0x14C++0x0B line.long 0x00 "IF3MCTRL,IF3 Message Control Register" bitfld.long 0x00 15. " NEWDAT ,New Data" "No new data,New data" bitfld.long 0x00 14. " MSGLST ,Message Lost" "Not lost,Lost" bitfld.long 0x00 13. " INTPND ,Interrupt Pending" "No interrupt,Interrupt" newline bitfld.long 0x00 12. " UMASK ,Use Acceptance Mask" "Ignored,Masked" bitfld.long 0x00 11. " TXIE ,Transmit Interrupt Enable" "Unchanged,Enabled" bitfld.long 0x00 10. " RXIE ,Receive Interrupt Enable" "Unchanged,Enabled" newline bitfld.long 0x00 9. " RMTEN ,Remote Enable" "Unchanged,Enabled" bitfld.long 0x00 8. " TXRQST ,Transmit Request" "Not requested,Requested" bitfld.long 0x00 7. " EOB ,End of Block" "Not last,Single/Last" newline bitfld.long 0x00 0.--3. " DLC[3-0] ,Data Length Code" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes" line.long 0x04 "IF3DATA,IF3 Data A Register" hexmask.long.byte 0x04 24.--31. 1. " DATA[3] ,4th data byte of a CAN Data Frame" hexmask.long.byte 0x04 16.--23. 1. " [2] ,3rd data byte of a CAN Data Frame" hexmask.long.byte 0x04 8.--15. 1. " [1] ,2nd data byte of a CAN Data Frame" hexmask.long.byte 0x04 0.--7. 1. " [0] ,1st data byte of a CAN Data Frame" line.long 0x08 "IF3DATB,IF3 Data B Register" hexmask.long.byte 0x08 24.--31. 1. " DATA[7] ,8th data byte of a CAN Data Frame" hexmask.long.byte 0x08 16.--23. 1. " [6] ,7th data byte of a CAN Data Frame" hexmask.long.byte 0x08 8.--15. 1. " [5] ,6th data byte of a CAN Data Frame" hexmask.long.byte 0x08 0.--7. 1. " [4] ,5th data byte of a CAN Data Frame" group.long 0x160++0x0F line.long 0x0 "IF3UENA2_1,Update Enable 2_1 Register" bitfld.long 0x00 31. " IF3UPDATEEN[32] ,IF3 Update Enabled Bit[32]" "Disabled,Enabled" bitfld.long 0x00 30. " [31] ,IF3 Update Enabled Bit[31]" "Disabled,Enabled" newline bitfld.long 0x00 29. " [30] ,IF3 Update Enabled Bit[30]" "Disabled,Enabled" bitfld.long 0x00 28. " [29] ,IF3 Update Enabled Bit[29]" "Disabled,Enabled" newline bitfld.long 0x00 27. " [28] ,IF3 Update Enabled Bit[28]" "Disabled,Enabled" bitfld.long 0x00 26. " [27] ,IF3 Update Enabled Bit[27]" "Disabled,Enabled" newline bitfld.long 0x00 25. " [26] ,IF3 Update Enabled Bit[26]" "Disabled,Enabled" bitfld.long 0x00 24. " [25] ,IF3 Update Enabled Bit[25]" "Disabled,Enabled" newline bitfld.long 0x00 23. " [24] ,IF3 Update Enabled Bit[24]" "Disabled,Enabled" bitfld.long 0x00 22. " [23] ,IF3 Update Enabled Bit[23]" "Disabled,Enabled" newline bitfld.long 0x00 21. " [22] ,IF3 Update Enabled Bit[22]" "Disabled,Enabled" bitfld.long 0x00 20. " [21] ,IF3 Update Enabled Bit[21]" "Disabled,Enabled" newline bitfld.long 0x00 19. " [20] ,IF3 Update Enabled Bit[20]" "Disabled,Enabled" bitfld.long 0x00 18. " [19] ,IF3 Update Enabled Bit[19]" "Disabled,Enabled" newline bitfld.long 0x00 17. " [18] ,IF3 Update Enabled Bit[18]" "Disabled,Enabled" bitfld.long 0x00 16. " [17] ,IF3 Update Enabled Bit[17]" "Disabled,Enabled" newline bitfld.long 0x00 15. " [16] ,IF3 Update Enabled Bit[16]" "Disabled,Enabled" bitfld.long 0x00 14. " [15] ,IF3 Update Enabled Bit[15]" "Disabled,Enabled" newline bitfld.long 0x00 13. " [14] ,IF3 Update Enabled Bit[14]" "Disabled,Enabled" bitfld.long 0x00 12. " [13] ,IF3 Update Enabled Bit[13]" "Disabled,Enabled" newline bitfld.long 0x00 11. " [12] ,IF3 Update Enabled Bit[12]" "Disabled,Enabled" bitfld.long 0x00 10. " [11] ,IF3 Update Enabled Bit[11]" "Disabled,Enabled" newline bitfld.long 0x00 9. " [10] ,IF3 Update Enabled Bit[10]" "Disabled,Enabled" bitfld.long 0x00 8. " [9] ,IF3 Update Enabled Bit[9]" "Disabled,Enabled" newline bitfld.long 0x00 7. " [8] ,IF3 Update Enabled Bit[8]" "Disabled,Enabled" bitfld.long 0x00 6. " [7] ,IF3 Update Enabled Bit[7]" "Disabled,Enabled" newline bitfld.long 0x00 5. " [6] ,IF3 Update Enabled Bit[6]" "Disabled,Enabled" bitfld.long 0x00 4. " [5] ,IF3 Update Enabled Bit[5]" "Disabled,Enabled" newline bitfld.long 0x00 3. " [4] ,IF3 Update Enabled Bit[4]" "Disabled,Enabled" bitfld.long 0x00 2. " [3] ,IF3 Update Enabled Bit[3]" "Disabled,Enabled" newline bitfld.long 0x00 1. " [2] ,IF3 Update Enabled Bit[2]" "Disabled,Enabled" bitfld.long 0x00 0. " [1] ,IF3 Update Enabled Bit[1]" "Disabled,Enabled" line.long 0x04 "IF3UENA4_3,Update Enable 4_3 Register" bitfld.long 0x04 31. " IF3UPDATEEN[64] ,IF3 Update Enabled Bit[64]" "Disabled,Enabled" bitfld.long 0x04 30. " [63] ,IF3 Update Enabled Bit[63]" "Disabled,Enabled" newline bitfld.long 0x04 29. " [62] ,IF3 Update Enabled Bit[62]" "Disabled,Enabled" bitfld.long 0x04 28. " [61] ,IF3 Update Enabled Bit[61]" "Disabled,Enabled" newline bitfld.long 0x04 27. " [60] ,IF3 Update Enabled Bit[60]" "Disabled,Enabled" bitfld.long 0x04 26. " [59] ,IF3 Update Enabled Bit[59]" "Disabled,Enabled" newline bitfld.long 0x04 25. " [58] ,IF3 Update Enabled Bit[58]" "Disabled,Enabled" bitfld.long 0x04 24. " [57] ,IF3 Update Enabled Bit[57]" "Disabled,Enabled" newline bitfld.long 0x04 23. " [56] ,IF3 Update Enabled Bit[56]" "Disabled,Enabled" bitfld.long 0x04 22. " [55] ,IF3 Update Enabled Bit[55]" "Disabled,Enabled" newline bitfld.long 0x04 21. " [54] ,IF3 Update Enabled Bit[54]" "Disabled,Enabled" bitfld.long 0x04 20. " [53] ,IF3 Update Enabled Bit[53]" "Disabled,Enabled" newline bitfld.long 0x04 19. " [52] ,IF3 Update Enabled Bit[52]" "Disabled,Enabled" bitfld.long 0x04 18. " [51] ,IF3 Update Enabled Bit[51]" "Disabled,Enabled" newline bitfld.long 0x04 17. " [50] ,IF3 Update Enabled Bit[50]" "Disabled,Enabled" bitfld.long 0x04 16. " [49] ,IF3 Update Enabled Bit[49]" "Disabled,Enabled" newline bitfld.long 0x04 15. " [48] ,IF3 Update Enabled Bit[48]" "Disabled,Enabled" bitfld.long 0x04 14. " [47] ,IF3 Update Enabled Bit[47]" "Disabled,Enabled" newline bitfld.long 0x04 13. " [46] ,IF3 Update Enabled Bit[46]" "Disabled,Enabled" bitfld.long 0x04 12. " [45] ,IF3 Update Enabled Bit[45]" "Disabled,Enabled" newline bitfld.long 0x04 11. " [44] ,IF3 Update Enabled Bit[44]" "Disabled,Enabled" bitfld.long 0x04 10. " [43] ,IF3 Update Enabled Bit[43]" "Disabled,Enabled" newline bitfld.long 0x04 9. " [42] ,IF3 Update Enabled Bit[42]" "Disabled,Enabled" bitfld.long 0x04 8. " [41] ,IF3 Update Enabled Bit[41]" "Disabled,Enabled" newline bitfld.long 0x04 7. " [40] ,IF3 Update Enabled Bit[40]" "Disabled,Enabled" bitfld.long 0x04 6. " [39] ,IF3 Update Enabled Bit[39]" "Disabled,Enabled" newline bitfld.long 0x04 5. " [38] ,IF3 Update Enabled Bit[38]" "Disabled,Enabled" bitfld.long 0x04 4. " [37] ,IF3 Update Enabled Bit[37]" "Disabled,Enabled" newline bitfld.long 0x04 3. " [36] ,IF3 Update Enabled Bit[36]" "Disabled,Enabled" bitfld.long 0x04 2. " [35] ,IF3 Update Enabled Bit[35]" "Disabled,Enabled" newline bitfld.long 0x04 1. " [34] ,IF3 Update Enabled Bit[34]" "Disabled,Enabled" bitfld.long 0x04 0. " [33] ,IF3 Update Enabled Bit[33]" "Disabled,Enabled" line.long 0x08 "IF3UENA6_5,Update Enable 6_5 Register" bitfld.long 0x08 31. " IF3UPDATEEN[96] ,IF3 Update Enabled Bit[96]" "Disabled,Enabled" bitfld.long 0x08 30. " [95] ,IF3 Update Enabled Bit[95]" "Disabled,Enabled" newline bitfld.long 0x08 29. " [94] ,IF3 Update Enabled Bit[94]" "Disabled,Enabled" bitfld.long 0x08 28. " [93] ,IF3 Update Enabled Bit[93]" "Disabled,Enabled" newline bitfld.long 0x08 27. " [92] ,IF3 Update Enabled Bit[92]" "Disabled,Enabled" bitfld.long 0x08 26. " [91] ,IF3 Update Enabled Bit[91]" "Disabled,Enabled" newline bitfld.long 0x08 25. " [90] ,IF3 Update Enabled Bit[90]" "Disabled,Enabled" bitfld.long 0x08 24. " [89] ,IF3 Update Enabled Bit[89]" "Disabled,Enabled" newline bitfld.long 0x08 23. " [88] ,IF3 Update Enabled Bit[88]" "Disabled,Enabled" bitfld.long 0x08 22. " [87] ,IF3 Update Enabled Bit[87]" "Disabled,Enabled" newline bitfld.long 0x08 21. " [86] ,IF3 Update Enabled Bit[86]" "Disabled,Enabled" bitfld.long 0x08 20. " [85] ,IF3 Update Enabled Bit[85]" "Disabled,Enabled" newline bitfld.long 0x08 19. " [84] ,IF3 Update Enabled Bit[84]" "Disabled,Enabled" bitfld.long 0x08 18. " [83] ,IF3 Update Enabled Bit[83]" "Disabled,Enabled" newline bitfld.long 0x08 17. " [82] ,IF3 Update Enabled Bit[82]" "Disabled,Enabled" bitfld.long 0x08 16. " [81] ,IF3 Update Enabled Bit[81]" "Disabled,Enabled" newline bitfld.long 0x08 15. " [80] ,IF3 Update Enabled Bit[80]" "Disabled,Enabled" bitfld.long 0x08 14. " [79] ,IF3 Update Enabled Bit[79]" "Disabled,Enabled" newline bitfld.long 0x08 13. " [78] ,IF3 Update Enabled Bit[78]" "Disabled,Enabled" bitfld.long 0x08 12. " [77] ,IF3 Update Enabled Bit[77]" "Disabled,Enabled" newline bitfld.long 0x08 11. " [76] ,IF3 Update Enabled Bit[76]" "Disabled,Enabled" bitfld.long 0x08 10. " [75] ,IF3 Update Enabled Bit[75]" "Disabled,Enabled" newline bitfld.long 0x08 9. " [74] ,IF3 Update Enabled Bit[74]" "Disabled,Enabled" bitfld.long 0x08 8. " [73] ,IF3 Update Enabled Bit[73]" "Disabled,Enabled" newline bitfld.long 0x08 7. " [72] ,IF3 Update Enabled Bit[72]" "Disabled,Enabled" bitfld.long 0x08 6. " [71] ,IF3 Update Enabled Bit[71]" "Disabled,Enabled" newline bitfld.long 0x08 5. " [70] ,IF3 Update Enabled Bit[70]" "Disabled,Enabled" bitfld.long 0x08 4. " [69] ,IF3 Update Enabled Bit[69]" "Disabled,Enabled" newline bitfld.long 0x08 3. " [68] ,IF3 Update Enabled Bit[68]" "Disabled,Enabled" bitfld.long 0x08 2. " [67] ,IF3 Update Enabled Bit[67]" "Disabled,Enabled" newline bitfld.long 0x08 1. " [66] ,IF3 Update Enabled Bit[66]" "Disabled,Enabled" bitfld.long 0x08 0. " [65] ,IF3 Update Enabled Bit[65]" "Disabled,Enabled" line.long 0x0C "IF3UENA8_7,Update Enable 8_7 Register" bitfld.long 0x0C 31. " IF3UPDATEEN[128] ,IF3 Update Enabled Bit[128]" "Disabled,Enabled" bitfld.long 0x0C 30. " [127] ,IF3 Update Enabled Bit[127]" "Disabled,Enabled" newline bitfld.long 0x0C 29. " [126] ,IF3 Update Enabled Bit[126]" "Disabled,Enabled" bitfld.long 0x0C 28. " [125] ,IF3 Update Enabled Bit[125]" "Disabled,Enabled" newline bitfld.long 0x0C 27. " [124] ,IF3 Update Enabled Bit[124]" "Disabled,Enabled" bitfld.long 0x0C 26. " [123] ,IF3 Update Enabled Bit[123]" "Disabled,Enabled" newline bitfld.long 0x0C 25. " [122] ,IF3 Update Enabled Bit[122]" "Disabled,Enabled" bitfld.long 0x0C 24. " [121] ,IF3 Update Enabled Bit[121]" "Disabled,Enabled" newline bitfld.long 0x0C 23. " [120] ,IF3 Update Enabled Bit[120]" "Disabled,Enabled" bitfld.long 0x0C 22. " [119] ,IF3 Update Enabled Bit[119]" "Disabled,Enabled" newline bitfld.long 0x0C 21. " [118] ,IF3 Update Enabled Bit[118]" "Disabled,Enabled" bitfld.long 0x0C 20. " [117] ,IF3 Update Enabled Bit[117]" "Disabled,Enabled" newline bitfld.long 0x0C 19. " [116] ,IF3 Update Enabled Bit[116]" "Disabled,Enabled" bitfld.long 0x0C 18. " [115] ,IF3 Update Enabled Bit[115]" "Disabled,Enabled" newline bitfld.long 0x0C 17. " [114] ,IF3 Update Enabled Bit[114]" "Disabled,Enabled" bitfld.long 0x0C 16. " [113] ,IF3 Update Enabled Bit[113]" "Disabled,Enabled" newline bitfld.long 0x0C 15. " [112] ,IF3 Update Enabled Bit[112]" "Disabled,Enabled" bitfld.long 0x0C 14. " [111] ,IF3 Update Enabled Bit[111]" "Disabled,Enabled" newline bitfld.long 0x0C 13. " [110] ,IF3 Update Enabled Bit[110]" "Disabled,Enabled" bitfld.long 0x0C 12. " [109] ,IF3 Update Enabled Bit[109]" "Disabled,Enabled" newline bitfld.long 0x0C 11. " [108] ,IF3 Update Enabled Bit[108]" "Disabled,Enabled" bitfld.long 0x0C 10. " [107] ,IF3 Update Enabled Bit[107]" "Disabled,Enabled" newline bitfld.long 0x0C 9. " [106] ,IF3 Update Enabled Bit[106]" "Disabled,Enabled" bitfld.long 0x0C 8. " [105] ,IF3 Update Enabled Bit[105]" "Disabled,Enabled" newline bitfld.long 0x0C 7. " [104] ,IF3 Update Enabled Bit[104]" "Disabled,Enabled" bitfld.long 0x0C 6. " [103] ,IF3 Update Enabled Bit[103]" "Disabled,Enabled" newline bitfld.long 0x0C 5. " [102] ,IF3 Update Enabled Bit[102]" "Disabled,Enabled" bitfld.long 0x0C 4. " [101] ,IF3 Update Enabled Bit[101]" "Disabled,Enabled" newline bitfld.long 0x0C 3. " [100] ,IF3 Update Enabled Bit[100]" "Disabled,Enabled" bitfld.long 0x0C 2. " [99] ,IF3 Update Enabled Bit[99]" "Disabled,Enabled" newline bitfld.long 0x0C 1. " [98] ,IF3 Update Enabled Bit[98]" "Disabled,Enabled" bitfld.long 0x0C 0. " [97] ,IF3 Update Enabled Bit[97]" "Disabled,Enabled" newline group.long 0x1E0++0x03 line.long 0x0 "IOCTRLTX,TX IO Control Register" sif (cpu()!="TMS470MF031"&&cpu()!="TMS470MF042"&&cpu()!="TMS470MF066"&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!=("TMS570LC4357")&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*")&&!cpuis("TMS570LS0232")&&!cpuis("TMS570LS0714*")&&!cpuis("TMS570LS0914*")) bitfld.long 0x00 19. " SR ,Slew Rate Selection of Output Driver" "Normal,Slow" newline endif bitfld.long 0x00 18. " PU ,Selection of Pull Direction" "Pull down,Pull up" bitfld.long 0x00 17. " PD ,Pull Functionality Disable" "No,Yes" bitfld.long 0x00 16. " OD ,Open Drain Mode" "Push pull,Open Drain" bitfld.long 0x00 3. " FUNC ,Functionality of Pin" "General,CAN" newline bitfld.long 0x00 2. " DIR ,Direction of Pin" "Input,Output" bitfld.long 0x00 1. " OUT ,Value to Drive to Pin if Configured for I/O" "Low,High" bitfld.long 0x00 0. " IN ,Value of Pin" "Low,High" group.long 0x1E4++0x03 line.long 0x0 "IOCTRLRX,RX IO Control Register" sif (cpu()!="TMS470MF031"&&cpu()!="TMS470MF042"&&cpu()!="TMS470MF066"&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!=("TMS570LC4357")&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*")&&!cpuis("TMS570LS0232")&&!cpuis("TMS570LS0714*")&&!cpuis("TMS570LS0914*")) bitfld.long 0x00 19. " SR ,Slew Rate Selection of Output Driver" "Normal,Slow" newline endif bitfld.long 0x00 18. " PU ,Selection of Pull Direction" "Pull down,Pull up" bitfld.long 0x00 17. " PD ,Pull Functionality Disable" "No,Yes" bitfld.long 0x00 16. " OD ,Open Drain Mode" "Push pull,Open Drain" bitfld.long 0x00 3. " FUNC ,Functionality of Pin" "General,CAN" newline bitfld.long 0x00 2. " DIR ,Direction of Pin" "Input,Output" bitfld.long 0x00 1. " OUT ,Value to Drive to Pin if Configured for I/O" "Low,High" bitfld.long 0x00 0. " IN ,Value of Pin" "Low,High" sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*") endian.le endif width 0x0B tree.end tree "DCAN3" base ad:0xFFF7E000 sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*") endian.be endif width 12. group.long 0x00++0x3 line.long 0x0 "CTRL,Config Register" bitfld.long 0x00 25. " WUBA ,Automatic Wake Up on Bus Activity When in Local Power Down Mode" "Not detected,Detected" bitfld.long 0x00 24. " PDR ,Request for Local Low Power Down Mode" "Not requested,Power down" sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS0232")) newline bitfld.long 0x00 20. " DE3 ,DMA Enable for IF3" "Disabled,Enabled" newline bitfld.long 0x00 19. " DE2 ,DMA Enable for IF2" "Disabled,Enabled" bitfld.long 0x00 18. " DE1 ,DMA Enable for IF1" "Disabled,Enabled" endif newline bitfld.long 0x00 17. " IE1 ,DCAN1INT Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " INITDBG ,Internal Init State While Debug Access Mode" "No debug,Debug" bitfld.long 0x00 15. " SWR ,SW Reset Enable" "No reset,Reset" bitfld.long 0x00 10.--13. " PMD ,Parity on/off" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" newline bitfld.long 0x00 9. " ABO ,Auto Bus On Enable" "Disabled,Enabled" bitfld.long 0x00 8. " IDS ,Interruption Debug Support Enable" "Disabled,Enabled" bitfld.long 0x00 7. " TEST ,Test Mode Enable" "Disabled,Enabled" newline bitfld.long 0x00 6. " CCE ,Configuration Change Enable" "Disabled,Enabled" bitfld.long 0x00 5. " DAR ,Disable Automatic Retransmission" "No,Yes" bitfld.long 0x00 3. " EIE ,Error Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " SIE ,Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 1. " IE ,DCAN0INT Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. " INIT ,Initialization" "Disabled,Enabled" sif (cpu()=="TMS470MF031"||cpu()=="TMS470MF042"||cpu()=="TMS470MF066"||cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10206-PGE")||cpu()==("TMS570LC4357")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")) group.long 0x04++0x3 line.long 0x0 "ES,Error and Status Register" rbitfld.long 0x00 10. " PDA ,Local Power Down Mode Acknowledge" "Not in,Is in" rbitfld.long 0x00 9. " WAKEUPPND ,Wake Up Pending" "No requested,Requested" rbitfld.long 0x00 8. " PER ,Parity Error Detected" "No error,Error" newline rbitfld.long 0x00 7. " BOFF ,Bus-Off State" "Not in,In" rbitfld.long 0x00 6. " EWARN ,Warning state" "<96,>96" rbitfld.long 0x00 5. " EPASS ,Error Passive State" "CAN Bus,Passive" newline bitfld.long 0x00 4. " RXOK ,Received a Message successfully" "No,Yes" bitfld.long 0x00 3. " TXOK ,Transmitted a Message successfully" "No,Yes" bitfld.long 0x00 0.--2. " LEC ,Last Error Code" "No error,Stuff,Form,Ack,Bit1,Bit0,CRC,No CAN" elif !cpuis("TMS570LS3137-EP") hgroup.long 0x04++0x3 hide.long 0x0 "STAT,Status Register" in else if (((per.l.be(ad:0xFFF7E000))&0x100)==0x100) group.long 0x04++0x3 line.long 0x0 "ES,Error and Status Register" rbitfld.long 0x00 10. " PDA ,Local Power Down Mode Acknowledge" "Not in,Is in" rbitfld.long 0x00 9. " WAKEUPPND ,Wake Up Pending" "No requested,Requested" rbitfld.long 0x00 8. " PER ,Parity Error Detected" "No error,Error" newline rbitfld.long 0x00 7. " BOFF ,Bus-Off State" "Not in,In" rbitfld.long 0x00 6. " EWARN ,Warning state" "<96,>96" rbitfld.long 0x00 5. " EPASS ,Error Passive State" "CAN Bus,Passive" newline bitfld.long 0x00 4. " RXOK ,Received a Message successfully" "No,Yes" bitfld.long 0x00 3. " TXOK ,Transmitted a Message successfully" "No,Yes" bitfld.long 0x00 0.--2. " LEC ,Last Error Code" "No error,Stuff,Form,Ack,Bit1,Bit0,CRC,No CAN" else hgroup.long 0x04++0x3 hide.long 0x0 "ES,Error and Status Register" in endif endif rgroup.long 0x08++0x3 line.long 0x0 "ERRC,Error Counter Register" bitfld.long 0x00 15. " RP ,Receive Error Passive" "Below,Reached" hexmask.long.byte 0x00 8.--14. 1. " REC ,Receive Error Counter" hexmask.long.byte 0x00 0.--7. 1. " TEC ,Transmit Error Counter" sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*") if (((per.l.be(ad:0xFFF7E000))&0x41)==0x41) group.long 0x0C++0x3 line.long 0x0 "BTBRP,Bit Timing_BRP Extension Register" bitfld.long 0x00 16.--19. " BRPE ,Baud Rate Prescaler Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--14. " TSEG2 ,The Time Segment After the Sample Point" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--11. " TSEG1 ,The Time Segment Before the Sample Point" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 6.--7. " SJW ,Synchronization Jump Width" "0,1,2,3" bitfld.long 0x00 0.--5. " BRP ,Baud Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.long 0x0C++0x3 line.long 0x0 "BTBRP,Bit Timing_BRP Extension Register" bitfld.long 0x00 16.--19. " BRPE ,Baud Rate Prescaler Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--14. " TSEG2 ,The Time Segment After the Sample Point" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--11. " TSEG1 ,The Time Segment Before the Sample Point" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 6.--7. " SJW ,Synchronization Jump Width" "0,1,2,3" bitfld.long 0x00 0.--5. " BRP ,Baud Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif else group.long 0x0C++0x3 line.long 0x0 "BTBRP,Bit Timing_BRP Extension Register" bitfld.long 0x00 16.--19. " BRPE ,Baud Rate Prescaler Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--14. " TSEG2 ,The Time Segment After the Sample Point" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--11. " TSEG1 ,The Time Segment Before the Sample Point" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 6.--7. " SJW ,Synchronization Jump Width" "0,1,2,3" bitfld.long 0x00 0.--5. " BRP ,Baud Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif rgroup.long 0x10++0x3 line.long 0x0 "INTR,Interrupt Register" hexmask.long.byte 0x00 16.--23. 1. " INT1ID[7-0] ,Interrupt 1 Identifier" hexmask.long.word 0x00 0.--15. 1. " INTID[15-0] ,Interrupt Identifier" sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*") if (((per.l.be(ad:0xFFF7E000))&0x41)==0x41) group.long 0x14++0x3 line.long 0x0 "TEST,Test Register" bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable" "Normal,Enabled" bitfld.long 0x00 8. " EXL ,External Loop Back Mode" "Normal,Enabled" bitfld.long 0x00 7. " RX ,Receive Pin" "Dominant,Recessive" newline bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Normal,Sample point,Dominant,Recessive" bitfld.long 0x00 4. " LBACK ,Loop Back Mode" "Disabled,Enabled" bitfld.long 0x00 3. " SILENT ,Silent Mode" "Normal,Enabled" else rgroup.long 0x14++0x3 line.long 0x0 "TEST,Test Register" bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable" "Normal,Enabled" bitfld.long 0x00 8. " EXL ,External Loop Back Mode" "Normal,Enabled" bitfld.long 0x00 7. " RX ,Receive Pin" "Dominant,Recessive" newline bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Normal,Sample point,Dominant,Recessive" bitfld.long 0x00 4. " LBACK ,Loop Back Mode" "Disabled,Enabled" bitfld.long 0x00 3. " SILENT ,Silent Mode" "Normal,Enabled" endif elif !cpuis("TMS570LS3137-EP") group.long 0x14++0x3 line.long 0x0 "TEST,Test Register" bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable" "Normal,Enabled" bitfld.long 0x00 8. " EXL ,External Loop Back Mode" "Normal,Enabled" bitfld.long 0x00 7. " RX ,Receive Pin" "Dominant,Recessive" newline sif (cpu()=="TMS470MF031"||cpu()=="TMS470MF042"||cpu()=="TMS470MF066"||cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10206-PGE")||cpu()==("TMS570LC4357")||cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS21*")||cpuis("TMS570LS31*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")) bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Normal,Sample point,Dominant,Recessive" else bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Reset,Sample point,Dominant,Recessive" endif bitfld.long 0x00 4. " LBACK ,Loop Back Mode" "Disabled,Enabled" bitfld.long 0x00 3. " SILENT ,Silent Mode" "Normal,Enabled" else if (((per.l.be(ad:0xFFF7E000))&0x80)==0x80) group.long 0x14++0x3 line.long 0x0 "TEST,Test Register" bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable" "Normal,Enabled" bitfld.long 0x00 8. " EXL ,External Loop Back Mode" "Normal,Enabled" bitfld.long 0x00 7. " RX ,Receive Pin" "Dominant,Recessive" newline bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Normal,Sample point,Dominant,Recessive" bitfld.long 0x00 4. " LBACK ,Loop Back Mode" "Disabled,Enabled" bitfld.long 0x00 3. " SILENT ,Silent Mode" "Normal,Enabled" else rgroup.long 0x14++0x3 line.long 0x0 "TEST,Test Register" bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable" "Normal,Enabled" bitfld.long 0x00 8. " EXL ,External Loop Back Mode" "Normal,Enabled" bitfld.long 0x00 7. " RX ,Receive Pin" "Dominant,Recessive" newline bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Normal,Sample point,Dominant,Recessive" bitfld.long 0x00 4. " LBACK ,Loop Back Mode" "Disabled,Enabled" bitfld.long 0x00 3. " SILENT ,Silent Mode" "Normal,Enabled" endif endif rgroup.long 0x1C++0x3 line.long 0x0 "PERR,Parity Error Code Register" bitfld.long 0x00 8.--10. " WORD_NUMBER ,Word Number" ",1,2,3,4,5,?..." hexmask.long.byte 0x00 0.--7. 1. " MESSAGE_NUMBER ,Message Number" sif (cpu()=="TMS470MF031"||cpu()=="TMS470MF042"||cpu()=="TMS470MF066"||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")) rgroup.long 0x20++0x3 line.long 0x00 "REL,DCAN Core Release Register" bitfld.long 0x00 28.--31. " REL ,Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " STEP ,Step of Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " SUBSTEP ,Substep of Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " YEAR ,Design Time Stamp - Year" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " MON ,Design Time Stamp - Month" hexmask.long.byte 0x00 0.--7. 1. " DAY ,Design Time Stamp - Day" endif width 19. sif (cpu()=="TMS570LC4357") group.long 0x24++0x0B line.long 0x00 "DCAN_ECCDIAG,ECC Diagnostic Register" bitfld.long 0x00 0.--3. " ECCDIAG , SECDED diagnostic mode enable/disable" ",,,,,Enabled,,,,,Disabled,?..." line.long 0x04 "DCAN_ECCDIAG_STAT, ECC Diagnostic Status Register" eventfld.long 0x04 8. " DEFLG_DIAG , Double bit error diagnostic" "No error,Error" eventfld.long 0x04 0. " SEFLG_DIAG , Single bit error diagnostic" "No error,Error" line.long 0x08 "DCAN_ECC_CS, ECC Control and Status Register" bitfld.long 0x08 24.--27. " SBE_EVT_EN , Single bit error event" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.long 0x08 16.--19. " ECCMODE , Single bit error correction" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" eventfld.long 0x08 8. " DEFLG , Double bit error flag" "No error,Error" eventfld.long 0x08 0. " SEFLG , Single bit error flag" "No error,Error" rgroup.long 0x30++0x03 line.long 0x00 "DCAN_ECC_SERR, ECC Single Bit Error Code Register" hexmask.long.byte 0x00 0.--7. 1. " Message_Number , Message object number where ECC single bit error has been detected" endif width 12. group.long 0x80++0x03 line.long 0x00 "ABOT,Auto Bus On Time" rgroup.long 0x84++0x4F line.long 0x00 "TRREQ,Transmission Request X" bitfld.long 0x00 14.--15. " TXRQSTREG8 ,Transmission Request 8" "0,1,2,3" bitfld.long 0x00 12.--13. " TXRQSTREG7 ,Transmission Request 7" "0,1,2,3" bitfld.long 0x00 10.--11. " TXRQSTREG6 ,Transmission Request 6" "0,1,2,3" bitfld.long 0x00 8.--9. " TXRQSTREG5 ,Transmission Request 5" "0,1,2,3" newline bitfld.long 0x00 6.--7. " TXRQSTREG4 ,Transmission Request 4" "0,1,2,3" bitfld.long 0x00 4.--5. " TXRQSTREG3 ,Transmission Request 3" "0,1,2,3" bitfld.long 0x00 2.--3. " TXRQSTREG2 ,Transmission Request 2" "0,1,2,3" bitfld.long 0x00 0.--1. " TXRQSTREG1 ,Transmission Request 1" "0,1,2,3" line.long 0x04 "TRREQ12,Transmission Request 1-2" bitfld.long 0x04 31. " TXRQST[32] ,Transmission Request Bits[32]" "Not requested,Requested" bitfld.long 0x04 30. " [31] ,Transmission Request Bits[31]" "Not requested,Requested" newline bitfld.long 0x04 29. " [30] ,Transmission Request Bits[30]" "Not requested,Requested" bitfld.long 0x04 28. " [29] ,Transmission Request Bits[29]" "Not requested,Requested" newline bitfld.long 0x04 27. " [28] ,Transmission Request Bits[28]" "Not requested,Requested" bitfld.long 0x04 26. " [27] ,Transmission Request Bits[27]" "Not requested,Requested" newline bitfld.long 0x04 25. " [26] ,Transmission Request Bits[26]" "Not requested,Requested" bitfld.long 0x04 24. " [25] ,Transmission Request Bits[25]" "Not requested,Requested" newline bitfld.long 0x04 23. " [24] ,Transmission Request Bits[24]" "Not requested,Requested" bitfld.long 0x04 22. " [23] ,Transmission Request Bits[23]" "Not requested,Requested" newline bitfld.long 0x04 21. " [22] ,Transmission Request Bits[22]" "Not requested,Requested" bitfld.long 0x04 20. " [21] ,Transmission Request Bits[21]" "Not requested,Requested" newline bitfld.long 0x04 19. " [20] ,Transmission Request Bits[20]" "Not requested,Requested" bitfld.long 0x04 18. " [19] ,Transmission Request Bits[19]" "Not requested,Requested" newline bitfld.long 0x04 17. " [18] ,Transmission Request Bits[18]" "Not requested,Requested" bitfld.long 0x04 16. " [17] ,Transmission Request Bits[17]" "Not requested,Requested" newline bitfld.long 0x04 15. " [16] ,Transmission Request Bits[16]" "Not requested,Requested" bitfld.long 0x04 14. " [15] ,Transmission Request Bits[15]" "Not requested,Requested" newline bitfld.long 0x04 13. " [14] ,Transmission Request Bits[14]" "Not requested,Requested" bitfld.long 0x04 12. " [13] ,Transmission Request Bits[13]" "Not requested,Requested" newline bitfld.long 0x04 11. " [12] ,Transmission Request Bits[12]" "Not requested,Requested" bitfld.long 0x04 10. " [11] ,Transmission Request Bits[11]" "Not requested,Requested" newline bitfld.long 0x04 9. " [10] ,Transmission Request Bits[10]" "Not requested,Requested" bitfld.long 0x04 8. " [9] ,Transmission Request Bits[9]" "Not requested,Requested" newline bitfld.long 0x04 7. " [8] ,Transmission Request Bits[8]" "Not requested,Requested" bitfld.long 0x04 6. " [7] ,Transmission Request Bits[7]" "Not requested,Requested" newline bitfld.long 0x04 5. " [6] ,Transmission Request Bits[6]" "Not requested,Requested" bitfld.long 0x04 4. " [5] ,Transmission Request Bits[5]" "Not requested,Requested" newline bitfld.long 0x04 3. " [4] ,Transmission Request Bits[4]" "Not requested,Requested" bitfld.long 0x04 2. " [3] ,Transmission Request Bits[3]" "Not requested,Requested" newline bitfld.long 0x04 1. " [2] ,Transmission Request Bits[2]" "Not requested,Requested" bitfld.long 0x04 0. " [1] ,Transmission Request Bits[1]" "Not requested,Requested" line.long 0x08 "TRREQ34,Transmission Request 3-4" bitfld.long 0x08 31. " TXRQST[64] ,Transmission Request Bits[64]" "Not requested,Requested" bitfld.long 0x08 30. " [63] ,Transmission Request Bits[63]" "Not requested,Requested" newline bitfld.long 0x08 29. " [62] ,Transmission Request Bits[62]" "Not requested,Requested" bitfld.long 0x08 28. " [61] ,Transmission Request Bits[61]" "Not requested,Requested" newline bitfld.long 0x08 27. " [60] ,Transmission Request Bits[60]" "Not requested,Requested" bitfld.long 0x08 26. " [59] ,Transmission Request Bits[59]" "Not requested,Requested" newline bitfld.long 0x08 25. " [58] ,Transmission Request Bits[58]" "Not requested,Requested" bitfld.long 0x08 24. " [57] ,Transmission Request Bits[57]" "Not requested,Requested" newline bitfld.long 0x08 23. " [56] ,Transmission Request Bits[56]" "Not requested,Requested" bitfld.long 0x08 22. " [55] ,Transmission Request Bits[55]" "Not requested,Requested" newline bitfld.long 0x08 21. " [54] ,Transmission Request Bits[54]" "Not requested,Requested" bitfld.long 0x08 20. " [53] ,Transmission Request Bits[53]" "Not requested,Requested" newline bitfld.long 0x08 19. " [52] ,Transmission Request Bits[52]" "Not requested,Requested" bitfld.long 0x08 18. " [51] ,Transmission Request Bits[51]" "Not requested,Requested" newline bitfld.long 0x08 17. " [50] ,Transmission Request Bits[50]" "Not requested,Requested" bitfld.long 0x08 16. " [49] ,Transmission Request Bits[49]" "Not requested,Requested" newline bitfld.long 0x08 15. " [48] ,Transmission Request Bits[48]" "Not requested,Requested" bitfld.long 0x08 14. " [47] ,Transmission Request Bits[47]" "Not requested,Requested" newline bitfld.long 0x08 13. " [46] ,Transmission Request Bits[46]" "Not requested,Requested" bitfld.long 0x08 12. " [45] ,Transmission Request Bits[45]" "Not requested,Requested" newline bitfld.long 0x08 11. " [44] ,Transmission Request Bits[44]" "Not requested,Requested" bitfld.long 0x08 10. " [43] ,Transmission Request Bits[43]" "Not requested,Requested" newline bitfld.long 0x08 9. " [42] ,Transmission Request Bits[42]" "Not requested,Requested" bitfld.long 0x08 8. " [41] ,Transmission Request Bits[41]" "Not requested,Requested" newline bitfld.long 0x08 7. " [40] ,Transmission Request Bits[40]" "Not requested,Requested" bitfld.long 0x08 6. " [39] ,Transmission Request Bits[39]" "Not requested,Requested" newline bitfld.long 0x08 5. " [38] ,Transmission Request Bits[38]" "Not requested,Requested" bitfld.long 0x08 4. " [37] ,Transmission Request Bits[37]" "Not requested,Requested" newline bitfld.long 0x08 3. " [36] ,Transmission Request Bits[36]" "Not requested,Requested" bitfld.long 0x08 2. " [35] ,Transmission Request Bits[35]" "Not requested,Requested" newline bitfld.long 0x08 1. " [34] ,Transmission Request Bits[34]" "Not requested,Requested" bitfld.long 0x08 0. " [33] ,Transmission Request Bits[33]" "Not requested,Requested" line.long 0x0C "TRREQ56,Transmission Request 5-6" bitfld.long 0x0C 31. " TXRQST[96] ,Transmission Request Bits[96]" "Not requested,Requested" bitfld.long 0x0C 30. " [95] ,Transmission Request Bits[95]" "Not requested,Requested" newline bitfld.long 0x0C 29. " [94] ,Transmission Request Bits[94]" "Not requested,Requested" bitfld.long 0x0C 28. " [93] ,Transmission Request Bits[93]" "Not requested,Requested" newline bitfld.long 0x0C 27. " [92] ,Transmission Request Bits[92]" "Not requested,Requested" bitfld.long 0x0C 26. " [91] ,Transmission Request Bits[91]" "Not requested,Requested" newline bitfld.long 0x0C 25. " [90] ,Transmission Request Bits[90]" "Not requested,Requested" bitfld.long 0x0C 24. " [89] ,Transmission Request Bits[89]" "Not requested,Requested" newline bitfld.long 0x0C 23. " [88] ,Transmission Request Bits[88]" "Not requested,Requested" bitfld.long 0x0C 22. " [87] ,Transmission Request Bits[87]" "Not requested,Requested" newline bitfld.long 0x0C 21. " [86] ,Transmission Request Bits[86]" "Not requested,Requested" bitfld.long 0x0C 20. " [85] ,Transmission Request Bits[85]" "Not requested,Requested" newline bitfld.long 0x0C 19. " [84] ,Transmission Request Bits[84]" "Not requested,Requested" bitfld.long 0x0C 18. " [83] ,Transmission Request Bits[83]" "Not requested,Requested" newline bitfld.long 0x0C 17. " [82] ,Transmission Request Bits[82]" "Not requested,Requested" bitfld.long 0x0C 16. " [81] ,Transmission Request Bits[81]" "Not requested,Requested" newline bitfld.long 0x0C 15. " [80] ,Transmission Request Bits[80]" "Not requested,Requested" bitfld.long 0x0C 14. " [79] ,Transmission Request Bits[79]" "Not requested,Requested" newline bitfld.long 0x0C 13. " [78] ,Transmission Request Bits[78]" "Not requested,Requested" bitfld.long 0x0C 12. " [77] ,Transmission Request Bits[77]" "Not requested,Requested" newline bitfld.long 0x0C 11. " [76] ,Transmission Request Bits[76]" "Not requested,Requested" bitfld.long 0x0C 10. " [75] ,Transmission Request Bits[75]" "Not requested,Requested" newline bitfld.long 0x0C 9. " [74] ,Transmission Request Bits[74]" "Not requested,Requested" bitfld.long 0x0C 8. " [73] ,Transmission Request Bits[73]" "Not requested,Requested" newline bitfld.long 0x0C 7. " [72] ,Transmission Request Bits[72]" "Not requested,Requested" bitfld.long 0x0C 6. " [71] ,Transmission Request Bits[71]" "Not requested,Requested" newline bitfld.long 0x0C 5. " [70] ,Transmission Request Bits[70]" "Not requested,Requested" bitfld.long 0x0C 4. " [69] ,Transmission Request Bits[69]" "Not requested,Requested" newline bitfld.long 0x0C 3. " [68] ,Transmission Request Bits[68]" "Not requested,Requested" bitfld.long 0x0C 2. " [67] ,Transmission Request Bits[67]" "Not requested,Requested" newline bitfld.long 0x0C 1. " [66] ,Transmission Request Bits[66]" "Not requested,Requested" bitfld.long 0x0C 0. " [65] ,Transmission Request Bits[65]" "Not requested,Requested" line.long 0x10 "TRREQ78,Transmission Request 7-8" bitfld.long 0x10 31. " TXRQST[128] ,Transmission Request Bits[128]" "Not requested,Requested" bitfld.long 0x10 30. " [127] ,Transmission Request Bits[127]" "Not requested,Requested" newline bitfld.long 0x10 29. " [126] ,Transmission Request Bits[126]" "Not requested,Requested" bitfld.long 0x10 28. " [125] ,Transmission Request Bits[125]" "Not requested,Requested" newline bitfld.long 0x10 27. " [124] ,Transmission Request Bits[124]" "Not requested,Requested" bitfld.long 0x10 26. " [123] ,Transmission Request Bits[123]" "Not requested,Requested" newline bitfld.long 0x10 25. " [122] ,Transmission Request Bits[122]" "Not requested,Requested" bitfld.long 0x10 24. " [121] ,Transmission Request Bits[121]" "Not requested,Requested" newline bitfld.long 0x10 23. " [120] ,Transmission Request Bits[120]" "Not requested,Requested" bitfld.long 0x10 22. " [119] ,Transmission Request Bits[119]" "Not requested,Requested" newline bitfld.long 0x10 21. " [118] ,Transmission Request Bits[118]" "Not requested,Requested" bitfld.long 0x10 20. " [117] ,Transmission Request Bits[117]" "Not requested,Requested" newline bitfld.long 0x10 19. " [116] ,Transmission Request Bits[116]" "Not requested,Requested" bitfld.long 0x10 18. " [115] ,Transmission Request Bits[115]" "Not requested,Requested" newline bitfld.long 0x10 17. " [114] ,Transmission Request Bits[114]" "Not requested,Requested" bitfld.long 0x10 16. " [113] ,Transmission Request Bits[113]" "Not requested,Requested" newline bitfld.long 0x10 15. " [112] ,Transmission Request Bits[112]" "Not requested,Requested" bitfld.long 0x10 14. " [111] ,Transmission Request Bits[111]" "Not requested,Requested" newline bitfld.long 0x10 13. " [110] ,Transmission Request Bits[110]" "Not requested,Requested" bitfld.long 0x10 12. " [109] ,Transmission Request Bits[109]" "Not requested,Requested" newline bitfld.long 0x10 11. " [108] ,Transmission Request Bits[108]" "Not requested,Requested" bitfld.long 0x10 10. " [107] ,Transmission Request Bits[107]" "Not requested,Requested" newline bitfld.long 0x10 9. " [106] ,Transmission Request Bits[106]" "Not requested,Requested" bitfld.long 0x10 8. " [105] ,Transmission Request Bits[105]" "Not requested,Requested" newline bitfld.long 0x10 7. " [104] ,Transmission Request Bits[104]" "Not requested,Requested" bitfld.long 0x10 6. " [103] ,Transmission Request Bits[103]" "Not requested,Requested" newline bitfld.long 0x10 5. " [102] ,Transmission Request Bits[102]" "Not requested,Requested" bitfld.long 0x10 4. " [101] ,Transmission Request Bits[101]" "Not requested,Requested" newline bitfld.long 0x10 3. " [100] ,Transmission Request Bits[100]" "Not requested,Requested" bitfld.long 0x10 2. " [99] ,Transmission Request Bits[99]" "Not requested,Requested" newline bitfld.long 0x10 1. " [98] ,Transmission Request Bits[98]" "Not requested,Requested" bitfld.long 0x10 0. " [97] ,Transmission Request Bits[97]" "Not requested,Requested" line.long 0x14 "NEWDAT,New Data X" bitfld.long 0x14 14.--15. " NEWDATREG8 ,New Data 8" "0,1,2,3" bitfld.long 0x14 12.--13. " NEWDATREG7 ,New Data 7" "0,1,2,3" bitfld.long 0x14 10.--11. " NEWDATREG6 ,New Data 6" "0,1,2,3" bitfld.long 0x14 8.--9. " NEWDATREG5 ,New Data 5" "0,1,2,3" newline bitfld.long 0x14 6.--7. " NEWDATREG4 ,NEW DATA 4" "0,1,2,3" bitfld.long 0x14 4.--5. " NEWDATREG3 ,New Data 3" "0,1,2,3" bitfld.long 0x14 2.--3. " NEWDATREG2 ,New Data 2" "0,1,2,3" bitfld.long 0x14 0.--1. " NEWDATREG1 ,New Data 1" "0,1,2,3" line.long 0x18 "NEWDAT12,New Data 1-2" bitfld.long 0x18 31. " NEWDAT[32] ,New Data Bit[32]" "Not requested,Requested" bitfld.long 0x18 30. " [31] ,New Data Bit[31]" "Not requested,Requested" newline bitfld.long 0x18 29. " [30] ,New Data Bit[30]" "Not requested,Requested" bitfld.long 0x18 28. " [29] ,New Data Bit[29]" "Not requested,Requested" newline bitfld.long 0x18 27. " [28] ,New Data Bit[28]" "Not requested,Requested" bitfld.long 0x18 26. " [27] ,New Data Bit[27]" "Not requested,Requested" newline bitfld.long 0x18 25. " [26] ,New Data Bit[26]" "Not requested,Requested" bitfld.long 0x18 24. " [25] ,New Data Bit[25]" "Not requested,Requested" newline bitfld.long 0x18 23. " [24] ,New Data Bit[24]" "Not requested,Requested" bitfld.long 0x18 22. " [23] ,New Data Bit[23]" "Not requested,Requested" newline bitfld.long 0x18 21. " [22] ,New Data Bit[22]" "Not requested,Requested" bitfld.long 0x18 20. " [21] ,New Data Bit[21]" "Not requested,Requested" newline bitfld.long 0x18 19. " [20] ,New Data Bit[20]" "Not requested,Requested" bitfld.long 0x18 18. " [19] ,New Data Bit[19]" "Not requested,Requested" newline bitfld.long 0x18 17. " [18] ,New Data Bit[18]" "Not requested,Requested" bitfld.long 0x18 16. " [17] ,New Data Bit[17]" "Not requested,Requested" newline bitfld.long 0x18 15. " [16] ,New Data Bit[16]" "Not requested,Requested" bitfld.long 0x18 14. " [15] ,New Data Bit[15]" "Not requested,Requested" newline bitfld.long 0x18 13. " [14] ,New Data Bit[14]" "Not requested,Requested" bitfld.long 0x18 12. " [13] ,New Data Bit[13]" "Not requested,Requested" newline bitfld.long 0x18 11. " [12] ,New Data Bit[12]" "Not requested,Requested" bitfld.long 0x18 10. " [11] ,New Data Bit[11]" "Not requested,Requested" newline bitfld.long 0x18 9. " [10] ,New Data Bit[10]" "Not requested,Requested" bitfld.long 0x18 8. " [9] ,New Data Bit[9]" "Not requested,Requested" newline bitfld.long 0x18 7. " [8] ,New Data Bit[8]" "Not requested,Requested" bitfld.long 0x18 6. " [7] ,New Data Bit[7]" "Not requested,Requested" newline bitfld.long 0x18 5. " [6] ,New Data Bit[6]" "Not requested,Requested" bitfld.long 0x18 4. " [5] ,New Data Bit[5]" "Not requested,Requested" newline bitfld.long 0x18 3. " [4] ,New Data Bit[4]" "Not requested,Requested" bitfld.long 0x18 2. " [3] ,New Data Bit[3]" "Not requested,Requested" newline bitfld.long 0x18 1. " [2] ,New Data Bit[2]" "Not requested,Requested" bitfld.long 0x18 0. " [1] ,New Data Bit[1]" "Not requested,Requested" line.long 0x1C "NEWDAT34,New Data 3-4" bitfld.long 0x1C 31. " NEWDAT[64] ,New Data Bit[64]" "Not requested,Requested" bitfld.long 0x1C 30. " [63] ,New Data Bit[63]" "Not requested,Requested" newline bitfld.long 0x1C 29. " [62] ,New Data Bit[62]" "Not requested,Requested" bitfld.long 0x1C 28. " [61] ,New Data Bit[61]" "Not requested,Requested" newline bitfld.long 0x1C 27. " [60] ,New Data Bit[60]" "Not requested,Requested" bitfld.long 0x1C 26. " [59] ,New Data Bit[59]" "Not requested,Requested" newline bitfld.long 0x1C 25. " [58] ,New Data Bit[58]" "Not requested,Requested" bitfld.long 0x1C 24. " [57] ,New Data Bit[57]" "Not requested,Requested" newline bitfld.long 0x1C 23. " [56] ,New Data Bit[56]" "Not requested,Requested" bitfld.long 0x1C 22. " [55] ,New Data Bit[55]" "Not requested,Requested" newline bitfld.long 0x1C 21. " [54] ,New Data Bit[54]" "Not requested,Requested" bitfld.long 0x1C 20. " [53] ,New Data Bit[53]" "Not requested,Requested" newline bitfld.long 0x1C 19. " [52] ,New Data Bit[52]" "Not requested,Requested" bitfld.long 0x1C 18. " [51] ,New Data Bit[51]" "Not requested,Requested" newline bitfld.long 0x1C 17. " [50] ,New Data Bit[50]" "Not requested,Requested" bitfld.long 0x1C 16. " [49] ,New Data Bit[49]" "Not requested,Requested" newline bitfld.long 0x1C 15. " [48] ,New Data Bit[48]" "Not requested,Requested" bitfld.long 0x1C 14. " [47] ,New Data Bit[47]" "Not requested,Requested" newline bitfld.long 0x1C 13. " [46] ,New Data Bit[46]" "Not requested,Requested" bitfld.long 0x1C 12. " [45] ,New Data Bit[45]" "Not requested,Requested" newline bitfld.long 0x1C 11. " [44] ,New Data Bit[44]" "Not requested,Requested" bitfld.long 0x1C 10. " [43] ,New Data Bit[43]" "Not requested,Requested" newline bitfld.long 0x1C 9. " [42] ,New Data Bit[42]" "Not requested,Requested" bitfld.long 0x1C 8. " [41] ,New Data Bit[41]" "Not requested,Requested" newline bitfld.long 0x1C 7. " [40] ,New Data Bit[40]" "Not requested,Requested" bitfld.long 0x1C 6. " [39] ,New Data Bit[39]" "Not requested,Requested" newline bitfld.long 0x1C 5. " [38] ,New Data Bit[38]" "Not requested,Requested" bitfld.long 0x1C 4. " [37] ,New Data Bit[37]" "Not requested,Requested" newline bitfld.long 0x1C 3. " [36] ,New Data Bit[36]" "Not requested,Requested" bitfld.long 0x1C 2. " [35] ,New Data Bit[35]" "Not requested,Requested" newline bitfld.long 0x1C 1. " [34] ,New Data Bit[34]" "Not requested,Requested" bitfld.long 0x1C 0. " [33] ,New Data Bit[33]" "Not requested,Requested" line.long 0x20 "NEWDAT56,New Data 5-6" bitfld.long 0x20 31. " NEWDAT[96] ,New Data Bit[96]" "Not requested,Requested" bitfld.long 0x20 30. " [95] ,New Data Bit[95]" "Not requested,Requested" newline bitfld.long 0x20 29. " [94] ,New Data Bit[94]" "Not requested,Requested" bitfld.long 0x20 28. " [93] ,New Data Bit[93]" "Not requested,Requested" newline bitfld.long 0x20 27. " [92] ,New Data Bit[92]" "Not requested,Requested" bitfld.long 0x20 26. " [91] ,New Data Bit[91]" "Not requested,Requested" newline bitfld.long 0x20 25. " [90] ,New Data Bit[90]" "Not requested,Requested" bitfld.long 0x20 24. " [89] ,New Data Bit[89]" "Not requested,Requested" newline bitfld.long 0x20 23. " [88] ,New Data Bit[88]" "Not requested,Requested" bitfld.long 0x20 22. " [87] ,New Data Bit[87]" "Not requested,Requested" newline bitfld.long 0x20 21. " [86] ,New Data Bit[86]" "Not requested,Requested" bitfld.long 0x20 20. " [85] ,New Data Bit[85]" "Not requested,Requested" newline bitfld.long 0x20 19. " [84] ,New Data Bit[84]" "Not requested,Requested" bitfld.long 0x20 18. " [83] ,New Data Bit[83]" "Not requested,Requested" newline bitfld.long 0x20 17. " [82] ,New Data Bit[82]" "Not requested,Requested" bitfld.long 0x20 16. " [81] ,New Data Bit[81]" "Not requested,Requested" newline bitfld.long 0x20 15. " [80] ,New Data Bit[80]" "Not requested,Requested" bitfld.long 0x20 14. " [79] ,New Data Bit[79]" "Not requested,Requested" newline bitfld.long 0x20 13. " [78] ,New Data Bit[78]" "Not requested,Requested" bitfld.long 0x20 12. " [77] ,New Data Bit[77]" "Not requested,Requested" newline bitfld.long 0x20 11. " [76] ,New Data Bit[76]" "Not requested,Requested" bitfld.long 0x20 10. " [75] ,New Data Bit[75]" "Not requested,Requested" newline bitfld.long 0x20 9. " [74] ,New Data Bit[74]" "Not requested,Requested" bitfld.long 0x20 8. " [73] ,New Data Bit[73]" "Not requested,Requested" newline bitfld.long 0x20 7. " [72] ,New Data Bit[72]" "Not requested,Requested" bitfld.long 0x20 6. " [71] ,New Data Bit[71]" "Not requested,Requested" newline bitfld.long 0x20 5. " [70] ,New Data Bit[70]" "Not requested,Requested" bitfld.long 0x20 4. " [69] ,New Data Bit[69]" "Not requested,Requested" newline bitfld.long 0x20 3. " [68] ,New Data Bit[68]" "Not requested,Requested" bitfld.long 0x20 2. " [67] ,New Data Bit[67]" "Not requested,Requested" newline bitfld.long 0x20 1. " [66] ,New Data Bit[66]" "Not requested,Requested" bitfld.long 0x20 0. " [65] ,New Data Bit[65]" "Not requested,Requested" line.long 0x24 "NEWDAT78,New Data 7-8" bitfld.long 0x24 31. " NEWDAT[128] ,New Data Bit[128]" "Not requested,Requested" bitfld.long 0x24 30. " [127] ,New Data Bit[127]" "Not requested,Requested" newline bitfld.long 0x24 29. " [126] ,New Data Bit[126]" "Not requested,Requested" bitfld.long 0x24 28. " [125] ,New Data Bit[125]" "Not requested,Requested" newline bitfld.long 0x24 27. " [124] ,New Data Bit[124]" "Not requested,Requested" bitfld.long 0x24 26. " [123] ,New Data Bit[123]" "Not requested,Requested" newline bitfld.long 0x24 25. " [122] ,New Data Bit[122]" "Not requested,Requested" bitfld.long 0x24 24. " [121] ,New Data Bit[121]" "Not requested,Requested" newline bitfld.long 0x24 23. " [120] ,New Data Bit[120]" "Not requested,Requested" bitfld.long 0x24 22. " [119] ,New Data Bit[119]" "Not requested,Requested" newline bitfld.long 0x24 21. " [118] ,New Data Bit[118]" "Not requested,Requested" bitfld.long 0x24 20. " [117] ,New Data Bit[117]" "Not requested,Requested" newline bitfld.long 0x24 19. " [116] ,New Data Bit[116]" "Not requested,Requested" bitfld.long 0x24 18. " [115] ,New Data Bit[115]" "Not requested,Requested" newline bitfld.long 0x24 17. " [114] ,New Data Bit[114]" "Not requested,Requested" bitfld.long 0x24 16. " [113] ,New Data Bit[113]" "Not requested,Requested" newline bitfld.long 0x24 15. " [112] ,New Data Bit[112]" "Not requested,Requested" bitfld.long 0x24 14. " [111] ,New Data Bit[111]" "Not requested,Requested" newline bitfld.long 0x24 13. " [110] ,New Data Bit[110]" "Not requested,Requested" bitfld.long 0x24 12. " [109] ,New Data Bit[109]" "Not requested,Requested" newline bitfld.long 0x24 11. " [108] ,New Data Bit[108]" "Not requested,Requested" bitfld.long 0x24 10. " [107] ,New Data Bit[107]" "Not requested,Requested" newline bitfld.long 0x24 9. " [106] ,New Data Bit[106]" "Not requested,Requested" bitfld.long 0x24 8. " [105] ,New Data Bit[105]" "Not requested,Requested" newline bitfld.long 0x24 7. " [104] ,New Data Bit[104]" "Not requested,Requested" bitfld.long 0x24 6. " [103] ,New Data Bit[103]" "Not requested,Requested" newline bitfld.long 0x24 5. " [102] ,New Data Bit[102]" "Not requested,Requested" bitfld.long 0x24 4. " [101] ,New Data Bit[101]" "Not requested,Requested" newline bitfld.long 0x24 3. " [100] ,New Data Bit[100]" "Not requested,Requested" bitfld.long 0x24 2. " [99] ,New Data Bit[99]" "Not requested,Requested" newline bitfld.long 0x24 1. " [98] ,New Data Bit[98]" "Not requested,Requested" bitfld.long 0x24 0. " [97] ,New Data Bit[97]" "Not requested,Requested" line.long 0x28 "INTPEN,Interrupt Pending X" bitfld.long 0x28 14.--15. " INTPENDREG[8] ,Interrupt Pending 8" "0,1,2,3" bitfld.long 0x28 12.--13. " [7] ,Interrupt Pending 7" "0,1,2,3" bitfld.long 0x28 10.--11. " [6] ,Interrupt Pending 6" "0,1,2,3" bitfld.long 0x28 8.--9. " [5] ,Interrupt Pending 5" "0,1,2,3" newline bitfld.long 0x28 6.--7. " [4] ,Interrupt Pending 4" "0,1,2,3" bitfld.long 0x28 4.--5. " [3] ,Interrupt Pending 3" "0,1,2,3" bitfld.long 0x28 2.--3. " [2] ,Interrupt Pending 2" "0,1,2,3" bitfld.long 0x28 0.--1. " [1] ,Interrupt Pending 1" "0,1,2,3" line.long 0x2C "INTPEN12,Interrupt Pending 1-2" bitfld.long 0x2C 31. " IntPnd[32] ,Interrupt Pending Bit[32]" "No interrupt,Interrupt" bitfld.long 0x2C 30. " [31] ,Interrupt Pending Bit[31]" "No interrupt,Interrupt" newline bitfld.long 0x2C 29. " [30] ,Interrupt Pending Bit[30]" "No interrupt,Interrupt" bitfld.long 0x2C 28. " [29] ,Interrupt Pending Bit[29]" "No interrupt,Interrupt" newline bitfld.long 0x2C 27. " [28] ,Interrupt Pending Bit[28]" "No interrupt,Interrupt" bitfld.long 0x2C 26. " [27] ,Interrupt Pending Bit[27]" "No interrupt,Interrupt" newline bitfld.long 0x2C 25. " [26] ,Interrupt Pending Bit[26]" "No interrupt,Interrupt" bitfld.long 0x2C 24. " [25] ,Interrupt Pending Bit[25]" "No interrupt,Interrupt" newline bitfld.long 0x2C 23. " [24] ,Interrupt Pending Bit[24]" "No interrupt,Interrupt" bitfld.long 0x2C 22. " [23] ,Interrupt Pending Bit[23]" "No interrupt,Interrupt" newline bitfld.long 0x2C 21. " [22] ,Interrupt Pending Bit[22]" "No interrupt,Interrupt" bitfld.long 0x2C 20. " [21] ,Interrupt Pending Bit[21]" "No interrupt,Interrupt" newline bitfld.long 0x2C 19. " [20] ,Interrupt Pending Bit[20]" "No interrupt,Interrupt" bitfld.long 0x2C 18. " [19] ,Interrupt Pending Bit[19]" "No interrupt,Interrupt" newline bitfld.long 0x2C 17. " [18] ,Interrupt Pending Bit[18]" "No interrupt,Interrupt" bitfld.long 0x2C 16. " [17] ,Interrupt Pending Bit[17]" "No interrupt,Interrupt" newline bitfld.long 0x2C 15. " [16] ,Interrupt Pending Bit[16]" "No interrupt,Interrupt" bitfld.long 0x2C 14. " [15] ,Interrupt Pending Bit[15]" "No interrupt,Interrupt" newline bitfld.long 0x2C 13. " [14] ,Interrupt Pending Bit[14]" "No interrupt,Interrupt" bitfld.long 0x2C 12. " [13] ,Interrupt Pending Bit[13]" "No interrupt,Interrupt" newline bitfld.long 0x2C 11. " [12] ,Interrupt Pending Bit[12]" "No interrupt,Interrupt" bitfld.long 0x2C 10. " [11] ,Interrupt Pending Bit[11]" "No interrupt,Interrupt" newline bitfld.long 0x2C 9. " [10] ,Interrupt Pending Bit[10]" "No interrupt,Interrupt" bitfld.long 0x2C 8. " [9] ,Interrupt Pending Bit[9]" "No interrupt,Interrupt" newline bitfld.long 0x2C 7. " [8] ,Interrupt Pending Bit[8]" "No interrupt,Interrupt" bitfld.long 0x2C 6. " [7] ,Interrupt Pending Bit[7]" "No interrupt,Interrupt" newline bitfld.long 0x2C 5. " [6] ,Interrupt Pending Bit[6]" "No interrupt,Interrupt" bitfld.long 0x2C 4. " [5] ,Interrupt Pending Bit[5]" "No interrupt,Interrupt" newline bitfld.long 0x2C 3. " [4] ,Interrupt Pending Bit[4]" "No interrupt,Interrupt" bitfld.long 0x2C 2. " [3] ,Interrupt Pending Bit[3]" "No interrupt,Interrupt" newline bitfld.long 0x2C 1. " [2] ,Interrupt Pending Bit[2]" "No interrupt,Interrupt" bitfld.long 0x2C 0. " [1] ,Interrupt Pending Bit[1]" "No interrupt,Interrupt" line.long 0x30 "INTPEN34,Interrupt Pending 3-4" bitfld.long 0x30 31. " INTPND[64] ,Interrupt Pending Bit[64]" "No interrupt,Interrupt" bitfld.long 0x30 30. " [63] ,Interrupt Pending Bit[63]" "No interrupt,Interrupt" newline bitfld.long 0x30 29. " [62] ,Interrupt Pending Bit[62]" "No interrupt,Interrupt" bitfld.long 0x30 28. " [61] ,Interrupt Pending Bit[61]" "No interrupt,Interrupt" newline bitfld.long 0x30 27. " [60] ,Interrupt Pending Bit[60]" "No interrupt,Interrupt" bitfld.long 0x30 26. " [59] ,Interrupt Pending Bit[59]" "No interrupt,Interrupt" newline bitfld.long 0x30 25. " [58] ,Interrupt Pending Bit[58]" "No interrupt,Interrupt" bitfld.long 0x30 24. " [57] ,Interrupt Pending Bit[57]" "No interrupt,Interrupt" newline bitfld.long 0x30 23. " [56] ,Interrupt Pending Bit[56]" "No interrupt,Interrupt" bitfld.long 0x30 22. " [55] ,Interrupt Pending Bit[55]" "No interrupt,Interrupt" newline bitfld.long 0x30 21. " [54] ,Interrupt Pending Bit[54]" "No interrupt,Interrupt" bitfld.long 0x30 20. " [53] ,Interrupt Pending Bit[53]" "No interrupt,Interrupt" newline bitfld.long 0x30 19. " [52] ,Interrupt Pending Bit[52]" "No interrupt,Interrupt" bitfld.long 0x30 18. " [51] ,Interrupt Pending Bit[51]" "No interrupt,Interrupt" newline bitfld.long 0x30 17. " [50] ,Interrupt Pending Bit[50]" "No interrupt,Interrupt" bitfld.long 0x30 16. " [49] ,Interrupt Pending Bit[49]" "No interrupt,Interrupt" newline bitfld.long 0x30 15. " [48] ,Interrupt Pending Bit[48]" "No interrupt,Interrupt" bitfld.long 0x30 14. " [47] ,Interrupt Pending Bit[47]" "No interrupt,Interrupt" newline bitfld.long 0x30 13. " [46] ,Interrupt Pending Bit[46]" "No interrupt,Interrupt" bitfld.long 0x30 12. " [45] ,Interrupt Pending Bit[45]" "No interrupt,Interrupt" newline bitfld.long 0x30 11. " [44] ,Interrupt Pending Bit[44]" "No interrupt,Interrupt" bitfld.long 0x30 10. " [43] ,Interrupt Pending Bit[43]" "No interrupt,Interrupt" newline bitfld.long 0x30 9. " [42] ,Interrupt Pending Bit[42]" "No interrupt,Interrupt" bitfld.long 0x30 8. " [41] ,Interrupt Pending Bit[41]" "No interrupt,Interrupt" newline bitfld.long 0x30 7. " [40] ,Interrupt Pending Bit[40]" "No interrupt,Interrupt" bitfld.long 0x30 6. " [39] ,Interrupt Pending Bit[39]" "No interrupt,Interrupt" newline bitfld.long 0x30 5. " [38] ,Interrupt Pending Bit[38]" "No interrupt,Interrupt" bitfld.long 0x30 4. " [37] ,Interrupt Pending Bit[37]" "No interrupt,Interrupt" newline bitfld.long 0x30 3. " [36] ,Interrupt Pending Bit[36]" "No interrupt,Interrupt" bitfld.long 0x30 2. " [35] ,Interrupt Pending Bit[35]" "No interrupt,Interrupt" newline bitfld.long 0x30 1. " [34] ,Interrupt Pending Bit[34]" "No interrupt,Interrupt" bitfld.long 0x30 0. " [33] ,Interrupt Pending Bit[33]" "No interrupt,Interrupt" line.long 0x34 "INTPEN56,Interrupt Pending 5-6" bitfld.long 0x34 31. " INTPND[96] ,Interrupt Pending Bit[96]" "No interrupt,Interrupt" bitfld.long 0x34 30. " [95] ,Interrupt Pending Bit[95]" "No interrupt,Interrupt" newline bitfld.long 0x34 29. " [94] ,Interrupt Pending Bit[94]" "No interrupt,Interrupt" bitfld.long 0x34 28. " [93] ,Interrupt Pending Bit[93]" "No interrupt,Interrupt" newline bitfld.long 0x34 27. " [92] ,Interrupt Pending Bit[92]" "No interrupt,Interrupt" bitfld.long 0x34 26. " [91] ,Interrupt Pending Bit[91]" "No interrupt,Interrupt" newline bitfld.long 0x34 25. " [90] ,Interrupt Pending Bit[90]" "No interrupt,Interrupt" bitfld.long 0x34 24. " [89] ,Interrupt Pending Bit[89]" "No interrupt,Interrupt" newline bitfld.long 0x34 23. " [88] ,Interrupt Pending Bit[88]" "No interrupt,Interrupt" bitfld.long 0x34 22. " [87] ,Interrupt Pending Bit[87]" "No interrupt,Interrupt" newline bitfld.long 0x34 21. " [86] ,Interrupt Pending Bit[86]" "No interrupt,Interrupt" bitfld.long 0x34 20. " [85] ,Interrupt Pending Bit[85]" "No interrupt,Interrupt" newline bitfld.long 0x34 19. " [84] ,Interrupt Pending Bit[84]" "No interrupt,Interrupt" bitfld.long 0x34 18. " [83] ,Interrupt Pending Bit[83]" "No interrupt,Interrupt" newline bitfld.long 0x34 17. " [82] ,Interrupt Pending Bit[82]" "No interrupt,Interrupt" bitfld.long 0x34 16. " [81] ,Interrupt Pending Bit[81]" "No interrupt,Interrupt" newline bitfld.long 0x34 15. " [80] ,Interrupt Pending Bit[80]" "No interrupt,Interrupt" bitfld.long 0x34 14. " [79] ,Interrupt Pending Bit[79]" "No interrupt,Interrupt" newline bitfld.long 0x34 13. " [78] ,Interrupt Pending Bit[78]" "No interrupt,Interrupt" bitfld.long 0x34 12. " [77] ,Interrupt Pending Bit[77]" "No interrupt,Interrupt" newline bitfld.long 0x34 11. " [76] ,Interrupt Pending Bit[76]" "No interrupt,Interrupt" bitfld.long 0x34 10. " [75] ,Interrupt Pending Bit[75]" "No interrupt,Interrupt" newline bitfld.long 0x34 9. " [74] ,Interrupt Pending Bit[74]" "No interrupt,Interrupt" bitfld.long 0x34 8. " [73] ,Interrupt Pending Bit[73]" "No interrupt,Interrupt" newline bitfld.long 0x34 7. " [72] ,Interrupt Pending Bit[72]" "No interrupt,Interrupt" bitfld.long 0x34 6. " [71] ,Interrupt Pending Bit[71]" "No interrupt,Interrupt" newline bitfld.long 0x34 5. " [70] ,Interrupt Pending Bit[70]" "No interrupt,Interrupt" bitfld.long 0x34 4. " [69] ,Interrupt Pending Bit[69]" "No interrupt,Interrupt" newline bitfld.long 0x34 3. " [68] ,Interrupt Pending Bit[68]" "No interrupt,Interrupt" bitfld.long 0x34 2. " [67] ,Interrupt Pending Bit[67]" "No interrupt,Interrupt" newline bitfld.long 0x34 1. " [66] ,Interrupt Pending Bit[66]" "No interrupt,Interrupt" bitfld.long 0x34 0. " [65] ,Interrupt Pending Bit[65]" "No interrupt,Interrupt" line.long 0x38 "INTPEN78,Interrupt Pending 7-8" bitfld.long 0x38 31. " INTPND[128] ,Interrupt Pending Bit[128]" "No interrupt,Interrupt" bitfld.long 0x38 30. " [127] ,Interrupt Pending Bit[127]" "No interrupt,Interrupt" newline bitfld.long 0x38 29. " [126] ,Interrupt Pending Bit[126]" "No interrupt,Interrupt" bitfld.long 0x38 28. " [125] ,Interrupt Pending Bit[125]" "No interrupt,Interrupt" newline bitfld.long 0x38 27. " [124] ,Interrupt Pending Bit[124]" "No interrupt,Interrupt" bitfld.long 0x38 26. " [123] ,Interrupt Pending Bit[123]" "No interrupt,Interrupt" newline bitfld.long 0x38 25. " [122] ,Interrupt Pending Bit[122]" "No interrupt,Interrupt" bitfld.long 0x38 24. " [121] ,Interrupt Pending Bit[121]" "No interrupt,Interrupt" newline bitfld.long 0x38 23. " [120] ,Interrupt Pending Bit[120]" "No interrupt,Interrupt" bitfld.long 0x38 22. " [119] ,Interrupt Pending Bit[119]" "No interrupt,Interrupt" newline bitfld.long 0x38 21. " [118] ,Interrupt Pending Bit[118]" "No interrupt,Interrupt" bitfld.long 0x38 20. " [117] ,Interrupt Pending Bit[117]" "No interrupt,Interrupt" newline bitfld.long 0x38 19. " [116] ,Interrupt Pending Bit[116]" "No interrupt,Interrupt" bitfld.long 0x38 18. " [115] ,Interrupt Pending Bit[115]" "No interrupt,Interrupt" newline bitfld.long 0x38 17. " [114] ,Interrupt Pending Bit[114]" "No interrupt,Interrupt" bitfld.long 0x38 16. " [113] ,Interrupt Pending Bit[113]" "No interrupt,Interrupt" newline bitfld.long 0x38 15. " [112] ,Interrupt Pending Bit[112]" "No interrupt,Interrupt" bitfld.long 0x38 14. " [111] ,Interrupt Pending Bit[111]" "No interrupt,Interrupt" newline bitfld.long 0x38 13. " [110] ,Interrupt Pending Bit[110]" "No interrupt,Interrupt" bitfld.long 0x38 12. " [109] ,Interrupt Pending Bit[109]" "No interrupt,Interrupt" newline bitfld.long 0x38 11. " [108] ,Interrupt Pending Bit[108]" "No interrupt,Interrupt" bitfld.long 0x38 10. " [107] ,Interrupt Pending Bit[107]" "No interrupt,Interrupt" newline bitfld.long 0x38 9. " [106] ,Interrupt Pending Bit[106]" "No interrupt,Interrupt" bitfld.long 0x38 8. " [105] ,Interrupt Pending Bit[105]" "No interrupt,Interrupt" newline bitfld.long 0x38 7. " [104] ,Interrupt Pending Bit[104]" "No interrupt,Interrupt" bitfld.long 0x38 6. " [103] ,Interrupt Pending Bit[103]" "No interrupt,Interrupt" newline bitfld.long 0x38 5. " [102] ,Interrupt Pending Bit[102]" "No interrupt,Interrupt" bitfld.long 0x38 4. " [101] ,Interrupt Pending Bit[101]" "No interrupt,Interrupt" newline bitfld.long 0x38 3. " [100] ,Interrupt Pending Bit[100]" "No interrupt,Interrupt" bitfld.long 0x38 2. " [99] ,Interrupt Pending Bit[99]" "No interrupt,Interrupt" newline bitfld.long 0x38 1. " [98] ,Interrupt Pending Bit[98]" "No interrupt,Interrupt" bitfld.long 0x38 0. " [97] ,Interrupt Pending Bit[97]" "No interrupt,Interrupt" line.long 0x3C "MVAL,Message Valid X" bitfld.long 0x3C 14.--15. " MSGVALREG8 ,Message Valid Register 8" "0,1,2,3" bitfld.long 0x3C 12.--13. " [7] ,Message Valid Register 7" "0,1,2,3" bitfld.long 0x3C 10.--11. " [6] ,Message Valid Register 6" "0,1,2,3" bitfld.long 0x3C 8.--9. " [5] ,Message Valid Register 5" "0,1,2,3" newline bitfld.long 0x3C 6.--7. " [4] ,Message Valid Register 4" "0,1,2,3" bitfld.long 0x3C 4.--5. " [3] ,Message Valid Register 3" "0,1,2,3" bitfld.long 0x3C 2.--3. " [2] ,Message Valid Register 2" "0,1,2,3" bitfld.long 0x3C 0.--1. " [1] ,Message Valid Register 1" "0,1,2,3" line.long 0x40 "MVAL12,Message Valid 1-2" bitfld.long 0x40 31. " MSGVAL[32] ,Message Valid Bit[32]" "Ignored,Configured" bitfld.long 0x40 30. " [31] ,Message Valid Bit[31]" "Ignored,Configured" newline bitfld.long 0x40 29. " [30] ,Message Valid Bit[30]" "Ignored,Configured" bitfld.long 0x40 28. " [29] ,Message Valid Bit[29]" "Ignored,Configured" newline bitfld.long 0x40 27. " [28] ,Message Valid Bit[28]" "Ignored,Configured" bitfld.long 0x40 26. " [27] ,Message Valid Bit[27]" "Ignored,Configured" newline bitfld.long 0x40 25. " [26] ,Message Valid Bit[26]" "Ignored,Configured" bitfld.long 0x40 24. " [25] ,Message Valid Bit[25]" "Ignored,Configured" newline bitfld.long 0x40 23. " [24] ,Message Valid Bit[24]" "Ignored,Configured" bitfld.long 0x40 22. " [23] ,Message Valid Bit[23]" "Ignored,Configured" newline bitfld.long 0x40 21. " [22] ,Message Valid Bit[22]" "Ignored,Configured" bitfld.long 0x40 20. " [21] ,Message Valid Bit[21]" "Ignored,Configured" newline bitfld.long 0x40 19. " [20] ,Message Valid Bit[20]" "Ignored,Configured" bitfld.long 0x40 18. " [19] ,Message Valid Bit[19]" "Ignored,Configured" newline bitfld.long 0x40 17. " [18] ,Message Valid Bit[18]" "Ignored,Configured" bitfld.long 0x40 16. " [17] ,Message Valid Bit[17]" "Ignored,Configured" newline bitfld.long 0x40 15. " [16] ,Message Valid Bit[16]" "Ignored,Configured" bitfld.long 0x40 14. " [15] ,Message Valid Bit[15]" "Ignored,Configured" newline bitfld.long 0x40 13. " [14] ,Message Valid Bit[14]" "Ignored,Configured" bitfld.long 0x40 12. " [13] ,Message Valid Bit[13]" "Ignored,Configured" newline bitfld.long 0x40 11. " [12] ,Message Valid Bit[12]" "Ignored,Configured" bitfld.long 0x40 10. " [11] ,Message Valid Bit[11]" "Ignored,Configured" newline bitfld.long 0x40 9. " [10] ,Message Valid Bit[10]" "Ignored,Configured" bitfld.long 0x40 8. " [9] ,Message Valid Bit[9]" "Ignored,Configured" newline bitfld.long 0x40 7. " [8] ,Message Valid Bit[8]" "Ignored,Configured" bitfld.long 0x40 6. " [7] ,Message Valid Bit[7]" "Ignored,Configured" newline bitfld.long 0x40 5. " [6] ,Message Valid Bit[6]" "Ignored,Configured" bitfld.long 0x40 4. " [5] ,Message Valid Bit[5]" "Ignored,Configured" newline bitfld.long 0x40 3. " [4] ,Message Valid Bit[4]" "Ignored,Configured" bitfld.long 0x40 2. " [3] ,Message Valid Bit[3]" "Ignored,Configured" newline bitfld.long 0x40 1. " [2] ,Message Valid Bit[2]" "Ignored,Configured" bitfld.long 0x40 0. " [1] ,Message Valid Bit[1]" "Ignored,Configured" line.long 0x44 "MVAL34,Message Valid 3-4" bitfld.long 0x44 31. " MSGVAl[64] ,Message Valid Bit[64]" "Ignored,Configured" bitfld.long 0x44 30. " [63] ,Message Valid Bit[63]" "Ignored,Configured" newline bitfld.long 0x44 29. " [62] ,Message Valid Bit[62]" "Ignored,Configured" bitfld.long 0x44 28. " [61] ,Message Valid Bit[61]" "Ignored,Configured" newline bitfld.long 0x44 27. " [60] ,Message Valid Bit[60]" "Ignored,Configured" bitfld.long 0x44 26. " [59] ,Message Valid Bit[59]" "Ignored,Configured" newline bitfld.long 0x44 25. " [58] ,Message Valid Bit[58]" "Ignored,Configured" bitfld.long 0x44 24. " [57] ,Message Valid Bit[57]" "Ignored,Configured" newline bitfld.long 0x44 23. " [56] ,Message Valid Bit[56]" "Ignored,Configured" bitfld.long 0x44 22. " [55] ,Message Valid Bit[55]" "Ignored,Configured" newline bitfld.long 0x44 21. " [54] ,Message Valid Bit[54]" "Ignored,Configured" bitfld.long 0x44 20. " [53] ,Message Valid Bit[53]" "Ignored,Configured" newline bitfld.long 0x44 19. " [52] ,Message Valid Bit[52]" "Ignored,Configured" bitfld.long 0x44 18. " [51] ,Message Valid Bit[51]" "Ignored,Configured" newline bitfld.long 0x44 17. " [50] ,Message Valid Bit[50]" "Ignored,Configured" bitfld.long 0x44 16. " [49] ,Message Valid Bit[49]" "Ignored,Configured" newline bitfld.long 0x44 15. " [48] ,Message Valid Bit[48]" "Ignored,Configured" bitfld.long 0x44 14. " [47] ,Message Valid Bit[47]" "Ignored,Configured" newline bitfld.long 0x44 13. " [46] ,Message Valid Bit[46]" "Ignored,Configured" bitfld.long 0x44 12. " [45] ,Message Valid Bit[45]" "Ignored,Configured" newline bitfld.long 0x44 11. " [44] ,Message Valid Bit[44]" "Ignored,Configured" bitfld.long 0x44 10. " [43] ,Message Valid Bit[43]" "Ignored,Configured" newline bitfld.long 0x44 9. " [42] ,Message Valid Bit[42]" "Ignored,Configured" bitfld.long 0x44 8. " [41] ,Message Valid Bit[41]" "Ignored,Configured" newline bitfld.long 0x44 7. " [40] ,Message Valid Bit[40]" "Ignored,Configured" bitfld.long 0x44 6. " [39] ,Message Valid Bit[39]" "Ignored,Configured" newline bitfld.long 0x44 5. " [38] ,Message Valid Bit[38]" "Ignored,Configured" bitfld.long 0x44 4. " [37] ,Message Valid Bit[37]" "Ignored,Configured" newline bitfld.long 0x44 3. " [36] ,Message Valid Bit[36]" "Ignored,Configured" bitfld.long 0x44 2. " [35] ,Message Valid Bit[35]" "Ignored,Configured" newline bitfld.long 0x44 1. " [34] ,Message Valid Bit[34]" "Ignored,Configured" bitfld.long 0x44 0. " [33] ,Message Valid Bit[33]" "Ignored,Configured" line.long 0x48 "MVAL56,Message Valid 5-6" bitfld.long 0x48 31. " MSGVAl[96] ,Message Valid Bit[96]" "Ignored,Configured" bitfld.long 0x48 30. " [95] ,Message Valid Bit[95]" "Ignored,Configured" newline bitfld.long 0x48 29. " [94] ,Message Valid Bit[94]" "Ignored,Configured" bitfld.long 0x48 28. " [93] ,Message Valid Bit[93]" "Ignored,Configured" newline bitfld.long 0x48 27. " [92] ,Message Valid Bit[92]" "Ignored,Configured" bitfld.long 0x48 26. " [91] ,Message Valid Bit[91]" "Ignored,Configured" newline bitfld.long 0x48 25. " [90] ,Message Valid Bit[90]" "Ignored,Configured" bitfld.long 0x48 24. " [89] ,Message Valid Bit[89]" "Ignored,Configured" newline bitfld.long 0x48 23. " [88] ,Message Valid Bit[88]" "Ignored,Configured" bitfld.long 0x48 22. " [87] ,Message Valid Bit[87]" "Ignored,Configured" newline bitfld.long 0x48 21. " [86] ,Message Valid Bit[86]" "Ignored,Configured" bitfld.long 0x48 20. " [85] ,Message Valid Bit[85]" "Ignored,Configured" newline bitfld.long 0x48 19. " [84] ,Message Valid Bit[84]" "Ignored,Configured" bitfld.long 0x48 18. " [83] ,Message Valid Bit[83]" "Ignored,Configured" newline bitfld.long 0x48 17. " [82] ,Message Valid Bit[82]" "Ignored,Configured" bitfld.long 0x48 16. " [81] ,Message Valid Bit[81]" "Ignored,Configured" newline bitfld.long 0x48 15. " [80] ,Message Valid Bit[80]" "Ignored,Configured" bitfld.long 0x48 14. " [79] ,Message Valid Bit[79]" "Ignored,Configured" newline bitfld.long 0x48 13. " [78] ,Message Valid Bit[78]" "Ignored,Configured" bitfld.long 0x48 12. " [77] ,Message Valid Bit[77]" "Ignored,Configured" newline bitfld.long 0x48 11. " [76] ,Message Valid Bit[76]" "Ignored,Configured" bitfld.long 0x48 10. " [75] ,Message Valid Bit[75]" "Ignored,Configured" newline bitfld.long 0x48 9. " [74] ,Message Valid Bit[74]" "Ignored,Configured" bitfld.long 0x48 8. " [73] ,Message Valid Bit[73]" "Ignored,Configured" newline bitfld.long 0x48 7. " [72] ,Message Valid Bit[72]" "Ignored,Configured" bitfld.long 0x48 6. " [71] ,Message Valid Bit[71]" "Ignored,Configured" newline bitfld.long 0x48 5. " [70] ,Message Valid Bit[70]" "Ignored,Configured" bitfld.long 0x48 4. " [69] ,Message Valid Bit[69]" "Ignored,Configured" newline bitfld.long 0x48 3. " [68] ,Message Valid Bit[68]" "Ignored,Configured" bitfld.long 0x48 2. " [67] ,Message Valid Bit[67]" "Ignored,Configured" newline bitfld.long 0x48 1. " [66] ,Message Valid Bit[66]" "Ignored,Configured" bitfld.long 0x48 0. " [65] ,Message Valid Bit[65]" "Ignored,Configured" line.long 0x4C "MVAL78,Message Valid 7-8" bitfld.long 0x4C 31. " MSGVAl[128] ,Message Valid Bit[128]" "Ignored,Configured" bitfld.long 0x4C 30. " [127] ,Message Valid Bit[127]" "Ignored,Configured" newline bitfld.long 0x4C 29. " [126] ,Message Valid Bit[126]" "Ignored,Configured" bitfld.long 0x4C 28. " [125] ,Message Valid Bit[125]" "Ignored,Configured" newline bitfld.long 0x4C 27. " [124] ,Message Valid Bit[124]" "Ignored,Configured" bitfld.long 0x4C 26. " [123] ,Message Valid Bit[123]" "Ignored,Configured" newline bitfld.long 0x4C 25. " [122] ,Message Valid Bit[122]" "Ignored,Configured" bitfld.long 0x4C 24. " [121] ,Message Valid Bit[121]" "Ignored,Configured" newline bitfld.long 0x4C 23. " [120] ,Message Valid Bit[120]" "Ignored,Configured" bitfld.long 0x4C 22. " [119] ,Message Valid Bit[119]" "Ignored,Configured" newline bitfld.long 0x4C 21. " [118] ,Message Valid Bit[118]" "Ignored,Configured" bitfld.long 0x4C 20. " [117] ,Message Valid Bit[117]" "Ignored,Configured" newline bitfld.long 0x4C 19. " [116] ,Message Valid Bit[116]" "Ignored,Configured" bitfld.long 0x4C 18. " [115] ,Message Valid Bit[115]" "Ignored,Configured" newline bitfld.long 0x4C 17. " [114] ,Message Valid Bit[114]" "Ignored,Configured" bitfld.long 0x4C 16. " [113] ,Message Valid Bit[113]" "Ignored,Configured" newline bitfld.long 0x4C 15. " [112] ,Message Valid Bit[112]" "Ignored,Configured" bitfld.long 0x4C 14. " [111] ,Message Valid Bit[111]" "Ignored,Configured" newline bitfld.long 0x4C 13. " [110] ,Message Valid Bit[110]" "Ignored,Configured" bitfld.long 0x4C 12. " [109] ,Message Valid Bit[109]" "Ignored,Configured" newline bitfld.long 0x4C 11. " [108] ,Message Valid Bit[108]" "Ignored,Configured" bitfld.long 0x4C 10. " [107] ,Message Valid Bit[107]" "Ignored,Configured" newline bitfld.long 0x4C 9. " [106] ,Message Valid Bit[106]" "Ignored,Configured" bitfld.long 0x4C 8. " [105] ,Message Valid Bit[105]" "Ignored,Configured" newline bitfld.long 0x4C 7. " [104] ,Message Valid Bit[104]" "Ignored,Configured" bitfld.long 0x4C 6. " [103] ,Message Valid Bit[103]" "Ignored,Configured" newline bitfld.long 0x4C 5. " [102] ,Message Valid Bit[102]" "Ignored,Configured" bitfld.long 0x4C 4. " [101] ,Message Valid Bit[101]" "Ignored,Configured" newline bitfld.long 0x4C 3. " [100] ,Message Valid Bit[100]" "Ignored,Configured" bitfld.long 0x4C 2. " [99] ,Message Valid Bit[99]" "Ignored,Configured" newline bitfld.long 0x4C 1. " [98] ,Message Valid Bit[98]" "Ignored,Configured" bitfld.long 0x4C 0. " [97] ,Message Valid Bit[97]" "Ignored,Configured" group.long 0xD8++0x0F line.long 0x00 "INTPMX12,Interrupt Multiplexer 1-2" bitfld.long 0x00 31. " INTPNDMUX[32] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[32]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 30. " [31] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[31]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x00 29. " [30] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[30]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 28. " [29] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[29]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x00 27. " [28] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[28]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 26. " [27] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[27]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x00 25. " [26] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[26]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 24. " [25] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[25]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x00 23. " [24] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[24]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 22. " [23] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[23]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x00 21. " [22] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[22]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 20. " [21] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[21]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x00 19. " [20] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[20]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 18. " [19] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[19]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x00 17. " [18] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[18]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 16. " [17] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[17]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x00 15. " [16] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[16]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 14. " [15] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[15]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x00 13. " [14] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[14]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 12. " [13] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[13]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x00 11. " [12] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[12]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 10. " [11] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[11]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x00 9. " [10] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[10]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 8. " [9] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[9]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x00 7. " [8] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[8]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 6. " [7] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[7]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x00 5. " [6] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[6]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 4. " [5] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[5]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x00 3. " [4] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[4]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 2. " [3] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[3]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x00 1. " [2] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[2]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 0. " [1] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[1]" "DCAN0INT,DCAN1INT" line.long 0x04 "INTPMX34,Interrupt Multiplexer 3-4" bitfld.long 0x04 31. " INTPNDMUX[64] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[64]" "DCAN0INT,DCAN1INT" bitfld.long 0x04 30. " [63] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[63]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x04 29. " [62] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[62]" "DCAN0INT,DCAN1INT" bitfld.long 0x04 28. " [61] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[61]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x04 27. " [60] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[60]" "DCAN0INT,DCAN1INT" bitfld.long 0x04 26. " [59] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[59]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x04 25. " [58] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[58]" "DCAN0INT,DCAN1INT" bitfld.long 0x04 24. " [57] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[57]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x04 23. " [56] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[56]" "DCAN0INT,DCAN1INT" bitfld.long 0x04 22. " [55] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[55]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x04 21. " [54] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[54]" "DCAN0INT,DCAN1INT" bitfld.long 0x04 20. " [53] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[53]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x04 19. " [52] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[52]" "DCAN0INT,DCAN1INT" bitfld.long 0x04 18. " [51] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[51]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x04 17. " [50] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[50]" "DCAN0INT,DCAN1INT" bitfld.long 0x04 16. " [49] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[49]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x04 15. " [48] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[48]" "DCAN0INT,DCAN1INT" bitfld.long 0x04 14. " [47] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[47]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x04 13. " [46] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[46]" "DCAN0INT,DCAN1INT" bitfld.long 0x04 12. " [45] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[45]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x04 11. " [44] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[44]" "DCAN0INT,DCAN1INT" bitfld.long 0x04 10. " [43] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[43]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x04 9. " [42] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[42]" "DCAN0INT,DCAN1INT" bitfld.long 0x04 8. " [41] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[41]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x04 7. " [40] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[40]" "DCAN0INT,DCAN1INT" bitfld.long 0x04 6. " [39] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[39]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x04 5. " [38] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[38]" "DCAN0INT,DCAN1INT" bitfld.long 0x04 4. " [37] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[37]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x04 3. " [36] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[36]" "DCAN0INT,DCAN1INT" bitfld.long 0x04 2. " [35] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[35]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x04 1. " [34] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[34]" "DCAN0INT,DCAN1INT" bitfld.long 0x04 0. " [33] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[33]" "DCAN0INT,DCAN1INT" line.long 0x08 "INTPMX56,Interrupt Multiplexer 5-6" bitfld.long 0x08 31. " INTPNDMUX[96] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[96]" "DCAN0INT,DCAN1INT" bitfld.long 0x08 30. " [95] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[95]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x08 29. " [94] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[94]" "DCAN0INT,DCAN1INT" bitfld.long 0x08 28. " [93] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[93]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x08 27. " [92] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[92]" "DCAN0INT,DCAN1INT" bitfld.long 0x08 26. " [91] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[91]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x08 25. " [90] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[90]" "DCAN0INT,DCAN1INT" bitfld.long 0x08 24. " [89] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[89]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x08 23. " [88] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[88]" "DCAN0INT,DCAN1INT" bitfld.long 0x08 22. " [87] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[87]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x08 21. " [86] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[86]" "DCAN0INT,DCAN1INT" bitfld.long 0x08 20. " [85] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[85]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x08 19. " [84] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[84]" "DCAN0INT,DCAN1INT" bitfld.long 0x08 18. " [83] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[83]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x08 17. " [82] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[82]" "DCAN0INT,DCAN1INT" bitfld.long 0x08 16. " [81] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[81]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x08 15. " [80] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[80]" "DCAN0INT,DCAN1INT" bitfld.long 0x08 14. " [79] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[79]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x08 13. " [78] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[78]" "DCAN0INT,DCAN1INT" bitfld.long 0x08 12. " [77] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[77]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x08 11. " [76] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[76]" "DCAN0INT,DCAN1INT" bitfld.long 0x08 10. " [75] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[75]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x08 9. " [74] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[74]" "DCAN0INT,DCAN1INT" bitfld.long 0x08 8. " [73] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[73]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x08 7. " [72] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[72]" "DCAN0INT,DCAN1INT" bitfld.long 0x08 6. " [71] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[71]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x08 5. " [70] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[70]" "DCAN0INT,DCAN1INT" bitfld.long 0x08 4. " [69] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[69]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x08 3. " [68] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[68]" "DCAN0INT,DCAN1INT" bitfld.long 0x08 2. " [67] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[67]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x08 1. " [66] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[66]" "DCAN0INT,DCAN1INT" bitfld.long 0x08 0. " [65] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[65]" "DCAN0INT,DCAN1INT" line.long 0x0C "INTPMX78,Interrupt Multiplexer 7-8" bitfld.long 0x0C 31. " INTPNDMUX[128] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[128]" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 30. " [127] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[127]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x0C 29. " [126] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[126]" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 28. " [125] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[125]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x0C 27. " [124] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[124]" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 26. " [123] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[123]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x0C 25. " [122] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[122]" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 24. " [121] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[121]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x0C 23. " [120] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[120]" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 22. " [119] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[119]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x0C 21. " [118] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[118]" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 20. " [117] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[117]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x0C 19. " [116] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[116]" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 18. " [115] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[115]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x0C 17. " [114] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[114]" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 16. " [113] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[113]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x0C 15. " [112] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[112]" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 14. " [111] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[111]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x0C 13. " [110] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[110]" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 12. " [109] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[109]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x0C 11. " [108] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[108]" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 10. " [107] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[107]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x0C 9. " [106] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[106]" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 8. " [105] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[105]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x0C 7. " [104] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[104]" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 6. " [103] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[103]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x0C 5. " [102] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[102]" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 4. " [101] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[101]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x0C 3. " [100] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[100]" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 2. " [99] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[99]" "DCAN0INT,DCAN1INT" newline bitfld.long 0x0C 1. " [98] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[98]" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 0. " [97] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[97]" "DCAN0INT,DCAN1INT" group.long 0x100++0x3 "IF1" line.long 0x00 "IF1COM,IF1 Command Mask / Command Request Register" bitfld.long 0x00 23. " WR/RD ,Write / Read direction" "Read,Write" newline bitfld.long 0x00 22. " MASK ,Access Mask Bits" "Unchanged,Identifier Mask+MDir+MXtd" newline bitfld.long 0x00 21. " ARB ,Access Arbitration Bits" "Unchanged,Identifier+Dir+Xtd+MSGVAl" newline bitfld.long 0x00 20. " CONTROL ,Access Control Bits" "Unchanged,Control bits" bitfld.long 0x00 19. " CLRINTPND ,Clear Interrupt Pending Bit" "Low,High" newline bitfld.long 0x00 18. " TXRQST/NEWDAT ,Access Transmission Request Bit" "Not requested,Requested" bitfld.long 0x00 17. " DATA_A ,Access Data Bytes 0-3" "Unchanged,Data bytes 0-3" newline bitfld.long 0x00 16. " DATA_B ,Access Data Bytes 4-7" "Unchanged,Data bytes 4-7" bitfld.long 0x00 15. " BUSY ,Busy Flag" "Not busy,Busy" newline sif (!cpuis("TMS570LS0332")&&!cpuis("TMS570LS0432")) bitfld.long 0x00 14. " DMAACTIVE ,Activation of DMA Feature for Subsequent Internal IF1 Update" "No active,Active" newline endif hexmask.long.byte 0x00 0.--7. 1. " MESSAGE_NUMBER ,Message Number" sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS3137-EP") if (((per.l.be(((ad:0xFFF7E000+0x100+0x08))))&0x40000000)==0x0) group.long (0x100+0x04)++0x07 line.long 0x0 "IF1MASK,IF1 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering" newline bitfld.long 0x00 28. " ID ,Message Identifier bit[10]" "0,1" bitfld.long 0x00 27. ",Message Identifier bit[9]" "0,1" bitfld.long 0x00 26. ",Message Identifier bit[8]" "0,1" bitfld.long 0x00 25. ",Message Identifier bit[7]" "0,1" bitfld.long 0x00 24. ",Message Identifier bit[6]" "0,1" bitfld.long 0x00 23. ",Message Identifier bit[5]" "0,1" bitfld.long 0x00 22. ",Message Identifier bit[4]" "0,1" bitfld.long 0x00 21. ",Message Identifier bit[3]" "0,1" bitfld.long 0x00 20. ",Message Identifier bit[2]" "0,1" bitfld.long 0x00 19. ",Message Identifier bit[1]" "0,1" bitfld.long 0x00 18. ",Message Identifier bit[0]" "0,1" line.long 0x04 "IF1ARB,IF1 Arbitration Register" bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure" bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit" bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit" hexmask.long.word 0x04 18.--28. 1. " ID ,Message Identifier" else group.long (0x100+0x04)++0x07 line.long 0x00 "IF1MASK,IF1 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering" newline bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1" bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1" bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1" bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1" bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1" bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1" bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1" bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1" bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1" bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1" bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1" bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1" bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1" bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1" bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1" bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1" bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1" bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1" bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1" bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1" bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1" bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1" bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1" bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1" bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1" bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1" bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1" bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1" bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1" line.long 0x04 "IF1ARB,IF1 Arbitation Register" bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure" bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit" bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit" hexmask.long 0x04 0.--28. 1. " ID ,Message Identifier" endif else if (((per.l(((ad:0xFFF7E000+0x100+0x08))))&0x40000000)==0x0) group.long (0x100+0x04)++0x07 line.long 0x0 "IF1MASK,IF1 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering" newline bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1" bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1" bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1" bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1" bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1" bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1" bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1" bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1" bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1" bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1" bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1" line.long 0x04 "IF1ARB,IF1 Arbitation Register" bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure" bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit" bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit" hexmask.long.word 0x04 18.--28. 1. " ID ,Message Identifier" else group.long (0x100+0x04)++0x07 line.long 0x0 "IF1MASK,IF1 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering" newline bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1" bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1" bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1" bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1" bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1" bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1" bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1" bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1" bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1" bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1" bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1" bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1" bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1" bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1" bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1" bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1" bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1" bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1" bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1" bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1" bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1" bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1" bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1" bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1" bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1" bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1" bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1" bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1" bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1" line.long 0x04 "IF1ARB,IF1 Arbitation Register" bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure" bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit" bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit" hexmask.long 0x04 0.--28. 1. " ID ,Message Identifier" endif endif group.long (0x100+0x0C)++0x0B line.long 0x00 "IF1MCTRL,IF1 Message Control Register" bitfld.long 0x00 15. " NEWDAT ,New Data" "No new data,New data" bitfld.long 0x00 14. " MSGLST ,Message Lost" "Not lost,Lost" bitfld.long 0x00 13. " INTPND ,Interrupt Pending" "No interrupt,Interrupt" newline bitfld.long 0x00 12. " UMASK ,Use Acceptance Mask" "Ignored,Masked" bitfld.long 0x00 11. " TXIE ,Transmit Interrupt Enable" "Unchanged,Set" bitfld.long 0x00 10. " RXIE ,Receive Interrupt Enable" "Unchanged,Set" newline bitfld.long 0x00 9. " RMTEN ,Remote Enable" "Disabled,Enabled" bitfld.long 0x00 8. " TXRQST ,Transmit Request" "Not requested,Requested" bitfld.long 0x00 7. " EOB ,End of Block" "Single/Last,Not last" newline bitfld.long 0x00 0.--3. " DLC[3-0] ,Data Length Code" "0 byte,1 bytes,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes" line.long 0x04 "IF1DATA,IF1 Data A Register" hexmask.long.byte 0x04 24.--31. 1. " DATA[3] ,4th data byte of a CAN Data Frame" hexmask.long.byte 0x04 16.--23. 1. " [2] ,3rd data byte of a CAN Data Frame" hexmask.long.byte 0x04 8.--15. 1. " [1] ,2nd data byte of a CAN Data Frame" hexmask.long.byte 0x04 0.--7. 1. " [0] ,1st data byte of a CAN Data Frame" line.long 0x08 "IF1DATB,IF1 Data B Register" hexmask.long.byte 0x08 24.--31. 1. " DATA[7] ,8th data byte of a CAN Data Frame" hexmask.long.byte 0x08 16.--23. 1. " [6] ,7th data byte of a CAN Data Frame" hexmask.long.byte 0x08 8.--15. 1. " [5] ,6th data byte of a CAN Data Frame" hexmask.long.byte 0x08 0.--7. 1. " [4] ,5th data byte of a CAN Data Frame" group.long 0x120++0x3 "IF2" line.long 0x00 "IF2COM,IF2 Command Mask / Command Request Register" bitfld.long 0x00 23. " WR/RD ,Write / Read direction" "Read,Write" newline bitfld.long 0x00 22. " MASK ,Access Mask Bits" "Unchanged,Identifier Mask+MDir+MXtd" newline bitfld.long 0x00 21. " ARB ,Access Arbitration Bits" "Unchanged,Identifier+Dir+Xtd+MSGVAl" newline bitfld.long 0x00 20. " CONTROL ,Access Control Bits" "Unchanged,Control bits" bitfld.long 0x00 19. " CLRINTPND ,Clear Interrupt Pending Bit" "Low,High" newline bitfld.long 0x00 18. " TXRQST/NEWDAT ,Access Transmission Request Bit" "Not requested,Requested" bitfld.long 0x00 17. " DATA_A ,Access Data Bytes 0-3" "Unchanged,Data bytes 0-3" newline bitfld.long 0x00 16. " DATA_B ,Access Data Bytes 4-7" "Unchanged,Data bytes 4-7" bitfld.long 0x00 15. " BUSY ,Busy Flag" "Not busy,Busy" newline sif (!cpuis("TMS570LS0332")&&!cpuis("TMS570LS0432")) bitfld.long 0x00 14. " DMAACTIVE ,Activation of DMA Feature for Subsequent Internal IF1 Update" "No active,Active" newline endif hexmask.long.byte 0x00 0.--7. 1. " MESSAGE_NUMBER ,Message Number" sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS3137-EP") if (((per.l.be(((ad:0xFFF7E000+0x120+0x08))))&0x40000000)==0x0) group.long (0x120+0x04)++0x07 line.long 0x0 "IF2MASK,IF2 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering" newline bitfld.long 0x00 28. " ID ,Message Identifier bit[10]" "0,1" bitfld.long 0x00 27. ",Message Identifier bit[9]" "0,1" bitfld.long 0x00 26. ",Message Identifier bit[8]" "0,1" bitfld.long 0x00 25. ",Message Identifier bit[7]" "0,1" bitfld.long 0x00 24. ",Message Identifier bit[6]" "0,1" bitfld.long 0x00 23. ",Message Identifier bit[5]" "0,1" bitfld.long 0x00 22. ",Message Identifier bit[4]" "0,1" bitfld.long 0x00 21. ",Message Identifier bit[3]" "0,1" bitfld.long 0x00 20. ",Message Identifier bit[2]" "0,1" bitfld.long 0x00 19. ",Message Identifier bit[1]" "0,1" bitfld.long 0x00 18. ",Message Identifier bit[0]" "0,1" line.long 0x04 "IF2ARB,IF2 Arbitration Register" bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure" bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit" bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit" hexmask.long.word 0x04 18.--28. 1. " ID ,Message Identifier" else group.long (0x120+0x04)++0x07 line.long 0x00 "IF2MASK,IF2 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering" newline bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1" bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1" bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1" bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1" bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1" bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1" bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1" bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1" bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1" bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1" bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1" bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1" bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1" bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1" bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1" bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1" bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1" bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1" bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1" bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1" bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1" bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1" bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1" bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1" bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1" bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1" bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1" bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1" bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1" line.long 0x04 "IF2ARB,IF2 Arbitation Register" bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure" bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit" bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit" hexmask.long 0x04 0.--28. 1. " ID ,Message Identifier" endif else if (((per.l(((ad:0xFFF7E000+0x120+0x08))))&0x40000000)==0x0) group.long (0x120+0x04)++0x07 line.long 0x0 "IF2MASK,IF2 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering" newline bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1" bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1" bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1" bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1" bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1" bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1" bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1" bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1" bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1" bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1" bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1" line.long 0x04 "IF2ARB,IF2 Arbitation Register" bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure" bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit" bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit" hexmask.long.word 0x04 18.--28. 1. " ID ,Message Identifier" else group.long (0x120+0x04)++0x07 line.long 0x0 "IF2MASK,IF2 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering" newline bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1" bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1" bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1" bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1" bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1" bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1" bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1" bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1" bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1" bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1" bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1" bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1" bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1" bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1" bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1" bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1" bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1" bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1" bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1" bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1" bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1" bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1" bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1" bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1" bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1" bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1" bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1" bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1" bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1" line.long 0x04 "IF2ARB,IF2 Arbitation Register" bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure" bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit" bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit" hexmask.long 0x04 0.--28. 1. " ID ,Message Identifier" endif endif group.long (0x120+0x0C)++0x0B line.long 0x00 "IF2MCTRL,IF2 Message Control Register" bitfld.long 0x00 15. " NEWDAT ,New Data" "No new data,New data" bitfld.long 0x00 14. " MSGLST ,Message Lost" "Not lost,Lost" bitfld.long 0x00 13. " INTPND ,Interrupt Pending" "No interrupt,Interrupt" newline bitfld.long 0x00 12. " UMASK ,Use Acceptance Mask" "Ignored,Masked" bitfld.long 0x00 11. " TXIE ,Transmit Interrupt Enable" "Unchanged,Set" bitfld.long 0x00 10. " RXIE ,Receive Interrupt Enable" "Unchanged,Set" newline bitfld.long 0x00 9. " RMTEN ,Remote Enable" "Disabled,Enabled" bitfld.long 0x00 8. " TXRQST ,Transmit Request" "Not requested,Requested" bitfld.long 0x00 7. " EOB ,End of Block" "Single/Last,Not last" newline bitfld.long 0x00 0.--3. " DLC[3-0] ,Data Length Code" "0 byte,1 bytes,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes" line.long 0x04 "IF2DATA,IF2 Data A Register" hexmask.long.byte 0x04 24.--31. 1. " DATA[3] ,4th data byte of a CAN Data Frame" hexmask.long.byte 0x04 16.--23. 1. " [2] ,3rd data byte of a CAN Data Frame" hexmask.long.byte 0x04 8.--15. 1. " [1] ,2nd data byte of a CAN Data Frame" hexmask.long.byte 0x04 0.--7. 1. " [0] ,1st data byte of a CAN Data Frame" line.long 0x08 "IF2DATB,IF2 Data B Register" hexmask.long.byte 0x08 24.--31. 1. " DATA[7] ,8th data byte of a CAN Data Frame" hexmask.long.byte 0x08 16.--23. 1. " [6] ,7th data byte of a CAN Data Frame" hexmask.long.byte 0x08 8.--15. 1. " [5] ,6th data byte of a CAN Data Frame" hexmask.long.byte 0x08 0.--7. 1. " [4] ,5th data byte of a CAN Data Frame" group.long 0x140++0x3 "IF3" line.long 0x00 "IF3OB,IF3 Observation Register" sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS21*")||cpuis("TMS570LS31*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")) rbitfld.long 0x00 15. " IF3UPD ,IF3 Updata Data" "Not loaded,Loaded" rbitfld.long 0x00 12. " IF3SDB ,IF3 Status of Data B Read Access" "Low,High" rbitfld.long 0x00 11. " IF3SDA ,IF3 Status of Data A Read Access" "Low,High" newline rbitfld.long 0x00 10. " IF3SC ,IF3 Status of Control Bits Read Access" "Low,High" rbitfld.long 0x00 9. " IF3SA ,IF3 Status of Arbitration Data Read Access" "Low,High" rbitfld.long 0x00 8. " IF3SM ,IF3 Status of Mask Data Read Access" "Low,High" else bitfld.long 0x00 15. " IF3UPD ,IF3 Updata Data" "Not loaded,Loaded" bitfld.long 0x00 12. " IF3SDB ,IF3 Status of Data B Read Access" "Low,High" bitfld.long 0x00 11. " IF3SDA ,IF3 Status of Data A Read Access" "Low,High" newline bitfld.long 0x00 10. " IF3SC ,IF3 Status of Control Bits Read Access" "Low,High" bitfld.long 0x00 9. " IF3SA ,IF3 Status of Arbitration Data Read Access" "Low,High" bitfld.long 0x00 8. " IF3SM ,IF3 Status of Mask Data Read Access" "Low,High" endif newline bitfld.long 0x00 4. " DATA_B ,Data B Read Observation" "Not read,Read" bitfld.long 0x00 3. " DATA_A ,Data A Read Observation" "Not read,Read" bitfld.long 0x00 2. " CTRL ,Ctrl Read Observation" "Not read,Read" newline bitfld.long 0x00 1. " ARB ,Arbitration Data Read Observation" "Not read,Read" bitfld.long 0x00 0. " MASK ,Mask Data Read Observation" "Not read,Read" sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*") if (((per.l.be((ad:0xFFF7E000+0x148)))&0x40000000)==0x0) rgroup.long 0x144++0x07 line.long 0x00 "IF3MASK,IF3 Mask Register" bitfld.long 0x00 31. " MXtd ,Mask Extended Identifier" "No effect,Filtering" bitfld.long 0x00 30. " MDir ,Mask Message Direction" "No effect,Filtering" newline bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1" bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1" bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1" bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1" bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1" bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1" bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1" bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1" bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1" bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1" bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1" line.long 0x04 "IF3ARB,IF3 Arbitation Register" bitfld.long 0x04 31. " MSGVAl ,Message Valid" "Ignored,Configured" bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit" bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit" newline hexmask.long.word 0x04 18.--28. 1. " ID ,Message Identifier" else rgroup.long 0x144++0x07 line.long 0x0 "IF3MASK,IF3 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering" newline bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1" bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1" bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1" bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1" bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1" bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1" bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1" bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1" bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1" bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1" bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1" bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1" bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1" bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1" bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1" bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1" bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1" bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1" bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1" bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1" bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1" bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1" bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1" bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1" bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1" bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1" bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1" bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1" bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1" line.long 0x04 "IF3ARB,IF3 Arbitation Register" bitfld.long 0x04 31. " MSGVAl ,Message Valid" "Ignored,Configured" bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit" bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit" newline hexmask.long 0x04 0.--28. 1. " ID ,Message Identifier" endif else if (((per.l((ad:0xFFF7E000+0x148)))&0x40000000)==0x0) rgroup.long 0x144++0x07 line.long 0x0 "IF3MASK,IF3 Mask Register" bitfld.long 0x00 31. " MXtd ,Mask Extended Identifier" "No effect,Filtering" bitfld.long 0x00 30. " MDir ,Mask Message Direction" "No effect,Filtering" newline bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1" bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1" bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1" bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1" bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1" bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1" bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1" bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1" bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1" bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1" bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1" line.long 0x04 "IF3ARB,IF3 Arbitation Register" bitfld.long 0x04 31. " MSGVAl ,Message Valid" "Ignored,Configured" bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit" bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit" newline hexmask.long.word 0x04 18.--28. 1. " ID ,Message Identifier" else rgroup.long 0x144++0x07 line.long 0x0 "IF3MASK,IF3 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering" newline bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1" bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1" bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1" bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1" bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1" bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1" bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1" bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1" bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1" bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1" bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1" bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1" bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1" bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1" bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1" bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1" bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1" bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1" bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1" bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1" bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1" bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1" bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1" bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1" bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1" bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1" bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1" bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1" bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1" line.long 0x04 "IF3ARB,IF3 Arbitation Register" bitfld.long 0x04 31. " MSGVAl ,Message Valid" "Ignored,Configured" bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit" bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit" newline hexmask.long 0x04 0.--28. 1. " ID ,Message Identifier" endif endif group.long 0x14C++0x0B line.long 0x00 "IF3MCTRL,IF3 Message Control Register" bitfld.long 0x00 15. " NEWDAT ,New Data" "No new data,New data" bitfld.long 0x00 14. " MSGLST ,Message Lost" "Not lost,Lost" bitfld.long 0x00 13. " INTPND ,Interrupt Pending" "No interrupt,Interrupt" newline bitfld.long 0x00 12. " UMASK ,Use Acceptance Mask" "Ignored,Masked" bitfld.long 0x00 11. " TXIE ,Transmit Interrupt Enable" "Unchanged,Enabled" bitfld.long 0x00 10. " RXIE ,Receive Interrupt Enable" "Unchanged,Enabled" newline bitfld.long 0x00 9. " RMTEN ,Remote Enable" "Unchanged,Enabled" bitfld.long 0x00 8. " TXRQST ,Transmit Request" "Not requested,Requested" bitfld.long 0x00 7. " EOB ,End of Block" "Not last,Single/Last" newline bitfld.long 0x00 0.--3. " DLC[3-0] ,Data Length Code" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes" line.long 0x04 "IF3DATA,IF3 Data A Register" hexmask.long.byte 0x04 24.--31. 1. " DATA[3] ,4th data byte of a CAN Data Frame" hexmask.long.byte 0x04 16.--23. 1. " [2] ,3rd data byte of a CAN Data Frame" hexmask.long.byte 0x04 8.--15. 1. " [1] ,2nd data byte of a CAN Data Frame" hexmask.long.byte 0x04 0.--7. 1. " [0] ,1st data byte of a CAN Data Frame" line.long 0x08 "IF3DATB,IF3 Data B Register" hexmask.long.byte 0x08 24.--31. 1. " DATA[7] ,8th data byte of a CAN Data Frame" hexmask.long.byte 0x08 16.--23. 1. " [6] ,7th data byte of a CAN Data Frame" hexmask.long.byte 0x08 8.--15. 1. " [5] ,6th data byte of a CAN Data Frame" hexmask.long.byte 0x08 0.--7. 1. " [4] ,5th data byte of a CAN Data Frame" group.long 0x160++0x0F line.long 0x0 "IF3UENA2_1,Update Enable 2_1 Register" bitfld.long 0x00 31. " IF3UPDATEEN[32] ,IF3 Update Enabled Bit[32]" "Disabled,Enabled" bitfld.long 0x00 30. " [31] ,IF3 Update Enabled Bit[31]" "Disabled,Enabled" newline bitfld.long 0x00 29. " [30] ,IF3 Update Enabled Bit[30]" "Disabled,Enabled" bitfld.long 0x00 28. " [29] ,IF3 Update Enabled Bit[29]" "Disabled,Enabled" newline bitfld.long 0x00 27. " [28] ,IF3 Update Enabled Bit[28]" "Disabled,Enabled" bitfld.long 0x00 26. " [27] ,IF3 Update Enabled Bit[27]" "Disabled,Enabled" newline bitfld.long 0x00 25. " [26] ,IF3 Update Enabled Bit[26]" "Disabled,Enabled" bitfld.long 0x00 24. " [25] ,IF3 Update Enabled Bit[25]" "Disabled,Enabled" newline bitfld.long 0x00 23. " [24] ,IF3 Update Enabled Bit[24]" "Disabled,Enabled" bitfld.long 0x00 22. " [23] ,IF3 Update Enabled Bit[23]" "Disabled,Enabled" newline bitfld.long 0x00 21. " [22] ,IF3 Update Enabled Bit[22]" "Disabled,Enabled" bitfld.long 0x00 20. " [21] ,IF3 Update Enabled Bit[21]" "Disabled,Enabled" newline bitfld.long 0x00 19. " [20] ,IF3 Update Enabled Bit[20]" "Disabled,Enabled" bitfld.long 0x00 18. " [19] ,IF3 Update Enabled Bit[19]" "Disabled,Enabled" newline bitfld.long 0x00 17. " [18] ,IF3 Update Enabled Bit[18]" "Disabled,Enabled" bitfld.long 0x00 16. " [17] ,IF3 Update Enabled Bit[17]" "Disabled,Enabled" newline bitfld.long 0x00 15. " [16] ,IF3 Update Enabled Bit[16]" "Disabled,Enabled" bitfld.long 0x00 14. " [15] ,IF3 Update Enabled Bit[15]" "Disabled,Enabled" newline bitfld.long 0x00 13. " [14] ,IF3 Update Enabled Bit[14]" "Disabled,Enabled" bitfld.long 0x00 12. " [13] ,IF3 Update Enabled Bit[13]" "Disabled,Enabled" newline bitfld.long 0x00 11. " [12] ,IF3 Update Enabled Bit[12]" "Disabled,Enabled" bitfld.long 0x00 10. " [11] ,IF3 Update Enabled Bit[11]" "Disabled,Enabled" newline bitfld.long 0x00 9. " [10] ,IF3 Update Enabled Bit[10]" "Disabled,Enabled" bitfld.long 0x00 8. " [9] ,IF3 Update Enabled Bit[9]" "Disabled,Enabled" newline bitfld.long 0x00 7. " [8] ,IF3 Update Enabled Bit[8]" "Disabled,Enabled" bitfld.long 0x00 6. " [7] ,IF3 Update Enabled Bit[7]" "Disabled,Enabled" newline bitfld.long 0x00 5. " [6] ,IF3 Update Enabled Bit[6]" "Disabled,Enabled" bitfld.long 0x00 4. " [5] ,IF3 Update Enabled Bit[5]" "Disabled,Enabled" newline bitfld.long 0x00 3. " [4] ,IF3 Update Enabled Bit[4]" "Disabled,Enabled" bitfld.long 0x00 2. " [3] ,IF3 Update Enabled Bit[3]" "Disabled,Enabled" newline bitfld.long 0x00 1. " [2] ,IF3 Update Enabled Bit[2]" "Disabled,Enabled" bitfld.long 0x00 0. " [1] ,IF3 Update Enabled Bit[1]" "Disabled,Enabled" line.long 0x04 "IF3UENA4_3,Update Enable 4_3 Register" bitfld.long 0x04 31. " IF3UPDATEEN[64] ,IF3 Update Enabled Bit[64]" "Disabled,Enabled" bitfld.long 0x04 30. " [63] ,IF3 Update Enabled Bit[63]" "Disabled,Enabled" newline bitfld.long 0x04 29. " [62] ,IF3 Update Enabled Bit[62]" "Disabled,Enabled" bitfld.long 0x04 28. " [61] ,IF3 Update Enabled Bit[61]" "Disabled,Enabled" newline bitfld.long 0x04 27. " [60] ,IF3 Update Enabled Bit[60]" "Disabled,Enabled" bitfld.long 0x04 26. " [59] ,IF3 Update Enabled Bit[59]" "Disabled,Enabled" newline bitfld.long 0x04 25. " [58] ,IF3 Update Enabled Bit[58]" "Disabled,Enabled" bitfld.long 0x04 24. " [57] ,IF3 Update Enabled Bit[57]" "Disabled,Enabled" newline bitfld.long 0x04 23. " [56] ,IF3 Update Enabled Bit[56]" "Disabled,Enabled" bitfld.long 0x04 22. " [55] ,IF3 Update Enabled Bit[55]" "Disabled,Enabled" newline bitfld.long 0x04 21. " [54] ,IF3 Update Enabled Bit[54]" "Disabled,Enabled" bitfld.long 0x04 20. " [53] ,IF3 Update Enabled Bit[53]" "Disabled,Enabled" newline bitfld.long 0x04 19. " [52] ,IF3 Update Enabled Bit[52]" "Disabled,Enabled" bitfld.long 0x04 18. " [51] ,IF3 Update Enabled Bit[51]" "Disabled,Enabled" newline bitfld.long 0x04 17. " [50] ,IF3 Update Enabled Bit[50]" "Disabled,Enabled" bitfld.long 0x04 16. " [49] ,IF3 Update Enabled Bit[49]" "Disabled,Enabled" newline bitfld.long 0x04 15. " [48] ,IF3 Update Enabled Bit[48]" "Disabled,Enabled" bitfld.long 0x04 14. " [47] ,IF3 Update Enabled Bit[47]" "Disabled,Enabled" newline bitfld.long 0x04 13. " [46] ,IF3 Update Enabled Bit[46]" "Disabled,Enabled" bitfld.long 0x04 12. " [45] ,IF3 Update Enabled Bit[45]" "Disabled,Enabled" newline bitfld.long 0x04 11. " [44] ,IF3 Update Enabled Bit[44]" "Disabled,Enabled" bitfld.long 0x04 10. " [43] ,IF3 Update Enabled Bit[43]" "Disabled,Enabled" newline bitfld.long 0x04 9. " [42] ,IF3 Update Enabled Bit[42]" "Disabled,Enabled" bitfld.long 0x04 8. " [41] ,IF3 Update Enabled Bit[41]" "Disabled,Enabled" newline bitfld.long 0x04 7. " [40] ,IF3 Update Enabled Bit[40]" "Disabled,Enabled" bitfld.long 0x04 6. " [39] ,IF3 Update Enabled Bit[39]" "Disabled,Enabled" newline bitfld.long 0x04 5. " [38] ,IF3 Update Enabled Bit[38]" "Disabled,Enabled" bitfld.long 0x04 4. " [37] ,IF3 Update Enabled Bit[37]" "Disabled,Enabled" newline bitfld.long 0x04 3. " [36] ,IF3 Update Enabled Bit[36]" "Disabled,Enabled" bitfld.long 0x04 2. " [35] ,IF3 Update Enabled Bit[35]" "Disabled,Enabled" newline bitfld.long 0x04 1. " [34] ,IF3 Update Enabled Bit[34]" "Disabled,Enabled" bitfld.long 0x04 0. " [33] ,IF3 Update Enabled Bit[33]" "Disabled,Enabled" line.long 0x08 "IF3UENA6_5,Update Enable 6_5 Register" bitfld.long 0x08 31. " IF3UPDATEEN[96] ,IF3 Update Enabled Bit[96]" "Disabled,Enabled" bitfld.long 0x08 30. " [95] ,IF3 Update Enabled Bit[95]" "Disabled,Enabled" newline bitfld.long 0x08 29. " [94] ,IF3 Update Enabled Bit[94]" "Disabled,Enabled" bitfld.long 0x08 28. " [93] ,IF3 Update Enabled Bit[93]" "Disabled,Enabled" newline bitfld.long 0x08 27. " [92] ,IF3 Update Enabled Bit[92]" "Disabled,Enabled" bitfld.long 0x08 26. " [91] ,IF3 Update Enabled Bit[91]" "Disabled,Enabled" newline bitfld.long 0x08 25. " [90] ,IF3 Update Enabled Bit[90]" "Disabled,Enabled" bitfld.long 0x08 24. " [89] ,IF3 Update Enabled Bit[89]" "Disabled,Enabled" newline bitfld.long 0x08 23. " [88] ,IF3 Update Enabled Bit[88]" "Disabled,Enabled" bitfld.long 0x08 22. " [87] ,IF3 Update Enabled Bit[87]" "Disabled,Enabled" newline bitfld.long 0x08 21. " [86] ,IF3 Update Enabled Bit[86]" "Disabled,Enabled" bitfld.long 0x08 20. " [85] ,IF3 Update Enabled Bit[85]" "Disabled,Enabled" newline bitfld.long 0x08 19. " [84] ,IF3 Update Enabled Bit[84]" "Disabled,Enabled" bitfld.long 0x08 18. " [83] ,IF3 Update Enabled Bit[83]" "Disabled,Enabled" newline bitfld.long 0x08 17. " [82] ,IF3 Update Enabled Bit[82]" "Disabled,Enabled" bitfld.long 0x08 16. " [81] ,IF3 Update Enabled Bit[81]" "Disabled,Enabled" newline bitfld.long 0x08 15. " [80] ,IF3 Update Enabled Bit[80]" "Disabled,Enabled" bitfld.long 0x08 14. " [79] ,IF3 Update Enabled Bit[79]" "Disabled,Enabled" newline bitfld.long 0x08 13. " [78] ,IF3 Update Enabled Bit[78]" "Disabled,Enabled" bitfld.long 0x08 12. " [77] ,IF3 Update Enabled Bit[77]" "Disabled,Enabled" newline bitfld.long 0x08 11. " [76] ,IF3 Update Enabled Bit[76]" "Disabled,Enabled" bitfld.long 0x08 10. " [75] ,IF3 Update Enabled Bit[75]" "Disabled,Enabled" newline bitfld.long 0x08 9. " [74] ,IF3 Update Enabled Bit[74]" "Disabled,Enabled" bitfld.long 0x08 8. " [73] ,IF3 Update Enabled Bit[73]" "Disabled,Enabled" newline bitfld.long 0x08 7. " [72] ,IF3 Update Enabled Bit[72]" "Disabled,Enabled" bitfld.long 0x08 6. " [71] ,IF3 Update Enabled Bit[71]" "Disabled,Enabled" newline bitfld.long 0x08 5. " [70] ,IF3 Update Enabled Bit[70]" "Disabled,Enabled" bitfld.long 0x08 4. " [69] ,IF3 Update Enabled Bit[69]" "Disabled,Enabled" newline bitfld.long 0x08 3. " [68] ,IF3 Update Enabled Bit[68]" "Disabled,Enabled" bitfld.long 0x08 2. " [67] ,IF3 Update Enabled Bit[67]" "Disabled,Enabled" newline bitfld.long 0x08 1. " [66] ,IF3 Update Enabled Bit[66]" "Disabled,Enabled" bitfld.long 0x08 0. " [65] ,IF3 Update Enabled Bit[65]" "Disabled,Enabled" line.long 0x0C "IF3UENA8_7,Update Enable 8_7 Register" bitfld.long 0x0C 31. " IF3UPDATEEN[128] ,IF3 Update Enabled Bit[128]" "Disabled,Enabled" bitfld.long 0x0C 30. " [127] ,IF3 Update Enabled Bit[127]" "Disabled,Enabled" newline bitfld.long 0x0C 29. " [126] ,IF3 Update Enabled Bit[126]" "Disabled,Enabled" bitfld.long 0x0C 28. " [125] ,IF3 Update Enabled Bit[125]" "Disabled,Enabled" newline bitfld.long 0x0C 27. " [124] ,IF3 Update Enabled Bit[124]" "Disabled,Enabled" bitfld.long 0x0C 26. " [123] ,IF3 Update Enabled Bit[123]" "Disabled,Enabled" newline bitfld.long 0x0C 25. " [122] ,IF3 Update Enabled Bit[122]" "Disabled,Enabled" bitfld.long 0x0C 24. " [121] ,IF3 Update Enabled Bit[121]" "Disabled,Enabled" newline bitfld.long 0x0C 23. " [120] ,IF3 Update Enabled Bit[120]" "Disabled,Enabled" bitfld.long 0x0C 22. " [119] ,IF3 Update Enabled Bit[119]" "Disabled,Enabled" newline bitfld.long 0x0C 21. " [118] ,IF3 Update Enabled Bit[118]" "Disabled,Enabled" bitfld.long 0x0C 20. " [117] ,IF3 Update Enabled Bit[117]" "Disabled,Enabled" newline bitfld.long 0x0C 19. " [116] ,IF3 Update Enabled Bit[116]" "Disabled,Enabled" bitfld.long 0x0C 18. " [115] ,IF3 Update Enabled Bit[115]" "Disabled,Enabled" newline bitfld.long 0x0C 17. " [114] ,IF3 Update Enabled Bit[114]" "Disabled,Enabled" bitfld.long 0x0C 16. " [113] ,IF3 Update Enabled Bit[113]" "Disabled,Enabled" newline bitfld.long 0x0C 15. " [112] ,IF3 Update Enabled Bit[112]" "Disabled,Enabled" bitfld.long 0x0C 14. " [111] ,IF3 Update Enabled Bit[111]" "Disabled,Enabled" newline bitfld.long 0x0C 13. " [110] ,IF3 Update Enabled Bit[110]" "Disabled,Enabled" bitfld.long 0x0C 12. " [109] ,IF3 Update Enabled Bit[109]" "Disabled,Enabled" newline bitfld.long 0x0C 11. " [108] ,IF3 Update Enabled Bit[108]" "Disabled,Enabled" bitfld.long 0x0C 10. " [107] ,IF3 Update Enabled Bit[107]" "Disabled,Enabled" newline bitfld.long 0x0C 9. " [106] ,IF3 Update Enabled Bit[106]" "Disabled,Enabled" bitfld.long 0x0C 8. " [105] ,IF3 Update Enabled Bit[105]" "Disabled,Enabled" newline bitfld.long 0x0C 7. " [104] ,IF3 Update Enabled Bit[104]" "Disabled,Enabled" bitfld.long 0x0C 6. " [103] ,IF3 Update Enabled Bit[103]" "Disabled,Enabled" newline bitfld.long 0x0C 5. " [102] ,IF3 Update Enabled Bit[102]" "Disabled,Enabled" bitfld.long 0x0C 4. " [101] ,IF3 Update Enabled Bit[101]" "Disabled,Enabled" newline bitfld.long 0x0C 3. " [100] ,IF3 Update Enabled Bit[100]" "Disabled,Enabled" bitfld.long 0x0C 2. " [99] ,IF3 Update Enabled Bit[99]" "Disabled,Enabled" newline bitfld.long 0x0C 1. " [98] ,IF3 Update Enabled Bit[98]" "Disabled,Enabled" bitfld.long 0x0C 0. " [97] ,IF3 Update Enabled Bit[97]" "Disabled,Enabled" newline group.long 0x1E0++0x03 line.long 0x0 "IOCTRLTX,TX IO Control Register" sif (cpu()!="TMS470MF031"&&cpu()!="TMS470MF042"&&cpu()!="TMS470MF066"&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!=("TMS570LC4357")&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*")&&!cpuis("TMS570LS0232")&&!cpuis("TMS570LS0714*")&&!cpuis("TMS570LS0914*")) bitfld.long 0x00 19. " SR ,Slew Rate Selection of Output Driver" "Normal,Slow" newline endif bitfld.long 0x00 18. " PU ,Selection of Pull Direction" "Pull down,Pull up" bitfld.long 0x00 17. " PD ,Pull Functionality Disable" "No,Yes" bitfld.long 0x00 16. " OD ,Open Drain Mode" "Push pull,Open Drain" bitfld.long 0x00 3. " FUNC ,Functionality of Pin" "General,CAN" newline bitfld.long 0x00 2. " DIR ,Direction of Pin" "Input,Output" bitfld.long 0x00 1. " OUT ,Value to Drive to Pin if Configured for I/O" "Low,High" bitfld.long 0x00 0. " IN ,Value of Pin" "Low,High" group.long 0x1E4++0x03 line.long 0x0 "IOCTRLRX,RX IO Control Register" sif (cpu()!="TMS470MF031"&&cpu()!="TMS470MF042"&&cpu()!="TMS470MF066"&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!=("TMS570LC4357")&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*")&&!cpuis("TMS570LS0232")&&!cpuis("TMS570LS0714*")&&!cpuis("TMS570LS0914*")) bitfld.long 0x00 19. " SR ,Slew Rate Selection of Output Driver" "Normal,Slow" newline endif bitfld.long 0x00 18. " PU ,Selection of Pull Direction" "Pull down,Pull up" bitfld.long 0x00 17. " PD ,Pull Functionality Disable" "No,Yes" bitfld.long 0x00 16. " OD ,Open Drain Mode" "Push pull,Open Drain" bitfld.long 0x00 3. " FUNC ,Functionality of Pin" "General,CAN" newline bitfld.long 0x00 2. " DIR ,Direction of Pin" "Input,Output" bitfld.long 0x00 1. " OUT ,Value to Drive to Pin if Configured for I/O" "Low,High" bitfld.long 0x00 0. " IN ,Value of Pin" "Low,High" sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*") endian.le endif width 0x0B tree.end tree.end tree "Flexray" base ad:0xFFF7C800 width 8. group.long 0x10++0x3 line.long 0x0 "TEST1,Test register 1" group.long 0x14++0x3 line.long 0x0 "TEST2,Test register 2" group.long 0x1C++0x3 line.long 0x0 "LCK,Lock register" group.long 0x20++0x3 line.long 0x0 "EIR,Error interrupt register" group.long 0x24++0x3 line.long 0x0 "SIR,Status interrupt register" group.long 0x28++0x3 line.long 0x0 "EILS,Error interrupt line select" group.long 0x2C++0x3 line.long 0x0 "SILS,Status interrupt line select" group.long 0x30++0x3 line.long 0x0 "EIES,Error interrupt enable set" group.long 0x34++0x3 line.long 0x0 "EIER,Error interrupt enable reset" group.long 0x38++0x3 line.long 0x0 "SIES,Status interrupt enable set" group.long 0x3C++0x3 line.long 0x0 "SIER,Status interrupt enable reset" group.long 0x40++0x3 line.long 0x0 "ILE,Interrupt line enable" group.long 0x44++0x3 line.long 0x0 "T0C,Timer 0 configuration" group.long 0x48++0x3 line.long 0x0 "T1C,Timer 1 configuration" group.long 0x4C++0x3 line.long 0x0 "STPW1,Stop watch register1" group.long 0x50++0x3 line.long 0x0 "STPW2,Stop watch register2" group.long 0x80++0x3 line.long 0x0 "SUCC1,SUC configuration register 1" group.long 0x84++0x3 line.long 0x0 "SUCC2,SUC configuration register 2" group.long 0x88++0x3 line.long 0x0 "SUCC3,SUC configuration register 3" group.long 0x8C++0x3 line.long 0x0 "NEMC,NEM configuration register" group.long 0x90++0x3 line.long 0x0 "PRTC1,PRT configuration register 1" group.long 0x94++0x3 line.long 0x0 "PRTC2,PRT configuration register 2" group.long 0x98++0x3 line.long 0x0 "MHDC,MHD configuration register" group.long 0xA0++0x3 line.long 0x0 "GTUC1,GTU configuration register 1" group.long 0xA4++0x3 line.long 0x0 "GTUC2,GTU configuration register 2" group.long 0xA8++0x3 line.long 0x0 "GTUC3,GTU configuration register 3" group.long 0xAC++0x3 line.long 0x0 "GTUC4,GTU configuration register 4" group.long 0xB0++0x3 line.long 0x0 "GTUC5,GTU configuration register 5" group.long 0xB4++0x3 line.long 0x0 "GTUC6,GTU configuration register 6" group.long 0xB8++0x3 line.long 0x0 "GTUC7,GTU configuration register 7" group.long 0xBC++0x3 line.long 0x0 "GTUC8,GTU configuration register 8" group.long 0xC0++0x3 line.long 0x0 "GTUC9,GTU configuration register 9" group.long 0xC4++0x3 line.long 0x0 "GTUC10,GTU configuration register 10" group.long 0xC8++0x3 line.long 0x0 "GTUC11,GTU configuration register 11" group.long 0x100++0x3 line.long 0x0 "CCSV,communication controller status vector" group.long 0x104++0x3 line.long 0x0 "CCEV,communication controller error vector" group.long 0x110++0x3 line.long 0x0 "SCV,Slot counter value" group.long 0x114++0x3 line.long 0x0 "MTCCV,Macrotick and cycle counter" group.long 0x118++0x3 line.long 0x0 "RCV,Rate correction value" group.long 0x11C++0x3 line.long 0x0 "OCV,Offset correction value" group.long 0x120++0x3 line.long 0x0 "SFS,Sync frame status" group.long 0x124++0x3 line.long 0x0 "SWNIT,Symbol window and NIT status" group.long 0x128++0x3 line.long 0x0 "ACS,Aggregated channel status" group.long 0x130++0x3 line.long 0x0 "ESIDn,Even sync ID [1-15]" group.long 0x134++0x3 line.long 0x0 "ESIDn,Even sync ID [1-15]" group.long 0x138++0x3 line.long 0x0 "ESIDn,Even sync ID [1-15]" group.long 0x13C++0x3 line.long 0x0 "ESIDn,Even sync ID [1-15]" group.long 0x140++0x3 line.long 0x0 "ESIDn,Even sync ID [1-15]" group.long 0x144++0x3 line.long 0x0 "ESIDn,Even sync ID [1-15]" group.long 0x148++0x3 line.long 0x0 "ESIDn,Even sync ID [1-15]" group.long 0x14C++0x3 line.long 0x0 "ESIDn,Even sync ID [1-15]" group.long 0x150++0x3 line.long 0x0 "ESIDn,Even sync ID [1-15]" group.long 0x154++0x3 line.long 0x0 "ESIDn,Even sync ID [1-15]" group.long 0x158++0x3 line.long 0x0 "ESIDn,Even sync ID [1-15]" group.long 0x15C++0x3 line.long 0x0 "ESIDn,Even sync ID [1-15]" group.long 0x160++0x3 line.long 0x0 "ESIDn,Even sync ID [1-15]" group.long 0x164++0x3 line.long 0x0 "ESIDn,Even sync ID [1-15]" group.long 0x168++0x3 line.long 0x0 "ESIDn,Even sync ID [1-15]" group.long 0x170++0x3 line.long 0x0 "OSIDn,Odd sync ID [1-15]" group.long 0x174++0x3 line.long 0x0 "OSIDn,Odd sync ID [1-15]" group.long 0x178++0x3 line.long 0x0 "OSIDn,Odd sync ID [1-15]" group.long 0x17C++0x3 line.long 0x0 "OSIDn,Odd sync ID [1-15]" group.long 0x180++0x3 line.long 0x0 "OSIDn,Odd sync ID [1-15]" group.long 0x184++0x3 line.long 0x0 "OSIDn,Odd sync ID [1-15]" group.long 0x188++0x3 line.long 0x0 "OSIDn,Odd sync ID [1-15]" group.long 0x18C++0x3 line.long 0x0 "OSIDn,Odd sync ID [1-15]" group.long 0x190++0x3 line.long 0x0 "OSIDn,Odd sync ID [1-15]" group.long 0x194++0x3 line.long 0x0 "OSIDn,Odd sync ID [1-15]" group.long 0x198++0x3 line.long 0x0 "OSIDn,Odd sync ID [1-15]" group.long 0x19C++0x3 line.long 0x0 "OSIDn,Odd sync ID [1-15]" group.long 0x1A0++0x3 line.long 0x0 "OSIDn,Odd sync ID [1-15]" group.long 0x1A4++0x3 line.long 0x0 "OSIDn,Odd sync ID [1-15]" group.long 0x1A8++0x3 line.long 0x0 "OSIDn,Odd sync ID [1-15]" group.long 0x1B0++0x3 line.long 0x0 "NMVn,Network management vector [1-3]" group.long 0x1B4++0x3 line.long 0x0 "NMVn,Network management vector [1-3]" group.long 0x1B8++0x3 line.long 0x0 "NMVn,Network management vector [1-3]" group.long 0x300++0x3 line.long 0x0 "MRC,Message RAM configuration" group.long 0x304++0x3 line.long 0x0 "FRF,FIFO rejection filter" group.long 0x308++0x3 line.long 0x0 "FRFM,FIFO rejection filter mask" group.long 0x30C++0x3 line.long 0x0 "FCIM,FIFO Critical Level" group.long 0x310++0x3 line.long 0x0 "MHDS,Message handler status" group.long 0x314++0x3 line.long 0x0 "LDTS,Last dynamic transmit slot" group.long 0x318++0x3 line.long 0x0 "FSR,FIFO status register" group.long 0x31C++0x3 line.long 0x0 "MHDF,Message handler constraint flags" group.long 0x320++0x3 line.long 0x0 "TXRQ1,Transmission request 1" group.long 0x324++0x3 line.long 0x0 "TXRQ2,Transmission request 2" group.long 0x328++0x3 line.long 0x0 "TXRQ3,Transmission request 3" group.long 0x32C++0x3 line.long 0x0 "TXRQ4,Transmission request 4" group.long 0x330++0x3 line.long 0x0 "NDAT1,New data 1" group.long 0x334++0x3 line.long 0x0 "NDAT2,New data 2" group.long 0x338++0x3 line.long 0x0 "NDAT3,New data 3" group.long 0x33C++0x3 line.long 0x0 "NDAT4,New data 4" group.long 0x340++0x3 line.long 0x0 "MBSC1,Message buffer status changed 1" group.long 0x344++0x3 line.long 0x0 "MBSC2,Message buffer status changed 2" group.long 0x348++0x3 line.long 0x0 "MBSC3,Message buffer status changed 3" group.long 0x34C++0x3 line.long 0x0 "MBSC4,Message buffer status changed 4" group.long 0x3E0++0x3 line.long 0x0 "CREL,Core release register" group.long 0x3E4++0x3 line.long 0x0 "ENDN,Endian register" group.long 0x400++0x3 line.long 0x0 "WRDSn,Write data section [1-64]" group.long 0x404++0x3 line.long 0x0 "WRDSn,Write data section [1-64]" group.long 0x408++0x3 line.long 0x0 "WRDSn,Write data section [1-64]" group.long 0x40C++0x3 line.long 0x0 "WRDSn,Write data section [1-64]" group.long 0x410++0x3 line.long 0x0 "WRDSn,Write data section [1-64]" group.long 0x414++0x3 line.long 0x0 "WRDSn,Write data section [1-64]" group.long 0x418++0x3 line.long 0x0 "WRDSn,Write data section [1-64]" group.long 0x41C++0x3 line.long 0x0 "WRDSn,Write data section [1-64]" group.long 0x420++0x3 line.long 0x0 "WRDSn,Write data section [1-64]" group.long 0x424++0x3 line.long 0x0 "WRDSn,Write data section [1-64]" group.long 0x428++0x3 line.long 0x0 "WRDSn,Write data section [1-64]" group.long 0x42C++0x3 line.long 0x0 "WRDSn,Write data section [1-64]" group.long 0x430++0x3 line.long 0x0 "WRDSn,Write data section [1-64]" group.long 0x434++0x3 line.long 0x0 "WRDSn,Write data section [1-64]" group.long 0x438++0x3 line.long 0x0 "WRDSn,Write data section [1-64]" group.long 0x43C++0x3 line.long 0x0 "WRDSn,Write data section [1-64]" group.long 0x440++0x3 line.long 0x0 "WRDSn,Write data section [1-64]" group.long 0x444++0x3 line.long 0x0 "WRDSn,Write data section [1-64]" group.long 0x448++0x3 line.long 0x0 "WRDSn,Write data section [1-64]" group.long 0x44C++0x3 line.long 0x0 "WRDSn,Write data section [1-64]" group.long 0x450++0x3 line.long 0x0 "WRDSn,Write data section [1-64]" group.long 0x454++0x3 line.long 0x0 "WRDSn,Write data section [1-64]" group.long 0x458++0x3 line.long 0x0 "WRDSn,Write data section [1-64]" group.long 0x45C++0x3 line.long 0x0 "WRDSn,Write data section [1-64]" group.long 0x460++0x3 line.long 0x0 "WRDSn,Write data section [1-64]" group.long 0x464++0x3 line.long 0x0 "WRDSn,Write data section [1-64]" group.long 0x468++0x3 line.long 0x0 "WRDSn,Write data section [1-64]" group.long 0x46C++0x3 line.long 0x0 "WRDSn,Write data section [1-64]" group.long 0x470++0x3 line.long 0x0 "WRDSn,Write data section [1-64]" group.long 0x474++0x3 line.long 0x0 "WRDSn,Write data section [1-64]" group.long 0x478++0x3 line.long 0x0 "WRDSn,Write data section [1-64]" group.long 0x47C++0x3 line.long 0x0 "WRDSn,Write data section [1-64]" group.long 0x480++0x3 line.long 0x0 "WRDSn,Write data section [1-64]" group.long 0x484++0x3 line.long 0x0 "WRDSn,Write data section [1-64]" group.long 0x488++0x3 line.long 0x0 "WRDSn,Write data section [1-64]" group.long 0x48C++0x3 line.long 0x0 "WRDSn,Write data section [1-64]" group.long 0x490++0x3 line.long 0x0 "WRDSn,Write data section [1-64]" group.long 0x494++0x3 line.long 0x0 "WRDSn,Write data section [1-64]" group.long 0x498++0x3 line.long 0x0 "WRDSn,Write data section [1-64]" group.long 0x49C++0x3 line.long 0x0 "WRDSn,Write data section [1-64]" group.long 0x4A0++0x3 line.long 0x0 "WRDSn,Write data section [1-64]" group.long 0x4A4++0x3 line.long 0x0 "WRDSn,Write data section [1-64]" group.long 0x4A8++0x3 line.long 0x0 "WRDSn,Write data section [1-64]" group.long 0x4AC++0x3 line.long 0x0 "WRDSn,Write data section [1-64]" group.long 0x4B0++0x3 line.long 0x0 "WRDSn,Write data section [1-64]" group.long 0x4B4++0x3 line.long 0x0 "WRDSn,Write data section [1-64]" group.long 0x4B8++0x3 line.long 0x0 "WRDSn,Write data section [1-64]" group.long 0x4BC++0x3 line.long 0x0 "WRDSn,Write data section [1-64]" group.long 0x4C0++0x3 line.long 0x0 "WRDSn,Write data section [1-64]" group.long 0x4C4++0x3 line.long 0x0 "WRDSn,Write data section [1-64]" group.long 0x4C8++0x3 line.long 0x0 "WRDSn,Write data section [1-64]" group.long 0x4CC++0x3 line.long 0x0 "WRDSn,Write data section [1-64]" group.long 0x4D0++0x3 line.long 0x0 "WRDSn,Write data section [1-64]" group.long 0x4D4++0x3 line.long 0x0 "WRDSn,Write data section [1-64]" group.long 0x4D8++0x3 line.long 0x0 "WRDSn,Write data section [1-64]" group.long 0x4DC++0x3 line.long 0x0 "WRDSn,Write data section [1-64]" group.long 0x4E0++0x3 line.long 0x0 "WRDSn,Write data section [1-64]" group.long 0x4E4++0x3 line.long 0x0 "WRDSn,Write data section [1-64]" group.long 0x4E8++0x3 line.long 0x0 "WRDSn,Write data section [1-64]" group.long 0x4EC++0x3 line.long 0x0 "WRDSn,Write data section [1-64]" group.long 0x4F0++0x3 line.long 0x0 "WRDSn,Write data section [1-64]" group.long 0x4F4++0x3 line.long 0x0 "WRDSn,Write data section [1-64]" group.long 0x4F8++0x3 line.long 0x0 "WRDSn,Write data section [1-64]" group.long 0x4FC++0x3 line.long 0x0 "WRDSn,Write data section [1-64]" group.long 0x500++0x3 line.long 0x0 "WRHS1,Write header section 1" group.long 0x504++0x3 line.long 0x0 "WRHS2,Write header section 2" group.long 0x508++0x3 line.long 0x0 "WRHS3,Write header section 3" group.long 0x510++0x3 line.long 0x0 "IBCM,Input buffer command mask" group.long 0x514++0x3 line.long 0x0 "IBCR,Input buffer command request" group.long 0x600++0x3 line.long 0x0 "RDDSn,Read data section [1-64]" group.long 0x604++0x3 line.long 0x0 "RDDSn,Read data section [1-64]" group.long 0x608++0x3 line.long 0x0 "RDDSn,Read data section [1-64]" group.long 0x60C++0x3 line.long 0x0 "RDDSn,Read data section [1-64]" group.long 0x610++0x3 line.long 0x0 "RDDSn,Read data section [1-64]" group.long 0x614++0x3 line.long 0x0 "RDDSn,Read data section [1-64]" group.long 0x618++0x3 line.long 0x0 "RDDSn,Read data section [1-64]" group.long 0x61C++0x3 line.long 0x0 "RDDSn,Read data section [1-64]" group.long 0x620++0x3 line.long 0x0 "RDDSn,Read data section [1-64]" group.long 0x624++0x3 line.long 0x0 "RDDSn,Read data section [1-64]" group.long 0x628++0x3 line.long 0x0 "RDDSn,Read data section [1-64]" group.long 0x62C++0x3 line.long 0x0 "RDDSn,Read data section [1-64]" group.long 0x630++0x3 line.long 0x0 "RDDSn,Read data section [1-64]" group.long 0x634++0x3 line.long 0x0 "RDDSn,Read data section [1-64]" group.long 0x638++0x3 line.long 0x0 "RDDSn,Read data section [1-64]" group.long 0x63C++0x3 line.long 0x0 "RDDSn,Read data section [1-64]" group.long 0x640++0x3 line.long 0x0 "RDDSn,Read data section [1-64]" group.long 0x644++0x3 line.long 0x0 "RDDSn,Read data section [1-64]" group.long 0x648++0x3 line.long 0x0 "RDDSn,Read data section [1-64]" group.long 0x64C++0x3 line.long 0x0 "RDDSn,Read data section [1-64]" group.long 0x650++0x3 line.long 0x0 "RDDSn,Read data section [1-64]" group.long 0x654++0x3 line.long 0x0 "RDDSn,Read data section [1-64]" group.long 0x658++0x3 line.long 0x0 "RDDSn,Read data section [1-64]" group.long 0x65C++0x3 line.long 0x0 "RDDSn,Read data section [1-64]" group.long 0x660++0x3 line.long 0x0 "RDDSn,Read data section [1-64]" group.long 0x664++0x3 line.long 0x0 "RDDSn,Read data section [1-64]" group.long 0x668++0x3 line.long 0x0 "RDDSn,Read data section [1-64]" group.long 0x66C++0x3 line.long 0x0 "RDDSn,Read data section [1-64]" group.long 0x670++0x3 line.long 0x0 "RDDSn,Read data section [1-64]" group.long 0x674++0x3 line.long 0x0 "RDDSn,Read data section [1-64]" group.long 0x678++0x3 line.long 0x0 "RDDSn,Read data section [1-64]" group.long 0x67C++0x3 line.long 0x0 "RDDSn,Read data section [1-64]" group.long 0x680++0x3 line.long 0x0 "RDDSn,Read data section [1-64]" group.long 0x684++0x3 line.long 0x0 "RDDSn,Read data section [1-64]" group.long 0x688++0x3 line.long 0x0 "RDDSn,Read data section [1-64]" group.long 0x68C++0x3 line.long 0x0 "RDDSn,Read data section [1-64]" group.long 0x690++0x3 line.long 0x0 "RDDSn,Read data section [1-64]" group.long 0x694++0x3 line.long 0x0 "RDDSn,Read data section [1-64]" group.long 0x698++0x3 line.long 0x0 "RDDSn,Read data section [1-64]" group.long 0x69C++0x3 line.long 0x0 "RDDSn,Read data section [1-64]" group.long 0x6A0++0x3 line.long 0x0 "RDDSn,Read data section [1-64]" group.long 0x6A4++0x3 line.long 0x0 "RDDSn,Read data section [1-64]" group.long 0x6A8++0x3 line.long 0x0 "RDDSn,Read data section [1-64]" group.long 0x6AC++0x3 line.long 0x0 "RDDSn,Read data section [1-64]" group.long 0x6B0++0x3 line.long 0x0 "RDDSn,Read data section [1-64]" group.long 0x6B4++0x3 line.long 0x0 "RDDSn,Read data section [1-64]" group.long 0x6B8++0x3 line.long 0x0 "RDDSn,Read data section [1-64]" group.long 0x6BC++0x3 line.long 0x0 "RDDSn,Read data section [1-64]" group.long 0x6C0++0x3 line.long 0x0 "RDDSn,Read data section [1-64]" group.long 0x6C4++0x3 line.long 0x0 "RDDSn,Read data section [1-64]" group.long 0x6C8++0x3 line.long 0x0 "RDDSn,Read data section [1-64]" group.long 0x6CC++0x3 line.long 0x0 "RDDSn,Read data section [1-64]" group.long 0x6D0++0x3 line.long 0x0 "RDDSn,Read data section [1-64]" group.long 0x6D4++0x3 line.long 0x0 "RDDSn,Read data section [1-64]" group.long 0x6D8++0x3 line.long 0x0 "RDDSn,Read data section [1-64]" group.long 0x6DC++0x3 line.long 0x0 "RDDSn,Read data section [1-64]" group.long 0x6E0++0x3 line.long 0x0 "RDDSn,Read data section [1-64]" group.long 0x6E4++0x3 line.long 0x0 "RDDSn,Read data section [1-64]" group.long 0x6E8++0x3 line.long 0x0 "RDDSn,Read data section [1-64]" group.long 0x6EC++0x3 line.long 0x0 "RDDSn,Read data section [1-64]" group.long 0x6F0++0x3 line.long 0x0 "RDDSn,Read data section [1-64]" group.long 0x6F4++0x3 line.long 0x0 "RDDSn,Read data section [1-64]" group.long 0x6F8++0x3 line.long 0x0 "RDDSn,Read data section [1-64]" group.long 0x6FC++0x3 line.long 0x0 "RDDSn,Read data section [1-64]" group.long 0x700++0x3 line.long 0x0 "RDHS1,Read header section 1" group.long 0x704++0x3 line.long 0x0 "RDHS2,Read header section 2" group.long 0x708++0x3 line.long 0x0 "RDHS3,Read header section 3" group.long 0x70C++0x3 line.long 0x0 "MBS,Message buffer status" group.long 0x710++0x3 line.long 0x0 "OBCM,Output buffer command mask" group.long 0x714++0x3 line.long 0x0 "OBCR,Output buffer command request" width 0xb tree.end tree "FlexrayTU" base ad:0xFFF7A000 width 9. group.long 0x00++0x3 line.long 0x0 "PICC,Product Identification Communication Controller" group.long 0x04++0x3 line.long 0x0 "GSN,Global Static Number" group.long 0x10++0x3 line.long 0x0 "GCS,Global Control Set" group.long 0x14++0x3 line.long 0x0 "GCR,Global Control Reset" group.long 0x18++0x3 line.long 0x0 "TSCB,Transfer Status" group.long 0x1C++0x3 line.long 0x0 "LTBCC,Last Transferred Buffer to Communication Controller" group.long 0x20++0x3 line.long 0x0 "LTBSM,Last Transferred Buffer to System Memory" group.long 0x24++0x3 line.long 0x0 "TBA,Transfer Base Address" group.long 0x28++0x3 line.long 0x0 "NTBA,Next Transfer Base Address" group.long 0x2C++0x3 line.long 0x0 "BAMS,Base Address of Mirrored Status" group.long 0x30++0x3 line.long 0x0 "SAMP,Start Address of Memory Protection" group.long 0x34++0x3 line.long 0x0 "EAMP,End Address of Memory Protection" group.long 0x40++0x3 line.long 0x0 "TSMO1,Transfer to System Memory Occurred 1" group.long 0x44++0x3 line.long 0x0 "TSMO2,Transfer to System Memory Occurred 2" group.long 0x48++0x3 line.long 0x0 "TSMO3,Transfer to System Memory Occurred 3" group.long 0x4C++0x3 line.long 0x0 "TSMO4,Transfer to System Memory Occurred 4" group.long 0x50++0x3 line.long 0x0 "TCCO1,Transfer to Communication Controller Occurred 1" group.long 0x54++0x3 line.long 0x0 "TCCO2,Transfer to Communication Controller Occurred 2" group.long 0x58++0x3 line.long 0x0 "TCCO3,Transfer to Communication Controller Occurred 3" group.long 0x5C++0x3 line.long 0x0 "TCCO4,Transfer to Communication Controller Occurred 4" group.long 0x60++0x3 line.long 0x0 "TOOFF,Transfer Occurred Offset" group.long 0x70++0x3 line.long 0x0 "PEADR,Parity Error Address" group.long 0x74++0x3 line.long 0x0 "TEIR,Transfer Error InterRupt" group.long 0x78++0x3 line.long 0x0 "TEIRES,Transfer Error InterRupt Enable Set" group.long 0x7C++0x3 line.long 0x0 "TEIRER,Transfer Error InterRupt Enable Reset" group.long 0x80++0x3 line.long 0x0 "TTSMS1,Trigger Transfer to System Memory Set 1" group.long 0x84++0x3 line.long 0x0 "TTSMR1,Trigger Transfer to System Memory Reset 1" group.long 0x88++0x3 line.long 0x0 "TTSMS2,Trigger Transfer to System Memory Set 2" group.long 0x8C++0x3 line.long 0x0 "TTSMR2,Trigger Transfer to System Memory Reset 2" group.long 0x90++0x3 line.long 0x0 "TTSMS3,Trigger Transfer to System Memory Set 3" group.long 0x94++0x3 line.long 0x0 "TTSMR3,Trigger Transfer to System Memory Reset 3" group.long 0x98++0x3 line.long 0x0 "TTSMS4,Trigger Transfer to System Memory Set 4" group.long 0x9C++0x3 line.long 0x0 "TTSMR4,Trigger Transfer to System Memory Reset 4" group.long 0xA0++0x3 line.long 0x0 "TTCCS1,Trigger Transfer to Communication Controller Set 1" group.long 0xA4++0x3 line.long 0x0 "TTCCR1,Trigger Transfer to Communication Controller Reset 1" group.long 0xA8++0x3 line.long 0x0 "TTCCS2,Trigger Transfer to Communication Controller Set 2" group.long 0xAC++0x3 line.long 0x0 "TTCCR2,Trigger Transfer to Communication Controller Reset 2" group.long 0xB0++0x3 line.long 0x0 "TTCCS3,Trigger Transfer to Communication Controller Set 3" group.long 0xB4++0x3 line.long 0x0 "TTCCR3,Trigger Transfer to Communication Controller Reset 3" group.long 0xB8++0x3 line.long 0x0 "TTCCS4,Trigger Transfer to Communication Controller Set 4" group.long 0xBC++0x3 line.long 0x0 "TTCCR4,Trigger Transfer to Communication Controller Reset 4" group.long 0xC0++0x3 line.long 0x0 "ETESMS1,Enable Transfer on Event to System Memory Set 1" group.long 0xC4++0x3 line.long 0x0 "ETESMR1,Enable Transfer on Event to System Memory Reset 1" group.long 0xC8++0x3 line.long 0x0 "ETESMS2,Enable Transfer on Event to System Memory Set 2" group.long 0xCC++0x3 line.long 0x0 "ETESMR2,Enable Transfer on Event to System Memory Reset 2" group.long 0xD0++0x3 line.long 0x0 "ETESMS3,Enable Transfer on Event to System Memory Set 3" group.long 0xD4++0x3 line.long 0x0 "ETESMR3,Enable Transfer on Event to System Memory Reset 3" group.long 0xD8++0x3 line.long 0x0 "ETESMS4,Enable Transfer on Event to System Memory Set 4" group.long 0xDC++0x3 line.long 0x0 "ETESMR4,Enable Transfer on Event to System Memory Reset 4" group.long 0xE0++0x3 line.long 0x0 "CESMS1,Clear on Event to System Memory Set 1" group.long 0xE4++0x3 line.long 0x0 "CESMR1,Clear on Event to System Memory Reset 1" group.long 0xE8++0x3 line.long 0x0 "CESMS2,Clear on Event to System Memory Set 2" group.long 0xEC++0x3 line.long 0x0 "CESMR2,Clear on Event to System Memory Reset 2" group.long 0xF0++0x3 line.long 0x0 "CESMS3,Clear on Event to System Memory Set 3" group.long 0xF4++0x3 line.long 0x0 "CESMR3,Clear on Event to System Memory Reset 3" group.long 0xF8++0x3 line.long 0x0 "CESMS4,Clear on Event to System Memory Set 4" group.long 0xFC++0x3 line.long 0x0 "CESMR4,Clear on Event to System Memory Reset 4" group.long 0x100++0x3 line.long 0x0 "TSMIES1,Transfer to System Memory Interrupt Enable Set 1" group.long 0x104++0x3 line.long 0x0 "TSMIER1,Transfer to System Memory Interrupt Enable Reset 1" group.long 0x108++0x3 line.long 0x0 "TSMIES2,Transfer to System Memory Interrupt Enable Set 2" group.long 0x10C++0x3 line.long 0x0 "TSMIER2,Transfer to System Memory Interrupt Enable Reset 2" group.long 0x110++0x3 line.long 0x0 "TSMIES3,Transfer to System Memory Interrupt Enable Set 3" group.long 0x114++0x3 line.long 0x0 "TSMIER3,Transfer to System Memory Interrupt Enable Reset 3" group.long 0x118++0x3 line.long 0x0 "TSMIES4,Transfer to System Memory Interrupt Enable Set 4" group.long 0x11C++0x3 line.long 0x0 "TSMIER4,Transfer to System Memory Interrupt Enable Reset 4" group.long 0x120++0x3 line.long 0x0 "TCCIES1,Transfer to Communication Controller Interrupt Enable Set 1" group.long 0x124++0x3 line.long 0x0 "TCCIER1,Transfer to Communication Controller Interrupt Enable Reset 1" group.long 0x128++0x3 line.long 0x0 "TCCIES2,Transfer to Communication Controller Interrupt Enable Set 2" group.long 0x12C++0x3 line.long 0x0 "TCCIER2,Transfer to Communication Controller Interrupt Enable Reset 2" group.long 0x130++0x3 line.long 0x0 "TCCIES3,Transfer to Communication Controller Interrupt Enable Set 3" group.long 0x134++0x3 line.long 0x0 "TCCIER3,Transfer to Communication Controller Interrupt Enable Reset 3" group.long 0x138++0x3 line.long 0x0 "TCCIES4,Transfer to Communication Controller Interrupt Enable Set 4" group.long 0x13C++0x3 line.long 0x0 "TCCIER4,Transfer to Communication Controller Interrupt Enable Reset 4" width 0xb tree.end tree.open "GPIO (General-Purpose Input/Output)" tree "GIO" base ad:0xFFF7BC00 width 6. sif (cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10206-PGE")||cpu()=="RM48L530-PGE"||cpu()=="RM48L530-ZWT"||cpu()=="RM48L540-PGE"||cpu()=="RM48L540-ZWT"||cpu()=="RM48L550-PGE"||cpu()=="RM48L550-ZWT"||cpu()=="RM48L730-PGE"||cpu()=="RM48L730-ZWT"||cpu()=="RM48L740-PGE"||cpu()=="RM48L740-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L930-PGE"||cpu()=="RM48L930-ZWT"||cpu()=="RM48L940-PGE"||cpu()=="RM48L940-ZWT"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L952-PGE"||cpu()=="RM48L952-ZWT"||cpu()=="RM42L432"||cpu()=="RM46L430-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L440-PGE"||cpu()=="RM46L440-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L840-PGE"||cpu()=="RM46L840-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM48L550-ZWT") group.long 0x0++0x3 line.long 0x00 "GCR0,Global Control Register" bitfld.long 0x00 0. " GIOGCR0 ,GIO Global Control" "Reset,Normal" else group.long 0x0++0x7 line.long 0x00 "GCR0,Global Control Register" bitfld.long 0x00 0. " GIOGCR0 ,GIO Global Control" "Reset,Normal" line.long 0x04 "PWDN,Power Down" endif width 8. tree "GIO Interrupt Registers" group.long 0x8++0x3 line.long 0x0 "INTDET,Interrupt Detect" sif (cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")&&cpu()!=("RM48L950")&&cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!="RM48L550-ZWT") bitfld.long 0x00 15. " INTDET_1_7 ,GIOB7 Interrupt Detection Select" "Falling/rising,Both" bitfld.long 0x00 14. " INTDET_1_6 ,GIOB6 Interrupt Detection Select" "Falling/rising,Both" textline " " bitfld.long 0x00 13. " INTDET_1_5 ,GIOB5 Interrupt Detection Select" "Falling/rising,Both" bitfld.long 0x00 12. " INTDET_1_4 ,GIOB4 Interrupt Detection Select" "Falling/rising,Both" textline " " bitfld.long 0x00 11. " INTDET_1_3 ,GIOB3 Interrupt Detection Select" "Falling/rising,Both" bitfld.long 0x00 10. " INTDET_1_2 ,GIOB2 Interrupt Detection Select" "Falling/rising,Both" textline " " bitfld.long 0x00 9. " INTDET_1_1 ,GIOB1 Interrupt Detection Select" "Falling/rising,Both" bitfld.long 0x00 8. " INTDET_1_0 ,GIOB0 Interrupt Detection Select" "Falling/rising,Both" textline " " endif bitfld.long 0x00 7. " INTDET_0_7 ,GIOA7 Interrupt Detection Select" "Falling/rising,Both" bitfld.long 0x00 6. " INTDET_0_6 ,GIOA6 Interrupt Detection Select" "Falling/rising,Both" textline " " bitfld.long 0x00 5. " INTDET_0_5 ,GIOA5 Interrupt Detection Select" "Falling/rising,Both" bitfld.long 0x00 4. " INTDET_0_4 ,GIOA4 Interrupt Detection Select" "Falling/rising,Both" textline " " bitfld.long 0x00 3. " INTDET_0_3 ,GIOA3 Interrupt Detection Select" "Falling/rising,Both" bitfld.long 0x00 2. " INTDET_0_2 ,GIOA2 Interrupt Detection Select" "Falling/rising,Both" textline " " bitfld.long 0x00 1. " INTDET_0_1 ,GIOA1 Interrupt Detection Select" "Falling/rising,Both" bitfld.long 0x00 0. " INTDET_0_0 ,GIOA0 Interrupt Detection Select" "Falling/rising,Both" width 8. group.long 0xC++0x3 line.long 0x0 "POL,Interrupt Polarity" sif (cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")&&cpu()!=("RM48L950")&&cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!="RM48L550-ZWT") bitfld.long 0x00 15. " GIOPOL_1_7 ,GIOB7 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High" bitfld.long 0x00 14. " GIOPOL_1_6 ,GIOB6 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High" textline " " bitfld.long 0x00 13. " GIOPOL_1_5 ,GIOB5 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High" bitfld.long 0x00 12. " GIOPOL_1_4 ,GIOB4 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High" textline " " bitfld.long 0x00 11. " GIOPOL_1_3 ,GIOB3 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High" bitfld.long 0x00 10. " GIOPOL_1_2 ,GIOB2 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High" textline " " bitfld.long 0x00 9. " GIOPOL_1_1 ,GIOB1 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High" bitfld.long 0x00 8. " GIOPOL_1_0 ,GIOB0 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High" textline " " endif bitfld.long 0x00 7. " GIOPOL_0_7 ,GIOA7 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High" bitfld.long 0x00 6. " GIOPOL_0_6 ,GIOA6 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High" textline " " bitfld.long 0x00 5. " GIOPOL_0_5 ,GIOA5 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High" bitfld.long 0x00 4. " GIOPOL_0_4 ,GIOA4 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High" textline " " bitfld.long 0x00 3. " GIOPOL_0_3 ,GIOA3 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High" bitfld.long 0x00 2. " GIOPOL_0_2 ,GIOA2 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High" textline " " bitfld.long 0x00 1. " GIOPOL_0_1 ,GIOA1 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High" bitfld.long 0x00 0. " GIOPOL_0_0 ,GIOA0 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High" width 8. tree "GIO Interrupt Enable Registers" group.long 0x10++0x3 line.long 0x0 "ENASET,Interrupt Enable Set" sif (cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")&&cpu()!=("RM48L950")&&cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!="RM48L550-ZWT") bitfld.long 0x00 15. " GIOENASET_1_7 ,GIOB7 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. " GIOENASET_1_6 ,GIOB6 Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " GIOENASET_1_5 ,GIOB5 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 12. " GIOENASET_1_4 ,GIOB4 Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " GIOENASET_1_3 ,GIOB3 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10. " GIOENASET_1_2 ,GIOB2 Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " GIOENASET_1_1 ,GIOB1 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 8. " GIOENASET_1_0 ,GIOB0 Interrupt Enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 7. " GIOENASET_0_7 ,GIOA7 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. " GIOENASET_0_6 ,GIOA6 Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " GIOENASET_0_5 ,GIOA5 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " GIOENASET_0_4 ,GIOA4 Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " GIOENASET_0_3 ,GIOA3 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. " GIOENASET_0_2 ,GIOA2 Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " GIOENASET_0_1 ,GIOA1 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. " GIOENASET_0_0 ,GIOA0 Interrupt Enable" "Disabled,Enabled" width 8. group.long 0x14++0x3 line.long 0x0 "ENACLR,Interrupt Enable Clear" sif (cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")&&cpu()!=("RM48L950")&&cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!="RM48L550-ZWT") bitfld.long 0x00 15. " GIOENACLR_1_7 ,GIOB7 Interrupt Disable" "No,Yes" bitfld.long 0x00 14. " GIOENACLR_1_6 ,GIOB6 Interrupt Disable" "No,Yes" textline " " bitfld.long 0x00 13. " GIOENACLR_1_5 ,GIOB5 Interrupt Disable" "No,Yes" bitfld.long 0x00 12. " GIOENACLR_1_4 ,GIOB4 Interrupt Disable" "No,Yes" textline " " bitfld.long 0x00 11. " GIOENACLR_1_3 ,GIOB3 Interrupt Disable" "No,Yes" bitfld.long 0x00 10. " GIOENACLR_1_2 ,GIOB2 Interrupt Disable" "No,Yes" textline " " bitfld.long 0x00 9. " GIOENACLR_1_1 ,GIOB1 Interrupt Disable" "No,Yes" bitfld.long 0x00 8. " GIOENACLR_1_0 ,GIOB0 Interrupt Disable" "No,Yes" textline " " endif bitfld.long 0x00 7. " GIOENACLR_0_7 ,GIOA7 Interrupt Disable" "No,Yes" bitfld.long 0x00 6. " GIOENACLR_0_6 ,GIOA6 Interrupt Disable" "No,Yes" textline " " bitfld.long 0x00 5. " GIOENACLR_0_5 ,GIOA5 Interrupt Disable" "No,Yes" bitfld.long 0x00 4. " GIOENACLR_0_4 ,GIOA4 Interrupt Disable" "No,Yes" textline " " bitfld.long 0x00 3. " GIOENACLR_0_3 ,GIOA3 Interrupt Disable" "No,Yes" bitfld.long 0x00 2. " GIOENACLR_0_2 ,GIOA2 Interrupt Disable" "No,Yes" textline " " bitfld.long 0x00 1. " GIOENACLR_0_1 ,GIOA1 Interrupt Disable" "No,Yes" bitfld.long 0x00 0. " GIOENACLR_0_0 ,GIOA0 Interrupt Disable" "No,Yes" tree.end width 8. tree "GIO Interrupt Priority Registers" group.long 0x18++0x3 line.long 0x0 "LVLSET,Interrupt Priority Set" sif (cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")&&cpu()!=("RM48L950")&&cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!="RM48L550-ZWT") bitfld.long 0x00 15. " GIOLVLSET_1_7 ,GIOB7 High Priority Interrupt" "No effect,High priority" bitfld.long 0x00 14. " GIOLVLSET_1_6 ,GIOB6 High Priority Interrupt" "No effect,High priority" textline " " bitfld.long 0x00 13. " GIOLVLSET_1_5 ,GIOB5 High Priority Interrupt" "No effect,High priority" bitfld.long 0x00 12. " GIOLVLSET_1_4 ,GIOB4 High Priority Interrupt" "No effect,High priority" textline " " bitfld.long 0x00 11. " GIOLVLSET_1_3 ,GIOB3 High Priority Interrupt" "No effect,High priority" bitfld.long 0x00 10. " GIOLVLSET_1_2 ,GIOB2 High Priority Interrupt" "No effect,High priority" textline " " bitfld.long 0x00 9. " GIOLVLSET_1_1 ,GIOB1 High Priority Interrupt" "No effect,High priority" bitfld.long 0x00 8. " GIOLVLSET_1_0 ,GIOB0 High Priority Interrupt" "No effect,High priority" textline " " endif bitfld.long 0x00 7. " GIOLVLSET_0_7 ,GIOA7 High Priority Interrupt" "No effect,High priority" bitfld.long 0x00 6. " GIOLVLSET_0_6 ,GIOA6 High Priority Interrupt" "No effect,High priority" textline " " bitfld.long 0x00 5. " GIOLVLSET_0_5 ,GIOA5 High Priority Interrupt" "No effect,High priority" bitfld.long 0x00 4. " GIOLVLSET_0_4 ,GIOA4 High Priority Interrupt" "No effect,High priority" textline " " bitfld.long 0x00 3. " GIOLVLSET_0_3 ,GIOA3 High Priority Interrupt" "No effect,High priority" bitfld.long 0x00 2. " GIOLVLSET_0_2 ,GIOA2 High Priority Interrupt" "No effect,High priority" textline " " bitfld.long 0x00 1. " GIOLVLSET_0_1 ,GIOA1 High Priority Interrupt" "No effect,High priority" bitfld.long 0x00 0. " GIOLVLSET_0_0 ,GIOA0 High Priority Interrupt" "No effect,High priority" group.long 0x1C++0x3 line.long 0x0 "LVLCLR,Interrupt Priority Clear" sif (cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")&&cpu()!=("RM48L950")&&cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!="RM48L550-ZWT") bitfld.long 0x00 15. " GIOLVLCLR_1_7 ,GIOB7 Low Priority Interrupt" "No effect,Low priority" bitfld.long 0x00 14. " GIOLVLCLR_1_6 ,GIOB6 Low Priority Interrupt" "No effect,Low priority" textline " " bitfld.long 0x00 13. " GIOLVLCLR_1_5 ,GIOB5 Low Priority Interrupt" "No effect,Low priority" bitfld.long 0x00 12. " GIOLVLCLR_1_4 ,GIOB4 Low Priority Interrupt" "No effect,Low priority" textline " " bitfld.long 0x00 11. " GIOLVLCLR_1_3 ,GIOB3 Low Priority Interrupt" "No effect,Low priority" bitfld.long 0x00 10. " GIOLVLCLR_1_2 ,GIOB2 Low Priority Interrupt" "No effect,Low priority" textline " " bitfld.long 0x00 9. " GIOLVLCLR_1_1 ,GIOB1 Low Priority Interrupt" "No effect,Low priority" bitfld.long 0x00 8. " GIOLVLCLR_1_0 ,GIOB0 Low Priority Interrupt" "No effect,Low priority" textline " " endif bitfld.long 0x00 7. " GIOLVLCLR_0_7 ,GIOA7 Low Priority Interrupt" "No effect,Low priority" bitfld.long 0x00 6. " GIOLVLCLR_0_6 ,GIOA6 Low Priority Interrupt" "No effect,Low priority" textline " " bitfld.long 0x00 5. " GIOLVLCLR_0_5 ,GIOA5 Low Priority Interrupt" "No effect,Low priority" bitfld.long 0x00 4. " GIOLVLCLR_0_4 ,GIOA4 Low Priority Interrupt" "No effect,Low priority" textline " " bitfld.long 0x00 3. " GIOLVLCLR_0_3 ,GIOA3 Low Priority Interrupt" "No effect,Low priority" bitfld.long 0x00 2. " GIOLVLCLR_0_2 ,GIOA2 Low Priority Interrupt" "No effect,Low priority" textline " " bitfld.long 0x00 1. " GIOLVLCLR_0_1 ,GIOA1 Low Priority Interrupt" "No effect,Low priority" bitfld.long 0x00 0. " GIOLVLCLR_0_0 ,GIOA0 Low Priority Interrupt" "No effect,Low priority" tree.end width 8. group.long 0x20++0x3 line.long 0x0 "FLG,Interrupt Flag" sif (cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")&&cpu()!=("RM48L950")&&cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!="RM48L550-ZWT") eventfld.long 0x00 15. " GIOFLG_1_7 ,GIOB7 Flag" "Not occurred,Occurred" eventfld.long 0x00 14. " GIOFLG_1_6 ,GIOB6 Flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 13. " GIOFLG_1_5 ,GIOB5 Flag" "Not occurred,Occurred" eventfld.long 0x00 12. " GIOFLG_1_4 ,GIOB4 Flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 11. " GIOFLG_1_3 ,GIOB3 Flag" "Not occurred,Occurred" eventfld.long 0x00 10. " GIOFLG_1_2 ,GIOB2 Flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 9. " GIOFLG_1_1 ,GIOB1 Flag" "Not occurred,Occurred" eventfld.long 0x00 8. " GIOFLG_1_0 ,GIOB0 Flag" "Not occurred,Occurred" textline " " endif eventfld.long 0x00 7. " GIOFLG_0_7 ,GIOA7 Flag" "Not occurred,Occurred" eventfld.long 0x00 6. " GIOFLG_0_6 ,GIOA6 Flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 5. " GIOFLG_0_5 ,GIOA5 Flag" "Not occurred,Occurred" eventfld.long 0x00 4. " GIOFLG_0_4 ,GIOA4 Flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 3. " GIOFLG_0_3 ,GIOA3 Flag" "Not occurred,Occurred" eventfld.long 0x00 2. " GIOFLG_0_2 ,GIOA2 Flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 1. " GIOFLG_0_1 ,GIOA1 Flag" "Not occurred,Occurred" eventfld.long 0x00 0. " GIOFLG_0_0 ,GIOA0 Flag" "Not occurred,Occurred" width 6. tree "GIO Interrupt Offset Registers" hgroup.long 0x24++0x3 hide.long 0x0 "OFFA,Offset A" in rgroup.long 0x2C++0x3 line.long 0x0 "EMUA,Emulation A" sif (cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")&&cpu()!=("RM48L950")&&cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!="RM48L550-ZWT") bitfld.long 0x00 0.--5. " GIOEMUA ,GIO Offset A" "No interrupt,Interrupt 0,Interrupt 1,Interrupt 2,Interrupt 3,Interrupt 4,Interrupt 5,Interrupt 6,Interrupt 7,?..." else bitfld.long 0x00 0.--5. " GIOEMUA ,GIO Offset A" "No interrupt,Interrupt 0,Interrupt 1,Interrupt 2,Interrupt 3,Interrupt 4,Interrupt 5,Interrupt 6,Interrupt 7,Interrupt 8,Interrupt 9,Interrupt 10,Interrupt 11,Interrupt 12,Interrupt 13,Interrupt 14,Interrupt 15,Interrupt 16,Interrupt 17,Interrupt 18,Interrupt 19,Interrupt 20,Interrupt 21,Interrupt 22,Interrupt 23,Interrupt 24,Interrupt 25,Interrupt 26,Interrupt 27,Interrupt 28,Interrupt 29,Interrupt 30,Interrupt 31,?..." endif hgroup.long 0x28++0x3 hide.long 0x0 "OFFB,Offset B" in rgroup.long 0x30++0x3 line.long 0x0 "EMUB,Emulation B" sif (cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")&&cpu()!=("RM48L950")&&cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!="RM48L550-ZWT") bitfld.long 0x00 0.--5. " GIOEMUB ,GIO Offset B" "No interrupt,Interrupt 0,Interrupt 1,Interrupt 2,Interrupt 3,Interrupt 4,Interrupt 5,Interrupt 6,Interrupt 7,?..." else bitfld.long 0x00 0.--5. " GIOEMUB ,GIO Offset B" "No interrupt,Interrupt 0,Interrupt 1,Interrupt 2,Interrupt 3,Interrupt 4,Interrupt 5,Interrupt 6,Interrupt 7,Interrupt 8,Interrupt 9,Interrupt 10,Interrupt 11,Interrupt 12,Interrupt 13,Interrupt 14,Interrupt 15,Interrupt 16,Interrupt 17,Interrupt 18,Interrupt 19,Interrupt 20,Interrupt 21,Interrupt 22,Interrupt 23,Interrupt 24,Interrupt 25,Interrupt 26,Interrupt 27,Interrupt 28,Interrupt 29,Interrupt 30,Interrupt 31,?..." endif tree.end tree.end width 0xb tree.end tree "GIOA" base ad:0xFFF7BC00 width 9. rgroup.long 0x34++0x3 line.long 0x0 "DIR,Data Direction GIOA" sif (cpu()==("TMS570LS2124-PGE")||cpu()==("TMS570LS2124-ZWT")||cpu()==("TMS570LS2134-PGE")||cpu()==("TMS570LS2134-ZWT")||cpu()==("TMS570LS3134-PGE")||cpu()==("TMS570LS3134-ZWT")||cpu()==("TMS570LS3135-PGE")||cpu()==("TMS570LS3135-ZWT")||cpu()==("TMS570LS3136")||cpu()==("TMS570LS3137-PGE")||cpu()==("TMS570LS3137-ZWT")||cpu()==("TMS570LS30336")||cpu()==("TMS570LS2126")||cpu()==("TMS570LS2127")||cpu()==("TMS570LS2136")||cpu()==("TMS570LS2137")||cpu()==("TMS570LS2125-PGE")||cpu()==("TMS570LS2125-ZWT")||cpu()==("TMS570LS2135-PGE")||cpu()==("TMS570LS2135-ZWT")||cpu()==("RM48L950")||cpu()=="RM48L952-PGE"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L940-ZWT"||cpu()=="RM48L940-PGE"||cpu()=="RM48L930-ZWT"||cpu()=="RM48L930-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L740-ZWT"||cpu()=="RM48L740-PGE"||cpu()=="RM48L730-ZWT"||cpu()=="RM48L730-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L540-ZWT"||cpu()=="RM48L540-PGE"||cpu()=="RM48L530-ZWT"||cpu()=="RM48L530-PGE"||cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L840-ZWT"||cpu()=="RM46L840-PGE"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L440-ZWT"||cpu()=="RM46L440-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L430-PGE") bitfld.long 0x00 7. " GIODIR7 ,GIO Data Direction 7" "Input,Output" bitfld.long 0x00 6. " GIODIR6 ,GIO Data Direction 6" "Input,Output" textline " " bitfld.long 0x00 5. " GIODIR5 ,GIO Data Direction 5" "Input,Output" bitfld.long 0x00 4. " GIODIR4 ,GIO Data Direction 4" "Input,Output" textline " " bitfld.long 0x00 3. " GIODIR3 ,GIO Data Direction 3" "Input,Output" bitfld.long 0x00 2. " GIODIR2 ,GIO Data Direction 2" "Input,Output" textline " " bitfld.long 0x00 1. " GIODIR1 ,GIO Data Direction 1" "Input,Output" bitfld.long 0x00 0. " GIODIR0 ,GIO Data Direction 0" "Input,Output" else bitfld.long 0x00 7. " GIODIR7 ,GIO Data Direction 7" "Output disabled,Output enabled" bitfld.long 0x00 6. " GIODIR6 ,GIO Data Direction 6" "Output disabled,Output enabled" textline " " bitfld.long 0x00 5. " GIODIR5 ,GIO Data Direction 5" "Output disabled,Output enabled" bitfld.long 0x00 4. " GIODIR4 ,GIO Data Direction 4" "Output disabled,Output enabled" textline " " bitfld.long 0x00 3. " GIODIR3 ,GIO Data Direction 3" "Output disabled,Output enabled" bitfld.long 0x00 2. " GIODIR2 ,GIO Data Direction 2" "Output disabled,Output enabled" textline " " bitfld.long 0x00 1. " GIODIR1 ,GIO Data Direction 1" "Output disabled,Output enabled" bitfld.long 0x00 0. " GIODIR0 ,GIO Data Direction 0" "Output disabled,Output enabled" endif width 9. rgroup.long 0x38++0x3 line.long 0x0 "DIN,Data Input GIOA" bitfld.long 0x00 7. " GIODIN7 ,GIO Data Input 7" "Low,High" bitfld.long 0x00 6. " GIODIN6 ,GIO Data Input 6" "Low,High" textline " " bitfld.long 0x00 5. " GIODIN5 ,GIO Data Input 5" "Low,High" bitfld.long 0x00 4. " GIODIN4 ,GIO Data Input 4" "Low,High" textline " " bitfld.long 0x00 3. " GIODIN3 ,GIO Data Input 3" "Low,High" bitfld.long 0x00 2. " GIODIN2 ,GIO Data Input 2" "Low,High" textline " " bitfld.long 0x00 1. " GIODIN1 ,GIO Data Input 1" "Low,High" bitfld.long 0x00 0. " GIODIN0 ,GIO Data Input 0" "Low,High" width 9. group.long 0x3C++0x3 line.long 0x0 "DOUT,Data Output GIOA" setclrfld.long 0x00 7. 0x04 7. 0x08 7. " GIODOUT7_set/clr ,GIO Data Output 7" "Low,High" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " GIODOUT6_set/clr ,GIO Data Output 6" "Low,High" textline " " setclrfld.long 0x00 5. 0x04 5. 0x08 5. " GIODOUT5_set/clr ,GIO Data Output 5" "Low,High" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " GIODOUT4_set/clr ,GIO Data Output 4" "Low,High" textline " " setclrfld.long 0x00 3. 0x04 3. 0x08 3. " GIODOUT3_set/clr ,GIO Data Output 3" "Low,High" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " GIODOUT2_set/clr ,GIO Data Output 2" "Low,High" textline " " setclrfld.long 0x00 1. 0x04 1. 0x08 1. " GIODOUT1_set/clr ,GIO Data Output 1" "Low,High" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " GIODOUT0_set/clr ,GIO Data Output 0" "Low,High" width 9. group.long 0x48++0x3 line.long 0x0 "PDR,Open Drain GIOA" bitfld.long 0x00 7. " GIOPDR7 ,GIO Open Drain 7" "Disabled,Enabled" bitfld.long 0x00 6. " GIOPDR6 ,GIO Open Drain 6" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " GIOPDR5 ,GIO Open Drain 5" "Disabled,Enabled" bitfld.long 0x00 4. " GIOPDR4 ,GIO Open Drain 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " GIOPDR3 ,GIO Open Drain 3" "Disabled,Enabled" bitfld.long 0x00 2. " GIOPDR2 ,GIO Open Drain 2" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " GIOPDR1 ,GIO Open Drain 1" "Disabled,Enabled" bitfld.long 0x00 0. " GIOPDR0 ,GIO Open Drain 0" "Disabled,Enabled" width 9. group.long 0x4C++0x3 line.long 0x0 "PULLDIS,Pull Disable GIOA" bitfld.long 0x0 7. " GIOPULDIS7 ,GIO Pull Disable 7" "No,Yes" bitfld.long 0x0 6. " GIOPULDIS6 ,GIO Pull Disable 6" "No,Yes" textline " " bitfld.long 0x0 5. " GIOPULDIS5 ,GIO Pull Disable 5" "No,Yes" bitfld.long 0x0 4. " GIOPULDIS4 ,GIO Pull Disable 4" "No,Yes" textline " " bitfld.long 0x0 3. " GIOPULDIS3 ,GIO Pull Disable 3" "No,Yes" bitfld.long 0x0 2. " GIOPULDIS2 ,GIO Pull Disable 2" "No,Yes" textline " " bitfld.long 0x0 1. " GIOPULDIS1 ,GIO Pull Disable 1" "No,Yes" bitfld.long 0x0 0. " GIOPULDIS0 ,GIO Pull Disable 0" "No,Yes" width 9. group.long 0x50++0x3 line.long 0x0 "PSL,Pull Select GIOA" bitfld.long 0x0 7. " GIOPSL7 ,GIO Pull Select 7" "Pull down,Pull up" bitfld.long 0x0 6. " GIOPSL6 ,GIO Pull Select 6" "Pull down,Pull up" textline " " bitfld.long 0x0 5. " GIOPSL5 ,GIO Pull Select 5" "Pull down,Pull up" bitfld.long 0x0 4. " GIOPSL4 ,GIO Pull Select 4" "Pull down,Pull up" textline " " bitfld.long 0x0 3. " GIOPSL3 ,GIO Pull Select 3" "Pull down,Pull up" bitfld.long 0x0 2. " GIOPSL2 ,GIO Pull Select 2" "Pull down,Pull up" textline " " bitfld.long 0x0 1. " GIOPSL1 ,GIO Pull Select 1" "Pull down,Pull up" bitfld.long 0x0 0. " GIOPSL0 ,GIO Pull Select 0" "Pull down,Pull up" sif (cpu()!="TMS570PSFC61"&&cpu()!="RM48L952-PGE"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!="RM46L852-PGE"&&cpu()!="RM46L852-ZWT"&&cpu()!="RM46L850-PGE"&&cpu()!="RM46L850-ZWT"&&cpu()!="RM46L840-ZWT"&&cpu()!="RM46L840-PGE"&&cpu()!="RM46L830-ZWT"&&cpu()!="RM46L830-PGE"&&cpu()!="RM46L450-ZWT"&&cpu()!="RM46L450-PGE"&&cpu()!="RM46L440-ZWT"&&cpu()!="RM46L440-PGE"&&cpu()!="RM46L430-ZWT"&&cpu()!="RM46L430-PGE"&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!="RM48L550-ZWT") width 9. group.long 0x134++0x3 line.long 0x0 "SRS,Slew Rate Select GIOA" bitfld.long 0x00 7. " GIOSRS7 ,GIO Slew Rate Select 7" "Normal,Slow" bitfld.long 0x00 6. " GIOSRS6 ,GIO Slew Rate Select 6" "Normal,Slow" textline " " bitfld.long 0x00 5. " GIOSRS5 ,GIO Slew Rate Select 5" "Normal,Slow" bitfld.long 0x00 4. " GIOSRS4 ,GIO Slew Rate Select 4" "Normal,Slow" textline " " bitfld.long 0x00 3. " GIOSRS3 ,GIO Slew Rate Select 3" "Normal,Slow" bitfld.long 0x00 2. " GIOSRS2 ,GIO Slew Rate Select 2" "Normal,Slow" textline " " bitfld.long 0x00 1. " GIOSRS1 ,GIO Slew Rate Select 1" "Normal,Slow" bitfld.long 0x00 0. " GIOSRS0 ,GIO Slew Rate Select 0" "Normal,Slow" endif width 0xb tree.end tree "GIOB" base ad:0xFFF7BC00 width 9. rgroup.long 0x54++0x3 line.long 0x0 "DIR,Data Direction GIOB" sif (cpu()=="TMS570PSFC61") bitfld.long 0x00 7. " GIODIR7 ,GIO Data Direction 7" "Output disabled,Output enabled" bitfld.long 0x00 6. " GIODIR6 ,GIO Data Direction 6" "Output disabled,Output enabled" textline " " bitfld.long 0x00 5. " GIODIR5 ,GIO Data Direction 5" "Output disabled,Output enabled" bitfld.long 0x00 4. " GIODIR4 ,GIO Data Direction 4" "Output disabled,Output enabled" textline " " bitfld.long 0x00 3. " GIODIR3 ,GIO Data Direction 3" "Output disabled,Output enabled" bitfld.long 0x00 2. " GIODIR2 ,GIO Data Direction 2" "Output disabled,Output enabled" textline " " bitfld.long 0x00 1. " GIODIR1 ,GIO Data Direction 1" "Output disabled,Output enabled" bitfld.long 0x00 0. " GIODIR0 ,GIO Data Direction 0" "Output disabled,Output enabled" elif (cpu()==("TMS570LS2124-PGE")||cpu()==("TMS570LS2124-ZWT")||cpu()==("TMS570LS2134-PGE")||cpu()==("TMS570LS2134-ZWT")||cpu()==("TMS570LS3134-PGE")||cpu()==("TMS570LS3134-ZWT")||cpu()==("TMS570LS3135-PGE")||cpu()==("TMS570LS3135-ZWT")||cpu()==("TMS570LS3136")||cpu()==("TMS570LS3137-PGE")||cpu()==("TMS570LS3137-ZWT")||cpu()==("TMS570LS30336")||cpu()==("TMS570LS2126")||cpu()==("TMS570LS2127")||cpu()==("TMS570LS2136")||cpu()==("TMS570LS2137")||cpu()==("TMS570LS2125-PGE")||cpu()==("TMS570LS2125-ZWT")||cpu()==("TMS570LS2135-PGE")||cpu()==("TMS570LS2135-ZWT")||cpu()==("RM48L950")||cpu()=="RM48L952-PGE"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L940-ZWT"||cpu()=="RM48L940-PGE"||cpu()=="RM48L930-ZWT"||cpu()=="RM48L930-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L740-ZWT"||cpu()=="RM48L740-PGE"||cpu()=="RM48L730-ZWT"||cpu()=="RM48L730-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L540-ZWT"||cpu()=="RM48L540-PGE"||cpu()=="RM48L530-ZWT"||cpu()=="RM48L530-PGE"||cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L840-ZWT"||cpu()=="RM46L840-PGE"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L440-ZWT"||cpu()=="RM46L440-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L430-PGE"||cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10206-PGE")||cpu()=="RM48L550-ZWT") bitfld.long 0x00 7. " GIODIR7 ,GIO Data Direction 7" "Input,Output" bitfld.long 0x00 6. " GIODIR6 ,GIO Data Direction 6" "Input,Output" textline " " bitfld.long 0x00 5. " GIODIR5 ,GIO Data Direction 5" "Input,Output" bitfld.long 0x00 4. " GIODIR4 ,GIO Data Direction 4" "Input,Output" textline " " bitfld.long 0x00 3. " GIODIR3 ,GIO Data Direction 3" "Input,Output" bitfld.long 0x00 2. " GIODIR2 ,GIO Data Direction 2" "Input,Output" textline " " bitfld.long 0x00 1. " GIODIR1 ,GIO Data Direction 1" "Input,Output" bitfld.long 0x00 0. " GIODIR0 ,GIO Data Direction 0" "Input,Output" else bitfld.long 0x00 1. " GIODIR1 ,GIO Data Direction 1" "Output disabled,Output enabled" bitfld.long 0x00 0. " GIODIR0 ,GIO Data Direction 0" "Output disabled,Output enabled" endif width 9. sif (cpu()=="TMS570PSFC61"||cpu()==("TMS570LS2126")||cpu()==("TMS570LS2127")||cpu()==("TMS570LS2136")||cpu()==("TMS570LS2137")||cpu()==("TMS570LS2125-PGE")||cpu()==("TMS570LS2125-ZWT")||cpu()==("TMS570LS2135-PGE")||cpu()==("TMS570LS2135-ZWT")||cpu()==("TMS570LS2124-PGE")||cpu()==("TMS570LS2124-ZWT")||cpu()==("TMS570LS2134-PGE")||cpu()==("TMS570LS2134-ZWT")||cpu()==("TMS570LS3134-PGE")||cpu()==("TMS570LS3134-ZWT")||cpu()==("TMS570LS3135-PGE")||cpu()==("TMS570LS3135-ZWT")||cpu()==("TMS570LS3136")||cpu()==("TMS570LS3137-PGE")||cpu()==("TMS570LS3137-ZWT")||cpu()==("TMS570LS30336")||cpu()==("RM48L950")||cpu()=="RM48L952-PGE"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L940-ZWT"||cpu()=="RM48L940-PGE"||cpu()=="RM48L930-ZWT"||cpu()=="RM48L930-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L740-ZWT"||cpu()=="RM48L740-PGE"||cpu()=="RM48L730-ZWT"||cpu()=="RM48L730-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L540-ZWT"||cpu()=="RM48L540-PGE"||cpu()=="RM48L530-ZWT"||cpu()=="RM48L530-PGE"||cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L840-ZWT"||cpu()=="RM46L840-PGE"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L440-ZWT"||cpu()=="RM46L440-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L430-PGE"||cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10206-PGE")||cpu()=="RM48L550-ZWT") rgroup.long 0x58++0x3 line.long 0x0 "DIN,Data Input GIOB" bitfld.long 0x00 7. " GIODIN7 ,GIO Data Input 7" "Low,High" bitfld.long 0x00 6. " GIODIN6 ,GIO Data Input 6" "Low,High" textline " " bitfld.long 0x00 5. " GIODIN5 ,GIO Data Input 5" "Low,High" bitfld.long 0x00 4. " GIODIN4 ,GIO Data Input 4" "Low,High" textline " " bitfld.long 0x00 3. " GIODIN3 ,GIO Data Input 3" "Low,High" bitfld.long 0x00 2. " GIODIN2 ,GIO Data Input 2" "Low,High" textline " " bitfld.long 0x00 1. " GIODIN1 ,GIO Data Input 1" "Low,High" bitfld.long 0x00 0. " GIODIN0 ,GIO Data Input 0" "Low,High" else group.long 0x58++0x3 line.long 0x0 "DIN,Data Input GIOB" bitfld.long 0x00 1. " GIODIN1 ,GIO Data Input 1" "Low,High" bitfld.long 0x00 0. " GIODIN0 ,GIO Data Input 0" "Low,High" endif width 9. group.long 0x5C++0x3 line.long 0x0 "DOUT,Data Output GIOB" sif (cpu()=="TMS570PSFC61"||cpu()==("TMS570LS2126")||cpu()==("TMS570LS2127")||cpu()==("TMS570LS2136")||cpu()==("TMS570LS2137")||cpu()==("TMS570LS2125-PGE")||cpu()==("TMS570LS2125-ZWT")||cpu()==("TMS570LS2135-PGE")||cpu()==("TMS570LS2135-ZWT")||cpu()==("TMS570LS2124-PGE")||cpu()==("TMS570LS2124-ZWT")||cpu()==("TMS570LS2134-PGE")||cpu()==("TMS570LS2134-ZWT")||cpu()==("TMS570LS3134-PGE")||cpu()==("TMS570LS3134-ZWT")||cpu()==("TMS570LS3135-PGE")||cpu()==("TMS570LS3135-ZWT")||cpu()==("TMS570LS3136")||cpu()==("TMS570LS3137-PGE")||cpu()==("TMS570LS3137-ZWT")||cpu()==("TMS570LS30336")||cpu()==("RM48L950")||cpu()=="RM48L952-PGE"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L940-ZWT"||cpu()=="RM48L940-PGE"||cpu()=="RM48L930-ZWT"||cpu()=="RM48L930-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L740-ZWT"||cpu()=="RM48L740-PGE"||cpu()=="RM48L730-ZWT"||cpu()=="RM48L730-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L540-ZWT"||cpu()=="RM48L540-PGE"||cpu()=="RM48L530-ZWT"||cpu()=="RM48L530-PGE"||cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L840-ZWT"||cpu()=="RM46L840-PGE"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L440-ZWT"||cpu()=="RM46L440-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L430-PGE"||cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10206-PGE")||cpu()=="RM48L550-ZWT") setclrfld.long 0x00 7. 0x04 7. 0x08 7. " GIODOUT7_set/clr ,GIO Data Output 7" "Low,High" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " GIODOUT6_set/clr ,GIO Data Output 6" "Low,High" textline " " setclrfld.long 0x00 5. 0x04 5. 0x08 5. " GIODOUT5_set/clr ,GIO Data Output 5" "Low,High" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " GIODOUT4_set/clr ,GIO Data Output 4" "Low,High" textline " " setclrfld.long 0x00 3. 0x04 3. 0x08 3. " GIODOUT3_set/clr ,GIO Data Output 3" "Low,High" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " GIODOUT2_set/clr ,GIO Data Output 2" "Low,High" textline " " endif setclrfld.long 0x00 1. 0x04 1. 0x08 1. " GIODOUT1_set/clr ,GIO Data Output 1" "Low,High" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " GIODOUT0_set/clr ,GIO Data Output 0" "Low,High" width 9. group.long 0x68++0x3 line.long 0x0 "PDR,Open Drain GIOB" sif (cpu()=="TMS570PSFC61"||cpu()==("TMS570LS2126")||cpu()==("TMS570LS2127")||cpu()==("TMS570LS2136")||cpu()==("TMS570LS2137")||cpu()==("TMS570LS2125-PGE")||cpu()==("TMS570LS2125-ZWT")||cpu()==("TMS570LS2135-PGE")||cpu()==("TMS570LS2135-ZWT")||cpu()==("TMS570LS2124-PGE")||cpu()==("TMS570LS2124-ZWT")||cpu()==("TMS570LS2134-PGE")||cpu()==("TMS570LS2134-ZWT")||cpu()==("TMS570LS3134-PGE")||cpu()==("TMS570LS3134-ZWT")||cpu()==("TMS570LS3135-PGE")||cpu()==("TMS570LS3135-ZWT")||cpu()==("TMS570LS3136")||cpu()==("TMS570LS3137-PGE")||cpu()==("TMS570LS3137-ZWT")||cpu()==("TMS570LS30336")||cpu()==("RM48L950")||cpu()=="RM48L952-PGE"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L940-ZWT"||cpu()=="RM48L940-PGE"||cpu()=="RM48L930-ZWT"||cpu()=="RM48L930-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L740-ZWT"||cpu()=="RM48L740-PGE"||cpu()=="RM48L730-ZWT"||cpu()=="RM48L730-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L540-ZWT"||cpu()=="RM48L540-PGE"||cpu()=="RM48L530-ZWT"||cpu()=="RM48L530-PGE"||cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L840-ZWT"||cpu()=="RM46L840-PGE"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L440-ZWT"||cpu()=="RM46L440-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L430-PGE"||cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10206-PGE")||cpu()=="RM48L550-ZWT") bitfld.long 0x00 7. " GIOPDR7 ,GIO Open Drain 7" "Disabled,Enabled" bitfld.long 0x00 6. " GIOPDR6 ,GIO Open Drain 6" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " GIOPDR5 ,GIO Open Drain 5" "Disabled,Enabled" bitfld.long 0x00 4. " GIOPDR4 ,GIO Open Drain 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " GIOPDR3 ,GIO Open Drain 3" "Disabled,Enabled" bitfld.long 0x00 2. " GIOPDR2 ,GIO Open Drain 2" "Disabled,Enabled" textline " " endif bitfld.long 0x00 1. " GIOPDR1 ,GIO Open Drain 1" "Disabled,Enabled" bitfld.long 0x00 0. " GIOPDR0 ,GIO Open Drain 0" "Disabled,Enabled" group.long 0x6C++0x3 line.long 0x0 "PULLDIS,Pull Disable GIOB" sif (cpu()=="TMS570PSFC61"||cpu()==("TMS570LS2126")||cpu()==("TMS570LS2127")||cpu()==("TMS570LS2136")||cpu()==("TMS570LS2137")||cpu()==("TMS570LS2125-PGE")||cpu()==("TMS570LS2125-ZWT")||cpu()==("TMS570LS2135-PGE")||cpu()==("TMS570LS2135-ZWT")||cpu()==("TMS570LS2124-PGE")||cpu()==("TMS570LS2124-ZWT")||cpu()==("TMS570LS2134-PGE")||cpu()==("TMS570LS2134-ZWT")||cpu()==("TMS570LS3134-PGE")||cpu()==("TMS570LS3134-ZWT")||cpu()==("TMS570LS3135-PGE")||cpu()==("TMS570LS3135-ZWT")||cpu()==("TMS570LS3136")||cpu()==("TMS570LS3137-PGE")||cpu()==("TMS570LS3137-ZWT")||cpu()==("TMS570LS30336")||cpu()==("RM48L950")||cpu()=="RM48L952-PGE"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L940-ZWT"||cpu()=="RM48L940-PGE"||cpu()=="RM48L930-ZWT"||cpu()=="RM48L930-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L740-ZWT"||cpu()=="RM48L740-PGE"||cpu()=="RM48L730-ZWT"||cpu()=="RM48L730-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L540-ZWT"||cpu()=="RM48L540-PGE"||cpu()=="RM48L530-ZWT"||cpu()=="RM48L530-PGE"||cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L840-ZWT"||cpu()=="RM46L840-PGE"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L440-ZWT"||cpu()=="RM46L440-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L430-PGE"||cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10206-PGE")||cpu()=="RM48L550-ZWT") bitfld.long 0x0 7. " GIOPULDIS6 ,GIO Pull Disable 6" "No,Yes" bitfld.long 0x0 6. " GIOPULDIS6 ,GIO Pull Disable 6" "No,Yes" textline " " bitfld.long 0x0 5. " GIOPULDIS5 ,GIO Pull Disable 5" "No,Yes" bitfld.long 0x0 4. " GIOPULDIS4 ,GIO Pull Disable 4" "No,Yes" textline " " bitfld.long 0x0 3. " GIOPULDIS3 ,GIO Pull Disable 3" "No,Yes" bitfld.long 0x0 2. " GIOPULDIS2 ,GIO Pull Disable 2" "No,Yes" textline " " endif bitfld.long 0x0 1. " GIOPULDIS1 ,GIO Pull Disable 1" "No,Yes" bitfld.long 0x0 0. " GIOPULDIS0 ,GIO Pull Disable 0" "No,Yes" group.long 0x70++0x3 line.long 0x0 "PSL,Pull Select GIOB" sif (cpu()=="TMS570PSFC61"||cpu()==("TMS570LS2126")||cpu()==("TMS570LS2127")||cpu()==("TMS570LS2136")||cpu()==("TMS570LS2137")||cpu()==("TMS570LS2125-PGE")||cpu()==("TMS570LS2125-ZWT")||cpu()==("TMS570LS2135-PGE")||cpu()==("TMS570LS2135-ZWT")||cpu()==("TMS570LS2124-PGE")||cpu()==("TMS570LS2124-ZWT")||cpu()==("TMS570LS2134-PGE")||cpu()==("TMS570LS2134-ZWT")||cpu()==("TMS570LS3134-PGE")||cpu()==("TMS570LS3134-ZWT")||cpu()==("TMS570LS3135-PGE")||cpu()==("TMS570LS3135-ZWT")||cpu()==("TMS570LS3136")||cpu()==("TMS570LS3137-PGE")||cpu()==("TMS570LS3137-ZWT")||cpu()==("TMS570LS30336")||cpu()==("RM48L950")||cpu()=="RM48L952-PGE"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L940-ZWT"||cpu()=="RM48L940-PGE"||cpu()=="RM48L930-ZWT"||cpu()=="RM48L930-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L740-ZWT"||cpu()=="RM48L740-PGE"||cpu()=="RM48L730-ZWT"||cpu()=="RM48L730-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L540-ZWT"||cpu()=="RM48L540-PGE"||cpu()=="RM48L530-ZWT"||cpu()=="RM48L530-PGE"||cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L840-ZWT"||cpu()=="RM46L840-PGE"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L440-ZWT"||cpu()=="RM46L440-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L430-PGE"||cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10206-PGE")||cpu()=="RM48L550-ZWT") bitfld.long 0x0 7. " GIOPSL7 ,GIO Pull Select 7" "Pull down,Pull up" bitfld.long 0x0 6. " GIOPSL6 ,GIO Pull Select 6" "Pull down,Pull up" textline " " bitfld.long 0x0 5. " GIOPSL5 ,GIO Pull Select 5" "Pull down,Pull up" bitfld.long 0x0 4. " GIOPSL4 ,GIO Pull Select 4" "Pull down,Pull up" textline " " bitfld.long 0x0 3. " GIOPSL3 ,GIO Pull Select 3" "Pull down,Pull up" bitfld.long 0x0 2. " GIOPSL2 ,GIO Pull Select 2" "Pull down,Pull up" textline " " endif bitfld.long 0x0 1. " GIOPSL1 ,GIO Pull Select 1" "Pull down,Pull up" bitfld.long 0x0 0. " GIOPSL0 ,GIO Pull Select 0" "Pull down,Pull up" sif (cpu()!="TMS570PSFC61"&&cpu()!="RM48L952-PGE"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!="RM46L852-PGE"&&cpu()!="RM46L852-ZWT"&&cpu()!="RM46L850-PGE"&&cpu()!="RM46L850-ZWT"&&cpu()!="RM46L840-ZWT"&&cpu()!="RM46L840-PGE"&&cpu()!="RM46L830-ZWT"&&cpu()!="RM46L830-PGE"&&cpu()!="RM46L450-ZWT"&&cpu()!="RM46L450-PGE"&&cpu()!="RM46L440-ZWT"&&cpu()!="RM46L440-PGE"&&cpu()!="RM46L430-ZWT"&&cpu()!="RM46L430-PGE"&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()=="RM48L550-ZWT") group.long 0x138++0x3 line.long 0x0 "SRS,Slew Rate Select GIOB" bitfld.long 0x00 1. " GIOSRS1 ,GIO Slew Rate Select 1" "Normal,Slow" bitfld.long 0x00 0. " GIOSRS0 ,GIO Slew Rate Select 0" "Normal,Slow" endif width 0xb tree.end tree.end tree "NHET (New High End Timer)" base ad:0xFFF7B800 sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*") endian.be endif width 15. group.long 0x00++0x07 line.long 0x0 "GCR,Global Control Register" bitfld.long 0x00 24. " HET_PIN_ENA ,NHET Pin Enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " MP ,Master Priority" "Lower,Higher,Round robin,?..." bitfld.long 0x00 18. " PPF ,Protect Program Fields" "Low,High" newline bitfld.long 0x00 17. " IS ,Ignore Suspend" "Not ignored,Ignored" bitfld.long 0x00 16. " CMS ,Clk_master/Slave" "Slave,Master" bitfld.long 0x00 0. " TO ,Turn On/Off" "Off,On" line.long 0x04 "PFR,Prescaler Factor Register" bitfld.long 0x04 8.--10. " LRPFC ,Loop Resolution Pre-scale Factor Code" "1,2,4,8,16,32,64,128" bitfld.long 0x04 0.--5. " HRPFC ,HR Prescale Factor Code" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" rgroup.long 0x08++0x0B line.long 0x0 "ADDR,Current Address Register" hexmask.long.word 0x00 0.--8. 1. " HETADDR ,N2HET Current Address" line.long 0x04 "OFF1,Offset Level 1 Register" hexmask.long.byte 0x04 0.--5. 1. " Offset1 ,Indexes the Currently Pending High-Priority Interrupt" line.long 0x08 "OFF2,Offset Level 2 Register" hexmask.long.byte 0x08 0.--5. 1. " Offset2 ,Indexes the Currently Pending High-Priority Interrupt" newline group.long 0x14++0x03 line.long 0x00 "INTENA_SETCLR,Interrupt Enable Set/Clear Register" setclrfld.long 0x00 31. 0x00 31. 0x04 31. " HETINTENAS_setclr[31] ,Interrupt Enable Set Pin 31" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Interrupt enable set/clear bit 30" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [29] ,Interrupt enable set/clear bit 29" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Interrupt enable set/clear bit 28" "Disabled,Enabled" newline setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Interrupt enable set/clear bit 27" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Interrupt enable set/clear bit 26" "Disabled,Enabled" setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [25] ,Interrupt enable set/clear bit 25" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Interrupt enable set/clear bit 24" "Disabled,Enabled" newline setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Interrupt enable set/clear bit 23" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Interrupt enable set/clear bit 22" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Interrupt enable set/clear bit 21" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Interrupt enable set/clear bit 20" "Disabled,Enabled" newline setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Interrupt enable set/clear bit 19" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Interrupt enable set/clear bit 18" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Interrupt enable set/clear bit 17" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Interrupt enable set/clear bit 16" "Disabled,Enabled" newline setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Interrupt enable set/clear bit 15" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Interrupt enable set/clear bit 14" "Disabled,Enabled" setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Interrupt enable set/clear bit 13" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Interrupt enable set/clear bit 12" "Disabled,Enabled" newline setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Interrupt enable set/clear bit 11" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Interrupt enable set/clear bit 10" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Interrupt enable set/clear bit 9" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Interrupt enable set/clear bit 8" "Disabled,Enabled" newline setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Interrupt enable set/clear bit 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Interrupt enable set/clear bit 6" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Interrupt enable set/clear bit 5" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Interrupt enable set/clear bit 4" "Disabled,Enabled" newline setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Interrupt enable set/clear bit 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Interrupt enable set/clear bit 2" "Disabled,Enabled" setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Interrupt enable set/clear bit 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Interrupt enable set/clear bit 0" "Disabled,Enabled" newline group.long 0x1C++0x0F line.long 0x00 "EXC1,Exception Control Register 1" bitfld.long 0x00 24. " APCNT_OVRFL_ENA ,APCNT Overflow Enable" "Disabled,Enabled" bitfld.long 0x00 16. " APCNT_UNDRFL_ENA ,APCNT Underflow Enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " PRGM_OVRFL_ENA ,Program Overflow Enable" "Disabled,Enabled" bitfld.long 0x00 2. " APCNT_OVRFL_ENA_PRY ,APCNT_Ovrfl_Ena Priority" "Level 2,Level 1" newline bitfld.long 0x00 1. " APCNT_UNDRFL_ENA_PRY ,APCNT_Undrfl_Ena Priority" "Level 2,Level 1" bitfld.long 0x00 0. " PRGM_OVRFL_ENA_PRY ,Prgm_Ovrfl_Ena Priority" "Level 2,Level 1" line.long 0x04 "EXC2,Exception Control Register 2" eventfld.long 0x04 8. " DEBUG_STATUS_FLG ,Debug_Status Flag" "No NHET,NHET" eventfld.long 0x04 2. " APCNT_OVRFL_FLG ,APCNT Overflow Flag" "Not occurred,Occurred" newline eventfld.long 0x04 1. " APCNT_UNDRFL_FLG ,APCNT Underflow Flag" "Not occurred,Occurred" eventfld.long 0x04 0. " PRGM_OVERFL_FLG ,Program Overflow Flag" "Not occurred,Occurred" newline line.long 0x08 "PRY,Interrupt Priority Register" bitfld.long 0x08 31. " HETPRY[31] ,HET Priority Level Bit[31]" "Level 2,Level 1" bitfld.long 0x08 30. " [30] ,HET Priority Level Bit[30]" "Level 2,Level 1" bitfld.long 0x08 29. " [29] ,HET Priority Level Bit[29]" "Level 2,Level 1" newline bitfld.long 0x08 28. " [28] ,HET Priority Level Bit[28]" "Level 2,Level 1" bitfld.long 0x08 27. " [27] ,HET Priority Level Bit[27]" "Level 2,Level 1" bitfld.long 0x08 26. " [26] ,HET Priority Level Bit[26]" "Level 2,Level 1" newline bitfld.long 0x08 25. " [25] ,HET Priority Level Bit[25]" "Level 2,Level 1" bitfld.long 0x08 24. " [24] ,HET Priority Level Bit[24]" "Level 2,Level 1" bitfld.long 0x08 23. " [23] ,HET Priority Level Bit[23]" "Level 2,Level 1" newline bitfld.long 0x08 22. " [22] ,HET Priority Level Bit[22]" "Level 2,Level 1" bitfld.long 0x08 21. " [21] ,HET Priority Level Bit[21]" "Level 2,Level 1" bitfld.long 0x08 20. " [20] ,HET Priority Level Bit[20]" "Level 2,Level 1" newline bitfld.long 0x08 19. " [19] ,HET Priority Level Bit[19]" "Level 2,Level 1" bitfld.long 0x08 18. " [18] ,HET Priority Level Bit[18]" "Level 2,Level 1" bitfld.long 0x08 17. " [17] ,HET Priority Level Bit[17]" "Level 2,Level 1" newline bitfld.long 0x08 16. " [16] ,HET Priority Level Bit[16]" "Level 2,Level 1" bitfld.long 0x08 15. " [15] ,HET Priority Level Bit[15]" "Level 2,Level 1" bitfld.long 0x08 14. " [14] ,HET Priority Level Bit[14]" "Level 2,Level 1" newline bitfld.long 0x08 13. " [13] ,HET Priority Level Bit[13]" "Level 2,Level 1" bitfld.long 0x08 12. " [12] ,HET Priority Level Bit[12]" "Level 2,Level 1" bitfld.long 0x08 11. " [11] ,HET Priority Level Bit[11]" "Level 2,Level 1" newline bitfld.long 0x08 10. " [10] ,HET Priority Level Bit[10]" "Level 2,Level 1" bitfld.long 0x08 9. " [9] ,HET Priority Level Bit[9]" "Level 2,Level 1" bitfld.long 0x08 8. " [8] ,HET Priority Level Bit[8]" "Level 2,Level 1" newline bitfld.long 0x08 7. " [7] ,HET Priority Level Bit[7]" "Level 2,Level 1" bitfld.long 0x08 6. " [6] ,HET Priority Level Bit[6]" "Level 2,Level 1" bitfld.long 0x08 5. " [5] ,HET Priority Level Bit[5]" "Level 2,Level 1" newline bitfld.long 0x08 4. " [4] ,HET Priority Level Bit[4]" "Level 2,Level 1" bitfld.long 0x08 3. " [3] ,HET Priority Level Bit[3]" "Level 2,Level 1" bitfld.long 0x08 2. " [2] ,HET Priority Level Bit[2]" "Level 2,Level 1" newline bitfld.long 0x08 1. " [1] ,HET Priority Level Bit[1]" "Level 2,Level 1" bitfld.long 0x08 0. " HETPRY[0] ,HET Priority Level Bit[0]" "Level 2,Level 1" line.long 0x0C "FLG,Interrupt Flag Register" eventfld.long 0x0C 31. " HETFLAG[31] ,Interrupt Flag Register Bit[31]" "No interrupt,Interrupt" eventfld.long 0x0C 30. " [30] ,Interrupt Flag Register Bit[30]" "No interrupt,Interrupt" newline eventfld.long 0x0C 29. " [29] ,Interrupt Flag Register Bit[29]" "No interrupt,Interrupt" eventfld.long 0x0C 28. " [28] ,Interrupt Flag Register Bit[28]" "No interrupt,Interrupt" newline eventfld.long 0x0C 27. " [27] ,Interrupt Flag Register Bit[27]" "No interrupt,Interrupt" eventfld.long 0x0C 26. " [26] ,Interrupt Flag Register Bit[26]" "No interrupt,Interrupt" newline eventfld.long 0x0C 25. " [25] ,Interrupt Flag Register Bit[25]" "No interrupt,Interrupt" eventfld.long 0x0C 24. " [24] ,Interrupt Flag Register Bit[24]" "No interrupt,Interrupt" newline eventfld.long 0x0C 23. " [23] ,Interrupt Flag Register Bit[23]" "No interrupt,Interrupt" eventfld.long 0x0C 22. " [22] ,Interrupt Flag Register Bit[22]" "No interrupt,Interrupt" newline eventfld.long 0x0C 21. " [21] ,Interrupt Flag Register Bit[21]" "No interrupt,Interrupt" eventfld.long 0x0C 20. " [20] ,Interrupt Flag Register Bit[20]" "No interrupt,Interrupt" newline eventfld.long 0x0C 19. " [19] ,Interrupt Flag Register Bit[19]" "No interrupt,Interrupt" eventfld.long 0x0C 18. " [18] ,Interrupt Flag Register Bit[18]" "No interrupt,Interrupt" newline eventfld.long 0x0C 17. " [17] ,Interrupt Flag Register Bit[17]" "No interrupt,Interrupt" eventfld.long 0x0C 16. " [16] ,Interrupt Flag Register Bit[16]" "No interrupt,Interrupt" newline eventfld.long 0x0C 15. " [15] ,Interrupt Flag Register Bit[15]" "No interrupt,Interrupt" eventfld.long 0x0C 14. " [14] ,Interrupt Flag Register Bit[14]" "No interrupt,Interrupt" newline eventfld.long 0x0C 13. " [13] ,Interrupt Flag Register Bit[13]" "No interrupt,Interrupt" eventfld.long 0x0C 12. " [12] ,Interrupt Flag Register Bit[12]" "No interrupt,Interrupt" newline eventfld.long 0x0C 11. " [11] ,Interrupt Flag Register Bit[11]" "No interrupt,Interrupt" eventfld.long 0x0C 10. " [10] ,Interrupt Flag Register Bit[10]" "No interrupt,Interrupt" newline eventfld.long 0x0C 9. " [9] ,Interrupt Flag Register Bit[9]" "No interrupt,Interrupt" eventfld.long 0x0C 8. " [8] ,Interrupt Flag Register Bit[8]" "No interrupt,Interrupt" newline eventfld.long 0x0C 7. " [7] ,Interrupt Flag Register Bit[7]" "No interrupt,Interrupt" eventfld.long 0x0C 6. " [6] ,Interrupt Flag Register Bit[6]" "No interrupt,Interrupt" newline eventfld.long 0x0C 5. " [5] ,Interrupt Flag Register Bit[5]" "No interrupt,Interrupt" eventfld.long 0x0C 4. " [4] ,Interrupt Flag Register Bit[4]" "No interrupt,Interrupt" newline eventfld.long 0x0C 3. " [3] ,Interrupt Flag Register Bit[3]" "No interrupt,Interrupt" eventfld.long 0x0C 2. " [2] ,Interrupt Flag Register Bit[2]" "No interrupt,Interrupt" newline eventfld.long 0x0C 1. " [1] ,Interrupt Flag Register Bit[1]" "No interrupt,Interrupt" eventfld.long 0x0C 0. " [0] ,Interrupt Flag Register Bit[0]" "No interrupt,Interrupt" sif (CPU()==("TMS570LS2124-PGE")||CPU()==("TMS570LS2124-ZWT")||CPU()==("TMS570LS2134-PGE")||CPU()==("TMS570LS2134-ZWT")||CPU()==("TMS570LS3134-PGE")||CPU()==("TMS570LS3134-ZWT")||CPU()==("TMS570LS3135-PGE")||CPU()==("TMS570LS3135-ZWT")||CPU()==("TMS570LS3136")||CPU()==("TMS570LS3137-PGE")||CPU()==("TMS570LS3137-ZWT")||CPU()==("TMS570LS30336")||CPU()==("TMS570LS2126")||CPU()==("TMS570LS2127")||CPU()==("TMS570LS2136")||CPU()==("TMS570LS2137")||CPU()==("TMS570LS2125-PGE")||CPU()==("TMS570LS2125-ZWT")||CPU()==("TMS570LS2135-PGE")||CPU()==("TMS570LS2135-ZWT")||CPU()==("RM48L950")||cpu()=="RM48L952-PGE"||cpu()=="RM48L952-ZWT"||CPU()=="RM48L950-PGE"||CPU()=="RM48L950-ZWT"||CPU()=="RM48L940-ZWT"||CPU()=="RM48L940-PGE"||CPU()=="RM48L930-ZWT"||CPU()=="RM48L930-PGE"||CPU()=="RM48L750-ZWT"||CPU()=="RM48L750-PGE"||CPU()=="RM48L740-ZWT"||CPU()=="RM48L740-PGE"||CPU()=="RM48L730-ZWT"||CPU()=="RM48L730-PGE"||CPU()=="RM48L550-PGE"||CPU()=="RM48L540-ZWT"||CPU()=="RM48L540-PGE"||CPU()=="RM48L530-ZWT"||CPU()=="RM48L530-PGE"||CPU()=="RM46L852-PGE"||CPU()=="RM46L852-ZWT"||CPU()=="RM46L850-PGE"||CPU()=="RM46L850-ZWT"||CPU()=="RM46L840-ZWT"||CPU()=="RM46L840-PGE"||CPU()=="RM46L830-ZWT"||CPU()=="RM46L830-PGE"||CPU()=="RM46L450-ZWT"||CPU()=="RM46L450-PGE"||CPU()=="RM46L440-ZWT"||CPU()=="RM46L440-PGE"||CPU()=="RM46L430-ZWT"||CPU()=="RM46L430-PGE"||CPU()=="RM42L432"||CPU()=="TMS570LC4357"||CPU()==("TMS570LS0332")||CPU()==("TMS570LS0432")||CPUIS("TMS570LS1114*")||CPUIS("TMS570LS1115*")||CPUIS("TMS570LS1224*")||CPUIS("TMS570LS1225*")||CPUIS("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")) group.long 0x2C++0x3 line.long 0x00 "HETAND,And Share Control Register" bitfld.long 0x00 15. " AND_SHARE[31/30] ,And share 31/30" "Not shared,Shared" bitfld.long 0x00 14. " [29/28] ,And share 29/28" "Not shared,Shared" newline bitfld.long 0x00 13. " [27/26] ,And share 27/26" "Not shared,Shared" bitfld.long 0x00 12. " [25/24] ,And share 25/24" "Not shared,Shared" newline bitfld.long 0x00 11. " [23/22] ,And share 23/22" "Not shared,Shared" bitfld.long 0x00 10. " [21/20] ,And share 21/20" "Not shared,Shared" newline bitfld.long 0x00 9. " [19/18] ,And share 19/18" "Not shared,Shared" bitfld.long 0x00 8. " [17/16] ,And share 17/16" "Not shared,Shared" newline bitfld.long 0x00 7. " [15/14] ,And share 15/14" "Not shared,Shared" bitfld.long 0x00 6. " [13/12] ,And share 13/12" "Not shared,Shared" newline bitfld.long 0x00 5. " [11/10] ,And share 11/10" "Not shared,Shared" bitfld.long 0x00 4. " [9/8] ,And share 9/8" "Not shared,Shared" newline bitfld.long 0x00 3. " [7/6] ,And share 7/6" "Not shared,Shared" bitfld.long 0x00 2. " [5/4] ,And share 5/4" "Not shared,Shared" newline bitfld.long 0x00 1. " [3/2] ,And share 3/2" "Not shared,Shared" bitfld.long 0x00 0. " [1/0] ,And share 1/0" "Not shared,Shared" endif group.long 0x34++0x07 line.long 0x0 "HRSH,HR Share Control Register" bitfld.long 0x00 15. " HR_SHARE[31/30] ,HR Share 31/30" "Not shared,Shared" bitfld.long 0x00 14. " [29/28] ,HR Share 29/28" "Not shared,Shared" newline bitfld.long 0x00 13. " [27/26] ,HR Share 27/26" "Not shared,Shared" bitfld.long 0x00 12. " [25/24] ,HR Share 25/24" "Not shared,Shared" newline bitfld.long 0x00 11. " [23/22] ,HR Share 23/22" "Not shared,Shared" bitfld.long 0x00 10. " [21/20] ,HR Share 21/20" "Not shared,Shared" newline bitfld.long 0x00 9. " [19/18] ,HR Share 19/18" "Not shared,Shared" bitfld.long 0x00 8. " [17/16] ,HR Share 17/16" "Not shared,Shared" newline bitfld.long 0x00 7. " [15/14] ,HR Share 15/14" "Not shared,Shared" bitfld.long 0x00 6. " [13/12] ,HR Share 13/12" "Not shared,Shared" newline bitfld.long 0x00 5. " [11/10] ,HR Share 11/10" "Not shared,Shared" bitfld.long 0x00 4. " [9/8] ,HR Share 9/8" "Not shared,Shared" newline bitfld.long 0x00 3. " [7/6] ,HR Share 7/6" "Not shared,Shared" bitfld.long 0x00 2. " [5/4] ,HR Share 5/4" "Not shared,Shared" newline bitfld.long 0x00 1. " [3/2] ,HR Share 3/2" "Not shared,Shared" bitfld.long 0x00 0. " [1/0] ,HR Share 1/0" "Not shared,Shared" line.long 0x04 "XOR,HR XOR Control Register" bitfld.long 0x04 15. " HR_XOR_SHARE[31/30] ,HR XOR-Share 31/30" "Not XOR-shared,XOR-shared" bitfld.long 0x04 14. " [29/28] ,HR XOR-Share 29/28" "Not XOR-shared,XOR-shared" newline bitfld.long 0x04 13. " [27/26] ,HR XOR-Share 27/26" "Not XOR-shared,XOR-shared" bitfld.long 0x04 12. " [25/24] ,HR XOR-Share 25/24" "Not XOR-shared,XOR-shared" newline bitfld.long 0x04 11. " [23/22] ,HR XOR-Share 23/22" "Not XOR-shared,XOR-shared" bitfld.long 0x04 10. " [21/20] ,HR XOR-Share 21/20" "Not XOR-shared,XOR-shared" newline bitfld.long 0x04 9. " [19/18] ,HR XOR-Share 19/18" "Not XOR-shared,XOR-shared" bitfld.long 0x04 8. " [17/16] ,HR XOR-Share 17/16" "Not XOR-shared,XOR-shared" newline bitfld.long 0x04 7. " [15/14] ,HR XOR-Share 15/14" "Not XOR-shared,XOR-shared" bitfld.long 0x04 6. " [13/12] ,HR XOR-Share 13/12" "Not XOR-shared,XOR-shared" newline bitfld.long 0x04 5. " [11/10] ,HR XOR-Share 11/10" "Not XOR-shared,XOR-shared" bitfld.long 0x04 4. " [9/8] ,HR XOR-Share 9/8" "Not XOR-shared,XOR-shared" newline bitfld.long 0x04 3. " [7/6] ,HR XOR-Share 7/6" "Not XOR-shared,XOR-shared" bitfld.long 0x04 2. " [5/4] ,HR XOR-Share 5/4" "Not XOR-shared,XOR-shared" newline bitfld.long 0x04 1. " [3/2] ,HR XOR-Share 3/2" "Not XOR-shared,XOR-shared" bitfld.long 0x04 0. " [1/0] ,HR XOR-Share 1/0" "Not XOR-shared,XOR-shared" group.long 0x3C++0x03 line.long 0x00 "REQEN_SETCLR,Request Enable Set/Clear Register" setclrfld.long 0x00 7. 0x00 7. 0x04 7. " REQENA_SET/CLR[7] ,Request enable set/clear bit [7]" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Request enable set/clear bit [6]" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Request enable set/clear bit [5]" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Request enable set/clear bit [4]" "Disabled,Enabled" newline setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Request enable set/clear bit [3]" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Request enable set/clear bit [2]" "Disabled,Enabled" setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Request enable set/clear bit [1]" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Request enable set/clear bit [0]" "Disabled,Enabled" sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS0232")) group.long 0x44++0x3 line.long 0x00 "REQDS,Request Destination Select Register" bitfld.long 0x00 23. " TDBS[7] ,HTU/DMA or Both Select Bit[7]" "HTU,Both" bitfld.long 0x00 22. " [6] ,HTU/DMA or Both Select Bit[6]" "HTU,Both" bitfld.long 0x00 21. " [5] ,HTU/DMA or Both Select Bit[5]" "HTU,Both" bitfld.long 0x00 20. " [4] ,HTU/DMA or Both Select Bit[4]" "HTU,Both" newline bitfld.long 0x00 19. " [3] ,HTU/DMA or Both Select Bit[3]" "HTU,Both" bitfld.long 0x00 18. " [2] ,HTU/DMA or Both Select Bit[2]" "HTU,Both" bitfld.long 0x00 17. " [1] ,HTU/DMA or Both Select Bit[1]" "HTU,Both" bitfld.long 0x00 16. " [0] ,HTU/DMA or Both Select Bit[0]" "HTU,Both" newline bitfld.long 0x00 7. " TDS[7] ,HTU or DMA Select Bit[7]" "HTU,DMA" bitfld.long 0x00 6. " TDS[6] ,HTU or DMA Select Bit[6]" "HTU,DMA" bitfld.long 0x00 5. " TDS[5] ,HTU or DMA Select Bit[5]" "HTU,DMA" bitfld.long 0x00 4. " TDS[4] ,HTU or DMA Select Bit[4]" "HTU,DMA" newline bitfld.long 0x00 3. " TDS[3] ,HTU or DMA Select Bit[3]" "HTU,DMA" bitfld.long 0x00 2. " TDS[2] ,HTU or DMA Select Bit[2]" "HTU,DMA" bitfld.long 0x00 1. " TDS[1] ,HTU or DMA Select Bit[1]" "HTU,DMA" bitfld.long 0x00 0. " TDS[0] ,HTU or DMA Select Bit[0]" "HTU,DMA" endif group.long 0x4C++0x3 line.long 0x00 "DIR,Direction Register" bitfld.long 0x00 31. " HET_DIR[31] ,Input/Output Direction Pin 31" "Input,Output" bitfld.long 0x00 30. " [30] ,Input/Output Direction Pin 30" "Input,Output" bitfld.long 0x00 29. " [29] ,Input/Output Direction Pin 29" "Input,Output" newline bitfld.long 0x00 28. " [28] ,Input/Output Direction Pin 28" "Input,Output" bitfld.long 0x00 27. " [27] ,Input/Output Direction Pin 27" "Input,Output" bitfld.long 0x00 26. " [26] ,Input/Output Direction Pin 26" "Input,Output" newline bitfld.long 0x00 25. " [25] ,Input/Output Direction Pin 25" "Input,Output" bitfld.long 0x00 24. " [24] ,Input/Output Direction Pin 24" "Input,Output" bitfld.long 0x00 23. " [23] ,Input/Output Direction Pin 23" "Input,Output" newline bitfld.long 0x00 22. " [22] ,Input/Output Direction Pin 22" "Input,Output" bitfld.long 0x00 21. " [21] ,Input/Output Direction Pin 21" "Input,Output" bitfld.long 0x00 20. " [20] ,Input/Output Direction Pin 20" "Input,Output" newline bitfld.long 0x00 19. " [19] ,Input/Output Direction Pin 19" "Input,Output" bitfld.long 0x00 18. " [18] ,Input/Output Direction Pin 18" "Input,Output" bitfld.long 0x00 17. " [17] ,Input/Output Direction Pin 17" "Input,Output" newline bitfld.long 0x00 16. " [16] ,Input/Output Direction Pin 16" "Input,Output" bitfld.long 0x00 15. " [15] ,Input/Output Direction Pin 15" "Input,Output" bitfld.long 0x00 14. " [14] ,Input/Output Direction Pin 14" "Input,Output" newline bitfld.long 0x00 13. " [13] ,Input/Output Direction Pin 13" "Input,Output" bitfld.long 0x00 12. " [12] ,Input/Output Direction Pin 12" "Input,Output" bitfld.long 0x00 11. " [11] ,Input/Output Direction Pin 11" "Input,Output" newline bitfld.long 0x00 10. " [10] ,Input/Output Direction Pin 10" "Input,Output" bitfld.long 0x00 9. " [9] ,Input/Output Direction Pin 9" "Input,Output" bitfld.long 0x00 8. " [8] ,Input/Output Direction Pin 8" "Input,Output" newline bitfld.long 0x00 7. " [7] ,Input/Output Direction Pin 7" "Input,Output" bitfld.long 0x00 6. " [6] ,Input/Output Direction Pin 6" "Input,Output" bitfld.long 0x00 5. " [5] ,Input/Output Direction Pin 5" "Input,Output" newline bitfld.long 0x00 4. " [4] ,Input/Output Direction Pin 4" "Input,Output" bitfld.long 0x00 3. " [3] ,Input/Output Direction Pin 3" "Input,Output" bitfld.long 0x00 2. " [2] ,Input/Output Direction Pin 2" "Input,Output" newline bitfld.long 0x00 1. " [1] ,Input/Output Direction Pin 1" "Input,Output" bitfld.long 0x00 0. " [0] ,Input/Output Direction Pin 0" "Input,Output" rgroup.long 0x50++0x3 line.long 0x00 "DIN,Input Data Register" bitfld.long 0x00 31. " HETDIN[31] ,NHET Data Input Register Pin 31" "Low,High" bitfld.long 0x00 30. " [30] ,NHET Data Input Register Pin 30" "Low,High" bitfld.long 0x00 29. " [29] ,NHET Data Input Register Pin 29" "Low,High" bitfld.long 0x00 28. " [28] ,NHET Data Input Register Pin 28" "Low,High" newline bitfld.long 0x00 27. " [27] ,NHET Data Input Register Pin 27" "Low,High" bitfld.long 0x00 26. " [26] ,NHET Data Input Register Pin 26" "Low,High" bitfld.long 0x00 25. " [25] ,NHET Data Input Register Pin 25" "Low,High" bitfld.long 0x00 24. " [24] ,NHET Data Input Register Pin 24" "Low,High" newline bitfld.long 0x00 23. " [23] ,NHET Data Input Register Pin 23" "Low,High" bitfld.long 0x00 22. " [22] ,NHET Data Input Register Pin 22" "Low,High" bitfld.long 0x00 21. " [21] ,NHET Data Input Register Pin 21" "Low,High" bitfld.long 0x00 20. " [20] ,NHET Data Input Register Pin 20" "Low,High" newline bitfld.long 0x00 19. " [19] ,NHET Data Input Register Pin 19" "Low,High" bitfld.long 0x00 18. " [18] ,NHET Data Input Register Pin 18" "Low,High" bitfld.long 0x00 17. " [17] ,NHET Data Input Register Pin 17" "Low,High" bitfld.long 0x00 16. " [16] ,NHET Data Input Register Pin 16" "Low,High" newline bitfld.long 0x00 15. " [15] ,NHET Data Input Register Pin 15" "Low,High" bitfld.long 0x00 14. " [14] ,NHET Data Input Register Pin 14" "Low,High" bitfld.long 0x00 13. " [13] ,NHET Data Input Register Pin 13" "Low,High" bitfld.long 0x00 12. " [12] ,NHET Data Input Register Pin 12" "Low,High" newline bitfld.long 0x00 11. " [11] ,NHET Data Input Register Pin 11" "Low,High" bitfld.long 0x00 10. " [10] ,NHET Data Input Register Pin 10" "Low,High" bitfld.long 0x00 9. " [9] ,NHET Data Input Register Pin 9" "Low,High" bitfld.long 0x00 8. " [8] ,NHET Data Input Register Pin 8" "Low,High" newline bitfld.long 0x00 7. " [7] ,NHET Data Input Register Pin 7" "Low,High" bitfld.long 0x00 6. " [6] ,NHET Data Input Register Pin 6" "Low,High" bitfld.long 0x00 5. " [5] ,NHET Data Input Register Pin 5" "Low,High" bitfld.long 0x00 4. " [4] ,NHET Data Input Register Pin 4" "Low,High" newline bitfld.long 0x00 3. " [3] ,NHET Data Input Register Pin 3" "Low,High" bitfld.long 0x00 2. " [2] ,NHET Data Input Register Pin 2" "Low,High" bitfld.long 0x00 1. " [1] ,NHET Data Input Register Pin 1" "Low,High" bitfld.long 0x00 0. " [0] ,NHET Data Input Register Pin 0" "Low,High" group.long 0x54++0x3 line.long 0x00 "DOUT_SET/CLR,Output Data Set/Clear Register" setclrfld.long 0x00 31. 0x04 31. 0x08 31. " HETDOUT[31] ,NHET Data Output Register Bit[31]" "Low,High" setclrfld.long 0x00 30. 0x04 30. 0x08 30. " [30] ,NHET Data Output Register Bit[30]" "Low,High" newline setclrfld.long 0x00 29. 0x04 29. 0x08 29. " [29] ,NHET Data Output Register Bit[29]" "Low,High" setclrfld.long 0x00 28. 0x04 28. 0x08 28. " [28] ,NHET Data Output Register Bit[28]" "Low,High" newline setclrfld.long 0x00 27. 0x04 27. 0x08 27. " [27] ,NHET Data Output Register Bit[27]" "Low,High" setclrfld.long 0x00 26. 0x04 26. 0x08 26. " [26] ,NHET Data Output Register Bit[26]" "Low,High" newline setclrfld.long 0x00 25. 0x04 25. 0x08 25. " [25] ,NHET Data Output Register Bit[25]" "Low,High" setclrfld.long 0x00 24. 0x04 24. 0x08 24. " [24] ,NHET Data Output Register Bit[24]" "Low,High" newline setclrfld.long 0x00 23. 0x04 23. 0x08 23. " [23] ,NHET Data Output Register Bit[23]" "Low,High" setclrfld.long 0x00 22. 0x04 22. 0x08 22. " [22] ,NHET Data Output Register Bit[22]" "Low,High" newline setclrfld.long 0x00 21. 0x04 21. 0x08 21. " [21] ,NHET Data Output Register Bit[21]" "Low,High" setclrfld.long 0x00 20. 0x04 20. 0x08 20. " [20] ,NHET Data Output Register Bit[20]" "Low,High" newline setclrfld.long 0x00 19. 0x04 19. 0x08 19. " [19] ,NHET Data Output Register Bit[19]" "Low,High" setclrfld.long 0x00 18. 0x04 18. 0x08 18. " [18] ,NHET Data Output Register Bit[18]" "Low,High" newline setclrfld.long 0x00 17. 0x04 17. 0x08 17. " [17] ,NHET Data Output Register Bit[17]" "Low,High" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " [16] ,NHET Data Output Register Bit[16]" "Low,High" newline setclrfld.long 0x00 15. 0x04 15. 0x08 15. " [15] ,NHET Data Output Register Bit[15]" "Low,High" setclrfld.long 0x00 14. 0x04 14. 0x08 14. " [14] ,NHET Data Output Register Bit[14]" "Low,High" newline setclrfld.long 0x00 13. 0x04 13. 0x08 13. " [13] ,NHET Data Output Register Bit[13]" "Low,High" setclrfld.long 0x00 12. 0x04 12. 0x08 12. " [12] ,NHET Data Output Register Bit[12]" "Low,High" newline setclrfld.long 0x00 11. 0x04 11. 0x08 11. " [11] ,NHET Data Output Register Bit[11]" "Low,High" setclrfld.long 0x00 10. 0x04 10. 0x08 10. " [10] ,NHET Data Output Register Bit[10]" "Low,High" newline setclrfld.long 0x00 9. 0x04 9. 0x08 9. " [9] ,NHET Data Output Register Bit[9]" "Low,High" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " [8] ,NHET Data Output Register Bit[8]" "Low,High" newline setclrfld.long 0x00 7. 0x04 7. 0x08 7. " [7] ,NHET Data Output Register Bit[7]" "Low,High" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " [6] ,NHET Data Output Register Bit[6]" "Low,High" newline setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [5] ,NHET Data Output Register Bit[5]" "Low,High" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [4] ,NHET Data Output Register Bit[4]" "Low,High" newline setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [3] ,NHET Data Output Register Bit[3]" "Low,High" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,NHET Data Output Register Bit[2]" "Low,High" newline setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,NHET Data Output Register Bit[1]" "Low,High" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,NHET Data Output Register Bit[0]" "Low,High" group.long 0x60++0x0B line.long 0x00 "PDR,Open Drain Register" bitfld.long 0x00 31. " HETPDR[31] ,NHET Open Drain Bit[31]" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,NHET Open Drain Bit[30]" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,NHET Open Drain Bit[29]" "Disabled,Enabled" newline bitfld.long 0x00 28. " [28] ,NHET Open Drain Bit[28]" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,NHET Open Drain Bit[27]" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,NHET Open Drain Bit[26]" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,NHET Open Drain Bit[25]" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,NHET Open Drain Bit[24]" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,NHET Open Drain Bit[23]" "Disabled,Enabled" newline bitfld.long 0x00 22. " [22] ,NHET Open Drain Bit[22]" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,NHET Open Drain Bit[21]" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,NHET Open Drain Bit[20]" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,NHET Open Drain Bit[19]" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,NHET Open Drain Bit[18]" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,NHET Open Drain Bit[17]" "Disabled,Enabled" newline bitfld.long 0x00 16. " [16] ,NHET Open Drain Bit[16]" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,NHET Open Drain Bit[15]" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,NHET Open Drain Bit[14]" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,NHET Open Drain Bit[13]" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,NHET Open Drain Bit[12]" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,NHET Open Drain Bit[11]" "Disabled,Enabled" newline bitfld.long 0x00 10. " [10] ,NHET Open Drain Bit[10]" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,NHET Open Drain Bit[9]" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,NHET Open Drain Bit[8]" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,NHET Open Drain Bit[7]" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,NHET Open Drain Bit[6]" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,NHET Open Drain Bit[5]" "Disabled,Enabled" newline bitfld.long 0x00 4. " [4] ,NHET Open Drain Bit[4]" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,NHET Open Drain Bit[3]" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,NHET Open Drain Bit[2]" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,NHET Open Drain Bit[1]" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,NHET Open Drain Bit[0]" "Disabled,Enabled" line.long 0x04 "PULDIS,Pull Disable Register" bitfld.long 0x04 31. " HETPULDIS[31] ,NHET Pull Disable Bit[31]" "No,Yes" bitfld.long 0x04 30. " [30] ,NHET Pull Disable Bit[30]" "No,Yes" bitfld.long 0x04 29. " [29] ,NHET Pull Disable Bit[29]" "No,Yes" newline bitfld.long 0x04 28. " [28] ,NHET Pull Disable Bit[28]" "No,Yes" bitfld.long 0x04 27. " [27] ,NHET Pull Disable Bit[27]" "No,Yes" bitfld.long 0x04 26. " [26] ,NHET Pull Disable Bit[26]" "No,Yes" newline bitfld.long 0x04 25. " [25] ,NHET Pull Disable Bit[25]" "No,Yes" bitfld.long 0x04 24. " [24] ,NHET Pull Disable Bit[24]" "No,Yes" bitfld.long 0x04 23. " [23] ,NHET Pull Disable Bit[23]" "No,Yes" newline bitfld.long 0x04 22. " [22] ,NHET Pull Disable Bit[22]" "No,Yes" bitfld.long 0x04 21. " [21] ,NHET Pull Disable Bit[21]" "No,Yes" bitfld.long 0x04 20. " [20] ,NHET Pull Disable Bit[20]" "No,Yes" newline bitfld.long 0x04 19. " [19] ,NHET Pull Disable Bit[19]" "No,Yes" bitfld.long 0x04 18. " [18] ,NHET Pull Disable Bit[18]" "No,Yes" bitfld.long 0x04 17. " [17] ,NHET Pull Disable Bit[17]" "No,Yes" newline bitfld.long 0x04 16. " [16] ,NHET Pull Disable Bit[16]" "No,Yes" bitfld.long 0x04 15. " [15] ,NHET Pull Disable Bit[15]" "No,Yes" bitfld.long 0x04 14. " [14] ,NHET Pull Disable Bit[14]" "No,Yes" newline bitfld.long 0x04 13. " [13] ,NHET Pull Disable Bit[13]" "No,Yes" bitfld.long 0x04 12. " [12] ,NHET Pull Disable Bit[12]" "No,Yes" bitfld.long 0x04 11. " [11] ,NHET Pull Disable Bit[11]" "No,Yes" newline bitfld.long 0x04 10. " [10] ,NHET Pull Disable Bit[10]" "No,Yes" bitfld.long 0x04 9. " [9] ,NHET Pull Disable Bit[9]" "No,Yes" bitfld.long 0x04 8. " [8] ,NHET Pull Disable Bit[8]" "No,Yes" newline bitfld.long 0x04 7. " [7] ,NHET Pull Disable Bit[7]" "No,Yes" bitfld.long 0x04 6. " [6] ,NHET Pull Disable Bit[6]" "No,Yes" bitfld.long 0x04 5. " [5] ,NHET Pull Disable Bit[5]" "No,Yes" newline bitfld.long 0x04 4. " [4] ,NHET Pull Disable Bit[4]" "No,Yes" bitfld.long 0x04 3. " [3] ,NHET Pull Disable Bit[3]" "No,Yes" bitfld.long 0x04 2. " [2] ,NHET Pull Disable Bit[2]" "No,Yes" newline bitfld.long 0x04 1. " [1] ,NHET Pull Disable Bit[1]" "No,Yes" bitfld.long 0x04 0. " [0] ,NHET Pull Disable Bit[0]" "No,Yes" line.long 0x08 "PSL,Pull Select Register" bitfld.long 0x08 31. " HETPSL[31] ,NHET Pull Select Bit[31]" "Pull down,Pull up" bitfld.long 0x08 30. " [30] ,NHET Pull Select Bit[30]" "Pull down,Pull up" bitfld.long 0x08 29. " [29] ,NHET Pull Select Bit[29]" "Pull down,Pull up" newline bitfld.long 0x08 28. " [28] ,NHET Pull Select Bit[28]" "Pull down,Pull up" bitfld.long 0x08 27. " [27] ,NHET Pull Select Bit[27]" "Pull down,Pull up" bitfld.long 0x08 26. " [26] ,NHET Pull Select Bit[26]" "Pull down,Pull up" newline bitfld.long 0x08 25. " [25] ,NHET Pull Select Bit[25]" "Pull down,Pull up" bitfld.long 0x08 24. " [24] ,NHET Pull Select Bit[24]" "Pull down,Pull up" bitfld.long 0x08 23. " [23] ,NHET Pull Select Bit[23]" "Pull down,Pull up" newline bitfld.long 0x08 22. " [22] ,NHET Pull Select Bit[22]" "Pull down,Pull up" bitfld.long 0x08 21. " [21] ,NHET Pull Select Bit[21]" "Pull down,Pull up" bitfld.long 0x08 20. " [20] ,NHET Pull Select Bit[20]" "Pull down,Pull up" newline bitfld.long 0x08 19. " [19] ,NHET Pull Select Bit[19]" "Pull down,Pull up" bitfld.long 0x08 18. " [18] ,NHET Pull Select Bit[18]" "Pull down,Pull up" bitfld.long 0x08 17. " [17] ,NHET Pull Select Bit[17]" "Pull down,Pull up" newline bitfld.long 0x08 16. " [16] ,NHET Pull Select Bit[16]" "Pull down,Pull up" bitfld.long 0x08 15. " [15] ,NHET Pull Select Bit[15]" "Pull down,Pull up" bitfld.long 0x08 14. " [14] ,NHET Pull Select Bit[14]" "Pull down,Pull up" newline bitfld.long 0x08 13. " [13] ,NHET Pull Select Bit[13]" "Pull down,Pull up" bitfld.long 0x08 12. " [12] ,NHET Pull Select Bit[12]" "Pull down,Pull up" bitfld.long 0x08 11. " [11] ,NHET Pull Select Bit[11]" "Pull down,Pull up" newline bitfld.long 0x08 10. " [10] ,NHET Pull Select Bit[10]" "Pull down,Pull up" bitfld.long 0x08 9. " [9] ,NHET Pull Select Bit[9]" "Pull down,Pull up" bitfld.long 0x08 8. " [8] ,NHET Pull Select Bit[8]" "Pull down,Pull up" newline bitfld.long 0x08 7. " [7] ,NHET Pull Select Bit[7]" "Pull down,Pull up" bitfld.long 0x08 6. " [6] ,NHET Pull Select Bit[6]" "Pull down,Pull up" bitfld.long 0x08 5. " [5] ,NHET Pull Select Bit[5]" "Pull down,Pull up" newline bitfld.long 0x08 4. " [4] ,NHET Pull Select Bit[4]" "Pull down,Pull up" bitfld.long 0x08 3. " [3] ,NHET Pull Select Bit[3]" "Pull down,Pull up" bitfld.long 0x08 2. " [2] ,NHET Pull Select Bit[2]" "Pull down,Pull up" newline bitfld.long 0x08 1. " [1] ,NHET Pull Select Bit[1]" "Pull down,Pull up" bitfld.long 0x08 0. " [0] ,NHET Pull Select Bit[0]" "Pull down,Pull up" group.long 0x74++0x3 line.long 0x0 "PCR,Parity Control Register" bitfld.long 0x00 8. " TEST ,TEST" "Not mapped,Mapped" bitfld.long 0x00 0.--3. " PARITY_ENA ,Enable / Disable Parity Checking" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" rgroup.long 0x78++0x3 line.long 0x0 "PAR,Parity Address Register" hexmask.long.word 0x00 2.--12. 0x4 " PAOFF ,Parity Error Address Offset" group.long 0x7C++0x0B line.long 0x0 "PPR,Parity Pin Register" bitfld.long 0x00 31. " HETPPR[31] ,NHET Parity Pin Select Bit[31]" "Low,High" bitfld.long 0x00 30. " [30] ,NHET Parity Pin Select Bit[30]" "Low,High" bitfld.long 0x00 29. " [29] ,NHET Parity Pin Select Bit[29]" "Low,High" bitfld.long 0x00 28. " [28] ,NHET Parity Pin Select Bit[28]" "Low,High" newline bitfld.long 0x00 27. " [27] ,NHET Parity Pin Select Bit[27]" "Low,High" bitfld.long 0x00 26. " [26] ,NHET Parity Pin Select Bit[26]" "Low,High" bitfld.long 0x00 25. " [25] ,NHET Parity Pin Select Bit[25]" "Low,High" bitfld.long 0x00 24. " [24] ,NHET Parity Pin Select Bit[24]" "Low,High" newline bitfld.long 0x00 23. " [23] ,NHET Parity Pin Select Bit[23]" "Low,High" bitfld.long 0x00 22. " [22] ,NHET Parity Pin Select Bit[22]" "Low,High" bitfld.long 0x00 21. " [21] ,NHET Parity Pin Select Bit[21]" "Low,High" bitfld.long 0x00 20. " [20] ,NHET Parity Pin Select Bit[20]" "Low,High" newline bitfld.long 0x00 19. " [19] ,NHET Parity Pin Select Bit[19]" "Low,High" bitfld.long 0x00 18. " [18] ,NHET Parity Pin Select Bit[18]" "Low,High" bitfld.long 0x00 17. " [17] ,NHET Parity Pin Select Bit[17]" "Low,High" bitfld.long 0x00 16. " [16] ,NHET Parity Pin Select Bit[16]" "Low,High" newline bitfld.long 0x00 15. " [15] ,NHET Parity Pin Select Bit[15]" "Low,High" bitfld.long 0x00 14. " [14] ,NHET Parity Pin Select Bit[14]" "Low,High" bitfld.long 0x00 13. " [13] ,NHET Parity Pin Select Bit[13]" "Low,High" bitfld.long 0x00 12. " [12] ,NHET Parity Pin Select Bit[12]" "Low,High" newline bitfld.long 0x00 11. " [11] ,NHET Parity Pin Select Bit[11]" "Low,High" bitfld.long 0x00 10. " [10] ,NHET Parity Pin Select Bit[10]" "Low,High" bitfld.long 0x00 9. " [9] ,NHET Parity Pin Select Bit[9]" "Low,High" bitfld.long 0x00 8. " [8] ,NHET Parity Pin Select Bit[8]" "Low,High" newline bitfld.long 0x00 7. " [7] ,NHET Parity Pin Select Bit[7]" "Low,High" bitfld.long 0x00 6. " [6] ,NHET Parity Pin Select Bit[6]" "Low,High" bitfld.long 0x00 5. " [5] ,NHET Parity Pin Select Bit[5]" "Low,High" bitfld.long 0x00 4. " [4] ,NHET Parity Pin Select Bit[4]" "Low,High" newline bitfld.long 0x00 3. " [3] ,NHET Parity Pin Select Bit[3]" "Low,High" bitfld.long 0x00 2. " [2] ,NHET Parity Pin Select Bit[2]" "Low,High" bitfld.long 0x00 1. " [1] ,NHET Parity Pin Select Bit[1]" "Low,High" bitfld.long 0x00 0. " [0] ,NHET Parity Pin Select Bit[0]" "Low,High" line.long 0x04 "SFPRLD,Suppresion Filter Preload Register" bitfld.long 0x04 16.--17. " CCDIV ,Counter Clock Divider" "VCLK2,VCLK2/2,VCLK2/3,VCLK2/4" hexmask.long.word 0x04 0.--9. 1. " CPRLD ,Counter Preload Value" line.long 0x08 "SFENA,Suppresion Filter Enable Register" bitfld.long 0x08 31. " HETSFENA[31] ,Suppression Filter Enable Bit[31]" "Disabled,Enabled" bitfld.long 0x08 30. " [30] ,Suppression Filter Enable Bit[30]" "Disabled,Enabled" bitfld.long 0x08 29. " [29] ,Suppression Filter Enable Bit[29]" "Disabled,Enabled" newline bitfld.long 0x08 28. " [28] ,Suppression Filter Enable Bit[28]" "Disabled,Enabled" bitfld.long 0x08 27. " [27] ,Suppression Filter Enable Bit[27]" "Disabled,Enabled" bitfld.long 0x08 26. " [26] ,Suppression Filter Enable Bit[26]" "Disabled,Enabled" newline bitfld.long 0x08 25. " [25] ,Suppression Filter Enable Bit[25]" "Disabled,Enabled" bitfld.long 0x08 24. " [24] ,Suppression Filter Enable Bit[24]" "Disabled,Enabled" bitfld.long 0x08 23. " [23] ,Suppression Filter Enable Bit[23]" "Disabled,Enabled" newline bitfld.long 0x08 22. " [22] ,Suppression Filter Enable Bit[22]" "Disabled,Enabled" bitfld.long 0x08 21. " [21] ,Suppression Filter Enable Bit[21]" "Disabled,Enabled" bitfld.long 0x08 20. " [20] ,Suppression Filter Enable Bit[20]" "Disabled,Enabled" newline bitfld.long 0x08 19. " [19] ,Suppression Filter Enable Bit[19]" "Disabled,Enabled" bitfld.long 0x08 18. " [18] ,Suppression Filter Enable Bit[18]" "Disabled,Enabled" bitfld.long 0x08 17. " [17] ,Suppression Filter Enable Bit[17]" "Disabled,Enabled" newline bitfld.long 0x08 16. " [16] ,Suppression Filter Enable Bit[16]" "Disabled,Enabled" bitfld.long 0x08 15. " [15] ,Suppression Filter Enable Bit[15]" "Disabled,Enabled" bitfld.long 0x08 14. " [14] ,Suppression Filter Enable Bit[14]" "Disabled,Enabled" newline bitfld.long 0x08 13. " [13] ,Suppression Filter Enable Bit[13]" "Disabled,Enabled" bitfld.long 0x08 12. " [12] ,Suppression Filter Enable Bit[12]" "Disabled,Enabled" bitfld.long 0x08 11. " [11] ,Suppression Filter Enable Bit[11]" "Disabled,Enabled" newline bitfld.long 0x08 10. " [10] ,Suppression Filter Enable Bit[10]" "Disabled,Enabled" bitfld.long 0x08 9. " [9] ,Suppression Filter Enable Bit[9]" "Disabled,Enabled" bitfld.long 0x08 8. " [8] ,Suppression Filter Enable Bit[8]" "Disabled,Enabled" newline bitfld.long 0x08 7. " [7] ,Suppression Filter Enable Bit[7]" "Disabled,Enabled" bitfld.long 0x08 6. " [6] ,Suppression Filter Enable Bit[6]" "Disabled,Enabled" bitfld.long 0x08 5. " [5] ,Suppression Filter Enable Bit[5]" "Disabled,Enabled" newline bitfld.long 0x08 4. " [4] ,Suppression Filter Enable Bit[4]" "Disabled,Enabled" bitfld.long 0x08 3. " [3] ,Suppression Filter Enable Bit[3]" "Disabled,Enabled" bitfld.long 0x08 2. " [2] ,Suppression Filter Enable Bit[2]" "Disabled,Enabled" newline bitfld.long 0x08 1. " [1] ,Suppression Filter Enable Bit[1]" "Disabled,Enabled" bitfld.long 0x08 0. " [0] ,Suppression Filter Enable Bit[0]" "Disabled,Enabled" sif (cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!="RM46L852-PGE"&&cpu()!="RM46L852-ZWT"&&cpu()!="RM46L850-PGE"&&cpu()!="RM46L850-ZWT"&&cpu()!="RM46L840-ZWT"&&cpu()!="RM46L840-PGE"&&cpu()!="RM46L830-ZWT"&&cpu()!="RM46L830-PGE"&&cpu()!="RM46L450-ZWT"&&cpu()!="RM46L450-PGE"&&cpu()!="RM46L440-ZWT"&&cpu()!="RM46L440-PGE"&&cpu()!="RM46L430-ZWT"&&cpu()!="RM46L430-PGE"&&cpu()!="TMS570LC4357"&&cpu()!="RM48L550-ZWT"&&cpu()!="RM42L432"&&!cpuis("TMS570LS0232")&&!cpuis("TMS570LS0714*")&&!cpuis("TMS570LS0914*")) if ((per.l(ad:0xFFF7B800+0x90)&0xF00)==0xA00) group.long 0x8C++0x3 line.long 0x0 "LBPSEL,Loop Back Pair Select Register" bitfld.long 0x00 31. " LBPTYPE[15] ,Loop Back Pair Type Select Bit[15]" "Digital,Analog" bitfld.long 0x00 30. " [14] ,Loop Back Pair Type Select Bit[14]" "Digital,Analog" newline bitfld.long 0x00 29. " [13] ,Loop Back Pair Type Select Bit[13]" "Digital,Analog" bitfld.long 0x00 28. " [12] ,Loop Back Pair Type Select Bit[12]" "Digital,Analog" newline bitfld.long 0x00 27. " [11] ,Loop Back Pair Type Select Bit[11]" "Digital,Analog" bitfld.long 0x00 26. " [10] ,Loop Back Pair Type Select Bit[10]" "Digital,Analog" newline bitfld.long 0x00 25. " [9] ,Loop Back Pair Type Select Bit[9]" "Digital,Analog" bitfld.long 0x00 24. " [8] ,Loop Back Pair Type Select Bit[8]" "Digital,Analog" newline bitfld.long 0x00 23. " [7] ,Loop Back Pair Type Select Bit[7]" "Digital,Analog" bitfld.long 0x00 22. " [6] ,Loop Back Pair Type Select Bit[6]" "Digital,Analog" newline bitfld.long 0x00 21. " [5] ,Loop Back Pair Type Select Bit[5]" "Digital,Analog" bitfld.long 0x00 20. " [4] ,Loop Back Pair Type Select Bit[4]" "Digital,Analog" newline bitfld.long 0x00 19. " [3] ,Loop Back Pair Type Select Bit[3]" "Digital,Analog" bitfld.long 0x00 18. " [2] ,Loop Back Pair Type Select Bit[2]" "Digital,Analog" newline bitfld.long 0x00 17. " [1] ,Loop Back Pair Type Select Bit[1]" "Digital,Analog" bitfld.long 0x00 16. " [0] ,Loop Back Pair Type Select Bit[0]" "Digital,Analog" newline bitfld.long 0x00 15. " LBPSEL[15] ,Loop Back Pair Select Bit[15]" "Not selected,Selected" bitfld.long 0x00 14. " [14] ,Loop Back Pair Select Bit[14]" "Not selected,Selected" newline bitfld.long 0x00 13. " [13] ,Loop Back Pair Select Bit[13]" "Not selected,Selected" bitfld.long 0x00 12. " [12] ,Loop Back Pair Select Bit[12]" "Not selected,Selected" newline bitfld.long 0x00 11. " [11] ,Loop Back Pair Select Bit[11]" "Not selected,Selected" bitfld.long 0x00 10. " [10] ,Loop Back Pair Select Bit[10]" "Not selected,Selected" newline bitfld.long 0x00 9. " [9] ,Loop Back Pair Select Bit[9]" "Not selected,Selected" bitfld.long 0x00 8. " [8] ,Loop Back Pair Select Bit[8]" "Not selected,Selected" newline bitfld.long 0x00 7. " [7] ,Loop Back Pair Select Bit[7]" "Not selected,Selected" bitfld.long 0x00 6. " [6] ,Loop Back Pair Select Bit[6]" "Not selected,Selected" newline bitfld.long 0x00 5. " [5] ,Loop Back Pair Select Bit[5]" "Not selected,Selected" bitfld.long 0x00 4. " [4] ,Loop Back Pair Select Bit[4]" "Not selected,Selected" newline bitfld.long 0x00 3. " [3] ,Loop Back Pair Select Bit[3]" "Not selected,Selected" bitfld.long 0x00 2. " [2] ,Loop Back Pair Select Bit[2]" "Not selected,Selected" newline bitfld.long 0x00 1. " [1] ,Loop Back Pair Select Bit[1]" "Not selected,Selected" bitfld.long 0x00 0. " [0] ,Loop Back Pair Select Bit[0]" "Not selected,Selected" else hgroup.long 0x8C++0x3 hide.long 0x0 "LBPSEL,Loop Back Pair Select Register" endif elif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*") if ((per.l.be(ad:0xFFF7B800+0x90)&0xF0000)==0xA0000) group.long 0x8C++0x3 line.long 0x0 "LBPSEL,Loop Back Pair Select Register" bitfld.long 0x00 31. " LBPTYPE[31/30] ,Loop Back Pair Type Select Bits 31/30" "Digital,Analog" bitfld.long 0x00 30. " [29/28] ,Loop Back Pair Type Select Bits 29/28" "Digital,Analog" newline bitfld.long 0x00 29. " [27/26] ,Loop Back Pair Type Select Bits 27/26" "Digital,Analog" bitfld.long 0x00 28. " [25/24] ,Loop Back Pair Type Select Bits 25/24" "Digital,Analog" newline bitfld.long 0x00 27. " [23/22] ,Loop Back Pair Type Select Bits 23/22" "Digital,Analog" bitfld.long 0x00 26. " [21/20] ,Loop Back Pair Type Select Bits 21/20" "Digital,Analog" newline bitfld.long 0x00 25. " [19/18] ,Loop Back Pair Type Select Bits 19/18" "Digital,Analog" bitfld.long 0x00 24. " [17/16] ,Loop Back Pair Type Select Bits 17/16" "Digital,Analog" newline bitfld.long 0x00 23. " [15/14] ,Loop Back Pair Type Select Bits 15/14" "Digital,Analog" bitfld.long 0x00 22. " [13/12] ,Loop Back Pair Type Select Bits 13/12" "Digital,Analog" newline bitfld.long 0x00 21. " [11/10] ,Loop Back Pair Type Select Bits 11/10" "Digital,Analog" bitfld.long 0x00 20. " [9/8] ,Loop Back Pair Type Select Bits 9/8" "Digital,Analog" newline bitfld.long 0x00 19. " [7/6] ,Loop Back Pair Type Select Bits 7/6" "Digital,Analog" bitfld.long 0x00 18. " [5/4] ,Loop Back Pair Type Select Bits 5/4" "Digital,Analog" newline bitfld.long 0x00 17. " [3/2] ,Loop Back Pair Type Select Bits 3/2" "Digital,Analog" bitfld.long 0x00 16. " [1/0] ,Loop Back Pair Type Select Bits 1/0" "Digital,Analog" newline bitfld.long 0x00 15. " LBPSEL31/30] ,Loop Back Pair Select Bits 31/30" "Not selected,Selected" bitfld.long 0x00 14. " [29/28] ,Loop Back Pair Select Bits 29/28" "Not selected,Selected" newline bitfld.long 0x00 13. " [27/26] ,Loop Back Pair Select Bits 27/26" "Not selected,Selected" bitfld.long 0x00 12. " [25/24] ,Loop Back Pair Select Bits 25/24" "Not selected,Selected" newline bitfld.long 0x00 11. " [23/22] ,Loop Back Pair Select Bits 23/22" "Not selected,Selected" bitfld.long 0x00 10. " [21/20] ,Loop Back Pair Select Bits 21/20" "Not selected,Selected" newline bitfld.long 0x00 9. " [19/18] ,Loop Back Pair Select Bits 19/18" "Not selected,Selected" bitfld.long 0x00 8. " [17/16] ,Loop Back Pair Select Bits 17/16" "Not selected,Selected" newline bitfld.long 0x00 7. " [15/14] ,Loop Back Pair Select Bits 15/14" "Not selected,Selected" bitfld.long 0x00 6. " [13/12] ,Loop Back Pair Select Bits 13/12" "Not selected,Selected" newline bitfld.long 0x00 5. " [11/10] ,Loop Back Pair Select Bits 11/10" "Not selected,Selected" bitfld.long 0x00 4. " [9/8] ,Loop Back Pair Select Bits 9/8" "Not selected,Selected" newline bitfld.long 0x00 3. " [7/6] ,Loop Back Pair Select Bits 7/6" "Not selected,Selected" bitfld.long 0x00 2. " [5/4] ,Loop Back Pair Select Bits 5/4" "Not selected,Selected" newline bitfld.long 0x00 1. " [3/2] ,Loop Back Pair Select Bits 3/2" "Not selected,Selected" bitfld.long 0x00 0. " [1/0] ,Loop Back Pair Select Bits 1/0" "Not selected,Selected" else hgroup.long 0x8C++0x3 hide.long 0x0 "LBPSEL,Loop Back Pair Select Register" endif else if ((per.l(ad:0xFFF7B800+0x90)&0xF0000)==0xA0000) group.long 0x8C++0x3 line.long 0x0 "LBPSEL,Loop Back Pair Select Register" bitfld.long 0x00 31. " LBPTYPE[15] ,Loop Back Pair Type Select Bit[15]" "Digital,Analog" bitfld.long 0x00 30. " [14] ,Loop Back Pair Type Select Bit[14]" "Digital,Analog" newline bitfld.long 0x00 29. " [13] ,Loop Back Pair Type Select Bit[13]" "Digital,Analog" bitfld.long 0x00 28. " [12] ,Loop Back Pair Type Select Bit[12]" "Digital,Analog" newline bitfld.long 0x00 27. " [11] ,Loop Back Pair Type Select Bit[11]" "Digital,Analog" bitfld.long 0x00 26. " [10] ,Loop Back Pair Type Select Bit[10]" "Digital,Analog" newline bitfld.long 0x00 25. " [9] ,Loop Back Pair Type Select Bit[9]" "Digital,Analog" bitfld.long 0x00 24. " [8] ,Loop Back Pair Type Select Bit[8]" "Digital,Analog" newline bitfld.long 0x00 23. " [7] ,Loop Back Pair Type Select Bit[7]" "Digital,Analog" bitfld.long 0x00 22. " [6] ,Loop Back Pair Type Select Bit[6]" "Digital,Analog" newline bitfld.long 0x00 21. " [5] ,Loop Back Pair Type Select Bit[5]" "Digital,Analog" bitfld.long 0x00 20. " [4] ,Loop Back Pair Type Select Bit[4]" "Digital,Analog" newline bitfld.long 0x00 19. " [3] ,Loop Back Pair Type Select Bit[3]" "Digital,Analog" bitfld.long 0x00 18. " [2] ,Loop Back Pair Type Select Bit[2]" "Digital,Analog" newline bitfld.long 0x00 17. " [1] ,Loop Back Pair Type Select Bit[1]" "Digital,Analog" bitfld.long 0x00 16. " [0] ,Loop Back Pair Type Select Bit[0]" "Digital,Analog" newline bitfld.long 0x00 15. " LBPSEL[15] ,Loop Back Pair Select Bit[15]" "Not selected,Selected" bitfld.long 0x00 14. " [14] ,Loop Back Pair Select Bit[14]" "Not selected,Selected" newline bitfld.long 0x00 13. " [13] ,Loop Back Pair Select Bit[13]" "Not selected,Selected" bitfld.long 0x00 12. " [12] ,Loop Back Pair Select Bit[12]" "Not selected,Selected" newline bitfld.long 0x00 11. " [11] ,Loop Back Pair Select Bit[11]" "Not selected,Selected" bitfld.long 0x00 10. " [10] ,Loop Back Pair Select Bit[10]" "Not selected,Selected" newline bitfld.long 0x00 9. " [9] ,Loop Back Pair Select Bit[9]" "Not selected,Selected" bitfld.long 0x00 8. " [8] ,Loop Back Pair Select Bit[8]" "Not selected,Selected" newline bitfld.long 0x00 7. " [7] ,Loop Back Pair Select Bit[7]" "Not selected,Selected" bitfld.long 0x00 6. " [6] ,Loop Back Pair Select Bit[6]" "Not selected,Selected" newline bitfld.long 0x00 5. " [5] ,Loop Back Pair Select Bit[5]" "Not selected,Selected" bitfld.long 0x00 4. " [4] ,Loop Back Pair Select Bit[4]" "Not selected,Selected" newline bitfld.long 0x00 3. " [3] ,Loop Back Pair Select Bit[3]" "Not selected,Selected" bitfld.long 0x00 2. " [2] ,Loop Back Pair Select Bit[2]" "Not selected,Selected" newline bitfld.long 0x00 1. " [1] ,Loop Back Pair Select Bit[1]" "Not selected,Selected" bitfld.long 0x00 0. " [0] ,Loop Back Pair Select Bit[0]" "Not selected,Selected" else hgroup.long 0x8C++0x3 hide.long 0x0 "LBPSEL,Loop Back Pair Select Register" endif endif group.long 0x90++0x07 line.long 0x00 "LBPDIR,Loop Back Pair Direction Register" bitfld.long 0x00 16.--19. " IODFTENA ,Module IODFT Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" bitfld.long 0x00 15. " LBPDIR[15] ,Loop Back Pair Direction Bit[15]" "Input,Output" bitfld.long 0x00 14. " [14] ,Loop Back Pair Direction Bit[14]" "Input,Output" newline bitfld.long 0x00 13. " [13] ,Loop Back Pair Direction Bit[13]" "Input,Output" bitfld.long 0x00 12. " [12] ,Loop Back Pair Direction Bit[12]" "Input,Output" bitfld.long 0x00 11. " [11] ,Loop Back Pair Direction Bit[11]" "Input,Output" newline bitfld.long 0x00 10. " [10] ,Loop Back Pair Direction Bit[10]" "Input,Output" bitfld.long 0x00 9. " [9] ,Loop Back Pair Direction Bit[9]" "Input,Output" bitfld.long 0x00 8. " [8] ,Loop Back Pair Direction Bit[8]" "Input,Output" newline bitfld.long 0x00 7. " [7] ,Loop Back Pair Direction Bit[7]" "Input,Output" bitfld.long 0x00 6. " [6] ,Loop Back Pair Direction Bit[6]" "Input,Output" bitfld.long 0x00 5. " [5] ,Loop Back Pair Direction Bit[5]" "Input,Output" newline bitfld.long 0x00 4. " [4] ,Loop Back Pair Direction Bit[4]" "Input,Output" bitfld.long 0x00 3. " [3] ,Loop Back Pair Direction Bit[3]" "Input,Output" bitfld.long 0x00 2. " [2] ,Loop Back Pair Direction Bit[2]" "Input,Output" newline bitfld.long 0x00 1. " [1] ,Loop Back Pair Direction Bit[1]" "Input,Output" bitfld.long 0x00 0. " [0] ,Loop Back Pair Direction Bit[0]" "Input,Output" line.long 0x04 "PINDIS,Pin Disable Register" bitfld.long 0x04 31. " HETPINDIS[31] ,NHET Pin Disable Bit[31]" "No,Yes" bitfld.long 0x04 30. " [30] ,NHET Pin Disable Bit[30]" "No,Yes" bitfld.long 0x04 29. " [29] ,NHET Pin Disable Bit[29]" "No,Yes" newline bitfld.long 0x04 28. " [28] ,NHET Pin Disable Bit[28]" "No,Yes" bitfld.long 0x04 27. " [27] ,NHET Pin Disable Bit[27]" "No,Yes" bitfld.long 0x04 26. " [26] ,NHET Pin Disable Bit[26]" "No,Yes" newline bitfld.long 0x04 25. " [25] ,NHET Pin Disable Bit[25]" "No,Yes" bitfld.long 0x04 24. " [24] ,NHET Pin Disable Bit[24]" "No,Yes" bitfld.long 0x04 23. " [23] ,NHET Pin Disable Bit[23]" "No,Yes" newline bitfld.long 0x04 22. " [22] ,NHET Pin Disable Bit[22]" "No,Yes" bitfld.long 0x04 21. " [21] ,NHET Pin Disable Bit[21]" "No,Yes" bitfld.long 0x04 20. " [20] ,NHET Pin Disable Bit[20]" "No,Yes" newline bitfld.long 0x04 19. " [19] ,NHET Pin Disable Bit[19]" "No,Yes" bitfld.long 0x04 18. " [18] ,NHET Pin Disable Bit[18]" "No,Yes" bitfld.long 0x04 17. " [17] ,NHET Pin Disable Bit[17]" "No,Yes" newline bitfld.long 0x04 16. " [16] ,NHET Pin Disable Bit[16]" "No,Yes" bitfld.long 0x04 15. " [15] ,NHET Pin Disable Bit[15]" "No,Yes" bitfld.long 0x04 14. " [14] ,NHET Pin Disable Bit[14]" "No,Yes" newline bitfld.long 0x04 13. " [13] ,NHET Pin Disable Bit[13]" "No,Yes" bitfld.long 0x04 12. " [12] ,NHET Pin Disable Bit[12]" "No,Yes" bitfld.long 0x04 11. " [11] ,NHET Pin Disable Bit[11]" "No,Yes" newline bitfld.long 0x04 10. " [10] ,NHET Pin Disable Bit[10]" "No,Yes" bitfld.long 0x04 9. " [9] ,NHET Pin Disable Bit[9]" "No,Yes" bitfld.long 0x04 8. " [8] ,NHET Pin Disable Bit[8]" "No,Yes" newline bitfld.long 0x04 7. " [7] ,NHET Pin Disable Bit[7]" "No,Yes" bitfld.long 0x04 6. " [6] ,NHET Pin Disable Bit[6]" "No,Yes" bitfld.long 0x04 5. " [5] ,NHET Pin Disable Bit[5]" "No,Yes" newline bitfld.long 0x04 4. " [4] ,NHET Pin Disable Bit[4]" "No,Yes" bitfld.long 0x04 3. " [3] ,NHET Pin Disable Bit[3]" "No,Yes" bitfld.long 0x04 2. " [2] ,NHET Pin Disable Bit[2]" "No,Yes" newline bitfld.long 0x04 1. " [1] ,NHET Pin Disable Bit[1]" "No,Yes" bitfld.long 0x04 0. " [0] ,NHET Pin Disable Bit[0]" "No,Yes" sif cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*") width 16. group.long 0x9C++0x13 "HWAG Registers" line.long 0x00 "HWAPINSEL,HWAG Pin Select Register" bitfld.long 0x00 0.--4. " PINSEL ,HWAG pin select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "HWAGCR0,HWAG Control Register 0" bitfld.long 0x04 0. " RESET ,HWAG module reset" "Reset,No reset" line.long 0x08 "HWAGCR1,HWAG Control Register 1" bitfld.long 0x08 0. " PPWN ,HWAG module power down" "Powered up,Powered down" line.long 0x0C "HWAGCR2,HWAG Control Register 2" bitfld.long 0x0C 24. " ARST ,Angle reset" "No reset,Reset" bitfld.long 0x0C 17. " TED ,Tooth edge" "Falling,Rising" bitfld.long 0x0C 16. " CRI ,Criteria enable" "Disabled,Enabled" newline bitfld.long 0x0C 8. " FIL ,Input filter enable" "Disabled,Enabled" bitfld.long 0x0C 0. " STRT ,Put the HWAG into run time start bit" "Stopped,Started" line.long 0x10 "HWAENA_SET/CLR,HWAG Interrupt Enable Set/Clear Register" setclrfld.long 0x10 7. 0x10 7. 0x14 7. " INTENA[7] ,Enable interrupt [7]" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x14 6. " [6] ,Enable interrupt [6]" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x14 5. " [5] ,Enable interrupt [5]" "Disabled,Enabled" newline setclrfld.long 0x10 4. 0x10 4. 0x14 4. " [4] ,Enable interrupt [4]" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x14 3. " [3] ,Enable interrupt [3]" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x14 2. " [2] ,Enable interrupt [2]" "Disabled,Enabled" newline setclrfld.long 0x10 1. 0x10 1. 0x14 1. " [1] ,Enable interrupt [1]" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x14 0. " [0] ,Enable interrupt [0]" "Disabled,Enabled" group.long 0xB0++0x03 line.long 0x00 "HWALVL_SET/CLR,HWAG Interrupt Priority Set Register" setclrfld.long 0x00 7. 0x00 7. 0x04 7. " LVLSET[7] ,Set interrupt [7] priority level" "Low,High" setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Set interrupt [6] priority level" "Low,High" setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Set interrupt [5] priority level" "Low,High" newline setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Set interrupt [4] priority level" "Low,High" setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Set interrupt [3] priority level" "Low,High" setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Set interrupt [2] priority level" "Low,High" newline setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Set interrupt [1] priority level" "Low,High" setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Set interrupt [0] priority level" "Low,High" group.long 0xB8++0x27 line.long 0x00 "HWAFLG,HWAG Interrupt Flags Register" eventfld.long 0x00 7. " INTFLG[7] ,Interrupt 7 flag" "No effect,Pending" eventfld.long 0x00 6. " [6] ,Interrupt 6 flag" "No effect,Pending" eventfld.long 0x00 5. " [5] ,Interrupt 5 flag" "No effect,Pending" newline eventfld.long 0x00 4. " [4] ,Interrupt 4 flag" "No effect,Pending" eventfld.long 0x00 3. " [3] ,Interrupt 3 flag" "No effect,Pending" eventfld.long 0x00 2. " [2] ,Interrupt 2 flag" "No effect,Pending" newline eventfld.long 0x00 1. " [1] ,Interrupt 1 flag" "No effect,Pending" eventfld.long 0x00 0. " [0] ,Interrupt 0 flag" "No effect,Pending" line.long 0x04 "HWAOFF0,HWAG Interrupt Offset Register 0" hexmask.long.byte 0x04 0.--7. 0x01 " OFFSET1 ,High-priority interrupt offset" line.long 0x08 "HWAOFF1,HWAG Interrupt Offset Register 1" hexmask.long.byte 0x08 0.--7. 0x01 " OFFSET2 ,Low-priority interrupt offset" line.long 0x0C "HWAACNT,HWAG ACNT Register, HWAG Angle Value" hexmask.long.tbyte 0x0C 0.--23. 1. " ACNT ,Angle value" line.long 0x10 "HWAPCNT1,HWAG PCNT (n-1) Register, HWAG Previous Tooth Period" hexmask.long.tbyte 0x10 0.--23. 1. " PCNT(N-1) ,Period (n-1) value" line.long 0x14 "HWAPCNT,HWAG PCNT (n) Register, HWAG Current Tooth Period" hexmask.long.tbyte 0x14 0.--23. 1. " PCNT(N) ,Period (n) value" line.long 0x18 "HWASTWD,HWAG Step Register" bitfld.long 0x18 0.--3. " STWD ,Step width (ticks per period)" "4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536,131072" line.long 0x1C "HWATHNB,HWAG Teeth Number Register" hexmask.long.byte 0x1C 0.--7. 1. " THNB ,Teeth number" line.long 0x20 "HWATHVL,HHWAG Current Teeth Number Register" hexmask.long.byte 0x20 0.--7. 1. " THVL ,Teeth value" line.long 0x24 "HWAFIL,HWAG Filter Register" hexmask.long.word 0x24 0.--9. 1. " FIL1 ,Filter value 1" group.long 0xE8++0x07 line.long 0x00 "HWAFIL2,HWAG Filter Register 2, HWAG Tick Counter Compare Value During Singularity Tooth" hexmask.long.word 0x00 0.--11. 1. " FIL2 ,Filter value 2" line.long 0x04 "HWAANGI,HWAG Angle Increment Register" hexmask.long.word 0x04 0.--9. 1. " ANGI ,Angle increment value" elif (cpu()==("TMS570LS2126")||cpu()==("TMS570LS2127")||cpu()==("TMS570LS2136")||cpu()==("TMS570LS2137")||cpu()==("TMS570LS2125-PGE")||cpu()==("TMS570LS2125-ZWT")||cpu()==("TMS570LS2135-PGE")||cpu()==("TMS570LS2135-ZWT")||cpu()==("TMS570LS2124-PGE")||cpu()==("TMS570LS2124-ZWT")||cpu()==("TMS570LS2134-PGE")||cpu()==("TMS570LS2134-ZWT")||cpu()==("TMS570LS3134-PGE")||cpu()==("TMS570LS3134-ZWT")||cpu()==("TMS570LS3135-PGE")||cpu()==("TMS570LS3135-ZWT")||cpu()==("TMS570LS3136")||cpu()==("TMS570LS3137-PGE")||cpu()==("TMS570LS3137-ZWT")||cpu()==("TMS570LS30336")||cpuis("RM48L950*")) group.long 0xA0++0x43 line.long 0x00 "HWAGCR0,HWAG Control Register 0" line.long 0x04 "HWAGCR1,HWAG Control Register 1" line.long 0x08 "HWAGCR2,HWAG Control Register 2" line.long 0x0C "HWAENASET,HWAG Interrupt Enable Set Register" line.long 0x10 "HWAENACLR,HWAG Interrupt Enable Clear Register" line.long 0x14 "HWALVLSET,HWAG Interrupt Priority Set Register" line.long 0x18 "HWALVLCLR,HWAG Interrupt Priority Clear Register" line.long 0x1C "HWAFLG,HWAG Interrupt Flags Register" line.long 0x20 "HWAOFF0,HWAG Interrupt Offset Register 1, HWAG Low Priority Interrupt Offset" line.long 0x24 "HWAOFF1,HWAG Interrupt Offset Register 2, HWAG High Priority Interrupt Offset" line.long 0x28 "HWAACNT,HWAG ACNT Register, HWAG Angle Value" line.long 0x2C "HWAPCNT1,HWAG PCNT (n-1) Register, HWAG Previous Tooth Period" line.long 0x30 "HWAPCNT,HWAG PCNT (n) Register, HWAG Current Tooth Period" line.long 0x34 "HWASTWD,HWAG Step Register" line.long 0x38 "HWATHNB,HWAG Teeth Number Register" line.long 0x3C "HWATHVL,HHWAG Current Teeth Number Register" line.long 0x40 "HWAFIL,HWAG Filter Register, HWAG Tick Counter Compare Value" group.long 0xE8++0x07 line.long 0x00 "HWAFIL2,HWAG Filter Register 2, HWAG Tick Counter Compare Value During Singularity Tooth" line.long 0x04 "HWAANGI,HWAG Angle Increment Register" endif sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*") endian.le endif width 0x0B tree.end tree "HTU (High End Timer Transfer Unit)" base ad:0xFFF7A400 sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*") endian.be endif width 10. group.long 0x00++0x07 line.long 0x00 "GC,Global Control Register" bitfld.long 0x00 24. " VBUS_HOLD ,Hold the VBUS bus" "Not held,Held" bitfld.long 0x00 16. " HTUEN ,Transfer unit enable bit" "Disabled,Enabled" bitfld.long 0x00 8. " DEBM ,Debug mode" "Suspended,Continue" newline bitfld.long 0x00 0. " HTU_RES ,HTU software reset" "No reset,Reset" line.long 0x04 "CPENA,Control Packet Enable Register" bitfld.long 0x04 14.--15. " CPENA7 ,CP enable bits 7 (CP B/CP A)" "Disabled,Disabled/Enabled,Enabled/Disabled,Disabled" bitfld.long 0x04 12.--13. " CPENA6 ,CP enable bits 6 (CP B/CP A)" "Disabled,Disabled/Enabled,Enabled/Disabled,Disabled" newline bitfld.long 0x04 10.--11. " CPENA5 ,CP enable bits 5 (CP B/CP A)" "Disabled,Disabled/Enabled,Enabled/Disabled,Disabled" bitfld.long 0x04 8.--9. " CPENA4 ,CP enable bits 4 (CP B/CP A)" "Disabled,Disabled/Enabled,Enabled/Disabled,Disabled" newline bitfld.long 0x04 6.--7. " CPENA3 ,CP enable bits 3 (CP B/CP A)" "Disabled,Disabled/Enabled,Enabled/Disabled,Disabled" bitfld.long 0x04 4.--5. " CPENA2 ,CP enable bits 2 (CP B/CP A)" "Disabled,Disabled/Enabled,Enabled/Disabled,Disabled" newline bitfld.long 0x04 2.--3. " CPENA1 ,CP enable bits 1 (CP B/CP A)" "Disabled,Disabled/Enabled,Enabled/Disabled,Disabled" bitfld.long 0x04 0.--1. " CPENA0 ,CP enable bits 0 (CP B/CP A)" "Disabled,Disabled/Enabled,Enabled/Disabled,Disabled" group.long 0x8++0x03 line.long 0x00 "BUSY0,Control Packet (CP) Busy Register 0" eventfld.long 0x00 24. " BUSY0A ,Busy flag for CP A of double CP 0" "Low,High" eventfld.long 0x00 16. " BUSY0B ,Busy flag for CP B of double CP 0" "Low,High" eventfld.long 0x00 8. " BUSY1A ,Busy flag for CP A of double CP 1" "Low,High" eventfld.long 0x00 0. " BUSY1B ,Busy flag for CP B of double CP 1" "Low,High" group.long 0xC++0x03 line.long 0x00 "BUSY1,Control Packet (CP) Busy Register 1" eventfld.long 0x00 24. " BUSY2A ,Busy flag for CP A of double CP 2" "Low,High" eventfld.long 0x00 16. " BUSY2B ,Busy flag for CP B of double CP 2" "Low,High" eventfld.long 0x00 8. " BUSY3A ,Busy flag for CP A of double CP 3" "Low,High" eventfld.long 0x00 0. " BUSY3B ,Busy flag for CP B of double CP 3" "Low,High" group.long 0x10++0x03 line.long 0x00 "BUSY2,Control Packet (CP) Busy Register 2" eventfld.long 0x00 24. " BUSY4A ,Busy flag for CP A of double CP 4" "Low,High" eventfld.long 0x00 16. " BUSY4B ,Busy flag for CP B of double CP 4" "Low,High" eventfld.long 0x00 8. " BUSY5A ,Busy flag for CP A of double CP 5" "Low,High" eventfld.long 0x00 0. " BUSY5B ,Busy flag for CP B of double CP 5" "Low,High" group.long 0x14++0x03 line.long 0x00 "BUSY3,Control Packet (CP) Busy Register 3" eventfld.long 0x00 24. " BUSY6A ,Busy flag for CP A of double CP 6" "Low,High" eventfld.long 0x00 16. " BUSY6B ,Busy flag for CP B of double CP 6" "Low,High" eventfld.long 0x00 8. " BUSY7A ,Busy flag for CP A of double CP 7" "Low,High" eventfld.long 0x00 0. " BUSY7B ,Busy flag for CP B of double CP 7" "Low,High" sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS3137-EP") group.long 0x18++0x3 line.long 0x00 "ACPE,Active Control Packet Register" eventfld.long 0x00 31. " ERRF ,Error flag" "No error,Error" rbitfld.long 0x00 24.--28. " ERRETC ,Error element transfer counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 16.--19. " ERRCPN ,Error control packet number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 15. " TIPF ,Transfer in progress flag" "Not active,Active" newline rbitfld.long 0x00 14. " BUS_BUSY ,VBUSP bus is busy" "Not busy,Busy" rbitfld.long 0x00 8.--12. " CETCOUNT ,Current element transfer counter" "No transfer,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 0.--3. " NACP ,Number of active control packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x18++0x3 line.long 0x00 "ACPE,Active Control Packet Register" eventfld.long 0x00 31. " ERRF ,Error flag" "No error,Error" bitfld.long 0x00 24.--28. " ERRETC ,Error element transfer counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 16.--19. 1. " ERRCPN ,Error control packet number" bitfld.long 0x00 15. " TIPF ,Transfer in progress flag" "Not active,Active" newline bitfld.long 0x00 14. " BUS_BUSY ,VBUSP bus is busy" "Not busy,Busy" bitfld.long 0x00 8.--12. " CETCOUNT ,Current element transfer counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 0.--3. 1. " NACP ,Number of active control packet" endif newline width 16. group.long 0x20++0x07 line.long 0x00 "RLBECTRL,Request Lost and Bus Error Control Register" bitfld.long 0x00 16. " BERINTENA ,Bus error interrupt enable bit" "Disabled,Enabled" bitfld.long 0x00 8. " CORL ,Continue on request lost error" "Lost,Continue" bitfld.long 0x00 0. " RLINTENA ,Request lost interrupt enable bit" "Disabled,Enabled" line.long 0x04 "BFINTS_SET/CLR,Buffer Full Interrupt Enable Set/Clr Register" setclrfld.long 0x04 15. 0x04 15. 0x08 15. " BFINTENA[15] ,CP B Buffer full interrupt enable bit 15" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x08 14. " [14] ,CP A Buffer full interrupt enable Bit 14" "Disabled,Enabled" setclrfld.long 0x04 13. 0x04 13. 0x08 13. " [13] ,CP B Bit 13" "Disabled,Enabled" newline setclrfld.long 0x04 12. 0x04 12. 0x08 12. " [12] ,CP A Buffer Full Interrupt Enable Bit 12" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x08 11. " [11] ,CP B buffer full interrupt enable bit 11" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x08 10. " [10] ,CP A buffer full interrupt enable bit 10" "Disabled,Enabled" newline setclrfld.long 0x04 9. 0x04 9. 0x08 9. " [9] ,CP B buffer full interrupt enable bit 9" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x08 8. " [8] ,CP A buffer full interrupt enable bit 8" "Disabled,Enabled" setclrfld.long 0x04 7. 0x04 7. 0x08 7. " [7] ,CP B buffer full interrupt enable bit 7" "Disabled,Enabled" newline setclrfld.long 0x04 6. 0x04 6. 0x08 6. " [6] ,CP A buffer full interrupt enable bit 6" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x08 5. " [5] ,CP B buffer full interrupt enable bit 5" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x08 4. " [4] ,CP A buffer full interrupt enable bit 4" "Disabled,Enabled" newline setclrfld.long 0x04 3. 0x04 3. 0x08 3. " [3] ,CP B buffer full interrupt enable bit 3" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x08 2. " [2] ,CP A buffer full interrupt enable bit 2" "Disabled,Enabled" setclrfld.long 0x04 1. 0x04 1. 0x08 1. " [1] ,CP B buffer full interrupt enable bit 1" "Disabled,Enabled" newline setclrfld.long 0x04 0. 0x04 0. 0x08 0. " [0] ,CP A buffer full interrupt enable bit 0" "Disabled,Enabled" group.long 0x2C++0x03 line.long 0x00 "INTMAP,Interrupt Mapping Register" bitfld.long 0x00 16. " MAPSEL ,Interrupt mapping select bit" "Low,High" bitfld.long 0x00 15. " CPINTMAP[15] ,CP B Interrupt mapping bit 15" "Line 0,Line 1" bitfld.long 0x00 14. " [14] ,CP A Interrupt mapping bit 14" "Line 0,Line 1" newline bitfld.long 0x00 13. " [13] ,CP B Interrupt mapping bit 13" "Line 0,Line 1" bitfld.long 0x00 12. " [12] ,CP A Interrupt mapping bit 12" "Line 0,Line 1" bitfld.long 0x00 11. " [11] ,CP B Interrupt mapping bit 11" "Line 0,Line 1" newline bitfld.long 0x00 10. " [10] ,CP A Interrupt mapping bit 10" "Line 0,Line 1" bitfld.long 0x00 9. " [9] ,CP B Interrupt mapping bit 9" "Line 0,Line 1" bitfld.long 0x00 8. " [8] ,CP A Interrupt mapping bit 8" "Line 0,Line 1" newline bitfld.long 0x00 7. " [7] ,CP B Interrupt mapping bit 7" "Line 0,Line 1" bitfld.long 0x00 6. " [6] ,CP A Interrupt mapping bit 6" "Line 0,Line 1" bitfld.long 0x00 5. " [5] ,CP B Interrupt mapping bit 5" "Line 0,Line 1" newline bitfld.long 0x00 4. " [4] ,CP A Interrupt mapping bit 4" "Line 0,Line 1" bitfld.long 0x00 3. " [3] ,CP B Interrupt mapping bit 3" "Line 0,Line 1" bitfld.long 0x00 2. " [2] ,CP A Interrupt mapping bit 2" "Line 0,Line 1" newline bitfld.long 0x00 1. " [1] ,CP B Interrupt mapping bit 1" "Line 0,Line 1" bitfld.long 0x00 0. " [0] ,CP A Interrupt mapping bit 0" "Line 0,Line 1" newline width 10. hgroup.long 0x34++0x3 hide.long 0x0 "INTOFF0,Interrupt Offset Register 0" in hgroup.long 0x38++0x3 hide.long 0x0 "INTOFF1,Interrupt Offset Register 1" in newline group.long 0x3C++0x23 line.long 0x00 "BIM,Buffer Initialization Mode Register" bitfld.long 0x00 7. " BIM[7] ,Buffer initialization mode bit 7" "Normal,Special" bitfld.long 0x00 6. " BIM[6] ,Buffer initialization mode bit 6" "Normal,Special" bitfld.long 0x00 5. " BIM[5] ,Buffer initialization mode bit 5" "Normal,Special" bitfld.long 0x00 4. " BIM[4] ,Buffer initialization mode bit 4" "Normal,Special" newline bitfld.long 0x00 3. " BIM[3] ,Buffer initialization mode bit 3" "Normal,Special" bitfld.long 0x00 2. " BIM[2] ,Buffer initialization mode bit 2" "Normal,Special" bitfld.long 0x00 1. " BIM[1] ,Buffer initialization mode bit 1" "Normal,Special" bitfld.long 0x00 0. " BIM[0] ,Buffer initialization mode bit 0" "Normal,Special" line.long 0x04 "RLOSTFL,Request Lost Flag Register" eventfld.long 0x04 15. " CPRLFL[15] ,CP B request lost flag 15" "Not requested,Requested" eventfld.long 0x04 14. " CPRLFL[14] ,CP A request lost flag 14" "Not requested,Requested" newline eventfld.long 0x04 13. " CPRLFL[13] ,CP B request lost flag 13" "Not requested,Requested" eventfld.long 0x04 12. " CPRLFL[12] ,CP A request lost flag 12" "Not requested,Requested" newline eventfld.long 0x04 11. " CPRLFL[11] ,CP B request lost flag 11" "Not requested,Requested" eventfld.long 0x04 10. " CPRLFL[10] ,CP A request lost flag 10" "Not requested,Requested" newline eventfld.long 0x04 9. " CPRLFL[9] ,CP B request lost flag 9" "Not requested,Requested" eventfld.long 0x04 8. " CPRLFL[8] ,CP A request lost flag 8" "Not requested,Requested" newline eventfld.long 0x04 7. " CPRLFL[7] ,CP B request lost flag 7" "Not requested,Requested" eventfld.long 0x04 6. " CPRLFL[6] ,CP A request lost flag 6" "Not requested,Requested" newline eventfld.long 0x04 5. " CPRLFL[5] ,CP B request lost flag 5" "Not requested,Requested" eventfld.long 0x04 4. " CPRLFL[4] ,CP A request lost flag 4" "Not requested,Requested" newline eventfld.long 0x04 3. " CPRLFL[3] ,CP B request lost flag 3" "Not requested,Requested" eventfld.long 0x04 2. " CPRLFL[2] ,CP A request lost flag 2" "Not requested,Requested" newline eventfld.long 0x04 1. " CPRLFL[1] ,CP B request lost flag 1" "Not requested,Requested" eventfld.long 0x04 0. " CPRLFL[0] ,CP A request lost flag 0" "Not requested,Requested" line.long 0x08 "BFINTFL,Buffer Full Interrupt Flag Register" eventfld.long 0x08 15. " BFINTFL[15] ,CP B buffer full interrupt flag 15" "No interrupt,Interrupt" eventfld.long 0x08 14. " BFINTFL[14] ,CP A buffer full interrupt flag 14" "No interrupt,Interrupt" newline eventfld.long 0x08 13. " BFINTFL[13] ,CP B buffer full interrupt flag 13" "No interrupt,Interrupt" eventfld.long 0x08 12. " BFINTFL[12] ,CP A buffer full interrupt flag 12" "No interrupt,Interrupt" newline eventfld.long 0x08 11. " BFINTFL[11] ,CP B buffer full interrupt flag 11" "No interrupt,Interrupt" eventfld.long 0x08 10. " BFINTFL[10] ,CP A buffer full interrupt flag 10" "No interrupt,Interrupt" newline eventfld.long 0x08 9. " BFINTFL[9] ,CP B buffer full interrupt flag 9" "No interrupt,Interrupt" eventfld.long 0x08 8. " BFINTFL[8] ,CP A buffer full interrupt flag 8" "No interrupt,Interrupt" newline eventfld.long 0x08 7. " BFINTFL[7] ,CP B buffer full interrupt flag 7" "No interrupt,Interrupt" eventfld.long 0x08 6. " BFINTFL[6] ,CP A buffer full interrupt flag 6" "No interrupt,Interrupt" newline eventfld.long 0x08 5. " BFINTFL[5] ,CP B buffer full interrupt flag 5" "No interrupt,Interrupt" eventfld.long 0x08 4. " BFINTFL[4] ,CP A buffer full interrupt flag 4" "No interrupt,Interrupt" newline eventfld.long 0x08 3. " BFINTFL[3] ,CP B buffer full interrupt flag 3" "No interrupt,Interrupt" eventfld.long 0x08 2. " BFINTFL[2] ,CP A buffer full interrupt flag 2" "No interrupt,Interrupt" newline eventfld.long 0x08 1. " BFINTFL[1] ,CP B buffer full interrupt flag 1" "No interrupt,Interrupt" eventfld.long 0x08 0. " BFINTFL[0] ,CP A buffer full interrupt flag 0" "No interrupt,Interrupt" line.long 0x0C "BERINTFL,BER Interrupt Flag Register" eventfld.long 0x0C 15. " BERINTFL[15] ,CP B bus error interrupt flag 15" "No interrupt,Interrupt" eventfld.long 0x0C 14. " BERINTFL[14] ,CP A bus error interrupt flag 14" "No interrupt,Interrupt" newline eventfld.long 0x0C 13. " BERINTFL[13] ,CP B bus error interrupt flag 13" "No interrupt,Interrupt" eventfld.long 0x0C 12. " BERINTFL[12] ,CP A bus error interrupt flag 12" "No interrupt,Interrupt" newline eventfld.long 0x0C 11. " BERINTFL[11] ,CP B bus error interrupt flag 11" "No interrupt,Interrupt" eventfld.long 0x0C 10. " BERINTFL[10] ,CP A bus error interrupt flag 10" "No interrupt,Interrupt" newline eventfld.long 0x0C 9. " BERINTFL[9] ,CP B bus error interrupt flag 9" "No interrupt,Interrupt" eventfld.long 0x0C 8. " BERINTFL[8] ,CP A bus error interrupt flag 8" "No interrupt,Interrupt" newline eventfld.long 0x0C 7. " BERINTFL[7] ,CP B bus error interrupt flag 7" "No interrupt,Interrupt" eventfld.long 0x0C 6. " BERINTFL[6] ,CP A bus error interrupt flag 6" "No interrupt,Interrupt" newline eventfld.long 0x0C 5. " BERINTFL[5] ,CP B bus error interrupt flag 5" "No interrupt,Interrupt" eventfld.long 0x0C 4. " BERINTFL[4] ,CP A bus error interrupt flag 4" "No interrupt,Interrupt" newline eventfld.long 0x0C 3. " BERINTFL[3] ,CP B bus error interrupt flag 3" "No interrupt,Interrupt" eventfld.long 0x0C 2. " BERINTFL[2] ,CP A bus error interrupt flag 2" "No interrupt,Interrupt" newline eventfld.long 0x0C 1. " BERINTFL[1] ,CP B bus error interrupt flag 1" "No interrupt,Interrupt" eventfld.long 0x0C 0. " BERINTFL[0] ,CP A bus error interrupt flag 0" "No interrupt,Interrupt" line.long 0x10 "MP1S,Memory Protection 1 Start Address" line.long 0x14 "MP1E,Memory Protection 1 End Address" line.long 0x18 "DCTRL,Debug Control Register" sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")) rbitfld.long 0x18 24.--27. " CPNUM ,CP number" "CP A of DCP0,CP B of DCP0,CP A of DCP1,,,,,,,,,,,,CP A of DCP7,CP B of DCP7" elif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS3137-EP") bitfld.long 0x18 24.--27. " CPNUM ,CP number" "CP A of DCP 0,CP B of DCP 0,CP A of DCP 1,CP B of DCP 1,CP A of DCP 2,CP B of DCP 2,CP A of DCP 3,CP B of DCP 3,CP A of DCP 4,CP B of DCP 4,CP A of DCP 5,CP B of DCP 5,CP A of DCP 6,CP B of DCP 6,CP A of DCP 7,CP B of DCP 7" else bitfld.long 0x18 24.--27. " CPNUM ,CP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline eventfld.long 0x18 16. " HTUDBGS ,HTU debug status" "Not detected,Detected" bitfld.long 0x18 0. " DBREN ,Debug request enable" "Disabled,Enabled" line.long 0x1C "WPR,Watch Point Register" line.long 0x20 "WMR,Watch Mask Register" rgroup.long 0x60++0x03 line.long 0x00 "ID,Module Identification Register" hexmask.long.byte 0x00 16.--23. 1. " CLASS ,Module class" hexmask.long.byte 0x00 8.--15. 1. " TYPE ,Subtype within a class" hexmask.long.byte 0x00 0.--7. 1. " REV ,Module revision number" group.long 0x64++0x07 line.long 0x0 "PCR,Parity Control Register" bitfld.long 0x00 16. " COPE , Continue on parity error" "Stopped,Continued" bitfld.long 0x00 8. " TEST ,Test" "Not mapped,Mapped" bitfld.long 0x00 0.--3. " PARITY_ENA ,Enable/disable parity checking" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" line.long 0x04 "PAR,Parity Address Register" eventfld.long 0x04 16. " PEFT ,Parity Error fault flag" "Not detected,Detected" hexmask.long.word 0x04 0.--8. 1. " PAOFF ,Parity error address offset" group.long 0x70++0x0B line.long 0x00 "MPCS,Memory Protection Control and Status Register" sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS3137-EP") rbitfld.long 0x00 24.--27. " CPNUM0 ,CP number" "CP A of DCP 0,CP B of DCP 0,CP A of DCP 1,CP B of DCP 1,CP A of DCP 2,CP B of DCP 2,CP A of DCP 3,CP B of DCP 3,CP A of DCP 4,CP B of DCP 4,CP A of DCP 5,CP B of DCP 5,CP A of DCP 6,CP B of DCP 6,CP A of DCP 7,CP B of DCP 7" else bitfld.long 0x00 24.--27. " CPNUM0 ,CP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline eventfld.long 0x00 17. " MPEFT1 ,Memory protection error fault flag" "Not detected,Detected" eventfld.long 0x00 16. " MPEFT0 ,Memory protection error fault flag" "Not detected,Detected" newline sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")) rbitfld.long 0x00 8.--11. " CPNUM1 ,CP number" "CP A of DCP0,CP B of DCP0,CP A of DCP1,,,,,,,,,,,,CP A of DCP7,CP B of DCP7" elif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS3137-EP") rbitfld.long 0x00 8.--11. " CPNUM1 ,CP number" "CP A of DCP 0,CP B of DCP 0,CP A of DCP 1,CP B of DCP 1,CP A of DCP 2,CP B of DCP 2,CP A of DCP 3,CP B of DCP 3,CP A of DCP 4,CP B of DCP 4,CP A of DCP 5,CP B of DCP 5,CP A of DCP 6,CP B of DCP 6,CP A of DCP 7,CP B of DCP 7" else bitfld.long 0x00 8.--11. " CPNUM1 ,CP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.long 0x00 5. " INTENA01 ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " ACCR01 ,Access rights HTU" "Allowed,Forbidden" newline bitfld.long 0x00 3. " REG01ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x00 2. " INTENA0 ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " ACCR ,Access rights HTU" "Allowed,Forbidden" newline bitfld.long 0x00 0. " REG0ENA ,Region enable" "Disabled,Enabled" line.long 0x04 "MP0S,Memory Protection Start Address Register" line.long 0x08 "MP0E,Memory Protection End Address Register" sif (cpuis("TMS570LS10106-PGE")||cpuis("TMS570LS10106-ZWT")||cpuis("TMS570LS10116-PGE")||cpuis("TMS570LS10116-ZWT")||cpuis("TMS570LS10206-PGE")||cpuis("TMS570LS10206-ZWT")||cpuis("TMS570LS10216-PGE")||cpuis("TMS570LS10216-ZWT")||cpuis("TMS570LS20206-PGE")||cpuis("TMS570LS20206-ZWT")||cpuis("TMS570LS20216-PGE")||cpuis("TMS570LS20216-ZWT")||cpuis("RM48L952-PGE")||cpuis("RM48L952-ZWT")||cpuis("RM48L950-PGE")||cpuis("RM48L950-ZWT")||cpuis("RM48L940-ZWT")||cpuis("RM48L940-PGE")||cpuis("RM48L930-ZWT")||cpuis("RM48L930-PGE")||cpuis("RM48L750-ZWT")||cpuis("RM48L750-PGE")||cpuis("RM48L740-ZWT")||cpuis("RM48L740-PGE")||cpuis("RM48L730-ZWT")||cpuis("RM48L730-PGE")||cpuis("RM48L550-PGE")||cpuis("RM48L540-ZWT")||cpuis("RM48L540-PGE")||cpuis("RM48L530-ZWT")||cpuis("RM48L530-PGE")||cpuis("RM46L852-PGE")||cpuis("RM46L852-ZWT")||cpuis("RM46L850-PGE")||cpuis("RM46L850-ZWT")||cpuis("RM46L840-ZWT")||cpuis("RM46L840-PGE")||cpuis("RM46L830-ZWT")||cpuis("RM46L830-PGE")||cpuis("RM46L450-ZWT")||cpuis("RM46L450-PGE")||cpuis("RM46L440-ZWT")||cpuis("RM46L440-PGE")||cpuis("RM46L430-ZWT")||cpuis("RM46L430-PGE")||cpuis("RM42L432")||cpuis("RM48L550-ZWT")||cpuis("TMS570LC4357")||cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS3137-EP")) tree "Double Control Packet Configuration Memory" base ad:0xFF4E0000 sif !cpuis("TMS570LS0714*")&&!cpuis("TMS570LS0914*")&&!cpuis("RM46L852*")&&!cpuis("TMS570LS3137-EP") group.long 0x00++0xF line.long 0x00 "IFADDRA,Initial main memory address Control Packet A" line.long 0x04 "IFADDRB,Initial main memory address Control Packet B" line.long 0x08 "IHADDRCT,Initial NHET address and control" bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET" bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit" newline bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (increment value)" "16 bytes,8 bytes" bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant" newline bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch" bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch" newline hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address" line.long 0x0C "ITCOUNT,Initial transfer count" bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count" group.long 0x100++0xB line.long 0x00 "CFADDRA,Current main memory address Control Packet A" line.long 0x04 "CFADDRB,Current main memory address Control Packet B" line.long 0x08 "CFCOUNT,Current frame count" hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A" hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B" else width 15. group.long 0x0++0x0F "DCP0" line.long 0x00 "DCP0IFADDRA,DCP0 Initial main memory address Control Packet A" line.long 0x04 "DCP0IFADDRB,DCP0 Initial main memory address Control Packet B" line.long 0x08 "DCP0IHADDRCT,DCP0 Initial NHET address and control" bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET" bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit" newline bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes" bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant" newline bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch" bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch" newline hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address" line.long 0x0C "DCP0ITCOUNT,DCP0 Initial transfer count" bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count" group.long (0x0+0x100)++0xB line.long 0x00 "DCP0CFADDRA,DCP0 Current main memory address control packet A" line.long 0x04 "DCP0CFADDRB,DCP0 Current main memory address control packet B" line.long 0x08 "DCP0CFCOUNT,DCP0 Current frame count" hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A" hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B" group.long 0x10++0x0F "DCP1" line.long 0x00 "DCP1IFADDRA,DCP1 Initial main memory address Control Packet A" line.long 0x04 "DCP1IFADDRB,DCP1 Initial main memory address Control Packet B" line.long 0x08 "DCP1IHADDRCT,DCP1 Initial NHET address and control" bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET" bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit" newline bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes" bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant" newline bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch" bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch" newline hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address" line.long 0x0C "DCP1ITCOUNT,DCP1 Initial transfer count" bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count" group.long (0x10+0x100)++0xB line.long 0x00 "DCP1CFADDRA,DCP1 Current main memory address control packet A" line.long 0x04 "DCP1CFADDRB,DCP1 Current main memory address control packet B" line.long 0x08 "DCP1CFCOUNT,DCP1 Current frame count" hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A" hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B" group.long 0x20++0x0F "DCP2" line.long 0x00 "DCP2IFADDRA,DCP2 Initial main memory address Control Packet A" line.long 0x04 "DCP2IFADDRB,DCP2 Initial main memory address Control Packet B" line.long 0x08 "DCP2IHADDRCT,DCP2 Initial NHET address and control" bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET" bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit" newline bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes" bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant" newline bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch" bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch" newline hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address" line.long 0x0C "DCP2ITCOUNT,DCP2 Initial transfer count" bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count" group.long (0x20+0x100)++0xB line.long 0x00 "DCP2CFADDRA,DCP2 Current main memory address control packet A" line.long 0x04 "DCP2CFADDRB,DCP2 Current main memory address control packet B" line.long 0x08 "DCP2CFCOUNT,DCP2 Current frame count" hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A" hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B" group.long 0x30++0x0F "DCP3" line.long 0x00 "DCP3IFADDRA,DCP3 Initial main memory address Control Packet A" line.long 0x04 "DCP3IFADDRB,DCP3 Initial main memory address Control Packet B" line.long 0x08 "DCP3IHADDRCT,DCP3 Initial NHET address and control" bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET" bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit" newline bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes" bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant" newline bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch" bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch" newline hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address" line.long 0x0C "DCP3ITCOUNT,DCP3 Initial transfer count" bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count" group.long (0x30+0x100)++0xB line.long 0x00 "DCP3CFADDRA,DCP3 Current main memory address control packet A" line.long 0x04 "DCP3CFADDRB,DCP3 Current main memory address control packet B" line.long 0x08 "DCP3CFCOUNT,DCP3 Current frame count" hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A" hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B" group.long 0x40++0x0F "DCP4" line.long 0x00 "DCP4IFADDRA,DCP4 Initial main memory address Control Packet A" line.long 0x04 "DCP4IFADDRB,DCP4 Initial main memory address Control Packet B" line.long 0x08 "DCP4IHADDRCT,DCP4 Initial NHET address and control" bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET" bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit" newline bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes" bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant" newline bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch" bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch" newline hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address" line.long 0x0C "DCP4ITCOUNT,DCP4 Initial transfer count" bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count" group.long (0x40+0x100)++0xB line.long 0x00 "DCP4CFADDRA,DCP4 Current main memory address control packet A" line.long 0x04 "DCP4CFADDRB,DCP4 Current main memory address control packet B" line.long 0x08 "DCP4CFCOUNT,DCP4 Current frame count" hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A" hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B" group.long 0x50++0x0F "DCP5" line.long 0x00 "DCP5IFADDRA,DCP5 Initial main memory address Control Packet A" line.long 0x04 "DCP5IFADDRB,DCP5 Initial main memory address Control Packet B" line.long 0x08 "DCP5IHADDRCT,DCP5 Initial NHET address and control" bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET" bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit" newline bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes" bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant" newline bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch" bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch" newline hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address" line.long 0x0C "DCP5ITCOUNT,DCP5 Initial transfer count" bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count" group.long (0x50+0x100)++0xB line.long 0x00 "DCP5CFADDRA,DCP5 Current main memory address control packet A" line.long 0x04 "DCP5CFADDRB,DCP5 Current main memory address control packet B" line.long 0x08 "DCP5CFCOUNT,DCP5 Current frame count" hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A" hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B" group.long 0x60++0x0F "DCP6" line.long 0x00 "DCP6IFADDRA,DCP6 Initial main memory address Control Packet A" line.long 0x04 "DCP6IFADDRB,DCP6 Initial main memory address Control Packet B" line.long 0x08 "DCP6IHADDRCT,DCP6 Initial NHET address and control" bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET" bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit" newline bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes" bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant" newline bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch" bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch" newline hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address" line.long 0x0C "DCP6ITCOUNT,DCP6 Initial transfer count" bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count" group.long (0x60+0x100)++0xB line.long 0x00 "DCP6CFADDRA,DCP6 Current main memory address control packet A" line.long 0x04 "DCP6CFADDRB,DCP6 Current main memory address control packet B" line.long 0x08 "DCP6CFCOUNT,DCP6 Current frame count" hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A" hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B" group.long 0x70++0x0F "DCP7" line.long 0x00 "DCP7IFADDRA,DCP7 Initial main memory address Control Packet A" line.long 0x04 "DCP7IFADDRB,DCP7 Initial main memory address Control Packet B" line.long 0x08 "DCP7IHADDRCT,DCP7 Initial NHET address and control" bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET" bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit" newline bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes" bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant" newline bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch" bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch" newline hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address" line.long 0x0C "DCP7ITCOUNT,DCP7 Initial transfer count" bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count" group.long (0x70+0x100)++0xB line.long 0x00 "DCP7CFADDRA,DCP7 Current main memory address control packet A" line.long 0x04 "DCP7CFADDRB,DCP7 Current main memory address control packet B" line.long 0x08 "DCP7CFCOUNT,DCP7 Current frame count" hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A" hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B" endif tree.end endif sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*") endian.le endif width 0x0B tree.end tree.open "SPI (Serial Peripheral Interface)" tree "MIBSPI1" base ad:0xFFF7F400 width 6. group.long 0x00++0x3 line.long 0x0 "GCR0,Global Control Register 0" bitfld.long 0x00 0. " nRESET ,This is the Reset Bit for the Module" "Reset,No reset" if (((d.l((ad:0xFFF7F400+0x04)))&0x03)==0x03) group.long 0x04++0x3 line.long 0x0 "GCR1,Global Control Register 1" bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI Pin Direction Determination" "Input/output,Output/input" bitfld.long 0x00 24. " SPIEN ,SPI Enable" "Not active,Active" bitfld.long 0x00 16. " LOOP_BACK ,Internal Loop-back Test Mode" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " POWERDOWN ,SPI State Machines Power Down State Enable" "Active,Power down" bitfld.long 0x00 1. " CLKMOD ,Clock Mode" "External,Internal" elif (((d.l((ad:0xFFF7F400+0x04)))&0x03)==0x02) group.long 0x04++0x3 line.long 0x0 "GCR1,Global Control Register 1" bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI Pin Direction Determination" "Input/output,Output/input" bitfld.long 0x00 24. " SPIEN ,SPI Enable" "Not active,Active" bitfld.long 0x00 8. " POWERDOWN ,SPI State Machines Power Down State Enable" "Active,Power down" textline " " bitfld.long 0x00 1. " CLKMOD ,Clock Mode" "External,Internal" elif (((d.l((ad:0xFFF7F400+0x04)))&0x03)==0x01) group.long 0x04++0x3 line.long 0x0 "GCR1,Global Control Register 1" bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI Pin Direction Determination" "Input/output,Output/input" bitfld.long 0x00 24. " SPIEN ,SPI Enable" "Not active,Active" bitfld.long 0x00 8. " POWERDOWN ,SPI State Machines Power Down State Enable" "Active,Power down" textline " " bitfld.long 0x00 1. " CLKMOD ,Clock Mode" "External,Internal" else group.long 0x04++0x3 line.long 0x0 "GCR1,Global Control Register 1" bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI Pin Direction Determination" "Input/output,Output/input" bitfld.long 0x00 24. " SPIEN ,SPI Enable" "Not active,Active" bitfld.long 0x00 8. " POWERDOWN ,SPI State Machines Power Down State Enable" "Active,Power down" textline " " bitfld.long 0x00 1. " CLKMOD ,Clock Mode" "External,Internal" endif width 6. if (((d.l((ad:0xFFF7F400+0x04)))&0x01)==0x01) group.long 0x08++0x3 line.long 0x0 "INT0,Interrupt Register" bitfld.long 0x00 24. " ENABLE_HIGHZ ,/SPIENA Pin High-z Enable" "Disabled,Enabled" bitfld.long 0x00 16. " DMA_REQ_EN ,DMA Request Enable" "Not used,Generated" textline " " bitfld.long 0x00 9. " TXINTENA ,Transmit Interrupt Enable" "Not generated,Generated" bitfld.long 0x00 8. " RXINTENA ,Receive Interrupt Enable" "Not generated,Generated" textline " " bitfld.long 0x00 6. " RXOVRNINTENA ,Overrun Interrupt Enable" "Not generated,Generated" bitfld.long 0x00 4. " BITERRENA ,Enables Interrupt on Bit Error" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " DESYNCENA ,Enables Interrupt on De-synchronized Slave" "Disabled,Enabled" bitfld.long 0x00 2. " PARERRENA ,Enables Interrupt on Parity Error" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " TIMEOUTENA ,Enables Interrupt on ENA Signal Time-out" "Disabled,Enabled" bitfld.long 0x00 0. " DLEN_ERR_ENA ,Data Length Error Interrupt Enable" "Disabled,Enabled" else group.long 0x08++0x3 line.long 0x0 "INT0,Interrupt Register" bitfld.long 0x00 24. " ENABLE_HIGHZ ,/SPIENA Pin High-z Enable" "Disabled,Enabled" bitfld.long 0x00 16. " DMA_REQ_EN ,DMA Request Enable" "Not used,Generated" textline " " bitfld.long 0x00 9. " TXINTENA ,Transmit Interrupt Enable" "Not generated,Generated" bitfld.long 0x00 8. " RXINTENA ,Receive Interrupt Enable" "Not generated,Generated" textline " " bitfld.long 0x00 6. " RXOVRNINTENA ,Overrun Interrupt Enable" "Not generated,Generated" bitfld.long 0x00 4. " BITERRENA ,Enables Interrupt on Bit Error" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " PARERRENA ,Enables Interrupt on Parity Error" "Disabled,Enabled" bitfld.long 0x00 1. " TIMEOUTENA ,Enables Interrupt on ENA Signal Time-out" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " DLEN_ERR_ENA ,Data Length Error Interrupt Enable" "Disabled,Enabled" endif width 6. if (((d.l((ad:0xFFF7F400+0x04)))&0x01)==0x01) group.long 0x0C++0x3 line.long 0x0 "LVL,Interrupt Level Register" bitfld.long 0x00 9. " TXINTLVL ,Transmit Interrupt Level" "INT0,INT1" bitfld.long 0x00 8. " RXINTLVL ,Receive Interrupt level" "INT0,INT1" sif (cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")) bitfld.long 0x00 6. " OVRNINTLVL ,Receive Overrun Interrupt level" "INT0,INT1" else bitfld.long 0x00 6. " RXOVRNINTLVL ,Receive Overrun Interrupt level" "INT0,INT1" endif textline " " bitfld.long 0x00 4. " BITERRLVL ,Bit Error Interrupt level" "INT0,INT1" bitfld.long 0x00 3. " DESYNCLVL ,De-synchronized Slave Interrupt Level" "INT0,INT1" bitfld.long 0x00 2. " PARERRLVL ,Parity Error Interrupt Level" "INT0,INT1" textline " " bitfld.long 0x00 1. " TIMEOUTLVL ,/SPIENA Pin Time-out Interrupt Level" "INT0,INT1" bitfld.long 0x00 0. " DLEN_ERR_LVL ,Data Length Error Interrupt Enable Level" "INT0,INT1" else group.long 0x0C++0x3 line.long 0x0 "LVL,Interrupt Level Register" bitfld.long 0x00 9. " TXINTLVL ,Transmit Interrupt Level" "INT0,INT1" bitfld.long 0x00 8. " RXINTLVL ,Receive Interrupt level" "INT0,INT1" sif (cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")) bitfld.long 0x00 6. " OVRNINTLVL ,Receive Overrun Interrupt level" "INT0,INT1" else bitfld.long 0x00 6. " RXOVRNINTLVL ,Receive Overrun Interrupt level" "INT0,INT1" endif textline " " bitfld.long 0x00 4. " BITERRLVL ,Bit Error Interrupt level" "INT0,INT1" bitfld.long 0x00 2. " PARERRLVL ,Parity Error Interrupt Level" "INT0,INT1" bitfld.long 0x00 1. " TIMEOUTLVL ,/SPIENA Pin Time-out Interrupt Level" "INT0,INT1" textline " " bitfld.long 0x00 0. " DLEN_ERR_LVL ,Data Length Error Interrupt Enable Level" "INT0,INT1" endif width 6. if (((d.l((ad:0xFFF7F400+0x04)))&0x01)==0x01) group.long 0x10++0x3 line.long 0x0 "FLG,Flag Register" bitfld.long 0x00 24. " BUF_INIT_ACTIVE ,Multibuffer Initialization Active" "Finished,Not finished" bitfld.long 0x00 9. " TXINTFLG ,Transmitter Empty Interrupt Flag" "Full,Empty" textline " " eventfld.long 0x00 8. " RXINTFLG ,Receiver Full Interrupt Flag" "Empty,Full" eventfld.long 0x00 6. " RXOVRNINTFLG ,Receiver Overrun Flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 4. " BITERRFLG ,Internal Transmit Data and Transmitted Data Mismatch" "Not occurred,Occurred" eventfld.long 0x00 3. " DESYNCFLG ,Slave Device De-Synchronization" "Not detected,Detected" textline " " eventfld.long 0x00 2. " PARITYERRFLG ,Parity Error Flag" "Not detected,Detected" eventfld.long 0x00 1. " TIMEOUTFLG ,Time-out Due to Non-activation of ENA Signal" "Not occurred,Occurred" textline " " eventfld.long 0x00 0. " DLEN_ERR_FLG ,Data Length Error Flag" "Not occurred,Occurred" else group.long 0x10++0x3 line.long 0x0 "FLG,Flag Register" bitfld.long 0x00 24. " BUF_INIT_ACTIVE ,Multibuffer Initialization Active" "Not completed,Completed" bitfld.long 0x00 9. " TXINTFLG ,Transmitter Empty Interrupt Flag" "No empty,Empty" textline " " eventfld.long 0x00 8. " RXINTFLG ,Receiver Full Interrupt Flag" "No full,Full" eventfld.long 0x00 6. " RXOVRNINTFLG ,Receiver Overrun Flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 4. " BITERRFLG ,Internal Transmit Data and Transmitted Data Mismatch" "Not occurred,Occurred" eventfld.long 0x00 2. " PARITYERRFLG ,Parity Error Flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 1. " TIMEOUTFLG ,Time-out Due to Non-activation of ENA Signal" "Not occurred,Occurred" eventfld.long 0x00 0. " DLEN_ERR_FLG ,Data Length Error Flag" "Not occurred,Occurred" endif width 5. tree "SPI Pin Control Registers" tree "SPI Pin Control Registers 0-5" group.long 0x14++0x3 line.long 0x0 "PC0,Pin Control Register 0" bitfld.long 0x00 31. " SOMIFUN7 ,Slave Out Master in Function 7" "GPIO,SPI/MibSPI" bitfld.long 0x00 30. " SOMIFUN6 ,Slave Out Master in Function 6" "GPIO,SPI/MibSPI" bitfld.long 0x00 29. " SOMIFUN5 ,Slave Out Master in Function 5" "GPIO,SPI/MibSPI" textline " " bitfld.long 0x00 28. " SOMIFUN4 ,Slave Out Master in Function 4" "GPIO,SPI/MibSPI" bitfld.long 0x00 27. " SOMIFUN3 ,Slave Out Master in Function 3" "GPIO,SPI/MibSPI" bitfld.long 0x00 26. " SOMIFUN2 ,Slave Out Master in Function 2" "GPIO,SPI/MibSPI" textline " " bitfld.long 0x00 25. " SOMIFUN1 ,Slave Out Master in Function 1" "GPIO,SPI/MibSPI" bitfld.long 0x00 24. " SOMIFUN0 ,Slave Out Master in Function 0" "GPIO,SPI/MibSPI" bitfld.long 0x00 23. " SIMOFUN7 ,Slave In Master Out Function 7" "GPIO,SPI/MibSPI" textline " " bitfld.long 0x00 22. " SIMOFUN6 ,Slave In Master Out Function 6" "GPIO,SPI/MibSPI" bitfld.long 0x00 21. " SIMOFUN5 ,Slave In Master Out Function 5" "GPIO,SPI/MibSPI" bitfld.long 0x00 20. " SIMOFUN4 ,Slave In Master Out Function 4" "GPIO,SPI/MibSPI" textline " " bitfld.long 0x00 19. " SIMOFUN3 ,Slave In Master Out Function 3" "GPIO,SPI/MibSPI" bitfld.long 0x00 18. " SIMOFUN2 ,Slave In Master Out Function 2" "GPIO,SPI/MibSPI" bitfld.long 0x00 17. " SIMOFUN1 ,Slave In Master Out Function 1" "GPIO,SPI/MibSPI" textline " " bitfld.long 0x00 16. " SIMOFUN0 ,Slave In Master Out Function 0" "GPIO,SPI/MibSPI" bitfld.long 0x00 11. " SOMIFUN0 ,Slave Out Master In Function" "GPIO,SPI/MibSPI" bitfld.long 0x00 10. " SIMOFUN0 ,Slave In Master Out Function" "GPIO,SPI/MibSPI" textline " " bitfld.long 0x00 9. " CLKFUN ,SPI/MibSPI Clock Function" "GPIO,SPI/MibSPI" bitfld.long 0x00 8. " ENAFUN ,/SPIENA function" "GPIO,SPI/MibSPI" bitfld.long 0x00 7. " SCSFUN7 ,/SPISCS7 Function" "GPIO,SPI" textline " " bitfld.long 0x00 6. " SCSFUN6 ,/SPISCS6 Function" "GPIO,SPI" bitfld.long 0x00 5. " SCSFUN5 ,/SPISCS5 Function" "GPIO,SPI" bitfld.long 0x00 4. " SCSFUN4 ,/SPISCS4 Function" "GPIO,SPI" textline " " bitfld.long 0x00 3. " SCSFUN3 ,/SPISCS3 Function" "GPIO,SPI" bitfld.long 0x00 2. " SCSFUN2 ,/SPISCS2 Function" "GPIO,SPI" bitfld.long 0x00 1. " SCSFUN1 ,/SPISCS1 Function" "GPIO,SPI" textline " " bitfld.long 0x00 0. " SCSFUN0 ,/SPISCS0 Function" "GPIO,SPI" group.long 0x18++0x3 line.long 0x0 "PC1,Pin Control Register 1" bitfld.long 0x00 31. " SOMIDIR7 ,SPISOMI7 Direction" "Input,Output" bitfld.long 0x00 30. " SOMIDIR6 ,SPISOMI6 Direction" "Input,Output" bitfld.long 0x00 29. " SOMIDIR5 ,SPISOMI5 Direction" "Input,Output" textline " " bitfld.long 0x00 28. " SOMIDIR4 ,SPISOMI4 Direction" "Input,Output" bitfld.long 0x00 27. " SOMIDIR3 ,SPISOMI3 Direction" "Input,Output" bitfld.long 0x00 26. " SOMIDIR2 ,SPISOMI2 Direction" "Input,Output" textline " " bitfld.long 0x00 25. " SOMIDIR1 ,SPISOMI1 Direction" "Input,Output" bitfld.long 0x00 24. " SOMIDIR0 ,SPISOMI0 Direction" "Input,Output" bitfld.long 0x00 23. " SIMODIR7 ,SPISIMO7 Direction" "Input,Output" textline " " bitfld.long 0x00 22. " SIMODIR6 ,SPISIMO6 Direction" "Input,Output" bitfld.long 0x00 21. " SIMODIR5 ,SPISIMO5 Direction" "Input,Output" bitfld.long 0x00 20. " SIMODIR4 ,SPISIMO4 Direction" "Input,Output" textline " " bitfld.long 0x00 19. " SIMODIR3 ,SPISIMO3 Direction" "Input,Output" bitfld.long 0x00 18. " SIMODIR2 ,SPISIMO2 Direction" "Input,Output" bitfld.long 0x00 17. " SIMODIR1 ,SPISIMO1 Direction" "Input,Output" textline " " bitfld.long 0x00 16. " SIMODIR0 ,SPISIMO0 Direction" "Input,Output" bitfld.long 0x00 11. " SOMIDIR0 ,SPISOMI0 Direction" "Input,Output" bitfld.long 0x00 10. " SIMODIR0 ,SPISIMO0 Direction" "Input,Output" textline " " bitfld.long 0x00 9. " CLKDIR ,SPICLK Direction" "Input,Output" bitfld.long 0x00 8. " ENADIR ,/SPIENA Direction" "Input,Output" bitfld.long 0x00 7. " SCSDIR7 ,/SPISCS7 Direction" "Input,Output" textline " " bitfld.long 0x00 6. " SCSDIR6 ,/SPISCS6 Direction" "Input,Output" bitfld.long 0x00 5. " SCSDIR5 ,/SPISCS5 Direction" "Input,Output" bitfld.long 0x00 4. " SCSDIR4 ,/SPISCS4 Direction" "Input,Output" textline " " bitfld.long 0x00 3. " SCSDIR3 ,/SPISCS3 Direction" "Input,Output" bitfld.long 0x00 2. " SCSDIR2 ,/SPISCS2 Direction" "Input,Output" bitfld.long 0x00 1. " SCSDIR1 ,/SPISCS1 Direction" "Input,Output" textline " " bitfld.long 0x00 0. " SCSDIR0 ,/SPISCS0 Direction" "Input,Output" rgroup.long 0x1C++0x3 line.long 0x0 "PC2,Pin Control Register 2" bitfld.long 0x00 31. " SOMIDIN7 ,SPISOMI7 Data In" "Low,High" bitfld.long 0x00 30. " SOMIDIN6 ,SPISOMI6 Data In" "Low,High" bitfld.long 0x00 29. " SOMIDIN5 ,SPISOMI5 Data In" "Low,High" textline " " bitfld.long 0x00 28. " SOMIDIN4 ,SPISOMI4 Data In" "Low,High" bitfld.long 0x00 27. " SOMIDIN3 ,SPISOMI3 Data In" "Low,High" bitfld.long 0x00 26. " SOMIDIN2 ,SPISOMI2 Data In" "Low,High" textline " " bitfld.long 0x00 25. " SOMIDIN1 ,SPISOMI1 Data In" "Low,High" bitfld.long 0x00 24. " SOMIDIN0 ,SPISOMI0 Data In" "Low,High" bitfld.long 0x00 23. " SIMODIN7 ,SPISIMO7 Data In" "Low,High" textline " " bitfld.long 0x00 22. " SIMODIN6 ,SPISIMO6 Data In" "Low,High" bitfld.long 0x00 21. " SIMODIN5 ,SPISIMO5 Data In" "Low,High" bitfld.long 0x00 20. " SIMODIN4 ,SPISIMO4 Data In" "Low,High" textline " " bitfld.long 0x00 19. " SIMODIN3 ,SPISIMO3 Data In" "Low,High" bitfld.long 0x00 18. " SIMODIN2 ,SPISIMO2 Data In" "Low,High" bitfld.long 0x00 17. " SIMODIN1 ,SPISIMO1 Data In" "Low,High" textline " " bitfld.long 0x00 16. " SIMODIN0 ,SPISIMO0 Data In" "Low,High" bitfld.long 0x00 11. " SOMIDIN0 ,SPISOMI0 Data In" "Low,High" bitfld.long 0x00 10. " SIMODIN0 ,SPISIMO0 Data In" "Low,High" textline " " bitfld.long 0x00 9. " CLKDIN ,Clock Data In" "Low,High" bitfld.long 0x00 8. " ENADIN ,/SPIENA Data In" "Low,High" bitfld.long 0x00 7. " SCSDIN7 ,SPISCS7 Data In" "Low,High" textline " " bitfld.long 0x00 6. " SCSDIN6 ,SPISCS6 Data In" "Low,High" bitfld.long 0x00 5. " SCSDIN5 ,SPISCS5 Data In" "Low,High" bitfld.long 0x00 4. " SCSDIN4 ,SPISCS4 Data In" "Low,High" textline " " bitfld.long 0x00 3. " SCSDIN3 ,SPISCS3 Data In" "Low,High" bitfld.long 0x00 2. " SCSDIN2 ,SPISCS2 Data In" "Low,High" bitfld.long 0x00 1. " SCSDIN1 ,SPISCS1 Data In" "Low,High" textline " " bitfld.long 0x00 0. " SCSDIN0 ,SPISCS0 Data In" "Low,High" width 5. group.long 0x20++0x3 line.long 0x0 "PC3,Pin Control Register 3" setclrfld.long 0x00 31. 0x04 31. 0x08 31. " SOMIDOUT7_set/clr ,SPISOMI7 Dataout Write" "Low,High" setclrfld.long 0x00 30. 0x04 30. 0x08 30. " SOMIDOUT6_set/clr ,SPISOMI6 Dataout Write" "Low,High" textline " " setclrfld.long 0x00 29. 0x04 29. 0x08 29. " SOMIDOUT5_set/clr ,SPISOMI5 Dataout Write" "Low,High" setclrfld.long 0x00 28. 0x04 28. 0x08 28. " SOMIDOUT4_set/clr ,SPISOMI4 Dataout Write" "Low,High" textline " " setclrfld.long 0x00 27. 0x04 27. 0x08 27. " SOMIDOUT3_set/clr ,SPISOMI3 Dataout Write" "Low,High" setclrfld.long 0x00 26. 0x04 26. 0x08 26. " SOMIDOUT2_set/clr ,SPISOMI2 Dataout Write" "Low,High" textline " " setclrfld.long 0x00 25. 0x04 25. 0x08 25. " SOMIDOUT1_set/clr ,SPISOMI1 Dataout Write" "Low,High" setclrfld.long 0x00 24. 0x04 24. 0x08 24. " SOMIDOUT0_set/clr ,SPISOMI0 Dataout Write" "Low,High" textline " " setclrfld.long 0x00 23. 0x04 23. 0x08 23. " SIMODOUT7_set/clr ,SPISIMO7 Dataout Write" "Low,High" setclrfld.long 0x00 22. 0x04 22. 0x08 22. " SIMODOUT6_set/clr ,SPISIMO6 Dataout Write" "Low,High" textline " " setclrfld.long 0x00 21. 0x04 21. 0x08 21. " SIMODOUT5_set/clr ,SPISIMO5 Dataout Write" "Low,High" setclrfld.long 0x00 20. 0x04 20. 0x08 20. " SIMODOUT4_set/clr ,SPISIMO4 Dataout Write" "Low,High" textline " " setclrfld.long 0x00 19. 0x04 19. 0x08 19. " SIMODOUT3_set/clr ,SPISIMO3 Dataout Write" "Low,High" setclrfld.long 0x00 18. 0x04 18. 0x08 18. " SIMODOUT2_set/clr ,SPISIMO2 Dataout Write" "Low,High" textline " " setclrfld.long 0x00 17. 0x04 17. 0x08 17. " SIMODOUT1_set/clr ,SPISIMO1 Dataout Write" "Low,High" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " SIMODOUT0_set/clr ,SPISIMO0 Dataout Write" "Low,High" textline " " setclrfld.long 0x00 11. 0x04 11. 0x08 11. " SOMIDOUT0_set/clr ,SPISOMI0 Dataout Write" "Low,High" setclrfld.long 0x00 10. 0x04 10. 0x08 10. " SIMODOUT0_set/clr ,SPISIMO0 Dataout Write" "Low,High" textline " " setclrfld.long 0x00 9. 0x04 9. 0x08 9. " CLKDOUT_set/clr ,SPICLK Dataout Write" "Low,High" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " ENADOUT_set/clr ,/SPIENA Dataout Write" "Low,High" textline " " setclrfld.long 0x00 7. 0x04 7. 0x08 7. " SCSDOUT7_set/clr ,SPISCS7 Dataout Write" "Low,High" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " SCSDOUT6_set/clr ,SPISCS6 Dataout Write" "Low,High" textline " " setclrfld.long 0x00 5. 0x04 5. 0x08 5. " SCSDOUT5_set/clr ,SPISCS5 Dataout Write" "Low,High" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " SCSDOUT4_set/clr ,SPISCS4 Dataout Write" "Low,High" textline " " setclrfld.long 0x00 3. 0x04 3. 0x08 3. " SCSDOUT3_set/clr ,SPISCS3 Dataout Write" "Low,High" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " SCSDOUT2_set/clr ,SPISCS2 Dataout Write" "Low,High" textline " " setclrfld.long 0x00 1. 0x04 1. 0x08 1. " SCSDOUT1_set/clr ,SPISCS1 Dataout Write" "Low,High" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " SCSDOUT0_set/clr ,SPISCS0 Dataout Write" "Low,High" tree.end width 5. tree "SPI Pin Control Registers 6-8" group.long 0x2C++0x3 line.long 0x0 "PC6,Pin Control Register 1" bitfld.long 0x00 31. " SOMIPDR7 ,SPISOMI7 Open Drain Enable" "High,Tri-stated" bitfld.long 0x00 30. " SOMIPDR6 ,SPISOMI6 Open Drain Enable" "High,Tri-stated" bitfld.long 0x00 29. " SOMIPDR5 ,SPISOMI5 Open Drain Enable" "High,Tri-stated" textline " " bitfld.long 0x00 28. " SOMIPDR4 ,SPISOMI4 Open Drain Enable" "High,Tri-stated" bitfld.long 0x00 27. " SOMIPDR3 ,SPISOMI3 Open Drain Enable" "High,Tri-stated" bitfld.long 0x00 26. " SOMIPDR2 ,SPISOMI2 Open Drain Enable" "High,Tri-stated" textline " " bitfld.long 0x00 25. " SOMIPDR1 ,SPISOMI1 Open Drain Enable" "High,Tri-stated" bitfld.long 0x00 24. " SOMIPDR0 ,SPISOMI0 Open Drain Enable" "High,Tri-stated" bitfld.long 0x00 23. " SIMOPDR7 ,SPISIMO7 Open Drain Enable" "High,Tri-stated" textline " " bitfld.long 0x00 22. " SIMOPDR6 ,SPISIMO6 Open Drain Enable" "High,Tri-stated" bitfld.long 0x00 21. " SIMOPDR5 ,SPISIMO5 Open Drain Enable" "High,Tri-stated" bitfld.long 0x00 20. " SIMOPDR4 ,SPISIMO4 Open Drain Enable" "High,Tri-stated" textline " " bitfld.long 0x00 19. " SIMOPDR3 ,SPISIMO3 Open Drain Enable" "High,Tri-stated" bitfld.long 0x00 18. " SIMOPDR2 ,SPISIMO2 Open Drain Enable" "High,Tri-stated" bitfld.long 0x00 17. " SIMOPDR1 ,SPISIMO1 Open Drain Enable" "High,Tri-stated" textline " " bitfld.long 0x00 16. " SIMOPDR0 ,SPISIMO0 Open Drain Enable" "High,Tri-stated" bitfld.long 0x00 11. " SOMIPDR0 ,SPISOMI0 Open Drain Enable" "High,Tri-stated" bitfld.long 0x00 10. " SIMOPDR0 ,SPISIMO0 Open Drain Enable" "High,Tri-stated" textline " " bitfld.long 0x00 9. " CLKPDR ,SPICLK Open Drain Enable" "High,Tri-stated" bitfld.long 0x00 8. " ENAPDR ,/SPIENA Open Drain Enable" "High,Tri-stated" bitfld.long 0x00 7. " SCSPDR7 ,/SPISCS7 Open Drain" "High,Tri-stated" textline " " bitfld.long 0x00 6. " SCSPDR6 ,/SPISCS6 Open Drain" "High,Tri-stated" bitfld.long 0x00 5. " SCSPDR5 ,/SPISCS5 Open Drain" "High,Tri-stated" bitfld.long 0x00 4. " SCSPDR4 ,/SPISCS4 Open Drain" "High,Tri-stated" textline " " bitfld.long 0x00 3. " SCSPDR3 ,/SPISCS3 Open Drain" "High,Tri-stated" bitfld.long 0x00 2. " SCSPDR2 ,/SPISCS2 Open Drain" "High,Tri-stated" bitfld.long 0x00 1. " SCSPDR1 ,/SPISCS1 Open Drain" "High,Tri-stated" textline " " bitfld.long 0x00 0. " SCSPDR0 ,/SPISCS0 Open Drain" "High,Tri-stated" group.long 0x30++0x3 line.long 0x0 "PC7,Pin Control Register 7" bitfld.long 0x00 31. " SOMIPDIS7 ,SPISOMI7 Pull Control Enable/Disable" "Enabled,Disabled" bitfld.long 0x00 30. " SOMIPDIS6 ,SPISOMI6 Pull Control Enable/Disable" "Enabled,Disabled" bitfld.long 0x00 29. " SOMIPDIS5 ,SPISOMI5 Pull Control Enable/Disable" "Enabled,Disabled" textline " " bitfld.long 0x00 28. " SOMIPDIS4 ,SPISOMI4 Pull Control Enable/Disable" "Enabled,Disabled" bitfld.long 0x00 27. " SOMIPDIS3 ,SPISOMI3 Pull Control Enable/Disable" "Enabled,Disabled" bitfld.long 0x00 26. " SOMIPDIS2 ,SPISOMI2 Pull Control Enable/Disable" "Enabled,Disabled" textline " " bitfld.long 0x00 25. " SOMIPDIS1 ,SPISOMI1 Pull Control Enable/Disable" "Enabled,Disabled" bitfld.long 0x00 24. " SOMIPDIS0 ,SPISOMI0 Pull Control Enable/Disable" "Enabled,Disabled" bitfld.long 0x00 23. " SIMOPDIS7 ,SPISIMO7 Pull Control Enable/Disable" "Enabled,Disabled" textline " " bitfld.long 0x00 22. " SIMOPDIS6 ,SPISIMO6 Pull Control Enable/Disable" "Enabled,Disabled" bitfld.long 0x00 21. " SIMOPDIS5 ,SPISIMO5 Pull Control Enable/Disable" "Enabled,Disabled" bitfld.long 0x00 20. " SIMOPDIS4 ,SPISIMO4 Pull Control Enable/Disable" "Enabled,Disabled" textline " " bitfld.long 0x00 19. " SIMOPDIS3 ,SPISIMO3 Pull Control Enable/Disable" "Enabled,Disabled" bitfld.long 0x00 18. " SIMOPDIS2 ,SPISIMO2 Pull Control Enable/Disable" "Enabled,Disabled" bitfld.long 0x00 17. " SIMOPDIS1 ,SPISIMO1 Pull Control Enable/Disable" "Enabled,Disabled" textline " " bitfld.long 0x00 16. " SIMOPDIS0 ,SPISIMO0 Pull Control Enable/Disable" "Enabled,Disabled" bitfld.long 0x00 11. " SOMIPDIS0 ,SPISOMI0 Pull Control Enable/Disable" "Enabled,Disabled" bitfld.long 0x00 10. " SIMOPDIS0 ,SPISIMO Pull Control Enable/Disable" "Enabled,Disabled" textline " " bitfld.long 0x00 9. " CLKPDIS ,SPICLK Pull Control Enable/Disable" "Enabled,Disabled" bitfld.long 0x00 8. " ENAPDIS ,SPIENA Pull Control Enable/Disable" "Enabled,Disabled" bitfld.long 0x00 7. " SCSPDIS7 ,SPISCS7 Pull Control Enable/Disable" "Enabled,Disabled" textline " " bitfld.long 0x00 6. " SCSPDIS6 ,SPISCS6 Pull Control Enable/Disable" "Enabled,Disabled" bitfld.long 0x00 5. " SCSPDIS5 ,SPISCS5 Pull Control Enable/Disable" "Enabled,Disabled" bitfld.long 0x00 4. " SCSPDIS4 ,SPISCS4 Pull Control Enable/Disable" "Enabled,Disabled" textline " " bitfld.long 0x00 3. " SCSPDIS3 ,SPISCS3 Pull Control Enable/Disable" "Enabled,Disabled" bitfld.long 0x00 2. " SCSPDIS2 ,SPISCS2 Pull Control Enable/Disable" "Enabled,Disabled" bitfld.long 0x00 1. " SCSPDIS1 ,SPISCS1 Pull Control Enable/Disable" "Enabled,Disabled" textline " " bitfld.long 0x00 0. " SCSPDIS0 ,SPISCS0 Pull Control Enable/Disable" "Enabled,Disabled" group.long 0x34++0x3 line.long 0x0 "PC8,Pin Control Register 8" bitfld.long 0x00 31. " SOMIPSEL7 ,SPISOMI7 Pull Select" "Pull down,Pull up" bitfld.long 0x00 30. " SOMIPSEL6 ,SPISOMI6 Pull Select" "Pull down,Pull up" bitfld.long 0x00 29. " SOMIPSEL5 ,SPISOMI5 Pull Select" "Pull down,Pull up" textline " " bitfld.long 0x00 28. " SOMIPSEL4 ,SPISOMI4 Pull Select" "Pull down,Pull up" bitfld.long 0x00 27. " SOMIPSEL3 ,SPISOMI3 Pull Select" "Pull down,Pull up" bitfld.long 0x00 26. " SOMIPSEL2 ,SPISOMI2 Pull Select" "Pull down,Pull up" textline " " bitfld.long 0x00 25. " SOMIPSEL1 ,SPISOMI1 Pull Select" "Pull down,Pull up" bitfld.long 0x00 24. " SOMIPSEL0 ,SPISOMI0 Pull Select" "Pull down,Pull up" bitfld.long 0x00 23. " SIMOPSEL7 ,SPISIMO7 Pull Select" "Pull down,Pull up" textline " " bitfld.long 0x00 22. " SIMOPSEL6 ,SPISIMO6 Pull Select" "Pull down,Pull up" bitfld.long 0x00 21. " SIMOPSEL5 ,SPISIMO5 Pull Select" "Pull down,Pull up" bitfld.long 0x00 20. " SIMOPSEL4 ,SPISIMO4 Pull Select" "Pull down,Pull up" textline " " bitfld.long 0x00 19. " SIMOPSEL3 ,SPISIMO3 Pull Select" "Pull down,Pull up" bitfld.long 0x00 18. " SIMOPSEL2 ,SPISIMO2 Pull Select" "Pull down,Pull up" bitfld.long 0x00 17. " SIMOPSEL1 ,SPISIMO1 Pull Select" "Pull down,Pull up" textline " " bitfld.long 0x00 16. " SIMOPSEL0 ,SPISIMO0 Pull Select" "Pull down,Pull up" bitfld.long 0x00 11. " SOMIPSEL ,SPISOMI Pull Select" "Pull down,Pull up" bitfld.long 0x00 10. " SIMOPSEL ,SPISIMO Pull Select" "Pull down,Pull up" textline " " bitfld.long 0x00 9. " CLKPSEL ,SPICLK Pull Select" "Pull down,Pull up" bitfld.long 0x00 8. " ENAPSEL ,SPIENA Pull Select" "Pull down,Pull up" bitfld.long 0x00 7. " SCSPSEL7 ,/SPISCS7 Pull select" "Pull down,Pull up" textline " " bitfld.long 0x00 6. " SCSPSEL6 ,/SPISCS6 Pull select" "Pull down,Pull up" bitfld.long 0x00 5. " SCSPSEL5 ,/SPISCS5 Pull select" "Pull down,Pull up" bitfld.long 0x00 4. " SCSPSEL4 ,/SPISCS4 Pull select" "Pull down,Pull up" textline " " bitfld.long 0x00 3. " SCSPSEL3 ,/SPISCS3 Pull select" "Pull down,Pull up" bitfld.long 0x00 2. " SCSPSEL2 ,/SPISCS2 Pull select" "Pull down,Pull up" bitfld.long 0x00 1. " SCSPSEL1 ,/SPISCS1 Pull select" "Pull down,Pull up" textline " " bitfld.long 0x00 0. " SCSPSEL0 ,/SPISCS0 Pull select" "Pull down,Pull up" tree.end tree.end width 7. if (((d.l((ad:0xFFF7F400+0x04)))&0x01000000)==0x01000000) group.long 0x38++0x3 line.long 0x0 "DAT0,Transmit Data Register 0" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,SPI / MibSPI Transmit Data" else rgroup.long 0x38++0x3 line.long 0x0 "DAT0,Transmit Data Register 0" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,SPI / MibSPI Transmit Data" endif if (((d.l((ad:0xFFF7F400+0x04)))&0x01)==0x01) group.long 0x3C++0x3 line.long 0x0 "DAT1,Transmit Data Register 1" bitfld.long 0x00 28. " CSHOLD ,Chip Select Hold Mode" "Not active,Active" bitfld.long 0x00 26. " WDEL ,Enable the Delay Counter at the End of the Current Transaction" "Disabled,Enabled" bitfld.long 0x00 24.--25. " DFSEL ,Data Word Format Select" "0,1,2,3" textline " " hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip Select Number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,SPI/MibSPI Transmit Data" else group.long 0x3C++0x3 line.long 0x0 "DAT1,Transmit Data Register 1" bitfld.long 0x00 24.--25. " DFSEL ,Data Word Format Select" "0,1,2,3" hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip Select Number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,SPI/MibSPI Transmit Data" endif hgroup.long 0x40++0x3 hide.long 0x0 "BUF,Receive Buffer Register" in width 7. if (((d.l((ad:0xFFF7F400+0x4)))&0x1)==0x1) rgroup.long 0x44++0x3 line.long 0x0 "EMU,Emulation Register" sif (cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")) bitfld.long 0x00 31. " RXEMPTY ,Receive Data Buffer Empty" "No empty,Empty" bitfld.long 0x00 30. " RXOVR ,Receive Data Buffer Overrun" "No overrun,Overrun" bitfld.long 0x00 29. " TXFULL ,Transmit Data Buffer Full" "Empty,Full" textline " " bitfld.long 0x00 28. " BITERR ,Mismatch of Internal Transmit Data and Transmitted Data" "Not occurred,Occurred" bitfld.long 0x00 27. " DESYNC ,De-synchronization of Slave Device" "No de-synchronized,De-synchronized" bitfld.long 0x00 26. " PARITYERR ,Calculated Parity Differs From Received Parity Bit" "No error,Error" textline " " bitfld.long 0x00 25. " TIMEOUT ,Time-out Due to Non-activation of ENA Pin" "Not occurred,Occurred" bitfld.long 0x00 24. " DLENERR ,Data Length Error Flag" "No error,Error" endif hexmask.long.byte 0x00 16.--23. 1. " LCSNR ,Last Chip Select Number" textline " " hexmask.long.word 0x00 0.--15. 1. " RXDATA ,SPI Receive Data" else rgroup.long 0x44++0x3 line.long 0x0 "EMU,Emulation Register" sif (cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")) bitfld.long 0x00 31. " RXEMPTY ,Receive Data Buffer Empty" "No empty,Empty" bitfld.long 0x00 30. " RXOVR ,Receive Data Buffer Overrun" "No overrun,Overrun" bitfld.long 0x00 29. " TXFULL ,Transmit Data Buffer Full" "Empty,Full" textline " " bitfld.long 0x00 28. " BITERR ,Mismatch of Internal Transmit Data and Transmitted Data" "Not occurred,Occurred" bitfld.long 0x00 26. " PARITYERR ,Calculated Parity Differs From Received Parity Bit" "No error,Error" bitfld.long 0x00 24. " DLENERR ,Data Length Error Flag" "No error,Error" textline " " endif hexmask.long.byte 0x00 16.--23. 1. " LCSNR ,Last Chip Select Number" hexmask.long.word 0x00 0.--15. 1. " RXDATA ,SPI Receive Data" endif if (((d.l((ad:0xFFF7F400+0x4)))&0x1)==0x1) group.long 0x48++0x3 line.long 0x0 "DELAY,Delay Register" hexmask.long.byte 0x00 24.--31. 1. " C2TDELAY ,Chip Select Active to Transmit Start Delay" hexmask.long.byte 0x00 16.--23. 1. " T2CDELAY ,Transmit End to Chip Select Inactive Delay" hexmask.long.byte 0x00 8.--15. 1. " T2EDELAY ,Transmit Data Finished to ENA Pin Inactive Time Out" textline " " hexmask.long.byte 0x00 0.--7. 1. " C2EDELAY ,Chip Select Active to ENA Signal Active Time Out" else hgroup.long 0x48++0x3 hide.long 0x0 "DELAY,Delay Register" endif width 7. group.long 0x4C++0x3 line.long 0x0 "DEF,Default Chip Select Register" bitfld.long 0x00 7. " CSDEF7 ,Chip Select Default Pattern 7" "Low,High" bitfld.long 0x00 6. " CSDEF6 ,Chip Select Default Pattern 6" "Low,High" bitfld.long 0x00 5. " CSDEF5 ,Chip Select Default Pattern 5" "Low,High" bitfld.long 0x00 4. " CSDEF4 ,Chip Select Default Pattern 4" "Low,High" textline " " bitfld.long 0x00 3. " CSDEF3 ,Chip Select Default Pattern 3" "Low,High" bitfld.long 0x00 2. " CSDEF2 ,Chip Select Default Pattern 2" "Low,High" bitfld.long 0x00 1. " CSDEF1 ,Chip Select Default Pattern 1" "Low,High" bitfld.long 0x00 0. " CSDEF0 ,Chip Select Default Pattern 0" "Low,High" width 6. tree "SPI Data Format Registers" group.long 0x50++0x3 line.long 0x0 "FMT0,Data Format Register 0" bitfld.long 0x00 24.--29. " WDELAY0 ,Delay in Between Transmissions For Data Format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " PARPOL0 ,Parity Polarity" "Even,Odd" bitfld.long 0x00 22. " PARITY0_ENA ,Parity Enable for Data Format 0" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " WAITENA0 ,Master Waits for ENA Signal From Slave for Data Format 0" "Not wait,Wait" bitfld.long 0x00 20. " SHIFTDIR0 ,Shift Direction for Data Format 0" "MSB,LSB" bitfld.long 0x00 18. " DIS_CS_TIMERS0 ,Disable Chipselect Timers for this Format Register" "No,Yes" textline " " bitfld.long 0x00 17. " POLARITY0 ,SPI Data Format 0 Clock Polarity" "Low-inactive,High-inactive" bitfld.long 0x00 16. " PHASE0 ,SPI Data Format 0 Clock Delay" "Not delayed,Delayed" hexmask.long.byte 0x00 8.--15. 1. " PRESCALE0 ,SPI Data Format 0 Prescaler" textline " " bitfld.long 0x00 0.--4. " CHARLEN0 ,SPI Data Format 0 Data Word Length" "Reserved,Reserved,2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..." group.long 0x54++0x3 line.long 0x0 "FMT1,Data Format Register 1" bitfld.long 0x00 24.--29. " WDELAY1 ,Delay in Between Transmissions For Data Format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " PARPOL1 ,Parity Polarity" "Even,Odd" bitfld.long 0x00 22. " PARITY1_ENA ,Parity Enable for Data Format 1" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " WAITENA1 ,Master Waits for ENA Signal From Slave for Data Format 1" "Not wait,Wait" bitfld.long 0x00 20. " SHIFTDIR1 ,Shift Direction for Data Format 1" "MSB,LSB" bitfld.long 0x00 18. " DIS_CS_TIMERS1 ,Disable Chipselect Timers for this Format Register" "No,Yes" textline " " bitfld.long 0x00 17. " POLARITY1 ,SPI Data Format 1 Clock Polarity" "Low-inactive,High-inactive" bitfld.long 0x00 16. " PHASE1 ,SPI Data Format 1 Clock Delay" "Not delayed,Delayed" hexmask.long.byte 0x00 8.--15. 1. " PRESCALE1 ,SPI Data Format 1 Prescaler" textline " " bitfld.long 0x00 0.--4. " CHARLEN1 ,SPI Data Format 1 Data Word Length" "Reserved,Reserved,2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..." group.long 0x58++0x3 line.long 0x0 "FMT2,Data Format Register 2" bitfld.long 0x00 24.--29. " WDELAY2 ,Delay in Between Transmissions For Data Format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " PARPOL2 ,Parity Polarity" "Even,Odd" bitfld.long 0x00 22. " PARITY2_ENA ,Parity Enable for Data Format 2" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " WAITENA2 ,Master Waits for ENA Signal From Slave for Data Format 2" "Not wait,Wait" bitfld.long 0x00 20. " SHIFTDIR2 ,Shift Direction for Data Format 2" "MSB,LSB" bitfld.long 0x00 18. " DIS_CS_TIMERS2 ,Disable Chipselect Timers for this Format Register" "No,Yes" textline " " bitfld.long 0x00 17. " POLARITY2 ,SPI Data Format 2 Clock Polarity" "Low-inactive,High-inactive" bitfld.long 0x00 16. " PHASE2 ,SPI Data Format 2 Clock Delay" "Not delayed,Delayed" hexmask.long.byte 0x00 8.--15. 1. " PRESCALE2 ,SPI Data Format 2 Prescaler" textline " " bitfld.long 0x00 0.--4. " CHARLEN2 ,SPI Data Format 2 Data Word Length" "Reserved,Reserved,2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..." group.long 0x5C++0x3 line.long 0x0 "FMT3,Data Format Register 3" bitfld.long 0x00 24.--29. " WDELAY3 ,Delay in Between Transmissions For Data Format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " PARPOL3 ,Parity Polarity" "Even,Odd" bitfld.long 0x00 22. " PARITY3_ENA ,Parity Enable for Data Format 3" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " WAITENA3 ,Master Waits for ENA Signal From Slave for Data Format 3" "Not wait,Wait" bitfld.long 0x00 20. " SHIFTDIR3 ,Shift Direction for Data Format 3" "MSB,LSB" bitfld.long 0x00 18. " DIS_CS_TIMERS3 ,Disable Chipselect Timers for this Format Register" "No,Yes" textline " " bitfld.long 0x00 17. " POLARITY3 ,SPI Data Format 3 Clock Polarity" "Low-inactive,High-inactive" bitfld.long 0x00 16. " PHASE3 ,SPI Data Format 3 Clock Delay" "Not delayed,Delayed" hexmask.long.byte 0x00 8.--15. 1. " PRESCALE3 ,SPI Data Format 3 Prescaler" textline " " bitfld.long 0x00 0.--4. " CHARLEN3 ,SPI Data Format 3 Data Word Length" "Reserved,Reserved,2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..." tree.end width 12. tree "SPI Interrupt Vector Registers" if (((d.l((ad:0xFFF7F400+0x70)))&0x01)==0x01) rgroup.long 0x60++0x3 line.long 0x0 "TGINTVECT0,Transfer Group Interrupt Vector Register 0" bitfld.long 0x00 1.--5. " INTVECT0 ,Interrupt Vector for Interrupt Line INT0" "No interrupt,Interrupt of transfer group 0,Interrupt of transfer group 1,Interrupt of transfer group 2,Interrupt of transfer group 3,Interrupt of transfer group 4,Interrupt of transfer group 5,Interrupt of transfer group 6,Interrupt of transfer group 7,Interrupt of transfer group 8,Interrupt of transfer group 9,Interrupt of transfer group 10,Interrupt of transfer group 11,Interrupt of transfer group 12,Interrupt of transfer group 13,Interrupt of transfer group 14,Interrupt of transfer group 15,Interrupt/SPIINT0,Reserved,RXORN Interrupt,?..." bitfld.long 0x00 0. " SUSPEND0 ,Transfer Suspended/Finished Interrupt" "Suspended,Finished" else rgroup.long 0x60++0x3 line.long 0x0 "TGINTVECT0,Transfer Group Interrupt Vector Register 0" bitfld.long 0x00 1.--5. " INTVECT0 ,Interrupt Vector for Interrupt Line INT0" "No interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Interrupt/SPIINT0,Receive Buffer Full Interrupt,Receive Buffer Overrun Interrupt,Transmit Buffer Empty Interrupt,?..." endif if (((d.l((ad:0xFFF7F400+0x70)))&0x01)==0x01) rgroup.long 0x64++0x3 line.long 0x0 "TGINTVECT1,Transfer Group Interrupt Vector Register 1" bitfld.long 0x00 1.--5. " INTVECT1 ,Interrupt Vector for Interrupt Line INT1" "No interrupt,Interrupt of transfer group 0,Interrupt of transfer group 1,Interrupt of transfer group 2,Interrupt of transfer group 3,Interrupt of transfer group 4,Interrupt of transfer group 5,Interrupt of transfer group 6,Interrupt of transfer group 7,Interrupt of transfer group 8,Interrupt of transfer group 9,Interrupt of transfer group 10,Interrupt of transfer group 11,Interrupt of transfer group 12,Interrupt of transfer group 13,Interrupt of transfer group 14,Interrupt of transfer group 15,Interrupt/SPIINT1,Reserved,RXORN Interrupt,?..." bitfld.long 0x00 0. " SUSPEND1 ,Transfer Suspended/Finished Interrupt" "Suspended,Finished" else rgroup.long 0x64++0x3 line.long 0x0 "TGINTVECT1,Transfer Group Interrupt Vector Register 1" bitfld.long 0x00 1.--5. " INTVECT1 ,Interrupt Vector for Interrupt Line INT1" "No interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Interrupt/SPIINT1,Receive Buffer Full Interrupt,Receive Buffer Overrun Interrupt,Transmit Buffer Empty Interrupt,?..." endif tree.end width 8. sif (cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")&&(cpu()!=("TMS570LS10116-PGE"))&&(cpu()!=("TMS570LS10216-PGE"))&&(cpu()!=("TMS570LS10116-ZWT"))&&(cpu()!=("TMS570LS10216-ZWT"))&&(cpu()!=("TMS570LS10106-PGE"))&&(cpu()!=("TMS570LS10206-PGE"))&&(cpu()!=("TMS570LS10106-ZWT"))&&(cpu()!=("TMS570LS10206-ZWT"))) group.long 0x68++0x3 line.long 0x0 "SRSEL,Pin Control Register 9" bitfld.long 0x00 31. " SPISOMISRS7 ,Controls the Slew Rate for the SPISOMI7" "Normal,Slow" bitfld.long 0x00 30. " SPISOMISRS6 ,Controls the Slew Rate for the SPISOMI6" "Normal,Slow" bitfld.long 0x00 29. " SPISOMISRS5 ,Controls the Slew Rate for the SPISOMI5" "Normal,Slow" textline " " bitfld.long 0x00 28. " SPISOMISRS4 ,Controls the Slew Rate for the SPISOMI4" "Normal,Slow" bitfld.long 0x00 27. " SPISOMISRS3 ,Controls the Slew Rate for the SPISOMI3" "Normal,Slow" bitfld.long 0x00 26. " SPISOMISRS2 ,Controls the Slew Rate for the SPISOMI2" "Normal,Slow" textline " " bitfld.long 0x00 25. " SPISOMISRS1 ,Controls the Slew Rate for the SPISOMI1" "Normal,Slow" bitfld.long 0x00 24. " SPISOMISRS0 ,Controls the Slew Rate for the SPISOMI0" "Normal,Slow" bitfld.long 0x00 23. " SPISIMOSRC7 ,Controls the Slew Rate for the SPISIMO7" "Normal,Slow" textline " " bitfld.long 0x00 22. " SPISIMOSRC6 ,Controls the Slew Rate for the SPISIMO6" "Normal,Slow" bitfld.long 0x00 21. " SPISIMOSRC5 ,Controls the Slew Rate for the SPISIMO5" "Normal,Slow" bitfld.long 0x00 20. " SPISIMOSRC4 ,Controls the Slew Rate for the SPISIMO4" "Normal,Slow" textline " " bitfld.long 0x00 19. " SPISIMOSRC3 ,Controls the Slew Rate for the SPISIMO3" "Normal,Slow" bitfld.long 0x00 18. " SPISIMOSRC2 ,Controls the Slew Rate for the SPISIMO2" "Normal,Slow" bitfld.long 0x00 17. " SPISIMOSRC1 ,Controls the Slew Rate for the SPISIMO1" "Normal,Slow" textline " " bitfld.long 0x00 16. " SPISIMOSRC0 ,Controls the Slew Rate for the SPISIMO0" "Normal,Slow" bitfld.long 0x00 11. " SPISOMISRS0 ,Controls the Slew Rate for SPISOMI0" "Normal,Slow" bitfld.long 0x00 10. " SPISIMOSRS0 ,Controls the Slew Rate for SPISIMO0" "Normal,Slow" textline " " bitfld.long 0x00 9. " SPICLKSRS ,Controls the Slew Rate for SPICLK" "Normal,Slow" bitfld.long 0x00 8. " SPIENASRS0 ,Controls the Slew Rate for /SPIENA" "Fast,Slow" bitfld.long 0x00 7. " SPISCSSRS7 ,Controls the Slew Rate for the /SPISCS7" "Normal,Slow" textline " " bitfld.long 0x00 6. " SPISCSSRS6 ,Controls the Slew Rate for the /SPISCS6" "Normal,Slow" bitfld.long 0x00 5. " SPISCSSRS5 ,Controls the Slew Rate for the /SPISCS5" "Normal,Slow" bitfld.long 0x00 4. " SPISCSSRS4 ,Controls the Slew Rate for the /SPISCS4" "Normal,Slow" textline " " bitfld.long 0x00 3. " SPISCSSRS3 ,Controls the Slew Rate for the /SPISCS3" "Normal,Slow" bitfld.long 0x00 2. " SPISCSSRS2 ,Controls the Slew Rate for the /SPISCS2" "Normal,Slow" bitfld.long 0x00 1. " SPISCSSRS1 ,Controls the Slew Rate for the /SPISCS1" "Normal,Slow" textline " " bitfld.long 0x00 0. " SPISCSSRS0 ,Controls the Slew Rate for the /SPISCS0" "Normal,Slow" endif if (((d.l((ad:0xFFF7F400+0x3c)))&0x03000000)==0x00) group.long 0x6c++0x03 line.long 0x00 "PMCTRL,Parallel/Modulo Mode Control Register" bitfld.long 0x00 5. " MOD_CLK_POL_0 ,Modulo Mode SPICLK Polarity" "Normal,Inverted" bitfld.long 0x00 2.--4. " MMODE_0 ,SPI Data Line Selection" "1-data,2-data,3-data,4-data,5-data,6-data,?..." sif (cpu()=="TMS570PSFC61") bitfld.long 0x00 0.--1. " PMODE_0 ,Parallel Mode" "1-data,2-data,4-data,?..." else bitfld.long 0x00 0.--1. " PMODE_0 ,Parallel Mode" "1-data,2-data,4-data,8-data" endif elif (((d.l((ad:0xFFF7F400+0x3c)))&0x03000000)==0x01000000) group.long 0x6c++0x03 line.long 0x00 "PMCTRL,Parallel/Modulo Mode Control Register" bitfld.long 0x00 13. " MOD_CLK_POL_1 ,Modulo Mode SPICLK Polarity" "Normal,Inverted" bitfld.long 0x00 10.--12. " MMODE_1 ,SPI Data Line Selection" "1-data,2-data,3-data,4-data,5-data,6-data,?..." sif (cpu()=="TMS570PSFC61") bitfld.long 0x00 8.--9. " PMODE_1 ,Parallel Mode" "1-data,2-data,4-data,?..." else bitfld.long 0x00 8.--9. " PMODE_1 ,Parallel Mode" "1-data,2-data,4-data,8-data" endif elif (((d.l((ad:0xFFF7F400+0x3c)))&0x03000000)==0x02000000) group.long 0x6c++0x03 line.long 0x00 "PMCTRL,Parallel/Modulo Mode Control Register" bitfld.long 0x00 21. " MOD_CLK_POL_2 ,Modulo Mode SPICLK Polarity" "Normal,Inverted" bitfld.long 0x00 18.--20. " MMODE_2 ,SPI Data Line Selection" "1-data,2-data,3-data,4-data,5-data,6-data,?..." sif (cpu()=="TMS570PSFC61") bitfld.long 0x00 16.--17. " PMODE_2 ,Parallel Mode" "1-data,2-data,4-data,?..." else bitfld.long 0x00 16.--17. " PMODE_2 ,Parallel Mode" "1-data,2-data,4-data,8-data" endif else group.long 0x6c++0x03 line.long 0x00 "PMCTRL,Parallel/Modulo Mode Control Register" bitfld.long 0x00 29. " MOD_CLK_POL_3 ,Modulo Mode SPICLK Polarity" "Normal,Inverted" bitfld.long 0x00 26.--28. " MMODE_3 ,SPI Data Line Selection" "1-data,2-data,3-data,4-data,5-data,6-data,?..." sif (cpu()=="TMS570PSFC61") bitfld.long 0x00 24.--25. " PMODE_3 ,Parallel Mode" "1-data,2-data,4-data,?..." else bitfld.long 0x00 24.--25. " PMODE_3 ,Parallel Mode" "1-data,2-data,4-data,8-data" endif endif width 11. tree "MibSPI Registers" group.long 0x70++0x3 line.long 0x0 "MIBSPIE,MibSPI Enable Register" bitfld.long 0x00 16. " RX_RAM_ACCESS ,Receive RAM Access Control Bit" "RX not writable,R/W" bitfld.long 0x00 0. " MSPIENA ,Multibuffer Mode Enable" "Disabled,Enabled" width 11. if (((d.l((ad:0xFFF7F400+0x70)))&0x01)==0x01) group.long 0x74++0x3 line.long 0x0 "TGITENST,MibSPI Transfer Group Interrupt Enable Register" sif cpu()!=("TMS570PSFC61")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE") setclrfld.long 0x00 31. 0x00 31. 0x04 31. " INTEN_RDY15_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x04 30. " INTEN_RDY14_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 29. 0x00 29. 0x04 29. " INTEN_RDY13_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x04 28. " INTEN_RDY12_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 27. 0x00 27. 0x04 27. " INTEN_RDY11_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x04 26. " INTEN_RDY10_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x04 25. " INTEN_RDY9_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x04 24. " INTEN_RDY8_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled" textline " " endif setclrfld.long 0x00 23. 0x00 23. 0x04 23. " INTEN_RDY7_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x04 22. " INTEN_RDY6_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 21. 0x00 21. 0x04 21. " INTEN_RDY5_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x04 20. " INTEN_RDY4_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x04 19. " INTEN_RDY3_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x04 18. " INTEN_RDY2_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 17. 0x00 17. 0x04 17. " INTEN_RDY1_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x04 16. " INTEN_RDY0_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled" textline " " sif cpu()!=("TMS570PSFC61")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE") setclrfld.long 0x00 15. 0x00 15. 0x04 15. " INTEN_SUS15_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x04 14. " INTEN_SUS14_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x04 13. " INTEN_SUS13_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x04 12. " INTEN_SUS12_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled" textline " " setclrfld.long 0x00 11. 0x00 11. 0x04 11. " INTEN_SUS11_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x04 10. " INTEN_SUS10_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled" textline " " setclrfld.long 0x00 9. 0x00 9. 0x04 9. " INTEN_SUS9_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x04 8. " INTEN_SUS8_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled" textline " " endif setclrfld.long 0x00 7. 0x00 7. 0x04 7. " INTEN_SUS7_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x04 6. " INTEN_SUS6_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. 0x00 5. 0x04 5. " INTEN_SUS5_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x04 4. " INTEN_SUS4_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled" textline " " setclrfld.long 0x00 3. 0x00 3. 0x04 3. " INTEN_SUS3_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x04 2. " INTEN_SUS2_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x04 1. " INTEN_SUS1_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x04 0. " INTEN_SUS0_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled" width 11. group.long 0x7c++0x3 line.long 0x00 "TGITLVST,MibSPI Transfer Group Interrupt Level Set Register" sif cpu()!=("TMS570PSFC61")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE") setclrfld.long 0x00 31. 0x00 31. 0x04 31. " INTLVL_RDY15_set/clr ,Transfer Group Completed Interrupt Level 15" "INT0,INT1" setclrfld.long 0x00 30. 0x00 30. 0x04 30. " INTLVL_RDY14_set/clr ,Transfer Group Completed Interrupt Level 14" "INT0,INT1" textline " " setclrfld.long 0x00 29. 0x00 29. 0x04 29. " INTLVL_RDY13_set/clr ,Transfer Group Completed Interrupt Level 13" "INT0,INT1" setclrfld.long 0x00 28. 0x00 28. 0x04 28. " INTLVL_RDY12_set/clr ,Transfer Group Completed Interrupt Level 12" "INT0,INT1" textline " " setclrfld.long 0x00 27. 0x00 27. 0x04 27. " INTLVL_RDY11_set/clr ,Transfer Group Completed Interrupt Level 11" "INT0,INT1" setclrfld.long 0x00 26. 0x00 26. 0x04 26. " INTLVL_RDY10_set/clr ,Transfer Group Completed Interrupt Level 10" "INT0,INT1" textline " " setclrfld.long 0x00 25. 0x00 25. 0x04 25. " INTLVL_RDY9_set/clr ,Transfer Group Completed Interrupt Level Set 9" "INT0,INT1" setclrfld.long 0x00 24. 0x00 24. 0x04 24. " INTLVL_RDY8_set/clr ,Transfer Group Completed Interrupt Level Set 8" "INT0,INT1" textline " " endif setclrfld.long 0x00 23. 0x00 23. 0x04 23. " INTLVL_RDY7_set/clr ,Transfer Group Completed Interrupt Level Set 7" "INT0,INT1" setclrfld.long 0x00 22. 0x00 22. 0x04 22. " INTLVL_RDY6_set/clr ,Transfer Group Completed Interrupt Level Set 6" "INT0,INT1" textline " " setclrfld.long 0x00 21. 0x00 21. 0x04 21. " INTLVL_RDY5_set/clr ,Transfer Group Completed Interrupt Level Set 5" "INT0,INT1" setclrfld.long 0x00 20. 0x00 20. 0x04 20. " INTLVL_RDY4_set/clr ,Transfer Group Completed Interrupt Level Set 4" "INT0,INT1" textline " " setclrfld.long 0x00 19. 0x00 19. 0x04 19. " INTLVL_RDY3_set/clr ,Transfer Group Completed Interrupt Level Set 3" "INT0,INT1" setclrfld.long 0x00 18. 0x00 18. 0x04 18. " INTLVL_RDY2_set/clr ,Transfer Group Completed Interrupt Level Set 2" "INT0,INT1" textline " " setclrfld.long 0x00 17. 0x00 17. 0x04 17. " INTLVL_RDY1_set/clr ,Transfer Group Completed Interrupt Level Set 1" "INT0,INT1" setclrfld.long 0x00 16. 0x00 16. 0x04 16. " INTLVL_RDY0_set/clr ,Transfer Group Completed Interrupt Level Set 0" "INT0,INT1" textline " " sif cpu()!=("TMS570PSFC61")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE") setclrfld.long 0x00 15. 0x00 15. 0x04 15. " INTLVL_SUS15_set/clr ,Transfer Group Suspended Interrupt Level Set 15" "INT0,INT1" setclrfld.long 0x00 14. 0x00 14. 0x04 14. " INTLVL_SUS14_set/clr ,Transfer Group Suspended Interrupt Level Set 14" "INT0,INT1" textline " " setclrfld.long 0x00 13. 0x00 13. 0x04 13. " INTLVL_SUS13_set/clr ,Transfer Group Suspended Interrupt Level Set 13" "INT0,INT1" setclrfld.long 0x00 12. 0x00 12. 0x04 12. " INTLVL_SUS12_set/clr ,Transfer Group Suspended Interrupt Level Set 12" "INT0,INT1" textline " " setclrfld.long 0x00 11. 0x00 11. 0x04 11. " INTLVL_SUS11_set/clr ,Transfer Group Suspended Interrupt Level Set 11" "INT0,INT1" setclrfld.long 0x00 10. 0x00 10. 0x04 10. " INTLVL_SUS10_set/clr ,Transfer Group Suspended Interrupt Level Set 10" "INT0,INT1" textline " " setclrfld.long 0x00 9. 0x00 9. 0x04 9. " INTLVL_SUS9_set/clr ,Transfer Group Suspended Interrupt Level Set 9" "INT0,INT1" setclrfld.long 0x00 8. 0x00 8. 0x04 8. " INTLVL_SUS8_set/clr ,Transfer Group Suspended Interrupt Level Set 8" "INT0,INT1" textline " " endif setclrfld.long 0x00 7. 0x00 7. 0x04 7. " INTLVL_SUS7_set/clr ,Transfer Group Suspended Interrupt Level Set 7" "INT0,INT1" setclrfld.long 0x00 6. 0x00 6. 0x04 6. " INTLVL_SUS6_set/clr ,Transfer Group Suspended Interrupt Level Set 6" "INT0,INT1" textline " " setclrfld.long 0x00 5. 0x00 5. 0x04 5. " INTLVL_SUS5_set/clr ,Transfer Group Suspended Interrupt Level Set 5" "INT0,INT1" setclrfld.long 0x00 4. 0x00 4. 0x04 4. " INTLVL_SUS4_set/clr ,Transfer Group Suspended Interrupt Level Set 4" "INT0,INT1" textline " " setclrfld.long 0x00 3. 0x00 3. 0x04 3. " INTLVL_SUS3_set/clr ,Transfer Group Suspended Interrupt Level Set 3" "INT0,INT1" setclrfld.long 0x00 2. 0x00 2. 0x04 2. " INTLVL_SUS2_set/clr ,Transfer Group Suspended Interrupt Level Set 2" "INT0,INT1" textline " " setclrfld.long 0x00 1. 0x00 1. 0x04 1. " INTLVL_SUS1_set/clr ,Transfer Group Suspended Interrupt Level Set 1" "INT0,INT1" setclrfld.long 0x00 0. 0x00 0. 0x04 0. " INTLVL_SUS0_set/clr ,Transfer Group Suspended Interrupt Level Set 0" "INT0,INT1" width 11. group.long 0x84++0x3 line.long 0x00 "TGINTFLAG,Transfer Group Interrupt Flag Register" sif cpu()!=("TMS570PSFC61")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE") eventfld.long 0x00 31. " INTFLGRDY15 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 30. " INTFLGRDY14 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 29. " INTFLGRDY13 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 28. " INTFLGRDY12 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 27. " INTFLGRDY11 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 26. " INTFLGRDY10 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 25. " INTFLGRDY9 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 24. " INTFLGRDY8 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt" textline " " endif eventfld.long 0x00 23. " INTFLGRDY7 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 22. " INTFLGRDY6 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 21. " INTFLGRDY5 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 20. " INTFLGRDY4 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 19. " INTFLGRDY3 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 18. " INTFLGRDY2 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 17. " INTFLGRDY1 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 16. " INTFLGRDY0 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt" textline " " sif cpu()!=("TMS570PSFC61")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE") eventfld.long 0x00 15. " INTFLGSUS15 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 14. " INTFLGSUS14 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 13. " INTFLGSUS13 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 12. " INTFLGSUS12 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 11. " INTFLGSUS11 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 10. " INTFLGSUS10 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 9. " INTFLGSUS9 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 8. " INTFLGSUS8 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt" textline " " endif eventfld.long 0x00 7. " INTFLGSUS7 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 6. " INTFLGSUS6 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 5. " INTFLGSUS5 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 4. " INTFLGSUS4 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " INTFLGSUS3 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 2. " INTFLGSUS2 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 1. " INTFLGSUS1 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 0. " INTFLGSUS0 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt" width 11. group.long 0x90++0x3 line.long 0x00 "TICKCNT,Tick Count Register" bitfld.long 0x00 31. " TICKENA ,Tick Counter Enable" "Disabled,Enabled" bitfld.long 0x00 30. " RELOAD ,Re-load Tick Counter" "No effect,Reload" textline " " bitfld.long 0x00 28.--29. " CLKCTRL ,Tick Counter Clock Source Control" "Format 0,Format 1,Format 2,Format 3" hexmask.long.word 0x00 0.--15. 1. " TICKVALUE ,Initial Value for Tick Counter" group.long 0x94++0x3 line.long 0x00 "LTGPEND,Last Transfer Group End Pointer" sif cpu()==("TMS570PSFC61")||cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10206-PGE") bitfld.long 0x00 24.--28. " TG_IN_SERVICE ,Transfer Group Currently Being Serviced by the Sequencer" "Not serviced,Group0,Group1,Group2,Group3,Group4,Group5,Group6,Group7,?..." else bitfld.long 0x00 24.--28. " TG_IN_SERVICE ,Transfer Group Currently Being Serviced by the Sequencer" "Not serviced,Group0,Group1,Group2,Group3,Group4,Group5,Group6,Group7,Group8,Group9,Group10,Group11,Group12,Group13,Group14,Group15,?..." endif hexmask.long.byte 0x00 8.--14. 1. " LPEND ,Last Transfer Group End Pointer" else hgroup.long 0x74++0x3 hide.long 0x00 "TGITENST,MibSPI Transfer Group Interrupt Enable Register" hgroup.long 0x7C++0x3 hide.long 0x00 "TGITLVST,MibSPI Transfer Group Interrupt Level Register" hgroup.long 0x84++0x3 hide.long 0x00 "TGINTFLAG,Transfer Group Interrupt Flag Register" hgroup.long 0x90++0x03 hide.long 0x00 "TICKCNT,Tick Count Register" hgroup.long 0x94++0x3 hide.long 0x00 "LTGPEND,Last Transfer Group End Pointer" endif width 9. tree "MibSPI Transfer Group Control Registers" if (((d.l((ad:0xFFF7F400+0x70)))&0x01)==0x01) sif (cpu()!="TMS570PSFC61")&&(cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")) group.long 0x98++0x3 line.long 0x00 "TG0CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA0 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT0 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST0 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD0 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT0 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC0 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART0 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT0 ,Transfer Group Pointer to Current Buffer" group.long 0x9C++0x3 line.long 0x00 "TG1CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA1 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT1 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST1 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD1 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT1 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC1 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART1 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT1 ,Transfer Group Pointer to Current Buffer" group.long 0xA0++0x3 line.long 0x00 "TG2CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA2 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT2 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST2 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD2 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT2 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC2 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART2 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT2 ,Transfer Group Pointer to Current Buffer" group.long 0xA4++0x3 line.long 0x00 "TG3CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA3 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT3 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST3 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD3 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT3 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC3 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART3 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT3 ,Transfer Group Pointer to Current Buffer" group.long 0xA8++0x3 line.long 0x00 "TG4CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA4 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT4 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST4 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD4 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT4 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC4 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART4 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT4 ,Transfer Group Pointer to Current Buffer" group.long 0xAC++0x3 line.long 0x00 "TG5CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA5 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT5 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST5 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD5 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT5 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC5 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART5 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT5 ,Transfer Group Pointer to Current Buffer" group.long 0xB0++0x3 line.long 0x00 "TG6CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA6 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT6 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST6 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD6 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT6 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC6 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART6 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT6 ,Transfer Group Pointer to Current Buffer" group.long 0xB4++0x3 line.long 0x00 "TG7CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA7 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT7 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST7 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD7 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT7 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC7 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART7 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT7 ,Transfer Group Pointer to Current Buffer" else group.long 0x98++0x3 line.long 0x00 "TG0CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA0 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT0 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST0 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD0 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT0 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC0 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART0 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT0 ,Transfer Group Pointer to Current Buffer" group.long 0x9C++0x3 line.long 0x00 "TG1CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA1 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT1 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST1 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD1 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT1 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC1 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART1 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT1 ,Transfer Group Pointer to Current Buffer" group.long 0xA0++0x3 line.long 0x00 "TG2CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA2 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT2 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST2 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD2 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT2 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC2 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART2 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT2 ,Transfer Group Pointer to Current Buffer" group.long 0xA4++0x3 line.long 0x00 "TG3CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA3 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT3 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST3 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD3 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT3 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC3 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART3 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT3 ,Transfer Group Pointer to Current Buffer" group.long 0xA8++0x3 line.long 0x00 "TG4CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA4 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT4 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST4 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD4 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT4 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC4 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART4 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT4 ,Transfer Group Pointer to Current Buffer" group.long 0xAC++0x3 line.long 0x00 "TG5CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA5 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT5 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST5 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD5 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT5 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC5 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART5 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT5 ,Transfer Group Pointer to Current Buffer" group.long 0xB0++0x3 line.long 0x00 "TG6CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA6 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT6 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST6 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD6 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT6 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC6 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART6 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT6 ,Transfer Group Pointer to Current Buffer" group.long 0xB4++0x3 line.long 0x00 "TG7CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA7 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT7 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST7 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD7 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT7 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC7 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART7 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT7 ,Transfer Group Pointer to Current Buffer" group.long 0xB8++0x3 line.long 0x00 "TG8CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA8 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT8 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST8 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD8 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT8 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC8 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART8 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT8 ,Transfer Group Pointer to Current Buffer" group.long 0xBC++0x3 line.long 0x00 "TG9CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA9 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT9 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST9 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD9 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT9 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC9 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART9 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT9 ,Transfer Group Pointer to Current Buffer" group.long 0xC0++0x3 line.long 0x00 "TG10CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA10 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT10 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST10 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD10 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT10 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC10 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART10 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT10 ,Transfer Group Pointer to Current Buffer" group.long 0xC4++0x3 line.long 0x00 "TG11CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA11 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT11 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST11 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD11 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT11 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC11 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART11 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT11 ,Transfer Group Pointer to Current Buffer" group.long 0xC8++0x3 line.long 0x00 "TG12CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA12 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT12 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST12 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD12 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT12 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC12 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART12 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT12 ,Transfer Group Pointer to Current Buffer" group.long 0xCC++0x3 line.long 0x00 "TG13CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA13 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT13 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST13 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD13 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT13 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC13 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART13 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT13 ,Transfer Group Pointer to Current Buffer" group.long 0xD0++0x3 line.long 0x00 "TG14CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA14 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT14 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST14 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD14 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT14 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC14 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART14 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT14 ,Transfer Group Pointer to Current Buffer" group.long 0xD4++0x3 line.long 0x00 "TG15CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA15 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT15 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST15 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD15 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT15 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC15 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART15 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT15 ,Transfer Group Pointer to Current Buffer" endif else sif cpu()==("TMS570PSFC61")||cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10206-PGE") hgroup.long 0x98++0x3 hide.long 0x00 "TG0CTRL,MibSPI Transfer Group Control Register" hgroup.long 0x9C++0x3 hide.long 0x00 "TG1CTRL,MibSPI Transfer Group Control Register" hgroup.long 0xA0++0x3 hide.long 0x00 "TG2CTRL,MibSPI Transfer Group Control Register" hgroup.long 0xA4++0x3 hide.long 0x00 "TG3CTRL,MibSPI Transfer Group Control Register" hgroup.long 0xA8++0x3 hide.long 0x00 "TG4CTRL,MibSPI Transfer Group Control Register" hgroup.long 0xAC++0x3 hide.long 0x00 "TG5CTRL,MibSPI Transfer Group Control Register" hgroup.long 0xB0++0x3 hide.long 0x00 "TG6CTRL,MibSPI Transfer Group Control Register" hgroup.long 0xB4++0x3 hide.long 0x00 "TG7CTRL,MibSPI Transfer Group Control Register" else hgroup.long 0x98++0x3 hide.long 0x00 "TG0CTRL,MibSPI Transfer Group Control Register" hgroup.long 0x9C++0x3 hide.long 0x00 "TG1CTRL,MibSPI Transfer Group Control Register" hgroup.long 0xA0++0x3 hide.long 0x00 "TG2CTRL,MibSPI Transfer Group Control Register" hgroup.long 0xA4++0x3 hide.long 0x00 "TG3CTRL,MibSPI Transfer Group Control Register" hgroup.long 0xA8++0x3 hide.long 0x00 "TG4CTRL,MibSPI Transfer Group Control Register" hgroup.long 0xAC++0x3 hide.long 0x00 "TG5CTRL,MibSPI Transfer Group Control Register" hgroup.long 0xB0++0x3 hide.long 0x00 "TG6CTRL,MibSPI Transfer Group Control Register" hgroup.long 0xB4++0x3 hide.long 0x00 "TG7CTRL,MibSPI Transfer Group Control Register" hgroup.long 0xB8++0x3 hide.long 0x00 "TG8CTRL,MibSPI Transfer Group Control Register" hgroup.long 0xBC++0x3 hide.long 0x00 "TG9CTRL,MibSPI Transfer Group Control Register" hgroup.long 0xC0++0x3 hide.long 0x00 "TG10CTRL,MibSPI Transfer Group Control Register" hgroup.long 0xC4++0x3 hide.long 0x00 "TG11CTRL,MibSPI Transfer Group Control Register" hgroup.long 0xC8++0x3 hide.long 0x00 "TG12CTRL,MibSPI Transfer Group Control Register" hgroup.long 0xCC++0x3 hide.long 0x00 "TG13CTRL,MibSPI Transfer Group Control Register" hgroup.long 0xD0++0x3 hide.long 0x00 "TG14CTRL,MibSPI Transfer Group Control Register" hgroup.long 0xD4++0x3 hide.long 0x00 "TG15CTRL,MibSPI Transfer Group Control Register" endif endif tree.end width 17. if ((((d.l((ad:0xFFF7F400+0x4)))&0x1)==0x1)&&((d.l((ad:0xFFF7F400+0x70)))&0x1)==0x1) group.long 0xD8++0x3 line.long 0x00 "DMA0CTRL,MibSPI DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT0 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 0" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID0 ,Buffer Utilized for DMA Transfer 0" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP0 ,Receive Data DMA Request Map 0" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP0 ,Transmit Data DMA Channel 0" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA0 ,Receive Data DMA Channel Enable 0" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA0 ,Transmit Data DMA Channel Enable 0" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK0 ,Non-interleaved DMA Block Transfer 0" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT0 ,Initial Count of DMA Transfers 0" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT170 ,The 17th Bit of COUNT Field of DMA0COUNT Register" "Low,High" bitfld.long 0x00 0.--5. " COUNT0 ,Actual Number of Remaining DMA Transfer 0" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l((ad:0xFFF7F400+0x4)))&0x1)==0x0)&&((d.l((ad:0xFFF7F400+0x70)))&0x1)==0x1) group.long 0xD8++0x3 line.long 0x00 "DMA0CTRL,MibSPI DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT0 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 0" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID0 ,Buffer Utilized for DMA Transfer 0" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP0 ,Receive Data DMA Request Map 0" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP0 ,Transmit Data DMA Channel 0" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA0 ,Receive Data DMA Channel Enable 0" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA0 ,Transmit Data DMA Channel Enable 0" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT0 ,Initial Count of DMA Transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT170 ,The 17th Bit of COUNT Field of DMA0COUNT Register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT0 ,Actual Number of Remaining DMA Transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xD8++0x3 hide.long 0x00 "DMA0CTRL,MibSPI DMA Channel Control Register" endif if ((((d.l((ad:0xFFF7F400+0x4)))&0x1)==0x1)&&((d.l((ad:0xFFF7F400+0x70)))&0x1)==0x1) group.long 0xDC++0x3 line.long 0x00 "DMA1CTRL,MibSPI DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT1 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 1" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID1 ,Buffer Utilized for DMA Transfer 1" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP1 ,Receive Data DMA Request Map 1" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP1 ,Transmit Data DMA Channel 1" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA1 ,Receive Data DMA Channel Enable 1" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA1 ,Transmit Data DMA Channel Enable 1" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK1 ,Non-interleaved DMA Block Transfer 1" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT1 ,Initial Count of DMA Transfers 1" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT171 ,The 17th Bit of COUNT Field of DMA1COUNT Register" "Low,High" bitfld.long 0x00 0.--5. " COUNT1 ,Actual Number of Remaining DMA Transfer 1" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l((ad:0xFFF7F400+0x4)))&0x1)==0x0)&&((d.l((ad:0xFFF7F400+0x70)))&0x1)==0x1) group.long 0xDC++0x3 line.long 0x00 "DMA1CTRL,MibSPI DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT1 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 1" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID1 ,Buffer Utilized for DMA Transfer 1" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP1 ,Receive Data DMA Request Map 1" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP1 ,Transmit Data DMA Channel 1" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA1 ,Receive Data DMA Channel Enable 1" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA1 ,Transmit Data DMA Channel Enable 1" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT1 ,Initial Count of DMA Transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT171 ,The 17th Bit of COUNT Field of DMA1COUNT Register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT1 ,Actual Number of Remaining DMA Transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xDC++0x3 hide.long 0x00 "DMA1CTRL,MibSPI DMA Channel Control Register" endif if ((((d.l((ad:0xFFF7F400+0x4)))&0x1)==0x1)&&((d.l((ad:0xFFF7F400+0x70)))&0x1)==0x1) group.long 0xE0++0x3 line.long 0x00 "DMA2CTRL,MibSPI DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT2 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 2" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID2 ,Buffer Utilized for DMA Transfer 2" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP2 ,Receive Data DMA Request Map 2" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP2 ,Transmit Data DMA Channel 2" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA2 ,Receive Data DMA Channel Enable 2" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA2 ,Transmit Data DMA Channel Enable 2" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK2 ,Non-interleaved DMA Block Transfer 2" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT2 ,Initial Count of DMA Transfers 2" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT172 ,The 17th Bit of COUNT Field of DMA2COUNT Register" "Low,High" bitfld.long 0x00 0.--5. " COUNT2 ,Actual Number of Remaining DMA Transfer 2" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l((ad:0xFFF7F400+0x4)))&0x1)==0x0)&&((d.l((ad:0xFFF7F400+0x70)))&0x1)==0x1) group.long 0xE0++0x3 line.long 0x00 "DMA2CTRL,MibSPI DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT2 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 2" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID2 ,Buffer Utilized for DMA Transfer 2" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP2 ,Receive Data DMA Request Map 2" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP2 ,Transmit Data DMA Channel 2" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA2 ,Receive Data DMA Channel Enable 2" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA2 ,Transmit Data DMA Channel Enable 2" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT2 ,Initial Count of DMA Transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT172 ,The 17th Bit of COUNT Field of DMA2COUNT Register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT2 ,Actual Number of Remaining DMA Transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xE0++0x3 hide.long 0x00 "DMA2CTRL,MibSPI DMA Channel Control Register" endif if ((((d.l((ad:0xFFF7F400+0x4)))&0x1)==0x1)&&((d.l((ad:0xFFF7F400+0x70)))&0x1)==0x1) group.long 0xE4++0x3 line.long 0x00 "DMA3CTRL,MibSPI DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT3 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 3" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID3 ,Buffer Utilized for DMA Transfer 3" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP3 ,Receive Data DMA Request Map 3" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP3 ,Transmit Data DMA Channel 3" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA3 ,Receive Data DMA Channel Enable 3" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA3 ,Transmit Data DMA Channel Enable 3" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK3 ,Non-interleaved DMA Block Transfer 3" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT3 ,Initial Count of DMA Transfers 3" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT173 ,The 17th Bit of COUNT Field of DMA3COUNT Register" "Low,High" bitfld.long 0x00 0.--5. " COUNT3 ,Actual Number of Remaining DMA Transfer 3" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l((ad:0xFFF7F400+0x4)))&0x1)==0x0)&&((d.l((ad:0xFFF7F400+0x70)))&0x1)==0x1) group.long 0xE4++0x3 line.long 0x00 "DMA3CTRL,MibSPI DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT3 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 3" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID3 ,Buffer Utilized for DMA Transfer 3" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP3 ,Receive Data DMA Request Map 3" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP3 ,Transmit Data DMA Channel 3" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA3 ,Receive Data DMA Channel Enable 3" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA3 ,Transmit Data DMA Channel Enable 3" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT3 ,Initial Count of DMA Transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT173 ,The 17th Bit of COUNT Field of DMA3COUNT Register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT3 ,Actual Number of Remaining DMA Transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xE4++0x3 hide.long 0x00 "DMA3CTRL,MibSPI DMA Channel Control Register" endif if ((((d.l((ad:0xFFF7F400+0x4)))&0x1)==0x1)&&((d.l((ad:0xFFF7F400+0x70)))&0x1)==0x1) group.long 0xE8++0x3 line.long 0x00 "DMA4CTRL,MibSPI DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT4 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 4" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID4 ,Buffer Utilized for DMA Transfer 4" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP4 ,Receive Data DMA Request Map 4" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP4 ,Transmit Data DMA Channel 4" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA4 ,Receive Data DMA Channel Enable 4" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA4 ,Transmit Data DMA Channel Enable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK4 ,Non-interleaved DMA Block Transfer 4" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT4 ,Initial Count of DMA Transfers 4" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT174 ,The 17th Bit of COUNT Field of DMA4COUNT Register" "Low,High" bitfld.long 0x00 0.--5. " COUNT4 ,Actual Number of Remaining DMA Transfer 4" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l((ad:0xFFF7F400+0x4)))&0x1)==0x0)&&((d.l((ad:0xFFF7F400+0x70)))&0x1)==0x1) group.long 0xE8++0x3 line.long 0x00 "DMA4CTRL,MibSPI DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT4 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 4" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID4 ,Buffer Utilized for DMA Transfer 4" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP4 ,Receive Data DMA Request Map 4" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP4 ,Transmit Data DMA Channel 4" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA4 ,Receive Data DMA Channel Enable 4" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA4 ,Transmit Data DMA Channel Enable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT4 ,Initial Count of DMA Transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT174 ,The 17th Bit of COUNT Field of DMA4COUNT Register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT4 ,Actual Number of Remaining DMA Transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xE8++0x3 hide.long 0x00 "DMA4CTRL,MibSPI DMA Channel Control Register" endif if ((((d.l((ad:0xFFF7F400+0x4)))&0x1)==0x1)&&((d.l((ad:0xFFF7F400+0x70)))&0x1)==0x1) group.long 0xEC++0x3 line.long 0x00 "DMA5CTRL,MibSPI DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT5 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 5" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID5 ,Buffer Utilized for DMA Transfer 5" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP5 ,Receive Data DMA Request Map 5" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP5 ,Transmit Data DMA Channel 5" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA5 ,Receive Data DMA Channel Enable 5" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA5 ,Transmit Data DMA Channel Enable 5" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK5 ,Non-interleaved DMA Block Transfer 5" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT5 ,Initial Count of DMA Transfers 5" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT175 ,The 17th Bit of COUNT Field of DMA5COUNT Register" "Low,High" bitfld.long 0x00 0.--5. " COUNT5 ,Actual Number of Remaining DMA Transfer 5" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l((ad:0xFFF7F400+0x4)))&0x1)==0x0)&&((d.l((ad:0xFFF7F400+0x70)))&0x1)==0x1) group.long 0xEC++0x3 line.long 0x00 "DMA5CTRL,MibSPI DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT5 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 5" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID5 ,Buffer Utilized for DMA Transfer 5" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP5 ,Receive Data DMA Request Map 5" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP5 ,Transmit Data DMA Channel 5" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA5 ,Receive Data DMA Channel Enable 5" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA5 ,Transmit Data DMA Channel Enable 5" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT5 ,Initial Count of DMA Transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT175 ,The 17th Bit of COUNT Field of DMA5COUNT Register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT5 ,Actual Number of Remaining DMA Transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xEC++0x3 hide.long 0x00 "DMA5CTRL,MibSPI DMA Channel Control Register" endif if ((((d.l((ad:0xFFF7F400+0x4)))&0x1)==0x1)&&((d.l((ad:0xFFF7F400+0x70)))&0x1)==0x1) group.long 0xF0++0x3 line.long 0x00 "DMA6CTRL,MibSPI DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT6 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 6" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID6 ,Buffer Utilized for DMA Transfer 6" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP6 ,Receive Data DMA Request Map 6" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP6 ,Transmit Data DMA Channel 6" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA6 ,Receive Data DMA Channel Enable 6" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA6 ,Transmit Data DMA Channel Enable 6" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK6 ,Non-interleaved DMA Block Transfer 6" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT6 ,Initial Count of DMA Transfers 6" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT176 ,The 17th Bit of COUNT Field of DMA6COUNT Register" "Low,High" bitfld.long 0x00 0.--5. " COUNT6 ,Actual Number of Remaining DMA Transfer 6" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l((ad:0xFFF7F400+0x4)))&0x1)==0x0)&&((d.l((ad:0xFFF7F400+0x70)))&0x1)==0x1) group.long 0xF0++0x3 line.long 0x00 "DMA6CTRL,MibSPI DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT6 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 6" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID6 ,Buffer Utilized for DMA Transfer 6" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP6 ,Receive Data DMA Request Map 6" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP6 ,Transmit Data DMA Channel 6" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA6 ,Receive Data DMA Channel Enable 6" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA6 ,Transmit Data DMA Channel Enable 6" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT6 ,Initial Count of DMA Transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT176 ,The 17th Bit of COUNT Field of DMA6COUNT Register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT6 ,Actual Number of Remaining DMA Transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xF0++0x3 hide.long 0x00 "DMA6CTRL,MibSPI DMA Channel Control Register" endif if ((((d.l((ad:0xFFF7F400+0x4)))&0x1)==0x1)&&((d.l((ad:0xFFF7F400+0x70)))&0x1)==0x1) group.long 0xF4++0x3 line.long 0x00 "DMA7CTRL,MibSPI DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT7 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 7" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID7 ,Buffer Utilized for DMA Transfer 7" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP7 ,Receive Data DMA Request Map 7" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP7 ,Transmit Data DMA Channel 7" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA7 ,Receive Data DMA Channel Enable 7" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA7 ,Transmit Data DMA Channel Enable 7" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK7 ,Non-interleaved DMA Block Transfer 7" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT7 ,Initial Count of DMA Transfers 7" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT177 ,The 17th Bit of COUNT Field of DMA7COUNT Register" "Low,High" bitfld.long 0x00 0.--5. " COUNT7 ,Actual Number of Remaining DMA Transfer 7" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l((ad:0xFFF7F400+0x4)))&0x1)==0x0)&&((d.l((ad:0xFFF7F400+0x70)))&0x1)==0x1) group.long 0xF4++0x3 line.long 0x00 "DMA7CTRL,MibSPI DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT7 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 7" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID7 ,Buffer Utilized for DMA Transfer 7" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP7 ,Receive Data DMA Request Map 7" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP7 ,Transmit Data DMA Channel 7" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA7 ,Receive Data DMA Channel Enable 7" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA7 ,Transmit Data DMA Channel Enable 7" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT7 ,Initial Count of DMA Transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT177 ,The 17th Bit of COUNT Field of DMA7COUNT Register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT7 ,Actual Number of Remaining DMA Transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xF4++0x3 hide.long 0x00 "DMA7CTRL,MibSPI DMA Channel Control Register" endif if (((d.l((ad:0xFFF7F400+0x70)))&0x01)==0x01) group.long 0xF8++0x3 line.long 0x00 "DMA0COUNT,ICOUNT Register 0" hexmask.long.word 0x00 16.--31. 1. " ICOUNT0 ,Initial Number of DMA Transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT0 ,Actual Number of Remaining DMA Transfer" else hgroup.long 0xF8++0x3 hide.long 0x00 "DMA0COUNT,ICOUNT Register 0" endif if (((d.l((ad:0xFFF7F400+0x70)))&0x01)==0x01) group.long 0xFC++0x3 line.long 0x00 "DMA1COUNT,ICOUNT Register 1" hexmask.long.word 0x00 16.--31. 1. " ICOUNT1 ,Initial Number of DMA Transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT1 ,Actual Number of Remaining DMA Transfer" else hgroup.long 0xFC++0x3 hide.long 0x00 "DMA1COUNT,ICOUNT Register 1" endif if (((d.l((ad:0xFFF7F400+0x70)))&0x01)==0x01) group.long 0x100++0x3 line.long 0x00 "DMA2COUNT,ICOUNT Register 2" hexmask.long.word 0x00 16.--31. 1. " ICOUNT2 ,Initial Number of DMA Transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT2 ,Actual Number of Remaining DMA Transfer" else hgroup.long 0x100++0x3 hide.long 0x00 "DMA2COUNT,ICOUNT Register 2" endif if (((d.l((ad:0xFFF7F400+0x70)))&0x01)==0x01) group.long 0x104++0x3 line.long 0x00 "DMA3COUNT,ICOUNT Register 3" hexmask.long.word 0x00 16.--31. 1. " ICOUNT3 ,Initial Number of DMA Transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT3 ,Actual Number of Remaining DMA Transfer" else hgroup.long 0x104++0x3 hide.long 0x00 "DMA3COUNT,ICOUNT Register 3" endif if (((d.l((ad:0xFFF7F400+0x70)))&0x01)==0x01) group.long 0x108++0x3 line.long 0x00 "DMA4COUNT,ICOUNT Register 4" hexmask.long.word 0x00 16.--31. 1. " ICOUNT4 ,Initial Number of DMA Transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT4 ,Actual Number of Remaining DMA Transfer" else hgroup.long 0x108++0x3 hide.long 0x00 "DMA4COUNT,ICOUNT Register 4" endif if (((d.l((ad:0xFFF7F400+0x70)))&0x01)==0x01) group.long 0x10C++0x3 line.long 0x00 "DMA5COUNT,ICOUNT Register 5" hexmask.long.word 0x00 16.--31. 1. " ICOUNT5 ,Initial Number of DMA Transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT5 ,Actual Number of Remaining DMA Transfer" else hgroup.long 0x10C++0x3 hide.long 0x00 "DMA5COUNT,ICOUNT Register 5" endif if (((d.l((ad:0xFFF7F400+0x70)))&0x01)==0x01) group.long 0x110++0x3 line.long 0x00 "DMA6COUNT,ICOUNT Register 6" hexmask.long.word 0x00 16.--31. 1. " ICOUNT6 ,Initial Number of DMA Transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT6 ,Actual Number of Remaining DMA Transfer" else hgroup.long 0x110++0x3 hide.long 0x00 "DMA6COUNT,ICOUNT Register 6" endif if (((d.l((ad:0xFFF7F400+0x70)))&0x01)==0x01) group.long 0x114++0x3 line.long 0x00 "DMA7COUNT,ICOUNT Register 7" hexmask.long.word 0x00 16.--31. 1. " ICOUNT7 ,Initial Number of DMA Transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT7 ,Actual Number of Remaining DMA Transfer" else hgroup.long 0x114++0x3 hide.long 0x00 "DMA7COUNT,ICOUNT Register 7" endif if (((d.l((ad:0xFFF7F400+0x70)))&0x01)==0x01) group.long 0x118++0x3 line.long 0x00 "DMACNTLEN,DMA LARGE COUNT Register" bitfld.long 0x00 0. " LARGE_COUNT ,Large Count" "Modified,Not modified" group.long 0x120++0x3 line.long 0x00 "UERRCTRL,Uncorrectable Parity Error Control Register" bitfld.long 0x00 8. " PTESTEN ,Parity Memory Test Enable" "Disabled,Enabled" bitfld.long 0x00 0.--3. " EDEN ,Error Detection Enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" hgroup.long 0x124++0x3 hide.long 0x00 "UERRSTAT,Uncorrectable Parity Error Status Register" in hgroup.long 0x128++0x3 hide.long 0x00 "UERRADDR1,Uncorrectable Parity Error Address Register" in hgroup.long 0x12c++0x3 hide.long 0x00 "UERRADDR0,Uncorrectable Parity Error Address Register" in hgroup.long 0x130++0x3 hide.long 0x00 "RXOVRN_BUF_ADDR,Receive RAM Overrun Buffer Address Register" in else hgroup.long 0x118++0x3 hide.long 0x00 "DMACNTLEN,DMA LARGE COUNT Register" hgroup.long 0x120++0x3 hide.long 0x00 "UERRCTRL,Uncorrectable Parity Error Control Register" hgroup.long 0x124++0x3 hide.long 0x00 "UERRSTAT,Uncorrectable Parity Error Status Register" hgroup.long 0x128++0x3 hide.long 0x00 "UERRADDR1,Uncorrectable Parity Error Address Register" hgroup.long 0x12c++0x3 hide.long 0x00 "UERRADDR0,Uncorrectable Parity Error Address Register" hgroup.long 0x130++0x3 hide.long 0x00 "RXOVRN_BUF_ADDR,Receive RAM Overrun Buffer Address Register" endif tree.end width 13. if ((((d.l((ad:0xFFF7F400+0x0134)))&0x0f00)==0x0a00)&&(((d.l((ad:0xFFF7F400+0x0134)))&0x02)==0x02)) group.long 0x134++0x3 line.long 0x00 "IOLPBKTSTCR,SPI/MibSPI IO Loopback Test Control Register" bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O Loopback Test Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" eventfld.long 0x00 24. " SCS_FAIL_FLG ,Analog Loopback /SPISCS Pin Compare Failure" "Not failed,Failed" textline " " bitfld.long 0x00 20. " CTRL_BITERR ,Inducing of BITERR During IO Loopback Test Mode Control" "Not affected,Flipped" bitfld.long 0x00 19. " CTRL_DESYNC ,Inducing of DESYNC Error During IO Loopback Test Mode Control" "Not affected,Forced to 0" textline " " bitfld.long 0x00 18. " CTRL_PARERR ,Inducing of Parity Error During IO Loopback Test Mode Control" "Not affected,Flipped" bitfld.long 0x00 17. " CTRL_TIMEOUT ,Inducing of TIMEOUT Error During IO Loopback Test Mode Control" "Not affected,Forced to 1" textline " " bitfld.long 0x00 16. " CTRL_DLENERR ,Inducing of Data Length Error During IO Loopback Test Mode Control" "Not affected,Forced to 1" bitfld.long 0x00 3.--5. " ERR_SCS_PIN ,Error on Chip Select Pin Injection" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]" textline " " bitfld.long 0x00 2. " CTRL_SCS_PIN_ERR ,/SPISCS[7:0] Pins Error Injection Enable Control" "Disabled,Enabled" bitfld.long 0x00 1. " LPBK_TYPE ,Module IO Loopback Type" "Digital,Analog" textline " " bitfld.long 0x00 0. " RXP_ENA ,Module Analog Loopback Through Receive Pin Enable" "Transmit,Receive" elif ((((data.long((ad:0xFFF7F400+0x0134)))&0x0f00)==0x0a00)&&(((data.long((ad:0xFFF7F400+0x0134)))&0x02)==0x00)) group.long 0x134++0x3 line.long 0x00 "IOLPBKTSTCR,SPI/MibSPI IO Loopback Test Control Register" bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O Loopback Test Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" eventfld.long 0x00 24. " SCS_FAIL_FLG ,Analog Loopback /SPISCS Pin Compare Failure" "Not failed,Failed" textline " " bitfld.long 0x00 20. " CTRL_BITERR ,Inducing of BITERR During IO Loopback Test Mode Control" "Not affected,Flipped" bitfld.long 0x00 19. " CTRL_DESYNC ,Inducing of DESYNC Error During IO Loopback Test Mode Control" "Not affected,Forced to 0" textline " " bitfld.long 0x00 18. " CTRL_PARERR ,Inducing of Parity Error During IO Loopback Test Mode Control" "Not affected,Flipped" bitfld.long 0x00 17. " CTRL_TIMEOUT ,Inducing of TIMEOUT Error During IO Loopback Test Mode Control" "Not affected,Forced to 1" textline " " bitfld.long 0x00 16. " CTRL_DLENERR ,Inducing of Data Length Error During IO Loopback Test Mode Control" "Not affected,Forced to 1" bitfld.long 0x00 3.--5. " ERR_SCS_PIN ,Error on Chip Select Pin Injection" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]" textline " " bitfld.long 0x00 2. " CTRL_SCS_PIN_ERR ,/SPISCS[7:0] Pins Error Injection Enable Control" "Disabled,Enabled" bitfld.long 0x00 1. " LPBK_TYPE ,Module IO Loopback Type" "Digital,Analog" else group.long 0x134++0x3 line.long 0x00 "IOLPBKTSTCR,SPI/MibSPI IO Loopback Test Control Register" bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O Loopback Test Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" endif width 0xb tree.end tree "MIBSPI3" base ad:0xFFF7F800 width 6. group.long 0x00++0x3 line.long 0x0 "GCR0,Global Control Register 0" bitfld.long 0x00 0. " nRESET ,This is the Reset Bit for the Module" "Reset,No reset" if (((d.l((ad:0xFFF7F800+0x04)))&0x03)==0x03) group.long 0x04++0x3 line.long 0x0 "GCR1,Global Control Register 1" bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI Pin Direction Determination" "Input/output,Output/input" bitfld.long 0x00 24. " SPIEN ,SPI Enable" "Not active,Active" bitfld.long 0x00 16. " LOOP_BACK ,Internal Loop-back Test Mode" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " POWERDOWN ,SPI State Machines Power Down State Enable" "Active,Power down" bitfld.long 0x00 1. " CLKMOD ,Clock Mode" "External,Internal" elif (((d.l((ad:0xFFF7F800+0x04)))&0x03)==0x02) group.long 0x04++0x3 line.long 0x0 "GCR1,Global Control Register 1" bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI Pin Direction Determination" "Input/output,Output/input" bitfld.long 0x00 24. " SPIEN ,SPI Enable" "Not active,Active" bitfld.long 0x00 8. " POWERDOWN ,SPI State Machines Power Down State Enable" "Active,Power down" textline " " bitfld.long 0x00 1. " CLKMOD ,Clock Mode" "External,Internal" elif (((d.l((ad:0xFFF7F800+0x04)))&0x03)==0x01) group.long 0x04++0x3 line.long 0x0 "GCR1,Global Control Register 1" bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI Pin Direction Determination" "Input/output,Output/input" bitfld.long 0x00 24. " SPIEN ,SPI Enable" "Not active,Active" bitfld.long 0x00 8. " POWERDOWN ,SPI State Machines Power Down State Enable" "Active,Power down" textline " " bitfld.long 0x00 1. " CLKMOD ,Clock Mode" "External,Internal" else group.long 0x04++0x3 line.long 0x0 "GCR1,Global Control Register 1" bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI Pin Direction Determination" "Input/output,Output/input" bitfld.long 0x00 24. " SPIEN ,SPI Enable" "Not active,Active" bitfld.long 0x00 8. " POWERDOWN ,SPI State Machines Power Down State Enable" "Active,Power down" textline " " bitfld.long 0x00 1. " CLKMOD ,Clock Mode" "External,Internal" endif width 6. if (((d.l((ad:0xFFF7F800+0x04)))&0x01)==0x01) group.long 0x08++0x3 line.long 0x0 "INT0,Interrupt Register" bitfld.long 0x00 24. " ENABLE_HIGHZ ,/SPIENA Pin High-z Enable" "Disabled,Enabled" bitfld.long 0x00 16. " DMA_REQ_EN ,DMA Request Enable" "Not used,Generated" textline " " bitfld.long 0x00 9. " TXINTENA ,Transmit Interrupt Enable" "Not generated,Generated" bitfld.long 0x00 8. " RXINTENA ,Receive Interrupt Enable" "Not generated,Generated" textline " " bitfld.long 0x00 6. " RXOVRNINTENA ,Overrun Interrupt Enable" "Not generated,Generated" bitfld.long 0x00 4. " BITERRENA ,Enables Interrupt on Bit Error" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " DESYNCENA ,Enables Interrupt on De-synchronized Slave" "Disabled,Enabled" bitfld.long 0x00 2. " PARERRENA ,Enables Interrupt on Parity Error" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " TIMEOUTENA ,Enables Interrupt on ENA Signal Time-out" "Disabled,Enabled" bitfld.long 0x00 0. " DLEN_ERR_ENA ,Data Length Error Interrupt Enable" "Disabled,Enabled" else group.long 0x08++0x3 line.long 0x0 "INT0,Interrupt Register" bitfld.long 0x00 24. " ENABLE_HIGHZ ,/SPIENA Pin High-z Enable" "Disabled,Enabled" bitfld.long 0x00 16. " DMA_REQ_EN ,DMA Request Enable" "Not used,Generated" textline " " bitfld.long 0x00 9. " TXINTENA ,Transmit Interrupt Enable" "Not generated,Generated" bitfld.long 0x00 8. " RXINTENA ,Receive Interrupt Enable" "Not generated,Generated" textline " " bitfld.long 0x00 6. " RXOVRNINTENA ,Overrun Interrupt Enable" "Not generated,Generated" bitfld.long 0x00 4. " BITERRENA ,Enables Interrupt on Bit Error" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " PARERRENA ,Enables Interrupt on Parity Error" "Disabled,Enabled" bitfld.long 0x00 1. " TIMEOUTENA ,Enables Interrupt on ENA Signal Time-out" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " DLEN_ERR_ENA ,Data Length Error Interrupt Enable" "Disabled,Enabled" endif width 6. if (((d.l((ad:0xFFF7F800+0x04)))&0x01)==0x01) group.long 0x0C++0x3 line.long 0x0 "LVL,Interrupt Level Register" bitfld.long 0x00 9. " TXINTLVL ,Transmit Interrupt Level" "INT0,INT1" bitfld.long 0x00 8. " RXINTLVL ,Receive Interrupt level" "INT0,INT1" sif (cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")) bitfld.long 0x00 6. " OVRNINTLVL ,Receive Overrun Interrupt level" "INT0,INT1" else bitfld.long 0x00 6. " RXOVRNINTLVL ,Receive Overrun Interrupt level" "INT0,INT1" endif textline " " bitfld.long 0x00 4. " BITERRLVL ,Bit Error Interrupt level" "INT0,INT1" bitfld.long 0x00 3. " DESYNCLVL ,De-synchronized Slave Interrupt Level" "INT0,INT1" bitfld.long 0x00 2. " PARERRLVL ,Parity Error Interrupt Level" "INT0,INT1" textline " " bitfld.long 0x00 1. " TIMEOUTLVL ,/SPIENA Pin Time-out Interrupt Level" "INT0,INT1" bitfld.long 0x00 0. " DLEN_ERR_LVL ,Data Length Error Interrupt Enable Level" "INT0,INT1" else group.long 0x0C++0x3 line.long 0x0 "LVL,Interrupt Level Register" bitfld.long 0x00 9. " TXINTLVL ,Transmit Interrupt Level" "INT0,INT1" bitfld.long 0x00 8. " RXINTLVL ,Receive Interrupt level" "INT0,INT1" sif (cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")) bitfld.long 0x00 6. " OVRNINTLVL ,Receive Overrun Interrupt level" "INT0,INT1" else bitfld.long 0x00 6. " RXOVRNINTLVL ,Receive Overrun Interrupt level" "INT0,INT1" endif textline " " bitfld.long 0x00 4. " BITERRLVL ,Bit Error Interrupt level" "INT0,INT1" bitfld.long 0x00 2. " PARERRLVL ,Parity Error Interrupt Level" "INT0,INT1" bitfld.long 0x00 1. " TIMEOUTLVL ,/SPIENA Pin Time-out Interrupt Level" "INT0,INT1" textline " " bitfld.long 0x00 0. " DLEN_ERR_LVL ,Data Length Error Interrupt Enable Level" "INT0,INT1" endif width 6. if (((d.l((ad:0xFFF7F800+0x04)))&0x01)==0x01) group.long 0x10++0x3 line.long 0x0 "FLG,Flag Register" bitfld.long 0x00 24. " BUF_INIT_ACTIVE ,Multibuffer Initialization Active" "Finished,Not finished" bitfld.long 0x00 9. " TXINTFLG ,Transmitter Empty Interrupt Flag" "Full,Empty" textline " " eventfld.long 0x00 8. " RXINTFLG ,Receiver Full Interrupt Flag" "Empty,Full" eventfld.long 0x00 6. " RXOVRNINTFLG ,Receiver Overrun Flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 4. " BITERRFLG ,Internal Transmit Data and Transmitted Data Mismatch" "Not occurred,Occurred" eventfld.long 0x00 3. " DESYNCFLG ,Slave Device De-Synchronization" "Not detected,Detected" textline " " eventfld.long 0x00 2. " PARITYERRFLG ,Parity Error Flag" "Not detected,Detected" eventfld.long 0x00 1. " TIMEOUTFLG ,Time-out Due to Non-activation of ENA Signal" "Not occurred,Occurred" textline " " eventfld.long 0x00 0. " DLEN_ERR_FLG ,Data Length Error Flag" "Not occurred,Occurred" else group.long 0x10++0x3 line.long 0x0 "FLG,Flag Register" bitfld.long 0x00 24. " BUF_INIT_ACTIVE ,Multibuffer Initialization Active" "Not completed,Completed" bitfld.long 0x00 9. " TXINTFLG ,Transmitter Empty Interrupt Flag" "No empty,Empty" textline " " eventfld.long 0x00 8. " RXINTFLG ,Receiver Full Interrupt Flag" "No full,Full" eventfld.long 0x00 6. " RXOVRNINTFLG ,Receiver Overrun Flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 4. " BITERRFLG ,Internal Transmit Data and Transmitted Data Mismatch" "Not occurred,Occurred" eventfld.long 0x00 2. " PARITYERRFLG ,Parity Error Flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 1. " TIMEOUTFLG ,Time-out Due to Non-activation of ENA Signal" "Not occurred,Occurred" eventfld.long 0x00 0. " DLEN_ERR_FLG ,Data Length Error Flag" "Not occurred,Occurred" endif width 5. tree "SPI Pin Control Registers" tree "SPI Pin Control Registers 0-5" group.long 0x14++0x3 line.long 0x0 "PC0,Pin Control Register 0" bitfld.long 0x00 31. " SOMIFUN7 ,Slave Out Master in Function 7" "GPIO,SPI/MibSPI" bitfld.long 0x00 30. " SOMIFUN6 ,Slave Out Master in Function 6" "GPIO,SPI/MibSPI" bitfld.long 0x00 29. " SOMIFUN5 ,Slave Out Master in Function 5" "GPIO,SPI/MibSPI" textline " " bitfld.long 0x00 28. " SOMIFUN4 ,Slave Out Master in Function 4" "GPIO,SPI/MibSPI" bitfld.long 0x00 27. " SOMIFUN3 ,Slave Out Master in Function 3" "GPIO,SPI/MibSPI" bitfld.long 0x00 26. " SOMIFUN2 ,Slave Out Master in Function 2" "GPIO,SPI/MibSPI" textline " " bitfld.long 0x00 25. " SOMIFUN1 ,Slave Out Master in Function 1" "GPIO,SPI/MibSPI" bitfld.long 0x00 24. " SOMIFUN0 ,Slave Out Master in Function 0" "GPIO,SPI/MibSPI" bitfld.long 0x00 23. " SIMOFUN7 ,Slave In Master Out Function 7" "GPIO,SPI/MibSPI" textline " " bitfld.long 0x00 22. " SIMOFUN6 ,Slave In Master Out Function 6" "GPIO,SPI/MibSPI" bitfld.long 0x00 21. " SIMOFUN5 ,Slave In Master Out Function 5" "GPIO,SPI/MibSPI" bitfld.long 0x00 20. " SIMOFUN4 ,Slave In Master Out Function 4" "GPIO,SPI/MibSPI" textline " " bitfld.long 0x00 19. " SIMOFUN3 ,Slave In Master Out Function 3" "GPIO,SPI/MibSPI" bitfld.long 0x00 18. " SIMOFUN2 ,Slave In Master Out Function 2" "GPIO,SPI/MibSPI" bitfld.long 0x00 17. " SIMOFUN1 ,Slave In Master Out Function 1" "GPIO,SPI/MibSPI" textline " " bitfld.long 0x00 16. " SIMOFUN0 ,Slave In Master Out Function 0" "GPIO,SPI/MibSPI" bitfld.long 0x00 11. " SOMIFUN0 ,Slave Out Master In Function" "GPIO,SPI/MibSPI" bitfld.long 0x00 10. " SIMOFUN0 ,Slave In Master Out Function" "GPIO,SPI/MibSPI" textline " " bitfld.long 0x00 9. " CLKFUN ,SPI/MibSPI Clock Function" "GPIO,SPI/MibSPI" bitfld.long 0x00 8. " ENAFUN ,/SPIENA function" "GPIO,SPI/MibSPI" bitfld.long 0x00 7. " SCSFUN7 ,/SPISCS7 Function" "GPIO,SPI" textline " " bitfld.long 0x00 6. " SCSFUN6 ,/SPISCS6 Function" "GPIO,SPI" bitfld.long 0x00 5. " SCSFUN5 ,/SPISCS5 Function" "GPIO,SPI" bitfld.long 0x00 4. " SCSFUN4 ,/SPISCS4 Function" "GPIO,SPI" textline " " bitfld.long 0x00 3. " SCSFUN3 ,/SPISCS3 Function" "GPIO,SPI" bitfld.long 0x00 2. " SCSFUN2 ,/SPISCS2 Function" "GPIO,SPI" bitfld.long 0x00 1. " SCSFUN1 ,/SPISCS1 Function" "GPIO,SPI" textline " " bitfld.long 0x00 0. " SCSFUN0 ,/SPISCS0 Function" "GPIO,SPI" group.long 0x18++0x3 line.long 0x0 "PC1,Pin Control Register 1" bitfld.long 0x00 31. " SOMIDIR7 ,SPISOMI7 Direction" "Input,Output" bitfld.long 0x00 30. " SOMIDIR6 ,SPISOMI6 Direction" "Input,Output" bitfld.long 0x00 29. " SOMIDIR5 ,SPISOMI5 Direction" "Input,Output" textline " " bitfld.long 0x00 28. " SOMIDIR4 ,SPISOMI4 Direction" "Input,Output" bitfld.long 0x00 27. " SOMIDIR3 ,SPISOMI3 Direction" "Input,Output" bitfld.long 0x00 26. " SOMIDIR2 ,SPISOMI2 Direction" "Input,Output" textline " " bitfld.long 0x00 25. " SOMIDIR1 ,SPISOMI1 Direction" "Input,Output" bitfld.long 0x00 24. " SOMIDIR0 ,SPISOMI0 Direction" "Input,Output" bitfld.long 0x00 23. " SIMODIR7 ,SPISIMO7 Direction" "Input,Output" textline " " bitfld.long 0x00 22. " SIMODIR6 ,SPISIMO6 Direction" "Input,Output" bitfld.long 0x00 21. " SIMODIR5 ,SPISIMO5 Direction" "Input,Output" bitfld.long 0x00 20. " SIMODIR4 ,SPISIMO4 Direction" "Input,Output" textline " " bitfld.long 0x00 19. " SIMODIR3 ,SPISIMO3 Direction" "Input,Output" bitfld.long 0x00 18. " SIMODIR2 ,SPISIMO2 Direction" "Input,Output" bitfld.long 0x00 17. " SIMODIR1 ,SPISIMO1 Direction" "Input,Output" textline " " bitfld.long 0x00 16. " SIMODIR0 ,SPISIMO0 Direction" "Input,Output" bitfld.long 0x00 11. " SOMIDIR0 ,SPISOMI0 Direction" "Input,Output" bitfld.long 0x00 10. " SIMODIR0 ,SPISIMO0 Direction" "Input,Output" textline " " bitfld.long 0x00 9. " CLKDIR ,SPICLK Direction" "Input,Output" bitfld.long 0x00 8. " ENADIR ,/SPIENA Direction" "Input,Output" bitfld.long 0x00 7. " SCSDIR7 ,/SPISCS7 Direction" "Input,Output" textline " " bitfld.long 0x00 6. " SCSDIR6 ,/SPISCS6 Direction" "Input,Output" bitfld.long 0x00 5. " SCSDIR5 ,/SPISCS5 Direction" "Input,Output" bitfld.long 0x00 4. " SCSDIR4 ,/SPISCS4 Direction" "Input,Output" textline " " bitfld.long 0x00 3. " SCSDIR3 ,/SPISCS3 Direction" "Input,Output" bitfld.long 0x00 2. " SCSDIR2 ,/SPISCS2 Direction" "Input,Output" bitfld.long 0x00 1. " SCSDIR1 ,/SPISCS1 Direction" "Input,Output" textline " " bitfld.long 0x00 0. " SCSDIR0 ,/SPISCS0 Direction" "Input,Output" rgroup.long 0x1C++0x3 line.long 0x0 "PC2,Pin Control Register 2" bitfld.long 0x00 31. " SOMIDIN7 ,SPISOMI7 Data In" "Low,High" bitfld.long 0x00 30. " SOMIDIN6 ,SPISOMI6 Data In" "Low,High" bitfld.long 0x00 29. " SOMIDIN5 ,SPISOMI5 Data In" "Low,High" textline " " bitfld.long 0x00 28. " SOMIDIN4 ,SPISOMI4 Data In" "Low,High" bitfld.long 0x00 27. " SOMIDIN3 ,SPISOMI3 Data In" "Low,High" bitfld.long 0x00 26. " SOMIDIN2 ,SPISOMI2 Data In" "Low,High" textline " " bitfld.long 0x00 25. " SOMIDIN1 ,SPISOMI1 Data In" "Low,High" bitfld.long 0x00 24. " SOMIDIN0 ,SPISOMI0 Data In" "Low,High" bitfld.long 0x00 23. " SIMODIN7 ,SPISIMO7 Data In" "Low,High" textline " " bitfld.long 0x00 22. " SIMODIN6 ,SPISIMO6 Data In" "Low,High" bitfld.long 0x00 21. " SIMODIN5 ,SPISIMO5 Data In" "Low,High" bitfld.long 0x00 20. " SIMODIN4 ,SPISIMO4 Data In" "Low,High" textline " " bitfld.long 0x00 19. " SIMODIN3 ,SPISIMO3 Data In" "Low,High" bitfld.long 0x00 18. " SIMODIN2 ,SPISIMO2 Data In" "Low,High" bitfld.long 0x00 17. " SIMODIN1 ,SPISIMO1 Data In" "Low,High" textline " " bitfld.long 0x00 16. " SIMODIN0 ,SPISIMO0 Data In" "Low,High" bitfld.long 0x00 11. " SOMIDIN0 ,SPISOMI0 Data In" "Low,High" bitfld.long 0x00 10. " SIMODIN0 ,SPISIMO0 Data In" "Low,High" textline " " bitfld.long 0x00 9. " CLKDIN ,Clock Data In" "Low,High" bitfld.long 0x00 8. " ENADIN ,/SPIENA Data In" "Low,High" bitfld.long 0x00 7. " SCSDIN7 ,SPISCS7 Data In" "Low,High" textline " " bitfld.long 0x00 6. " SCSDIN6 ,SPISCS6 Data In" "Low,High" bitfld.long 0x00 5. " SCSDIN5 ,SPISCS5 Data In" "Low,High" bitfld.long 0x00 4. " SCSDIN4 ,SPISCS4 Data In" "Low,High" textline " " bitfld.long 0x00 3. " SCSDIN3 ,SPISCS3 Data In" "Low,High" bitfld.long 0x00 2. " SCSDIN2 ,SPISCS2 Data In" "Low,High" bitfld.long 0x00 1. " SCSDIN1 ,SPISCS1 Data In" "Low,High" textline " " bitfld.long 0x00 0. " SCSDIN0 ,SPISCS0 Data In" "Low,High" width 5. group.long 0x20++0x3 line.long 0x0 "PC3,Pin Control Register 3" setclrfld.long 0x00 31. 0x04 31. 0x08 31. " SOMIDOUT7_set/clr ,SPISOMI7 Dataout Write" "Low,High" setclrfld.long 0x00 30. 0x04 30. 0x08 30. " SOMIDOUT6_set/clr ,SPISOMI6 Dataout Write" "Low,High" textline " " setclrfld.long 0x00 29. 0x04 29. 0x08 29. " SOMIDOUT5_set/clr ,SPISOMI5 Dataout Write" "Low,High" setclrfld.long 0x00 28. 0x04 28. 0x08 28. " SOMIDOUT4_set/clr ,SPISOMI4 Dataout Write" "Low,High" textline " " setclrfld.long 0x00 27. 0x04 27. 0x08 27. " SOMIDOUT3_set/clr ,SPISOMI3 Dataout Write" "Low,High" setclrfld.long 0x00 26. 0x04 26. 0x08 26. " SOMIDOUT2_set/clr ,SPISOMI2 Dataout Write" "Low,High" textline " " setclrfld.long 0x00 25. 0x04 25. 0x08 25. " SOMIDOUT1_set/clr ,SPISOMI1 Dataout Write" "Low,High" setclrfld.long 0x00 24. 0x04 24. 0x08 24. " SOMIDOUT0_set/clr ,SPISOMI0 Dataout Write" "Low,High" textline " " setclrfld.long 0x00 23. 0x04 23. 0x08 23. " SIMODOUT7_set/clr ,SPISIMO7 Dataout Write" "Low,High" setclrfld.long 0x00 22. 0x04 22. 0x08 22. " SIMODOUT6_set/clr ,SPISIMO6 Dataout Write" "Low,High" textline " " setclrfld.long 0x00 21. 0x04 21. 0x08 21. " SIMODOUT5_set/clr ,SPISIMO5 Dataout Write" "Low,High" setclrfld.long 0x00 20. 0x04 20. 0x08 20. " SIMODOUT4_set/clr ,SPISIMO4 Dataout Write" "Low,High" textline " " setclrfld.long 0x00 19. 0x04 19. 0x08 19. " SIMODOUT3_set/clr ,SPISIMO3 Dataout Write" "Low,High" setclrfld.long 0x00 18. 0x04 18. 0x08 18. " SIMODOUT2_set/clr ,SPISIMO2 Dataout Write" "Low,High" textline " " setclrfld.long 0x00 17. 0x04 17. 0x08 17. " SIMODOUT1_set/clr ,SPISIMO1 Dataout Write" "Low,High" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " SIMODOUT0_set/clr ,SPISIMO0 Dataout Write" "Low,High" textline " " setclrfld.long 0x00 11. 0x04 11. 0x08 11. " SOMIDOUT0_set/clr ,SPISOMI0 Dataout Write" "Low,High" setclrfld.long 0x00 10. 0x04 10. 0x08 10. " SIMODOUT0_set/clr ,SPISIMO0 Dataout Write" "Low,High" textline " " setclrfld.long 0x00 9. 0x04 9. 0x08 9. " CLKDOUT_set/clr ,SPICLK Dataout Write" "Low,High" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " ENADOUT_set/clr ,/SPIENA Dataout Write" "Low,High" textline " " setclrfld.long 0x00 7. 0x04 7. 0x08 7. " SCSDOUT7_set/clr ,SPISCS7 Dataout Write" "Low,High" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " SCSDOUT6_set/clr ,SPISCS6 Dataout Write" "Low,High" textline " " setclrfld.long 0x00 5. 0x04 5. 0x08 5. " SCSDOUT5_set/clr ,SPISCS5 Dataout Write" "Low,High" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " SCSDOUT4_set/clr ,SPISCS4 Dataout Write" "Low,High" textline " " setclrfld.long 0x00 3. 0x04 3. 0x08 3. " SCSDOUT3_set/clr ,SPISCS3 Dataout Write" "Low,High" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " SCSDOUT2_set/clr ,SPISCS2 Dataout Write" "Low,High" textline " " setclrfld.long 0x00 1. 0x04 1. 0x08 1. " SCSDOUT1_set/clr ,SPISCS1 Dataout Write" "Low,High" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " SCSDOUT0_set/clr ,SPISCS0 Dataout Write" "Low,High" tree.end width 5. tree "SPI Pin Control Registers 6-8" group.long 0x2C++0x3 line.long 0x0 "PC6,Pin Control Register 1" bitfld.long 0x00 31. " SOMIPDR7 ,SPISOMI7 Open Drain Enable" "High,Tri-stated" bitfld.long 0x00 30. " SOMIPDR6 ,SPISOMI6 Open Drain Enable" "High,Tri-stated" bitfld.long 0x00 29. " SOMIPDR5 ,SPISOMI5 Open Drain Enable" "High,Tri-stated" textline " " bitfld.long 0x00 28. " SOMIPDR4 ,SPISOMI4 Open Drain Enable" "High,Tri-stated" bitfld.long 0x00 27. " SOMIPDR3 ,SPISOMI3 Open Drain Enable" "High,Tri-stated" bitfld.long 0x00 26. " SOMIPDR2 ,SPISOMI2 Open Drain Enable" "High,Tri-stated" textline " " bitfld.long 0x00 25. " SOMIPDR1 ,SPISOMI1 Open Drain Enable" "High,Tri-stated" bitfld.long 0x00 24. " SOMIPDR0 ,SPISOMI0 Open Drain Enable" "High,Tri-stated" bitfld.long 0x00 23. " SIMOPDR7 ,SPISIMO7 Open Drain Enable" "High,Tri-stated" textline " " bitfld.long 0x00 22. " SIMOPDR6 ,SPISIMO6 Open Drain Enable" "High,Tri-stated" bitfld.long 0x00 21. " SIMOPDR5 ,SPISIMO5 Open Drain Enable" "High,Tri-stated" bitfld.long 0x00 20. " SIMOPDR4 ,SPISIMO4 Open Drain Enable" "High,Tri-stated" textline " " bitfld.long 0x00 19. " SIMOPDR3 ,SPISIMO3 Open Drain Enable" "High,Tri-stated" bitfld.long 0x00 18. " SIMOPDR2 ,SPISIMO2 Open Drain Enable" "High,Tri-stated" bitfld.long 0x00 17. " SIMOPDR1 ,SPISIMO1 Open Drain Enable" "High,Tri-stated" textline " " bitfld.long 0x00 16. " SIMOPDR0 ,SPISIMO0 Open Drain Enable" "High,Tri-stated" bitfld.long 0x00 11. " SOMIPDR0 ,SPISOMI0 Open Drain Enable" "High,Tri-stated" bitfld.long 0x00 10. " SIMOPDR0 ,SPISIMO0 Open Drain Enable" "High,Tri-stated" textline " " bitfld.long 0x00 9. " CLKPDR ,SPICLK Open Drain Enable" "High,Tri-stated" bitfld.long 0x00 8. " ENAPDR ,/SPIENA Open Drain Enable" "High,Tri-stated" bitfld.long 0x00 7. " SCSPDR7 ,/SPISCS7 Open Drain" "High,Tri-stated" textline " " bitfld.long 0x00 6. " SCSPDR6 ,/SPISCS6 Open Drain" "High,Tri-stated" bitfld.long 0x00 5. " SCSPDR5 ,/SPISCS5 Open Drain" "High,Tri-stated" bitfld.long 0x00 4. " SCSPDR4 ,/SPISCS4 Open Drain" "High,Tri-stated" textline " " bitfld.long 0x00 3. " SCSPDR3 ,/SPISCS3 Open Drain" "High,Tri-stated" bitfld.long 0x00 2. " SCSPDR2 ,/SPISCS2 Open Drain" "High,Tri-stated" bitfld.long 0x00 1. " SCSPDR1 ,/SPISCS1 Open Drain" "High,Tri-stated" textline " " bitfld.long 0x00 0. " SCSPDR0 ,/SPISCS0 Open Drain" "High,Tri-stated" group.long 0x30++0x3 line.long 0x0 "PC7,Pin Control Register 7" bitfld.long 0x00 31. " SOMIPDIS7 ,SPISOMI7 Pull Control Enable/Disable" "Enabled,Disabled" bitfld.long 0x00 30. " SOMIPDIS6 ,SPISOMI6 Pull Control Enable/Disable" "Enabled,Disabled" bitfld.long 0x00 29. " SOMIPDIS5 ,SPISOMI5 Pull Control Enable/Disable" "Enabled,Disabled" textline " " bitfld.long 0x00 28. " SOMIPDIS4 ,SPISOMI4 Pull Control Enable/Disable" "Enabled,Disabled" bitfld.long 0x00 27. " SOMIPDIS3 ,SPISOMI3 Pull Control Enable/Disable" "Enabled,Disabled" bitfld.long 0x00 26. " SOMIPDIS2 ,SPISOMI2 Pull Control Enable/Disable" "Enabled,Disabled" textline " " bitfld.long 0x00 25. " SOMIPDIS1 ,SPISOMI1 Pull Control Enable/Disable" "Enabled,Disabled" bitfld.long 0x00 24. " SOMIPDIS0 ,SPISOMI0 Pull Control Enable/Disable" "Enabled,Disabled" bitfld.long 0x00 23. " SIMOPDIS7 ,SPISIMO7 Pull Control Enable/Disable" "Enabled,Disabled" textline " " bitfld.long 0x00 22. " SIMOPDIS6 ,SPISIMO6 Pull Control Enable/Disable" "Enabled,Disabled" bitfld.long 0x00 21. " SIMOPDIS5 ,SPISIMO5 Pull Control Enable/Disable" "Enabled,Disabled" bitfld.long 0x00 20. " SIMOPDIS4 ,SPISIMO4 Pull Control Enable/Disable" "Enabled,Disabled" textline " " bitfld.long 0x00 19. " SIMOPDIS3 ,SPISIMO3 Pull Control Enable/Disable" "Enabled,Disabled" bitfld.long 0x00 18. " SIMOPDIS2 ,SPISIMO2 Pull Control Enable/Disable" "Enabled,Disabled" bitfld.long 0x00 17. " SIMOPDIS1 ,SPISIMO1 Pull Control Enable/Disable" "Enabled,Disabled" textline " " bitfld.long 0x00 16. " SIMOPDIS0 ,SPISIMO0 Pull Control Enable/Disable" "Enabled,Disabled" bitfld.long 0x00 11. " SOMIPDIS0 ,SPISOMI0 Pull Control Enable/Disable" "Enabled,Disabled" bitfld.long 0x00 10. " SIMOPDIS0 ,SPISIMO Pull Control Enable/Disable" "Enabled,Disabled" textline " " bitfld.long 0x00 9. " CLKPDIS ,SPICLK Pull Control Enable/Disable" "Enabled,Disabled" bitfld.long 0x00 8. " ENAPDIS ,SPIENA Pull Control Enable/Disable" "Enabled,Disabled" bitfld.long 0x00 7. " SCSPDIS7 ,SPISCS7 Pull Control Enable/Disable" "Enabled,Disabled" textline " " bitfld.long 0x00 6. " SCSPDIS6 ,SPISCS6 Pull Control Enable/Disable" "Enabled,Disabled" bitfld.long 0x00 5. " SCSPDIS5 ,SPISCS5 Pull Control Enable/Disable" "Enabled,Disabled" bitfld.long 0x00 4. " SCSPDIS4 ,SPISCS4 Pull Control Enable/Disable" "Enabled,Disabled" textline " " bitfld.long 0x00 3. " SCSPDIS3 ,SPISCS3 Pull Control Enable/Disable" "Enabled,Disabled" bitfld.long 0x00 2. " SCSPDIS2 ,SPISCS2 Pull Control Enable/Disable" "Enabled,Disabled" bitfld.long 0x00 1. " SCSPDIS1 ,SPISCS1 Pull Control Enable/Disable" "Enabled,Disabled" textline " " bitfld.long 0x00 0. " SCSPDIS0 ,SPISCS0 Pull Control Enable/Disable" "Enabled,Disabled" group.long 0x34++0x3 line.long 0x0 "PC8,Pin Control Register 8" bitfld.long 0x00 31. " SOMIPSEL7 ,SPISOMI7 Pull Select" "Pull down,Pull up" bitfld.long 0x00 30. " SOMIPSEL6 ,SPISOMI6 Pull Select" "Pull down,Pull up" bitfld.long 0x00 29. " SOMIPSEL5 ,SPISOMI5 Pull Select" "Pull down,Pull up" textline " " bitfld.long 0x00 28. " SOMIPSEL4 ,SPISOMI4 Pull Select" "Pull down,Pull up" bitfld.long 0x00 27. " SOMIPSEL3 ,SPISOMI3 Pull Select" "Pull down,Pull up" bitfld.long 0x00 26. " SOMIPSEL2 ,SPISOMI2 Pull Select" "Pull down,Pull up" textline " " bitfld.long 0x00 25. " SOMIPSEL1 ,SPISOMI1 Pull Select" "Pull down,Pull up" bitfld.long 0x00 24. " SOMIPSEL0 ,SPISOMI0 Pull Select" "Pull down,Pull up" bitfld.long 0x00 23. " SIMOPSEL7 ,SPISIMO7 Pull Select" "Pull down,Pull up" textline " " bitfld.long 0x00 22. " SIMOPSEL6 ,SPISIMO6 Pull Select" "Pull down,Pull up" bitfld.long 0x00 21. " SIMOPSEL5 ,SPISIMO5 Pull Select" "Pull down,Pull up" bitfld.long 0x00 20. " SIMOPSEL4 ,SPISIMO4 Pull Select" "Pull down,Pull up" textline " " bitfld.long 0x00 19. " SIMOPSEL3 ,SPISIMO3 Pull Select" "Pull down,Pull up" bitfld.long 0x00 18. " SIMOPSEL2 ,SPISIMO2 Pull Select" "Pull down,Pull up" bitfld.long 0x00 17. " SIMOPSEL1 ,SPISIMO1 Pull Select" "Pull down,Pull up" textline " " bitfld.long 0x00 16. " SIMOPSEL0 ,SPISIMO0 Pull Select" "Pull down,Pull up" bitfld.long 0x00 11. " SOMIPSEL ,SPISOMI Pull Select" "Pull down,Pull up" bitfld.long 0x00 10. " SIMOPSEL ,SPISIMO Pull Select" "Pull down,Pull up" textline " " bitfld.long 0x00 9. " CLKPSEL ,SPICLK Pull Select" "Pull down,Pull up" bitfld.long 0x00 8. " ENAPSEL ,SPIENA Pull Select" "Pull down,Pull up" bitfld.long 0x00 7. " SCSPSEL7 ,/SPISCS7 Pull select" "Pull down,Pull up" textline " " bitfld.long 0x00 6. " SCSPSEL6 ,/SPISCS6 Pull select" "Pull down,Pull up" bitfld.long 0x00 5. " SCSPSEL5 ,/SPISCS5 Pull select" "Pull down,Pull up" bitfld.long 0x00 4. " SCSPSEL4 ,/SPISCS4 Pull select" "Pull down,Pull up" textline " " bitfld.long 0x00 3. " SCSPSEL3 ,/SPISCS3 Pull select" "Pull down,Pull up" bitfld.long 0x00 2. " SCSPSEL2 ,/SPISCS2 Pull select" "Pull down,Pull up" bitfld.long 0x00 1. " SCSPSEL1 ,/SPISCS1 Pull select" "Pull down,Pull up" textline " " bitfld.long 0x00 0. " SCSPSEL0 ,/SPISCS0 Pull select" "Pull down,Pull up" tree.end tree.end width 7. if (((d.l((ad:0xFFF7F800+0x04)))&0x01000000)==0x01000000) group.long 0x38++0x3 line.long 0x0 "DAT0,Transmit Data Register 0" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,SPI / MibSPI Transmit Data" else rgroup.long 0x38++0x3 line.long 0x0 "DAT0,Transmit Data Register 0" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,SPI / MibSPI Transmit Data" endif if (((d.l((ad:0xFFF7F800+0x04)))&0x01)==0x01) group.long 0x3C++0x3 line.long 0x0 "DAT1,Transmit Data Register 1" bitfld.long 0x00 28. " CSHOLD ,Chip Select Hold Mode" "Not active,Active" bitfld.long 0x00 26. " WDEL ,Enable the Delay Counter at the End of the Current Transaction" "Disabled,Enabled" bitfld.long 0x00 24.--25. " DFSEL ,Data Word Format Select" "0,1,2,3" textline " " hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip Select Number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,SPI/MibSPI Transmit Data" else group.long 0x3C++0x3 line.long 0x0 "DAT1,Transmit Data Register 1" bitfld.long 0x00 24.--25. " DFSEL ,Data Word Format Select" "0,1,2,3" hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip Select Number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,SPI/MibSPI Transmit Data" endif hgroup.long 0x40++0x3 hide.long 0x0 "BUF,Receive Buffer Register" in width 7. if (((d.l((ad:0xFFF7F800+0x4)))&0x1)==0x1) rgroup.long 0x44++0x3 line.long 0x0 "EMU,Emulation Register" sif (cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")) bitfld.long 0x00 31. " RXEMPTY ,Receive Data Buffer Empty" "No empty,Empty" bitfld.long 0x00 30. " RXOVR ,Receive Data Buffer Overrun" "No overrun,Overrun" bitfld.long 0x00 29. " TXFULL ,Transmit Data Buffer Full" "Empty,Full" textline " " bitfld.long 0x00 28. " BITERR ,Mismatch of Internal Transmit Data and Transmitted Data" "Not occurred,Occurred" bitfld.long 0x00 27. " DESYNC ,De-synchronization of Slave Device" "No de-synchronized,De-synchronized" bitfld.long 0x00 26. " PARITYERR ,Calculated Parity Differs From Received Parity Bit" "No error,Error" textline " " bitfld.long 0x00 25. " TIMEOUT ,Time-out Due to Non-activation of ENA Pin" "Not occurred,Occurred" bitfld.long 0x00 24. " DLENERR ,Data Length Error Flag" "No error,Error" endif hexmask.long.byte 0x00 16.--23. 1. " LCSNR ,Last Chip Select Number" textline " " hexmask.long.word 0x00 0.--15. 1. " RXDATA ,SPI Receive Data" else rgroup.long 0x44++0x3 line.long 0x0 "EMU,Emulation Register" sif (cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")) bitfld.long 0x00 31. " RXEMPTY ,Receive Data Buffer Empty" "No empty,Empty" bitfld.long 0x00 30. " RXOVR ,Receive Data Buffer Overrun" "No overrun,Overrun" bitfld.long 0x00 29. " TXFULL ,Transmit Data Buffer Full" "Empty,Full" textline " " bitfld.long 0x00 28. " BITERR ,Mismatch of Internal Transmit Data and Transmitted Data" "Not occurred,Occurred" bitfld.long 0x00 26. " PARITYERR ,Calculated Parity Differs From Received Parity Bit" "No error,Error" bitfld.long 0x00 24. " DLENERR ,Data Length Error Flag" "No error,Error" textline " " endif hexmask.long.byte 0x00 16.--23. 1. " LCSNR ,Last Chip Select Number" hexmask.long.word 0x00 0.--15. 1. " RXDATA ,SPI Receive Data" endif if (((d.l((ad:0xFFF7F800+0x4)))&0x1)==0x1) group.long 0x48++0x3 line.long 0x0 "DELAY,Delay Register" hexmask.long.byte 0x00 24.--31. 1. " C2TDELAY ,Chip Select Active to Transmit Start Delay" hexmask.long.byte 0x00 16.--23. 1. " T2CDELAY ,Transmit End to Chip Select Inactive Delay" hexmask.long.byte 0x00 8.--15. 1. " T2EDELAY ,Transmit Data Finished to ENA Pin Inactive Time Out" textline " " hexmask.long.byte 0x00 0.--7. 1. " C2EDELAY ,Chip Select Active to ENA Signal Active Time Out" else hgroup.long 0x48++0x3 hide.long 0x0 "DELAY,Delay Register" endif width 7. group.long 0x4C++0x3 line.long 0x0 "DEF,Default Chip Select Register" bitfld.long 0x00 7. " CSDEF7 ,Chip Select Default Pattern 7" "Low,High" bitfld.long 0x00 6. " CSDEF6 ,Chip Select Default Pattern 6" "Low,High" bitfld.long 0x00 5. " CSDEF5 ,Chip Select Default Pattern 5" "Low,High" bitfld.long 0x00 4. " CSDEF4 ,Chip Select Default Pattern 4" "Low,High" textline " " bitfld.long 0x00 3. " CSDEF3 ,Chip Select Default Pattern 3" "Low,High" bitfld.long 0x00 2. " CSDEF2 ,Chip Select Default Pattern 2" "Low,High" bitfld.long 0x00 1. " CSDEF1 ,Chip Select Default Pattern 1" "Low,High" bitfld.long 0x00 0. " CSDEF0 ,Chip Select Default Pattern 0" "Low,High" width 6. tree "SPI Data Format Registers" group.long 0x50++0x3 line.long 0x0 "FMT0,Data Format Register 0" bitfld.long 0x00 24.--29. " WDELAY0 ,Delay in Between Transmissions For Data Format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " PARPOL0 ,Parity Polarity" "Even,Odd" bitfld.long 0x00 22. " PARITY0_ENA ,Parity Enable for Data Format 0" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " WAITENA0 ,Master Waits for ENA Signal From Slave for Data Format 0" "Not wait,Wait" bitfld.long 0x00 20. " SHIFTDIR0 ,Shift Direction for Data Format 0" "MSB,LSB" bitfld.long 0x00 18. " DIS_CS_TIMERS0 ,Disable Chipselect Timers for this Format Register" "No,Yes" textline " " bitfld.long 0x00 17. " POLARITY0 ,SPI Data Format 0 Clock Polarity" "Low-inactive,High-inactive" bitfld.long 0x00 16. " PHASE0 ,SPI Data Format 0 Clock Delay" "Not delayed,Delayed" hexmask.long.byte 0x00 8.--15. 1. " PRESCALE0 ,SPI Data Format 0 Prescaler" textline " " bitfld.long 0x00 0.--4. " CHARLEN0 ,SPI Data Format 0 Data Word Length" "Reserved,Reserved,2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..." group.long 0x54++0x3 line.long 0x0 "FMT1,Data Format Register 1" bitfld.long 0x00 24.--29. " WDELAY1 ,Delay in Between Transmissions For Data Format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " PARPOL1 ,Parity Polarity" "Even,Odd" bitfld.long 0x00 22. " PARITY1_ENA ,Parity Enable for Data Format 1" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " WAITENA1 ,Master Waits for ENA Signal From Slave for Data Format 1" "Not wait,Wait" bitfld.long 0x00 20. " SHIFTDIR1 ,Shift Direction for Data Format 1" "MSB,LSB" bitfld.long 0x00 18. " DIS_CS_TIMERS1 ,Disable Chipselect Timers for this Format Register" "No,Yes" textline " " bitfld.long 0x00 17. " POLARITY1 ,SPI Data Format 1 Clock Polarity" "Low-inactive,High-inactive" bitfld.long 0x00 16. " PHASE1 ,SPI Data Format 1 Clock Delay" "Not delayed,Delayed" hexmask.long.byte 0x00 8.--15. 1. " PRESCALE1 ,SPI Data Format 1 Prescaler" textline " " bitfld.long 0x00 0.--4. " CHARLEN1 ,SPI Data Format 1 Data Word Length" "Reserved,Reserved,2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..." group.long 0x58++0x3 line.long 0x0 "FMT2,Data Format Register 2" bitfld.long 0x00 24.--29. " WDELAY2 ,Delay in Between Transmissions For Data Format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " PARPOL2 ,Parity Polarity" "Even,Odd" bitfld.long 0x00 22. " PARITY2_ENA ,Parity Enable for Data Format 2" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " WAITENA2 ,Master Waits for ENA Signal From Slave for Data Format 2" "Not wait,Wait" bitfld.long 0x00 20. " SHIFTDIR2 ,Shift Direction for Data Format 2" "MSB,LSB" bitfld.long 0x00 18. " DIS_CS_TIMERS2 ,Disable Chipselect Timers for this Format Register" "No,Yes" textline " " bitfld.long 0x00 17. " POLARITY2 ,SPI Data Format 2 Clock Polarity" "Low-inactive,High-inactive" bitfld.long 0x00 16. " PHASE2 ,SPI Data Format 2 Clock Delay" "Not delayed,Delayed" hexmask.long.byte 0x00 8.--15. 1. " PRESCALE2 ,SPI Data Format 2 Prescaler" textline " " bitfld.long 0x00 0.--4. " CHARLEN2 ,SPI Data Format 2 Data Word Length" "Reserved,Reserved,2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..." group.long 0x5C++0x3 line.long 0x0 "FMT3,Data Format Register 3" bitfld.long 0x00 24.--29. " WDELAY3 ,Delay in Between Transmissions For Data Format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " PARPOL3 ,Parity Polarity" "Even,Odd" bitfld.long 0x00 22. " PARITY3_ENA ,Parity Enable for Data Format 3" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " WAITENA3 ,Master Waits for ENA Signal From Slave for Data Format 3" "Not wait,Wait" bitfld.long 0x00 20. " SHIFTDIR3 ,Shift Direction for Data Format 3" "MSB,LSB" bitfld.long 0x00 18. " DIS_CS_TIMERS3 ,Disable Chipselect Timers for this Format Register" "No,Yes" textline " " bitfld.long 0x00 17. " POLARITY3 ,SPI Data Format 3 Clock Polarity" "Low-inactive,High-inactive" bitfld.long 0x00 16. " PHASE3 ,SPI Data Format 3 Clock Delay" "Not delayed,Delayed" hexmask.long.byte 0x00 8.--15. 1. " PRESCALE3 ,SPI Data Format 3 Prescaler" textline " " bitfld.long 0x00 0.--4. " CHARLEN3 ,SPI Data Format 3 Data Word Length" "Reserved,Reserved,2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..." tree.end width 12. tree "SPI Interrupt Vector Registers" if (((d.l((ad:0xFFF7F800+0x70)))&0x01)==0x01) rgroup.long 0x60++0x3 line.long 0x0 "TGINTVECT0,Transfer Group Interrupt Vector Register 0" bitfld.long 0x00 1.--5. " INTVECT0 ,Interrupt Vector for Interrupt Line INT0" "No interrupt,Interrupt of transfer group 0,Interrupt of transfer group 1,Interrupt of transfer group 2,Interrupt of transfer group 3,Interrupt of transfer group 4,Interrupt of transfer group 5,Interrupt of transfer group 6,Interrupt of transfer group 7,Interrupt of transfer group 8,Interrupt of transfer group 9,Interrupt of transfer group 10,Interrupt of transfer group 11,Interrupt of transfer group 12,Interrupt of transfer group 13,Interrupt of transfer group 14,Interrupt of transfer group 15,Interrupt/SPIINT0,Reserved,RXORN Interrupt,?..." bitfld.long 0x00 0. " SUSPEND0 ,Transfer Suspended/Finished Interrupt" "Suspended,Finished" else rgroup.long 0x60++0x3 line.long 0x0 "TGINTVECT0,Transfer Group Interrupt Vector Register 0" bitfld.long 0x00 1.--5. " INTVECT0 ,Interrupt Vector for Interrupt Line INT0" "No interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Interrupt/SPIINT0,Receive Buffer Full Interrupt,Receive Buffer Overrun Interrupt,Transmit Buffer Empty Interrupt,?..." endif if (((d.l((ad:0xFFF7F800+0x70)))&0x01)==0x01) rgroup.long 0x64++0x3 line.long 0x0 "TGINTVECT1,Transfer Group Interrupt Vector Register 1" bitfld.long 0x00 1.--5. " INTVECT1 ,Interrupt Vector for Interrupt Line INT1" "No interrupt,Interrupt of transfer group 0,Interrupt of transfer group 1,Interrupt of transfer group 2,Interrupt of transfer group 3,Interrupt of transfer group 4,Interrupt of transfer group 5,Interrupt of transfer group 6,Interrupt of transfer group 7,Interrupt of transfer group 8,Interrupt of transfer group 9,Interrupt of transfer group 10,Interrupt of transfer group 11,Interrupt of transfer group 12,Interrupt of transfer group 13,Interrupt of transfer group 14,Interrupt of transfer group 15,Interrupt/SPIINT1,Reserved,RXORN Interrupt,?..." bitfld.long 0x00 0. " SUSPEND1 ,Transfer Suspended/Finished Interrupt" "Suspended,Finished" else rgroup.long 0x64++0x3 line.long 0x0 "TGINTVECT1,Transfer Group Interrupt Vector Register 1" bitfld.long 0x00 1.--5. " INTVECT1 ,Interrupt Vector for Interrupt Line INT1" "No interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Interrupt/SPIINT1,Receive Buffer Full Interrupt,Receive Buffer Overrun Interrupt,Transmit Buffer Empty Interrupt,?..." endif tree.end width 8. sif (cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")&&(cpu()!=("TMS570LS10116-PGE"))&&(cpu()!=("TMS570LS10216-PGE"))&&(cpu()!=("TMS570LS10116-ZWT"))&&(cpu()!=("TMS570LS10216-ZWT"))&&(cpu()!=("TMS570LS10106-PGE"))&&(cpu()!=("TMS570LS10206-PGE"))&&(cpu()!=("TMS570LS10106-ZWT"))&&(cpu()!=("TMS570LS10206-ZWT"))) group.long 0x68++0x3 line.long 0x0 "SRSEL,Pin Control Register 9" bitfld.long 0x00 31. " SPISOMISRS7 ,Controls the Slew Rate for the SPISOMI7" "Normal,Slow" bitfld.long 0x00 30. " SPISOMISRS6 ,Controls the Slew Rate for the SPISOMI6" "Normal,Slow" bitfld.long 0x00 29. " SPISOMISRS5 ,Controls the Slew Rate for the SPISOMI5" "Normal,Slow" textline " " bitfld.long 0x00 28. " SPISOMISRS4 ,Controls the Slew Rate for the SPISOMI4" "Normal,Slow" bitfld.long 0x00 27. " SPISOMISRS3 ,Controls the Slew Rate for the SPISOMI3" "Normal,Slow" bitfld.long 0x00 26. " SPISOMISRS2 ,Controls the Slew Rate for the SPISOMI2" "Normal,Slow" textline " " bitfld.long 0x00 25. " SPISOMISRS1 ,Controls the Slew Rate for the SPISOMI1" "Normal,Slow" bitfld.long 0x00 24. " SPISOMISRS0 ,Controls the Slew Rate for the SPISOMI0" "Normal,Slow" bitfld.long 0x00 23. " SPISIMOSRC7 ,Controls the Slew Rate for the SPISIMO7" "Normal,Slow" textline " " bitfld.long 0x00 22. " SPISIMOSRC6 ,Controls the Slew Rate for the SPISIMO6" "Normal,Slow" bitfld.long 0x00 21. " SPISIMOSRC5 ,Controls the Slew Rate for the SPISIMO5" "Normal,Slow" bitfld.long 0x00 20. " SPISIMOSRC4 ,Controls the Slew Rate for the SPISIMO4" "Normal,Slow" textline " " bitfld.long 0x00 19. " SPISIMOSRC3 ,Controls the Slew Rate for the SPISIMO3" "Normal,Slow" bitfld.long 0x00 18. " SPISIMOSRC2 ,Controls the Slew Rate for the SPISIMO2" "Normal,Slow" bitfld.long 0x00 17. " SPISIMOSRC1 ,Controls the Slew Rate for the SPISIMO1" "Normal,Slow" textline " " bitfld.long 0x00 16. " SPISIMOSRC0 ,Controls the Slew Rate for the SPISIMO0" "Normal,Slow" bitfld.long 0x00 11. " SPISOMISRS0 ,Controls the Slew Rate for SPISOMI0" "Normal,Slow" bitfld.long 0x00 10. " SPISIMOSRS0 ,Controls the Slew Rate for SPISIMO0" "Normal,Slow" textline " " bitfld.long 0x00 9. " SPICLKSRS ,Controls the Slew Rate for SPICLK" "Normal,Slow" bitfld.long 0x00 8. " SPIENASRS0 ,Controls the Slew Rate for /SPIENA" "Fast,Slow" bitfld.long 0x00 7. " SPISCSSRS7 ,Controls the Slew Rate for the /SPISCS7" "Normal,Slow" textline " " bitfld.long 0x00 6. " SPISCSSRS6 ,Controls the Slew Rate for the /SPISCS6" "Normal,Slow" bitfld.long 0x00 5. " SPISCSSRS5 ,Controls the Slew Rate for the /SPISCS5" "Normal,Slow" bitfld.long 0x00 4. " SPISCSSRS4 ,Controls the Slew Rate for the /SPISCS4" "Normal,Slow" textline " " bitfld.long 0x00 3. " SPISCSSRS3 ,Controls the Slew Rate for the /SPISCS3" "Normal,Slow" bitfld.long 0x00 2. " SPISCSSRS2 ,Controls the Slew Rate for the /SPISCS2" "Normal,Slow" bitfld.long 0x00 1. " SPISCSSRS1 ,Controls the Slew Rate for the /SPISCS1" "Normal,Slow" textline " " bitfld.long 0x00 0. " SPISCSSRS0 ,Controls the Slew Rate for the /SPISCS0" "Normal,Slow" endif if (((d.l((ad:0xFFF7F800+0x3c)))&0x03000000)==0x00) group.long 0x6c++0x03 line.long 0x00 "PMCTRL,Parallel/Modulo Mode Control Register" bitfld.long 0x00 5. " MOD_CLK_POL_0 ,Modulo Mode SPICLK Polarity" "Normal,Inverted" bitfld.long 0x00 2.--4. " MMODE_0 ,SPI Data Line Selection" "1-data,2-data,3-data,4-data,5-data,6-data,?..." sif (cpu()=="TMS570PSFC61") bitfld.long 0x00 0.--1. " PMODE_0 ,Parallel Mode" "1-data,2-data,4-data,?..." else bitfld.long 0x00 0.--1. " PMODE_0 ,Parallel Mode" "1-data,2-data,4-data,8-data" endif elif (((d.l((ad:0xFFF7F800+0x3c)))&0x03000000)==0x01000000) group.long 0x6c++0x03 line.long 0x00 "PMCTRL,Parallel/Modulo Mode Control Register" bitfld.long 0x00 13. " MOD_CLK_POL_1 ,Modulo Mode SPICLK Polarity" "Normal,Inverted" bitfld.long 0x00 10.--12. " MMODE_1 ,SPI Data Line Selection" "1-data,2-data,3-data,4-data,5-data,6-data,?..." sif (cpu()=="TMS570PSFC61") bitfld.long 0x00 8.--9. " PMODE_1 ,Parallel Mode" "1-data,2-data,4-data,?..." else bitfld.long 0x00 8.--9. " PMODE_1 ,Parallel Mode" "1-data,2-data,4-data,8-data" endif elif (((d.l((ad:0xFFF7F800+0x3c)))&0x03000000)==0x02000000) group.long 0x6c++0x03 line.long 0x00 "PMCTRL,Parallel/Modulo Mode Control Register" bitfld.long 0x00 21. " MOD_CLK_POL_2 ,Modulo Mode SPICLK Polarity" "Normal,Inverted" bitfld.long 0x00 18.--20. " MMODE_2 ,SPI Data Line Selection" "1-data,2-data,3-data,4-data,5-data,6-data,?..." sif (cpu()=="TMS570PSFC61") bitfld.long 0x00 16.--17. " PMODE_2 ,Parallel Mode" "1-data,2-data,4-data,?..." else bitfld.long 0x00 16.--17. " PMODE_2 ,Parallel Mode" "1-data,2-data,4-data,8-data" endif else group.long 0x6c++0x03 line.long 0x00 "PMCTRL,Parallel/Modulo Mode Control Register" bitfld.long 0x00 29. " MOD_CLK_POL_3 ,Modulo Mode SPICLK Polarity" "Normal,Inverted" bitfld.long 0x00 26.--28. " MMODE_3 ,SPI Data Line Selection" "1-data,2-data,3-data,4-data,5-data,6-data,?..." sif (cpu()=="TMS570PSFC61") bitfld.long 0x00 24.--25. " PMODE_3 ,Parallel Mode" "1-data,2-data,4-data,?..." else bitfld.long 0x00 24.--25. " PMODE_3 ,Parallel Mode" "1-data,2-data,4-data,8-data" endif endif width 11. tree "MibSPI Registers" group.long 0x70++0x3 line.long 0x0 "MIBSPIE,MibSPI Enable Register" bitfld.long 0x00 16. " RX_RAM_ACCESS ,Receive RAM Access Control Bit" "RX not writable,R/W" bitfld.long 0x00 0. " MSPIENA ,Multibuffer Mode Enable" "Disabled,Enabled" width 11. if (((d.l((ad:0xFFF7F800+0x70)))&0x01)==0x01) group.long 0x74++0x3 line.long 0x0 "TGITENST,MibSPI Transfer Group Interrupt Enable Register" sif cpu()!=("TMS570PSFC61")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE") setclrfld.long 0x00 31. 0x00 31. 0x04 31. " INTEN_RDY15_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x04 30. " INTEN_RDY14_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 29. 0x00 29. 0x04 29. " INTEN_RDY13_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x04 28. " INTEN_RDY12_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 27. 0x00 27. 0x04 27. " INTEN_RDY11_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x04 26. " INTEN_RDY10_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x04 25. " INTEN_RDY9_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x04 24. " INTEN_RDY8_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled" textline " " endif setclrfld.long 0x00 23. 0x00 23. 0x04 23. " INTEN_RDY7_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x04 22. " INTEN_RDY6_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 21. 0x00 21. 0x04 21. " INTEN_RDY5_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x04 20. " INTEN_RDY4_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x04 19. " INTEN_RDY3_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x04 18. " INTEN_RDY2_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 17. 0x00 17. 0x04 17. " INTEN_RDY1_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x04 16. " INTEN_RDY0_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled" textline " " sif cpu()!=("TMS570PSFC61")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE") setclrfld.long 0x00 15. 0x00 15. 0x04 15. " INTEN_SUS15_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x04 14. " INTEN_SUS14_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x04 13. " INTEN_SUS13_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x04 12. " INTEN_SUS12_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled" textline " " setclrfld.long 0x00 11. 0x00 11. 0x04 11. " INTEN_SUS11_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x04 10. " INTEN_SUS10_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled" textline " " setclrfld.long 0x00 9. 0x00 9. 0x04 9. " INTEN_SUS9_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x04 8. " INTEN_SUS8_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled" textline " " endif setclrfld.long 0x00 7. 0x00 7. 0x04 7. " INTEN_SUS7_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x04 6. " INTEN_SUS6_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. 0x00 5. 0x04 5. " INTEN_SUS5_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x04 4. " INTEN_SUS4_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled" textline " " setclrfld.long 0x00 3. 0x00 3. 0x04 3. " INTEN_SUS3_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x04 2. " INTEN_SUS2_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x04 1. " INTEN_SUS1_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x04 0. " INTEN_SUS0_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled" width 11. group.long 0x7c++0x3 line.long 0x00 "TGITLVST,MibSPI Transfer Group Interrupt Level Set Register" sif cpu()!=("TMS570PSFC61")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE") setclrfld.long 0x00 31. 0x00 31. 0x04 31. " INTLVL_RDY15_set/clr ,Transfer Group Completed Interrupt Level 15" "INT0,INT1" setclrfld.long 0x00 30. 0x00 30. 0x04 30. " INTLVL_RDY14_set/clr ,Transfer Group Completed Interrupt Level 14" "INT0,INT1" textline " " setclrfld.long 0x00 29. 0x00 29. 0x04 29. " INTLVL_RDY13_set/clr ,Transfer Group Completed Interrupt Level 13" "INT0,INT1" setclrfld.long 0x00 28. 0x00 28. 0x04 28. " INTLVL_RDY12_set/clr ,Transfer Group Completed Interrupt Level 12" "INT0,INT1" textline " " setclrfld.long 0x00 27. 0x00 27. 0x04 27. " INTLVL_RDY11_set/clr ,Transfer Group Completed Interrupt Level 11" "INT0,INT1" setclrfld.long 0x00 26. 0x00 26. 0x04 26. " INTLVL_RDY10_set/clr ,Transfer Group Completed Interrupt Level 10" "INT0,INT1" textline " " setclrfld.long 0x00 25. 0x00 25. 0x04 25. " INTLVL_RDY9_set/clr ,Transfer Group Completed Interrupt Level Set 9" "INT0,INT1" setclrfld.long 0x00 24. 0x00 24. 0x04 24. " INTLVL_RDY8_set/clr ,Transfer Group Completed Interrupt Level Set 8" "INT0,INT1" textline " " endif setclrfld.long 0x00 23. 0x00 23. 0x04 23. " INTLVL_RDY7_set/clr ,Transfer Group Completed Interrupt Level Set 7" "INT0,INT1" setclrfld.long 0x00 22. 0x00 22. 0x04 22. " INTLVL_RDY6_set/clr ,Transfer Group Completed Interrupt Level Set 6" "INT0,INT1" textline " " setclrfld.long 0x00 21. 0x00 21. 0x04 21. " INTLVL_RDY5_set/clr ,Transfer Group Completed Interrupt Level Set 5" "INT0,INT1" setclrfld.long 0x00 20. 0x00 20. 0x04 20. " INTLVL_RDY4_set/clr ,Transfer Group Completed Interrupt Level Set 4" "INT0,INT1" textline " " setclrfld.long 0x00 19. 0x00 19. 0x04 19. " INTLVL_RDY3_set/clr ,Transfer Group Completed Interrupt Level Set 3" "INT0,INT1" setclrfld.long 0x00 18. 0x00 18. 0x04 18. " INTLVL_RDY2_set/clr ,Transfer Group Completed Interrupt Level Set 2" "INT0,INT1" textline " " setclrfld.long 0x00 17. 0x00 17. 0x04 17. " INTLVL_RDY1_set/clr ,Transfer Group Completed Interrupt Level Set 1" "INT0,INT1" setclrfld.long 0x00 16. 0x00 16. 0x04 16. " INTLVL_RDY0_set/clr ,Transfer Group Completed Interrupt Level Set 0" "INT0,INT1" textline " " sif cpu()!=("TMS570PSFC61")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE") setclrfld.long 0x00 15. 0x00 15. 0x04 15. " INTLVL_SUS15_set/clr ,Transfer Group Suspended Interrupt Level Set 15" "INT0,INT1" setclrfld.long 0x00 14. 0x00 14. 0x04 14. " INTLVL_SUS14_set/clr ,Transfer Group Suspended Interrupt Level Set 14" "INT0,INT1" textline " " setclrfld.long 0x00 13. 0x00 13. 0x04 13. " INTLVL_SUS13_set/clr ,Transfer Group Suspended Interrupt Level Set 13" "INT0,INT1" setclrfld.long 0x00 12. 0x00 12. 0x04 12. " INTLVL_SUS12_set/clr ,Transfer Group Suspended Interrupt Level Set 12" "INT0,INT1" textline " " setclrfld.long 0x00 11. 0x00 11. 0x04 11. " INTLVL_SUS11_set/clr ,Transfer Group Suspended Interrupt Level Set 11" "INT0,INT1" setclrfld.long 0x00 10. 0x00 10. 0x04 10. " INTLVL_SUS10_set/clr ,Transfer Group Suspended Interrupt Level Set 10" "INT0,INT1" textline " " setclrfld.long 0x00 9. 0x00 9. 0x04 9. " INTLVL_SUS9_set/clr ,Transfer Group Suspended Interrupt Level Set 9" "INT0,INT1" setclrfld.long 0x00 8. 0x00 8. 0x04 8. " INTLVL_SUS8_set/clr ,Transfer Group Suspended Interrupt Level Set 8" "INT0,INT1" textline " " endif setclrfld.long 0x00 7. 0x00 7. 0x04 7. " INTLVL_SUS7_set/clr ,Transfer Group Suspended Interrupt Level Set 7" "INT0,INT1" setclrfld.long 0x00 6. 0x00 6. 0x04 6. " INTLVL_SUS6_set/clr ,Transfer Group Suspended Interrupt Level Set 6" "INT0,INT1" textline " " setclrfld.long 0x00 5. 0x00 5. 0x04 5. " INTLVL_SUS5_set/clr ,Transfer Group Suspended Interrupt Level Set 5" "INT0,INT1" setclrfld.long 0x00 4. 0x00 4. 0x04 4. " INTLVL_SUS4_set/clr ,Transfer Group Suspended Interrupt Level Set 4" "INT0,INT1" textline " " setclrfld.long 0x00 3. 0x00 3. 0x04 3. " INTLVL_SUS3_set/clr ,Transfer Group Suspended Interrupt Level Set 3" "INT0,INT1" setclrfld.long 0x00 2. 0x00 2. 0x04 2. " INTLVL_SUS2_set/clr ,Transfer Group Suspended Interrupt Level Set 2" "INT0,INT1" textline " " setclrfld.long 0x00 1. 0x00 1. 0x04 1. " INTLVL_SUS1_set/clr ,Transfer Group Suspended Interrupt Level Set 1" "INT0,INT1" setclrfld.long 0x00 0. 0x00 0. 0x04 0. " INTLVL_SUS0_set/clr ,Transfer Group Suspended Interrupt Level Set 0" "INT0,INT1" width 11. group.long 0x84++0x3 line.long 0x00 "TGINTFLAG,Transfer Group Interrupt Flag Register" sif cpu()!=("TMS570PSFC61")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE") eventfld.long 0x00 31. " INTFLGRDY15 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 30. " INTFLGRDY14 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 29. " INTFLGRDY13 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 28. " INTFLGRDY12 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 27. " INTFLGRDY11 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 26. " INTFLGRDY10 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 25. " INTFLGRDY9 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 24. " INTFLGRDY8 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt" textline " " endif eventfld.long 0x00 23. " INTFLGRDY7 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 22. " INTFLGRDY6 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 21. " INTFLGRDY5 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 20. " INTFLGRDY4 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 19. " INTFLGRDY3 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 18. " INTFLGRDY2 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 17. " INTFLGRDY1 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 16. " INTFLGRDY0 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt" textline " " sif cpu()!=("TMS570PSFC61")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE") eventfld.long 0x00 15. " INTFLGSUS15 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 14. " INTFLGSUS14 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 13. " INTFLGSUS13 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 12. " INTFLGSUS12 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 11. " INTFLGSUS11 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 10. " INTFLGSUS10 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 9. " INTFLGSUS9 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 8. " INTFLGSUS8 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt" textline " " endif eventfld.long 0x00 7. " INTFLGSUS7 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 6. " INTFLGSUS6 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 5. " INTFLGSUS5 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 4. " INTFLGSUS4 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " INTFLGSUS3 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 2. " INTFLGSUS2 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 1. " INTFLGSUS1 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 0. " INTFLGSUS0 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt" width 11. group.long 0x90++0x3 line.long 0x00 "TICKCNT,Tick Count Register" bitfld.long 0x00 31. " TICKENA ,Tick Counter Enable" "Disabled,Enabled" bitfld.long 0x00 30. " RELOAD ,Re-load Tick Counter" "No effect,Reload" textline " " bitfld.long 0x00 28.--29. " CLKCTRL ,Tick Counter Clock Source Control" "Format 0,Format 1,Format 2,Format 3" hexmask.long.word 0x00 0.--15. 1. " TICKVALUE ,Initial Value for Tick Counter" group.long 0x94++0x3 line.long 0x00 "LTGPEND,Last Transfer Group End Pointer" sif cpu()==("TMS570PSFC61")||cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10206-PGE") bitfld.long 0x00 24.--28. " TG_IN_SERVICE ,Transfer Group Currently Being Serviced by the Sequencer" "Not serviced,Group0,Group1,Group2,Group3,Group4,Group5,Group6,Group7,?..." else bitfld.long 0x00 24.--28. " TG_IN_SERVICE ,Transfer Group Currently Being Serviced by the Sequencer" "Not serviced,Group0,Group1,Group2,Group3,Group4,Group5,Group6,Group7,Group8,Group9,Group10,Group11,Group12,Group13,Group14,Group15,?..." endif hexmask.long.byte 0x00 8.--14. 1. " LPEND ,Last Transfer Group End Pointer" else hgroup.long 0x74++0x3 hide.long 0x00 "TGITENST,MibSPI Transfer Group Interrupt Enable Register" hgroup.long 0x7C++0x3 hide.long 0x00 "TGITLVST,MibSPI Transfer Group Interrupt Level Register" hgroup.long 0x84++0x3 hide.long 0x00 "TGINTFLAG,Transfer Group Interrupt Flag Register" hgroup.long 0x90++0x03 hide.long 0x00 "TICKCNT,Tick Count Register" hgroup.long 0x94++0x3 hide.long 0x00 "LTGPEND,Last Transfer Group End Pointer" endif width 9. tree "MibSPI Transfer Group Control Registers" if (((d.l((ad:0xFFF7F800+0x70)))&0x01)==0x01) sif (cpu()!="TMS570PSFC61")&&(cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")) group.long 0x98++0x3 line.long 0x00 "TG0CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA0 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT0 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST0 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD0 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT0 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC0 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART0 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT0 ,Transfer Group Pointer to Current Buffer" group.long 0x9C++0x3 line.long 0x00 "TG1CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA1 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT1 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST1 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD1 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT1 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC1 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART1 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT1 ,Transfer Group Pointer to Current Buffer" group.long 0xA0++0x3 line.long 0x00 "TG2CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA2 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT2 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST2 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD2 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT2 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC2 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART2 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT2 ,Transfer Group Pointer to Current Buffer" group.long 0xA4++0x3 line.long 0x00 "TG3CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA3 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT3 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST3 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD3 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT3 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC3 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART3 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT3 ,Transfer Group Pointer to Current Buffer" group.long 0xA8++0x3 line.long 0x00 "TG4CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA4 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT4 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST4 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD4 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT4 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC4 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART4 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT4 ,Transfer Group Pointer to Current Buffer" group.long 0xAC++0x3 line.long 0x00 "TG5CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA5 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT5 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST5 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD5 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT5 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC5 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART5 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT5 ,Transfer Group Pointer to Current Buffer" group.long 0xB0++0x3 line.long 0x00 "TG6CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA6 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT6 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST6 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD6 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT6 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC6 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART6 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT6 ,Transfer Group Pointer to Current Buffer" group.long 0xB4++0x3 line.long 0x00 "TG7CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA7 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT7 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST7 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD7 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT7 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC7 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART7 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT7 ,Transfer Group Pointer to Current Buffer" else group.long 0x98++0x3 line.long 0x00 "TG0CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA0 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT0 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST0 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD0 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT0 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC0 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART0 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT0 ,Transfer Group Pointer to Current Buffer" group.long 0x9C++0x3 line.long 0x00 "TG1CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA1 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT1 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST1 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD1 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT1 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC1 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART1 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT1 ,Transfer Group Pointer to Current Buffer" group.long 0xA0++0x3 line.long 0x00 "TG2CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA2 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT2 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST2 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD2 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT2 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC2 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART2 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT2 ,Transfer Group Pointer to Current Buffer" group.long 0xA4++0x3 line.long 0x00 "TG3CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA3 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT3 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST3 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD3 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT3 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC3 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART3 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT3 ,Transfer Group Pointer to Current Buffer" group.long 0xA8++0x3 line.long 0x00 "TG4CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA4 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT4 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST4 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD4 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT4 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC4 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART4 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT4 ,Transfer Group Pointer to Current Buffer" group.long 0xAC++0x3 line.long 0x00 "TG5CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA5 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT5 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST5 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD5 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT5 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC5 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART5 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT5 ,Transfer Group Pointer to Current Buffer" group.long 0xB0++0x3 line.long 0x00 "TG6CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA6 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT6 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST6 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD6 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT6 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC6 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART6 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT6 ,Transfer Group Pointer to Current Buffer" group.long 0xB4++0x3 line.long 0x00 "TG7CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA7 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT7 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST7 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD7 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT7 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC7 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART7 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT7 ,Transfer Group Pointer to Current Buffer" group.long 0xB8++0x3 line.long 0x00 "TG8CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA8 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT8 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST8 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD8 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT8 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC8 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART8 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT8 ,Transfer Group Pointer to Current Buffer" group.long 0xBC++0x3 line.long 0x00 "TG9CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA9 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT9 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST9 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD9 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT9 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC9 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART9 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT9 ,Transfer Group Pointer to Current Buffer" group.long 0xC0++0x3 line.long 0x00 "TG10CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA10 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT10 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST10 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD10 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT10 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC10 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART10 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT10 ,Transfer Group Pointer to Current Buffer" group.long 0xC4++0x3 line.long 0x00 "TG11CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA11 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT11 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST11 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD11 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT11 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC11 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART11 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT11 ,Transfer Group Pointer to Current Buffer" group.long 0xC8++0x3 line.long 0x00 "TG12CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA12 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT12 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST12 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD12 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT12 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC12 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART12 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT12 ,Transfer Group Pointer to Current Buffer" group.long 0xCC++0x3 line.long 0x00 "TG13CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA13 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT13 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST13 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD13 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT13 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC13 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART13 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT13 ,Transfer Group Pointer to Current Buffer" group.long 0xD0++0x3 line.long 0x00 "TG14CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA14 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT14 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST14 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD14 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT14 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC14 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART14 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT14 ,Transfer Group Pointer to Current Buffer" group.long 0xD4++0x3 line.long 0x00 "TG15CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA15 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT15 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST15 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD15 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT15 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC15 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART15 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT15 ,Transfer Group Pointer to Current Buffer" endif else sif cpu()==("TMS570PSFC61")||cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10206-PGE") hgroup.long 0x98++0x3 hide.long 0x00 "TG0CTRL,MibSPI Transfer Group Control Register" hgroup.long 0x9C++0x3 hide.long 0x00 "TG1CTRL,MibSPI Transfer Group Control Register" hgroup.long 0xA0++0x3 hide.long 0x00 "TG2CTRL,MibSPI Transfer Group Control Register" hgroup.long 0xA4++0x3 hide.long 0x00 "TG3CTRL,MibSPI Transfer Group Control Register" hgroup.long 0xA8++0x3 hide.long 0x00 "TG4CTRL,MibSPI Transfer Group Control Register" hgroup.long 0xAC++0x3 hide.long 0x00 "TG5CTRL,MibSPI Transfer Group Control Register" hgroup.long 0xB0++0x3 hide.long 0x00 "TG6CTRL,MibSPI Transfer Group Control Register" hgroup.long 0xB4++0x3 hide.long 0x00 "TG7CTRL,MibSPI Transfer Group Control Register" else hgroup.long 0x98++0x3 hide.long 0x00 "TG0CTRL,MibSPI Transfer Group Control Register" hgroup.long 0x9C++0x3 hide.long 0x00 "TG1CTRL,MibSPI Transfer Group Control Register" hgroup.long 0xA0++0x3 hide.long 0x00 "TG2CTRL,MibSPI Transfer Group Control Register" hgroup.long 0xA4++0x3 hide.long 0x00 "TG3CTRL,MibSPI Transfer Group Control Register" hgroup.long 0xA8++0x3 hide.long 0x00 "TG4CTRL,MibSPI Transfer Group Control Register" hgroup.long 0xAC++0x3 hide.long 0x00 "TG5CTRL,MibSPI Transfer Group Control Register" hgroup.long 0xB0++0x3 hide.long 0x00 "TG6CTRL,MibSPI Transfer Group Control Register" hgroup.long 0xB4++0x3 hide.long 0x00 "TG7CTRL,MibSPI Transfer Group Control Register" hgroup.long 0xB8++0x3 hide.long 0x00 "TG8CTRL,MibSPI Transfer Group Control Register" hgroup.long 0xBC++0x3 hide.long 0x00 "TG9CTRL,MibSPI Transfer Group Control Register" hgroup.long 0xC0++0x3 hide.long 0x00 "TG10CTRL,MibSPI Transfer Group Control Register" hgroup.long 0xC4++0x3 hide.long 0x00 "TG11CTRL,MibSPI Transfer Group Control Register" hgroup.long 0xC8++0x3 hide.long 0x00 "TG12CTRL,MibSPI Transfer Group Control Register" hgroup.long 0xCC++0x3 hide.long 0x00 "TG13CTRL,MibSPI Transfer Group Control Register" hgroup.long 0xD0++0x3 hide.long 0x00 "TG14CTRL,MibSPI Transfer Group Control Register" hgroup.long 0xD4++0x3 hide.long 0x00 "TG15CTRL,MibSPI Transfer Group Control Register" endif endif tree.end width 17. if ((((d.l((ad:0xFFF7F800+0x4)))&0x1)==0x1)&&((d.l((ad:0xFFF7F800+0x70)))&0x1)==0x1) group.long 0xD8++0x3 line.long 0x00 "DMA0CTRL,MibSPI DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT0 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 0" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID0 ,Buffer Utilized for DMA Transfer 0" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP0 ,Receive Data DMA Request Map 0" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP0 ,Transmit Data DMA Channel 0" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA0 ,Receive Data DMA Channel Enable 0" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA0 ,Transmit Data DMA Channel Enable 0" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK0 ,Non-interleaved DMA Block Transfer 0" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT0 ,Initial Count of DMA Transfers 0" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT170 ,The 17th Bit of COUNT Field of DMA0COUNT Register" "Low,High" bitfld.long 0x00 0.--5. " COUNT0 ,Actual Number of Remaining DMA Transfer 0" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l((ad:0xFFF7F800+0x4)))&0x1)==0x0)&&((d.l((ad:0xFFF7F800+0x70)))&0x1)==0x1) group.long 0xD8++0x3 line.long 0x00 "DMA0CTRL,MibSPI DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT0 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 0" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID0 ,Buffer Utilized for DMA Transfer 0" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP0 ,Receive Data DMA Request Map 0" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP0 ,Transmit Data DMA Channel 0" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA0 ,Receive Data DMA Channel Enable 0" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA0 ,Transmit Data DMA Channel Enable 0" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT0 ,Initial Count of DMA Transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT170 ,The 17th Bit of COUNT Field of DMA0COUNT Register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT0 ,Actual Number of Remaining DMA Transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xD8++0x3 hide.long 0x00 "DMA0CTRL,MibSPI DMA Channel Control Register" endif if ((((d.l((ad:0xFFF7F800+0x4)))&0x1)==0x1)&&((d.l((ad:0xFFF7F800+0x70)))&0x1)==0x1) group.long 0xDC++0x3 line.long 0x00 "DMA1CTRL,MibSPI DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT1 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 1" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID1 ,Buffer Utilized for DMA Transfer 1" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP1 ,Receive Data DMA Request Map 1" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP1 ,Transmit Data DMA Channel 1" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA1 ,Receive Data DMA Channel Enable 1" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA1 ,Transmit Data DMA Channel Enable 1" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK1 ,Non-interleaved DMA Block Transfer 1" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT1 ,Initial Count of DMA Transfers 1" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT171 ,The 17th Bit of COUNT Field of DMA1COUNT Register" "Low,High" bitfld.long 0x00 0.--5. " COUNT1 ,Actual Number of Remaining DMA Transfer 1" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l((ad:0xFFF7F800+0x4)))&0x1)==0x0)&&((d.l((ad:0xFFF7F800+0x70)))&0x1)==0x1) group.long 0xDC++0x3 line.long 0x00 "DMA1CTRL,MibSPI DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT1 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 1" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID1 ,Buffer Utilized for DMA Transfer 1" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP1 ,Receive Data DMA Request Map 1" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP1 ,Transmit Data DMA Channel 1" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA1 ,Receive Data DMA Channel Enable 1" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA1 ,Transmit Data DMA Channel Enable 1" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT1 ,Initial Count of DMA Transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT171 ,The 17th Bit of COUNT Field of DMA1COUNT Register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT1 ,Actual Number of Remaining DMA Transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xDC++0x3 hide.long 0x00 "DMA1CTRL,MibSPI DMA Channel Control Register" endif if ((((d.l((ad:0xFFF7F800+0x4)))&0x1)==0x1)&&((d.l((ad:0xFFF7F800+0x70)))&0x1)==0x1) group.long 0xE0++0x3 line.long 0x00 "DMA2CTRL,MibSPI DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT2 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 2" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID2 ,Buffer Utilized for DMA Transfer 2" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP2 ,Receive Data DMA Request Map 2" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP2 ,Transmit Data DMA Channel 2" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA2 ,Receive Data DMA Channel Enable 2" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA2 ,Transmit Data DMA Channel Enable 2" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK2 ,Non-interleaved DMA Block Transfer 2" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT2 ,Initial Count of DMA Transfers 2" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT172 ,The 17th Bit of COUNT Field of DMA2COUNT Register" "Low,High" bitfld.long 0x00 0.--5. " COUNT2 ,Actual Number of Remaining DMA Transfer 2" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l((ad:0xFFF7F800+0x4)))&0x1)==0x0)&&((d.l((ad:0xFFF7F800+0x70)))&0x1)==0x1) group.long 0xE0++0x3 line.long 0x00 "DMA2CTRL,MibSPI DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT2 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 2" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID2 ,Buffer Utilized for DMA Transfer 2" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP2 ,Receive Data DMA Request Map 2" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP2 ,Transmit Data DMA Channel 2" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA2 ,Receive Data DMA Channel Enable 2" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA2 ,Transmit Data DMA Channel Enable 2" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT2 ,Initial Count of DMA Transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT172 ,The 17th Bit of COUNT Field of DMA2COUNT Register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT2 ,Actual Number of Remaining DMA Transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xE0++0x3 hide.long 0x00 "DMA2CTRL,MibSPI DMA Channel Control Register" endif if ((((d.l((ad:0xFFF7F800+0x4)))&0x1)==0x1)&&((d.l((ad:0xFFF7F800+0x70)))&0x1)==0x1) group.long 0xE4++0x3 line.long 0x00 "DMA3CTRL,MibSPI DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT3 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 3" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID3 ,Buffer Utilized for DMA Transfer 3" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP3 ,Receive Data DMA Request Map 3" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP3 ,Transmit Data DMA Channel 3" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA3 ,Receive Data DMA Channel Enable 3" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA3 ,Transmit Data DMA Channel Enable 3" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK3 ,Non-interleaved DMA Block Transfer 3" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT3 ,Initial Count of DMA Transfers 3" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT173 ,The 17th Bit of COUNT Field of DMA3COUNT Register" "Low,High" bitfld.long 0x00 0.--5. " COUNT3 ,Actual Number of Remaining DMA Transfer 3" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l((ad:0xFFF7F800+0x4)))&0x1)==0x0)&&((d.l((ad:0xFFF7F800+0x70)))&0x1)==0x1) group.long 0xE4++0x3 line.long 0x00 "DMA3CTRL,MibSPI DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT3 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 3" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID3 ,Buffer Utilized for DMA Transfer 3" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP3 ,Receive Data DMA Request Map 3" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP3 ,Transmit Data DMA Channel 3" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA3 ,Receive Data DMA Channel Enable 3" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA3 ,Transmit Data DMA Channel Enable 3" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT3 ,Initial Count of DMA Transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT173 ,The 17th Bit of COUNT Field of DMA3COUNT Register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT3 ,Actual Number of Remaining DMA Transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xE4++0x3 hide.long 0x00 "DMA3CTRL,MibSPI DMA Channel Control Register" endif if ((((d.l((ad:0xFFF7F800+0x4)))&0x1)==0x1)&&((d.l((ad:0xFFF7F800+0x70)))&0x1)==0x1) group.long 0xE8++0x3 line.long 0x00 "DMA4CTRL,MibSPI DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT4 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 4" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID4 ,Buffer Utilized for DMA Transfer 4" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP4 ,Receive Data DMA Request Map 4" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP4 ,Transmit Data DMA Channel 4" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA4 ,Receive Data DMA Channel Enable 4" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA4 ,Transmit Data DMA Channel Enable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK4 ,Non-interleaved DMA Block Transfer 4" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT4 ,Initial Count of DMA Transfers 4" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT174 ,The 17th Bit of COUNT Field of DMA4COUNT Register" "Low,High" bitfld.long 0x00 0.--5. " COUNT4 ,Actual Number of Remaining DMA Transfer 4" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l((ad:0xFFF7F800+0x4)))&0x1)==0x0)&&((d.l((ad:0xFFF7F800+0x70)))&0x1)==0x1) group.long 0xE8++0x3 line.long 0x00 "DMA4CTRL,MibSPI DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT4 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 4" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID4 ,Buffer Utilized for DMA Transfer 4" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP4 ,Receive Data DMA Request Map 4" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP4 ,Transmit Data DMA Channel 4" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA4 ,Receive Data DMA Channel Enable 4" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA4 ,Transmit Data DMA Channel Enable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT4 ,Initial Count of DMA Transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT174 ,The 17th Bit of COUNT Field of DMA4COUNT Register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT4 ,Actual Number of Remaining DMA Transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xE8++0x3 hide.long 0x00 "DMA4CTRL,MibSPI DMA Channel Control Register" endif if ((((d.l((ad:0xFFF7F800+0x4)))&0x1)==0x1)&&((d.l((ad:0xFFF7F800+0x70)))&0x1)==0x1) group.long 0xEC++0x3 line.long 0x00 "DMA5CTRL,MibSPI DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT5 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 5" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID5 ,Buffer Utilized for DMA Transfer 5" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP5 ,Receive Data DMA Request Map 5" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP5 ,Transmit Data DMA Channel 5" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA5 ,Receive Data DMA Channel Enable 5" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA5 ,Transmit Data DMA Channel Enable 5" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK5 ,Non-interleaved DMA Block Transfer 5" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT5 ,Initial Count of DMA Transfers 5" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT175 ,The 17th Bit of COUNT Field of DMA5COUNT Register" "Low,High" bitfld.long 0x00 0.--5. " COUNT5 ,Actual Number of Remaining DMA Transfer 5" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l((ad:0xFFF7F800+0x4)))&0x1)==0x0)&&((d.l((ad:0xFFF7F800+0x70)))&0x1)==0x1) group.long 0xEC++0x3 line.long 0x00 "DMA5CTRL,MibSPI DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT5 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 5" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID5 ,Buffer Utilized for DMA Transfer 5" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP5 ,Receive Data DMA Request Map 5" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP5 ,Transmit Data DMA Channel 5" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA5 ,Receive Data DMA Channel Enable 5" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA5 ,Transmit Data DMA Channel Enable 5" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT5 ,Initial Count of DMA Transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT175 ,The 17th Bit of COUNT Field of DMA5COUNT Register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT5 ,Actual Number of Remaining DMA Transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xEC++0x3 hide.long 0x00 "DMA5CTRL,MibSPI DMA Channel Control Register" endif if ((((d.l((ad:0xFFF7F800+0x4)))&0x1)==0x1)&&((d.l((ad:0xFFF7F800+0x70)))&0x1)==0x1) group.long 0xF0++0x3 line.long 0x00 "DMA6CTRL,MibSPI DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT6 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 6" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID6 ,Buffer Utilized for DMA Transfer 6" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP6 ,Receive Data DMA Request Map 6" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP6 ,Transmit Data DMA Channel 6" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA6 ,Receive Data DMA Channel Enable 6" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA6 ,Transmit Data DMA Channel Enable 6" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK6 ,Non-interleaved DMA Block Transfer 6" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT6 ,Initial Count of DMA Transfers 6" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT176 ,The 17th Bit of COUNT Field of DMA6COUNT Register" "Low,High" bitfld.long 0x00 0.--5. " COUNT6 ,Actual Number of Remaining DMA Transfer 6" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l((ad:0xFFF7F800+0x4)))&0x1)==0x0)&&((d.l((ad:0xFFF7F800+0x70)))&0x1)==0x1) group.long 0xF0++0x3 line.long 0x00 "DMA6CTRL,MibSPI DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT6 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 6" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID6 ,Buffer Utilized for DMA Transfer 6" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP6 ,Receive Data DMA Request Map 6" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP6 ,Transmit Data DMA Channel 6" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA6 ,Receive Data DMA Channel Enable 6" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA6 ,Transmit Data DMA Channel Enable 6" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT6 ,Initial Count of DMA Transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT176 ,The 17th Bit of COUNT Field of DMA6COUNT Register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT6 ,Actual Number of Remaining DMA Transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xF0++0x3 hide.long 0x00 "DMA6CTRL,MibSPI DMA Channel Control Register" endif if ((((d.l((ad:0xFFF7F800+0x4)))&0x1)==0x1)&&((d.l((ad:0xFFF7F800+0x70)))&0x1)==0x1) group.long 0xF4++0x3 line.long 0x00 "DMA7CTRL,MibSPI DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT7 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 7" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID7 ,Buffer Utilized for DMA Transfer 7" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP7 ,Receive Data DMA Request Map 7" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP7 ,Transmit Data DMA Channel 7" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA7 ,Receive Data DMA Channel Enable 7" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA7 ,Transmit Data DMA Channel Enable 7" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK7 ,Non-interleaved DMA Block Transfer 7" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT7 ,Initial Count of DMA Transfers 7" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT177 ,The 17th Bit of COUNT Field of DMA7COUNT Register" "Low,High" bitfld.long 0x00 0.--5. " COUNT7 ,Actual Number of Remaining DMA Transfer 7" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l((ad:0xFFF7F800+0x4)))&0x1)==0x0)&&((d.l((ad:0xFFF7F800+0x70)))&0x1)==0x1) group.long 0xF4++0x3 line.long 0x00 "DMA7CTRL,MibSPI DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT7 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 7" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID7 ,Buffer Utilized for DMA Transfer 7" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP7 ,Receive Data DMA Request Map 7" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP7 ,Transmit Data DMA Channel 7" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA7 ,Receive Data DMA Channel Enable 7" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA7 ,Transmit Data DMA Channel Enable 7" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT7 ,Initial Count of DMA Transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT177 ,The 17th Bit of COUNT Field of DMA7COUNT Register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT7 ,Actual Number of Remaining DMA Transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xF4++0x3 hide.long 0x00 "DMA7CTRL,MibSPI DMA Channel Control Register" endif if (((d.l((ad:0xFFF7F800+0x70)))&0x01)==0x01) group.long 0xF8++0x3 line.long 0x00 "DMA0COUNT,ICOUNT Register 0" hexmask.long.word 0x00 16.--31. 1. " ICOUNT0 ,Initial Number of DMA Transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT0 ,Actual Number of Remaining DMA Transfer" else hgroup.long 0xF8++0x3 hide.long 0x00 "DMA0COUNT,ICOUNT Register 0" endif if (((d.l((ad:0xFFF7F800+0x70)))&0x01)==0x01) group.long 0xFC++0x3 line.long 0x00 "DMA1COUNT,ICOUNT Register 1" hexmask.long.word 0x00 16.--31. 1. " ICOUNT1 ,Initial Number of DMA Transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT1 ,Actual Number of Remaining DMA Transfer" else hgroup.long 0xFC++0x3 hide.long 0x00 "DMA1COUNT,ICOUNT Register 1" endif if (((d.l((ad:0xFFF7F800+0x70)))&0x01)==0x01) group.long 0x100++0x3 line.long 0x00 "DMA2COUNT,ICOUNT Register 2" hexmask.long.word 0x00 16.--31. 1. " ICOUNT2 ,Initial Number of DMA Transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT2 ,Actual Number of Remaining DMA Transfer" else hgroup.long 0x100++0x3 hide.long 0x00 "DMA2COUNT,ICOUNT Register 2" endif if (((d.l((ad:0xFFF7F800+0x70)))&0x01)==0x01) group.long 0x104++0x3 line.long 0x00 "DMA3COUNT,ICOUNT Register 3" hexmask.long.word 0x00 16.--31. 1. " ICOUNT3 ,Initial Number of DMA Transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT3 ,Actual Number of Remaining DMA Transfer" else hgroup.long 0x104++0x3 hide.long 0x00 "DMA3COUNT,ICOUNT Register 3" endif if (((d.l((ad:0xFFF7F800+0x70)))&0x01)==0x01) group.long 0x108++0x3 line.long 0x00 "DMA4COUNT,ICOUNT Register 4" hexmask.long.word 0x00 16.--31. 1. " ICOUNT4 ,Initial Number of DMA Transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT4 ,Actual Number of Remaining DMA Transfer" else hgroup.long 0x108++0x3 hide.long 0x00 "DMA4COUNT,ICOUNT Register 4" endif if (((d.l((ad:0xFFF7F800+0x70)))&0x01)==0x01) group.long 0x10C++0x3 line.long 0x00 "DMA5COUNT,ICOUNT Register 5" hexmask.long.word 0x00 16.--31. 1. " ICOUNT5 ,Initial Number of DMA Transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT5 ,Actual Number of Remaining DMA Transfer" else hgroup.long 0x10C++0x3 hide.long 0x00 "DMA5COUNT,ICOUNT Register 5" endif if (((d.l((ad:0xFFF7F800+0x70)))&0x01)==0x01) group.long 0x110++0x3 line.long 0x00 "DMA6COUNT,ICOUNT Register 6" hexmask.long.word 0x00 16.--31. 1. " ICOUNT6 ,Initial Number of DMA Transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT6 ,Actual Number of Remaining DMA Transfer" else hgroup.long 0x110++0x3 hide.long 0x00 "DMA6COUNT,ICOUNT Register 6" endif if (((d.l((ad:0xFFF7F800+0x70)))&0x01)==0x01) group.long 0x114++0x3 line.long 0x00 "DMA7COUNT,ICOUNT Register 7" hexmask.long.word 0x00 16.--31. 1. " ICOUNT7 ,Initial Number of DMA Transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT7 ,Actual Number of Remaining DMA Transfer" else hgroup.long 0x114++0x3 hide.long 0x00 "DMA7COUNT,ICOUNT Register 7" endif if (((d.l((ad:0xFFF7F800+0x70)))&0x01)==0x01) group.long 0x118++0x3 line.long 0x00 "DMACNTLEN,DMA LARGE COUNT Register" bitfld.long 0x00 0. " LARGE_COUNT ,Large Count" "Modified,Not modified" group.long 0x120++0x3 line.long 0x00 "UERRCTRL,Uncorrectable Parity Error Control Register" bitfld.long 0x00 8. " PTESTEN ,Parity Memory Test Enable" "Disabled,Enabled" bitfld.long 0x00 0.--3. " EDEN ,Error Detection Enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" hgroup.long 0x124++0x3 hide.long 0x00 "UERRSTAT,Uncorrectable Parity Error Status Register" in hgroup.long 0x128++0x3 hide.long 0x00 "UERRADDR1,Uncorrectable Parity Error Address Register" in hgroup.long 0x12c++0x3 hide.long 0x00 "UERRADDR0,Uncorrectable Parity Error Address Register" in hgroup.long 0x130++0x3 hide.long 0x00 "RXOVRN_BUF_ADDR,Receive RAM Overrun Buffer Address Register" in else hgroup.long 0x118++0x3 hide.long 0x00 "DMACNTLEN,DMA LARGE COUNT Register" hgroup.long 0x120++0x3 hide.long 0x00 "UERRCTRL,Uncorrectable Parity Error Control Register" hgroup.long 0x124++0x3 hide.long 0x00 "UERRSTAT,Uncorrectable Parity Error Status Register" hgroup.long 0x128++0x3 hide.long 0x00 "UERRADDR1,Uncorrectable Parity Error Address Register" hgroup.long 0x12c++0x3 hide.long 0x00 "UERRADDR0,Uncorrectable Parity Error Address Register" hgroup.long 0x130++0x3 hide.long 0x00 "RXOVRN_BUF_ADDR,Receive RAM Overrun Buffer Address Register" endif tree.end width 13. if ((((d.l((ad:0xFFF7F800+0x0134)))&0x0f00)==0x0a00)&&(((d.l((ad:0xFFF7F800+0x0134)))&0x02)==0x02)) group.long 0x134++0x3 line.long 0x00 "IOLPBKTSTCR,SPI/MibSPI IO Loopback Test Control Register" bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O Loopback Test Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" eventfld.long 0x00 24. " SCS_FAIL_FLG ,Analog Loopback /SPISCS Pin Compare Failure" "Not failed,Failed" textline " " bitfld.long 0x00 20. " CTRL_BITERR ,Inducing of BITERR During IO Loopback Test Mode Control" "Not affected,Flipped" bitfld.long 0x00 19. " CTRL_DESYNC ,Inducing of DESYNC Error During IO Loopback Test Mode Control" "Not affected,Forced to 0" textline " " bitfld.long 0x00 18. " CTRL_PARERR ,Inducing of Parity Error During IO Loopback Test Mode Control" "Not affected,Flipped" bitfld.long 0x00 17. " CTRL_TIMEOUT ,Inducing of TIMEOUT Error During IO Loopback Test Mode Control" "Not affected,Forced to 1" textline " " bitfld.long 0x00 16. " CTRL_DLENERR ,Inducing of Data Length Error During IO Loopback Test Mode Control" "Not affected,Forced to 1" bitfld.long 0x00 3.--5. " ERR_SCS_PIN ,Error on Chip Select Pin Injection" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]" textline " " bitfld.long 0x00 2. " CTRL_SCS_PIN_ERR ,/SPISCS[7:0] Pins Error Injection Enable Control" "Disabled,Enabled" bitfld.long 0x00 1. " LPBK_TYPE ,Module IO Loopback Type" "Digital,Analog" textline " " bitfld.long 0x00 0. " RXP_ENA ,Module Analog Loopback Through Receive Pin Enable" "Transmit,Receive" elif ((((data.long((ad:0xFFF7F800+0x0134)))&0x0f00)==0x0a00)&&(((data.long((ad:0xFFF7F800+0x0134)))&0x02)==0x00)) group.long 0x134++0x3 line.long 0x00 "IOLPBKTSTCR,SPI/MibSPI IO Loopback Test Control Register" bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O Loopback Test Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" eventfld.long 0x00 24. " SCS_FAIL_FLG ,Analog Loopback /SPISCS Pin Compare Failure" "Not failed,Failed" textline " " bitfld.long 0x00 20. " CTRL_BITERR ,Inducing of BITERR During IO Loopback Test Mode Control" "Not affected,Flipped" bitfld.long 0x00 19. " CTRL_DESYNC ,Inducing of DESYNC Error During IO Loopback Test Mode Control" "Not affected,Forced to 0" textline " " bitfld.long 0x00 18. " CTRL_PARERR ,Inducing of Parity Error During IO Loopback Test Mode Control" "Not affected,Flipped" bitfld.long 0x00 17. " CTRL_TIMEOUT ,Inducing of TIMEOUT Error During IO Loopback Test Mode Control" "Not affected,Forced to 1" textline " " bitfld.long 0x00 16. " CTRL_DLENERR ,Inducing of Data Length Error During IO Loopback Test Mode Control" "Not affected,Forced to 1" bitfld.long 0x00 3.--5. " ERR_SCS_PIN ,Error on Chip Select Pin Injection" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]" textline " " bitfld.long 0x00 2. " CTRL_SCS_PIN_ERR ,/SPISCS[7:0] Pins Error Injection Enable Control" "Disabled,Enabled" bitfld.long 0x00 1. " LPBK_TYPE ,Module IO Loopback Type" "Digital,Analog" else group.long 0x134++0x3 line.long 0x00 "IOLPBKTSTCR,SPI/MibSPI IO Loopback Test Control Register" bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O Loopback Test Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" endif width 0xb tree.end tree "MIPSPIP5" base ad:0xFFF7FC00 width 6. group.long 0x00++0x3 line.long 0x0 "GCR0,Global Control Register 0" bitfld.long 0x00 0. " nRESET ,This is the Reset Bit for the Module" "Reset,No reset" if (((d.l((ad:0xFFF7FC00+0x04)))&0x03)==0x03) group.long 0x04++0x3 line.long 0x0 "GCR1,Global Control Register 1" bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI Pin Direction Determination" "Input/output,Output/input" bitfld.long 0x00 24. " SPIEN ,SPI Enable" "Not active,Active" bitfld.long 0x00 16. " LOOP_BACK ,Internal Loop-back Test Mode" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " POWERDOWN ,SPI State Machines Power Down State Enable" "Active,Power down" bitfld.long 0x00 1. " CLKMOD ,Clock Mode" "External,Internal" elif (((d.l((ad:0xFFF7FC00+0x04)))&0x03)==0x02) group.long 0x04++0x3 line.long 0x0 "GCR1,Global Control Register 1" bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI Pin Direction Determination" "Input/output,Output/input" bitfld.long 0x00 24. " SPIEN ,SPI Enable" "Not active,Active" bitfld.long 0x00 8. " POWERDOWN ,SPI State Machines Power Down State Enable" "Active,Power down" textline " " bitfld.long 0x00 1. " CLKMOD ,Clock Mode" "External,Internal" elif (((d.l((ad:0xFFF7FC00+0x04)))&0x03)==0x01) group.long 0x04++0x3 line.long 0x0 "GCR1,Global Control Register 1" bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI Pin Direction Determination" "Input/output,Output/input" bitfld.long 0x00 24. " SPIEN ,SPI Enable" "Not active,Active" bitfld.long 0x00 8. " POWERDOWN ,SPI State Machines Power Down State Enable" "Active,Power down" textline " " bitfld.long 0x00 1. " CLKMOD ,Clock Mode" "External,Internal" else group.long 0x04++0x3 line.long 0x0 "GCR1,Global Control Register 1" bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI Pin Direction Determination" "Input/output,Output/input" bitfld.long 0x00 24. " SPIEN ,SPI Enable" "Not active,Active" bitfld.long 0x00 8. " POWERDOWN ,SPI State Machines Power Down State Enable" "Active,Power down" textline " " bitfld.long 0x00 1. " CLKMOD ,Clock Mode" "External,Internal" endif width 6. if (((d.l((ad:0xFFF7FC00+0x04)))&0x01)==0x01) group.long 0x08++0x3 line.long 0x0 "INT0,Interrupt Register" bitfld.long 0x00 24. " ENABLE_HIGHZ ,/SPIENA Pin High-z Enable" "Disabled,Enabled" bitfld.long 0x00 16. " DMA_REQ_EN ,DMA Request Enable" "Not used,Generated" textline " " bitfld.long 0x00 9. " TXINTENA ,Transmit Interrupt Enable" "Not generated,Generated" bitfld.long 0x00 8. " RXINTENA ,Receive Interrupt Enable" "Not generated,Generated" textline " " bitfld.long 0x00 6. " RXOVRNINTENA ,Overrun Interrupt Enable" "Not generated,Generated" bitfld.long 0x00 4. " BITERRENA ,Enables Interrupt on Bit Error" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " DESYNCENA ,Enables Interrupt on De-synchronized Slave" "Disabled,Enabled" bitfld.long 0x00 2. " PARERRENA ,Enables Interrupt on Parity Error" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " TIMEOUTENA ,Enables Interrupt on ENA Signal Time-out" "Disabled,Enabled" bitfld.long 0x00 0. " DLEN_ERR_ENA ,Data Length Error Interrupt Enable" "Disabled,Enabled" else group.long 0x08++0x3 line.long 0x0 "INT0,Interrupt Register" bitfld.long 0x00 24. " ENABLE_HIGHZ ,/SPIENA Pin High-z Enable" "Disabled,Enabled" bitfld.long 0x00 16. " DMA_REQ_EN ,DMA Request Enable" "Not used,Generated" textline " " bitfld.long 0x00 9. " TXINTENA ,Transmit Interrupt Enable" "Not generated,Generated" bitfld.long 0x00 8. " RXINTENA ,Receive Interrupt Enable" "Not generated,Generated" textline " " bitfld.long 0x00 6. " RXOVRNINTENA ,Overrun Interrupt Enable" "Not generated,Generated" bitfld.long 0x00 4. " BITERRENA ,Enables Interrupt on Bit Error" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " PARERRENA ,Enables Interrupt on Parity Error" "Disabled,Enabled" bitfld.long 0x00 1. " TIMEOUTENA ,Enables Interrupt on ENA Signal Time-out" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " DLEN_ERR_ENA ,Data Length Error Interrupt Enable" "Disabled,Enabled" endif width 6. if (((d.l((ad:0xFFF7FC00+0x04)))&0x01)==0x01) group.long 0x0C++0x3 line.long 0x0 "LVL,Interrupt Level Register" bitfld.long 0x00 9. " TXINTLVL ,Transmit Interrupt Level" "INT0,INT1" bitfld.long 0x00 8. " RXINTLVL ,Receive Interrupt level" "INT0,INT1" sif (cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")) bitfld.long 0x00 6. " OVRNINTLVL ,Receive Overrun Interrupt level" "INT0,INT1" else bitfld.long 0x00 6. " RXOVRNINTLVL ,Receive Overrun Interrupt level" "INT0,INT1" endif textline " " bitfld.long 0x00 4. " BITERRLVL ,Bit Error Interrupt level" "INT0,INT1" bitfld.long 0x00 3. " DESYNCLVL ,De-synchronized Slave Interrupt Level" "INT0,INT1" bitfld.long 0x00 2. " PARERRLVL ,Parity Error Interrupt Level" "INT0,INT1" textline " " bitfld.long 0x00 1. " TIMEOUTLVL ,/SPIENA Pin Time-out Interrupt Level" "INT0,INT1" bitfld.long 0x00 0. " DLEN_ERR_LVL ,Data Length Error Interrupt Enable Level" "INT0,INT1" else group.long 0x0C++0x3 line.long 0x0 "LVL,Interrupt Level Register" bitfld.long 0x00 9. " TXINTLVL ,Transmit Interrupt Level" "INT0,INT1" bitfld.long 0x00 8. " RXINTLVL ,Receive Interrupt level" "INT0,INT1" sif (cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")) bitfld.long 0x00 6. " OVRNINTLVL ,Receive Overrun Interrupt level" "INT0,INT1" else bitfld.long 0x00 6. " RXOVRNINTLVL ,Receive Overrun Interrupt level" "INT0,INT1" endif textline " " bitfld.long 0x00 4. " BITERRLVL ,Bit Error Interrupt level" "INT0,INT1" bitfld.long 0x00 2. " PARERRLVL ,Parity Error Interrupt Level" "INT0,INT1" bitfld.long 0x00 1. " TIMEOUTLVL ,/SPIENA Pin Time-out Interrupt Level" "INT0,INT1" textline " " bitfld.long 0x00 0. " DLEN_ERR_LVL ,Data Length Error Interrupt Enable Level" "INT0,INT1" endif width 6. if (((d.l((ad:0xFFF7FC00+0x04)))&0x01)==0x01) group.long 0x10++0x3 line.long 0x0 "FLG,Flag Register" bitfld.long 0x00 24. " BUF_INIT_ACTIVE ,Multibuffer Initialization Active" "Finished,Not finished" bitfld.long 0x00 9. " TXINTFLG ,Transmitter Empty Interrupt Flag" "Full,Empty" textline " " eventfld.long 0x00 8. " RXINTFLG ,Receiver Full Interrupt Flag" "Empty,Full" eventfld.long 0x00 6. " RXOVRNINTFLG ,Receiver Overrun Flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 4. " BITERRFLG ,Internal Transmit Data and Transmitted Data Mismatch" "Not occurred,Occurred" eventfld.long 0x00 3. " DESYNCFLG ,Slave Device De-Synchronization" "Not detected,Detected" textline " " eventfld.long 0x00 2. " PARITYERRFLG ,Parity Error Flag" "Not detected,Detected" eventfld.long 0x00 1. " TIMEOUTFLG ,Time-out Due to Non-activation of ENA Signal" "Not occurred,Occurred" textline " " eventfld.long 0x00 0. " DLEN_ERR_FLG ,Data Length Error Flag" "Not occurred,Occurred" else group.long 0x10++0x3 line.long 0x0 "FLG,Flag Register" bitfld.long 0x00 24. " BUF_INIT_ACTIVE ,Multibuffer Initialization Active" "Not completed,Completed" bitfld.long 0x00 9. " TXINTFLG ,Transmitter Empty Interrupt Flag" "No empty,Empty" textline " " eventfld.long 0x00 8. " RXINTFLG ,Receiver Full Interrupt Flag" "No full,Full" eventfld.long 0x00 6. " RXOVRNINTFLG ,Receiver Overrun Flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 4. " BITERRFLG ,Internal Transmit Data and Transmitted Data Mismatch" "Not occurred,Occurred" eventfld.long 0x00 2. " PARITYERRFLG ,Parity Error Flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 1. " TIMEOUTFLG ,Time-out Due to Non-activation of ENA Signal" "Not occurred,Occurred" eventfld.long 0x00 0. " DLEN_ERR_FLG ,Data Length Error Flag" "Not occurred,Occurred" endif width 5. tree "SPI Pin Control Registers" tree "SPI Pin Control Registers 0-5" group.long 0x14++0x3 line.long 0x0 "PC0,Pin Control Register 0" bitfld.long 0x00 31. " SOMIFUN7 ,Slave Out Master in Function 7" "GPIO,SPI/MibSPI" bitfld.long 0x00 30. " SOMIFUN6 ,Slave Out Master in Function 6" "GPIO,SPI/MibSPI" bitfld.long 0x00 29. " SOMIFUN5 ,Slave Out Master in Function 5" "GPIO,SPI/MibSPI" textline " " bitfld.long 0x00 28. " SOMIFUN4 ,Slave Out Master in Function 4" "GPIO,SPI/MibSPI" bitfld.long 0x00 27. " SOMIFUN3 ,Slave Out Master in Function 3" "GPIO,SPI/MibSPI" bitfld.long 0x00 26. " SOMIFUN2 ,Slave Out Master in Function 2" "GPIO,SPI/MibSPI" textline " " bitfld.long 0x00 25. " SOMIFUN1 ,Slave Out Master in Function 1" "GPIO,SPI/MibSPI" bitfld.long 0x00 24. " SOMIFUN0 ,Slave Out Master in Function 0" "GPIO,SPI/MibSPI" bitfld.long 0x00 23. " SIMOFUN7 ,Slave In Master Out Function 7" "GPIO,SPI/MibSPI" textline " " bitfld.long 0x00 22. " SIMOFUN6 ,Slave In Master Out Function 6" "GPIO,SPI/MibSPI" bitfld.long 0x00 21. " SIMOFUN5 ,Slave In Master Out Function 5" "GPIO,SPI/MibSPI" bitfld.long 0x00 20. " SIMOFUN4 ,Slave In Master Out Function 4" "GPIO,SPI/MibSPI" textline " " bitfld.long 0x00 19. " SIMOFUN3 ,Slave In Master Out Function 3" "GPIO,SPI/MibSPI" bitfld.long 0x00 18. " SIMOFUN2 ,Slave In Master Out Function 2" "GPIO,SPI/MibSPI" bitfld.long 0x00 17. " SIMOFUN1 ,Slave In Master Out Function 1" "GPIO,SPI/MibSPI" textline " " bitfld.long 0x00 16. " SIMOFUN0 ,Slave In Master Out Function 0" "GPIO,SPI/MibSPI" bitfld.long 0x00 11. " SOMIFUN0 ,Slave Out Master In Function" "GPIO,SPI/MibSPI" bitfld.long 0x00 10. " SIMOFUN0 ,Slave In Master Out Function" "GPIO,SPI/MibSPI" textline " " bitfld.long 0x00 9. " CLKFUN ,SPI/MibSPI Clock Function" "GPIO,SPI/MibSPI" bitfld.long 0x00 8. " ENAFUN ,/SPIENA function" "GPIO,SPI/MibSPI" bitfld.long 0x00 7. " SCSFUN7 ,/SPISCS7 Function" "GPIO,SPI" textline " " bitfld.long 0x00 6. " SCSFUN6 ,/SPISCS6 Function" "GPIO,SPI" bitfld.long 0x00 5. " SCSFUN5 ,/SPISCS5 Function" "GPIO,SPI" bitfld.long 0x00 4. " SCSFUN4 ,/SPISCS4 Function" "GPIO,SPI" textline " " bitfld.long 0x00 3. " SCSFUN3 ,/SPISCS3 Function" "GPIO,SPI" bitfld.long 0x00 2. " SCSFUN2 ,/SPISCS2 Function" "GPIO,SPI" bitfld.long 0x00 1. " SCSFUN1 ,/SPISCS1 Function" "GPIO,SPI" textline " " bitfld.long 0x00 0. " SCSFUN0 ,/SPISCS0 Function" "GPIO,SPI" group.long 0x18++0x3 line.long 0x0 "PC1,Pin Control Register 1" bitfld.long 0x00 31. " SOMIDIR7 ,SPISOMI7 Direction" "Input,Output" bitfld.long 0x00 30. " SOMIDIR6 ,SPISOMI6 Direction" "Input,Output" bitfld.long 0x00 29. " SOMIDIR5 ,SPISOMI5 Direction" "Input,Output" textline " " bitfld.long 0x00 28. " SOMIDIR4 ,SPISOMI4 Direction" "Input,Output" bitfld.long 0x00 27. " SOMIDIR3 ,SPISOMI3 Direction" "Input,Output" bitfld.long 0x00 26. " SOMIDIR2 ,SPISOMI2 Direction" "Input,Output" textline " " bitfld.long 0x00 25. " SOMIDIR1 ,SPISOMI1 Direction" "Input,Output" bitfld.long 0x00 24. " SOMIDIR0 ,SPISOMI0 Direction" "Input,Output" bitfld.long 0x00 23. " SIMODIR7 ,SPISIMO7 Direction" "Input,Output" textline " " bitfld.long 0x00 22. " SIMODIR6 ,SPISIMO6 Direction" "Input,Output" bitfld.long 0x00 21. " SIMODIR5 ,SPISIMO5 Direction" "Input,Output" bitfld.long 0x00 20. " SIMODIR4 ,SPISIMO4 Direction" "Input,Output" textline " " bitfld.long 0x00 19. " SIMODIR3 ,SPISIMO3 Direction" "Input,Output" bitfld.long 0x00 18. " SIMODIR2 ,SPISIMO2 Direction" "Input,Output" bitfld.long 0x00 17. " SIMODIR1 ,SPISIMO1 Direction" "Input,Output" textline " " bitfld.long 0x00 16. " SIMODIR0 ,SPISIMO0 Direction" "Input,Output" bitfld.long 0x00 11. " SOMIDIR0 ,SPISOMI0 Direction" "Input,Output" bitfld.long 0x00 10. " SIMODIR0 ,SPISIMO0 Direction" "Input,Output" textline " " bitfld.long 0x00 9. " CLKDIR ,SPICLK Direction" "Input,Output" bitfld.long 0x00 8. " ENADIR ,/SPIENA Direction" "Input,Output" bitfld.long 0x00 7. " SCSDIR7 ,/SPISCS7 Direction" "Input,Output" textline " " bitfld.long 0x00 6. " SCSDIR6 ,/SPISCS6 Direction" "Input,Output" bitfld.long 0x00 5. " SCSDIR5 ,/SPISCS5 Direction" "Input,Output" bitfld.long 0x00 4. " SCSDIR4 ,/SPISCS4 Direction" "Input,Output" textline " " bitfld.long 0x00 3. " SCSDIR3 ,/SPISCS3 Direction" "Input,Output" bitfld.long 0x00 2. " SCSDIR2 ,/SPISCS2 Direction" "Input,Output" bitfld.long 0x00 1. " SCSDIR1 ,/SPISCS1 Direction" "Input,Output" textline " " bitfld.long 0x00 0. " SCSDIR0 ,/SPISCS0 Direction" "Input,Output" rgroup.long 0x1C++0x3 line.long 0x0 "PC2,Pin Control Register 2" bitfld.long 0x00 31. " SOMIDIN7 ,SPISOMI7 Data In" "Low,High" bitfld.long 0x00 30. " SOMIDIN6 ,SPISOMI6 Data In" "Low,High" bitfld.long 0x00 29. " SOMIDIN5 ,SPISOMI5 Data In" "Low,High" textline " " bitfld.long 0x00 28. " SOMIDIN4 ,SPISOMI4 Data In" "Low,High" bitfld.long 0x00 27. " SOMIDIN3 ,SPISOMI3 Data In" "Low,High" bitfld.long 0x00 26. " SOMIDIN2 ,SPISOMI2 Data In" "Low,High" textline " " bitfld.long 0x00 25. " SOMIDIN1 ,SPISOMI1 Data In" "Low,High" bitfld.long 0x00 24. " SOMIDIN0 ,SPISOMI0 Data In" "Low,High" bitfld.long 0x00 23. " SIMODIN7 ,SPISIMO7 Data In" "Low,High" textline " " bitfld.long 0x00 22. " SIMODIN6 ,SPISIMO6 Data In" "Low,High" bitfld.long 0x00 21. " SIMODIN5 ,SPISIMO5 Data In" "Low,High" bitfld.long 0x00 20. " SIMODIN4 ,SPISIMO4 Data In" "Low,High" textline " " bitfld.long 0x00 19. " SIMODIN3 ,SPISIMO3 Data In" "Low,High" bitfld.long 0x00 18. " SIMODIN2 ,SPISIMO2 Data In" "Low,High" bitfld.long 0x00 17. " SIMODIN1 ,SPISIMO1 Data In" "Low,High" textline " " bitfld.long 0x00 16. " SIMODIN0 ,SPISIMO0 Data In" "Low,High" bitfld.long 0x00 11. " SOMIDIN0 ,SPISOMI0 Data In" "Low,High" bitfld.long 0x00 10. " SIMODIN0 ,SPISIMO0 Data In" "Low,High" textline " " bitfld.long 0x00 9. " CLKDIN ,Clock Data In" "Low,High" bitfld.long 0x00 8. " ENADIN ,/SPIENA Data In" "Low,High" bitfld.long 0x00 7. " SCSDIN7 ,SPISCS7 Data In" "Low,High" textline " " bitfld.long 0x00 6. " SCSDIN6 ,SPISCS6 Data In" "Low,High" bitfld.long 0x00 5. " SCSDIN5 ,SPISCS5 Data In" "Low,High" bitfld.long 0x00 4. " SCSDIN4 ,SPISCS4 Data In" "Low,High" textline " " bitfld.long 0x00 3. " SCSDIN3 ,SPISCS3 Data In" "Low,High" bitfld.long 0x00 2. " SCSDIN2 ,SPISCS2 Data In" "Low,High" bitfld.long 0x00 1. " SCSDIN1 ,SPISCS1 Data In" "Low,High" textline " " bitfld.long 0x00 0. " SCSDIN0 ,SPISCS0 Data In" "Low,High" width 5. group.long 0x20++0x3 line.long 0x0 "PC3,Pin Control Register 3" setclrfld.long 0x00 31. 0x04 31. 0x08 31. " SOMIDOUT7_set/clr ,SPISOMI7 Dataout Write" "Low,High" setclrfld.long 0x00 30. 0x04 30. 0x08 30. " SOMIDOUT6_set/clr ,SPISOMI6 Dataout Write" "Low,High" textline " " setclrfld.long 0x00 29. 0x04 29. 0x08 29. " SOMIDOUT5_set/clr ,SPISOMI5 Dataout Write" "Low,High" setclrfld.long 0x00 28. 0x04 28. 0x08 28. " SOMIDOUT4_set/clr ,SPISOMI4 Dataout Write" "Low,High" textline " " setclrfld.long 0x00 27. 0x04 27. 0x08 27. " SOMIDOUT3_set/clr ,SPISOMI3 Dataout Write" "Low,High" setclrfld.long 0x00 26. 0x04 26. 0x08 26. " SOMIDOUT2_set/clr ,SPISOMI2 Dataout Write" "Low,High" textline " " setclrfld.long 0x00 25. 0x04 25. 0x08 25. " SOMIDOUT1_set/clr ,SPISOMI1 Dataout Write" "Low,High" setclrfld.long 0x00 24. 0x04 24. 0x08 24. " SOMIDOUT0_set/clr ,SPISOMI0 Dataout Write" "Low,High" textline " " setclrfld.long 0x00 23. 0x04 23. 0x08 23. " SIMODOUT7_set/clr ,SPISIMO7 Dataout Write" "Low,High" setclrfld.long 0x00 22. 0x04 22. 0x08 22. " SIMODOUT6_set/clr ,SPISIMO6 Dataout Write" "Low,High" textline " " setclrfld.long 0x00 21. 0x04 21. 0x08 21. " SIMODOUT5_set/clr ,SPISIMO5 Dataout Write" "Low,High" setclrfld.long 0x00 20. 0x04 20. 0x08 20. " SIMODOUT4_set/clr ,SPISIMO4 Dataout Write" "Low,High" textline " " setclrfld.long 0x00 19. 0x04 19. 0x08 19. " SIMODOUT3_set/clr ,SPISIMO3 Dataout Write" "Low,High" setclrfld.long 0x00 18. 0x04 18. 0x08 18. " SIMODOUT2_set/clr ,SPISIMO2 Dataout Write" "Low,High" textline " " setclrfld.long 0x00 17. 0x04 17. 0x08 17. " SIMODOUT1_set/clr ,SPISIMO1 Dataout Write" "Low,High" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " SIMODOUT0_set/clr ,SPISIMO0 Dataout Write" "Low,High" textline " " setclrfld.long 0x00 11. 0x04 11. 0x08 11. " SOMIDOUT0_set/clr ,SPISOMI0 Dataout Write" "Low,High" setclrfld.long 0x00 10. 0x04 10. 0x08 10. " SIMODOUT0_set/clr ,SPISIMO0 Dataout Write" "Low,High" textline " " setclrfld.long 0x00 9. 0x04 9. 0x08 9. " CLKDOUT_set/clr ,SPICLK Dataout Write" "Low,High" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " ENADOUT_set/clr ,/SPIENA Dataout Write" "Low,High" textline " " setclrfld.long 0x00 7. 0x04 7. 0x08 7. " SCSDOUT7_set/clr ,SPISCS7 Dataout Write" "Low,High" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " SCSDOUT6_set/clr ,SPISCS6 Dataout Write" "Low,High" textline " " setclrfld.long 0x00 5. 0x04 5. 0x08 5. " SCSDOUT5_set/clr ,SPISCS5 Dataout Write" "Low,High" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " SCSDOUT4_set/clr ,SPISCS4 Dataout Write" "Low,High" textline " " setclrfld.long 0x00 3. 0x04 3. 0x08 3. " SCSDOUT3_set/clr ,SPISCS3 Dataout Write" "Low,High" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " SCSDOUT2_set/clr ,SPISCS2 Dataout Write" "Low,High" textline " " setclrfld.long 0x00 1. 0x04 1. 0x08 1. " SCSDOUT1_set/clr ,SPISCS1 Dataout Write" "Low,High" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " SCSDOUT0_set/clr ,SPISCS0 Dataout Write" "Low,High" tree.end width 5. tree "SPI Pin Control Registers 6-8" group.long 0x2C++0x3 line.long 0x0 "PC6,Pin Control Register 1" bitfld.long 0x00 31. " SOMIPDR7 ,SPISOMI7 Open Drain Enable" "High,Tri-stated" bitfld.long 0x00 30. " SOMIPDR6 ,SPISOMI6 Open Drain Enable" "High,Tri-stated" bitfld.long 0x00 29. " SOMIPDR5 ,SPISOMI5 Open Drain Enable" "High,Tri-stated" textline " " bitfld.long 0x00 28. " SOMIPDR4 ,SPISOMI4 Open Drain Enable" "High,Tri-stated" bitfld.long 0x00 27. " SOMIPDR3 ,SPISOMI3 Open Drain Enable" "High,Tri-stated" bitfld.long 0x00 26. " SOMIPDR2 ,SPISOMI2 Open Drain Enable" "High,Tri-stated" textline " " bitfld.long 0x00 25. " SOMIPDR1 ,SPISOMI1 Open Drain Enable" "High,Tri-stated" bitfld.long 0x00 24. " SOMIPDR0 ,SPISOMI0 Open Drain Enable" "High,Tri-stated" bitfld.long 0x00 23. " SIMOPDR7 ,SPISIMO7 Open Drain Enable" "High,Tri-stated" textline " " bitfld.long 0x00 22. " SIMOPDR6 ,SPISIMO6 Open Drain Enable" "High,Tri-stated" bitfld.long 0x00 21. " SIMOPDR5 ,SPISIMO5 Open Drain Enable" "High,Tri-stated" bitfld.long 0x00 20. " SIMOPDR4 ,SPISIMO4 Open Drain Enable" "High,Tri-stated" textline " " bitfld.long 0x00 19. " SIMOPDR3 ,SPISIMO3 Open Drain Enable" "High,Tri-stated" bitfld.long 0x00 18. " SIMOPDR2 ,SPISIMO2 Open Drain Enable" "High,Tri-stated" bitfld.long 0x00 17. " SIMOPDR1 ,SPISIMO1 Open Drain Enable" "High,Tri-stated" textline " " bitfld.long 0x00 16. " SIMOPDR0 ,SPISIMO0 Open Drain Enable" "High,Tri-stated" bitfld.long 0x00 11. " SOMIPDR0 ,SPISOMI0 Open Drain Enable" "High,Tri-stated" bitfld.long 0x00 10. " SIMOPDR0 ,SPISIMO0 Open Drain Enable" "High,Tri-stated" textline " " bitfld.long 0x00 9. " CLKPDR ,SPICLK Open Drain Enable" "High,Tri-stated" bitfld.long 0x00 8. " ENAPDR ,/SPIENA Open Drain Enable" "High,Tri-stated" bitfld.long 0x00 7. " SCSPDR7 ,/SPISCS7 Open Drain" "High,Tri-stated" textline " " bitfld.long 0x00 6. " SCSPDR6 ,/SPISCS6 Open Drain" "High,Tri-stated" bitfld.long 0x00 5. " SCSPDR5 ,/SPISCS5 Open Drain" "High,Tri-stated" bitfld.long 0x00 4. " SCSPDR4 ,/SPISCS4 Open Drain" "High,Tri-stated" textline " " bitfld.long 0x00 3. " SCSPDR3 ,/SPISCS3 Open Drain" "High,Tri-stated" bitfld.long 0x00 2. " SCSPDR2 ,/SPISCS2 Open Drain" "High,Tri-stated" bitfld.long 0x00 1. " SCSPDR1 ,/SPISCS1 Open Drain" "High,Tri-stated" textline " " bitfld.long 0x00 0. " SCSPDR0 ,/SPISCS0 Open Drain" "High,Tri-stated" group.long 0x30++0x3 line.long 0x0 "PC7,Pin Control Register 7" bitfld.long 0x00 31. " SOMIPDIS7 ,SPISOMI7 Pull Control Enable/Disable" "Enabled,Disabled" bitfld.long 0x00 30. " SOMIPDIS6 ,SPISOMI6 Pull Control Enable/Disable" "Enabled,Disabled" bitfld.long 0x00 29. " SOMIPDIS5 ,SPISOMI5 Pull Control Enable/Disable" "Enabled,Disabled" textline " " bitfld.long 0x00 28. " SOMIPDIS4 ,SPISOMI4 Pull Control Enable/Disable" "Enabled,Disabled" bitfld.long 0x00 27. " SOMIPDIS3 ,SPISOMI3 Pull Control Enable/Disable" "Enabled,Disabled" bitfld.long 0x00 26. " SOMIPDIS2 ,SPISOMI2 Pull Control Enable/Disable" "Enabled,Disabled" textline " " bitfld.long 0x00 25. " SOMIPDIS1 ,SPISOMI1 Pull Control Enable/Disable" "Enabled,Disabled" bitfld.long 0x00 24. " SOMIPDIS0 ,SPISOMI0 Pull Control Enable/Disable" "Enabled,Disabled" bitfld.long 0x00 23. " SIMOPDIS7 ,SPISIMO7 Pull Control Enable/Disable" "Enabled,Disabled" textline " " bitfld.long 0x00 22. " SIMOPDIS6 ,SPISIMO6 Pull Control Enable/Disable" "Enabled,Disabled" bitfld.long 0x00 21. " SIMOPDIS5 ,SPISIMO5 Pull Control Enable/Disable" "Enabled,Disabled" bitfld.long 0x00 20. " SIMOPDIS4 ,SPISIMO4 Pull Control Enable/Disable" "Enabled,Disabled" textline " " bitfld.long 0x00 19. " SIMOPDIS3 ,SPISIMO3 Pull Control Enable/Disable" "Enabled,Disabled" bitfld.long 0x00 18. " SIMOPDIS2 ,SPISIMO2 Pull Control Enable/Disable" "Enabled,Disabled" bitfld.long 0x00 17. " SIMOPDIS1 ,SPISIMO1 Pull Control Enable/Disable" "Enabled,Disabled" textline " " bitfld.long 0x00 16. " SIMOPDIS0 ,SPISIMO0 Pull Control Enable/Disable" "Enabled,Disabled" bitfld.long 0x00 11. " SOMIPDIS0 ,SPISOMI0 Pull Control Enable/Disable" "Enabled,Disabled" bitfld.long 0x00 10. " SIMOPDIS0 ,SPISIMO Pull Control Enable/Disable" "Enabled,Disabled" textline " " bitfld.long 0x00 9. " CLKPDIS ,SPICLK Pull Control Enable/Disable" "Enabled,Disabled" bitfld.long 0x00 8. " ENAPDIS ,SPIENA Pull Control Enable/Disable" "Enabled,Disabled" bitfld.long 0x00 7. " SCSPDIS7 ,SPISCS7 Pull Control Enable/Disable" "Enabled,Disabled" textline " " bitfld.long 0x00 6. " SCSPDIS6 ,SPISCS6 Pull Control Enable/Disable" "Enabled,Disabled" bitfld.long 0x00 5. " SCSPDIS5 ,SPISCS5 Pull Control Enable/Disable" "Enabled,Disabled" bitfld.long 0x00 4. " SCSPDIS4 ,SPISCS4 Pull Control Enable/Disable" "Enabled,Disabled" textline " " bitfld.long 0x00 3. " SCSPDIS3 ,SPISCS3 Pull Control Enable/Disable" "Enabled,Disabled" bitfld.long 0x00 2. " SCSPDIS2 ,SPISCS2 Pull Control Enable/Disable" "Enabled,Disabled" bitfld.long 0x00 1. " SCSPDIS1 ,SPISCS1 Pull Control Enable/Disable" "Enabled,Disabled" textline " " bitfld.long 0x00 0. " SCSPDIS0 ,SPISCS0 Pull Control Enable/Disable" "Enabled,Disabled" group.long 0x34++0x3 line.long 0x0 "PC8,Pin Control Register 8" bitfld.long 0x00 31. " SOMIPSEL7 ,SPISOMI7 Pull Select" "Pull down,Pull up" bitfld.long 0x00 30. " SOMIPSEL6 ,SPISOMI6 Pull Select" "Pull down,Pull up" bitfld.long 0x00 29. " SOMIPSEL5 ,SPISOMI5 Pull Select" "Pull down,Pull up" textline " " bitfld.long 0x00 28. " SOMIPSEL4 ,SPISOMI4 Pull Select" "Pull down,Pull up" bitfld.long 0x00 27. " SOMIPSEL3 ,SPISOMI3 Pull Select" "Pull down,Pull up" bitfld.long 0x00 26. " SOMIPSEL2 ,SPISOMI2 Pull Select" "Pull down,Pull up" textline " " bitfld.long 0x00 25. " SOMIPSEL1 ,SPISOMI1 Pull Select" "Pull down,Pull up" bitfld.long 0x00 24. " SOMIPSEL0 ,SPISOMI0 Pull Select" "Pull down,Pull up" bitfld.long 0x00 23. " SIMOPSEL7 ,SPISIMO7 Pull Select" "Pull down,Pull up" textline " " bitfld.long 0x00 22. " SIMOPSEL6 ,SPISIMO6 Pull Select" "Pull down,Pull up" bitfld.long 0x00 21. " SIMOPSEL5 ,SPISIMO5 Pull Select" "Pull down,Pull up" bitfld.long 0x00 20. " SIMOPSEL4 ,SPISIMO4 Pull Select" "Pull down,Pull up" textline " " bitfld.long 0x00 19. " SIMOPSEL3 ,SPISIMO3 Pull Select" "Pull down,Pull up" bitfld.long 0x00 18. " SIMOPSEL2 ,SPISIMO2 Pull Select" "Pull down,Pull up" bitfld.long 0x00 17. " SIMOPSEL1 ,SPISIMO1 Pull Select" "Pull down,Pull up" textline " " bitfld.long 0x00 16. " SIMOPSEL0 ,SPISIMO0 Pull Select" "Pull down,Pull up" bitfld.long 0x00 11. " SOMIPSEL ,SPISOMI Pull Select" "Pull down,Pull up" bitfld.long 0x00 10. " SIMOPSEL ,SPISIMO Pull Select" "Pull down,Pull up" textline " " bitfld.long 0x00 9. " CLKPSEL ,SPICLK Pull Select" "Pull down,Pull up" bitfld.long 0x00 8. " ENAPSEL ,SPIENA Pull Select" "Pull down,Pull up" bitfld.long 0x00 7. " SCSPSEL7 ,/SPISCS7 Pull select" "Pull down,Pull up" textline " " bitfld.long 0x00 6. " SCSPSEL6 ,/SPISCS6 Pull select" "Pull down,Pull up" bitfld.long 0x00 5. " SCSPSEL5 ,/SPISCS5 Pull select" "Pull down,Pull up" bitfld.long 0x00 4. " SCSPSEL4 ,/SPISCS4 Pull select" "Pull down,Pull up" textline " " bitfld.long 0x00 3. " SCSPSEL3 ,/SPISCS3 Pull select" "Pull down,Pull up" bitfld.long 0x00 2. " SCSPSEL2 ,/SPISCS2 Pull select" "Pull down,Pull up" bitfld.long 0x00 1. " SCSPSEL1 ,/SPISCS1 Pull select" "Pull down,Pull up" textline " " bitfld.long 0x00 0. " SCSPSEL0 ,/SPISCS0 Pull select" "Pull down,Pull up" tree.end tree.end width 7. if (((d.l((ad:0xFFF7FC00+0x04)))&0x01000000)==0x01000000) group.long 0x38++0x3 line.long 0x0 "DAT0,Transmit Data Register 0" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,SPI / MibSPI Transmit Data" else rgroup.long 0x38++0x3 line.long 0x0 "DAT0,Transmit Data Register 0" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,SPI / MibSPI Transmit Data" endif if (((d.l((ad:0xFFF7FC00+0x04)))&0x01)==0x01) group.long 0x3C++0x3 line.long 0x0 "DAT1,Transmit Data Register 1" bitfld.long 0x00 28. " CSHOLD ,Chip Select Hold Mode" "Not active,Active" bitfld.long 0x00 26. " WDEL ,Enable the Delay Counter at the End of the Current Transaction" "Disabled,Enabled" bitfld.long 0x00 24.--25. " DFSEL ,Data Word Format Select" "0,1,2,3" textline " " hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip Select Number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,SPI/MibSPI Transmit Data" else group.long 0x3C++0x3 line.long 0x0 "DAT1,Transmit Data Register 1" bitfld.long 0x00 24.--25. " DFSEL ,Data Word Format Select" "0,1,2,3" hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip Select Number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,SPI/MibSPI Transmit Data" endif hgroup.long 0x40++0x3 hide.long 0x0 "BUF,Receive Buffer Register" in width 7. if (((d.l((ad:0xFFF7FC00+0x4)))&0x1)==0x1) rgroup.long 0x44++0x3 line.long 0x0 "EMU,Emulation Register" sif (cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")) bitfld.long 0x00 31. " RXEMPTY ,Receive Data Buffer Empty" "No empty,Empty" bitfld.long 0x00 30. " RXOVR ,Receive Data Buffer Overrun" "No overrun,Overrun" bitfld.long 0x00 29. " TXFULL ,Transmit Data Buffer Full" "Empty,Full" textline " " bitfld.long 0x00 28. " BITERR ,Mismatch of Internal Transmit Data and Transmitted Data" "Not occurred,Occurred" bitfld.long 0x00 27. " DESYNC ,De-synchronization of Slave Device" "No de-synchronized,De-synchronized" bitfld.long 0x00 26. " PARITYERR ,Calculated Parity Differs From Received Parity Bit" "No error,Error" textline " " bitfld.long 0x00 25. " TIMEOUT ,Time-out Due to Non-activation of ENA Pin" "Not occurred,Occurred" bitfld.long 0x00 24. " DLENERR ,Data Length Error Flag" "No error,Error" endif hexmask.long.byte 0x00 16.--23. 1. " LCSNR ,Last Chip Select Number" textline " " hexmask.long.word 0x00 0.--15. 1. " RXDATA ,SPI Receive Data" else rgroup.long 0x44++0x3 line.long 0x0 "EMU,Emulation Register" sif (cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")) bitfld.long 0x00 31. " RXEMPTY ,Receive Data Buffer Empty" "No empty,Empty" bitfld.long 0x00 30. " RXOVR ,Receive Data Buffer Overrun" "No overrun,Overrun" bitfld.long 0x00 29. " TXFULL ,Transmit Data Buffer Full" "Empty,Full" textline " " bitfld.long 0x00 28. " BITERR ,Mismatch of Internal Transmit Data and Transmitted Data" "Not occurred,Occurred" bitfld.long 0x00 26. " PARITYERR ,Calculated Parity Differs From Received Parity Bit" "No error,Error" bitfld.long 0x00 24. " DLENERR ,Data Length Error Flag" "No error,Error" textline " " endif hexmask.long.byte 0x00 16.--23. 1. " LCSNR ,Last Chip Select Number" hexmask.long.word 0x00 0.--15. 1. " RXDATA ,SPI Receive Data" endif if (((d.l((ad:0xFFF7FC00+0x4)))&0x1)==0x1) group.long 0x48++0x3 line.long 0x0 "DELAY,Delay Register" hexmask.long.byte 0x00 24.--31. 1. " C2TDELAY ,Chip Select Active to Transmit Start Delay" hexmask.long.byte 0x00 16.--23. 1. " T2CDELAY ,Transmit End to Chip Select Inactive Delay" hexmask.long.byte 0x00 8.--15. 1. " T2EDELAY ,Transmit Data Finished to ENA Pin Inactive Time Out" textline " " hexmask.long.byte 0x00 0.--7. 1. " C2EDELAY ,Chip Select Active to ENA Signal Active Time Out" else hgroup.long 0x48++0x3 hide.long 0x0 "DELAY,Delay Register" endif width 7. group.long 0x4C++0x3 line.long 0x0 "DEF,Default Chip Select Register" bitfld.long 0x00 7. " CSDEF7 ,Chip Select Default Pattern 7" "Low,High" bitfld.long 0x00 6. " CSDEF6 ,Chip Select Default Pattern 6" "Low,High" bitfld.long 0x00 5. " CSDEF5 ,Chip Select Default Pattern 5" "Low,High" bitfld.long 0x00 4. " CSDEF4 ,Chip Select Default Pattern 4" "Low,High" textline " " bitfld.long 0x00 3. " CSDEF3 ,Chip Select Default Pattern 3" "Low,High" bitfld.long 0x00 2. " CSDEF2 ,Chip Select Default Pattern 2" "Low,High" bitfld.long 0x00 1. " CSDEF1 ,Chip Select Default Pattern 1" "Low,High" bitfld.long 0x00 0. " CSDEF0 ,Chip Select Default Pattern 0" "Low,High" width 6. tree "SPI Data Format Registers" group.long 0x50++0x3 line.long 0x0 "FMT0,Data Format Register 0" bitfld.long 0x00 24.--29. " WDELAY0 ,Delay in Between Transmissions For Data Format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " PARPOL0 ,Parity Polarity" "Even,Odd" bitfld.long 0x00 22. " PARITY0_ENA ,Parity Enable for Data Format 0" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " WAITENA0 ,Master Waits for ENA Signal From Slave for Data Format 0" "Not wait,Wait" bitfld.long 0x00 20. " SHIFTDIR0 ,Shift Direction for Data Format 0" "MSB,LSB" bitfld.long 0x00 18. " DIS_CS_TIMERS0 ,Disable Chipselect Timers for this Format Register" "No,Yes" textline " " bitfld.long 0x00 17. " POLARITY0 ,SPI Data Format 0 Clock Polarity" "Low-inactive,High-inactive" bitfld.long 0x00 16. " PHASE0 ,SPI Data Format 0 Clock Delay" "Not delayed,Delayed" hexmask.long.byte 0x00 8.--15. 1. " PRESCALE0 ,SPI Data Format 0 Prescaler" textline " " bitfld.long 0x00 0.--4. " CHARLEN0 ,SPI Data Format 0 Data Word Length" "Reserved,Reserved,2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..." group.long 0x54++0x3 line.long 0x0 "FMT1,Data Format Register 1" bitfld.long 0x00 24.--29. " WDELAY1 ,Delay in Between Transmissions For Data Format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " PARPOL1 ,Parity Polarity" "Even,Odd" bitfld.long 0x00 22. " PARITY1_ENA ,Parity Enable for Data Format 1" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " WAITENA1 ,Master Waits for ENA Signal From Slave for Data Format 1" "Not wait,Wait" bitfld.long 0x00 20. " SHIFTDIR1 ,Shift Direction for Data Format 1" "MSB,LSB" bitfld.long 0x00 18. " DIS_CS_TIMERS1 ,Disable Chipselect Timers for this Format Register" "No,Yes" textline " " bitfld.long 0x00 17. " POLARITY1 ,SPI Data Format 1 Clock Polarity" "Low-inactive,High-inactive" bitfld.long 0x00 16. " PHASE1 ,SPI Data Format 1 Clock Delay" "Not delayed,Delayed" hexmask.long.byte 0x00 8.--15. 1. " PRESCALE1 ,SPI Data Format 1 Prescaler" textline " " bitfld.long 0x00 0.--4. " CHARLEN1 ,SPI Data Format 1 Data Word Length" "Reserved,Reserved,2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..." group.long 0x58++0x3 line.long 0x0 "FMT2,Data Format Register 2" bitfld.long 0x00 24.--29. " WDELAY2 ,Delay in Between Transmissions For Data Format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " PARPOL2 ,Parity Polarity" "Even,Odd" bitfld.long 0x00 22. " PARITY2_ENA ,Parity Enable for Data Format 2" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " WAITENA2 ,Master Waits for ENA Signal From Slave for Data Format 2" "Not wait,Wait" bitfld.long 0x00 20. " SHIFTDIR2 ,Shift Direction for Data Format 2" "MSB,LSB" bitfld.long 0x00 18. " DIS_CS_TIMERS2 ,Disable Chipselect Timers for this Format Register" "No,Yes" textline " " bitfld.long 0x00 17. " POLARITY2 ,SPI Data Format 2 Clock Polarity" "Low-inactive,High-inactive" bitfld.long 0x00 16. " PHASE2 ,SPI Data Format 2 Clock Delay" "Not delayed,Delayed" hexmask.long.byte 0x00 8.--15. 1. " PRESCALE2 ,SPI Data Format 2 Prescaler" textline " " bitfld.long 0x00 0.--4. " CHARLEN2 ,SPI Data Format 2 Data Word Length" "Reserved,Reserved,2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..." group.long 0x5C++0x3 line.long 0x0 "FMT3,Data Format Register 3" bitfld.long 0x00 24.--29. " WDELAY3 ,Delay in Between Transmissions For Data Format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " PARPOL3 ,Parity Polarity" "Even,Odd" bitfld.long 0x00 22. " PARITY3_ENA ,Parity Enable for Data Format 3" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " WAITENA3 ,Master Waits for ENA Signal From Slave for Data Format 3" "Not wait,Wait" bitfld.long 0x00 20. " SHIFTDIR3 ,Shift Direction for Data Format 3" "MSB,LSB" bitfld.long 0x00 18. " DIS_CS_TIMERS3 ,Disable Chipselect Timers for this Format Register" "No,Yes" textline " " bitfld.long 0x00 17. " POLARITY3 ,SPI Data Format 3 Clock Polarity" "Low-inactive,High-inactive" bitfld.long 0x00 16. " PHASE3 ,SPI Data Format 3 Clock Delay" "Not delayed,Delayed" hexmask.long.byte 0x00 8.--15. 1. " PRESCALE3 ,SPI Data Format 3 Prescaler" textline " " bitfld.long 0x00 0.--4. " CHARLEN3 ,SPI Data Format 3 Data Word Length" "Reserved,Reserved,2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..." tree.end width 12. tree "SPI Interrupt Vector Registers" if (((d.l((ad:0xFFF7FC00+0x70)))&0x01)==0x01) rgroup.long 0x60++0x3 line.long 0x0 "TGINTVECT0,Transfer Group Interrupt Vector Register 0" bitfld.long 0x00 1.--5. " INTVECT0 ,Interrupt Vector for Interrupt Line INT0" "No interrupt,Interrupt of transfer group 0,Interrupt of transfer group 1,Interrupt of transfer group 2,Interrupt of transfer group 3,Interrupt of transfer group 4,Interrupt of transfer group 5,Interrupt of transfer group 6,Interrupt of transfer group 7,Interrupt of transfer group 8,Interrupt of transfer group 9,Interrupt of transfer group 10,Interrupt of transfer group 11,Interrupt of transfer group 12,Interrupt of transfer group 13,Interrupt of transfer group 14,Interrupt of transfer group 15,Interrupt/SPIINT0,Reserved,RXORN Interrupt,?..." bitfld.long 0x00 0. " SUSPEND0 ,Transfer Suspended/Finished Interrupt" "Suspended,Finished" else rgroup.long 0x60++0x3 line.long 0x0 "TGINTVECT0,Transfer Group Interrupt Vector Register 0" bitfld.long 0x00 1.--5. " INTVECT0 ,Interrupt Vector for Interrupt Line INT0" "No interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Interrupt/SPIINT0,Receive Buffer Full Interrupt,Receive Buffer Overrun Interrupt,Transmit Buffer Empty Interrupt,?..." endif if (((d.l((ad:0xFFF7FC00+0x70)))&0x01)==0x01) rgroup.long 0x64++0x3 line.long 0x0 "TGINTVECT1,Transfer Group Interrupt Vector Register 1" bitfld.long 0x00 1.--5. " INTVECT1 ,Interrupt Vector for Interrupt Line INT1" "No interrupt,Interrupt of transfer group 0,Interrupt of transfer group 1,Interrupt of transfer group 2,Interrupt of transfer group 3,Interrupt of transfer group 4,Interrupt of transfer group 5,Interrupt of transfer group 6,Interrupt of transfer group 7,Interrupt of transfer group 8,Interrupt of transfer group 9,Interrupt of transfer group 10,Interrupt of transfer group 11,Interrupt of transfer group 12,Interrupt of transfer group 13,Interrupt of transfer group 14,Interrupt of transfer group 15,Interrupt/SPIINT1,Reserved,RXORN Interrupt,?..." bitfld.long 0x00 0. " SUSPEND1 ,Transfer Suspended/Finished Interrupt" "Suspended,Finished" else rgroup.long 0x64++0x3 line.long 0x0 "TGINTVECT1,Transfer Group Interrupt Vector Register 1" bitfld.long 0x00 1.--5. " INTVECT1 ,Interrupt Vector for Interrupt Line INT1" "No interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Interrupt/SPIINT1,Receive Buffer Full Interrupt,Receive Buffer Overrun Interrupt,Transmit Buffer Empty Interrupt,?..." endif tree.end width 8. sif (cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")&&(cpu()!=("TMS570LS10116-PGE"))&&(cpu()!=("TMS570LS10216-PGE"))&&(cpu()!=("TMS570LS10116-ZWT"))&&(cpu()!=("TMS570LS10216-ZWT"))&&(cpu()!=("TMS570LS10106-PGE"))&&(cpu()!=("TMS570LS10206-PGE"))&&(cpu()!=("TMS570LS10106-ZWT"))&&(cpu()!=("TMS570LS10206-ZWT"))) group.long 0x68++0x3 line.long 0x0 "SRSEL,Pin Control Register 9" bitfld.long 0x00 31. " SPISOMISRS7 ,Controls the Slew Rate for the SPISOMI7" "Normal,Slow" bitfld.long 0x00 30. " SPISOMISRS6 ,Controls the Slew Rate for the SPISOMI6" "Normal,Slow" bitfld.long 0x00 29. " SPISOMISRS5 ,Controls the Slew Rate for the SPISOMI5" "Normal,Slow" textline " " bitfld.long 0x00 28. " SPISOMISRS4 ,Controls the Slew Rate for the SPISOMI4" "Normal,Slow" bitfld.long 0x00 27. " SPISOMISRS3 ,Controls the Slew Rate for the SPISOMI3" "Normal,Slow" bitfld.long 0x00 26. " SPISOMISRS2 ,Controls the Slew Rate for the SPISOMI2" "Normal,Slow" textline " " bitfld.long 0x00 25. " SPISOMISRS1 ,Controls the Slew Rate for the SPISOMI1" "Normal,Slow" bitfld.long 0x00 24. " SPISOMISRS0 ,Controls the Slew Rate for the SPISOMI0" "Normal,Slow" bitfld.long 0x00 23. " SPISIMOSRC7 ,Controls the Slew Rate for the SPISIMO7" "Normal,Slow" textline " " bitfld.long 0x00 22. " SPISIMOSRC6 ,Controls the Slew Rate for the SPISIMO6" "Normal,Slow" bitfld.long 0x00 21. " SPISIMOSRC5 ,Controls the Slew Rate for the SPISIMO5" "Normal,Slow" bitfld.long 0x00 20. " SPISIMOSRC4 ,Controls the Slew Rate for the SPISIMO4" "Normal,Slow" textline " " bitfld.long 0x00 19. " SPISIMOSRC3 ,Controls the Slew Rate for the SPISIMO3" "Normal,Slow" bitfld.long 0x00 18. " SPISIMOSRC2 ,Controls the Slew Rate for the SPISIMO2" "Normal,Slow" bitfld.long 0x00 17. " SPISIMOSRC1 ,Controls the Slew Rate for the SPISIMO1" "Normal,Slow" textline " " bitfld.long 0x00 16. " SPISIMOSRC0 ,Controls the Slew Rate for the SPISIMO0" "Normal,Slow" bitfld.long 0x00 11. " SPISOMISRS0 ,Controls the Slew Rate for SPISOMI0" "Normal,Slow" bitfld.long 0x00 10. " SPISIMOSRS0 ,Controls the Slew Rate for SPISIMO0" "Normal,Slow" textline " " bitfld.long 0x00 9. " SPICLKSRS ,Controls the Slew Rate for SPICLK" "Normal,Slow" bitfld.long 0x00 8. " SPIENASRS0 ,Controls the Slew Rate for /SPIENA" "Fast,Slow" bitfld.long 0x00 7. " SPISCSSRS7 ,Controls the Slew Rate for the /SPISCS7" "Normal,Slow" textline " " bitfld.long 0x00 6. " SPISCSSRS6 ,Controls the Slew Rate for the /SPISCS6" "Normal,Slow" bitfld.long 0x00 5. " SPISCSSRS5 ,Controls the Slew Rate for the /SPISCS5" "Normal,Slow" bitfld.long 0x00 4. " SPISCSSRS4 ,Controls the Slew Rate for the /SPISCS4" "Normal,Slow" textline " " bitfld.long 0x00 3. " SPISCSSRS3 ,Controls the Slew Rate for the /SPISCS3" "Normal,Slow" bitfld.long 0x00 2. " SPISCSSRS2 ,Controls the Slew Rate for the /SPISCS2" "Normal,Slow" bitfld.long 0x00 1. " SPISCSSRS1 ,Controls the Slew Rate for the /SPISCS1" "Normal,Slow" textline " " bitfld.long 0x00 0. " SPISCSSRS0 ,Controls the Slew Rate for the /SPISCS0" "Normal,Slow" endif if (((d.l((ad:0xFFF7FC00+0x3c)))&0x03000000)==0x00) group.long 0x6c++0x03 line.long 0x00 "PMCTRL,Parallel/Modulo Mode Control Register" bitfld.long 0x00 5. " MOD_CLK_POL_0 ,Modulo Mode SPICLK Polarity" "Normal,Inverted" bitfld.long 0x00 2.--4. " MMODE_0 ,SPI Data Line Selection" "1-data,2-data,3-data,4-data,5-data,6-data,?..." sif (cpu()=="TMS570PSFC61") bitfld.long 0x00 0.--1. " PMODE_0 ,Parallel Mode" "1-data,2-data,4-data,?..." else bitfld.long 0x00 0.--1. " PMODE_0 ,Parallel Mode" "1-data,2-data,4-data,8-data" endif elif (((d.l((ad:0xFFF7FC00+0x3c)))&0x03000000)==0x01000000) group.long 0x6c++0x03 line.long 0x00 "PMCTRL,Parallel/Modulo Mode Control Register" bitfld.long 0x00 13. " MOD_CLK_POL_1 ,Modulo Mode SPICLK Polarity" "Normal,Inverted" bitfld.long 0x00 10.--12. " MMODE_1 ,SPI Data Line Selection" "1-data,2-data,3-data,4-data,5-data,6-data,?..." sif (cpu()=="TMS570PSFC61") bitfld.long 0x00 8.--9. " PMODE_1 ,Parallel Mode" "1-data,2-data,4-data,?..." else bitfld.long 0x00 8.--9. " PMODE_1 ,Parallel Mode" "1-data,2-data,4-data,8-data" endif elif (((d.l((ad:0xFFF7FC00+0x3c)))&0x03000000)==0x02000000) group.long 0x6c++0x03 line.long 0x00 "PMCTRL,Parallel/Modulo Mode Control Register" bitfld.long 0x00 21. " MOD_CLK_POL_2 ,Modulo Mode SPICLK Polarity" "Normal,Inverted" bitfld.long 0x00 18.--20. " MMODE_2 ,SPI Data Line Selection" "1-data,2-data,3-data,4-data,5-data,6-data,?..." sif (cpu()=="TMS570PSFC61") bitfld.long 0x00 16.--17. " PMODE_2 ,Parallel Mode" "1-data,2-data,4-data,?..." else bitfld.long 0x00 16.--17. " PMODE_2 ,Parallel Mode" "1-data,2-data,4-data,8-data" endif else group.long 0x6c++0x03 line.long 0x00 "PMCTRL,Parallel/Modulo Mode Control Register" bitfld.long 0x00 29. " MOD_CLK_POL_3 ,Modulo Mode SPICLK Polarity" "Normal,Inverted" bitfld.long 0x00 26.--28. " MMODE_3 ,SPI Data Line Selection" "1-data,2-data,3-data,4-data,5-data,6-data,?..." sif (cpu()=="TMS570PSFC61") bitfld.long 0x00 24.--25. " PMODE_3 ,Parallel Mode" "1-data,2-data,4-data,?..." else bitfld.long 0x00 24.--25. " PMODE_3 ,Parallel Mode" "1-data,2-data,4-data,8-data" endif endif width 11. tree "MibSPI Registers" group.long 0x70++0x3 line.long 0x0 "MIBSPIE,MibSPI Enable Register" bitfld.long 0x00 16. " RX_RAM_ACCESS ,Receive RAM Access Control Bit" "RX not writable,R/W" bitfld.long 0x00 0. " MSPIENA ,Multibuffer Mode Enable" "Disabled,Enabled" width 11. if (((d.l((ad:0xFFF7FC00+0x70)))&0x01)==0x01) group.long 0x74++0x3 line.long 0x0 "TGITENST,MibSPI Transfer Group Interrupt Enable Register" sif cpu()!=("TMS570PSFC61")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE") setclrfld.long 0x00 31. 0x00 31. 0x04 31. " INTEN_RDY15_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x04 30. " INTEN_RDY14_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 29. 0x00 29. 0x04 29. " INTEN_RDY13_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x04 28. " INTEN_RDY12_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 27. 0x00 27. 0x04 27. " INTEN_RDY11_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x04 26. " INTEN_RDY10_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x04 25. " INTEN_RDY9_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x04 24. " INTEN_RDY8_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled" textline " " endif setclrfld.long 0x00 23. 0x00 23. 0x04 23. " INTEN_RDY7_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x04 22. " INTEN_RDY6_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 21. 0x00 21. 0x04 21. " INTEN_RDY5_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x04 20. " INTEN_RDY4_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x04 19. " INTEN_RDY3_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x04 18. " INTEN_RDY2_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 17. 0x00 17. 0x04 17. " INTEN_RDY1_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x04 16. " INTEN_RDY0_set/clr ,Transfer Group Interrupt Enable When Transfer Finished" "Disabled,Enabled" textline " " sif cpu()!=("TMS570PSFC61")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE") setclrfld.long 0x00 15. 0x00 15. 0x04 15. " INTEN_SUS15_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x04 14. " INTEN_SUS14_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x04 13. " INTEN_SUS13_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x04 12. " INTEN_SUS12_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled" textline " " setclrfld.long 0x00 11. 0x00 11. 0x04 11. " INTEN_SUS11_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x04 10. " INTEN_SUS10_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled" textline " " setclrfld.long 0x00 9. 0x00 9. 0x04 9. " INTEN_SUS9_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x04 8. " INTEN_SUS8_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled" textline " " endif setclrfld.long 0x00 7. 0x00 7. 0x04 7. " INTEN_SUS7_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x04 6. " INTEN_SUS6_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. 0x00 5. 0x04 5. " INTEN_SUS5_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x04 4. " INTEN_SUS4_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled" textline " " setclrfld.long 0x00 3. 0x00 3. 0x04 3. " INTEN_SUS3_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x04 2. " INTEN_SUS2_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x04 1. " INTEN_SUS1_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x04 0. " INTEN_SUS0_set/clr ,Transfer Group Interrupt Enable When Transfer Suspended" "Disabled,Enabled" width 11. group.long 0x7c++0x3 line.long 0x00 "TGITLVST,MibSPI Transfer Group Interrupt Level Set Register" sif cpu()!=("TMS570PSFC61")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE") setclrfld.long 0x00 31. 0x00 31. 0x04 31. " INTLVL_RDY15_set/clr ,Transfer Group Completed Interrupt Level 15" "INT0,INT1" setclrfld.long 0x00 30. 0x00 30. 0x04 30. " INTLVL_RDY14_set/clr ,Transfer Group Completed Interrupt Level 14" "INT0,INT1" textline " " setclrfld.long 0x00 29. 0x00 29. 0x04 29. " INTLVL_RDY13_set/clr ,Transfer Group Completed Interrupt Level 13" "INT0,INT1" setclrfld.long 0x00 28. 0x00 28. 0x04 28. " INTLVL_RDY12_set/clr ,Transfer Group Completed Interrupt Level 12" "INT0,INT1" textline " " setclrfld.long 0x00 27. 0x00 27. 0x04 27. " INTLVL_RDY11_set/clr ,Transfer Group Completed Interrupt Level 11" "INT0,INT1" setclrfld.long 0x00 26. 0x00 26. 0x04 26. " INTLVL_RDY10_set/clr ,Transfer Group Completed Interrupt Level 10" "INT0,INT1" textline " " setclrfld.long 0x00 25. 0x00 25. 0x04 25. " INTLVL_RDY9_set/clr ,Transfer Group Completed Interrupt Level Set 9" "INT0,INT1" setclrfld.long 0x00 24. 0x00 24. 0x04 24. " INTLVL_RDY8_set/clr ,Transfer Group Completed Interrupt Level Set 8" "INT0,INT1" textline " " endif setclrfld.long 0x00 23. 0x00 23. 0x04 23. " INTLVL_RDY7_set/clr ,Transfer Group Completed Interrupt Level Set 7" "INT0,INT1" setclrfld.long 0x00 22. 0x00 22. 0x04 22. " INTLVL_RDY6_set/clr ,Transfer Group Completed Interrupt Level Set 6" "INT0,INT1" textline " " setclrfld.long 0x00 21. 0x00 21. 0x04 21. " INTLVL_RDY5_set/clr ,Transfer Group Completed Interrupt Level Set 5" "INT0,INT1" setclrfld.long 0x00 20. 0x00 20. 0x04 20. " INTLVL_RDY4_set/clr ,Transfer Group Completed Interrupt Level Set 4" "INT0,INT1" textline " " setclrfld.long 0x00 19. 0x00 19. 0x04 19. " INTLVL_RDY3_set/clr ,Transfer Group Completed Interrupt Level Set 3" "INT0,INT1" setclrfld.long 0x00 18. 0x00 18. 0x04 18. " INTLVL_RDY2_set/clr ,Transfer Group Completed Interrupt Level Set 2" "INT0,INT1" textline " " setclrfld.long 0x00 17. 0x00 17. 0x04 17. " INTLVL_RDY1_set/clr ,Transfer Group Completed Interrupt Level Set 1" "INT0,INT1" setclrfld.long 0x00 16. 0x00 16. 0x04 16. " INTLVL_RDY0_set/clr ,Transfer Group Completed Interrupt Level Set 0" "INT0,INT1" textline " " sif cpu()!=("TMS570PSFC61")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE") setclrfld.long 0x00 15. 0x00 15. 0x04 15. " INTLVL_SUS15_set/clr ,Transfer Group Suspended Interrupt Level Set 15" "INT0,INT1" setclrfld.long 0x00 14. 0x00 14. 0x04 14. " INTLVL_SUS14_set/clr ,Transfer Group Suspended Interrupt Level Set 14" "INT0,INT1" textline " " setclrfld.long 0x00 13. 0x00 13. 0x04 13. " INTLVL_SUS13_set/clr ,Transfer Group Suspended Interrupt Level Set 13" "INT0,INT1" setclrfld.long 0x00 12. 0x00 12. 0x04 12. " INTLVL_SUS12_set/clr ,Transfer Group Suspended Interrupt Level Set 12" "INT0,INT1" textline " " setclrfld.long 0x00 11. 0x00 11. 0x04 11. " INTLVL_SUS11_set/clr ,Transfer Group Suspended Interrupt Level Set 11" "INT0,INT1" setclrfld.long 0x00 10. 0x00 10. 0x04 10. " INTLVL_SUS10_set/clr ,Transfer Group Suspended Interrupt Level Set 10" "INT0,INT1" textline " " setclrfld.long 0x00 9. 0x00 9. 0x04 9. " INTLVL_SUS9_set/clr ,Transfer Group Suspended Interrupt Level Set 9" "INT0,INT1" setclrfld.long 0x00 8. 0x00 8. 0x04 8. " INTLVL_SUS8_set/clr ,Transfer Group Suspended Interrupt Level Set 8" "INT0,INT1" textline " " endif setclrfld.long 0x00 7. 0x00 7. 0x04 7. " INTLVL_SUS7_set/clr ,Transfer Group Suspended Interrupt Level Set 7" "INT0,INT1" setclrfld.long 0x00 6. 0x00 6. 0x04 6. " INTLVL_SUS6_set/clr ,Transfer Group Suspended Interrupt Level Set 6" "INT0,INT1" textline " " setclrfld.long 0x00 5. 0x00 5. 0x04 5. " INTLVL_SUS5_set/clr ,Transfer Group Suspended Interrupt Level Set 5" "INT0,INT1" setclrfld.long 0x00 4. 0x00 4. 0x04 4. " INTLVL_SUS4_set/clr ,Transfer Group Suspended Interrupt Level Set 4" "INT0,INT1" textline " " setclrfld.long 0x00 3. 0x00 3. 0x04 3. " INTLVL_SUS3_set/clr ,Transfer Group Suspended Interrupt Level Set 3" "INT0,INT1" setclrfld.long 0x00 2. 0x00 2. 0x04 2. " INTLVL_SUS2_set/clr ,Transfer Group Suspended Interrupt Level Set 2" "INT0,INT1" textline " " setclrfld.long 0x00 1. 0x00 1. 0x04 1. " INTLVL_SUS1_set/clr ,Transfer Group Suspended Interrupt Level Set 1" "INT0,INT1" setclrfld.long 0x00 0. 0x00 0. 0x04 0. " INTLVL_SUS0_set/clr ,Transfer Group Suspended Interrupt Level Set 0" "INT0,INT1" width 11. group.long 0x84++0x3 line.long 0x00 "TGINTFLAG,Transfer Group Interrupt Flag Register" sif cpu()!=("TMS570PSFC61")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE") eventfld.long 0x00 31. " INTFLGRDY15 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 30. " INTFLGRDY14 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 29. " INTFLGRDY13 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 28. " INTFLGRDY12 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 27. " INTFLGRDY11 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 26. " INTFLGRDY10 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 25. " INTFLGRDY9 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 24. " INTFLGRDY8 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt" textline " " endif eventfld.long 0x00 23. " INTFLGRDY7 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 22. " INTFLGRDY6 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 21. " INTFLGRDY5 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 20. " INTFLGRDY4 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 19. " INTFLGRDY3 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 18. " INTFLGRDY2 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 17. " INTFLGRDY1 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 16. " INTFLGRDY0 ,Transfer Group Interrupt Flag for Transfer Finished Interrupt" "No interrupt,Interrupt" textline " " sif cpu()!=("TMS570PSFC61")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE") eventfld.long 0x00 15. " INTFLGSUS15 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 14. " INTFLGSUS14 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 13. " INTFLGSUS13 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 12. " INTFLGSUS12 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 11. " INTFLGSUS11 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 10. " INTFLGSUS10 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 9. " INTFLGSUS9 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 8. " INTFLGSUS8 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt" textline " " endif eventfld.long 0x00 7. " INTFLGSUS7 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 6. " INTFLGSUS6 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 5. " INTFLGSUS5 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 4. " INTFLGSUS4 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " INTFLGSUS3 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 2. " INTFLGSUS2 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 1. " INTFLGSUS1 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 0. " INTFLGSUS0 ,Transfer Group Interrupt Flag for Transfer Suspend Interrupt" "No interrupt,Interrupt" width 11. group.long 0x90++0x3 line.long 0x00 "TICKCNT,Tick Count Register" bitfld.long 0x00 31. " TICKENA ,Tick Counter Enable" "Disabled,Enabled" bitfld.long 0x00 30. " RELOAD ,Re-load Tick Counter" "No effect,Reload" textline " " bitfld.long 0x00 28.--29. " CLKCTRL ,Tick Counter Clock Source Control" "Format 0,Format 1,Format 2,Format 3" hexmask.long.word 0x00 0.--15. 1. " TICKVALUE ,Initial Value for Tick Counter" group.long 0x94++0x3 line.long 0x00 "LTGPEND,Last Transfer Group End Pointer" sif cpu()==("TMS570PSFC61")||cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10206-PGE") bitfld.long 0x00 24.--28. " TG_IN_SERVICE ,Transfer Group Currently Being Serviced by the Sequencer" "Not serviced,Group0,Group1,Group2,Group3,Group4,Group5,Group6,Group7,?..." else bitfld.long 0x00 24.--28. " TG_IN_SERVICE ,Transfer Group Currently Being Serviced by the Sequencer" "Not serviced,Group0,Group1,Group2,Group3,Group4,Group5,Group6,Group7,Group8,Group9,Group10,Group11,Group12,Group13,Group14,Group15,?..." endif hexmask.long.byte 0x00 8.--14. 1. " LPEND ,Last Transfer Group End Pointer" else hgroup.long 0x74++0x3 hide.long 0x00 "TGITENST,MibSPI Transfer Group Interrupt Enable Register" hgroup.long 0x7C++0x3 hide.long 0x00 "TGITLVST,MibSPI Transfer Group Interrupt Level Register" hgroup.long 0x84++0x3 hide.long 0x00 "TGINTFLAG,Transfer Group Interrupt Flag Register" hgroup.long 0x90++0x03 hide.long 0x00 "TICKCNT,Tick Count Register" hgroup.long 0x94++0x3 hide.long 0x00 "LTGPEND,Last Transfer Group End Pointer" endif width 9. tree "MibSPI Transfer Group Control Registers" if (((d.l((ad:0xFFF7FC00+0x70)))&0x01)==0x01) sif (cpu()!="TMS570PSFC61")&&(cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")) group.long 0x98++0x3 line.long 0x00 "TG0CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA0 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT0 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST0 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD0 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT0 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC0 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART0 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT0 ,Transfer Group Pointer to Current Buffer" group.long 0x9C++0x3 line.long 0x00 "TG1CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA1 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT1 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST1 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD1 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT1 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC1 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART1 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT1 ,Transfer Group Pointer to Current Buffer" group.long 0xA0++0x3 line.long 0x00 "TG2CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA2 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT2 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST2 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD2 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT2 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC2 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART2 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT2 ,Transfer Group Pointer to Current Buffer" group.long 0xA4++0x3 line.long 0x00 "TG3CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA3 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT3 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST3 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD3 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT3 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC3 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART3 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT3 ,Transfer Group Pointer to Current Buffer" group.long 0xA8++0x3 line.long 0x00 "TG4CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA4 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT4 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST4 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD4 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT4 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC4 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART4 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT4 ,Transfer Group Pointer to Current Buffer" group.long 0xAC++0x3 line.long 0x00 "TG5CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA5 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT5 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST5 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD5 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT5 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC5 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART5 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT5 ,Transfer Group Pointer to Current Buffer" group.long 0xB0++0x3 line.long 0x00 "TG6CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA6 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT6 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST6 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD6 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT6 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC6 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART6 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT6 ,Transfer Group Pointer to Current Buffer" group.long 0xB4++0x3 line.long 0x00 "TG7CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA7 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT7 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST7 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD7 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT7 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC7 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART7 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT7 ,Transfer Group Pointer to Current Buffer" else group.long 0x98++0x3 line.long 0x00 "TG0CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA0 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT0 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST0 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD0 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT0 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC0 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART0 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT0 ,Transfer Group Pointer to Current Buffer" group.long 0x9C++0x3 line.long 0x00 "TG1CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA1 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT1 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST1 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD1 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT1 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC1 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART1 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT1 ,Transfer Group Pointer to Current Buffer" group.long 0xA0++0x3 line.long 0x00 "TG2CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA2 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT2 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST2 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD2 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT2 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC2 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART2 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT2 ,Transfer Group Pointer to Current Buffer" group.long 0xA4++0x3 line.long 0x00 "TG3CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA3 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT3 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST3 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD3 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT3 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC3 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART3 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT3 ,Transfer Group Pointer to Current Buffer" group.long 0xA8++0x3 line.long 0x00 "TG4CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA4 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT4 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST4 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD4 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT4 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC4 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART4 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT4 ,Transfer Group Pointer to Current Buffer" group.long 0xAC++0x3 line.long 0x00 "TG5CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA5 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT5 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST5 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD5 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT5 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC5 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART5 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT5 ,Transfer Group Pointer to Current Buffer" group.long 0xB0++0x3 line.long 0x00 "TG6CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA6 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT6 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST6 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD6 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT6 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC6 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART6 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT6 ,Transfer Group Pointer to Current Buffer" group.long 0xB4++0x3 line.long 0x00 "TG7CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA7 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT7 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST7 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD7 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT7 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC7 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART7 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT7 ,Transfer Group Pointer to Current Buffer" group.long 0xB8++0x3 line.long 0x00 "TG8CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA8 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT8 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST8 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD8 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT8 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC8 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART8 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT8 ,Transfer Group Pointer to Current Buffer" group.long 0xBC++0x3 line.long 0x00 "TG9CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA9 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT9 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST9 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD9 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT9 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC9 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART9 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT9 ,Transfer Group Pointer to Current Buffer" group.long 0xC0++0x3 line.long 0x00 "TG10CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA10 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT10 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST10 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD10 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT10 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC10 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART10 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT10 ,Transfer Group Pointer to Current Buffer" group.long 0xC4++0x3 line.long 0x00 "TG11CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA11 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT11 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST11 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD11 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT11 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC11 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART11 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT11 ,Transfer Group Pointer to Current Buffer" group.long 0xC8++0x3 line.long 0x00 "TG12CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA12 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT12 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST12 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD12 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT12 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC12 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART12 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT12 ,Transfer Group Pointer to Current Buffer" group.long 0xCC++0x3 line.long 0x00 "TG13CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA13 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT13 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST13 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD13 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT13 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC13 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART13 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT13 ,Transfer Group Pointer to Current Buffer" group.long 0xD0++0x3 line.long 0x00 "TG14CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA14 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT14 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST14 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD14 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT14 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC14 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART14 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT14 ,Transfer Group Pointer to Current Buffer" group.long 0xD4++0x3 line.long 0x00 "TG15CTRL,MibSPI Transfer Group Control Register" bitfld.long 0x00 31. " TGENA15 ,Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT15 ,Single Transfer for this Transfer Group Enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST15 ,Transfer Group Pointer Reset Mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD15 ,Transfer Group Triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT15 ,Type of Trigger Event" "Never,Rising edge,Falling edge,Both edges,Reserved,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC15 ,Trigger Source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART15 ,Transfer Group Start Address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT15 ,Transfer Group Pointer to Current Buffer" endif else sif cpu()==("TMS570PSFC61")||cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10206-PGE") hgroup.long 0x98++0x3 hide.long 0x00 "TG0CTRL,MibSPI Transfer Group Control Register" hgroup.long 0x9C++0x3 hide.long 0x00 "TG1CTRL,MibSPI Transfer Group Control Register" hgroup.long 0xA0++0x3 hide.long 0x00 "TG2CTRL,MibSPI Transfer Group Control Register" hgroup.long 0xA4++0x3 hide.long 0x00 "TG3CTRL,MibSPI Transfer Group Control Register" hgroup.long 0xA8++0x3 hide.long 0x00 "TG4CTRL,MibSPI Transfer Group Control Register" hgroup.long 0xAC++0x3 hide.long 0x00 "TG5CTRL,MibSPI Transfer Group Control Register" hgroup.long 0xB0++0x3 hide.long 0x00 "TG6CTRL,MibSPI Transfer Group Control Register" hgroup.long 0xB4++0x3 hide.long 0x00 "TG7CTRL,MibSPI Transfer Group Control Register" else hgroup.long 0x98++0x3 hide.long 0x00 "TG0CTRL,MibSPI Transfer Group Control Register" hgroup.long 0x9C++0x3 hide.long 0x00 "TG1CTRL,MibSPI Transfer Group Control Register" hgroup.long 0xA0++0x3 hide.long 0x00 "TG2CTRL,MibSPI Transfer Group Control Register" hgroup.long 0xA4++0x3 hide.long 0x00 "TG3CTRL,MibSPI Transfer Group Control Register" hgroup.long 0xA8++0x3 hide.long 0x00 "TG4CTRL,MibSPI Transfer Group Control Register" hgroup.long 0xAC++0x3 hide.long 0x00 "TG5CTRL,MibSPI Transfer Group Control Register" hgroup.long 0xB0++0x3 hide.long 0x00 "TG6CTRL,MibSPI Transfer Group Control Register" hgroup.long 0xB4++0x3 hide.long 0x00 "TG7CTRL,MibSPI Transfer Group Control Register" hgroup.long 0xB8++0x3 hide.long 0x00 "TG8CTRL,MibSPI Transfer Group Control Register" hgroup.long 0xBC++0x3 hide.long 0x00 "TG9CTRL,MibSPI Transfer Group Control Register" hgroup.long 0xC0++0x3 hide.long 0x00 "TG10CTRL,MibSPI Transfer Group Control Register" hgroup.long 0xC4++0x3 hide.long 0x00 "TG11CTRL,MibSPI Transfer Group Control Register" hgroup.long 0xC8++0x3 hide.long 0x00 "TG12CTRL,MibSPI Transfer Group Control Register" hgroup.long 0xCC++0x3 hide.long 0x00 "TG13CTRL,MibSPI Transfer Group Control Register" hgroup.long 0xD0++0x3 hide.long 0x00 "TG14CTRL,MibSPI Transfer Group Control Register" hgroup.long 0xD4++0x3 hide.long 0x00 "TG15CTRL,MibSPI Transfer Group Control Register" endif endif tree.end width 17. if ((((d.l((ad:0xFFF7FC00+0x4)))&0x1)==0x1)&&((d.l((ad:0xFFF7FC00+0x70)))&0x1)==0x1) group.long 0xD8++0x3 line.long 0x00 "DMA0CTRL,MibSPI DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT0 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 0" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID0 ,Buffer Utilized for DMA Transfer 0" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP0 ,Receive Data DMA Request Map 0" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP0 ,Transmit Data DMA Channel 0" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA0 ,Receive Data DMA Channel Enable 0" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA0 ,Transmit Data DMA Channel Enable 0" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK0 ,Non-interleaved DMA Block Transfer 0" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT0 ,Initial Count of DMA Transfers 0" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT170 ,The 17th Bit of COUNT Field of DMA0COUNT Register" "Low,High" bitfld.long 0x00 0.--5. " COUNT0 ,Actual Number of Remaining DMA Transfer 0" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l((ad:0xFFF7FC00+0x4)))&0x1)==0x0)&&((d.l((ad:0xFFF7FC00+0x70)))&0x1)==0x1) group.long 0xD8++0x3 line.long 0x00 "DMA0CTRL,MibSPI DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT0 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 0" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID0 ,Buffer Utilized for DMA Transfer 0" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP0 ,Receive Data DMA Request Map 0" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP0 ,Transmit Data DMA Channel 0" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA0 ,Receive Data DMA Channel Enable 0" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA0 ,Transmit Data DMA Channel Enable 0" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT0 ,Initial Count of DMA Transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT170 ,The 17th Bit of COUNT Field of DMA0COUNT Register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT0 ,Actual Number of Remaining DMA Transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xD8++0x3 hide.long 0x00 "DMA0CTRL,MibSPI DMA Channel Control Register" endif if ((((d.l((ad:0xFFF7FC00+0x4)))&0x1)==0x1)&&((d.l((ad:0xFFF7FC00+0x70)))&0x1)==0x1) group.long 0xDC++0x3 line.long 0x00 "DMA1CTRL,MibSPI DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT1 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 1" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID1 ,Buffer Utilized for DMA Transfer 1" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP1 ,Receive Data DMA Request Map 1" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP1 ,Transmit Data DMA Channel 1" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA1 ,Receive Data DMA Channel Enable 1" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA1 ,Transmit Data DMA Channel Enable 1" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK1 ,Non-interleaved DMA Block Transfer 1" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT1 ,Initial Count of DMA Transfers 1" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT171 ,The 17th Bit of COUNT Field of DMA1COUNT Register" "Low,High" bitfld.long 0x00 0.--5. " COUNT1 ,Actual Number of Remaining DMA Transfer 1" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l((ad:0xFFF7FC00+0x4)))&0x1)==0x0)&&((d.l((ad:0xFFF7FC00+0x70)))&0x1)==0x1) group.long 0xDC++0x3 line.long 0x00 "DMA1CTRL,MibSPI DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT1 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 1" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID1 ,Buffer Utilized for DMA Transfer 1" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP1 ,Receive Data DMA Request Map 1" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP1 ,Transmit Data DMA Channel 1" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA1 ,Receive Data DMA Channel Enable 1" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA1 ,Transmit Data DMA Channel Enable 1" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT1 ,Initial Count of DMA Transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT171 ,The 17th Bit of COUNT Field of DMA1COUNT Register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT1 ,Actual Number of Remaining DMA Transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xDC++0x3 hide.long 0x00 "DMA1CTRL,MibSPI DMA Channel Control Register" endif if ((((d.l((ad:0xFFF7FC00+0x4)))&0x1)==0x1)&&((d.l((ad:0xFFF7FC00+0x70)))&0x1)==0x1) group.long 0xE0++0x3 line.long 0x00 "DMA2CTRL,MibSPI DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT2 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 2" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID2 ,Buffer Utilized for DMA Transfer 2" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP2 ,Receive Data DMA Request Map 2" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP2 ,Transmit Data DMA Channel 2" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA2 ,Receive Data DMA Channel Enable 2" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA2 ,Transmit Data DMA Channel Enable 2" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK2 ,Non-interleaved DMA Block Transfer 2" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT2 ,Initial Count of DMA Transfers 2" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT172 ,The 17th Bit of COUNT Field of DMA2COUNT Register" "Low,High" bitfld.long 0x00 0.--5. " COUNT2 ,Actual Number of Remaining DMA Transfer 2" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l((ad:0xFFF7FC00+0x4)))&0x1)==0x0)&&((d.l((ad:0xFFF7FC00+0x70)))&0x1)==0x1) group.long 0xE0++0x3 line.long 0x00 "DMA2CTRL,MibSPI DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT2 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 2" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID2 ,Buffer Utilized for DMA Transfer 2" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP2 ,Receive Data DMA Request Map 2" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP2 ,Transmit Data DMA Channel 2" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA2 ,Receive Data DMA Channel Enable 2" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA2 ,Transmit Data DMA Channel Enable 2" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT2 ,Initial Count of DMA Transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT172 ,The 17th Bit of COUNT Field of DMA2COUNT Register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT2 ,Actual Number of Remaining DMA Transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xE0++0x3 hide.long 0x00 "DMA2CTRL,MibSPI DMA Channel Control Register" endif if ((((d.l((ad:0xFFF7FC00+0x4)))&0x1)==0x1)&&((d.l((ad:0xFFF7FC00+0x70)))&0x1)==0x1) group.long 0xE4++0x3 line.long 0x00 "DMA3CTRL,MibSPI DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT3 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 3" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID3 ,Buffer Utilized for DMA Transfer 3" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP3 ,Receive Data DMA Request Map 3" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP3 ,Transmit Data DMA Channel 3" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA3 ,Receive Data DMA Channel Enable 3" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA3 ,Transmit Data DMA Channel Enable 3" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK3 ,Non-interleaved DMA Block Transfer 3" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT3 ,Initial Count of DMA Transfers 3" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT173 ,The 17th Bit of COUNT Field of DMA3COUNT Register" "Low,High" bitfld.long 0x00 0.--5. " COUNT3 ,Actual Number of Remaining DMA Transfer 3" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l((ad:0xFFF7FC00+0x4)))&0x1)==0x0)&&((d.l((ad:0xFFF7FC00+0x70)))&0x1)==0x1) group.long 0xE4++0x3 line.long 0x00 "DMA3CTRL,MibSPI DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT3 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 3" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID3 ,Buffer Utilized for DMA Transfer 3" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP3 ,Receive Data DMA Request Map 3" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP3 ,Transmit Data DMA Channel 3" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA3 ,Receive Data DMA Channel Enable 3" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA3 ,Transmit Data DMA Channel Enable 3" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT3 ,Initial Count of DMA Transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT173 ,The 17th Bit of COUNT Field of DMA3COUNT Register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT3 ,Actual Number of Remaining DMA Transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xE4++0x3 hide.long 0x00 "DMA3CTRL,MibSPI DMA Channel Control Register" endif if ((((d.l((ad:0xFFF7FC00+0x4)))&0x1)==0x1)&&((d.l((ad:0xFFF7FC00+0x70)))&0x1)==0x1) group.long 0xE8++0x3 line.long 0x00 "DMA4CTRL,MibSPI DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT4 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 4" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID4 ,Buffer Utilized for DMA Transfer 4" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP4 ,Receive Data DMA Request Map 4" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP4 ,Transmit Data DMA Channel 4" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA4 ,Receive Data DMA Channel Enable 4" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA4 ,Transmit Data DMA Channel Enable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK4 ,Non-interleaved DMA Block Transfer 4" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT4 ,Initial Count of DMA Transfers 4" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT174 ,The 17th Bit of COUNT Field of DMA4COUNT Register" "Low,High" bitfld.long 0x00 0.--5. " COUNT4 ,Actual Number of Remaining DMA Transfer 4" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l((ad:0xFFF7FC00+0x4)))&0x1)==0x0)&&((d.l((ad:0xFFF7FC00+0x70)))&0x1)==0x1) group.long 0xE8++0x3 line.long 0x00 "DMA4CTRL,MibSPI DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT4 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 4" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID4 ,Buffer Utilized for DMA Transfer 4" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP4 ,Receive Data DMA Request Map 4" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP4 ,Transmit Data DMA Channel 4" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA4 ,Receive Data DMA Channel Enable 4" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA4 ,Transmit Data DMA Channel Enable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT4 ,Initial Count of DMA Transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT174 ,The 17th Bit of COUNT Field of DMA4COUNT Register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT4 ,Actual Number of Remaining DMA Transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xE8++0x3 hide.long 0x00 "DMA4CTRL,MibSPI DMA Channel Control Register" endif if ((((d.l((ad:0xFFF7FC00+0x4)))&0x1)==0x1)&&((d.l((ad:0xFFF7FC00+0x70)))&0x1)==0x1) group.long 0xEC++0x3 line.long 0x00 "DMA5CTRL,MibSPI DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT5 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 5" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID5 ,Buffer Utilized for DMA Transfer 5" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP5 ,Receive Data DMA Request Map 5" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP5 ,Transmit Data DMA Channel 5" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA5 ,Receive Data DMA Channel Enable 5" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA5 ,Transmit Data DMA Channel Enable 5" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK5 ,Non-interleaved DMA Block Transfer 5" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT5 ,Initial Count of DMA Transfers 5" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT175 ,The 17th Bit of COUNT Field of DMA5COUNT Register" "Low,High" bitfld.long 0x00 0.--5. " COUNT5 ,Actual Number of Remaining DMA Transfer 5" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l((ad:0xFFF7FC00+0x4)))&0x1)==0x0)&&((d.l((ad:0xFFF7FC00+0x70)))&0x1)==0x1) group.long 0xEC++0x3 line.long 0x00 "DMA5CTRL,MibSPI DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT5 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 5" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID5 ,Buffer Utilized for DMA Transfer 5" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP5 ,Receive Data DMA Request Map 5" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP5 ,Transmit Data DMA Channel 5" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA5 ,Receive Data DMA Channel Enable 5" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA5 ,Transmit Data DMA Channel Enable 5" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT5 ,Initial Count of DMA Transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT175 ,The 17th Bit of COUNT Field of DMA5COUNT Register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT5 ,Actual Number of Remaining DMA Transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xEC++0x3 hide.long 0x00 "DMA5CTRL,MibSPI DMA Channel Control Register" endif if ((((d.l((ad:0xFFF7FC00+0x4)))&0x1)==0x1)&&((d.l((ad:0xFFF7FC00+0x70)))&0x1)==0x1) group.long 0xF0++0x3 line.long 0x00 "DMA6CTRL,MibSPI DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT6 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 6" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID6 ,Buffer Utilized for DMA Transfer 6" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP6 ,Receive Data DMA Request Map 6" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP6 ,Transmit Data DMA Channel 6" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA6 ,Receive Data DMA Channel Enable 6" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA6 ,Transmit Data DMA Channel Enable 6" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK6 ,Non-interleaved DMA Block Transfer 6" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT6 ,Initial Count of DMA Transfers 6" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT176 ,The 17th Bit of COUNT Field of DMA6COUNT Register" "Low,High" bitfld.long 0x00 0.--5. " COUNT6 ,Actual Number of Remaining DMA Transfer 6" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l((ad:0xFFF7FC00+0x4)))&0x1)==0x0)&&((d.l((ad:0xFFF7FC00+0x70)))&0x1)==0x1) group.long 0xF0++0x3 line.long 0x00 "DMA6CTRL,MibSPI DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT6 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 6" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID6 ,Buffer Utilized for DMA Transfer 6" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP6 ,Receive Data DMA Request Map 6" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP6 ,Transmit Data DMA Channel 6" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA6 ,Receive Data DMA Channel Enable 6" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA6 ,Transmit Data DMA Channel Enable 6" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT6 ,Initial Count of DMA Transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT176 ,The 17th Bit of COUNT Field of DMA6COUNT Register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT6 ,Actual Number of Remaining DMA Transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xF0++0x3 hide.long 0x00 "DMA6CTRL,MibSPI DMA Channel Control Register" endif if ((((d.l((ad:0xFFF7FC00+0x4)))&0x1)==0x1)&&((d.l((ad:0xFFF7FC00+0x70)))&0x1)==0x1) group.long 0xF4++0x3 line.long 0x00 "DMA7CTRL,MibSPI DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT7 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 7" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID7 ,Buffer Utilized for DMA Transfer 7" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP7 ,Receive Data DMA Request Map 7" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP7 ,Transmit Data DMA Channel 7" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA7 ,Receive Data DMA Channel Enable 7" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA7 ,Transmit Data DMA Channel Enable 7" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK7 ,Non-interleaved DMA Block Transfer 7" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT7 ,Initial Count of DMA Transfers 7" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT177 ,The 17th Bit of COUNT Field of DMA7COUNT Register" "Low,High" bitfld.long 0x00 0.--5. " COUNT7 ,Actual Number of Remaining DMA Transfer 7" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l((ad:0xFFF7FC00+0x4)))&0x1)==0x0)&&((d.l((ad:0xFFF7FC00+0x70)))&0x1)==0x1) group.long 0xF4++0x3 line.long 0x00 "DMA7CTRL,MibSPI DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT7 ,Auto-Disable of DMA Channel After ICOUNT+1 Transfers 7" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID7 ,Buffer Utilized for DMA Transfer 7" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP7 ,Receive Data DMA Request Map 7" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP7 ,Transmit Data DMA Channel 7" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA7 ,Receive Data DMA Channel Enable 7" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA7 ,Transmit Data DMA Channel Enable 7" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT7 ,Initial Count of DMA Transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT177 ,The 17th Bit of COUNT Field of DMA7COUNT Register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT7 ,Actual Number of Remaining DMA Transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xF4++0x3 hide.long 0x00 "DMA7CTRL,MibSPI DMA Channel Control Register" endif if (((d.l((ad:0xFFF7FC00+0x70)))&0x01)==0x01) group.long 0xF8++0x3 line.long 0x00 "DMA0COUNT,ICOUNT Register 0" hexmask.long.word 0x00 16.--31. 1. " ICOUNT0 ,Initial Number of DMA Transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT0 ,Actual Number of Remaining DMA Transfer" else hgroup.long 0xF8++0x3 hide.long 0x00 "DMA0COUNT,ICOUNT Register 0" endif if (((d.l((ad:0xFFF7FC00+0x70)))&0x01)==0x01) group.long 0xFC++0x3 line.long 0x00 "DMA1COUNT,ICOUNT Register 1" hexmask.long.word 0x00 16.--31. 1. " ICOUNT1 ,Initial Number of DMA Transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT1 ,Actual Number of Remaining DMA Transfer" else hgroup.long 0xFC++0x3 hide.long 0x00 "DMA1COUNT,ICOUNT Register 1" endif if (((d.l((ad:0xFFF7FC00+0x70)))&0x01)==0x01) group.long 0x100++0x3 line.long 0x00 "DMA2COUNT,ICOUNT Register 2" hexmask.long.word 0x00 16.--31. 1. " ICOUNT2 ,Initial Number of DMA Transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT2 ,Actual Number of Remaining DMA Transfer" else hgroup.long 0x100++0x3 hide.long 0x00 "DMA2COUNT,ICOUNT Register 2" endif if (((d.l((ad:0xFFF7FC00+0x70)))&0x01)==0x01) group.long 0x104++0x3 line.long 0x00 "DMA3COUNT,ICOUNT Register 3" hexmask.long.word 0x00 16.--31. 1. " ICOUNT3 ,Initial Number of DMA Transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT3 ,Actual Number of Remaining DMA Transfer" else hgroup.long 0x104++0x3 hide.long 0x00 "DMA3COUNT,ICOUNT Register 3" endif if (((d.l((ad:0xFFF7FC00+0x70)))&0x01)==0x01) group.long 0x108++0x3 line.long 0x00 "DMA4COUNT,ICOUNT Register 4" hexmask.long.word 0x00 16.--31. 1. " ICOUNT4 ,Initial Number of DMA Transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT4 ,Actual Number of Remaining DMA Transfer" else hgroup.long 0x108++0x3 hide.long 0x00 "DMA4COUNT,ICOUNT Register 4" endif if (((d.l((ad:0xFFF7FC00+0x70)))&0x01)==0x01) group.long 0x10C++0x3 line.long 0x00 "DMA5COUNT,ICOUNT Register 5" hexmask.long.word 0x00 16.--31. 1. " ICOUNT5 ,Initial Number of DMA Transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT5 ,Actual Number of Remaining DMA Transfer" else hgroup.long 0x10C++0x3 hide.long 0x00 "DMA5COUNT,ICOUNT Register 5" endif if (((d.l((ad:0xFFF7FC00+0x70)))&0x01)==0x01) group.long 0x110++0x3 line.long 0x00 "DMA6COUNT,ICOUNT Register 6" hexmask.long.word 0x00 16.--31. 1. " ICOUNT6 ,Initial Number of DMA Transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT6 ,Actual Number of Remaining DMA Transfer" else hgroup.long 0x110++0x3 hide.long 0x00 "DMA6COUNT,ICOUNT Register 6" endif if (((d.l((ad:0xFFF7FC00+0x70)))&0x01)==0x01) group.long 0x114++0x3 line.long 0x00 "DMA7COUNT,ICOUNT Register 7" hexmask.long.word 0x00 16.--31. 1. " ICOUNT7 ,Initial Number of DMA Transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT7 ,Actual Number of Remaining DMA Transfer" else hgroup.long 0x114++0x3 hide.long 0x00 "DMA7COUNT,ICOUNT Register 7" endif if (((d.l((ad:0xFFF7FC00+0x70)))&0x01)==0x01) group.long 0x118++0x3 line.long 0x00 "DMACNTLEN,DMA LARGE COUNT Register" bitfld.long 0x00 0. " LARGE_COUNT ,Large Count" "Modified,Not modified" group.long 0x120++0x3 line.long 0x00 "UERRCTRL,Uncorrectable Parity Error Control Register" bitfld.long 0x00 8. " PTESTEN ,Parity Memory Test Enable" "Disabled,Enabled" bitfld.long 0x00 0.--3. " EDEN ,Error Detection Enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" hgroup.long 0x124++0x3 hide.long 0x00 "UERRSTAT,Uncorrectable Parity Error Status Register" in hgroup.long 0x128++0x3 hide.long 0x00 "UERRADDR1,Uncorrectable Parity Error Address Register" in hgroup.long 0x12c++0x3 hide.long 0x00 "UERRADDR0,Uncorrectable Parity Error Address Register" in hgroup.long 0x130++0x3 hide.long 0x00 "RXOVRN_BUF_ADDR,Receive RAM Overrun Buffer Address Register" in else hgroup.long 0x118++0x3 hide.long 0x00 "DMACNTLEN,DMA LARGE COUNT Register" hgroup.long 0x120++0x3 hide.long 0x00 "UERRCTRL,Uncorrectable Parity Error Control Register" hgroup.long 0x124++0x3 hide.long 0x00 "UERRSTAT,Uncorrectable Parity Error Status Register" hgroup.long 0x128++0x3 hide.long 0x00 "UERRADDR1,Uncorrectable Parity Error Address Register" hgroup.long 0x12c++0x3 hide.long 0x00 "UERRADDR0,Uncorrectable Parity Error Address Register" hgroup.long 0x130++0x3 hide.long 0x00 "RXOVRN_BUF_ADDR,Receive RAM Overrun Buffer Address Register" endif tree.end width 13. if ((((d.l((ad:0xFFF7FC00+0x0134)))&0x0f00)==0x0a00)&&(((d.l((ad:0xFFF7FC00+0x0134)))&0x02)==0x02)) group.long 0x134++0x3 line.long 0x00 "IOLPBKTSTCR,SPI/MibSPI IO Loopback Test Control Register" bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O Loopback Test Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" eventfld.long 0x00 24. " SCS_FAIL_FLG ,Analog Loopback /SPISCS Pin Compare Failure" "Not failed,Failed" textline " " bitfld.long 0x00 20. " CTRL_BITERR ,Inducing of BITERR During IO Loopback Test Mode Control" "Not affected,Flipped" bitfld.long 0x00 19. " CTRL_DESYNC ,Inducing of DESYNC Error During IO Loopback Test Mode Control" "Not affected,Forced to 0" textline " " bitfld.long 0x00 18. " CTRL_PARERR ,Inducing of Parity Error During IO Loopback Test Mode Control" "Not affected,Flipped" bitfld.long 0x00 17. " CTRL_TIMEOUT ,Inducing of TIMEOUT Error During IO Loopback Test Mode Control" "Not affected,Forced to 1" textline " " bitfld.long 0x00 16. " CTRL_DLENERR ,Inducing of Data Length Error During IO Loopback Test Mode Control" "Not affected,Forced to 1" bitfld.long 0x00 3.--5. " ERR_SCS_PIN ,Error on Chip Select Pin Injection" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]" textline " " bitfld.long 0x00 2. " CTRL_SCS_PIN_ERR ,/SPISCS[7:0] Pins Error Injection Enable Control" "Disabled,Enabled" bitfld.long 0x00 1. " LPBK_TYPE ,Module IO Loopback Type" "Digital,Analog" textline " " bitfld.long 0x00 0. " RXP_ENA ,Module Analog Loopback Through Receive Pin Enable" "Transmit,Receive" elif ((((data.long((ad:0xFFF7FC00+0x0134)))&0x0f00)==0x0a00)&&(((data.long((ad:0xFFF7FC00+0x0134)))&0x02)==0x00)) group.long 0x134++0x3 line.long 0x00 "IOLPBKTSTCR,SPI/MibSPI IO Loopback Test Control Register" bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O Loopback Test Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" eventfld.long 0x00 24. " SCS_FAIL_FLG ,Analog Loopback /SPISCS Pin Compare Failure" "Not failed,Failed" textline " " bitfld.long 0x00 20. " CTRL_BITERR ,Inducing of BITERR During IO Loopback Test Mode Control" "Not affected,Flipped" bitfld.long 0x00 19. " CTRL_DESYNC ,Inducing of DESYNC Error During IO Loopback Test Mode Control" "Not affected,Forced to 0" textline " " bitfld.long 0x00 18. " CTRL_PARERR ,Inducing of Parity Error During IO Loopback Test Mode Control" "Not affected,Flipped" bitfld.long 0x00 17. " CTRL_TIMEOUT ,Inducing of TIMEOUT Error During IO Loopback Test Mode Control" "Not affected,Forced to 1" textline " " bitfld.long 0x00 16. " CTRL_DLENERR ,Inducing of Data Length Error During IO Loopback Test Mode Control" "Not affected,Forced to 1" bitfld.long 0x00 3.--5. " ERR_SCS_PIN ,Error on Chip Select Pin Injection" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]" textline " " bitfld.long 0x00 2. " CTRL_SCS_PIN_ERR ,/SPISCS[7:0] Pins Error Injection Enable Control" "Disabled,Enabled" bitfld.long 0x00 1. " LPBK_TYPE ,Module IO Loopback Type" "Digital,Analog" else group.long 0x134++0x3 line.long 0x00 "IOLPBKTSTCR,SPI/MibSPI IO Loopback Test Control Register" bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O Loopback Test Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" endif width 0xb tree.end tree.end tree "SCI (Serial Communication Interface)" tree "LIN1" base ad:0xFFF7E400 width 8. group.long 0x00++0x3 line.long 0x0 "GCR0,Global Control Register" bitfld.long 0x00 0. " RESET ,SCI Module Reset" "Under reset,Out of reset" if ((d.l(ad:0xFFF7E400+0x4)&0x44)==0x44) group.long 0x04++0x3 line.long 0x0 "GCR1,Global Control Register" bitfld.long 0x00 25. " TXENA ,SCI Transmitter Enable" "Disabled,Enabled" bitfld.long 0x00 24. " RXENA ,SCI Receiver Enable" "Prevented,Allowed" textline " " bitfld.long 0x00 17. " CONT ,Continue on Suspend" "Frozen,Continue" bitfld.long 0x00 16. " LOOP_BACK ,LOOP BACK Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " STOP_EXT_FRAME ,Stop Extended Frame Communication" "Not stopped,Stopped" bitfld.long 0x00 12. " HGEN_CTRL ,LIN Mode Bit (Type of Mask Filtering Comparison)" "ID-Byte,ID-Slave task byte" textline " " bitfld.long 0x00 11. " CTYPE ,LIN Mode Bit (Classic/Enhanced)" "Classic,Enhanced" bitfld.long 0x00 10. " MBUF_MODE ,Receive/Transmit Buffer Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " ADAPT ,LIN Mode Bit (Automatic Baudrate Adjustment)" "Disabled,Enabled" bitfld.long 0x00 8. " SLEEP ,SCI Sleep Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " SW_nRESET ,Software Reset" "Reset,Ready" bitfld.long 0x00 6. " LIN_MODE ,LIN MODE Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " CLOCK ,SCI Internal Clock Enable" "Slave,Master" sif (cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")) bitfld.long 0x00 4. " STOP ,SCI Number of Stop Bits" "1 bit,2 bits" textline " " bitfld.long 0x00 3. " PARITY ,SCI Parity Odd/Even Selection" "Odd,Even" endif bitfld.long 0x00 2. " PARITY_ENA ,ID-Parity Enable" "Disabled,Enabled" textline " " sif (cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")) bitfld.long 0x00 1. " TIMING_MODE ,SCI Timing Mode Bit" "Synchronous,Asynchronous" endif bitfld.long 0x00 0. " COMM_MODE ,SCI/BLIN Communication Mode Bit ID4 and ID5 Use" "Not used,Used" elif ((d.l(ad:0xFFF7E400+0x4)&0x44)==0x40) group.long 0x04++0x3 line.long 0x0 "GCR1,Global Control Register" bitfld.long 0x00 25. " TXENA ,SCI Transmitter Enable" "Disabled,Enabled" bitfld.long 0x00 24. " RXENA ,SCI Receiver Enable" "Prevented,Allowed" textline " " bitfld.long 0x00 17. " CONT ,Continue on Suspend" "Frozen,Continue" bitfld.long 0x00 16. " LOOP_BACK ,LOOP BACK Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " STOP_EXT_FRAME ,Stop Extended Frame Communication" "Not stopped,Stopped" bitfld.long 0x00 12. " HGEN_CTRL ,LIN Mode Bit (Type of Mask Filtering Comparison)" "ID-Byte,ID-SlaveTask" textline " " bitfld.long 0x00 11. " CTYPE ,LIN Mode Bit (Classic/Enhanced)" "Classic,Enhanced" bitfld.long 0x00 10. " MBUF_MODE ,Receive/Transmit Buffer Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " ADAPT ,LIN Mode Bit (Automatic Baudrate Adjustment)" "Disabled,Enabled" bitfld.long 0x00 8. " SLEEP ,SCI Sleep Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " SW_nRESET ,Software Reset" "Reset,Ready" bitfld.long 0x00 6. " LIN_MODE ,LIN MODE Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " CLOCK ,SCI Internal Clock Enable" "Slave,Master" sif (cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")) bitfld.long 0x00 4. " STOP ,SCI Number of Stop Bits" "1 bit,2 bits" endif textline " " bitfld.long 0x00 2. " PARITY_ENA ,ID-Parity Enable" "Disabled,Enabled" textline " " sif (cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")) bitfld.long 0x00 1. " TIMING_MODE ,SCI Timing Mode Bit" "Synchronous,Asynchronous" endif bitfld.long 0x00 0. " COMM_MODE ,SCI/BLIN Communication Mode Bit ID4 and ID5 Use" "Not used,Used" elif (((d.l((ad:0xFFF7E400+0x4)))&0x44)==0x04) group.long 0x04++0x3 line.long 0x0 "GCR1,Global Control Register" bitfld.long 0x00 25. " TXENA ,SCI Transmitter Enable" "Disabled,Enabled" bitfld.long 0x00 24. " RXENA ,SCI Receiver Enable" "Prevented,Allowed" textline " " bitfld.long 0x00 17. " CONT ,Continue on Suspend" "Frozen,Continue" bitfld.long 0x00 16. " LOOP_BACK ,LOOP BACK Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " MBUF_MODE ,Receive/Transmit Buffer Enable" "Disabled,Enabled" bitfld.long 0x00 8. " SLEEP ,SCI Sleep Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " SW_nRESET ,Software Reset" "Reset,Ready" bitfld.long 0x00 6. " LIN_MODE ,LIN MODE Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " CLOCK ,SCI Internal Clock Enable" "External,Internal" bitfld.long 0x00 4. " STOP ,SCI Number of Stop Bits" "1 bit,2 bits" textline " " bitfld.long 0x00 3. " PARITY ,SCI Parity Odd/Even Selection" "Odd,Even" bitfld.long 0x00 2. " PARITY_ENA ,Parity Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " TIMING_MODE ,SCI Timing Mode Bit" "Synchronous,Asynchronous" bitfld.long 0x00 0. " COMM_MODE ,SCI/BLIN Communication Mode Bit" "Idle-line,Address-bit" else group.long 0x04++0x3 line.long 0x0 "GCR1,Global Control Register" bitfld.long 0x00 25. " TXENA ,SCI Transmitter Enable" "Disabled,Enabled" bitfld.long 0x00 24. " RXENA ,SCI Receiver Enable" "Prevented,Allowed" textline " " bitfld.long 0x00 17. " CONT ,Continue on Suspend" "Frozen,Continue" bitfld.long 0x00 16. " LOOP_BACK ,LOOP BACK Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " MBUF_MODE ,Receive/Transmit Buffer Enable" "Disabled,Enabled" bitfld.long 0x00 8. " SLEEP ,SCI Sleep Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " SW_nRESET ,Software Reset" "Reset,Ready" bitfld.long 0x00 6. " LIN_MODE ,LIN MODE Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " CLOCK ,SCI Internal Clock Enable" "External,Internal" bitfld.long 0x00 4. " STOP ,SCI Number of Stop Bits" "1 bit,2 bits" textline " " bitfld.long 0x00 2. " PARITY_ENA ,Parity Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " TIMING_MODE ,SCI Timing Mode Bit" "Synchronous,Asynchronous" bitfld.long 0x00 0. " COMM_MODE ,SCI/BLIN Communication Mode Bit" "Idle-line,Address-bit" endif width 8. if ((d.l(ad:0xFFF7E400+0x4)&0x40)==0x40) group.long 0x08++0x3 line.long 0x0 "GCR2,Global Control Register" bitfld.long 0x00 17. " CC ,Compare Checksum" "No effect,Compared" bitfld.long 0x00 16. " SC ,Send Checksum" "No effect,Compared" textline " " bitfld.long 0x00 8. " GEN_WU ,Generate Wakeup Signal" "No effect,Generated" bitfld.long 0x00 0. " POWERDOWN ,POWERDOWN" "Normal,Local low-power" else group.long 0x08++0x3 line.long 0x0 "GCR2,Global Control Register" sif (cpu()!="TMS570PSFC61")&&(cpu()!="TMS470MF031")&&(cpu()!="TMS470MF042")&&(cpu()!="TMS470MF066")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*") bitfld.long 0x00 8. " GEN_WU ,Generate Wakeup Signal" "No effect,Generated" textline " " endif bitfld.long 0x00 0. " POWERDOWN ,POWERDOWN" "Normal,Local low-power" endif width 11. tree "SCI Interrupt Registers" if ((d.l(ad:0xFFF7E400+0x4)&0x40)==0x40) group.long 0x0C++0x3 line.long 0x0 "SETINT,Interrupt Register" setclrfld.long 0x00 31. 0x00 31. 0x04 31. " BE_INT_set/clr ,Bit Error Interrupt" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x04 30. " PBE_INT_set/clr ,Physical Bus Error Interrupt" "Disabled,Enabled" textline " " setclrfld.long 0x00 29. 0x00 29. 0x04 29. " CE_INT_set/clr ,Checksum-Error Interrupt" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x04 28. " ISFE_INT_set/clr ,Inconsistent-Synch-Field-Error Interrupt" "Disabled,Enabled" textline " " setclrfld.long 0x00 27. 0x00 27. 0x04 27. " NRE_INT_set/clr ,No-Reponse-Error Interrupt" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x04 26. " FE_INT_set/clr ,Framing-Error Interrupt" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x04 25. " OE_INT_set/clr ,Overrun-Error Interrupt" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PE_INT_set/clr ,Parity Interrupt" "Disabled,Enabled" textline " " sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")) setclrfld.long 0x00 17. 0x00 17. 0x04 17. " RX_DMA_set/clr ,Receive DMA" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x04 16. " TX_DMA_set/clr ,Transmit DMA" "Disabled,Enabled" textline " " endif setclrfld.long 0x00 13. 0x00 13. 0x04 13. " ID_INT_set/clr ,ID Interrupt" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x04 9. " RX_INT_set/clr ,Receiver Interrupt Enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 8. 0x00 8. 0x04 8. " TX_INT_set/clr ,Transmitter Interrupt" "Disabled,Enabled" setclrfld.long 0x00 7. 0x00 7. 0x04 7. " TOA3WUS_INT_set/clr ,Timeout After 3 Wakeup Signals Interrupt" "Disabled,Enabled" textline " " setclrfld.long 0x00 6. 0x00 6. 0x04 6. " TOAWUS_INT_set/clr ,Timeout After Wakeup Signal Interrupt" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x04 4. " TIMEOUT_INT_set/clr ,Timeout Interrupt" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x04 1. " WAKEUP_INT_set/clr ,Wake-up Interrupt" "Disabled,Enabled" else group.long 0x0C++0x3 line.long 0x0 "SETINT,Interrupt Register" setclrfld.long 0x00 26. 0x00 26. 0x04 26. " FE_INT_set/clr ,Framing-Error Interrupt" "Disabled,Enabled" setclrfld.long 0x00 25. 0x00 25. 0x04 25. " OE_INT_set/clr ,Overrun-Error Interrupt" "Disabled,Enabled" textline " " setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PE_INT_set/clr ,Parity Interrupt" "Disabled,Enabled" sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")) setclrfld.long 0x00 18. 0x00 18. 0x04 18. " RX_DMA_ALL_set/clr ,Receive DMA All" "Disabled,Enabled" textline " " setclrfld.long 0x00 17. 0x00 17. 0x04 17. " RX_DMA_set/clr ,Receive DMA" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x04 16. " TX_DMA_set/clr ,Transmit DMA" "Disabled,Enabled" endif textline " " setclrfld.long 0x00 9. 0x00 9. 0x04 9. " RX_INT_set/clr ,Receiver Interrupt Enable" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x04 8. " TX_INT_set/clr ,Transmitter Interrupt" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x04 1. " WAKEUP_INT_set/clr ,Wake-up Interrupt" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x04 0. " BRKDT_INT_set/clr ,Break-detect Interrupt" "Disabled,Enabled" endif width 11. if ((d.l(ad:0xFFF7E400+0x4)&0x40)==0x40) group.long 0x14++0x3 line.long 0x0 "SETINTLVL,Interrupt Level Register" setclrfld.long 0x00 31. 0x00 31. 0x04 31. " BE_INT_LVL_set/clr ,Bit Error Interrupt Level" "INT0,INT1" setclrfld.long 0x00 30. 0x00 30. 0x04 30. " PBE_INT_LVL_set/clr ,Physical Bus Error Interrupt Level" "INT0,INT1" textline " " setclrfld.long 0x00 29. 0x00 29. 0x04 29. " CE_INT_LVL_set/clr ,Checksum-Error Interrupt Level" "INT0,INT1" setclrfld.long 0x00 28. 0x00 28. 0x04 28. " ISFE_INT_LVL_set/clr ,Inconsistent-Synch-Field-Error Interrupt Level" "INT0,INT1" textline " " setclrfld.long 0x00 27. 0x00 27. 0x04 27. " NRE_INT_LVL_set/clr ,No-Reponse-Error Interrupt Level" "INT0,INT1" setclrfld.long 0x00 26. 0x00 26. 0x04 26. " FE_INT_LVL_set/clr ,Framing-Error Interrupt Level" "INT0,INT1" textline " " setclrfld.long 0x00 25. 0x00 25. 0x04 25. " OE_INT_LVL_set/clr ,Overrun-Error Interrupt Level" "INT0,INT1" setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PE_INT_LVL_set/clr ,Parity Error Interrupt Level" "INT0,INT1" textline " " setclrfld.long 0x00 13. 0x00 13. 0x04 13. " ID_INT_LVL_set/clr ,ID Interrupt Level" "INT0,INT1" setclrfld.long 0x00 9. 0x00 9. 0x04 9. " RX_INT_LVL_set/clr ,Receiver Interrupt Level" "INT0,INT1" textline " " setclrfld.long 0x00 8. 0x00 8. 0x04 8. " TX_INT_LVL_set/clr ,Transmitter Interrupt Level" "INT0,INT1" setclrfld.long 0x00 7. 0x00 7. 0x04 7. " TOA3WUS_INT_LVL_set/clr ,Timeout After 3 Wakeup Signals Interrupt" "INT0,INT1" textline " " setclrfld.long 0x00 6. 0x00 6. 0x04 6. " TOAWUS_INT_LVL_set/clr ,Timeout After Wakeup Signal Interrupt Level" "INT0,INT1" setclrfld.long 0x00 4. 0x00 4. 0x04 4. " TIMEOUT_INT_LVL_set/clr ,Timeout Interrupt Level" "INT0,INT1" textline " " setclrfld.long 0x00 1. 0x00 1. 0x04 1. " WAKEUP_INT_LVL_set/clr ,Wake-up Interrupt Level" "INT0,INT1" else group.long 0x14++0x3 line.long 0x0 "SETINTLVL,Interrupt Level Register" setclrfld.long 0x00 26. 0x00 26. 0x04 26. " FE_INT_LVL_set/clr ,Framing-Error Interrupt Level" "INT0,INT1" setclrfld.long 0x00 25. 0x00 25. 0x04 25. " OE_INT_LVL_set/clr ,Overrun-Error Interrupt Level" "INT0,INT1" textline " " setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PE_INT_LVL_set/clr ,Parity Error Interrupt Level" "INT0,INT1" sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")) setclrfld.long 0x00 18. 0x00 18. 0x04 18. " RX_DMA_ALL_INT_LVL_set/clr ,Receive DMA All Interrupt Level" "INT0,INT1" endif textline " " setclrfld.long 0x00 9. 0x00 9. 0x04 9. " RX_INT_LVL_set/clr ,Receiver Interrupt Level" "INT0,INT1" setclrfld.long 0x00 8. 0x00 8. 0x04 8. " TX_INT_LVL_set/clr ,Transmitter Interrupt Level" "INT0,INT1" textline " " setclrfld.long 0x00 1. 0x00 1. 0x04 1. " WAKEUP_INT_LVL_set/clr ,Wake-up Interrupt Level" "INT0,INT1" setclrfld.long 0x00 0. 0x00 0. 0x04 0. " BRKDT_INT_set/clr ,Break-Detect Interrupt Level" "INT0,INT1" endif tree.end width 8. if ((d.l(ad:0xFFF7E400+0x4)&0x40)==0x40) group.long 0x1C++0x3 line.long 0x0 "FLR,Flags Register" eventfld.long 0x00 31. " BE ,Bit Error Flag" "Not detected,Detected" eventfld.long 0x00 30. " PBE ,Physiscal Bus Error Flag" "Not detected,Detected" textline " " eventfld.long 0x00 29. " CE ,Checksum Error Flag" "Not detected,Detected" eventfld.long 0x00 28. " ISFE ,Inconsistent Synch Field Error Flag" "Not detected,Detected" textline " " eventfld.long 0x00 27. " NRE ,No-Response Error Flag" "Not detected,Detected" eventfld.long 0x00 26. " FE ,Framing Error Flag" "Not detected,Detected" textline " " eventfld.long 0x00 25. " OE ,Overrun Error Flag" "Not detected,Detected" eventfld.long 0x00 24. " PE ,Parity Error Flag" "Not detected,Detected" textline " " eventfld.long 0x00 14. " ID_RX_FLAG ,Identifier On Receive Flag" "Not received,Received" eventfld.long 0x00 13. " ID_TX_FLAG ,Identifier On Transmit Flag" "Not received,Received" textline " " bitfld.long 0x00 11. " TX_EMPTY ,Transmitter Empty Flag" "Not empty,Empty" eventfld.long 0x00 9. " RXRDY ,Receiver Ready Flag" "Not ready,Ready" textline " " bitfld.long 0x00 8. " TXRDY ,Transmitter Buffer Register Ready Flag" "Full,Ready" eventfld.long 0x00 7. " TOA3WUS ,Timeout After 3 Wakeup Signals Flag" "No timeout,Timeout" textline " " eventfld.long 0x00 6. " TOAWUS ,Timeout After Wakeup Signal Flag" "No timeout,Timeout" eventfld.long 0x00 4. " TIMEOUT ,LIN Bus IDLE Timeout Flag" "Not detected,Detected" textline " " bitfld.long 0x00 3. " BUSY_FLAG ,BUSY Flag" "Not busy,Busy" eventfld.long 0x00 1. " WAKEUP ,Wake-up Flag" "No wake up,Wake up" else group.long 0x1C++0x3 line.long 0x0 "FLR,Flags Register" sif (cpu()!="TMS570PSFC61")&&(cpu()!="TMS470MF031")&&(cpu()!="TMS470MF042")&&(cpu()!="TMS470MF066")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*") eventfld.long 0x00 31. " BE ,Bit Error Flag" "Not detected,Detected" textline " " endif eventfld.long 0x00 26. " FE ,Framing Error Flag" "Not detected,Detected" textline " " eventfld.long 0x00 25. " OE ,Overrun Error Flag" "Not detected,Detected" eventfld.long 0x00 24. " PE ,Parity Error Flag" "Not detected,Detected" textline " " bitfld.long 0x00 12. " RXWAKE ,Receiver Wakeup Detect Flag" "Not address,Address" bitfld.long 0x00 11. " TX_EMPTY ,Transmitter Empty Flag" "Not empty,Empty" textline " " bitfld.long 0x00 10. " TXWAKE ,SCI Transmitter Wakeup Method Select" "Data,Address" eventfld.long 0x00 9. " RXRDY ,Receiver Ready Flag" "Not ready,Ready" textline " " bitfld.long 0x00 8. " TXRDY ,Transmitter Buffer Register Ready Flag (SCITD)" "Full,Ready" bitfld.long 0x00 3. " BUSY_FLAG ,BUSY Flag" "Not busy,Busy" textline " " bitfld.long 0x00 2. " IDLE ,SCI Receiver in Idle State" "Not detected,Detected" sif (cpu()!="TMS570PSFC61")&&(cpu()!="TMS470MF031")&&(cpu()!="TMS470MF042")&&(cpu()!="TMS470MF066")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!=("TMS570LS0332")&&!cpuis("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*") eventfld.long 0x00 1. " WAKEUP ,Wake-up Flag" "No wake up,Wake up" endif textline " " eventfld.long 0x00 0. " BRKDT ,SCI Break-Detect Flag" "Not detected,Detected" endif width 9. tree "SCI Interrupt Vector Offset Registers" hgroup.long 0x20++0x3 hide.long 0x0 "INVECT0,Interrupt Vector Offset 0" in hgroup.long 0x24++0x3 hide.long 0x0 "INVECT1,Interrupt Vector Offset 1" in tree.end width 8. if ((d.l(ad:0xFFF7E400+0x4)&0x40)==0x40) group.long 0x28++0x3 line.long 0x0 "FORMAT,Format Control Register" bitfld.long 0x00 16.--18. " LENGTH ,Frame Length Control Bits" "1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes" elif (((d.l(ad:0xFFF7E400+0x4)&0x40)==0x0)&&(((d.l((ad:0xFFF7E400+0x04)))&0x0400)==0x0400)) group.long 0x28++0x3 line.long 0x0 "FORMAT,Format Control Register" bitfld.long 0x00 16.--18. " LENGTH ,Frame Length Control Bits" "1 character,2 characters,3 characters,4 characters,5 characters,6 characters,7 characters,8 characters" bitfld.long 0x00 0.--2. " CHAR ,Character Length Control Bits" "1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits" else group.long 0x28++0x3 line.long 0x0 "FORMAT,Format Control Register" bitfld.long 0x00 0.--2. " CHAR ,Character Length Control Bits" "1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits" endif group.long 0x2C++0x3 line.long 0x0 "BRSR,Baud Rate Selection Register" hexmask.long.byte 0x00 28.--30. 1. " U ,SCI/BLIN Super Fractional Divider Selection" hexmask.long.byte 0x00 24.--27. 1. " M ,SCI/BLIN 4-bit Fractional Divider Selection" hexmask.long.tbyte 0x00 0.--23. 1. " PRESCALER_P ,SCI/BLIN 24-bit Integer Prescaler Selection" width 4. tree "SCI Data Buffer Registers" rgroup.long 0x30++0x3 line.long 0x0 "ED,SCI Data Buffer" hexmask.long.byte 0x00 0.--7. 1. " ED ,Emulation Data" hgroup.long 0x34++0x3 hide.long 0x0 "RD,SCI Data Buffer" in group.long 0x38++0x3 line.long 0x0 "TD,SCI Data Buffer" hexmask.long.byte 0x00 0.--7. 1. " TD ,Transmit Data" tree.end tree "SCI Pin I/O Control Registers" width 6. if ((d.l(ad:0xFFF7E400+0x4)&0x40)==0x40) group.long 0x3C++0x3 line.long 0x0 "PIO0,Pin I/O Control Register 0" bitfld.long 0x00 2. " TX_FUNC ,Defines the Function of Pin SCITX" "GPIO,SCITX" bitfld.long 0x00 1. " RX_FUNC ,Defines the Function of Pin SCIRX" "GPIO,SCIRX" sif (cpu()!="TMS570PSFC61"&&cpu()!="TMS570LC4357"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*")) textline " " bitfld.long 0x00 0. " CLK_FUNC ,Clock Function" "GPIO,?..." endif else group.long 0x3C++0x3 line.long 0x0 "PIO0,Pin I/O Control Register 0" bitfld.long 0x00 2. " TX_FUNC ,Defines the Function of Pin SCITX" "GPIO,SCITX" bitfld.long 0x00 1. " RX_FUNC ,Defines the Function of Pin SCIRX" "GPIO,SCIRX" sif (cpu()!="TMS570PSFC61"&&cpu()!="TMS570LC4357"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*")) textline " " bitfld.long 0x00 0. " CLK_FUNC ,Clock Function" "GPIO,SCICLK" endif endif sif (cpu()!="TMS570PSFC61"&&cpu()!="TMS570LC4357") if ((d.l(ad:0xFFF7E400+0x3c)&0x1)==0x0) group.long 0x40++0x3 line.long 0x0 "PIO1,Pin I/O Control Register 1" bitfld.long 0x00 2. " TX_DIR ,Transmit Direction" "Input,Output" bitfld.long 0x00 1. " RX_DIR ,Receive Direction" "Input,Output" sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*")) textline " " bitfld.long 0x00 0. " CLK_DIR ,Clock Data Direction" "Input,Output" endif elif (((d.l(ad:0xFFF7E400+0x3c)&0x1)==0x1)&&((d.l(ad:0xFFF7E400+0x4)&0x60)==0x20)) group.long 0x40++0x3 line.long 0x0 "PIO1,Pin I/O Control Register 1" bitfld.long 0x00 2. " TX_DIR ,Transmit Direction" "Input,Output" bitfld.long 0x00 1. " RX_DIR ,Receive Direction" "Input,Output" sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*")) textline " " bitfld.long 0x00 0. " CLK_DIR ,Clock Data Direction" "Not output,Output" endif elif (((d.l(ad:0xFFF7E400+0x3c)&0x1)==0x1)&&((d.l(ad:0xFFF7E400+0x4)&0x60)==0x0)) group.long 0x40++0x3 line.long 0x0 "PIO1,Pin I/O Control Register 1" bitfld.long 0x00 2. " TX_DIR ,Transmit Direction" "Input,Output" bitfld.long 0x00 1. " RX_DIR ,Receive Direction" "Input,Output" sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*")) textline " " bitfld.long 0x00 0. " CLK_DIR ,Clock Data Direction" "Input,Not input" endif else group.long 0x40++0x3 line.long 0x0 "PIO1,Pin I/O Control Register 1" bitfld.long 0x00 2. " TX_DIR ,Transmit Direction" "Input,Output" bitfld.long 0x00 1. " RX_DIR ,Receive Direction" "Input,Output" sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*")) textline " " bitfld.long 0x00 0. " CLK_DIR ,Clock Data Direction" "Input,Output" endif endif else group.long 0x40++0x3 line.long 0x0 "PIO1,Pin I/O Control Register 1" bitfld.long 0x00 2. " TX_DIR ,Transmit Direction" "Input,Output" bitfld.long 0x00 1. " RX_DIR ,Receive Direction" "Input,Output" endif rgroup.long 0x44++0x3 line.long 0x0 "PIO2,Pin I/O Control Register 2" bitfld.long 0x00 2. " TX_IN ,Contains Current Value on the SCITX Pin" "Low,High" bitfld.long 0x00 1. " RX_IN ,Contains Current Value on the SCIRX Pin" "Low,High" sif (cpu()!="TMS570PSFC61"&&cpu()!="TMS570LC4357"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")) textline " " bitfld.long 0x00 0. " CLK_IN ,Contains the Current Value on Pin SCICLK" "Low,High" endif width 6. group.long 0x48++0x3 line.long 0x0 "PIO3,Pin I/O Control Register 3" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " TX_OUT_set/clr ,SCITX Pin Data Output" "Low,High" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " RX_OUT_set/clr ,SCIRX Pin Data Output" "Low,High" sif (cpu()!="TMS570PSFC61"&&cpu()!="TMS570LC4357"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*")) textline " " setclrfld.long 0x00 0. 0x00 0. 0x08 0. " CLK_OUT_set/clr ,SCICLK Pin Data Output" "Low,High" endif sif cpuis("TMS570LS21*")||cpuis("TMS570LS31*") group.long 0x4C++0x3 line.long 0x0 "PIO4,Pin I/O Control Register 4" bitfld.long 0x00 2. " TX_DIR ,Transmit Direction" "Input,Output" bitfld.long 0x00 1. " RX_DIR ,Receive Direction" "Input,Output" group.long 0x50++0x3 line.long 0x0 "PIO5,Pin I/O Control Register 5" bitfld.long 0x00 2. " TX_DIR ,Transmit Direction" "Input,Output" bitfld.long 0x00 1. " RX_DIR ,Receive Direction" "Input,Output" endif width 6. group.long 0x54++0x3 line.long 0x0 "PIO6,Pin I/O Control Register 6" bitfld.long 0x00 2. " TX_ODR ,TX Open Drain Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RX_ODR ,RX Open Drain Enable" "Disabled,Enabled" sif (cpu()!="TMS570PSFC61"&&cpu()!="TMS570LC4357"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*")) textline " " bitfld.long 0x00 0. " CLK_ODR ,CLK Open Drain Enable" "Disabled,Enabled" endif group.long 0x58++0x3 line.long 0x0 "PIO7,Pin I/O Control Register 7" bitfld.long 0x00 2. " TX_PD ,TX Pin Pull Control Disable" "No,Yes" bitfld.long 0x00 1. " RX_PD ,RX Pin Pull Control Disable" "No,Yes" sif (cpu()!="TMS570PSFC61"&&cpu()!="TMS570LC4357"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&cpu()!=("TMS570LS1114*")&&cpu()!=("TMS570LS1115*")&&cpu()!=("TMS570LS1224*")&&cpu()!=("TMS570LS1225*")&&cpu()!=("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*")) textline " " bitfld.long 0x00 0. " CLK_PD ,CLK Pin Pull Control Disable" "No,Yes" endif group.long 0x5C++0x3 line.long 0x0 "PIO8,Pin I/O Control Register 8" bitfld.long 0x00 2. " TX_PSL ,TX Pin Pull Select" "Pull down,Pull up" bitfld.long 0x00 1. " RX_PSL ,RX Pin Pull Select" "Pull down,Pull up" sif (cpu()!="TMS570PSFC61"&&cpu()!="TMS570LC4357"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*")) textline " " bitfld.long 0x00 0. " CLK_PSL ,CLK Pin Pull Select" "Pull down,Pull up" endif tree.end tree "BLIN Registers" width 9. if ((d.l(ad:0xFFF7E400+0x4)&0x40)==0x40) group.long 0x60++0x3 line.long 0x0 "LINCOMP,BLINCOMPARE Register" bitfld.long 0x00 8.--9. " SDEL ,2-bit Synch Delimiter Compare" "1 bit,2 bits,3 bits,4 bits" bitfld.long 0x00 0.--2. " SBREAK ,3-bit Synch Break Extend" "Not extended,1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits" else hgroup.long 0x60++0x3 hide.long 0x0 "LINCOMP,BLINCOMPARE Register" endif sif (cpu()!="TMS570LC4357"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")) hgroup.long 0x64++0x3 hide.long 0x0 "LINRD0,LINRD0 Register" in hgroup.long 0x68++0x3 hide.long 0x0 "LINRD1,LINRD1 Register" in else rgroup.long 0x64++0x3 line.long 0x0 "LINRD0,LINRD0 Register" hexmask.long.byte 0x00 24.--31. 0x1 " RD0 ,Receive Buffer 0" hexmask.long.byte 0x00 16.--23. 0x1 " RD1 ,Receive Buffer 1" hexmask.long.byte 0x00 8.--15. 0x1 " RD2 ,Receive Buffer 2" hexmask.long.byte 0x00 0.--7. 0x1 " RD3 ,Receive Buffer 3" rgroup.long 0x68++0x3 line.long 0x0 "LINRD1,LINRD1 Register" hexmask.long.byte 0x00 24.--31. 0x1 " RD4 ,Receive Buffer 4" hexmask.long.byte 0x00 16.--23. 0x1 " RD5 , Receive Buffer 5" hexmask.long.byte 0x00 8.--15. 0x1 " RD6 ,Receive Buffer 6" hexmask.long.byte 0x00 0.--7. 0x1 " RD7 ,Receive Buffer 7" endif width 9. if ((d.l(ad:0xFFF7E400+0x4)&0x40)==0x40) group.long 0x6C++0x3 line.long 0x0 "LINMASK,LINMASK Register" bitfld.long 0x00 23. " RX_ID_MASK7 ,RX ID Mask 7" "Not masked,Masked" bitfld.long 0x00 22. " RX_ID_MASK6 ,RX ID Mask 6" "Not masked,Masked" textline " " bitfld.long 0x00 21. " RX_ID_MASK5 ,RX ID Mask 5" "Not masked,Masked" bitfld.long 0x00 20. " RX_ID_MASK4 ,RX ID Mask 4" "Not masked,Masked" textline " " bitfld.long 0x00 19. " RX_ID_MASK3 ,RX ID Mask 3" "Not masked,Masked" bitfld.long 0x00 18. " RX_ID_MASK2 ,RX ID Mask 2" "Not masked,Masked" textline " " bitfld.long 0x00 17. " RX_ID_MASK1 ,RX ID Mask 1" "Not masked,Masked" bitfld.long 0x00 16. " RX_ID_MASK0 ,RX ID Mask 0" "Not masked,Masked" textline " " bitfld.long 0x00 7. " TX_ID_MASK7 ,TX ID Mask 7" "Not masked,Masked" bitfld.long 0x00 6. " TX_ID_MASK6 ,TX ID Mask 6" "Not masked,Masked" textline " " bitfld.long 0x00 5. " TX_ID_MASK5 ,TX ID Mask 5" "Not masked,Masked" bitfld.long 0x00 4. " TX_ID_MASK4 ,TX ID Mask 4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " TX_ID_MASK3 ,TX ID Mask 3" "Not masked,Masked" bitfld.long 0x00 2. " TX_ID_MASK2 ,TX ID Mask 2" "Not masked,Masked" textline " " bitfld.long 0x00 1. " TX_ID_MASK1 ,TX ID Mask 1" "Not masked,Masked" bitfld.long 0x00 0. " TX_ID_MASK0 ,TX ID Mask 0" "Not masked,Masked" else hgroup.long 0x6C++0x3 hide.long 0x0 "LINMASK,LINMASK Register" endif width 9. if ((d.l(ad:0xFFF7E400+0x4)&0x40)==0x40) group.long 0x70++0x3 line.long 0x0 "LINID,LINID Register" hexmask.long.byte 0x00 16.--23. 1. " RECEIVED_ID ,Received Identifier" hexmask.long.byte 0x00 8.--15. 1. " ID_SLAVETASK_BYTE ,Identifier Slave Task Byte" hexmask.long.byte 0x00 0.--7. 1. " ID_BYTE ,Identifier Byte" else hgroup.long 0x70++0x3 hide.long 0x0 "LINID,LINID Register" endif width 9. group.long 0x74++0x3 line.long 0x0 "LINTD0,LINTD0 Register" hexmask.long.byte 0x00 24.--31. 1. " TD0 ,8-bit Transmit Buffer 0" hexmask.long.byte 0x00 16.--23. 1. " TD1 ,8-bit Transmit Buffer 1" hexmask.long.byte 0x00 8.--15. 1. " TD2 ,8-bit Transmit Buffer 2" hexmask.long.byte 0x00 0.--7. 1. " TD3 ,8-bit Transmit Buffer 3" group.long 0x78++0x3 line.long 0x0 "LINTD1,LINTD1 Register" hexmask.long.byte 0x00 24.--31. 1. " TD4 ,8-bit Transmit Buffer 4" hexmask.long.byte 0x00 16.--23. 1. " TD5 ,8-bit Transmit Buffer 5" hexmask.long.byte 0x00 8.--15. 1. " TD6 ,8-bit Transmit Buffer 6" hexmask.long.byte 0x00 0.--7. 1. " TD7 ,8-bit Transmit Buffer 7" tree.end width 11. if ((d.l(ad:0xFFF7E400+0x4)&0x40)==0x40) group.long 0x7C++0x3 line.long 0x0 "MBRSR,Maximum Baud Rate Selection Register" hexmask.long.word 0x00 0.--12. 1. " MBR ,Maximum Baud Rate Prescaler" else hgroup.long 0x7C++0x3 hide.long 0x0 "MBRSR,Maximum Baud Rate Selection Register" endif sif (cpu()!="TMS470MF031")&&(cpu()!="TMS470MF042")&&(cpu()!="TMS470MF066")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&(cpu()!="TMS570LC4357")&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*") group.long 0x80++0x3 line.long 0x0 "PIO9,Pin I/O Control Register 9" bitfld.long 0x00 2. " TX_SL ,This Bit Controls the Slew Rate for the SCITX Pin" "Normal,Slew" bitfld.long 0x00 1. " RX_SL ,This Bit Controls the Slew Rate for the SCIRX Pin" "Normal,Slew" sif (cpu()!="TMS570PSFC61") bitfld.long 0x00 0. " CLK_SL ,This Bit Controls the Slew Rate for the SCICLK Pin" "Normal,Slew" endif endif width 11. if ((d.l(ad:0xFFF7E400+0x4)&0x40)==0x40) group.long 0x90++0x3 line.long 0x0 "IODFTCTRL,IODFT for BLIN Moduler" bitfld.long 0x00 31. " BEEN ,Bit Error Enable" "Disabled,Enabled" bitfld.long 0x00 30. " PBEEN ,Physical Bus Error Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " CEEN ,Checksum Error Enable" "Disabled,Enabled" bitfld.long 0x00 28. " ISFEEN ,Inconsistent Synch Field Error Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " FEEN ,Frame Error Enable" "Disabled,Enabled" bitfld.long 0x00 19.--20. " PSM ,PIN SAMPLE MASK" "No mask,TBIT_CENTER,TBIT_CENTER + SCLK,TBIT_CENTER + 2 SCLK" textline " " bitfld.long 0x00 16.--18. " TX_SHIFT ,Transmit Shift" "No delay,1 SCLK,2 SCLKs,3 SCLKs,4 SCLKs,5 SCLKs,6 SCLKs,7 SCLKs" bitfld.long 0x00 8.--11. " IODFTENA ,IO DFT Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" textline " " bitfld.long 0x00 1. " LPBENA ,Module Loopback Enable" "Analog,Digital" bitfld.long 0x00 0. " RXPENA ,Module Analog Loopback Through Receive/Transmit Pin Enable" "Transmit,Receive" else group.long 0x90++0x3 line.long 0x0 "IODFTCTRL,IODFT for BLIN Moduler" bitfld.long 0x00 26. " FEEN ,Frame Error Enable" "Disabled,Enabled" bitfld.long 0x00 25. " PEEN ,Parity Error Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " BDEEN ,Break Detect Error Enable" "Disabled,Enabled" bitfld.long 0x00 19.--20. " PSM ,PIN SAMPLE MASK" "No mask,TBIT_CENTER,TBIT_CENTER + SCLK,TBIT_CENTER + 2 SCLK" textline " " bitfld.long 0x00 16.--18. " TX_SHIFT ,Transmit Shift" "No delay,1 SCLK,2 SCLKs,3 SCLKs,4 SCLKs,5 SCLKs,6 SCLKs,7 SCLKs" bitfld.long 0x00 8.--11. " IODFTENA ,IO DFT Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" textline " " bitfld.long 0x00 1. " LPBENA ,Module Loopback Enable" "Analog,Digital" bitfld.long 0x00 0. " RXPENA ,Module Analog Loopback Through Receive/Transmit Pin Enable" "Transmit,Receive" endif width 0xb tree.end tree "LIN2" base ad:0xFFF7E500 width 8. group.long 0x00++0x3 line.long 0x0 "GCR0,Global Control Register" bitfld.long 0x00 0. " RESET ,SCI Module Reset" "Under reset,Out of reset" if ((d.l(ad:0xFFF7E500+0x4)&0x44)==0x44) group.long 0x04++0x3 line.long 0x0 "GCR1,Global Control Register" bitfld.long 0x00 25. " TXENA ,SCI Transmitter Enable" "Disabled,Enabled" bitfld.long 0x00 24. " RXENA ,SCI Receiver Enable" "Prevented,Allowed" textline " " bitfld.long 0x00 17. " CONT ,Continue on Suspend" "Frozen,Continue" bitfld.long 0x00 16. " LOOP_BACK ,LOOP BACK Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " STOP_EXT_FRAME ,Stop Extended Frame Communication" "Not stopped,Stopped" bitfld.long 0x00 12. " HGEN_CTRL ,LIN Mode Bit (Type of Mask Filtering Comparison)" "ID-Byte,ID-Slave task byte" textline " " bitfld.long 0x00 11. " CTYPE ,LIN Mode Bit (Classic/Enhanced)" "Classic,Enhanced" bitfld.long 0x00 10. " MBUF_MODE ,Receive/Transmit Buffer Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " ADAPT ,LIN Mode Bit (Automatic Baudrate Adjustment)" "Disabled,Enabled" bitfld.long 0x00 8. " SLEEP ,SCI Sleep Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " SW_nRESET ,Software Reset" "Reset,Ready" bitfld.long 0x00 6. " LIN_MODE ,LIN MODE Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " CLOCK ,SCI Internal Clock Enable" "Slave,Master" sif (cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")) bitfld.long 0x00 4. " STOP ,SCI Number of Stop Bits" "1 bit,2 bits" textline " " bitfld.long 0x00 3. " PARITY ,SCI Parity Odd/Even Selection" "Odd,Even" endif bitfld.long 0x00 2. " PARITY_ENA ,ID-Parity Enable" "Disabled,Enabled" textline " " sif (cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")) bitfld.long 0x00 1. " TIMING_MODE ,SCI Timing Mode Bit" "Synchronous,Asynchronous" endif bitfld.long 0x00 0. " COMM_MODE ,SCI/BLIN Communication Mode Bit ID4 and ID5 Use" "Not used,Used" elif ((d.l(ad:0xFFF7E500+0x4)&0x44)==0x40) group.long 0x04++0x3 line.long 0x0 "GCR1,Global Control Register" bitfld.long 0x00 25. " TXENA ,SCI Transmitter Enable" "Disabled,Enabled" bitfld.long 0x00 24. " RXENA ,SCI Receiver Enable" "Prevented,Allowed" textline " " bitfld.long 0x00 17. " CONT ,Continue on Suspend" "Frozen,Continue" bitfld.long 0x00 16. " LOOP_BACK ,LOOP BACK Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " STOP_EXT_FRAME ,Stop Extended Frame Communication" "Not stopped,Stopped" bitfld.long 0x00 12. " HGEN_CTRL ,LIN Mode Bit (Type of Mask Filtering Comparison)" "ID-Byte,ID-SlaveTask" textline " " bitfld.long 0x00 11. " CTYPE ,LIN Mode Bit (Classic/Enhanced)" "Classic,Enhanced" bitfld.long 0x00 10. " MBUF_MODE ,Receive/Transmit Buffer Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " ADAPT ,LIN Mode Bit (Automatic Baudrate Adjustment)" "Disabled,Enabled" bitfld.long 0x00 8. " SLEEP ,SCI Sleep Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " SW_nRESET ,Software Reset" "Reset,Ready" bitfld.long 0x00 6. " LIN_MODE ,LIN MODE Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " CLOCK ,SCI Internal Clock Enable" "Slave,Master" sif (cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")) bitfld.long 0x00 4. " STOP ,SCI Number of Stop Bits" "1 bit,2 bits" endif textline " " bitfld.long 0x00 2. " PARITY_ENA ,ID-Parity Enable" "Disabled,Enabled" textline " " sif (cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")) bitfld.long 0x00 1. " TIMING_MODE ,SCI Timing Mode Bit" "Synchronous,Asynchronous" endif bitfld.long 0x00 0. " COMM_MODE ,SCI/BLIN Communication Mode Bit ID4 and ID5 Use" "Not used,Used" elif (((d.l((ad:0xFFF7E500+0x4)))&0x44)==0x04) group.long 0x04++0x3 line.long 0x0 "GCR1,Global Control Register" bitfld.long 0x00 25. " TXENA ,SCI Transmitter Enable" "Disabled,Enabled" bitfld.long 0x00 24. " RXENA ,SCI Receiver Enable" "Prevented,Allowed" textline " " bitfld.long 0x00 17. " CONT ,Continue on Suspend" "Frozen,Continue" bitfld.long 0x00 16. " LOOP_BACK ,LOOP BACK Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " MBUF_MODE ,Receive/Transmit Buffer Enable" "Disabled,Enabled" bitfld.long 0x00 8. " SLEEP ,SCI Sleep Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " SW_nRESET ,Software Reset" "Reset,Ready" bitfld.long 0x00 6. " LIN_MODE ,LIN MODE Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " CLOCK ,SCI Internal Clock Enable" "External,Internal" bitfld.long 0x00 4. " STOP ,SCI Number of Stop Bits" "1 bit,2 bits" textline " " bitfld.long 0x00 3. " PARITY ,SCI Parity Odd/Even Selection" "Odd,Even" bitfld.long 0x00 2. " PARITY_ENA ,Parity Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " TIMING_MODE ,SCI Timing Mode Bit" "Synchronous,Asynchronous" bitfld.long 0x00 0. " COMM_MODE ,SCI/BLIN Communication Mode Bit" "Idle-line,Address-bit" else group.long 0x04++0x3 line.long 0x0 "GCR1,Global Control Register" bitfld.long 0x00 25. " TXENA ,SCI Transmitter Enable" "Disabled,Enabled" bitfld.long 0x00 24. " RXENA ,SCI Receiver Enable" "Prevented,Allowed" textline " " bitfld.long 0x00 17. " CONT ,Continue on Suspend" "Frozen,Continue" bitfld.long 0x00 16. " LOOP_BACK ,LOOP BACK Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " MBUF_MODE ,Receive/Transmit Buffer Enable" "Disabled,Enabled" bitfld.long 0x00 8. " SLEEP ,SCI Sleep Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " SW_nRESET ,Software Reset" "Reset,Ready" bitfld.long 0x00 6. " LIN_MODE ,LIN MODE Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " CLOCK ,SCI Internal Clock Enable" "External,Internal" bitfld.long 0x00 4. " STOP ,SCI Number of Stop Bits" "1 bit,2 bits" textline " " bitfld.long 0x00 2. " PARITY_ENA ,Parity Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " TIMING_MODE ,SCI Timing Mode Bit" "Synchronous,Asynchronous" bitfld.long 0x00 0. " COMM_MODE ,SCI/BLIN Communication Mode Bit" "Idle-line,Address-bit" endif width 8. if ((d.l(ad:0xFFF7E500+0x4)&0x40)==0x40) group.long 0x08++0x3 line.long 0x0 "GCR2,Global Control Register" bitfld.long 0x00 17. " CC ,Compare Checksum" "No effect,Compared" bitfld.long 0x00 16. " SC ,Send Checksum" "No effect,Compared" textline " " bitfld.long 0x00 8. " GEN_WU ,Generate Wakeup Signal" "No effect,Generated" bitfld.long 0x00 0. " POWERDOWN ,POWERDOWN" "Normal,Local low-power" else group.long 0x08++0x3 line.long 0x0 "GCR2,Global Control Register" sif (cpu()!="TMS570PSFC61")&&(cpu()!="TMS470MF031")&&(cpu()!="TMS470MF042")&&(cpu()!="TMS470MF066")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*") bitfld.long 0x00 8. " GEN_WU ,Generate Wakeup Signal" "No effect,Generated" textline " " endif bitfld.long 0x00 0. " POWERDOWN ,POWERDOWN" "Normal,Local low-power" endif width 11. tree "SCI Interrupt Registers" if ((d.l(ad:0xFFF7E500+0x4)&0x40)==0x40) group.long 0x0C++0x3 line.long 0x0 "SETINT,Interrupt Register" setclrfld.long 0x00 31. 0x00 31. 0x04 31. " BE_INT_set/clr ,Bit Error Interrupt" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x04 30. " PBE_INT_set/clr ,Physical Bus Error Interrupt" "Disabled,Enabled" textline " " setclrfld.long 0x00 29. 0x00 29. 0x04 29. " CE_INT_set/clr ,Checksum-Error Interrupt" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x04 28. " ISFE_INT_set/clr ,Inconsistent-Synch-Field-Error Interrupt" "Disabled,Enabled" textline " " setclrfld.long 0x00 27. 0x00 27. 0x04 27. " NRE_INT_set/clr ,No-Reponse-Error Interrupt" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x04 26. " FE_INT_set/clr ,Framing-Error Interrupt" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x04 25. " OE_INT_set/clr ,Overrun-Error Interrupt" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PE_INT_set/clr ,Parity Interrupt" "Disabled,Enabled" textline " " sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")) setclrfld.long 0x00 17. 0x00 17. 0x04 17. " RX_DMA_set/clr ,Receive DMA" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x04 16. " TX_DMA_set/clr ,Transmit DMA" "Disabled,Enabled" textline " " endif setclrfld.long 0x00 13. 0x00 13. 0x04 13. " ID_INT_set/clr ,ID Interrupt" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x04 9. " RX_INT_set/clr ,Receiver Interrupt Enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 8. 0x00 8. 0x04 8. " TX_INT_set/clr ,Transmitter Interrupt" "Disabled,Enabled" setclrfld.long 0x00 7. 0x00 7. 0x04 7. " TOA3WUS_INT_set/clr ,Timeout After 3 Wakeup Signals Interrupt" "Disabled,Enabled" textline " " setclrfld.long 0x00 6. 0x00 6. 0x04 6. " TOAWUS_INT_set/clr ,Timeout After Wakeup Signal Interrupt" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x04 4. " TIMEOUT_INT_set/clr ,Timeout Interrupt" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x04 1. " WAKEUP_INT_set/clr ,Wake-up Interrupt" "Disabled,Enabled" else group.long 0x0C++0x3 line.long 0x0 "SETINT,Interrupt Register" setclrfld.long 0x00 26. 0x00 26. 0x04 26. " FE_INT_set/clr ,Framing-Error Interrupt" "Disabled,Enabled" setclrfld.long 0x00 25. 0x00 25. 0x04 25. " OE_INT_set/clr ,Overrun-Error Interrupt" "Disabled,Enabled" textline " " setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PE_INT_set/clr ,Parity Interrupt" "Disabled,Enabled" sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")) setclrfld.long 0x00 18. 0x00 18. 0x04 18. " RX_DMA_ALL_set/clr ,Receive DMA All" "Disabled,Enabled" textline " " setclrfld.long 0x00 17. 0x00 17. 0x04 17. " RX_DMA_set/clr ,Receive DMA" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x04 16. " TX_DMA_set/clr ,Transmit DMA" "Disabled,Enabled" endif textline " " setclrfld.long 0x00 9. 0x00 9. 0x04 9. " RX_INT_set/clr ,Receiver Interrupt Enable" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x04 8. " TX_INT_set/clr ,Transmitter Interrupt" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x04 1. " WAKEUP_INT_set/clr ,Wake-up Interrupt" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x04 0. " BRKDT_INT_set/clr ,Break-detect Interrupt" "Disabled,Enabled" endif width 11. if ((d.l(ad:0xFFF7E500+0x4)&0x40)==0x40) group.long 0x14++0x3 line.long 0x0 "SETINTLVL,Interrupt Level Register" setclrfld.long 0x00 31. 0x00 31. 0x04 31. " BE_INT_LVL_set/clr ,Bit Error Interrupt Level" "INT0,INT1" setclrfld.long 0x00 30. 0x00 30. 0x04 30. " PBE_INT_LVL_set/clr ,Physical Bus Error Interrupt Level" "INT0,INT1" textline " " setclrfld.long 0x00 29. 0x00 29. 0x04 29. " CE_INT_LVL_set/clr ,Checksum-Error Interrupt Level" "INT0,INT1" setclrfld.long 0x00 28. 0x00 28. 0x04 28. " ISFE_INT_LVL_set/clr ,Inconsistent-Synch-Field-Error Interrupt Level" "INT0,INT1" textline " " setclrfld.long 0x00 27. 0x00 27. 0x04 27. " NRE_INT_LVL_set/clr ,No-Reponse-Error Interrupt Level" "INT0,INT1" setclrfld.long 0x00 26. 0x00 26. 0x04 26. " FE_INT_LVL_set/clr ,Framing-Error Interrupt Level" "INT0,INT1" textline " " setclrfld.long 0x00 25. 0x00 25. 0x04 25. " OE_INT_LVL_set/clr ,Overrun-Error Interrupt Level" "INT0,INT1" setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PE_INT_LVL_set/clr ,Parity Error Interrupt Level" "INT0,INT1" textline " " setclrfld.long 0x00 13. 0x00 13. 0x04 13. " ID_INT_LVL_set/clr ,ID Interrupt Level" "INT0,INT1" setclrfld.long 0x00 9. 0x00 9. 0x04 9. " RX_INT_LVL_set/clr ,Receiver Interrupt Level" "INT0,INT1" textline " " setclrfld.long 0x00 8. 0x00 8. 0x04 8. " TX_INT_LVL_set/clr ,Transmitter Interrupt Level" "INT0,INT1" setclrfld.long 0x00 7. 0x00 7. 0x04 7. " TOA3WUS_INT_LVL_set/clr ,Timeout After 3 Wakeup Signals Interrupt" "INT0,INT1" textline " " setclrfld.long 0x00 6. 0x00 6. 0x04 6. " TOAWUS_INT_LVL_set/clr ,Timeout After Wakeup Signal Interrupt Level" "INT0,INT1" setclrfld.long 0x00 4. 0x00 4. 0x04 4. " TIMEOUT_INT_LVL_set/clr ,Timeout Interrupt Level" "INT0,INT1" textline " " setclrfld.long 0x00 1. 0x00 1. 0x04 1. " WAKEUP_INT_LVL_set/clr ,Wake-up Interrupt Level" "INT0,INT1" else group.long 0x14++0x3 line.long 0x0 "SETINTLVL,Interrupt Level Register" setclrfld.long 0x00 26. 0x00 26. 0x04 26. " FE_INT_LVL_set/clr ,Framing-Error Interrupt Level" "INT0,INT1" setclrfld.long 0x00 25. 0x00 25. 0x04 25. " OE_INT_LVL_set/clr ,Overrun-Error Interrupt Level" "INT0,INT1" textline " " setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PE_INT_LVL_set/clr ,Parity Error Interrupt Level" "INT0,INT1" sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")) setclrfld.long 0x00 18. 0x00 18. 0x04 18. " RX_DMA_ALL_INT_LVL_set/clr ,Receive DMA All Interrupt Level" "INT0,INT1" endif textline " " setclrfld.long 0x00 9. 0x00 9. 0x04 9. " RX_INT_LVL_set/clr ,Receiver Interrupt Level" "INT0,INT1" setclrfld.long 0x00 8. 0x00 8. 0x04 8. " TX_INT_LVL_set/clr ,Transmitter Interrupt Level" "INT0,INT1" textline " " setclrfld.long 0x00 1. 0x00 1. 0x04 1. " WAKEUP_INT_LVL_set/clr ,Wake-up Interrupt Level" "INT0,INT1" setclrfld.long 0x00 0. 0x00 0. 0x04 0. " BRKDT_INT_set/clr ,Break-Detect Interrupt Level" "INT0,INT1" endif tree.end width 8. if ((d.l(ad:0xFFF7E500+0x4)&0x40)==0x40) group.long 0x1C++0x3 line.long 0x0 "FLR,Flags Register" eventfld.long 0x00 31. " BE ,Bit Error Flag" "Not detected,Detected" eventfld.long 0x00 30. " PBE ,Physiscal Bus Error Flag" "Not detected,Detected" textline " " eventfld.long 0x00 29. " CE ,Checksum Error Flag" "Not detected,Detected" eventfld.long 0x00 28. " ISFE ,Inconsistent Synch Field Error Flag" "Not detected,Detected" textline " " eventfld.long 0x00 27. " NRE ,No-Response Error Flag" "Not detected,Detected" eventfld.long 0x00 26. " FE ,Framing Error Flag" "Not detected,Detected" textline " " eventfld.long 0x00 25. " OE ,Overrun Error Flag" "Not detected,Detected" eventfld.long 0x00 24. " PE ,Parity Error Flag" "Not detected,Detected" textline " " eventfld.long 0x00 14. " ID_RX_FLAG ,Identifier On Receive Flag" "Not received,Received" eventfld.long 0x00 13. " ID_TX_FLAG ,Identifier On Transmit Flag" "Not received,Received" textline " " bitfld.long 0x00 11. " TX_EMPTY ,Transmitter Empty Flag" "Not empty,Empty" eventfld.long 0x00 9. " RXRDY ,Receiver Ready Flag" "Not ready,Ready" textline " " bitfld.long 0x00 8. " TXRDY ,Transmitter Buffer Register Ready Flag" "Full,Ready" eventfld.long 0x00 7. " TOA3WUS ,Timeout After 3 Wakeup Signals Flag" "No timeout,Timeout" textline " " eventfld.long 0x00 6. " TOAWUS ,Timeout After Wakeup Signal Flag" "No timeout,Timeout" eventfld.long 0x00 4. " TIMEOUT ,LIN Bus IDLE Timeout Flag" "Not detected,Detected" textline " " bitfld.long 0x00 3. " BUSY_FLAG ,BUSY Flag" "Not busy,Busy" eventfld.long 0x00 1. " WAKEUP ,Wake-up Flag" "No wake up,Wake up" else group.long 0x1C++0x3 line.long 0x0 "FLR,Flags Register" sif (cpu()!="TMS570PSFC61")&&(cpu()!="TMS470MF031")&&(cpu()!="TMS470MF042")&&(cpu()!="TMS470MF066")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*") eventfld.long 0x00 31. " BE ,Bit Error Flag" "Not detected,Detected" textline " " endif eventfld.long 0x00 26. " FE ,Framing Error Flag" "Not detected,Detected" textline " " eventfld.long 0x00 25. " OE ,Overrun Error Flag" "Not detected,Detected" eventfld.long 0x00 24. " PE ,Parity Error Flag" "Not detected,Detected" textline " " bitfld.long 0x00 12. " RXWAKE ,Receiver Wakeup Detect Flag" "Not address,Address" bitfld.long 0x00 11. " TX_EMPTY ,Transmitter Empty Flag" "Not empty,Empty" textline " " bitfld.long 0x00 10. " TXWAKE ,SCI Transmitter Wakeup Method Select" "Data,Address" eventfld.long 0x00 9. " RXRDY ,Receiver Ready Flag" "Not ready,Ready" textline " " bitfld.long 0x00 8. " TXRDY ,Transmitter Buffer Register Ready Flag (SCITD)" "Full,Ready" bitfld.long 0x00 3. " BUSY_FLAG ,BUSY Flag" "Not busy,Busy" textline " " bitfld.long 0x00 2. " IDLE ,SCI Receiver in Idle State" "Not detected,Detected" sif (cpu()!="TMS570PSFC61")&&(cpu()!="TMS470MF031")&&(cpu()!="TMS470MF042")&&(cpu()!="TMS470MF066")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!=("TMS570LS0332")&&!cpuis("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*") eventfld.long 0x00 1. " WAKEUP ,Wake-up Flag" "No wake up,Wake up" endif textline " " eventfld.long 0x00 0. " BRKDT ,SCI Break-Detect Flag" "Not detected,Detected" endif width 9. tree "SCI Interrupt Vector Offset Registers" hgroup.long 0x20++0x3 hide.long 0x0 "INVECT0,Interrupt Vector Offset 0" in hgroup.long 0x24++0x3 hide.long 0x0 "INVECT1,Interrupt Vector Offset 1" in tree.end width 8. if ((d.l(ad:0xFFF7E500+0x4)&0x40)==0x40) group.long 0x28++0x3 line.long 0x0 "FORMAT,Format Control Register" bitfld.long 0x00 16.--18. " LENGTH ,Frame Length Control Bits" "1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes" elif (((d.l(ad:0xFFF7E500+0x4)&0x40)==0x0)&&(((d.l((ad:0xFFF7E500+0x04)))&0x0400)==0x0400)) group.long 0x28++0x3 line.long 0x0 "FORMAT,Format Control Register" bitfld.long 0x00 16.--18. " LENGTH ,Frame Length Control Bits" "1 character,2 characters,3 characters,4 characters,5 characters,6 characters,7 characters,8 characters" bitfld.long 0x00 0.--2. " CHAR ,Character Length Control Bits" "1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits" else group.long 0x28++0x3 line.long 0x0 "FORMAT,Format Control Register" bitfld.long 0x00 0.--2. " CHAR ,Character Length Control Bits" "1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits" endif group.long 0x2C++0x3 line.long 0x0 "BRSR,Baud Rate Selection Register" hexmask.long.byte 0x00 28.--30. 1. " U ,SCI/BLIN Super Fractional Divider Selection" hexmask.long.byte 0x00 24.--27. 1. " M ,SCI/BLIN 4-bit Fractional Divider Selection" hexmask.long.tbyte 0x00 0.--23. 1. " PRESCALER_P ,SCI/BLIN 24-bit Integer Prescaler Selection" width 4. tree "SCI Data Buffer Registers" rgroup.long 0x30++0x3 line.long 0x0 "ED,SCI Data Buffer" hexmask.long.byte 0x00 0.--7. 1. " ED ,Emulation Data" hgroup.long 0x34++0x3 hide.long 0x0 "RD,SCI Data Buffer" in group.long 0x38++0x3 line.long 0x0 "TD,SCI Data Buffer" hexmask.long.byte 0x00 0.--7. 1. " TD ,Transmit Data" tree.end tree "SCI Pin I/O Control Registers" width 6. if ((d.l(ad:0xFFF7E500+0x4)&0x40)==0x40) group.long 0x3C++0x3 line.long 0x0 "PIO0,Pin I/O Control Register 0" bitfld.long 0x00 2. " TX_FUNC ,Defines the Function of Pin SCITX" "GPIO,SCITX" bitfld.long 0x00 1. " RX_FUNC ,Defines the Function of Pin SCIRX" "GPIO,SCIRX" sif (cpu()!="TMS570PSFC61"&&cpu()!="TMS570LC4357"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*")) textline " " bitfld.long 0x00 0. " CLK_FUNC ,Clock Function" "GPIO,?..." endif else group.long 0x3C++0x3 line.long 0x0 "PIO0,Pin I/O Control Register 0" bitfld.long 0x00 2. " TX_FUNC ,Defines the Function of Pin SCITX" "GPIO,SCITX" bitfld.long 0x00 1. " RX_FUNC ,Defines the Function of Pin SCIRX" "GPIO,SCIRX" sif (cpu()!="TMS570PSFC61"&&cpu()!="TMS570LC4357"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*")) textline " " bitfld.long 0x00 0. " CLK_FUNC ,Clock Function" "GPIO,SCICLK" endif endif sif (cpu()!="TMS570PSFC61"&&cpu()!="TMS570LC4357") if ((d.l(ad:0xFFF7E500+0x3c)&0x1)==0x0) group.long 0x40++0x3 line.long 0x0 "PIO1,Pin I/O Control Register 1" bitfld.long 0x00 2. " TX_DIR ,Transmit Direction" "Input,Output" bitfld.long 0x00 1. " RX_DIR ,Receive Direction" "Input,Output" sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*")) textline " " bitfld.long 0x00 0. " CLK_DIR ,Clock Data Direction" "Input,Output" endif elif (((d.l(ad:0xFFF7E500+0x3c)&0x1)==0x1)&&((d.l(ad:0xFFF7E500+0x4)&0x60)==0x20)) group.long 0x40++0x3 line.long 0x0 "PIO1,Pin I/O Control Register 1" bitfld.long 0x00 2. " TX_DIR ,Transmit Direction" "Input,Output" bitfld.long 0x00 1. " RX_DIR ,Receive Direction" "Input,Output" sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*")) textline " " bitfld.long 0x00 0. " CLK_DIR ,Clock Data Direction" "Not output,Output" endif elif (((d.l(ad:0xFFF7E500+0x3c)&0x1)==0x1)&&((d.l(ad:0xFFF7E500+0x4)&0x60)==0x0)) group.long 0x40++0x3 line.long 0x0 "PIO1,Pin I/O Control Register 1" bitfld.long 0x00 2. " TX_DIR ,Transmit Direction" "Input,Output" bitfld.long 0x00 1. " RX_DIR ,Receive Direction" "Input,Output" sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*")) textline " " bitfld.long 0x00 0. " CLK_DIR ,Clock Data Direction" "Input,Not input" endif else group.long 0x40++0x3 line.long 0x0 "PIO1,Pin I/O Control Register 1" bitfld.long 0x00 2. " TX_DIR ,Transmit Direction" "Input,Output" bitfld.long 0x00 1. " RX_DIR ,Receive Direction" "Input,Output" sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*")) textline " " bitfld.long 0x00 0. " CLK_DIR ,Clock Data Direction" "Input,Output" endif endif else group.long 0x40++0x3 line.long 0x0 "PIO1,Pin I/O Control Register 1" bitfld.long 0x00 2. " TX_DIR ,Transmit Direction" "Input,Output" bitfld.long 0x00 1. " RX_DIR ,Receive Direction" "Input,Output" endif rgroup.long 0x44++0x3 line.long 0x0 "PIO2,Pin I/O Control Register 2" bitfld.long 0x00 2. " TX_IN ,Contains Current Value on the SCITX Pin" "Low,High" bitfld.long 0x00 1. " RX_IN ,Contains Current Value on the SCIRX Pin" "Low,High" sif (cpu()!="TMS570PSFC61"&&cpu()!="TMS570LC4357"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")) textline " " bitfld.long 0x00 0. " CLK_IN ,Contains the Current Value on Pin SCICLK" "Low,High" endif width 6. group.long 0x48++0x3 line.long 0x0 "PIO3,Pin I/O Control Register 3" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " TX_OUT_set/clr ,SCITX Pin Data Output" "Low,High" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " RX_OUT_set/clr ,SCIRX Pin Data Output" "Low,High" sif (cpu()!="TMS570PSFC61"&&cpu()!="TMS570LC4357"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*")) textline " " setclrfld.long 0x00 0. 0x00 0. 0x08 0. " CLK_OUT_set/clr ,SCICLK Pin Data Output" "Low,High" endif sif cpuis("TMS570LS21*")||cpuis("TMS570LS31*") group.long 0x4C++0x3 line.long 0x0 "PIO4,Pin I/O Control Register 4" bitfld.long 0x00 2. " TX_DIR ,Transmit Direction" "Input,Output" bitfld.long 0x00 1. " RX_DIR ,Receive Direction" "Input,Output" group.long 0x50++0x3 line.long 0x0 "PIO5,Pin I/O Control Register 5" bitfld.long 0x00 2. " TX_DIR ,Transmit Direction" "Input,Output" bitfld.long 0x00 1. " RX_DIR ,Receive Direction" "Input,Output" endif width 6. group.long 0x54++0x3 line.long 0x0 "PIO6,Pin I/O Control Register 6" bitfld.long 0x00 2. " TX_ODR ,TX Open Drain Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RX_ODR ,RX Open Drain Enable" "Disabled,Enabled" sif (cpu()!="TMS570PSFC61"&&cpu()!="TMS570LC4357"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*")) textline " " bitfld.long 0x00 0. " CLK_ODR ,CLK Open Drain Enable" "Disabled,Enabled" endif group.long 0x58++0x3 line.long 0x0 "PIO7,Pin I/O Control Register 7" bitfld.long 0x00 2. " TX_PD ,TX Pin Pull Control Disable" "No,Yes" bitfld.long 0x00 1. " RX_PD ,RX Pin Pull Control Disable" "No,Yes" sif (cpu()!="TMS570PSFC61"&&cpu()!="TMS570LC4357"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&cpu()!=("TMS570LS1114*")&&cpu()!=("TMS570LS1115*")&&cpu()!=("TMS570LS1224*")&&cpu()!=("TMS570LS1225*")&&cpu()!=("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*")) textline " " bitfld.long 0x00 0. " CLK_PD ,CLK Pin Pull Control Disable" "No,Yes" endif group.long 0x5C++0x3 line.long 0x0 "PIO8,Pin I/O Control Register 8" bitfld.long 0x00 2. " TX_PSL ,TX Pin Pull Select" "Pull down,Pull up" bitfld.long 0x00 1. " RX_PSL ,RX Pin Pull Select" "Pull down,Pull up" sif (cpu()!="TMS570PSFC61"&&cpu()!="TMS570LC4357"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*")) textline " " bitfld.long 0x00 0. " CLK_PSL ,CLK Pin Pull Select" "Pull down,Pull up" endif tree.end tree "BLIN Registers" width 9. if ((d.l(ad:0xFFF7E500+0x4)&0x40)==0x40) group.long 0x60++0x3 line.long 0x0 "LINCOMP,BLINCOMPARE Register" bitfld.long 0x00 8.--9. " SDEL ,2-bit Synch Delimiter Compare" "1 bit,2 bits,3 bits,4 bits" bitfld.long 0x00 0.--2. " SBREAK ,3-bit Synch Break Extend" "Not extended,1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits" else hgroup.long 0x60++0x3 hide.long 0x0 "LINCOMP,BLINCOMPARE Register" endif sif (cpu()!="TMS570LC4357"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")) hgroup.long 0x64++0x3 hide.long 0x0 "LINRD0,LINRD0 Register" in hgroup.long 0x68++0x3 hide.long 0x0 "LINRD1,LINRD1 Register" in else rgroup.long 0x64++0x3 line.long 0x0 "LINRD0,LINRD0 Register" hexmask.long.byte 0x00 24.--31. 0x1 " RD0 ,Receive Buffer 0" hexmask.long.byte 0x00 16.--23. 0x1 " RD1 ,Receive Buffer 1" hexmask.long.byte 0x00 8.--15. 0x1 " RD2 ,Receive Buffer 2" hexmask.long.byte 0x00 0.--7. 0x1 " RD3 ,Receive Buffer 3" rgroup.long 0x68++0x3 line.long 0x0 "LINRD1,LINRD1 Register" hexmask.long.byte 0x00 24.--31. 0x1 " RD4 ,Receive Buffer 4" hexmask.long.byte 0x00 16.--23. 0x1 " RD5 , Receive Buffer 5" hexmask.long.byte 0x00 8.--15. 0x1 " RD6 ,Receive Buffer 6" hexmask.long.byte 0x00 0.--7. 0x1 " RD7 ,Receive Buffer 7" endif width 9. if ((d.l(ad:0xFFF7E500+0x4)&0x40)==0x40) group.long 0x6C++0x3 line.long 0x0 "LINMASK,LINMASK Register" bitfld.long 0x00 23. " RX_ID_MASK7 ,RX ID Mask 7" "Not masked,Masked" bitfld.long 0x00 22. " RX_ID_MASK6 ,RX ID Mask 6" "Not masked,Masked" textline " " bitfld.long 0x00 21. " RX_ID_MASK5 ,RX ID Mask 5" "Not masked,Masked" bitfld.long 0x00 20. " RX_ID_MASK4 ,RX ID Mask 4" "Not masked,Masked" textline " " bitfld.long 0x00 19. " RX_ID_MASK3 ,RX ID Mask 3" "Not masked,Masked" bitfld.long 0x00 18. " RX_ID_MASK2 ,RX ID Mask 2" "Not masked,Masked" textline " " bitfld.long 0x00 17. " RX_ID_MASK1 ,RX ID Mask 1" "Not masked,Masked" bitfld.long 0x00 16. " RX_ID_MASK0 ,RX ID Mask 0" "Not masked,Masked" textline " " bitfld.long 0x00 7. " TX_ID_MASK7 ,TX ID Mask 7" "Not masked,Masked" bitfld.long 0x00 6. " TX_ID_MASK6 ,TX ID Mask 6" "Not masked,Masked" textline " " bitfld.long 0x00 5. " TX_ID_MASK5 ,TX ID Mask 5" "Not masked,Masked" bitfld.long 0x00 4. " TX_ID_MASK4 ,TX ID Mask 4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " TX_ID_MASK3 ,TX ID Mask 3" "Not masked,Masked" bitfld.long 0x00 2. " TX_ID_MASK2 ,TX ID Mask 2" "Not masked,Masked" textline " " bitfld.long 0x00 1. " TX_ID_MASK1 ,TX ID Mask 1" "Not masked,Masked" bitfld.long 0x00 0. " TX_ID_MASK0 ,TX ID Mask 0" "Not masked,Masked" else hgroup.long 0x6C++0x3 hide.long 0x0 "LINMASK,LINMASK Register" endif width 9. if ((d.l(ad:0xFFF7E500+0x4)&0x40)==0x40) group.long 0x70++0x3 line.long 0x0 "LINID,LINID Register" hexmask.long.byte 0x00 16.--23. 1. " RECEIVED_ID ,Received Identifier" hexmask.long.byte 0x00 8.--15. 1. " ID_SLAVETASK_BYTE ,Identifier Slave Task Byte" hexmask.long.byte 0x00 0.--7. 1. " ID_BYTE ,Identifier Byte" else hgroup.long 0x70++0x3 hide.long 0x0 "LINID,LINID Register" endif width 9. group.long 0x74++0x3 line.long 0x0 "LINTD0,LINTD0 Register" hexmask.long.byte 0x00 24.--31. 1. " TD0 ,8-bit Transmit Buffer 0" hexmask.long.byte 0x00 16.--23. 1. " TD1 ,8-bit Transmit Buffer 1" hexmask.long.byte 0x00 8.--15. 1. " TD2 ,8-bit Transmit Buffer 2" hexmask.long.byte 0x00 0.--7. 1. " TD3 ,8-bit Transmit Buffer 3" group.long 0x78++0x3 line.long 0x0 "LINTD1,LINTD1 Register" hexmask.long.byte 0x00 24.--31. 1. " TD4 ,8-bit Transmit Buffer 4" hexmask.long.byte 0x00 16.--23. 1. " TD5 ,8-bit Transmit Buffer 5" hexmask.long.byte 0x00 8.--15. 1. " TD6 ,8-bit Transmit Buffer 6" hexmask.long.byte 0x00 0.--7. 1. " TD7 ,8-bit Transmit Buffer 7" tree.end width 11. if ((d.l(ad:0xFFF7E500+0x4)&0x40)==0x40) group.long 0x7C++0x3 line.long 0x0 "MBRSR,Maximum Baud Rate Selection Register" hexmask.long.word 0x00 0.--12. 1. " MBR ,Maximum Baud Rate Prescaler" else hgroup.long 0x7C++0x3 hide.long 0x0 "MBRSR,Maximum Baud Rate Selection Register" endif sif (cpu()!="TMS470MF031")&&(cpu()!="TMS470MF042")&&(cpu()!="TMS470MF066")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&(cpu()!="TMS570LC4357")&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*") group.long 0x80++0x3 line.long 0x0 "PIO9,Pin I/O Control Register 9" bitfld.long 0x00 2. " TX_SL ,This Bit Controls the Slew Rate for the SCITX Pin" "Normal,Slew" bitfld.long 0x00 1. " RX_SL ,This Bit Controls the Slew Rate for the SCIRX Pin" "Normal,Slew" sif (cpu()!="TMS570PSFC61") bitfld.long 0x00 0. " CLK_SL ,This Bit Controls the Slew Rate for the SCICLK Pin" "Normal,Slew" endif endif width 11. if ((d.l(ad:0xFFF7E500+0x4)&0x40)==0x40) group.long 0x90++0x3 line.long 0x0 "IODFTCTRL,IODFT for BLIN Moduler" bitfld.long 0x00 31. " BEEN ,Bit Error Enable" "Disabled,Enabled" bitfld.long 0x00 30. " PBEEN ,Physical Bus Error Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " CEEN ,Checksum Error Enable" "Disabled,Enabled" bitfld.long 0x00 28. " ISFEEN ,Inconsistent Synch Field Error Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " FEEN ,Frame Error Enable" "Disabled,Enabled" bitfld.long 0x00 19.--20. " PSM ,PIN SAMPLE MASK" "No mask,TBIT_CENTER,TBIT_CENTER + SCLK,TBIT_CENTER + 2 SCLK" textline " " bitfld.long 0x00 16.--18. " TX_SHIFT ,Transmit Shift" "No delay,1 SCLK,2 SCLKs,3 SCLKs,4 SCLKs,5 SCLKs,6 SCLKs,7 SCLKs" bitfld.long 0x00 8.--11. " IODFTENA ,IO DFT Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" textline " " bitfld.long 0x00 1. " LPBENA ,Module Loopback Enable" "Analog,Digital" bitfld.long 0x00 0. " RXPENA ,Module Analog Loopback Through Receive/Transmit Pin Enable" "Transmit,Receive" else group.long 0x90++0x3 line.long 0x0 "IODFTCTRL,IODFT for BLIN Moduler" bitfld.long 0x00 26. " FEEN ,Frame Error Enable" "Disabled,Enabled" bitfld.long 0x00 25. " PEEN ,Parity Error Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " BDEEN ,Break Detect Error Enable" "Disabled,Enabled" bitfld.long 0x00 19.--20. " PSM ,PIN SAMPLE MASK" "No mask,TBIT_CENTER,TBIT_CENTER + SCLK,TBIT_CENTER + 2 SCLK" textline " " bitfld.long 0x00 16.--18. " TX_SHIFT ,Transmit Shift" "No delay,1 SCLK,2 SCLKs,3 SCLKs,4 SCLKs,5 SCLKs,6 SCLKs,7 SCLKs" bitfld.long 0x00 8.--11. " IODFTENA ,IO DFT Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" textline " " bitfld.long 0x00 1. " LPBENA ,Module Loopback Enable" "Analog,Digital" bitfld.long 0x00 0. " RXPENA ,Module Analog Loopback Through Receive/Transmit Pin Enable" "Transmit,Receive" endif width 0xb tree.end tree.end ; System Modules Registers tree "CCMR4 (CPU Compare Module - CortexR4)" base ad:0xFFFFF600 width 9. group.long 0x00++0x07 line.long 0x00 "CCMSR,CCM-R4F Status Register" eventfld.long 0x00 16. " CMPE ,Compare error" "No error,Error" bitfld.long 0x00 8. " STC ,Self-test complete" "Not completed,Completed" bitfld.long 0x00 1. " STET ,Self test error type" "Compare match,Compare mismatch" bitfld.long 0x00 0. " STE ,Self-test error" "No error,Error" line.long 0x04 "CCMKEYR,CCM-R4F Key Register" bitfld.long 0x04 0.--3. " MKEY ,Mode key" "Lockstep,,,,,,Self-test,,,Error Forcing,,,,,,Self-test error forcing" width 0x0B tree.end tree "CRC" base ad:0xFE000000 width 20. group.long 0x00++0x03 line.long 0x00 "CRC_CTRL0,CRC Global Control Register 0" sif (cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!="RM46L852-PGE"&&cpu()!="RM46L852-ZWT"&&cpu()!="RM46L850-PGE"&&cpu()!="RM46L850-ZWT"&&cpu()!="RM46L840-ZWT"&&cpu()!="RM46L840-PGE"&&cpu()!="RM46L830-ZWT"&&cpu()!="RM46L830-PGE"&&cpu()!="RM46L450-ZWT"&&cpu()!="RM46L450-PGE"&&cpu()!="RM46L440-ZWT"&&cpu()!="RM46L440-PGE"&&cpu()!="RM46L430-ZWT"&&cpu()!="RM46L430-PGE"&&cpu()!="RM48L950"&&cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")&&cpu()!="RM48L550-ZWT"&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&cpu()!=("TMS570LS3137-EP")) bitfld.long 0x00 24. " CH4_PSA_SWREST ,Channel 4 PSA software reset" "No reset,Reset" bitfld.long 0x00 16. " CH3_PSA_SWREST ,Channel 3 psa software reset" "No reset,Reset" newline endif bitfld.long 0x00 8. " CH2_PSA_SWREST ,Channel 2 PSA software reset" "No reset,Reset" bitfld.long 0x00 0. " CH1_PSA_SWREST ,Channel 1 PSA software reset" "No reset,Reset" group.long 0x08++0x03 line.long 0x00 "CRC_CTRL1,CRC Global Control Register 1" bitfld.long 0x00 0. " PWDN ,Power down" "Not powered down,Powered down" group.long 0x10++0x03 line.long 0x00 "CRC_CTRL2,CRC Global Control Register 2" sif (cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!="RM46L852-PGE"&&cpu()!="RM46L852-ZWT"&&cpu()!="RM46L850-PGE"&&cpu()!="RM46L850-ZWT"&&cpu()!="RM46L840-ZWT"&&cpu()!="RM46L840-PGE"&&cpu()!="RM46L830-ZWT"&&cpu()!="RM46L830-PGE"&&cpu()!="RM46L450-ZWT"&&cpu()!="RM46L450-PGE"&&cpu()!="RM46L440-ZWT"&&cpu()!="RM46L440-PGE"&&cpu()!="RM46L430-ZWT"&&cpu()!="RM46L430-PGE"&&cpu()!="RM48L950"&&cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")&&cpu()!="RM48L550-ZWT"&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&cpu()!=("TMS570LS3137-EP")) bitfld.long 0x00 24.--25. " CH4_MODE ,Channel 4 mode" "Data capture,Auto,,Full-CPU" bitfld.long 0x00 16.--17. " CH3_MODE ,Channel 3 mode" "Data capture,Auto,,Full-CPU" newline endif sif !cpuis("TMS570LS3137-EP") bitfld.long 0x00 8.--9. " CH2_MODE ,Channel 2 mode" "Data capture,Auto,,Full-CPU" bitfld.long 0x00 4. " CH1_TRACEEN ,Channel 1 data trace Enable" "Disabled,Enabled" newline bitfld.long 0x00 0.--1. " CH1_MODE ,Channel 1 mode" "Data capture,Auto,,Full-CPU" else bitfld.long 0x00 8.--9. " CH2_MODE ,Channel 2 mode" "Data capture,Auto,Semi-CPU,Full-CPU" bitfld.long 0x00 4. " CH1_TRACEEN ,Channel 1 data trace Enable" "Disabled,Enabled" newline bitfld.long 0x00 0.--1. " CH1_MODE ,Channel 1 mode" "Data capture,Auto,Semi-CPU,Full-CPU" endif sif (cpu()==("TMS570LS3137-EP")) group.long 0x18++0x03 line.long 0x00 "CRC_INT_SET/CLR,CRC Interrupt Enable Set/Reset Register" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " CH2_TIMEOUTEN ,Channel 2 timeout interrupt" "Disabled,Enabled" setclrfld.long 0x00 11. 0x08 11. 0x10 11. " CH2_UNDEREN ,Channel 2 underrun interrupt" "Disabled,Enabled" newline setclrfld.long 0x00 10. 0x08 10. 0x10 10. " CH2_OVEREN ,Channel 2 overrun interrupt" "Disabled,Enabled" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " CH2_CRCFAILEN ,Channel 2 CRC fail interrupt" "Disabled,Enabled" newline setclrfld.long 0x00 8. 0x08 8. 0x10 8. " CH2_CCITEN ,Channel 2 compression complete interrupt" "Disabled,Enabled" setclrfld.long 0x00 4. 0x08 4. 0x10 4. " CH1_TIMEOUTEN ,Channel 1 timeout interrupt" "Disabled,Enabled" newline setclrfld.long 0x00 3. 0x08 3. 0x10 3. " CH1_UNDEREN ,Channel 1 underrun interrupt" "Disabled,Enabled" setclrfld.long 0x00 2. 0x08 2. 0x10 2. " CH1_OVEREN ,Channel 1 overrun interrupt" "Disabled,Enabled" newline setclrfld.long 0x00 1. 0x08 1. 0x10 1. " CH1_CRCFAILEN ,Channel 1 CRC fail interrupt" "Disabled,Enabled" setclrfld.long 0x00 0. 0x08 0. 0x10 0. " CH1_CCITEN ,Channel 1 compression complete interrupt" "Disabled,Enabled" else group.long 0x18++0x03 line.long 0x00 "CRC_INTS,CRC Interrupt Enable Set Register" sif (!cpuis("RM48L952-PGE")&&!cpuis("RM48L952-ZWT")&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!="RM46L852-PGE"&&cpu()!="RM46L852-ZWT"&&cpu()!="RM46L850-PGE"&&cpu()!="RM46L850-ZWT"&&cpu()!="RM46L840-ZWT"&&cpu()!="RM46L840-PGE"&&cpu()!="RM46L830-ZWT"&&cpu()!="RM46L830-PGE"&&cpu()!="RM46L450-ZWT"&&cpu()!="RM46L450-PGE"&&cpu()!="RM46L440-ZWT"&&cpu()!="RM46L440-PGE"&&cpu()!="RM46L430-ZWT"&&cpu()!="RM46L430-PGE"&&cpu()!="RM48L950"&&cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")&&cpu()!="RM48L550-ZWT"&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")) bitfld.long 0x00 28. " CH4_TIMEOUTEN ,Channel 4 timeout interrupt enable" "Disabled,Enabled" bitfld.long 0x00 27. " CH4_UNDEREN ,Channel 4 underrun interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 26. " CH4_OVEREN ,Channel 4 overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 25. " CH4_CRCFAILEN ,Channel 4 CRC fail interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 20. " CH3_TIMEOUTEN ,Channel 3 timeout interrupt enable" "Disabled,Enabled" bitfld.long 0x00 19. " CH3_UNDEREN ,Channel 3 underrun interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 18. " CH3_OVEREN ,Channel 3 overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 17. " CH3_CRCFAILEN ,Channel 3 CRC fail interrupt enable" "Disabled,Enabled" newline endif bitfld.long 0x00 12. " CH2_TIMEOUTENS ,Channel 2 timeout interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " CH2_UNDERENS ,Channel 2 underrun interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 10. " CH2_OVERENS ,Channel 2 overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " CH2_CRCFAILENS ,Channel 2 CRC fail interrupt enable" "Disabled,Enabled" newline sif (!cpuis("RM48L950*")&&cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")) bitfld.long 0x00 8. " CH2_CCITEN ,Channel 2 compression complete interrupt enable" "Disabled,Enabled" newline endif bitfld.long 0x00 4. " CH1_TIMEOUTENS ,Channel 1 timeout interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " CH1_UNDERENS ,Channel 1 underrun interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " CH1_OVERENS ,Channel 1 overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " CH1_CRCFAILENS ,Channel 1 CRC fail interrupt enable" "Disabled,Enabled" sif (!cpuis("RM48L950*")&&cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")&&cpu()!="RM48L550-ZWT") newline bitfld.long 0x00 0. " CH1_CCITEN ,Channel 1 compression complete interrupt enable" "Disabled,Enabled" endif group.long 0x20++0x03 line.long 0x00 "CRC_INTR,CRC Interrupt Enable Reset Register" sif (cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!="RM46L852-PGE"&&cpu()!="RM46L852-ZWT"&&cpu()!="RM46L850-PGE"&&cpu()!="RM46L850-ZWT"&&cpu()!="RM46L840-ZWT"&&cpu()!="RM46L840-PGE"&&cpu()!="RM46L830-ZWT"&&cpu()!="RM46L830-PGE"&&cpu()!="RM46L450-ZWT"&&cpu()!="RM46L450-PGE"&&cpu()!="RM46L440-ZWT"&&cpu()!="RM46L440-PGE"&&cpu()!="RM46L430-ZWT"&&cpu()!="RM46L430-PGE"&&cpu()!="RM48L950"&&cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")&&cpu()!="RM48L550-ZWT"&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")) bitfld.long 0x00 28. " CH4_TIMEOUTEN ,Channel 4 timeout interrupt disable" "No,Yes" bitfld.long 0x00 27. " CH4_UNDEREN ,Channel 4 underrun interrupt Disable" "No,Yes" newline bitfld.long 0x00 26. " CH4_OVEREN ,Channel 4 overrun interrupt disable" "No,Yes" bitfld.long 0x00 25. " CH4_CRCFAILEN ,Channel 4 CRC fail interrupt Disable" "No,Yes" newline bitfld.long 0x00 20. " CH3_TIMEOUTEN ,Channel 3 Timeout interrupt disable" "No,Yes" bitfld.long 0x00 19. " CH3_UNDEREN ,Channel 3 underrun interrupt disable" "No,Yes" newline bitfld.long 0x00 18. " CH3_OVEREN ,Channel 3 overrun interrupt disable" "No,Yes" bitfld.long 0x00 17. " CH3_CRCFAILEN ,Channel 3 CRC fail interrupt disable" "No,Yes" newline endif bitfld.long 0x00 12. " CH2_TIMEOUTENR ,Channel 2 timeout interrupt disable" "No,Yes" bitfld.long 0x00 11. " CH2_UNDERENR ,Channel 2 underrun interrupt disable" "No,Yes" newline bitfld.long 0x00 10. " CH2_OVERENR ,Channel 2 overrun interrupt disable" "No,Yes" bitfld.long 0x00 9. " CH2_CRCFAILENR ,Channel 2 CRC fail interrupt disable" "No,Yes" newline sif (!cpuis("RM48L950*")&&cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")&&cpu()!="RM48L550-ZWT") bitfld.long 0x00 8. " CH2_CCITEN ,Channel 2 compression complete interrupt disable" "No,Yes" newline endif bitfld.long 0x00 4. " CH1_TIMEOUTENR ,Channel 1 timeout interrupt disable" "No,Yes" bitfld.long 0x00 3. " CH1_UNDERENR ,Channel 1 underrun interrupt disable" "No,Yes" newline bitfld.long 0x00 2. " CH1_OVERENR ,Channel 1 overrun interrupt disable" "No,Yes" bitfld.long 0x00 1. " CH1_CRCFAILENR ,Channel 1 CRC fail interrupt disable" "No,Yes" sif (!cpuis("RM48L950*")&&cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")&&cpu()!="RM48L550-ZWT") newline bitfld.long 0x00 0. " CH1_CCITEN ,Channel 1 compression complete interrupt disable" "No,Yes" endif endif group.long 0x28++0x03 line.long 0x00 "CRC_STATUS,CRC Interrupt Status Register" sif (cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!="RM46L852-PGE"&&cpu()!="RM46L852-ZWT"&&cpu()!="RM46L850-PGE"&&cpu()!="RM46L850-ZWT"&&cpu()!="RM46L840-ZWT"&&cpu()!="RM46L840-PGE"&&cpu()!="RM46L830-ZWT"&&cpu()!="RM46L830-PGE"&&cpu()!="RM46L450-ZWT"&&cpu()!="RM46L450-PGE"&&cpu()!="RM46L440-ZWT"&&cpu()!="RM46L440-PGE"&&cpu()!="RM46L430-ZWT"&&cpu()!="RM46L430-PGE"&&cpu()!="RM48L950"&&cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")&&cpu()!="RM48L550-ZWT"&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS3137-EP")) eventfld.long 0x00 28. " CH4_TIMEOUT ,Channel 4 CRC timeout status flag" "No interrupt,Interrupt" eventfld.long 0x00 27. " CH4_UNDER ,Channel 4 CRC underrun status flag" "No interrupt,Interrupt" newline eventfld.long 0x00 26. " CH4_OVER ,Channel 4 CRC overrun status flag" "No interrupt,Interrupt" eventfld.long 0x00 25. " CH4_CRCFAIL ,Channel 4 CRC compare fail status flag" "No interrupt,Interrupt" newline eventfld.long 0x00 20. " CH3_TIMEOUT ,Channel 3 CRC timeout status flag" "No interrupt,Interrupt" eventfld.long 0x00 19. " CH3_UNDER ,Channel 3 CRC underrun status flag" "No interrupt,Interrupt" newline eventfld.long 0x00 18. " CH3_OVER ,Channel 3 CRC overrun status flag" "No interrupt,Interrupt" eventfld.long 0x00 17. " CH3_CRCFAIL ,Channel 3 CRC compare fail status flag" "No interrupt,Interrupt" newline endif eventfld.long 0x00 12. " CH2_TIMEOUT ,Channel 2 CRC timeout status flag" "No interrupt,Interrupt" eventfld.long 0x00 11. " CH2_UNDER ,Channel 2 CRC underrun status flag" "No interrupt,Interrupt" newline eventfld.long 0x00 10. " CH2_OVER ,Channel 2 CRC overrun status flag" "No interrupt,Interrupt" eventfld.long 0x00 9. " CH2_CRCFAIL ,Channel 2 CRC compare fail status flag" "No interrupt,Interrupt" newline sif (!cpuis("RM48L950*")&&cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")) eventfld.long 0x00 8. " CH2_CCIT ,Channel 2 CRC pattern compression complete status flag" "No interrupt,Interrupt" newline endif eventfld.long 0x00 4. " CH1_TIMEOUT ,Channel 1 CRC timeout status flag" "No interrupt,Interrupt" eventfld.long 0x00 3. " CH1_UNDER ,Channel 1 CRC underrun status flag" "No interrupt,Interrupt" newline eventfld.long 0x00 2. " CH1_OVER ,Channel 1 CRC overrun status flag" "No interrupt,Interrupt" eventfld.long 0x00 1. " CH1_CRCFAIL ,Channel 1 CRC compare fail status flag" "No interrupt,Interrupt" sif (!cpuis("RM48L950*")&&cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")) newline eventfld.long 0x00 0. " CH1_CCIT ,Channel 1 CRC pattern compression complete status flag" "No interrupt,Interrupt" endif sif !cpuis("TMS570LS3137-EP") rgroup.long 0x30++0x03 line.long 0x00 "CRC_INT_OFFSET_REG,CRC Interrupt Offset Register" hexmask.long.byte 0x00 0.--7. 1. " OFSTREG ,CRC interrupt offset" else hgroup.long 0x30++0x03 hide.long 0x00 "CRC_INT_OFFSET_REG,CRC Interrupt Offset Register" in endif rgroup.long 0x38++0x03 line.long 0x00 "CRC_BUSY,CRC Busy Register" sif (cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!="RM46L852-PGE"&&cpu()!="RM46L852-ZWT"&&cpu()!="RM46L850-PGE"&&cpu()!="RM46L850-ZWT"&&cpu()!="RM46L840-ZWT"&&cpu()!="RM46L840-PGE"&&cpu()!="RM46L830-ZWT"&&cpu()!="RM46L830-PGE"&&cpu()!="RM46L450-ZWT"&&cpu()!="RM46L450-PGE"&&cpu()!="RM46L440-ZWT"&&cpu()!="RM46L440-PGE"&&cpu()!="RM46L430-ZWT"&&cpu()!="RM46L430-PGE"&&cpu()!="RM48L950"&&cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")&&cpu()!="RM48L550-ZWT"&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS3137-EP")) bitfld.long 0x00 24. " CH4_BUSY ,Channel 4 busy flag" "Not busy,Busy" bitfld.long 0x00 16. " CH3_BUSY ,Channel 3 busy flag" "Not busy,Busy" newline endif bitfld.long 0x00 8. " CH2_BUSY ,Channel 2 busy flag" "Not busy,Busy" bitfld.long 0x00 0. " CH1_BUSY ,Channel 1 busy flag" "Not busy,Busy" sif !cpuis("TMS570LS3137-EP") rgroup.long 0x140++0x03 line.long 0x00 "MCRC_TRACE_BUS_SEL,Data Bus Selection Register" bitfld.long 0x00 2. " MEN ,Enable/disables the tracing of VBUSM" "Disabled,Enabled" bitfld.long 0x00 1. " DTCMEN ,Enable/disables the tracing of data TCM" "Disabled,Enabled" newline bitfld.long 0x00 0. " ITCMEN ,Enable/disables the tracing of instruction TCM" "Disabled,Enabled" else group.long 0x140++0x03 line.long 0x00 "CRC_TRACE_BUS_SEL,Data Bus Selection Register" bitfld.long 0x00 2. " MEn ,Enable/disables the tracing of VBUSM" "Disabled,Enabled" bitfld.long 0x00 1. " DTCMEn ,Enable/disables the tracing of data TCM" "Disabled,Enabled" newline bitfld.long 0x00 0. " ITCMEn ,Enable/disables the tracing of instruction TCM" "Disabled,Enabled" endif tree "Channel 1 Registers" group.long 0x40++0x07 line.long 0x00 "CRC_PCOUNT_REG1,CRC Pattern Counter Preload Register 1" hexmask.long.tbyte 0x00 0.--19. 1. " CRC_PAT_COUNT1 ,Channel 1 pattern counter preload" line.long 0x04 "CRC_SCOUNT_REG1,CRC Sector Counter Preload Register 1" hexmask.long.word 0x04 0.--15. 1. " CRC_SEC_COUNT1 ,Channel 1 sector counter preload" hgroup.long 0x48++0x03 hide.long 0x00 "CRC_CURSEC_REG1,CRC Current Sector Register 1" in group.long 0x4C++0x07 line.long 0x00 "CRC_WDTOPLD1,Watchdog Timeout Preload Register" hexmask.long.tbyte 0x00 0.--23. 1. " CRC_WDTOPLD1 ,Channel 1 watchdog timeout counter preload" line.long 0x04 "CRC_BCTOPLD1,CRC channel 1 block complete timeout preload register" hexmask.long.tbyte 0x04 0.--23. 1. " CRC_BCTOPLD1 ,Channel 1 block complete timeout counter preload" group.long 0x60++0x0F line.long 0x00 "PSA_SIGREGL1,Channel 1 PSA Signature Low Register" line.long 0x04 "PSA_SIGREGH1,Channel 1 PSA Signature High Register" line.long 0x08 "CRC_REGL1,Channel 1 CRC Value Low Register" line.long 0x0C "CRC_REGH1,Channel 1 CRC Value High Register" rgroup.long 0x70++0x0F line.long 0x00 "PSA_SECSIGREGL1,Channel 1 PSA Sector Signature Low Register 1" line.long 0x04 "PSA_SECSIGREGH1,Channel 1 PSA Sector Signature High Register 1" line.long 0x08 "RAW_DATAREGL1,Channel 1 Raw Data Low Register 1" line.long 0x0C "RAW_DATAREGH1,Channel 1 Raw Data High Register 1" tree.end tree "Channel 2 Registers" group.long 0x80++0x07 line.long 0x00 "CRC_PCOUNT_REG2,CRC Pattern Counter Preload Register 2" hexmask.long.tbyte 0x00 0.--19. 1. " CRC_PAT_COUNT2 ,Channel 2 pattern counter preload" line.long 0x04 "CRC_SCOUNT_REG2,CRC Sector Counter Preload Register 2" hexmask.long.word 0x04 0.--15. 1. " CRC_SEC_COUNT2 ,Channel 2 sector counter preload" hgroup.long 0x88++0x03 hide.long 0x00 "CRC_CURSEC_REG2,CRC Current Sector Register 2" in group.long 0x8C++0x07 line.long 0x00 "CRC_WDTOPLD2,Watchdog Timeout Preload Register" hexmask.long.tbyte 0x00 0.--23. 1. " CRC_WDTOPLD2 ,Channel 2 watchdog timeout counter preload" line.long 0x04 "CRC_BCTOPLD2,CRC Channel 2 Block Complete Timeout Preload Register" hexmask.long.tbyte 0x04 0.--23. 1. " CRC_BCTOPLD2 ,Channel 2 block complete timeout counter preload" group.long 0xA0++0x0F line.long 0x00 "PSA_SIGREGL2,Channel 2 PSA Signature Low Register" line.long 0x04 "PSA_SIGREGH2,Channel 2 PSA Signature High Register" line.long 0x08 "CRC_REGL2,Channel 2 CRC Value Low Register" line.long 0x0C "CRC_REGH2,Channel 2 CRC Value High Register" rgroup.long 0xB0++0x0F line.long 0x00 "PSA_SECSIGREGL2,Channel 2 PSA Sector Signature Low Register 2" line.long 0x04 "PSA_SECSIGREGH2,Channel 2 PSA Sector Signature High Register 2" line.long 0x08 "RAW_DATAREGL2,Channel 2 Raw Data Low Register 2" line.long 0x0C "RAW_DATAREGH2,Channel 2 Raw Data High Register 2" tree.end sif (cpu()!="TMS570PSFC61"&&cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!="RM46L852-PGE"&&cpu()!="RM46L852-ZWT"&&cpu()!="RM46L850-PGE"&&cpu()!="RM46L850-ZWT"&&cpu()!="RM46L840-ZWT"&&cpu()!="RM46L840-PGE"&&cpu()!="RM46L830-ZWT"&&cpu()!="RM46L830-PGE"&&cpu()!="RM46L450-ZWT"&&cpu()!="RM46L450-PGE"&&cpu()!="RM46L440-ZWT"&&cpu()!="RM46L440-PGE"&&cpu()!="RM46L430-ZWT"&&cpu()!="RM46L430-PGE"&&cpu()!="RM48L550-ZWT"&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&cpu()!=("TMS570LS3137-EP")) tree "Channel 3 Registers" group.long 0xC0++0x07 line.long 0x00 "CRC_PCOUNT_REG3,CRC Pattern Counter Preload Register 3" hexmask.long.tbyte 0x00 0.--19. 1. " CRC_PAT_COUNT3[19:0] ,Channel 3 pattern counter preload" line.long 0x04 "CRC_SCOUNT_REG3,CRC Sector Counter Preload Register 3" hexmask.long.word 0x04 0.--15. 1. " CRC_SEC_COUNT3[15:0] ,Channel 3 sector counter preload" hgroup.long 0xC8++0x03 hide.long 0x00 "CRC_CURSEC_REG3,CRC Current Sector Register 3" in group.long 0xCC++0x07 line.long 0x00 "CRC_WDTOPLD3,Watchdog Timeout Preload Register" hexmask.long.tbyte 0x00 0.--23. 1. " CRC_WDTOPLD3[23:0] ,Channel 3 watchdog timeout counter preload" line.long 0x04 "CRC_BCTOPLD3,CRC Channel 3 Block Complete Timeout Preload Register" hexmask.long.tbyte 0x04 0.--23. 1. " CRC_BCTOPLD3[23:0] ,Channel 3 block complete timeout counter preload" group.long 0xE0++0x0F line.long 0x00 "PSA_SIGREGL3,Channel 3 PSA Signature Low Register" line.long 0x04 "PSA_SIGREGH3,Channel 3 PSA Signature High Register" line.long 0x08 "CRC_REGL3,Channel 3 CRC Value Low Register" line.long 0x0C "CRC_REGH3,Channel 3 CRC Value High Register" rgroup.long 0xF0++0x0F line.long 0x00 "PSA_SECSIGREGL3,Channel 3 PSA Sector Signature Low Register 3" line.long 0x04 "PSA_SECSIGREGH3,Channel 3 PSA Sector Signature High Register 3" line.long 0x08 "RAW_DATAREGL3,Channel 3 Raw Data Low Register 3" line.long 0x0C "RAW_DATAREGH3,Channel 3 Raw Data High Register 3" tree.end tree "Channel 4 Registers" group.long 0x100++0x07 line.long 0x00 "CRC_PCOUNT_REG4,CRC Pattern Counter Preload Register 4" hexmask.long.tbyte 0x00 0.--19. 1. " CRC_PAT_COUNT4 ,Channel 4 pattern counter preload" line.long 0x04 "CRC_SCOUNT_REG4,CRC Sector Counter Preload Register 4" hexmask.long.word 0x04 0.--15. 1. " CRC_SEC_COUNT4 ,Channel 4 sector counter preload" hgroup.long 0x108++0x03 hide.long 0x00 "CRC_CURSEC_REG4,CRC Current Sector Register 4" in group.long 0x10C++0x07 line.long 0x00 "CRC_WDTOPLD4,Watchdog Timeout Preload Register" hexmask.long.tbyte 0x00 0.--23. 1. " CRC_WDTOPLD4[23:0] ,Channel 4 watchdog timeout counter preload" line.long 0x04 "CRC_BCTOPLD4,CRC Channel 4 Block Complete Timeout Preload Register" hexmask.long.tbyte 0x04 0.--23. 1. " CRC_BCTOPLD4[23:0] ,Channel 4 block complete timeout counter preload" group.long 0x120++0x0F line.long 0x00 "PSA_SIGREGL4,Channel 4 PSA Signature Low Register" line.long 0x04 "PSA_SIGREGH4,Channel 4 PSA Signature High Register" line.long 0x08 "CRC_REGL4,Channel 4 CRC Value Low Register" line.long 0x0C "CRC_REGH4,Channel 4 CRC Value High Register" rgroup.long 0x130++0x0F line.long 0x00 "PSA_SECSIGREGL4,Channel 4 PSA Sector Signature Low Register 4" line.long 0x04 "PSA_SECSIGREGH4,Channel 4 PSA Sector Signature High Register 4" line.long 0x08 "RAW_DATAREGL4,Channel 4 Raw Data Low Register 4" line.long 0x0C "RAW_DATAREGH4,Channel 4 Raw Data High Register 4" tree.end endif width 0x0B tree.end tree "DMA (Direct Memory Access)" base ad:0xFFFFF000 width 9. group.long 0x00++0x3 line.long 0x0 "GCTRL,GLOBAL CONTROL Register" bitfld.long 0x00 16. " DMA_EN ,DMA Enable" "Disabled,Enabled" bitfld.long 0x00 14. " BUS_BUSY ,DMA External AHB Bus Status" "Not busy,Busy" bitfld.long 0x00 8.--9. " DEBUG_MODE[1:0] ,Debug Mode" "Suspend ignored,Block finished,Frame finished,Immediate stop" textline " " bitfld.long 0x00 0. " DMA_RES ,DMA Software Reset" "No reset,Reset" width 9. rgroup.long 0x04++0x3 line.long 0x0 "PEND,CHANNEL PENDING Register" bitfld.long 0x00 28. " PEND28 ,Channel Pending 28 Register" "Inactive,Pending" bitfld.long 0x00 27. " PEND27 ,Channel Pending 27 Register" "Inactive,Pending" bitfld.long 0x00 26. " PEND26 ,Channel Pending 26 Register" "Inactive,Pending" bitfld.long 0x00 25. " PEND25 ,Channel Pending 25 Register" "Inactive,Pending" textline " " bitfld.long 0x00 24. " PEND24 ,Channel Pending 24 Register" "Inactive,Pending" bitfld.long 0x00 23. " PEND23 ,Channel Pending 23 Register" "Inactive,Pending" bitfld.long 0x00 22. " PEND22 ,Channel Pending 22 Register" "Inactive,Pending" bitfld.long 0x00 21. " PEND21 ,Channel Pending 21 Register" "Inactive,Pending" textline " " bitfld.long 0x00 20. " PEND20 ,Channel Pending 20 Register" "Inactive,Pending" bitfld.long 0x00 19. " PEND19 ,Channel Pending 19 Register" "Inactive,Pending" bitfld.long 0x00 18. " PEND18 ,Channel Pending 18 Register" "Inactive,Pending" bitfld.long 0x00 17. " PEND17 ,Channel Pending 17 Register" "Inactive,Pending" textline " " bitfld.long 0x00 16. " PEND16 ,Channel Pending 16 Register" "Inactive,Pending" bitfld.long 0x00 15. " PEND15 ,Channel Pending 15 Register" "Inactive,Pending" bitfld.long 0x00 14. " PEND14 ,Channel Pending 14 Register" "Inactive,Pending" bitfld.long 0x00 13. " PEND13 ,Channel Pending 13 Register" "Inactive,Pending" textline " " bitfld.long 0x00 12. " PEND12 ,Channel Pending 12 Register" "Inactive,Pending" bitfld.long 0x00 10. " PEND10 ,Channel Pending 10 Register" "Inactive,Pending" bitfld.long 0x00 9. " PEND9 ,Channel Pending 9 Register" "Inactive,Pending" bitfld.long 0x00 8. " PEND8 ,Channel Pending 8 Register" "Inactive,Pending" textline " " bitfld.long 0x00 7. " PEND7 ,Channel Pending 7 Register" "Inactive,Pending" bitfld.long 0x00 6. " PEND6 ,Channel Pending 6 Register" "Inactive,Pending" bitfld.long 0x00 5. " PEND5 ,Channel Pending 5 Register" "Inactive,Pending" bitfld.long 0x00 4. " PEND4 ,Channel Pending 4 Register" "Inactive,Pending" textline " " bitfld.long 0x00 3. " PEND3 ,Channel Pending 3 Register" "Inactive,Pending" bitfld.long 0x00 2. " PEND2 ,Channel Pending 2 Register" "Inactive,Pending" bitfld.long 0x00 1. " PEND1 ,Channel Pending 1 Register" "Inactive,Pending" bitfld.long 0x00 0. " PEND0 ,Channel Pending 0 Register" "Inactive,Pending" width 9. group.long 0x08++0x3 line.long 0x0 "FBREG,FALL BACK Register" bitfld.long 0x00 8.--11. " FSM_FB ,FSM Fallback Feature" "No effect,No effect,No effect,No effect,No effect,Enabled,Disabled,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect" bitfld.long 0x00 0.--3. " VBUSP_FB ,VBUSP Fallback Feature" "No effect,No effect,No effect,No effect,No effect,Enabled,No effect,No effect,No effect,No effect,Disabled,No effect,No effect,No effect,No effect,No effect" width 9. rgroup.long 0x0C++0x3 line.long 0x0 "DMASTAT,DMA STATUS Register" bitfld.long 0x00 28. " STCH28 ,Status of DMA Channel 28" "Inactive,Active" bitfld.long 0x00 27. " STCH27 ,Status of DMA Channel 27" "Inactive,Active" bitfld.long 0x00 26. " STCH26 ,Status of DMA Channel 26" "Inactive,Active" bitfld.long 0x00 25. " STCH25 ,Status of DMA Channel 25" "Inactive,Active" textline " " bitfld.long 0x00 24. " STCH24 ,Status of DMA Channel 24" "Inactive,Active" bitfld.long 0x00 23. " STCH23 ,Status of DMA Channel 23" "Inactive,Active" bitfld.long 0x00 22. " STCH22 ,Status of DMA Channel 22" "Inactive,Active" bitfld.long 0x00 21. " STCH21 ,Status of DMA Channel 21" "Inactive,Active" textline " " bitfld.long 0x00 20. " STCH20 ,Status of DMA Channel 20" "Inactive,Active" bitfld.long 0x00 19. " STCH19 ,Status of DMA Channel 19" "Inactive,Active" bitfld.long 0x00 18. " STCH18 ,Status of DMA Channel 18" "Inactive,Active" bitfld.long 0x00 17. " STCH17 ,Status of DMA Channel 17" "Inactive,Active" textline " " bitfld.long 0x00 16. " STCH16 ,Status of DMA Channel 16" "Inactive,Active" bitfld.long 0x00 15. " STCH15 ,Status of DMA Channel 15" "Inactive,Active" bitfld.long 0x00 14. " STCH14 ,Status of DMA Channel 14" "Inactive,Active" bitfld.long 0x00 13. " STCH13 ,Status of DMA Channel 13" "Inactive,Active" textline " " bitfld.long 0x00 12. " STCH12 ,Status of DMA Channel 12" "Inactive,Active" bitfld.long 0x00 10. " STCH10 ,Status of DMA Channel 10" "Inactive,Active" bitfld.long 0x00 9. " STCH9 ,Status of DMA Channel 9" "Inactive,Active" bitfld.long 0x00 8. " STCH8 ,Status of DMA Channel 8" "Inactive,Active" textline " " bitfld.long 0x00 7. " STCH7 ,Status of DMA Channel 7" "Inactive,Active" bitfld.long 0x00 6. " STCH6 ,Status of DMA Channel 6" "Inactive,Active" bitfld.long 0x00 5. " STCH5 ,Status of DMA Channel 5" "Inactive,Active" bitfld.long 0x00 4. " STCH4 ,Status of DMA Channel 4" "Inactive,Active" textline " " bitfld.long 0x00 3. " STCH3 ,Status of DMA Channel 3" "Inactive,Active" bitfld.long 0x00 2. " STCH2 ,Status of DMA Channel 2" "Inactive,Active" bitfld.long 0x00 1. " STCH1 ,Status of DMA Channel 1" "Inactive,Active" bitfld.long 0x00 0. " STCH0 ,Status of DMA Channel 0" "Inactive,Active" tree "Channel Enable Status Registers" width 10. group.long 0x14++0x3 line.long 0x0 "HWCHENAS,HWCHANNEL ENABLE SET and STATUS Register" bitfld.long 0x00 28. " HWCHENA28 ,HW Channel 28 Enable Status" "Disabled,Enabled" bitfld.long 0x00 27. " HWCHENA27 ,HW Channel 27 Enable Status" "Disabled,Enabled" bitfld.long 0x00 26. " HWCH26 ,HW Channel 26 Enable Status" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " HWCHENA25 ,HW Channel 25 Enable Status" "Disabled,Enabled" bitfld.long 0x00 24. " HWCHENA24 ,HW Channel 24 Enable Status" "Disabled,Enabled" bitfld.long 0x00 23. " HWCHENA23 ,HW Channel 23 Enable Status" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " HWCHENA22 ,HW Channel 22 Enable Status" "Disabled,Enabled" bitfld.long 0x00 21. " HWCHENA21 ,HW Channel 21 Enable Status" "Disabled,Enabled" bitfld.long 0x00 20. " HWCHENA20 ,HW Channel 20 Enable Status" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " HWCHENA19 ,HW Channel 19 Enable Status" "Disabled,Enabled" bitfld.long 0x00 18. " HWCHENA18 ,HW Channel 18 Enable Status" "Disabled,Enabled" bitfld.long 0x00 17. " HWCHENA17 ,HW Channel 17 Enable Status" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " HWCHENA16 ,HW Channel 16 Enable Status" "Disabled,Enabled" bitfld.long 0x00 15. " HWCHENA15 ,HW Channel 15 Enable Status" "Disabled,Enabled" bitfld.long 0x00 14. " HWCHENA14 ,HW Channel 14 Enable Status" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " HWCHENA13 ,HW Channel 13 Enable Status" "Disabled,Enabled" bitfld.long 0x00 12. " HWCHENA12 ,HW Channel 12 Enable Status" "Disabled,Enabled" bitfld.long 0x00 10. " HWCHENA10 ,HW Channel 10 Enable Status" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " HWCHENA9 ,HW Channel 9 Enable Status" "Disabled,Enabled" bitfld.long 0x00 8. " HWCHENA8 ,HW Channel 8 Enable Status" "Disabled,Enabled" bitfld.long 0x00 7. " HWCHENA7 ,HW Channel 7 Enable Status" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " HWCHENA6 ,HW Channel 6 Enable Status" "Disabled,Enabled" bitfld.long 0x00 5. " HWCHENA5 ,HW Channel 5 Enable Status" "Disabled,Enabled" bitfld.long 0x00 4. " HWCHENA4 ,HW Channel 4 Enable Status" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " HWCHENA3 ,HW Channel 3 Enable Status" "Disabled,Enabled" bitfld.long 0x00 2. " HWCHENA2 ,HW Channel 2 Enable Status" "Disabled,Enabled" bitfld.long 0x00 1. " HWCHENA1 ,HW Channel 1 Enable Status" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " HWCHENA0 ,HW Channel 0 Enable Status" "Disabled,Enabled" width 10. group.long 0x1C++0x3 line.long 0x0 "HWCHENAR,HWCHANNEL ENABLE RESET and STATUS Register" bitfld.long 0x00 28. " HWCHDIS28 ,HW Channel 28 Disable" "No effect,Reset" bitfld.long 0x00 27. " HWCHDIS27 ,HW Channel 27 Disable" "No effect,Reset" bitfld.long 0x00 26. " HWCHDIS26 ,HW Channel 26 Disable" "No effect,Reset" textline " " bitfld.long 0x00 25. " HWCHDIS25 ,HW Channel 25 Disable" "No effect,Reset" bitfld.long 0x00 24. " HWCHDIS24 ,HW Channel 24 Disable" "No effect,Reset" bitfld.long 0x00 23. " HWCHDIS23 ,HW Channel 23 Disable" "No effect,Reset" textline " " bitfld.long 0x00 22. " HWCHDIS22 ,HW Channel 22 Disable" "No effect,Reset" bitfld.long 0x00 21. " HWCHDIS21 ,HW Channel 21 Disable" "No effect,Reset" bitfld.long 0x00 20. " HWCHDIS20 ,HW Channel 20 Disable" "No effect,Reset" textline " " bitfld.long 0x00 19. " HWCHDIS19 ,HW Channel 19 Disable" "No effect,Reset" bitfld.long 0x00 18. " HWCHDIS18 ,HW Channel 18 Disable" "No effect,Reset" bitfld.long 0x00 17. " HWCHDIS17 ,HW Channel 17 Disable" "No effect,Reset" textline " " bitfld.long 0x00 16. " HWCHDIS16 ,HW Channel 16 Disable" "No effect,Reset" bitfld.long 0x00 15. " HWCHDIS15 ,HW Channel 15 Disable" "No effect,Reset" bitfld.long 0x00 14. " HWCHDIS14 ,HW Channel 14 Disable" "No effect,Reset" textline " " bitfld.long 0x00 13. " HWCHDIS13 ,HW Channel 13 Disable" "No effect,Reset" bitfld.long 0x00 12. " HWCHDIS12 ,HW Channel 12 Disable" "No effect,Reset" bitfld.long 0x00 10. " HWCHDIS10 ,HW Channel 10 Disable" "No effect,Reset" textline " " bitfld.long 0x00 9. " HWCHDIS9 ,HW Channel 9 Disable" "No effect,Reset" bitfld.long 0x00 8. " HWCHDIS8 ,HW Channel 8 Disable" "No effect,Reset" bitfld.long 0x00 7. " HWCHDIS7 ,HW Channel 7 Disable" "No effect,Reset" textline " " bitfld.long 0x00 6. " HWCHDIS6 ,HW Channel 6 Disable" "No effect,Reset" bitfld.long 0x00 5. " HWCHDIS5 ,HW Channel 5 Disable" "No effect,Reset" bitfld.long 0x00 4. " HWCHDIS4 ,HW Channel 4 Disable" "No effect,Reset" textline " " bitfld.long 0x00 3. " HWCHDIS3 ,HW Channel 3 Disable" "No effect,Reset" bitfld.long 0x00 2. " HWCHDIS2 ,HW Channel 2 Disable" "No effect,Reset" bitfld.long 0x00 1. " HWCHDIS1 ,HW Channel 1 Disable" "No effect,Reset" textline " " bitfld.long 0x00 0. " HWCHDIS0 ,HW Channel 0 Disable" "No effect,Reset" width 10. group.long 0x24++0x3 line.long 0x0 "SWCHENAS,SWCHANNEL ENABLE SET and STATUS Register" bitfld.long 0x00 28. " SWCHENA28 ,SW Channel 28 Enable Status" "Not triggered,Triggered" bitfld.long 0x00 27. " SWCHENA27 ,SW Channel 27 Enable Status" "Not triggered,Triggered" textline " " bitfld.long 0x00 26. " SWCHENA26 ,SW Channel 26 Enable Status" "Not triggered,Triggered" bitfld.long 0x00 25. " SWCHENA25 ,SW Channel 25 Enable Status" "Not triggered,Triggered" textline " " bitfld.long 0x00 24. " SWCHENA24 ,SW Channel 24 Enable Status" "Not triggered,Triggered" bitfld.long 0x00 23. " SWCHENA23 ,SW Channel 23 Enable Status" "Not triggered,Triggered" textline " " bitfld.long 0x00 22. " SWCHENA22 ,SW Channel 22 Enable Status" "Not triggered,Triggered" bitfld.long 0x00 21. " SWCHENA21 ,SW Channel 21 Enable Status" "Not triggered,Triggered" textline " " bitfld.long 0x00 20. " SWCHENA20 ,SW Channel 20 Enable Status" "Not triggered,Triggered" bitfld.long 0x00 19. " SWCHENA19 ,SW Channel 19 Enable Status" "Not triggered,Triggered" textline " " bitfld.long 0x00 18. " SWCHENA18 ,SW Channel 18 Enable Status" "Not triggered,Triggered" bitfld.long 0x00 17. " SWCHENA17 ,SW Channel 17 Enable Status" "Not triggered,Triggered" textline " " bitfld.long 0x00 16. " SWCHENA16 ,SW Channel 16 Enable Status" "Not triggered,Triggered" bitfld.long 0x00 15. " SWCHENA15 ,SW Channel 15 Enable Status" "Not triggered,Triggered" textline " " bitfld.long 0x00 14. " SWCHENA14 ,SW Channel 14 Enable Status" "Not triggered,Triggered" bitfld.long 0x00 13. " SWCHENA13 ,SW Channel 13 Enable Status" "Not triggered,Triggered" textline " " bitfld.long 0x00 12. " SWCHENA12 ,SW Channel 12 Enable Status" "Not triggered,Triggered" bitfld.long 0x00 10. " SWCHENA10 ,SW Channel 10 Enable Status" "Not triggered,Triggered" textline " " bitfld.long 0x00 9. " SWCHENA9 ,SW Channel 9 Enable Status" "Not triggered,Triggered" bitfld.long 0x00 8. " SWCHENA8 ,SW Channel 8 Enable Status" "Not triggered,Triggered" textline " " bitfld.long 0x00 7. " SWCHENA7 ,SW Channel 7 Enable Status" "Not triggered,Triggered" bitfld.long 0x00 6. " SWCHENA6 ,SW Channel 6 Enable Status" "Not triggered,Triggered" textline " " bitfld.long 0x00 5. " SWCHENA5 ,SW Channel 5 Enable Status" "Not triggered,Triggered" bitfld.long 0x00 4. " SWCHENA4 ,SW Channel 4 Enable Status" "Not triggered,Triggered" textline " " bitfld.long 0x00 3. " SWCHENA3 ,SW Channel 3 Enable Status" "Not triggered,Triggered" bitfld.long 0x00 2. " SWCHENA2 ,SW Channel 2 Enable Status" "Not triggered,Triggered" textline " " bitfld.long 0x00 1. " SWCHENA1 ,SW Channel 1 Enable Status" "Not triggered,Triggered" bitfld.long 0x00 0. " SWCHENA0 ,SW Channel 0 Enable Status" "Not triggered,Triggered" width 10. group.long 0x2c++0x3 line.long 0x0 "SWCHENAR,SWCHANNEL ENABLE RESET and STATUS Register" bitfld.long 0x00 28. " SWCHDIS28 ,SW Channel 28 Disable" "No effect,Reset" bitfld.long 0x00 27. " SWCHDIS27 ,SW Channel 27 Disable" "No effect,Reset" bitfld.long 0x00 26. " SWCHDIS26 ,SW Channel 26 Disable" "No effect,Reset" textline " " bitfld.long 0x00 25. " SWCHDIS25 ,SW Channel 25 Disable" "No effect,Reset" bitfld.long 0x00 24. " SWCHDIS24 ,SW Channel 24 Disable" "No effect,Reset" bitfld.long 0x00 23. " SWCHDIS23 ,SW Channel 23 Disable" "No effect,Reset" textline " " bitfld.long 0x00 22. " SWCHDIS22 ,SW Channel 22 Disable" "No effect,Reset" bitfld.long 0x00 21. " SWCHDIS21 ,SW Channel 21 Disable" "No effect,Reset" bitfld.long 0x00 20. " SWCHDIS20 ,SW Channel 20 Disable" "No effect,Reset" textline " " bitfld.long 0x00 19. " SWCHDIS19 ,SW Channel 19 Disable" "No effect,Reset" bitfld.long 0x00 18. " SWCHDIS18 ,SW Channel 18 Disable" "No effect,Reset" bitfld.long 0x00 17. " SWCHDIS17 ,SW Channel 17 Disable" "No effect,Reset" textline " " bitfld.long 0x00 16. " SWCHDIS16 ,SW Channel 16 Disable" "No effect,Reset" bitfld.long 0x00 15. " SWCHDIS15 ,SW Channel 15 Disable" "No effect,Reset" bitfld.long 0x00 14. " SWCHDIS14 ,SW Channel 14 Disable" "No effect,Reset" textline " " bitfld.long 0x00 13. " SWCHDIS13 ,SW Channel 13 Disable" "No effect,Reset" bitfld.long 0x00 12. " SWCHDIS12 ,SW Channel 12 Disable" "No effect,Reset" bitfld.long 0x00 10. " SWCHDIS10 ,SW Channel 10 Disable" "No effect,Reset" textline " " bitfld.long 0x00 9. " SWCHDIS9 ,SW Channel 9 Disable" "No effect,Reset" bitfld.long 0x00 8. " SWCHDIS8 ,SW Channel 8 Disable" "No effect,Reset" bitfld.long 0x00 7. " SWCHDIS7 ,SW Channel 7 Disable" "No effect,Reset" textline " " bitfld.long 0x00 6. " SWCHDIS6 ,SW Channel 6 Disable" "No effect,Reset" bitfld.long 0x00 5. " SWCHDIS5 ,SW Channel 5 Disable" "No effect,Reset" bitfld.long 0x00 4. " SWCHDIS4 ,SW Channel 4 Disable" "No effect,Reset" textline " " bitfld.long 0x00 3. " SWCHDIS3 ,SW Channel 3 Disable" "No effect,Reset" bitfld.long 0x00 2. " SWCHDIS2 ,SW Channel 2 Disable" "No effect,Reset" bitfld.long 0x00 1. " SWCHDIS1 ,SW Channel 1 Disable" "No effect,Reset" textline " " bitfld.long 0x00 0. " SWCHDIS0 ,SW Channel 0 Disable" "No effect,Reset" tree.end textline " " width 10. group.long 0x34++0x3 line.long 0x0 "CHPRIOS,CHANNEL PRIORITY SET Register" bitfld.long 0x00 28. " CPS28 ,Channel Priority 28 Set" "Low,High" bitfld.long 0x00 27. " CPS27 ,Channel Priority 27 Set" "Low,High" bitfld.long 0x00 26. " CPS26 ,Channel Priority 26 Set" "Low,High" bitfld.long 0x00 25. " CPS25 ,Channel Priority 25 Set" "Low,High" bitfld.long 0x00 24. " CPS24 ,Channel Priority 24 Set" "Low,High" bitfld.long 0x00 23. " CPS23 ,Channel Priority 23 Set" "Low,High" textline " " bitfld.long 0x00 22. " CPS22 ,Channel Priority 22 Set" "Low,High" bitfld.long 0x00 21. " CPS21 ,Channel Priority 21 Set" "Low,High" bitfld.long 0x00 20. " CPS20 ,Channel Priority 20 Set" "Low,High" bitfld.long 0x00 19. " CPS19 ,Channel Priority 19 Set" "Low,High" bitfld.long 0x00 18. " CPS18 ,Channel Priority 18 Set" "Low,High" bitfld.long 0x00 17. " CPS17 ,Channel Priority 17 Set" "Low,High" textline " " bitfld.long 0x00 16. " CPS16 ,Channel Priority 16 Set" "Low,High" bitfld.long 0x00 15. " CPS15 ,Channel Priority 15 Set" "Low,High" bitfld.long 0x00 14. " CPS14 ,Channel Priority 14 Set" "Low,High" bitfld.long 0x00 13. " CPS13 ,Channel Priority 13 Set" "Low,High" bitfld.long 0x00 12. " CPS12 ,Channel Priority 12 Set" "Low,High" bitfld.long 0x00 10. " CPS10 ,Channel Priority 10 Set" "Low,High" textline " " bitfld.long 0x00 9. " CPS9 ,Channel Priority 9 Set" "Low,High" bitfld.long 0x00 8. " CPS8 ,Channel Priority 8 Set" "Low,High" bitfld.long 0x00 7. " CPS7 ,Channel Priority 7 Set" "Low,High" bitfld.long 0x00 6. " CPS6 ,Channel Priority 6 Set" "Low,High" bitfld.long 0x00 5. " CPS5 ,Channel Priority 5 Set" "Low,High" bitfld.long 0x00 4. " CPS4 ,Channel Priority 4 Set" "Low,High" textline " " bitfld.long 0x00 3. " CPS3 ,Channel Priority 3 Set" "Low,High" bitfld.long 0x00 2. " CPS2 ,Channel Priority 2 Set" "Low,High" bitfld.long 0x00 1. " CPS1 ,Channel Priority 1 Set" "Low,High" bitfld.long 0x00 0. " CPS0 ,Channel Priority 0 Set" "Low,High" width 10. group.long 0x3C++0x3 line.long 0x0 "CHPRIOR,CHANNEL PRIORITY RESET" bitfld.long 0x00 28. " CPR28 ,Channel Priority 28" "No effect,Reset" bitfld.long 0x00 27. " CPR27 ,Channel Priority 27" "No effect,Reset" bitfld.long 0x00 26. " CPR26 ,Channel Priority 26" "No effect,Reset" bitfld.long 0x00 25. " CPR25 ,Channel Priority 25" "No effect,Reset" textline " " bitfld.long 0x00 24. " CPR24 ,Channel Priority 24" "No effect,Reset" bitfld.long 0x00 23. " CPR23 ,Channel Priority 23" "No effect,Reset" bitfld.long 0x00 22. " CPR22 ,Channel Priority 22" "No effect,Reset" bitfld.long 0x00 21. " CPR21 ,Channel Priority 21" "No effect,Reset" textline " " bitfld.long 0x00 20. " CPR20 ,Channel Priority 20" "No effect,Reset" bitfld.long 0x00 19. " CPR19 ,Channel Priority 19" "No effect,Reset" bitfld.long 0x00 18. " CPR18 ,Channel Priority 18" "No effect,Reset" bitfld.long 0x00 17. " CPR17 ,Channel Priority 17" "No effect,Reset" textline " " bitfld.long 0x00 16. " CPR16 ,Channel Priority 16" "No effect,Reset" bitfld.long 0x00 15. " CPR15 ,Channel Priority 15" "No effect,Reset" bitfld.long 0x00 14. " CPR14 ,Channel Priority 14" "No effect,Reset" bitfld.long 0x00 13. " CPR13 ,Channel Priority 13" "No effect,Reset" textline " " bitfld.long 0x00 12. " CPR12 ,Channel Priority 12" "No effect,Reset" bitfld.long 0x00 10. " CPR10 ,Channel Priority 10" "No effect,Reset" bitfld.long 0x00 9. " CPR9 ,Channel Priority 9" "No effect,Reset" bitfld.long 0x00 8. " CPR8 ,Channel Priority 8" "No effect,Reset" textline " " bitfld.long 0x00 7. " CPR7 ,Channel Priority 7" "No effect,Reset" bitfld.long 0x00 6. " CPR6 ,Channel Priority 6" "No effect,Reset" bitfld.long 0x00 5. " CPR5 ,Channel Priority 5" "No effect,Reset" bitfld.long 0x00 4. " CPR4 ,Channel Priority 4" "No effect,Reset" textline " " bitfld.long 0x00 3. " CPR3 ,Channel Priority 3" "No effect,Reset" bitfld.long 0x00 2. " CPR2 ,Channel Priority 2" "No effect,Reset" bitfld.long 0x00 1. " CPR1 ,Channel Priority 1" "No effect,Reset" bitfld.long 0x00 0. " CPR0 ,Channel Priority 0" "No effect,Reset" width 10. group.long 0x44++0x3 line.long 0x0 "GCHIENAS,GLOBAL CHANNEL INTERRUPT ENABLE SET" bitfld.long 0x00 28. " GCHIE28 ,Global Channel Interrupt Enable 28" "Disabled,Enabled" bitfld.long 0x00 27. " GCHIE27 ,Global Channel Interrupt Enable 27" "Disabled,Enabled" bitfld.long 0x00 26. " GCHIE26 ,Global Channel Interrupt Enable 26" "Disabled,Enabled" bitfld.long 0x00 25. " GCHIE25 ,Global Channel Interrupt Enable 25" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " GCHIE24 ,Global Channel Interrupt Enable 24" "Disabled,Enabled" bitfld.long 0x00 23. " GCHIE23 ,Global Channel Interrupt Enable 23" "Disabled,Enabled" bitfld.long 0x00 22. " GCHIE22 ,Global Channel Interrupt Enable 22" "Disabled,Enabled" bitfld.long 0x00 21. " GCHIE21 ,Global Channel Interrupt Enable 21" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " GCHIE20 ,Global Channel Interrupt Enable 20" "Disabled,Enabled" bitfld.long 0x00 19. " GCHIE19 ,Global Channel Interrupt Enable 19" "Disabled,Enabled" bitfld.long 0x00 18. " GCHIE18 ,Global Channel Interrupt Enable 18" "Disabled,Enabled" bitfld.long 0x00 17. " GCHIE17 ,Global Channel Interrupt Enable 17" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " GCHIE16 ,Global Channel Interrupt Enable 16" "Disabled,Enabled" bitfld.long 0x00 15. " GCHIE15 ,Global Channel Interrupt Enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " GCHIE14 ,Global Channel Interrupt Enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " GCHIE13 ,Global Channel Interrupt Enable 13" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " GCHIE12 ,Global Channel Interrupt Enable 12" "Disabled,Enabled" bitfld.long 0x00 10. " GCHIE10 ,Global Channel Interrupt Enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " GCHIE9 ,Global Channel Interrupt Enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " GCHIE8 ,Global Channel Interrupt Enable 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " GCHIE7 ,Global Channel Interrupt Enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " GCHIE6 ,Global Channel Interrupt Enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " GCHIE5 ,Global Channel Interrupt Enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " GCHIE4 ,Global Channel Interrupt Enable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " GCHIE3 ,Global Channel Interrupt Enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " GCHIE2 ,Global Channel Interrupt Enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " GCHIE1 ,Global Channel Interrupt Enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " GCHIE0 ,Global Channel Interrupt Enable 0" "Disabled,Enabled" width 10. group.long 0x4C++0x3 line.long 0x0 "GCHIENAR,GLOBAL CHANNEL INTERRUPT ENABLE RESET" bitfld.long 0x00 28. " GCHID28 ,Global Channel Interrupt Disable 28" "No effect,Reset" bitfld.long 0x00 27. " GCHID27 ,Global Channel Interrupt Disable 27" "No effect,Reset" bitfld.long 0x00 26. " GCHID26 ,Global Channel Interrupt Disable 26" "No effect,Reset" textline " " bitfld.long 0x00 25. " GCHID25 ,Global Channel Interrupt Disable 25" "No effect,Reset" bitfld.long 0x00 24. " GCHID24 ,Global Channel Interrupt Disable 24" "No effect,Reset" bitfld.long 0x00 23. " GCHID23 ,Global Channel Interrupt Disable 23" "No effect,Reset" textline " " bitfld.long 0x00 22. " GCHID22 ,Global Channel Interrupt Disable 22" "No effect,Reset" bitfld.long 0x00 21. " GCHID21 ,Global Channel Interrupt Disable 21" "No effect,Reset" bitfld.long 0x00 20. " GCHID20 ,Global Channel Interrupt Disable 20" "No effect,Reset" textline " " bitfld.long 0x00 19. " GCHID19 ,Global Channel Interrupt Disable 19" "No effect,Reset" bitfld.long 0x00 18. " GCHID18 ,Global Channel Interrupt Disable 18" "No effect,Reset" bitfld.long 0x00 17. " GCHID17 ,Global Channel Interrupt Disable 17" "No effect,Reset" textline " " bitfld.long 0x00 16. " GCHID16 ,Global Channel Interrupt Disable 16" "No effect,Reset" bitfld.long 0x00 15. " GCHID15 ,Global Channel Interrupt Disable 15" "No effect,Reset" bitfld.long 0x00 14. " GCHID14 ,Global Channel Interrupt Disable 14" "No effect,Reset" textline " " bitfld.long 0x00 13. " GCHID13 ,Global Channel Interrupt Disable 13" "No effect,Reset" bitfld.long 0x00 12. " GCHID12 ,Global Channel Interrupt Disable 12" "No effect,Reset" bitfld.long 0x00 10. " GCHID10 ,Global Channel Interrupt Disable 10" "No effect,Reset" textline " " bitfld.long 0x00 9. " GCHID9 ,Global Channel Interrupt Disable 9" "No effect,Reset" bitfld.long 0x00 8. " GCHID8 ,Global Channel Interrupt Disable 8" "No effect,Reset" bitfld.long 0x00 7. " GCHID7 ,Global Channel Interrupt Disable 7" "No effect,Reset" textline " " bitfld.long 0x00 6. " GCHID6 ,Global Channel Interrupt Disable 6" "No effect,Reset" bitfld.long 0x00 5. " GCHID5 ,Global Channel Interrupt Disable 5" "No effect,Reset" bitfld.long 0x00 4. " GCHID4 ,Global Channel Interrupt Disable 4" "No effect,Reset" textline " " bitfld.long 0x00 3. " GCHID3 ,Global Channel Interrupt Disable 3" "No effect,Reset" bitfld.long 0x00 2. " GCHID2 ,Global Channel Interrupt Disable 2" "No effect,Reset" bitfld.long 0x00 1. " GCHID1 ,Global Channel Interrupt Disable 1" "No effect,Reset" textline " " bitfld.long 0x00 0. " GCHID0 ,Global Channel Interrupt Disable 0" "No effect,Reset" width 10. tree "DMA Request Assignment Registers" group.long 0x54++0x3 line.long 0x0 "DREQASI0,DMA REQUEST ASSIGNMENT Register 0" bitfld.long 0x00 24.--29. " CH0ASI ,Channel 0 Assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63" bitfld.long 0x00 16.--21. " CH1ASI ,Channel 1 Assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63" bitfld.long 0x00 8.--13. " CH2ASI ,Channel 2 Assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63" bitfld.long 0x00 0.--5. " CH3ASI ,Channel 3 Assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63" group.long 0x58++0x3 line.long 0x0 "DREQASI1,DMA REQUEST ASSIGNMENT Register 1" bitfld.long 0x00 24.--29. " CH04SI ,Channel 4 Assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63" bitfld.long 0x00 16.--21. " CH5ASI ,Channel 5 Assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63" bitfld.long 0x00 8.--13. " CH6ASI ,Channel 6 Assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63" bitfld.long 0x00 0.--5. " CH7ASI ,Channel 7 Assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63" group.long 0x5C++0x3 line.long 0x0 "DREQASI2,DMA REQUEST ASSIGNMENT Register 2" bitfld.long 0x00 24.--29. " CH8ASI ,Channel 8 Assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63" bitfld.long 0x00 16.--21. " CH9ASI ,Channel 9 Assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63" bitfld.long 0x00 8.--13. " CH10ASI ,Channel 10 Assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63" group.long 0x60++0x3 line.long 0x0 "DREQASI3,DMA REQUEST ASSIGNMENT Register 3" bitfld.long 0x00 24.--29. " CH12ASI ,Channel 12 Assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63" bitfld.long 0x00 16.--21. " CH13ASI ,Channel 13 Assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63" bitfld.long 0x00 8.--13. " CH14ASI ,Channel 14 Assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63" bitfld.long 0x00 0.--5. " CH15ASI ,Channel 15 Assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63" group.long 0x64++0x3 line.long 0x0 "DREQASI4,DMA REQUEST ASSIGNMENT Register 4" bitfld.long 0x00 24.--29. " CH16ASI ,Channel 16 Assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63" bitfld.long 0x00 16.--21. " CH17ASI ,Channel 17 Assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63" bitfld.long 0x00 8.--13. " CH18ASI ,Channel 18 Assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63" bitfld.long 0x00 0.--5. " CH19ASI ,Channel 19 Assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63" group.long 0x68++0x3 line.long 0x0 "DREQASI5,DMA REQUEST ASSIGNMENT Register 5" bitfld.long 0x00 24.--29. " CH20ASI ,Channel 20 Assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63" bitfld.long 0x00 16.--21. " CH21ASI ,Channel 21 Assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63" bitfld.long 0x00 8.--13. " CH22ASI ,Channel 22 Assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63" bitfld.long 0x00 0.--5. " CH23ASI ,Channel 23 Assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63" group.long 0x6C++0x3 line.long 0x0 "DREQASI6,DMA REQUEST ASSIGNMENT Register 6" bitfld.long 0x00 24.--29. " CH24ASI ,Channel 24 Assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63" bitfld.long 0x00 16.--21. " CH25ASI ,Channel 25 Assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63" bitfld.long 0x00 8.--13. " CH26ASI ,Channel 26 Assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63" bitfld.long 0x00 0.--5. " CH27ASI ,Channel 27 Assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63" group.long 0x70++0x3 line.long 0x0 "DREQASI7,DMA REQUEST ASSIGNMENT Register 7" bitfld.long 0x00 24.--29. " CH28ASI ,Channel 28 Assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63" tree.end width 6. tree "Port Assignment Registers" group.long 0x94++0x3 line.long 0x0 "PAR0,PORT Assignment Register 0" bitfld.long 0x00 28.--30. " CH0PA ,Port Channel 0 Assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B" bitfld.long 0x00 24.--26. " CH1PA ,Port Channel 1 Assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B" bitfld.long 0x00 20.--22. " CH2PA ,Port Channel 2 Assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B" textline " " bitfld.long 0x00 16.--18. " CH3PA ,Port Channel 3 Assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B" bitfld.long 0x00 12.--14. " CH4PA ,Port Channel 4 Assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B" bitfld.long 0x00 8.--10. " CH5PA ,Port Channel 5 Assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B" textline " " bitfld.long 0x00 4.--6. " CH6PA ,Port Channel 6 Assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B" bitfld.long 0x00 0.--2. " CH7PA ,Port Channel 7 Assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B" group.long 0x98++0x3 line.long 0x0 "PAR1,PORT Assignment Register 1" bitfld.long 0x00 28.--30. " CH8PA ,Port Channel 8 Assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B" bitfld.long 0x00 24.--26. " CH9PA ,Port Channel 9 Assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B" bitfld.long 0x00 20.--22. " CH10PA ,Port Channel 10 Assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B" textline " " bitfld.long 0x00 12.--14. " CH12PA ,Port Channel 12 Assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B" bitfld.long 0x00 8.--10. " CH13PA ,Port Channel 13 Assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B" bitfld.long 0x00 4.--6. " CH14PA ,Port Channel 14 Assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B" textline " " bitfld.long 0x00 0.--2. " CH15PA ,Port Channel 15 Assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B" group.long 0x9C++0x3 line.long 0x0 "PAR2,PORT Assignment Register 2" bitfld.long 0x00 28.--30. " CH16PA ,Port Channel 16 Assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B" bitfld.long 0x00 24.--26. " CH17PA ,Port Channel 17 Assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B" bitfld.long 0x00 20.--22. " CH18PA ,Port Channel 18 Assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B" textline " " bitfld.long 0x00 16.--18. " CH19PA ,Port Channel 19 Assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B" bitfld.long 0x00 12.--14. " CH20PA ,Port Channel 20 Assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B" bitfld.long 0x00 8.--10. " CH21PA ,Port Channel 21 Assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B" textline " " bitfld.long 0x00 4.--6. " CH22PA ,Port Channel 22 Assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B" bitfld.long 0x00 0.--2. " CH23PA ,Port Channel 23 Assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B" group.long 0xA0++0x3 line.long 0x0 "PAR3,PORT Assignment Register 3" bitfld.long 0x00 28.--30. " CH24PA ,Port Channel 24 Assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B" bitfld.long 0x00 24.--26. " CH25PA ,Port Channel 25 Assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B" bitfld.long 0x00 20.--22. " CH26PA ,Port Channel 26 Assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B" textline " " bitfld.long 0x00 16.--18. " CH27PA ,Port Channel 27 Assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B" bitfld.long 0x00 12.--14. " CH28PA ,Port Channel 28 Assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B" tree.end width 8. tree "Interrupt Mapping Registers" group.long 0xB4++0x3 line.long 0x0 "FTCMAP,FTC INTERRUPT MAPPING Register" bitfld.long 0x00 28. " FTCAB28 ,Frame Transfer Complete Interrupt of Channel 28 to group A/B" "A,B" bitfld.long 0x00 27. " FTCAB27 ,Frame Transfer Complete Interrupt of Channel 27 to group A/B" "A,B" bitfld.long 0x00 26. " FTCAB26 ,Frame Transfer Complete Interrupt of Channel 26 to group A/B" "A,B" bitfld.long 0x00 25. " FTCAB25 ,Frame Transfer Complete Interrupt of Channel 25 to group A/B" "A,B" bitfld.long 0x00 24. " FTCAB24 ,Frame Transfer Complete Interrupt of Channel 24 to group A/B" "A,B" bitfld.long 0x00 23. " FTCAB23 ,Frame Transfer Complete Interrupt of Channel 23 to group A/B" "A,B" textline " " bitfld.long 0x00 22. " FTCAB22 ,Frame Transfer Complete Interrupt of Channel 22 to group A/B" "A,B" bitfld.long 0x00 21. " FTCAB21 ,Frame Transfer Complete Interrupt of Channel 21 to group A/B" "A,B" bitfld.long 0x00 20. " FTCAB20 ,Frame Transfer Complete Interrupt of Channel 20 to group A/B" "A,B" bitfld.long 0x00 19. " FTCAB19 ,Frame Transfer Complete Interrupt of Channel 19 to group A/B" "A,B" bitfld.long 0x00 18. " FTCAB18 ,Frame Transfer Complete Interrupt of Channel 18 to group A/B" "A,B" bitfld.long 0x00 17. " FTCAB17 ,Frame Transfer Complete Interrupt of Channel 17 to group A/B" "A,B" textline " " bitfld.long 0x00 16. " FTCAB16 ,Frame Transfer Complete Interrupt of Channel 16 to group A/B" "A,B" bitfld.long 0x00 15. " FTCAB15 ,Frame Transfer Complete Interrupt of Channel 15 to group A/B" "A,B" bitfld.long 0x00 14. " FTCAB14 ,Frame Transfer Complete Interrupt of Channel 14 to group A/B" "A,B" bitfld.long 0x00 13. " FTCAB13 ,Frame Transfer Complete Interrupt of Channel 13 to group A/B" "A,B" bitfld.long 0x00 12. " FTCAB12 ,Frame Transfer Complete Interrupt of Channel 12 to group A/B" "A,B" bitfld.long 0x00 10. " FTCAB10 ,Frame Transfer Complete Interrupt of Channel 10 to group A/B" "A,B" textline " " bitfld.long 0x00 9. " FTCAB9 ,Frame Transfer Complete Interrupt of Channel 9 to group A/B" "A,B" bitfld.long 0x00 8. " FTCAB8 ,Frame Transfer Complete Interrupt of Channel 8 to group A/B" "A,B" bitfld.long 0x00 7. " FTCAB7 ,Frame Transfer Complete Interrupt of Channel 7 to group A/B" "A,B" bitfld.long 0x00 6. " FTCAB6 ,Frame Transfer Complete Interrupt of Channel 6 to group A/B" "A,B" bitfld.long 0x00 5. " FTCAB5 ,Frame Transfer Complete Interrupt of Channel 5 to group A/B" "A,B" bitfld.long 0x00 4. " FTCAB4 ,Frame Transfer Complete Interrupt of Channel 4 to group A/B" "A,B" textline " " bitfld.long 0x00 3. " FTCAB3 ,Frame Transfer Complete Interrupt of Channel 3 to group A/B" "A,B" bitfld.long 0x00 2. " FTCAB2 ,Frame Transfer Complete Interrupt of Channel 2 to group A/B" "A,B" bitfld.long 0x00 1. " FTCAB1 ,Frame Transfer Complete Interrupt of Channel 1 to group A/B" "A,B" bitfld.long 0x00 0. " FTCAB0 ,Frame Transfer Complete Interrupt of Channel 0 to group A/B" "A,B" group.long 0xBC++0x3 line.long 0x0 "LFSMAP,LFS INTERRUPT MAPPING Register" bitfld.long 0x00 28. " LFSAB28 ,Last Frame Started Interrupt of Channel 28 to group A/B" "A,B" bitfld.long 0x00 27. " LFSAB27 ,Last Frame Started Interrupt of Channel 27 to group A/B" "A,B" bitfld.long 0x00 26. " LFSAB26 ,Last Frame Started Interrupt of Channel 26 to group A/B" "A,B" bitfld.long 0x00 25. " LFSAB25 ,Last Frame Started Interrupt of Channel 25 to group A/B" "A,B" bitfld.long 0x00 24. " LFSAB24 ,Last Frame Started Interrupt of Channel 24 to group A/B" "A,B" bitfld.long 0x00 23. " LFSAB23 ,Last Frame Started Interrupt of Channel 23 to group A/B" "A,B" textline " " bitfld.long 0x00 22. " LFSAB22 ,Last Frame Started Interrupt of Channel 22 to group A/B" "A,B" bitfld.long 0x00 21. " LFSAB21 ,Last Frame Started Interrupt of Channel 21 to group A/B" "A,B" bitfld.long 0x00 20. " LFSAB20 ,Last Frame Started Interrupt of Channel 20 to group A/B" "A,B" bitfld.long 0x00 19. " LFSAB19 ,Last Frame Started Interrupt of Channel 19 to group A/B" "A,B" bitfld.long 0x00 18. " LFSAB18 ,Last Frame Started Interrupt of Channel 18 to group A/B" "A,B" bitfld.long 0x00 17. " LFSAB17 ,Last Frame Started Interrupt of Channel 17 to group A/B" "A,B" textline " " bitfld.long 0x00 16. " LFSAB16 ,Last Frame Started Interrupt of Channel 16 to group A/B" "A,B" bitfld.long 0x00 15. " LFSAB15 ,Last Frame Started Interrupt of Channel 15 to group A/B" "A,B" bitfld.long 0x00 14. " LFSAB14 ,Last Frame Started Interrupt of Channel 14 to group A/B" "A,B" bitfld.long 0x00 13. " LFSAB13 ,Last Frame Started Interrupt of Channel 13 to group A/B" "A,B" bitfld.long 0x00 12. " LFSAB12 ,Last Frame Started Interrupt of Channel 12 to group A/B" "A,B" bitfld.long 0x00 10. " LFSAB10 ,Last Frame Started Interrupt of Channel 10 to group A/B" "A,B" textline " " bitfld.long 0x00 9. " LFSAB9 ,Last Frame Started Interrupt of Channel 9 to group A/B" "A,B" bitfld.long 0x00 8. " LFSAB8 ,Last Frame Started Interrupt of Channel 8 to group A/B" "A,B" bitfld.long 0x00 7. " LFSAB7 ,Last Frame Started Interrupt of Channel 7 to group A/B" "A,B" bitfld.long 0x00 6. " LFSAB6 ,Last Frame Started Interrupt of Channel 6 to group A/B" "A,B" bitfld.long 0x00 5. " LFSAB5 ,Last Frame Started Interrupt of Channel 5 to group A/B" "A,B" bitfld.long 0x00 4. " LFSAB4 ,Last Frame Started Interrupt of Channel 4 to group A/B" "A,B" textline " " bitfld.long 0x00 3. " LFSAB3 ,Last Frame Started Interrupt of Channel 3 to group A/B" "A,B" bitfld.long 0x00 2. " LFSAB2 ,Last Frame Started Interrupt of Channel 2 to group A/B" "A,B" bitfld.long 0x00 1. " LFSAB1 ,Last Frame Started Interrupt of Channel 1 to group A/B" "A,B" bitfld.long 0x00 0. " LFSAB0 ,Last Frame Started Interrupt of Channel 0 to group A/B" "A,B" group.long 0xC4++0x3 line.long 0x0 "HBCMAP,HBC INTERRUPT MAPPING Register" bitfld.long 0x00 28. " HBCAB28 ,Half Block Complete Interrupt of Channel 28 to group A/B" "A,B" bitfld.long 0x00 27. " HBCAB27 ,Half Block Complete Interrupt of Channel 27 to group A/B" "A,B" bitfld.long 0x00 26. " HBCAB26 ,Half Block Complete Interrupt of Channel 26 to group A/B" "A,B" bitfld.long 0x00 25. " HBCAB25 ,Half Block Complete Interrupt of Channel 25 to group A/B" "A,B" bitfld.long 0x00 24. " HBCAB24 ,Half Block Complete Interrupt of Channel 24 to group A/B" "A,B" bitfld.long 0x00 23. " HBCAB23 ,Half Block Complete Interrupt of Channel 23 to group A/B" "A,B" textline " " bitfld.long 0x00 22. " HBCAB22 ,Half Block Complete Interrupt of Channel 22 to group A/B" "A,B" bitfld.long 0x00 21. " HBCAB21 ,Half Block Complete Interrupt of Channel 21 to group A/B" "A,B" bitfld.long 0x00 20. " HBCAB20 ,Half Block Complete Interrupt of Channel 20 to group A/B" "A,B" bitfld.long 0x00 19. " HBCAB19 ,Half Block Complete Interrupt of Channel 19 to group A/B" "A,B" bitfld.long 0x00 18. " HBCAB18 ,Half Block Complete Interrupt of Channel 18 to group A/B" "A,B" bitfld.long 0x00 17. " HBCAB17 ,Half Block Complete Interrupt of Channel 17 to group A/B" "A,B" textline " " bitfld.long 0x00 16. " HBCAB16 ,Half Block Complete Interrupt of Channel 16 to group A/B" "A,B" bitfld.long 0x00 15. " HBCAB15 ,Half Block Complete Interrupt of Channel 15 to group A/B" "A,B" bitfld.long 0x00 14. " HBCAB14 ,Half Block Complete Interrupt of Channel 14 to group A/B" "A,B" bitfld.long 0x00 13. " HBCAB13 ,Half Block Complete Interrupt of Channel 13 to group A/B" "A,B" bitfld.long 0x00 12. " HBCAB12 ,Half Block Complete Interrupt of Channel 12 to group A/B" "A,B" bitfld.long 0x00 10. " HBCAB10 ,Half Block Complete Interrupt of Channel 10 to group A/B" "A,B" textline " " bitfld.long 0x00 9. " HBCAB9 ,Half Block Complete Interrupt of Channel 9 to group A/B" "A,B" bitfld.long 0x00 8. " HBCAB8 ,Half Block Complete Interrupt of Channel 8 to group A/B" "A,B" bitfld.long 0x00 7. " HBCAB7 ,Half Block Complete Interrupt of Channel 7 to group A/B" "A,B" bitfld.long 0x00 6. " HBCAB6 ,Half Block Complete Interrupt of Channel 6 to group A/B" "A,B" bitfld.long 0x00 5. " HBCAB5 ,Half Block Complete Interrupt of Channel 5 to group A/B" "A,B" bitfld.long 0x00 4. " HBCAB4 ,Half Block Complete Interrupt of Channel 4 to group A/B" "A,B" textline " " bitfld.long 0x00 3. " HBCAB3 ,Half Block Complete Interrupt of Channel 3 to group A/B" "A,B" bitfld.long 0x00 2. " HBCAB2 ,Half Block Complete Interrupt of Channel 2 to group A/B" "A,B" bitfld.long 0x00 1. " HBCAB1 ,Half Block Complete Interrupt of Channel 1 to group A/B" "A,B" bitfld.long 0x00 0. " HBCAB0 ,Half Block Complete Interrupt of Channel 0 to group A/B" "A,B" group.long 0xCC++0x3 line.long 0x0 "BTCMAP,BTC INTERRUPT MAPPING Register" bitfld.long 0x00 28. " BTCAB28 ,Block Transfer Complete Interrupt of Channel 28 to group A/B" "A,B" bitfld.long 0x00 27. " BTCAB27 ,Block Transfer Complete Interrupt of Channel 27 to group A/B" "A,B" bitfld.long 0x00 26. " BTCAB26 ,Block Transfer Complete Interrupt of Channel 26 to group A/B" "A,B" bitfld.long 0x00 25. " BTCAB25 ,Block Transfer Complete Interrupt of Channel 25 to group A/B" "A,B" bitfld.long 0x00 24. " BTCAB24 ,Block Transfer Complete Interrupt of Channel 24 to group A/B" "A,B" bitfld.long 0x00 23. " BTCAB23 ,Block Transfer Complete Interrupt of Channel 23 to group A/B" "A,B" textline " " bitfld.long 0x00 22. " BTCAB22 ,Block Transfer Complete Interrupt of Channel 22 to group A/B" "A,B" bitfld.long 0x00 21. " BTCAB21 ,Block Transfer Complete Interrupt of Channel 21 to group A/B" "A,B" bitfld.long 0x00 20. " BTCAB20 ,Block Transfer Complete Interrupt of Channel 20 to group A/B" "A,B" bitfld.long 0x00 19. " BTCAB19 ,Block Transfer Complete Interrupt of Channel 19 to group A/B" "A,B" bitfld.long 0x00 18. " BTCAB18 ,Block Transfer Complete Interrupt of Channel 18 to group A/B" "A,B" bitfld.long 0x00 17. " BTCAB17 ,Block Transfer Complete Interrupt of Channel 17 to group A/B" "A,B" textline " " bitfld.long 0x00 16. " BTCAB16 ,Block Transfer Complete Interrupt of Channel 16 to group A/B" "A,B" bitfld.long 0x00 15. " BTCAB15 ,Block Transfer Complete Interrupt of Channel 15 to group A/B" "A,B" bitfld.long 0x00 14. " BTCAB14 ,Block Transfer Complete Interrupt of Channel 14 to group A/B" "A,B" bitfld.long 0x00 13. " BTCAB13 ,Block Transfer Complete Interrupt of Channel 13 to group A/B" "A,B" bitfld.long 0x00 12. " BTCAB12 ,Block Transfer Complete Interrupt of Channel 12 to group A/B" "A,B" bitfld.long 0x00 10. " BTCAB10 ,Block Transfer Complete Interrupt of Channel 10 to group A/B" "A,B" textline " " bitfld.long 0x00 9. " BTCAB9 ,Block Transfer Complete Interrupt of Channel 9 to group A/B" "A,B" bitfld.long 0x00 8. " BTCAB8 ,Block Transfer Complete Interrupt of Channel 8 to group A/B" "A,B" bitfld.long 0x00 7. " BTCAB7 ,Block Transfer Complete Interrupt of Channel 7 to group A/B" "A,B" bitfld.long 0x00 6. " BTCAB6 ,Block Transfer Complete Interrupt of Channel 6 to group A/B" "A,B" bitfld.long 0x00 5. " BTCAB5 ,Block Transfer Complete Interrupt of Channel 5 to group A/B" "A,B" bitfld.long 0x00 4. " BTCAB4 ,Block Transfer Complete Interrupt of Channel 4 to group A/B" "A,B" textline " " bitfld.long 0x00 3. " BTCAB3 ,Block Transfer Complete Interrupt of Channel 3 to group A/B" "A,B" bitfld.long 0x00 2. " BTCAB2 ,Block Transfer Complete Interrupt of Channel 2 to group A/B" "A,B" bitfld.long 0x00 1. " BTCAB1 ,Block Transfer Complete Interrupt of Channel 1 to group A/B" "A,B" bitfld.long 0x00 0. " BTCAB0 ,Block Transfer Complete Interrupt of Channel 0 to group A/B" "A,B" group.long 0xD4++0x3 line.long 0x0 "BERMAP,BER INTERRUPT MAPPING Register" bitfld.long 0x00 28. " BERAB28 ,Bus Error Interrupt of Channel 28 to group A/B" "A,B" bitfld.long 0x00 27. " BERAB27 ,Bus Error Interrupt of Channel 27 to group A/B" "A,B" bitfld.long 0x00 26. " BERAB26 ,Bus Error Interrupt of Channel 26 to group A/B" "A,B" bitfld.long 0x00 25. " BERAB25 ,Bus Error Interrupt of Channel 25 to group A/B" "A,B" bitfld.long 0x00 24. " BERAB24 ,Bus Error Interrupt of Channel 24 to group A/B" "A,B" bitfld.long 0x00 23. " BERAB23 ,Bus Error Interrupt of Channel 23 to group A/B" "A,B" textline " " bitfld.long 0x00 22. " BERAB22 ,Bus Error Interrupt of Channel 22 to group A/B" "A,B" bitfld.long 0x00 21. " BERAB21 ,Bus Error Interrupt of Channel 21 to group A/B" "A,B" bitfld.long 0x00 20. " BERAB20 ,Bus Error Interrupt of Channel 20 to group A/B" "A,B" bitfld.long 0x00 19. " BERAB19 ,Bus Error Interrupt of Channel 19 to group A/B" "A,B" bitfld.long 0x00 18. " BERAB18 ,Bus Error Interrupt of Channel 18 to group A/B" "A,B" bitfld.long 0x00 17. " BERAB17 ,Bus Error Interrupt of Channel 17 to group A/B" "A,B" textline " " bitfld.long 0x00 16. " BERAB16 ,Bus Error Interrupt of Channel 16 to group A/B" "A,B" bitfld.long 0x00 15. " BERAB15 ,Bus Error Interrupt of Channel 15 to group A/B" "A,B" bitfld.long 0x00 14. " BERAB14 ,Bus Error Interrupt of Channel 14 to group A/B" "A,B" bitfld.long 0x00 13. " BERAB13 ,Bus Error Interrupt of Channel 13 to group A/B" "A,B" bitfld.long 0x00 12. " BERAB12 ,Bus Error Interrupt of Channel 12 to group A/B" "A,B" bitfld.long 0x00 10. " BERAB10 ,Bus Error Interrupt of Channel 10 to group A/B" "A,B" textline " " bitfld.long 0x00 9. " BERAB9 ,Bus Error Interrupt of Channel 9 to group A/B" "A,B" bitfld.long 0x00 8. " BERAB8 ,Bus Error Interrupt of Channel 8 to group A/B" "A,B" bitfld.long 0x00 7. " BERAB7 ,Bus Error Interrupt of Channel 7 to group A/B" "A,B" bitfld.long 0x00 6. " BERAB6 ,Bus Error Interrupt of Channel 6 to group A/B" "A,B" bitfld.long 0x00 5. " BERAB5 ,Bus Error Interrupt of Channel 5 to group A/B" "A,B" bitfld.long 0x00 4. " BERAB4 ,Bus Error Interrupt of Channel 4 to group A/B" "A,B" textline " " bitfld.long 0x00 3. " BERAB3 ,Bus Error Interrupt of Channel 3 to group A/B" "A,B" bitfld.long 0x00 2. " BERAB2 ,Bus Error Interrupt of Channel 2 to group A/B" "A,B" bitfld.long 0x00 1. " BERAB1 ,Bus Error Interrupt of Channel 1 to group A/B" "A,B" bitfld.long 0x00 0. " BERAB0 ,Bus Error Interrupt of Channel 0 to group A/B" "A,B" tree.end width 0xc tree "Interrupt Enable Registers" group.long 0xDC++0x3 line.long 0x0 "FTCINTENAS,FTC INTERRUPT ENABLE SET" bitfld.long 0x00 28. " FTCINTENA28 ,FTC (Frame Transfer Complete) Interrupt Enable 28" "Disabled,Enabled" bitfld.long 0x00 27. " FTCINTENA27 ,FTC (Frame Transfer Complete) Interrupt Enable 27" "Disabled,Enabled" bitfld.long 0x00 26. " FTCINTENA26 ,FTC (Frame Transfer Complete) Interrupt Enable 26" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " FTCINTENA25 ,FTC (Frame Transfer Complete) Interrupt Enable 25" "Disabled,Enabled" bitfld.long 0x00 24. " FTCINTENA24 ,FTC (Frame Transfer Complete) Interrupt Enable 24" "Disabled,Enabled" bitfld.long 0x00 23. " FTCINTENA23 ,FTC (Frame Transfer Complete) Interrupt Enable 23" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " FTCINTENA22 ,FTC (Frame Transfer Complete) Interrupt Enable 22" "Disabled,Enabled" bitfld.long 0x00 21. " FTCINTENA21 ,FTC (Frame Transfer Complete) Interrupt Enable 21" "Disabled,Enabled" bitfld.long 0x00 20. " FTCINTENA20 ,FTC (Frame Transfer Complete) Interrupt Enable 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " FTCINTENA19 ,FTC (Frame Transfer Complete) Interrupt Enable 19" "Disabled,Enabled" bitfld.long 0x00 18. " FTCINTENA18 ,FTC (Frame Transfer Complete) Interrupt Enable 18" "Disabled,Enabled" bitfld.long 0x00 17. " FTCINTENA17 ,FTC (Frame Transfer Complete) Interrupt Enable 17" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " FTCINTENA16 ,FTC (Frame Transfer Complete) Interrupt Enable 16" "Disabled,Enabled" bitfld.long 0x00 15. " FTCINTENA15 ,FTC (Frame Transfer Complete) Interrupt Enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " FTCINTENA14 ,FTC (Frame Transfer Complete) Interrupt Enable 14" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " FTCINTENA13 ,FTC (Frame Transfer Complete) Interrupt Enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " FTCINTENA12 ,FTC (Frame Transfer Complete) Interrupt Enable 12" "Disabled,Enabled" bitfld.long 0x00 10. " FTCINTENA10 ,FTC (Frame Transfer Complete) Interrupt Enable 10" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " FTCINTENA9 ,FTC (Frame Transfer Complete) Interrupt Enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " FTCINTENA8 ,FTC (Frame Transfer Complete) Interrupt Enable 8" "Disabled,Enabled" bitfld.long 0x00 7. " FTCINTENA7 ,FTC (Frame Transfer Complete) Interrupt Enable 7" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " FTCINTENA6 ,FTC (Frame Transfer Complete) Interrupt Enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " FTCINTENA5 ,FTC (Frame Transfer Complete) Interrupt Enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " FTCINTENA4 ,FTC (Frame Transfer Complete) Interrupt Enable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " FTCINTENA3 ,FTC (Frame Transfer Complete) Interrupt Enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " FTCINTENA2 ,FTC (Frame Transfer Complete) Interrupt Enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " FTCINTENA1 ,FTC (Frame Transfer Complete) Interrupt Enable 1" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " FTCINTENA0 ,FTC (Frame Transfer Complete) Interrupt Enable 0" "Disabled,Enabled" width 0xc group.long 0xE4++0x3 line.long 0x0 "FTCINTENAR,FTC INTERRUPT ENABLE RESET" bitfld.long 0x00 28. " FTCINTENA28 ,FTC (Frame Transfer Complete) Interrupt Disable 28" "No effect,Reset" bitfld.long 0x00 27. " FTCINTENA27 ,FTC (Frame Transfer Complete) Interrupt Disable 27" "No effect,Reset" bitfld.long 0x00 26. " FTCINTENA26 ,FTC (Frame Transfer Complete) Interrupt Disable 26" "No effect,Reset" textline " " bitfld.long 0x00 25. " FTCINTENA25 ,FTC (Frame Transfer Complete) Interrupt Disable 25" "No effect,Reset" bitfld.long 0x00 24. " FTCINTENA24 ,FTC (Frame Transfer Complete) Interrupt Disable 24" "No effect,Reset" bitfld.long 0x00 23. " FTCINTENA23 ,FTC (Frame Transfer Complete) Interrupt Disable 23" "No effect,Reset" textline " " bitfld.long 0x00 22. " FTCINTENA22 ,FTC (Frame Transfer Complete) Interrupt Disable 22" "No effect,Reset" bitfld.long 0x00 21. " FTCINTENA21 ,FTC (Frame Transfer Complete) Interrupt Disable 21" "No effect,Reset" bitfld.long 0x00 20. " FTCINTENA20 ,FTC (Frame Transfer Complete) Interrupt Disable 20" "No effect,Reset" textline " " bitfld.long 0x00 19. " FTCINTENA19 ,FTC (Frame Transfer Complete) Interrupt Disable 19" "No effect,Reset" bitfld.long 0x00 18. " FTCINTENA18 ,FTC (Frame Transfer Complete) Interrupt Disable 18" "No effect,Reset" bitfld.long 0x00 17. " FTCINTENA17 ,FTC (Frame Transfer Complete) Interrupt Disable 17" "No effect,Reset" textline " " bitfld.long 0x00 16. " FTCINTENA16 ,FTC (Frame Transfer Complete) Interrupt Disable 16" "No effect,Reset" bitfld.long 0x00 15. " FTCINTENA15 ,FTC (Frame Transfer Complete) Interrupt Disable 15" "No effect,Reset" bitfld.long 0x00 14. " FTCINTENA14 ,FTC (Frame Transfer Complete) Interrupt Disable 14" "No effect,Reset" textline " " bitfld.long 0x00 13. " FTCINTENA13 ,FTC (Frame Transfer Complete) Interrupt Disable 13" "No effect,Reset" bitfld.long 0x00 12. " FTCINTENA12 ,FTC (Frame Transfer Complete) Interrupt Disable 12" "No effect,Reset" bitfld.long 0x00 10. " FTCINTENA10 ,FTC (Frame Transfer Complete) Interrupt Disable 10" "No effect,Reset" textline " " bitfld.long 0x00 9. " FTCINTENA9 ,FTC (Frame Transfer Complete) Interrupt Disable 9" "No effect,Reset" bitfld.long 0x00 8. " FTCINTENA8 ,FTC (Frame Transfer Complete) Interrupt Disable 8" "No effect,Reset" bitfld.long 0x00 7. " FTCINTENA7 ,FTC (Frame Transfer Complete) Interrupt Disable 7" "No effect,Reset" textline " " bitfld.long 0x00 6. " FTCINTENA6 ,FTC (Frame Transfer Complete) Interrupt Disable 6" "No effect,Reset" bitfld.long 0x00 5. " FTCINTENA5 ,FTC (Frame Transfer Complete) Interrupt Disable 5" "No effect,Reset" bitfld.long 0x00 4. " FTCINTENA4 ,FTC (Frame Transfer Complete) Interrupt Disable 4" "No effect,Reset" textline " " bitfld.long 0x00 3. " FTCINTENA3 ,FTC (Frame Transfer Complete) Interrupt Disable 3" "No effect,Reset" bitfld.long 0x00 2. " FTCINTENA2 ,FTC (Frame Transfer Complete) Interrupt Disable 2" "No effect,Reset" bitfld.long 0x00 1. " FTCINTENA1 ,FTC (Frame Transfer Complete) Interrupt Disable 1" "No effect,Reset" textline " " bitfld.long 0x00 0. " FTCINTENA0 ,FTC (Frame Transfer Complete) Interrupt Disable 0" "No effect,Reset" width 0xc group.long 0xEC++0x3 line.long 0x0 "LFSINTENAS,LFS INTERRUPT ENABLE SET" bitfld.long 0x00 28. " LFSINTENA28 ,LFS (Last Frame Started) Interrupt Enable 28" "Disabled,Enabled" bitfld.long 0x00 27. " LFSINTENA27 ,LFS (Last Frame Started) Interrupt Enable 27" "Disabled,Enabled" bitfld.long 0x00 26. " LFSINTENA26 ,LFS (Last Frame Started) Interrupt Enable 26" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " LFSINTENA25 ,LFS (Last Frame Started) Interrupt Enable 25" "Disabled,Enabled" bitfld.long 0x00 24. " LFSINTENA24 ,LFS (Last Frame Started) Interrupt Enable 24" "Disabled,Enabled" bitfld.long 0x00 23. " LFSINTENA23 ,LFS (Last Frame Started) Interrupt Enable 23" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " LFSINTENA22 ,LFS (Last Frame Started) Interrupt Enable 22" "Disabled,Enabled" bitfld.long 0x00 21. " LFSINTENA21 ,LFS (Last Frame Started) Interrupt Enable 21" "Disabled,Enabled" bitfld.long 0x00 20. " LFSINTENA20 ,LFS (Last Frame Started) Interrupt Enable 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " LFSINTENA19 ,LFS (Last Frame Started) Interrupt Enable 19" "Disabled,Enabled" bitfld.long 0x00 18. " LFSINTENA18 ,LFS (Last Frame Started) Interrupt Enable 18" "Disabled,Enabled" bitfld.long 0x00 17. " LFSINTENA17 ,LFS (Last Frame Started) Interrupt Enable 17" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " LFSINTENA16 ,LFS (Last Frame Started) Interrupt Enable 16" "Disabled,Enabled" bitfld.long 0x00 15. " LFSINTENA15 ,LFS (Last Frame Started) Interrupt Enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " LFSINTENA14 ,LFS (Last Frame Started) Interrupt Enable 14" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " LFSINTENA13 ,LFS (Last Frame Started) Interrupt Enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " LFSINTENA12 ,LFS (Last Frame Started) Interrupt Enable 12" "Disabled,Enabled" bitfld.long 0x00 10. " LFSINTENA10 ,LFS (Last Frame Started) Interrupt Enable 10" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " LFSINTENA9 ,LFS (Last Frame Started) Interrupt Enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " LFSINTENA8 ,LFS (Last Frame Started) Interrupt Enable 8" "Disabled,Enabled" bitfld.long 0x00 7. " LFSINTENA7 ,LFS (Last Frame Started) Interrupt Enable 7" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " LFSINTENA6 ,LFS (Last Frame Started) Interrupt Enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " LFSINTENA5 ,LFS (Last Frame Started) Interrupt Enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " LFSINTENA4 ,LFS (Last Frame Started) Interrupt Enable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " LFSINTENA3 ,LFS (Last Frame Started) Interrupt Enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " LFSINTENA2 ,LFS (Last Frame Started) Interrupt Enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " LFSINTENA1 ,LFS (Last Frame Started) Interrupt Enable 1" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " LFSINTENA0 ,LFS (Last Frame Started) Interrupt Enable 0" "Disabled,Enabled" width 0xc group.long 0xF4++0x3 line.long 0x0 "LFSINTENAR,LFS INTERRUPT ENABLE RESET" bitfld.long 0x00 28. " LFSINTENA28 ,LFS (Last Frame Started) Interrupt Disable 28" "No effect,Reset" bitfld.long 0x00 27. " LFSINTENA27 ,LFS (Last Frame Started) Interrupt Disable 27" "No effect,Reset" bitfld.long 0x00 26. " LFSINTENA26 ,LFS (Last Frame Started) Interrupt Disable 26" "No effect,Reset" textline " " bitfld.long 0x00 25. " LFSINTENA25 ,LFS (Last Frame Started) Interrupt Disable 25" "No effect,Reset" bitfld.long 0x00 24. " LFSINTENA24 ,LFS (Last Frame Started) Interrupt Disable 24" "No effect,Reset" bitfld.long 0x00 23. " LFSINTENA23 ,LFS (Last Frame Started) Interrupt Disable 23" "No effect,Reset" textline " " bitfld.long 0x00 22. " LFSINTENA22 ,LFS (Last Frame Started) Interrupt Disable 22" "No effect,Reset" bitfld.long 0x00 21. " LFSINTENA21 ,LFS (Last Frame Started) Interrupt Disable 21" "No effect,Reset" bitfld.long 0x00 20. " LFSINTENA20 ,LFS (Last Frame Started) Interrupt Disable 20" "No effect,Reset" textline " " bitfld.long 0x00 19. " LFSINTENA19 ,LFS (Last Frame Started) Interrupt Disable 19" "No effect,Reset" bitfld.long 0x00 18. " LFSINTENA18 ,LFS (Last Frame Started) Interrupt Disable 18" "No effect,Reset" bitfld.long 0x00 17. " LFSINTENA17 ,LFS (Last Frame Started) Interrupt Disable 17" "No effect,Reset" textline " " bitfld.long 0x00 16. " LFSINTENA16 ,LFS (Last Frame Started) Interrupt Disable 16" "No effect,Reset" bitfld.long 0x00 15. " LFSINTENA15 ,LFS (Last Frame Started) Interrupt Disable 15" "No effect,Reset" bitfld.long 0x00 14. " LFSINTENA14 ,LFS (Last Frame Started) Interrupt Disable 14" "No effect,Reset" textline " " bitfld.long 0x00 13. " LFSINTENA13 ,LFS (Last Frame Started) Interrupt Disable 13" "No effect,Reset" bitfld.long 0x00 12. " LFSINTENA12 ,LFS (Last Frame Started) Interrupt Disable 12" "No effect,Reset" bitfld.long 0x00 10. " LFSINTENA10 ,LFS (Last Frame Started) Interrupt Disable 10" "No effect,Reset" textline " " bitfld.long 0x00 9. " LFSINTENA9 ,LFS (Last Frame Started) Interrupt Disable 9" "No effect,Reset" bitfld.long 0x00 8. " LFSINTENA8 ,LFS (Last Frame Started) Interrupt Disable 8" "No effect,Reset" bitfld.long 0x00 7. " LFSINTENA7 ,LFS (Last Frame Started) Interrupt Disable 7" "No effect,Reset" textline " " bitfld.long 0x00 6. " LFSINTENA6 ,LFS (Last Frame Started) Interrupt Disable 6" "No effect,Reset" bitfld.long 0x00 5. " LFSINTENA5 ,LFS (Last Frame Started) Interrupt Disable 5" "No effect,Reset" bitfld.long 0x00 4. " LFSINTENA4 ,LFS (Last Frame Started) Interrupt Disable 4" "No effect,Reset" textline " " bitfld.long 0x00 3. " LFSINTENA3 ,LFS (Last Frame Started) Interrupt Disable 3" "No effect,Reset" bitfld.long 0x00 2. " LFSINTENA2 ,LFS (Last Frame Started) Interrupt Disable 2" "No effect,Reset" bitfld.long 0x00 1. " LFSINTENA1 ,LFS (Last Frame Started) Interrupt Disable 1" "No effect,Reset" textline " " bitfld.long 0x00 0. " LFSINTENA0 ,LFS (Last Frame Started) Interrupt Disable 0" "No effect,Reset" width 0xc group.long 0xFC++0x3 line.long 0x0 "HBCINTENAS,HBC INTERRUPT ENABLE SET" bitfld.long 0x00 28. " HBCINTENA28 ,HBC (Half Block Complete) Interrupt Enable 28" "Disabled,Enabled" bitfld.long 0x00 27. " HBCINTENA27 ,HBC (Half Block Complete) Interrupt Enable 27" "Disabled,Enabled" bitfld.long 0x00 26. " HBCINTENA26 ,HBC (Half Block Complete) Interrupt Enable 26" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " HBCINTENA25 ,HBC (Half Block Complete) Interrupt Enable 25" "Disabled,Enabled" bitfld.long 0x00 24. " HBCINTENA24 ,HBC (Half Block Complete) Interrupt Enable 24" "Disabled,Enabled" bitfld.long 0x00 23. " HBCINTENA23 ,HBC (Half Block Complete) Interrupt Enable 23" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " HBCINTENA22 ,HBC (Half Block Complete) Interrupt Enable 22" "Disabled,Enabled" bitfld.long 0x00 21. " HBCINTENA21 ,HBC (Half Block Complete) Interrupt Enable 21" "Disabled,Enabled" bitfld.long 0x00 20. " HBCINTENA20 ,HBC (Half Block Complete) Interrupt Enable 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " HBCINTENA19 ,HBC (Half Block Complete) Interrupt Enable 19" "Disabled,Enabled" bitfld.long 0x00 18. " HBCINTENA18 ,HBC (Half Block Complete) Interrupt Enable 18" "Disabled,Enabled" bitfld.long 0x00 17. " HBCINTENA17 ,HBC (Half Block Complete) Interrupt Enable 17" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " HBCINTENA16 ,HBC (Half Block Complete) Interrupt Enable 16" "Disabled,Enabled" bitfld.long 0x00 15. " HBCINTENA15 ,HBC (Half Block Complete) Interrupt Enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " HBCINTENA14 ,HBC (Half Block Complete) Interrupt Enable 14" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " HBCINTENA13 ,HBC (Half Block Complete) Interrupt Enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " HBCINTENA12 ,HBC (Half Block Complete) Interrupt Enable 12" "Disabled,Enabled" bitfld.long 0x00 10. " HBCINTENA10 ,HBC (Half Block Complete) Interrupt Enable 10" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " HBCINTENA9 ,HBC (Half Block Complete) Interrupt Enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " HBCINTENA8 ,HBC (Half Block Complete) Interrupt Enable 8" "Disabled,Enabled" bitfld.long 0x00 7. " HBCINTENA7 ,HBC (Half Block Complete) Interrupt Enable 7" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " HBCINTENA6 ,HBC (Half Block Complete) Interrupt Enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " HBCINTENA5 ,HBC (Half Block Complete) Interrupt Enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " HBCINTENA4 ,HBC (Half Block Complete) Interrupt Enable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " HBCINTENA3 ,HBC (Half Block Complete) Interrupt Enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " HBCINTENA2 ,HBC (Half Block Complete) Interrupt Enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " HBCINTENA1 ,HBC (Half Block Complete) Interrupt Enable 1" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " HBCINTENA0 ,HBC (Half Block Complete) Interrupt Enable 0" "Disabled,Enabled" width 0xc group.long 0x104++0x3 line.long 0x0 "HBCINTENAR,HBC INTERRUPT ENABLE RESET" bitfld.long 0x00 28. " HBCINTENA28 ,HBC (Half Block Complete) Interrupt Disable 28" "No effect,Reset" bitfld.long 0x00 27. " HBCINTENA27 ,HBC (Half Block Complete) Interrupt Disable 27" "No effect,Reset" bitfld.long 0x00 26. " HBCINTENA26 ,HBC (Half Block Complete) Interrupt Disable 26" "No effect,Reset" textline " " bitfld.long 0x00 25. " HBCINTENA25 ,HBC (Half Block Complete) Interrupt Disable 25" "No effect,Reset" bitfld.long 0x00 24. " HBCINTENA24 ,HBC (Half Block Complete) Interrupt Disable 24" "No effect,Reset" bitfld.long 0x00 23. " HBCINTENA23 ,HBC (Half Block Complete) Interrupt Disable 23" "No effect,Reset" textline " " bitfld.long 0x00 22. " HBCINTENA22 ,HBC (Half Block Complete) Interrupt Disable 22" "No effect,Reset" bitfld.long 0x00 21. " HBCINTENA21 ,HBC (Half Block Complete) Interrupt Disable 21" "No effect,Reset" bitfld.long 0x00 20. " HBCINTENA20 ,HBC (Half Block Complete) Interrupt Disable 20" "No effect,Reset" textline " " bitfld.long 0x00 19. " HBCINTENA19 ,HBC (Half Block Complete) Interrupt Disable 19" "No effect,Reset" bitfld.long 0x00 18. " HBCINTENA18 ,HBC (Half Block Complete) Interrupt Disable 18" "No effect,Reset" bitfld.long 0x00 17. " HBCINTENA17 ,HBC (Half Block Complete) Interrupt Disable 17" "No effect,Reset" textline " " bitfld.long 0x00 16. " HBCINTENA16 ,HBC (Half Block Complete) Interrupt Disable 16" "No effect,Reset" bitfld.long 0x00 15. " HBCINTENA15 ,HBC (Half Block Complete) Interrupt Disable 15" "No effect,Reset" bitfld.long 0x00 14. " HBCINTENA14 ,HBC (Half Block Complete) Interrupt Disable 14" "No effect,Reset" textline " " bitfld.long 0x00 13. " HBCINTENA13 ,HBC (Half Block Complete) Interrupt Disable 13" "No effect,Reset" bitfld.long 0x00 12. " HBCINTENA12 ,HBC (Half Block Complete) Interrupt Disable 12" "No effect,Reset" bitfld.long 0x00 10. " HBCINTENA10 ,HBC (Half Block Complete) Interrupt Disable 10" "No effect,Reset" textline " " bitfld.long 0x00 9. " HBCINTENA9 ,HBC (Half Block Complete) Interrupt Disable 9" "No effect,Reset" bitfld.long 0x00 8. " HBCINTENA8 ,HBC (Half Block Complete) Interrupt Disable 8" "No effect,Reset" bitfld.long 0x00 7. " HBCINTENA7 ,HBC (Half Block Complete) Interrupt Disable 7" "No effect,Reset" textline " " bitfld.long 0x00 6. " HBCINTENA6 ,HBC (Half Block Complete) Interrupt Disable 6" "No effect,Reset" bitfld.long 0x00 5. " HBCINTENA5 ,HBC (Half Block Complete) Interrupt Disable 5" "No effect,Reset" bitfld.long 0x00 4. " HBCINTENA4 ,HBC (Half Block Complete) Interrupt Disable 4" "No effect,Reset" textline " " bitfld.long 0x00 3. " HBCINTENA3 ,HBC (Half Block Complete) Interrupt Disable 3" "No effect,Reset" bitfld.long 0x00 2. " HBCINTENA2 ,HBC (Half Block Complete) Interrupt Disable 2" "No effect,Reset" bitfld.long 0x00 1. " HBCINTENA1 ,HBC (Half Block Complete) Interrupt Disable 1" "No effect,Reset" textline " " bitfld.long 0x00 0. " HBCINTENA0 ,HBC (Half Block Complete) Interrupt Disable 0" "No effect,Reset" width 0xc group.long 0x10C++0x3 line.long 0x0 "BTCINTENAS,BTC INTERRUPT ENABLE SET" bitfld.long 0x00 28. " BTCINTENA28 ,BTC (Block Transfer Complete) Interrupt Enable 28" "Disabled,Enabled" bitfld.long 0x00 27. " BTCINTENA27 ,BTC (Block Transfer Complete) Interrupt Enable 27" "Disabled,Enabled" bitfld.long 0x00 26. " BTCINTENA26 ,BTC (Block Transfer Complete) Interrupt Enable 26" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " BTCINTENA25 ,BTC (Block Transfer Complete) Interrupt Enable 25" "Disabled,Enabled" bitfld.long 0x00 24. " BTCINTENA24 ,BTC (Block Transfer Complete) Interrupt Enable 24" "Disabled,Enabled" bitfld.long 0x00 23. " BTCINTENA23 ,BTC (Block Transfer Complete) Interrupt Enable 23" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " BTCINTENA22 ,BTC (Block Transfer Complete) Interrupt Enable 22" "Disabled,Enabled" bitfld.long 0x00 21. " BTCINTENA21 ,BTC (Block Transfer Complete) Interrupt Enable 21" "Disabled,Enabled" bitfld.long 0x00 20. " BTCINTENA20 ,BTC (Block Transfer Complete) Interrupt Enable 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " BTCINTENA19 ,BTC (Block Transfer Complete) Interrupt Enable 19" "Disabled,Enabled" bitfld.long 0x00 18. " BTCINTENA18 ,BTC (Block Transfer Complete) Interrupt Enable 18" "Disabled,Enabled" bitfld.long 0x00 17. " BTCINTENA17 ,BTC (Block Transfer Complete) Interrupt Enable 17" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " BTCINTENA16 ,BTC (Block Transfer Complete) Interrupt Enable 16" "Disabled,Enabled" bitfld.long 0x00 15. " BTCINTENA15 ,BTC (Block Transfer Complete) Interrupt Enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " BTCINTENA14 ,BTC (Block Transfer Complete) Interrupt Enable 14" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " BTCINTENA13 ,BTC (Block Transfer Complete) Interrupt Enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " BTCINTENA12 ,BTC (Block Transfer Complete) Interrupt Enable 12" "Disabled,Enabled" bitfld.long 0x00 10. " BTCINTENA10 ,BTC (Block Transfer Complete) Interrupt Enable 10" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " BTCINTENA9 ,BTC (Block Transfer Complete) Interrupt Enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " BTCINTENA8 ,BTC (Block Transfer Complete) Interrupt Enable 8" "Disabled,Enabled" bitfld.long 0x00 7. " BTCINTENA7 ,BTC (Block Transfer Complete) Interrupt Enable 7" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " BTCINTENA6 ,BTC (Block Transfer Complete) Interrupt Enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " BTCINTENA5 ,BTC (Block Transfer Complete) Interrupt Enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " BTCINTENA4 ,BTC (Block Transfer Complete) Interrupt Enable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " BTCINTENA3 ,BTC (Block Transfer Complete) Interrupt Enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " BTCINTENA2 ,BTC (Block Transfer Complete) Interrupt Enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " BTCINTENA1 ,BTC (Block Transfer Complete) Interrupt Enable 1" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " BTCINTENA0 ,BTC (Block Transfer Complete) Interrupt Enable 0" "Disabled,Enabled" width 0xc group.long 0x114++0x3 line.long 0x0 "BTCINTENAR,BTC INTERRUPT ENABLE RESET" bitfld.long 0x00 28. " BTCINTENA28 ,BTC (Block Transfer Complete) Interrupt Disable 28" "No effect,Reset" bitfld.long 0x00 27. " BTCINTENA27 ,BTC (Block Transfer Complete) Interrupt Disable 27" "No effect,Reset" bitfld.long 0x00 26. " BTCINTENA26 ,BTC (Block Transfer Complete) Interrupt Disable 26" "No effect,Reset" textline " " bitfld.long 0x00 25. " BTCINTENA25 ,BTC (Block Transfer Complete) Interrupt Disable 25" "No effect,Reset" bitfld.long 0x00 24. " BTCINTENA24 ,BTC (Block Transfer Complete) Interrupt Disable 24" "No effect,Reset" bitfld.long 0x00 23. " BTCINTENA23 ,BTC (Block Transfer Complete) Interrupt Disable 23" "No effect,Reset" textline " " bitfld.long 0x00 22. " BTCINTENA22 ,BTC (Block Transfer Complete) Interrupt Disable 22" "No effect,Reset" bitfld.long 0x00 21. " BTCINTENA21 ,BTC (Block Transfer Complete) Interrupt Disable 21" "No effect,Reset" bitfld.long 0x00 20. " BTCINTENA20 ,BTC (Block Transfer Complete) Interrupt Disable 20" "No effect,Reset" textline " " bitfld.long 0x00 19. " BTCINTENA19 ,BTC (Block Transfer Complete) Interrupt Disable 19" "No effect,Reset" bitfld.long 0x00 18. " BTCINTENA18 ,BTC (Block Transfer Complete) Interrupt Disable 18" "No effect,Reset" bitfld.long 0x00 17. " BTCINTENA17 ,BTC (Block Transfer Complete) Interrupt Disable 17" "No effect,Reset" textline " " bitfld.long 0x00 16. " BTCINTENA16 ,BTC (Block Transfer Complete) Interrupt Disable 16" "No effect,Reset" bitfld.long 0x00 15. " BTCINTENA15 ,BTC (Block Transfer Complete) Interrupt Disable 15" "No effect,Reset" bitfld.long 0x00 14. " BTCINTENA14 ,BTC (Block Transfer Complete) Interrupt Disable 14" "No effect,Reset" textline " " bitfld.long 0x00 13. " BTCINTENA13 ,BTC (Block Transfer Complete) Interrupt Disable 13" "No effect,Reset" bitfld.long 0x00 12. " BTCINTENA12 ,BTC (Block Transfer Complete) Interrupt Disable 12" "No effect,Reset" bitfld.long 0x00 10. " BTCINTENA10 ,BTC (Block Transfer Complete) Interrupt Disable 10" "No effect,Reset" textline " " bitfld.long 0x00 9. " BTCINTENA9 ,BTC (Block Transfer Complete) Interrupt Disable 9" "No effect,Reset" bitfld.long 0x00 8. " BTCINTENA8 ,BTC (Block Transfer Complete) Interrupt Disable 8" "No effect,Reset" bitfld.long 0x00 7. " BTCINTENA7 ,BTC (Block Transfer Complete) Interrupt Disable 7" "No effect,Reset" textline " " bitfld.long 0x00 6. " BTCINTENA6 ,BTC (Block Transfer Complete) Interrupt Disable 6" "No effect,Reset" bitfld.long 0x00 5. " BTCINTENA5 ,BTC (Block Transfer Complete) Interrupt Disable 5" "No effect,Reset" bitfld.long 0x00 4. " BTCINTENA4 ,BTC (Block Transfer Complete) Interrupt Disable 4" "No effect,Reset" textline " " bitfld.long 0x00 3. " BTCINTENA3 ,BTC (Block Transfer Complete) Interrupt Disable 3" "No effect,Reset" bitfld.long 0x00 2. " BTCINTENA2 ,BTC (Block Transfer Complete) Interrupt Disable 2" "No effect,Reset" bitfld.long 0x00 1. " BTCINTENA1 ,BTC (Block Transfer Complete) Interrupt Disable 1" "No effect,Reset" textline " " bitfld.long 0x00 0. " BTCINTENA0 ,BTC (Block Transfer Complete) Interrupt Disable 0" "No effect,Reset" tree.end width 0x9 tree "Interrupt Flag Registers" group.long 0x11C++0x3 line.long 0x0 "GINTFLAG,GLOBAL INTERRUPT FLAG Register" bitfld.long 0x00 28. " GINT28 ,Global Interrupt Flag 28" "Not pending,Pending" bitfld.long 0x00 27. " GINT27 ,Global Interrupt Flag 27" "Not pending,Pending" bitfld.long 0x00 26. " GINT26 ,Global Interrupt Flag 26" "Not pending,Pending" textline " " bitfld.long 0x00 25. " GINT25 ,Global Interrupt Flag 25" "Not pending,Pending" bitfld.long 0x00 24. " GINT24 ,Global Interrupt Flag 24" "Not pending,Pending" bitfld.long 0x00 23. " GINT23 ,Global Interrupt Flag 23" "Not pending,Pending" textline " " bitfld.long 0x00 22. " GINT22 ,Global Interrupt Flag 22" "Not pending,Pending" bitfld.long 0x00 21. " GINT21 ,Global Interrupt Flag 21" "Not pending,Pending" bitfld.long 0x00 20. " GINT20 ,Global Interrupt Flag 20" "Not pending,Pending" textline " " bitfld.long 0x00 19. " GINT19 ,Global Interrupt Flag 19" "Not pending,Pending" bitfld.long 0x00 18. " GINT18 ,Global Interrupt Flag 18" "Not pending,Pending" bitfld.long 0x00 17. " GINT17 ,Global Interrupt Flag 17" "Not pending,Pending" textline " " bitfld.long 0x00 16. " GINT16 ,Global Interrupt Flag 16" "Not pending,Pending" bitfld.long 0x00 15. " GINT15 ,Global Interrupt Flag 15" "Not pending,Pending" bitfld.long 0x00 14. " GINT14 ,Global Interrupt Flag 14" "Not pending,Pending" textline " " bitfld.long 0x00 13. " GINT13 ,Global Interrupt Flag 13" "Not pending,Pending" bitfld.long 0x00 12. " GINT12 ,Global Interrupt Flag 12" "Not pending,Pending" bitfld.long 0x00 10. " GINT10 ,Global Interrupt Flag 10" "Not pending,Pending" textline " " bitfld.long 0x00 9. " GINT9 ,Global Interrupt Flag 9" "Not pending,Pending" bitfld.long 0x00 8. " GINT8 ,Global Interrupt Flag 8" "Not pending,Pending" bitfld.long 0x00 7. " GINT7 ,Global Interrupt Flag 7" "Not pending,Pending" textline " " bitfld.long 0x00 6. " GINT6 ,Global Interrupt Flag 6" "Not pending,Pending" bitfld.long 0x00 5. " GINT5 ,Global Interrupt Flag 5" "Not pending,Pending" bitfld.long 0x00 4. " GINT4 ,Global Interrupt Flag 4" "Not pending,Pending" textline " " bitfld.long 0x00 3. " GINT3 ,Global Interrupt Flag 3" "Not pending,Pending" bitfld.long 0x00 2. " GINT2 ,Global Interrupt Flag 2" "Not pending,Pending" bitfld.long 0x00 1. " GINT1 ,Global Interrupt Flag 1" "Not pending,Pending" textline " " bitfld.long 0x00 0. " GINT0 ,Global Interrupt Flag 0" "Not pending,Pending" width 0x9 group.long 0x124++0x3 line.long 0x0 "FTCFLAG,FTC INTERRUPT FLAG Register" eventfld.long 0x00 28. " FTCI28 ,Frame Transfer Complete Flag 28" "Not pending,Pending" eventfld.long 0x00 27. " FTCI27 ,Frame Transfer Complete Flag 27" "Not pending,Pending" eventfld.long 0x00 26. " FTCI26 ,Frame Transfer Complete Flag 26" "Not pending,Pending" textline " " eventfld.long 0x00 25. " FTCI25 ,Frame Transfer Complete Flag 25" "Not pending,Pending" eventfld.long 0x00 24. " FTCI24 ,Frame Transfer Complete Flag 24" "Not pending,Pending" eventfld.long 0x00 23. " FTCI23 ,Frame Transfer Complete Flag 23" "Not pending,Pending" textline " " eventfld.long 0x00 22. " FTCI22 ,Frame Transfer Complete Flag 22" "Not pending,Pending" eventfld.long 0x00 21. " FTCI21 ,Frame Transfer Complete Flag 21" "Not pending,Pending" eventfld.long 0x00 20. " FTCI20 ,Frame Transfer Complete Flag 20" "Not pending,Pending" textline " " eventfld.long 0x00 19. " FTCI19 ,Frame Transfer Complete Flag 19" "Not pending,Pending" eventfld.long 0x00 18. " FTCI18 ,Frame Transfer Complete Flag 18" "Not pending,Pending" eventfld.long 0x00 17. " FTCI17 ,Frame Transfer Complete Flag 17" "Not pending,Pending" textline " " eventfld.long 0x00 16. " FTCI16 ,Frame Transfer Complete Flag 16" "Not pending,Pending" eventfld.long 0x00 15. " FTCI15 ,Frame Transfer Complete Flag 15" "Not pending,Pending" eventfld.long 0x00 14. " FTCI14 ,Frame Transfer Complete Flag 14" "Not pending,Pending" textline " " eventfld.long 0x00 13. " FTCI13 ,Frame Transfer Complete Flag 13" "Not pending,Pending" eventfld.long 0x00 12. " FTCI12 ,Frame Transfer Complete Flag 12" "Not pending,Pending" eventfld.long 0x00 10. " FTCI10 ,Frame Transfer Complete Flag 10" "Not pending,Pending" textline " " eventfld.long 0x00 9. " FTCI9 ,Frame Transfer Complete Flag 9" "Not pending,Pending" eventfld.long 0x00 8. " FTCI8 ,Frame Transfer Complete Flag 8" "Not pending,Pending" eventfld.long 0x00 7. " FTCI7 ,Frame Transfer Complete Flag 7" "Not pending,Pending" textline " " eventfld.long 0x00 6. " FTCI6 ,Frame Transfer Complete Flag 6" "Not pending,Pending" eventfld.long 0x00 5. " FTCI5 ,Frame Transfer Complete Flag 5" "Not pending,Pending" eventfld.long 0x00 4. " FTCI4 ,Frame Transfer Complete Flag 4" "Not pending,Pending" textline " " eventfld.long 0x00 3. " FTCI3 ,Frame Transfer Complete Flag 3" "Not pending,Pending" eventfld.long 0x00 2. " FTCI2 ,Frame Transfer Complete Flag 2" "Not pending,Pending" eventfld.long 0x00 1. " FTCI1 ,Frame Transfer Complete Flag 1" "Not pending,Pending" textline " " eventfld.long 0x00 0. " FTCI0 ,Frame Transfer Complete Flag 0" "Not pending,Pending" group.long 0x12C++0x3 line.long 0x0 "LFSFLAG,LFS INTERRUPT FLAG Register" eventfld.long 0x00 28. " LFSI28 ,Last Frame Transfer Started Flag 28" "Not pending,Pending" eventfld.long 0x00 27. " LFSI27 ,Last Frame Transfer Started Flag 27" "Not pending,Pending" eventfld.long 0x00 26. " LFSI26 ,Last Frame Transfer Started Flag 26" "Not pending,Pending" textline " " eventfld.long 0x00 25. " LFSI25 ,Last Frame Transfer Started Flag 25" "Not pending,Pending" eventfld.long 0x00 24. " LFSI24 ,Last Frame Transfer Started Flag 24" "Not pending,Pending" eventfld.long 0x00 23. " LFSI23 ,Last Frame Transfer Started Flag 23" "Not pending,Pending" textline " " eventfld.long 0x00 22. " LFSI22 ,Last Frame Transfer Started Flag 22" "Not pending,Pending" eventfld.long 0x00 21. " LFSI21 ,Last Frame Transfer Started Flag 21" "Not pending,Pending" eventfld.long 0x00 20. " LFSI20 ,Last Frame Transfer Started Flag 20" "Not pending,Pending" textline " " eventfld.long 0x00 19. " LFSI19 ,Last Frame Transfer Started Flag 19" "Not pending,Pending" eventfld.long 0x00 18. " LFSI18 ,Last Frame Transfer Started Flag 18" "Not pending,Pending" eventfld.long 0x00 17. " LFSI17 ,Last Frame Transfer Started Flag 17" "Not pending,Pending" textline " " eventfld.long 0x00 16. " LFSI16 ,Last Frame Transfer Started Flag 16" "Not pending,Pending" eventfld.long 0x00 15. " LFSI15 ,Last Frame Transfer Started Flag 15" "Not pending,Pending" eventfld.long 0x00 14. " LFSI14 ,Last Frame Transfer Started Flag 14" "Not pending,Pending" textline " " eventfld.long 0x00 13. " LFSI13 ,Last Frame Transfer Started Flag 13" "Not pending,Pending" eventfld.long 0x00 12. " LFSI12 ,Last Frame Transfer Started Flag 12" "Not pending,Pending" eventfld.long 0x00 10. " LFSI10 ,Last Frame Transfer Started Flag 10" "Not pending,Pending" textline " " eventfld.long 0x00 9. " LFSI9 ,Last Frame Transfer Started Flag 9" "Not pending,Pending" eventfld.long 0x00 8. " LFSI8 ,Last Frame Transfer Started Flag 8" "Not pending,Pending" eventfld.long 0x00 7. " LFSI7 ,Last Frame Transfer Started Flag 7" "Not pending,Pending" textline " " eventfld.long 0x00 6. " LFSI6 ,Last Frame Transfer Started Flag 6" "Not pending,Pending" eventfld.long 0x00 5. " LFSI5 ,Last Frame Transfer Started Flag 5" "Not pending,Pending" eventfld.long 0x00 4. " LFSI4 ,Last Frame Transfer Started Flag 4" "Not pending,Pending" textline " " eventfld.long 0x00 3. " LFSI3 ,Last Frame Transfer Started Flag 3" "Not pending,Pending" eventfld.long 0x00 2. " LFSI2 ,Last Frame Transfer Started Flag 2" "Not pending,Pending" eventfld.long 0x00 1. " LFSI1 ,Last Frame Transfer Started Flag 1" "Not pending,Pending" textline " " eventfld.long 0x00 0. " LFSI0 ,Last Frame Transfer Started Flag 0" "Not pending,Pending" group.long 0x134++0x3 line.long 0x0 "HBCFLAG,HBC INTERRUPT FLAG Register" eventfld.long 0x00 28. " HBCI28 ,Half of Block Transfer Complete Flag 28" "Not pending,Pending" eventfld.long 0x00 27. " HBCI27 ,Half of Block Transfer Complete Flag 27" "Not pending,Pending" eventfld.long 0x00 26. " HBCI26 ,Half of Block Transfer Complete Flag 26" "Not pending,Pending" textline " " eventfld.long 0x00 25. " HBCI25 ,Half of Block Transfer Complete Flag 25" "Not pending,Pending" eventfld.long 0x00 24. " HBCI24 ,Half of Block Transfer Complete Flag 24" "Not pending,Pending" eventfld.long 0x00 23. " HBCI23 ,Half of Block Transfer Complete Flag 23" "Not pending,Pending" textline " " eventfld.long 0x00 22. " HBCI22 ,Half of Block Transfer Complete Flag 22" "Not pending,Pending" eventfld.long 0x00 21. " HBCI21 ,Half of Block Transfer Complete Flag 21" "Not pending,Pending" eventfld.long 0x00 20. " HBCI20 ,Half of Block Transfer Complete Flag 20" "Not pending,Pending" textline " " eventfld.long 0x00 19. " HBCI19 ,Half of Block Transfer Complete Flag 19" "Not pending,Pending" eventfld.long 0x00 18. " HBCI18 ,Half of Block Transfer Complete Flag 18" "Not pending,Pending" eventfld.long 0x00 17. " HBCI17 ,Half of Block Transfer Complete Flag 17" "Not pending,Pending" textline " " eventfld.long 0x00 16. " HBCI16 ,Half of Block Transfer Complete Flag 16" "Not pending,Pending" eventfld.long 0x00 15. " HBCI15 ,Half of Block Transfer Complete Flag 15" "Not pending,Pending" eventfld.long 0x00 14. " HBCI14 ,Half of Block Transfer Complete Flag 14" "Not pending,Pending" textline " " eventfld.long 0x00 13. " HBCI13 ,Half of Block Transfer Complete Flag 13" "Not pending,Pending" eventfld.long 0x00 12. " HBCI12 ,Half of Block Transfer Complete Flag 12" "Not pending,Pending" eventfld.long 0x00 10. " HBCI10 ,Half of Block Transfer Complete Flag 10" "Not pending,Pending" textline " " eventfld.long 0x00 9. " HBCI9 ,Half of Block Transfer Complete Flag 9" "Not pending,Pending" eventfld.long 0x00 8. " HBCI8 ,Half of Block Transfer Complete Flag 8" "Not pending,Pending" eventfld.long 0x00 7. " HBCI7 ,Half of Block Transfer Complete Flag 7" "Not pending,Pending" textline " " eventfld.long 0x00 6. " HBCI6 ,Half of Block Transfer Complete Flag 6" "Not pending,Pending" eventfld.long 0x00 5. " HBCI5 ,Half of Block Transfer Complete Flag 5" "Not pending,Pending" eventfld.long 0x00 4. " HBCI4 ,Half of Block Transfer Complete Flag 4" "Not pending,Pending" textline " " eventfld.long 0x00 3. " HBCI3 ,Half of Block Transfer Complete Flag 3" "Not pending,Pending" eventfld.long 0x00 2. " HBCI2 ,Half of Block Transfer Complete Flag 2" "Not pending,Pending" eventfld.long 0x00 1. " HBCI1 ,Half of Block Transfer Complete Flag 1" "Not pending,Pending" textline " " eventfld.long 0x00 0. " HBCI0 ,Half of Block Transfer Complete Flag 0" "Not pending,Pending" group.long 0x13C++0x3 line.long 0x0 "BTCFLAG,BER INTERRUPT FLAG Register" eventfld.long 0x00 28. " BTCI28 ,Block Transfer Complete Flag 28" "Not pending,Pending" eventfld.long 0x00 27. " BTCI27 ,Block Transfer Complete Flag 27" "Not pending,Pending" eventfld.long 0x00 26. " BTCI26 ,Block Transfer Complete Flag 26" "Not pending,Pending" textline " " eventfld.long 0x00 25. " BTCI25 ,Block Transfer Complete Flag 25" "Not pending,Pending" eventfld.long 0x00 24. " BTCI24 ,Block Transfer Complete Flag 24" "Not pending,Pending" eventfld.long 0x00 23. " BTCI23 ,Block Transfer Complete Flag 23" "Not pending,Pending" textline " " eventfld.long 0x00 22. " BTCI22 ,Block Transfer Complete Flag 22" "Not pending,Pending" eventfld.long 0x00 21. " BTCI21 ,Block Transfer Complete Flag 21" "Not pending,Pending" eventfld.long 0x00 20. " BTCI20 ,Block Transfer Complete Flag 20" "Not pending,Pending" textline " " eventfld.long 0x00 19. " BTCI19 ,Block Transfer Complete Flag 19" "Not pending,Pending" eventfld.long 0x00 18. " BTCI18 ,Block Transfer Complete Flag 18" "Not pending,Pending" eventfld.long 0x00 17. " BTCI17 ,Block Transfer Complete Flag 17" "Not pending,Pending" textline " " eventfld.long 0x00 16. " BTCI16 ,Block Transfer Complete Flag 16" "Not pending,Pending" eventfld.long 0x00 15. " BTCI15 ,Block Transfer Complete Flag 15" "Not pending,Pending" eventfld.long 0x00 14. " BTCI14 ,Block Transfer Complete Flag 14" "Not pending,Pending" textline " " eventfld.long 0x00 13. " BTCI13 ,Block Transfer Complete Flag 13" "Not pending,Pending" eventfld.long 0x00 12. " BTCI12 ,Block Transfer Complete Flag 12" "Not pending,Pending" eventfld.long 0x00 10. " BTCI10 ,Block Transfer Complete Flag 10" "Not pending,Pending" textline " " eventfld.long 0x00 9. " BTCI9 ,Block Transfer Complete Flag 9" "Not pending,Pending" eventfld.long 0x00 8. " BTCI8 ,Block Transfer Complete Flag 8" "Not pending,Pending" eventfld.long 0x00 7. " BTCI7 ,Block Transfer Complete Flag 7" "Not pending,Pending" textline " " eventfld.long 0x00 6. " BTCI6 ,Block Transfer Complete Flag 6" "Not pending,Pending" eventfld.long 0x00 5. " BTCI5 ,Block Transfer Complete Flag 5" "Not pending,Pending" eventfld.long 0x00 4. " BTCI4 ,Block Transfer Complete Flag 4" "Not pending,Pending" textline " " eventfld.long 0x00 3. " BTCI3 ,Block Transfer Complete Flag 3" "Not pending,Pending" eventfld.long 0x00 2. " BTCI2 ,Block Transfer Complete Flag 2" "Not pending,Pending" eventfld.long 0x00 1. " BTCI1 ,Block Transfer Complete Flag 1" "Not pending,Pending" textline " " eventfld.long 0x00 0. " BTCI0 ,Block Transfer Complete Flag 0" "Not pending,Pending" group.long 0x144++0x3 line.long 0x0 "BERFLAG,BER INTERRUPT FLAG Register" eventfld.long 0x00 28. " BERI28 ,Bus Error Flag 28" "Not pending,Pending" eventfld.long 0x00 27. " BERI27 ,Bus Error Flag 27" "Not pending,Pending" eventfld.long 0x00 26. " BERI26 ,Bus Error Flag 26" "Not pending,Pending" textline " " eventfld.long 0x00 25. " BERI25 ,Bus Error Flag 25" "Not pending,Pending" eventfld.long 0x00 24. " BERI24 ,Bus Error Flag 24" "Not pending,Pending" eventfld.long 0x00 23. " BERI23 ,Bus Error Flag 23" "Not pending,Pending" textline " " eventfld.long 0x00 22. " BERI22 ,Bus Error Flag 22" "Not pending,Pending" eventfld.long 0x00 21. " BERI21 ,Bus Error Flag 21" "Not pending,Pending" eventfld.long 0x00 20. " BERI20 ,Bus Error Flag 20" "Not pending,Pending" textline " " eventfld.long 0x00 19. " BERI19 ,Bus Error Flag 19" "Not pending,Pending" eventfld.long 0x00 18. " BERI18 ,Bus Error Flag 18" "Not pending,Pending" eventfld.long 0x00 17. " BERI17 ,Bus Error Flag 17" "Not pending,Pending" textline " " eventfld.long 0x00 16. " BERI16 ,Bus Error Flag 16" "Not pending,Pending" eventfld.long 0x00 15. " BERI15 ,Bus Error Flag 15" "Not pending,Pending" eventfld.long 0x00 14. " BERI14 ,Bus Error Flag 14" "Not pending,Pending" textline " " eventfld.long 0x00 13. " BERI13 ,Bus Error Flag 13" "Not pending,Pending" eventfld.long 0x00 12. " BERI12 ,Bus Error Flag 12" "Not pending,Pending" eventfld.long 0x00 10. " BERI10 ,Bus Error Flag 10" "Not pending,Pending" textline " " eventfld.long 0x00 9. " BERI9 ,Bus Error Flag 9" "Not pending,Pending" eventfld.long 0x00 8. " BERI8 ,Bus Error Flag 8" "Not pending,Pending" eventfld.long 0x00 7. " BERI7 ,Bus Error Flag 7" "Not pending,Pending" textline " " eventfld.long 0x00 6. " BERI6 ,Bus Error Flag 6" "Not pending,Pending" eventfld.long 0x00 5. " BERI5 ,Bus Error Flag 5" "Not pending,Pending" eventfld.long 0x00 4. " BERI4 ,Bus Error Flag 4" "Not pending,Pending" textline " " eventfld.long 0x00 3. " BERI3 ,Bus Error Flag 3" "Not pending,Pending" eventfld.long 0x00 2. " BERI2 ,Bus Error Flag 2" "Not pending,Pending" eventfld.long 0x00 1. " BERI1 ,Bus Error Flag 1" "Not pending,Pending" textline " " eventfld.long 0x00 0. " BERI0 ,Bus Error Flag 0" "Not pending,Pending" tree.end width 0xc tree "Interrupt Channel Offset Registers" hgroup.long 0x14C++0x3 hide.long 0x0 "FTCAOFFSET,FTCA INTERRUPT CHANNEL OFFSET Register" in hgroup.long 0x150++0x3 hide.long 0x0 "LFSAOFFSET,LFSA INTERRUPT CHANNEL OFFSET Register" in hgroup.long 0x154++0x3 hide.long 0x0 "HBCAOFFSET,HBCA INTERRUPT CHANNEL OFFSET Register" in hgroup.long 0x158++0x3 hide.long 0x0 "BTCAOFFSET,BTCA INTERRUPT CHANNEL OFFSET Register" in hgroup.long 0x15C++0x3 hide.long 0x0 "BERAOFFSET,BERA INTERRUPT CHANNEL OFFSET Register" in hgroup.long 0x160++0x3 hide.long 0x0 "FTCBOFFSET,FTCB INTERRUPT CHANNEL OFFSET Register" in hgroup.long 0x164++0x3 hide.long 0x0 "LSFBOFFSET,LFSB INTERRUPT CHANNEL OFFSET Register" in hgroup.long 0x168++0x3 hide.long 0x0 "HBCBOFFSET,HBCB INTERRUPT CHANNEL OFFSET Register" in hgroup.long 0x16C++0x3 hide.long 0x0 "BTCBOFFSET,BTCB INTERRUPT CHANNEL OFFSET Register" in hgroup.long 0x170++0x3 hide.long 0x0 "BERBOFFSET,BERB INTERRUPT CHANNEL OFFSET Register" in group.long 0x178++0x3 tree.end width 0x8 textline " " group.long 0x178++0x3 line.long 0x0 "PTCRL,PORT CONTROL Register" bitfld.long 0x00 24. " PENDB ,Port B Transactions Pending" "Not pending,Pending" bitfld.long 0x00 18. " BYB ,Bypass FIFO B" "Not limited,Limited" bitfld.long 0x00 17. " PSFRHQPB ,Port B High Priority Queue Priority Scheme" "Fixed,Rotated" textline " " bitfld.long 0x00 16. " PSFRLQPB ,Port B Low Priority Queue Priority Scheme" "Fixed,Rotated" bitfld.long 0x00 8. " PENDA ,Port A Transactions Pending" "Not pending,Pending" bitfld.long 0x00 2. " BYA ,Bypass FIFO A" "Not limited,Limited" textline " " bitfld.long 0x00 1. " PSFRHQPA ,Port A High Priority Queue Priority Scheme" "Fixed,Rotated" bitfld.long 0x00 0. " PSFRLQPA ,Port A Low Priority Queue Priority Scheme" "Fixed,Rotated" group.long 0x17C++0x3 line.long 0x0 "RTCTRL,RAM TEST CONTROL" bitfld.long 0x00 0. " RTC ,RAM Test Control" "Not accessed,Accessed" group.long 0x180++0x3 line.long 0x0 "DCTRL,DEBUG CONTROL" bitfld.long 0x00 24.--28. " CHNUM ,Channel Number" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Reserved,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,?..." eventfld.long 0x00 16. " DMADBGS ,DMA Debug Status" "Not detected,Detected" bitfld.long 0x00 0. " DBGEN ,Debug Enable" "Disabled,Enabled" group.long 0x184++0x3 line.long 0x0 "WPR,Watch Point Register" width 0x8 group.long 0x188++0x3 line.long 0x0 "WMR,WATCH MASK Register" bitfld.long 0x00 31. " WM ,Watch Mask 31" "0,1" bitfld.long 0x00 30. ",Watch Mask 30" "0,1" bitfld.long 0x00 29. ",Watch Mask 29" "0,1" bitfld.long 0x00 28. ",Watch Mask 28" "0,1" bitfld.long 0x00 27. ",Watch Mask 27" "0,1" bitfld.long 0x00 26. ",Watch Mask 26" "0,1" bitfld.long 0x00 25. ",Watch Mask 25" "0,1" bitfld.long 0x00 24. ",Watch Mask 24" "0,1" bitfld.long 0x00 23. ",Watch Mask 23" "0,1" bitfld.long 0x00 22. ",Watch Mask 22" "0,1" bitfld.long 0x00 21. ",Watch Mask 21" "0,1" bitfld.long 0x00 20. ",Watch Mask 20" "0,1" bitfld.long 0x00 19. ",Watch Mask 19" "0,1" bitfld.long 0x00 18. ",Watch Mask 18" "0,1" bitfld.long 0x00 17. ",Watch Mask 17" "0,1" bitfld.long 0x00 16. ",Watch Mask 16" "0,1" bitfld.long 0x00 15. ",Watch Mask 15" "0,1" bitfld.long 0x00 14. ",Watch Mask 14" "0,1" bitfld.long 0x00 13. ",Watch Mask 13" "0,1" bitfld.long 0x00 12. ",Watch Mask 12" "0,1" bitfld.long 0x00 11. ",Watch Mask 11" "0,1" bitfld.long 0x00 10. ",Watch Mask 10" "0,1" bitfld.long 0x00 9. ",Watch Mask 9" "0,1" bitfld.long 0x00 8. ",Watch Mask 8" "0,1" bitfld.long 0x00 7. ",Watch Mask 7" "0,1" bitfld.long 0x00 6. ",Watch Mask 6" "0,1" bitfld.long 0x00 5. ",Watch Mask 5" "0,1" bitfld.long 0x00 4. ",Watch Mask 4" "0,1" bitfld.long 0x00 3. ",Watch Mask 3" "0,1" bitfld.long 0x00 2. ",Watch Mask 2" "0,1" bitfld.long 0x00 1. ",Watch Mask 1" "0,1" bitfld.long 0x00 0. ",Watch Mask 0" "0,1" width 0xb tree "Active Channel Registers" group.long 0x18C++0x3 line.long 0x0 "PAACSADDR,PORTB ACTIVE CHANNEL SOURCE ADDRESS Register" group.long 0x190++0x3 line.long 0x0 "PAACDADDR,PORTA ACTIVE CHANNEL DESTINATION ADDRESS Register" group.long 0x194++0x3 line.long 0x0 "PAACTC,PORTA ACTIVE CHANNEL TRANSFER COUNT Register" hexmask.long.word 0x00 16.--28. 1. " PAFTCOUNT ,Port A Active Channel Frame Count" hexmask.long.word 0x00 0.--12. 1. " PAETCOUNT ,Port A Active Channel Element Count" group.long 0x198++0x3 line.long 0x0 "PBACSADDR,PORTB ACTIVE CHANNEL SOURCE ADDRESS Register" group.long 0x19C++0x3 line.long 0x0 "PBACDADDR,PORTB ACTIVE CHANNEL DESTINATION ADDRESS Register" group.long 0x1A0++0x3 line.long 0x0 "PBACTC,PORTB ACTIVE CHANNEL TRANSFER COUNT Register" hexmask.long.word 0x00 16.--28. 1. " PBFTCOUNT ,Port B Active Channel Frame Count" hexmask.long.word 0x00 0.--12. 1. " PBETCOUNT ,Port B Active Channel Element Count" tree.end width 8. textline " " group.long 0x1A8++0x3 line.long 0x0 "DMAPCR,PARITY CONTROL Register" bitfld.long 0x00 16. " ERRA ,Error Action" "Unchanged,Disabled" bitfld.long 0x00 8. " TEST ,Test" "Not mapped,Mapped" bitfld.long 0x00 0.--3. " PARITY_ENA ,Parity Error Detection Enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" group.long 0x1AC++0x3 line.long 0x0 "DMAPAR,Parity Error Address Register" eventfld.long 0x00 24. " EDFLG ,Parity Error Detection Flag" "No error,Error" hexmask.long.word 0x00 0.--11. 1. " ERROR_ADDRESS ,Error Address" width 0xb tree "DMA Memory Protection Registers" group.long 0x1B0++0x3 line.long 0x0 "DMAMPCTRL,Memory Protection Control Register" bitfld.long 0x00 28. " INT3AB ,Interrupt Assignment of Region 3 to group A/B" "VIM,DSP" bitfld.long 0x00 27. " INT3ENA ,Interrupt Enable of Region 3" "Disabled,Enabled" bitfld.long 0x00 25.--26. " REG3AP ,Region 3 Access Permission" "R/W,Read,Write,Not allowed" textline " " bitfld.long 0x00 24. " REG3ENA ,Region 3 Enable" "Disabled,Enabled" bitfld.long 0x00 20. " INT2AB ,Interrupt Assignment of Region 2 to group A/B" "VIM,DSP" bitfld.long 0x00 19. " INT2ENA ,Interrupt Enable of Region 2" "Disabled,Enabled" textline " " bitfld.long 0x00 17.--18. " REG2AP ,Region 2 Access Permission" "R/W,Read,Write,Not allowed" bitfld.long 0x00 16. " REG2ENA ,Region 2 Enable" "Disabled,Enabled" bitfld.long 0x00 12. " INT1AB ,Interrupt Assignment of Region 1 to group A/B" "VIM,DSP" textline " " bitfld.long 0x00 11. " INT1ENA ,Interrupt Enable of Region 1" "Disabled,Enabled" bitfld.long 0x00 9.--10. " REG1AP ,Region 1 Access Permission" "R/W,Read,Write,Not allowed" bitfld.long 0x00 8. " REG1ENA ,Region 1 Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " INT0AB ,Interrupt Assignment of Region 0 to group A/B" "VIM,DSP" bitfld.long 0x00 3. " INT0ENA ,Interrupt Enable of Region 0" "Disabled,Enabled" bitfld.long 0x00 1.--2. " REG0AP ,Region 0 Access Permission" "R/W,Read,Write,Not allowed" textline " " bitfld.long 0x00 0. " REG0ENA ,Region 0 Enable" "Disabled,Enabled" group.long 0x1B4++0x3 line.long 0x0 "DMAMPST,Memory Protection Status Register" eventfld.long 0x00 24. " REG3FT ,Region 3 Fault" "Not detected,Detected" eventfld.long 0x00 16. " REG2FT ,Region 2 Fault" "Not detected,Detected" eventfld.long 0x00 8. " REG1FT ,Region 1 Fault" "Not detected,Detected" textline " " eventfld.long 0x00 0. " REG0FT ,Region 0 Fault" "Not detected,Detected" group.long 0x1B8++0x3 line.long 0x0 "DMAPR0S,Defines Starting Address of Region 0" group.long 0x1BC++0x3 line.long 0x0 "DMAPR0E,Defines end Address of Region 0" group.long 0x1C0++0x3 line.long 0x0 "DMAPR1S,Defines Starting Address of Region 0" group.long 0x1C4++0x3 line.long 0x0 "DMAPR1E,Defines end Address of Region 1" group.long 0x1C8++0x3 line.long 0x0 "DMAPR2S,Defines Starting Address of Region 2" group.long 0x1CC++0x3 line.long 0x0 "DMAPR2E,Defines end Address of Region 2" group.long 0x1D0++0x3 line.long 0x0 "DMAPR3S,Defines Starting Address of Region 3" group.long 0x1D4++0x3 line.long 0x0 "DMAPR3E,Defines end Address of Region 3" tree.end base ad:0xFFF80000 tree "Control Packet Registers" width 9. tree.open "Primary Control Packet Registers" tree "Primary Control Packet 0" group.long (0x0)++0x0b line.long 0x00 "ISADDR,Initial Source Address Register" line.long 0x04 "IDADDR,Initial Destination Address Register" line.long 0x08 "ITCOUNT,Initial Transfer Count Register" hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial Frame Transfer Count" hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial Element Transfer Count" group.long (0x0+0x10)++0x0b line.long 0x00 "CHCTRL,Channel Control Register" bitfld.long 0x00 16.--21. " CHAIN ,Next Channel to be Triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Reserved,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,?..." bitfld.long 0x00 14.--15. " RES ,Read Element Size" "8 bits,16 bits,32 bits,64 bits" bitfld.long 0x00 12.--13. " WES ,Write Element Size" "8 bits,16 bits,32 bits,64 bits" textline " " bitfld.long 0x00 8. " TTYPE ,Transfer Type" "Frame,Block" bitfld.long 0x00 3.--4. " ADDMR ,Addressing Mode Read" "Constant,Post-increment,Reserved,Indexed" textline " " bitfld.long 0x00 1.--2. " ADDMW ,Addressing Mode Write" "Constant,Post-increment,Reserved,Indexed" bitfld.long 0x00 0. " AIM ,Autoinitiation Mode" "Single block,Autoinitiation" line.long 0x04 "EIOFF,Element Index Offset Register" hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination Address Element Index" hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source Address Element Index" line.long 0x08 "FIOFF,Frame Index Offset Register" hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination Address Frame Index" hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source Address Frame Index" tree.end tree "Primary Control Packet 1" group.long (0x20)++0x0b line.long 0x00 "ISADDR,Initial Source Address Register" line.long 0x04 "IDADDR,Initial Destination Address Register" line.long 0x08 "ITCOUNT,Initial Transfer Count Register" hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial Frame Transfer Count" hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial Element Transfer Count" group.long (0x20+0x10)++0x0b line.long 0x00 "CHCTRL,Channel Control Register" bitfld.long 0x00 16.--21. " CHAIN ,Next Channel to be Triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Reserved,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,?..." bitfld.long 0x00 14.--15. " RES ,Read Element Size" "8 bits,16 bits,32 bits,64 bits" bitfld.long 0x00 12.--13. " WES ,Write Element Size" "8 bits,16 bits,32 bits,64 bits" textline " " bitfld.long 0x00 8. " TTYPE ,Transfer Type" "Frame,Block" bitfld.long 0x00 3.--4. " ADDMR ,Addressing Mode Read" "Constant,Post-increment,Reserved,Indexed" textline " " bitfld.long 0x00 1.--2. " ADDMW ,Addressing Mode Write" "Constant,Post-increment,Reserved,Indexed" bitfld.long 0x00 0. " AIM ,Autoinitiation Mode" "Single block,Autoinitiation" line.long 0x04 "EIOFF,Element Index Offset Register" hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination Address Element Index" hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source Address Element Index" line.long 0x08 "FIOFF,Frame Index Offset Register" hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination Address Frame Index" hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source Address Frame Index" tree.end tree "Primary Control Packet 2" group.long (0x40)++0x0b line.long 0x00 "ISADDR,Initial Source Address Register" line.long 0x04 "IDADDR,Initial Destination Address Register" line.long 0x08 "ITCOUNT,Initial Transfer Count Register" hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial Frame Transfer Count" hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial Element Transfer Count" group.long (0x40+0x10)++0x0b line.long 0x00 "CHCTRL,Channel Control Register" bitfld.long 0x00 16.--21. " CHAIN ,Next Channel to be Triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Reserved,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,?..." bitfld.long 0x00 14.--15. " RES ,Read Element Size" "8 bits,16 bits,32 bits,64 bits" bitfld.long 0x00 12.--13. " WES ,Write Element Size" "8 bits,16 bits,32 bits,64 bits" textline " " bitfld.long 0x00 8. " TTYPE ,Transfer Type" "Frame,Block" bitfld.long 0x00 3.--4. " ADDMR ,Addressing Mode Read" "Constant,Post-increment,Reserved,Indexed" textline " " bitfld.long 0x00 1.--2. " ADDMW ,Addressing Mode Write" "Constant,Post-increment,Reserved,Indexed" bitfld.long 0x00 0. " AIM ,Autoinitiation Mode" "Single block,Autoinitiation" line.long 0x04 "EIOFF,Element Index Offset Register" hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination Address Element Index" hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source Address Element Index" line.long 0x08 "FIOFF,Frame Index Offset Register" hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination Address Frame Index" hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source Address Frame Index" tree.end tree "Primary Control Packet 3" group.long (0x60)++0x0b line.long 0x00 "ISADDR,Initial Source Address Register" line.long 0x04 "IDADDR,Initial Destination Address Register" line.long 0x08 "ITCOUNT,Initial Transfer Count Register" hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial Frame Transfer Count" hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial Element Transfer Count" group.long (0x60+0x10)++0x0b line.long 0x00 "CHCTRL,Channel Control Register" bitfld.long 0x00 16.--21. " CHAIN ,Next Channel to be Triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Reserved,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,?..." bitfld.long 0x00 14.--15. " RES ,Read Element Size" "8 bits,16 bits,32 bits,64 bits" bitfld.long 0x00 12.--13. " WES ,Write Element Size" "8 bits,16 bits,32 bits,64 bits" textline " " bitfld.long 0x00 8. " TTYPE ,Transfer Type" "Frame,Block" bitfld.long 0x00 3.--4. " ADDMR ,Addressing Mode Read" "Constant,Post-increment,Reserved,Indexed" textline " " bitfld.long 0x00 1.--2. " ADDMW ,Addressing Mode Write" "Constant,Post-increment,Reserved,Indexed" bitfld.long 0x00 0. " AIM ,Autoinitiation Mode" "Single block,Autoinitiation" line.long 0x04 "EIOFF,Element Index Offset Register" hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination Address Element Index" hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source Address Element Index" line.long 0x08 "FIOFF,Frame Index Offset Register" hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination Address Frame Index" hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source Address Frame Index" tree.end tree "Primary Control Packet 4" group.long (0x80)++0x0b line.long 0x00 "ISADDR,Initial Source Address Register" line.long 0x04 "IDADDR,Initial Destination Address Register" line.long 0x08 "ITCOUNT,Initial Transfer Count Register" hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial Frame Transfer Count" hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial Element Transfer Count" group.long (0x80+0x10)++0x0b line.long 0x00 "CHCTRL,Channel Control Register" bitfld.long 0x00 16.--21. " CHAIN ,Next Channel to be Triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Reserved,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,?..." bitfld.long 0x00 14.--15. " RES ,Read Element Size" "8 bits,16 bits,32 bits,64 bits" bitfld.long 0x00 12.--13. " WES ,Write Element Size" "8 bits,16 bits,32 bits,64 bits" textline " " bitfld.long 0x00 8. " TTYPE ,Transfer Type" "Frame,Block" bitfld.long 0x00 3.--4. " ADDMR ,Addressing Mode Read" "Constant,Post-increment,Reserved,Indexed" textline " " bitfld.long 0x00 1.--2. " ADDMW ,Addressing Mode Write" "Constant,Post-increment,Reserved,Indexed" bitfld.long 0x00 0. " AIM ,Autoinitiation Mode" "Single block,Autoinitiation" line.long 0x04 "EIOFF,Element Index Offset Register" hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination Address Element Index" hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source Address Element Index" line.long 0x08 "FIOFF,Frame Index Offset Register" hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination Address Frame Index" hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source Address Frame Index" tree.end tree "Primary Control Packet 5" group.long (0xA0)++0x0b line.long 0x00 "ISADDR,Initial Source Address Register" line.long 0x04 "IDADDR,Initial Destination Address Register" line.long 0x08 "ITCOUNT,Initial Transfer Count Register" hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial Frame Transfer Count" hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial Element Transfer Count" group.long (0xA0+0x10)++0x0b line.long 0x00 "CHCTRL,Channel Control Register" bitfld.long 0x00 16.--21. " CHAIN ,Next Channel to be Triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Reserved,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,?..." bitfld.long 0x00 14.--15. " RES ,Read Element Size" "8 bits,16 bits,32 bits,64 bits" bitfld.long 0x00 12.--13. " WES ,Write Element Size" "8 bits,16 bits,32 bits,64 bits" textline " " bitfld.long 0x00 8. " TTYPE ,Transfer Type" "Frame,Block" bitfld.long 0x00 3.--4. " ADDMR ,Addressing Mode Read" "Constant,Post-increment,Reserved,Indexed" textline " " bitfld.long 0x00 1.--2. " ADDMW ,Addressing Mode Write" "Constant,Post-increment,Reserved,Indexed" bitfld.long 0x00 0. " AIM ,Autoinitiation Mode" "Single block,Autoinitiation" line.long 0x04 "EIOFF,Element Index Offset Register" hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination Address Element Index" hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source Address Element Index" line.long 0x08 "FIOFF,Frame Index Offset Register" hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination Address Frame Index" hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source Address Frame Index" tree.end tree "Primary Control Packet 6" group.long (0xC0)++0x0b line.long 0x00 "ISADDR,Initial Source Address Register" line.long 0x04 "IDADDR,Initial Destination Address Register" line.long 0x08 "ITCOUNT,Initial Transfer Count Register" hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial Frame Transfer Count" hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial Element Transfer Count" group.long (0xC0+0x10)++0x0b line.long 0x00 "CHCTRL,Channel Control Register" bitfld.long 0x00 16.--21. " CHAIN ,Next Channel to be Triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Reserved,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,?..." bitfld.long 0x00 14.--15. " RES ,Read Element Size" "8 bits,16 bits,32 bits,64 bits" bitfld.long 0x00 12.--13. " WES ,Write Element Size" "8 bits,16 bits,32 bits,64 bits" textline " " bitfld.long 0x00 8. " TTYPE ,Transfer Type" "Frame,Block" bitfld.long 0x00 3.--4. " ADDMR ,Addressing Mode Read" "Constant,Post-increment,Reserved,Indexed" textline " " bitfld.long 0x00 1.--2. " ADDMW ,Addressing Mode Write" "Constant,Post-increment,Reserved,Indexed" bitfld.long 0x00 0. " AIM ,Autoinitiation Mode" "Single block,Autoinitiation" line.long 0x04 "EIOFF,Element Index Offset Register" hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination Address Element Index" hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source Address Element Index" line.long 0x08 "FIOFF,Frame Index Offset Register" hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination Address Frame Index" hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source Address Frame Index" tree.end tree "Primary Control Packet 7" group.long (0xE0)++0x0b line.long 0x00 "ISADDR,Initial Source Address Register" line.long 0x04 "IDADDR,Initial Destination Address Register" line.long 0x08 "ITCOUNT,Initial Transfer Count Register" hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial Frame Transfer Count" hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial Element Transfer Count" group.long (0xE0+0x10)++0x0b line.long 0x00 "CHCTRL,Channel Control Register" bitfld.long 0x00 16.--21. " CHAIN ,Next Channel to be Triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Reserved,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,?..." bitfld.long 0x00 14.--15. " RES ,Read Element Size" "8 bits,16 bits,32 bits,64 bits" bitfld.long 0x00 12.--13. " WES ,Write Element Size" "8 bits,16 bits,32 bits,64 bits" textline " " bitfld.long 0x00 8. " TTYPE ,Transfer Type" "Frame,Block" bitfld.long 0x00 3.--4. " ADDMR ,Addressing Mode Read" "Constant,Post-increment,Reserved,Indexed" textline " " bitfld.long 0x00 1.--2. " ADDMW ,Addressing Mode Write" "Constant,Post-increment,Reserved,Indexed" bitfld.long 0x00 0. " AIM ,Autoinitiation Mode" "Single block,Autoinitiation" line.long 0x04 "EIOFF,Element Index Offset Register" hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination Address Element Index" hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source Address Element Index" line.long 0x08 "FIOFF,Frame Index Offset Register" hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination Address Frame Index" hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source Address Frame Index" tree.end tree "Primary Control Packet 8" group.long (0x100)++0x0b line.long 0x00 "ISADDR,Initial Source Address Register" line.long 0x04 "IDADDR,Initial Destination Address Register" line.long 0x08 "ITCOUNT,Initial Transfer Count Register" hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial Frame Transfer Count" hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial Element Transfer Count" group.long (0x100+0x10)++0x0b line.long 0x00 "CHCTRL,Channel Control Register" bitfld.long 0x00 16.--21. " CHAIN ,Next Channel to be Triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Reserved,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,?..." bitfld.long 0x00 14.--15. " RES ,Read Element Size" "8 bits,16 bits,32 bits,64 bits" bitfld.long 0x00 12.--13. " WES ,Write Element Size" "8 bits,16 bits,32 bits,64 bits" textline " " bitfld.long 0x00 8. " TTYPE ,Transfer Type" "Frame,Block" bitfld.long 0x00 3.--4. " ADDMR ,Addressing Mode Read" "Constant,Post-increment,Reserved,Indexed" textline " " bitfld.long 0x00 1.--2. " ADDMW ,Addressing Mode Write" "Constant,Post-increment,Reserved,Indexed" bitfld.long 0x00 0. " AIM ,Autoinitiation Mode" "Single block,Autoinitiation" line.long 0x04 "EIOFF,Element Index Offset Register" hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination Address Element Index" hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source Address Element Index" line.long 0x08 "FIOFF,Frame Index Offset Register" hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination Address Frame Index" hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source Address Frame Index" tree.end tree "Primary Control Packet 9" group.long (0x120)++0x0b line.long 0x00 "ISADDR,Initial Source Address Register" line.long 0x04 "IDADDR,Initial Destination Address Register" line.long 0x08 "ITCOUNT,Initial Transfer Count Register" hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial Frame Transfer Count" hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial Element Transfer Count" group.long (0x120+0x10)++0x0b line.long 0x00 "CHCTRL,Channel Control Register" bitfld.long 0x00 16.--21. " CHAIN ,Next Channel to be Triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Reserved,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,?..." bitfld.long 0x00 14.--15. " RES ,Read Element Size" "8 bits,16 bits,32 bits,64 bits" bitfld.long 0x00 12.--13. " WES ,Write Element Size" "8 bits,16 bits,32 bits,64 bits" textline " " bitfld.long 0x00 8. " TTYPE ,Transfer Type" "Frame,Block" bitfld.long 0x00 3.--4. " ADDMR ,Addressing Mode Read" "Constant,Post-increment,Reserved,Indexed" textline " " bitfld.long 0x00 1.--2. " ADDMW ,Addressing Mode Write" "Constant,Post-increment,Reserved,Indexed" bitfld.long 0x00 0. " AIM ,Autoinitiation Mode" "Single block,Autoinitiation" line.long 0x04 "EIOFF,Element Index Offset Register" hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination Address Element Index" hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source Address Element Index" line.long 0x08 "FIOFF,Frame Index Offset Register" hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination Address Frame Index" hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source Address Frame Index" tree.end tree "Primary Control Packet 10" group.long (0x140)++0x0b line.long 0x00 "ISADDR,Initial Source Address Register" line.long 0x04 "IDADDR,Initial Destination Address Register" line.long 0x08 "ITCOUNT,Initial Transfer Count Register" hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial Frame Transfer Count" hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial Element Transfer Count" group.long (0x140+0x10)++0x0b line.long 0x00 "CHCTRL,Channel Control Register" bitfld.long 0x00 16.--21. " CHAIN ,Next Channel to be Triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Reserved,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,?..." bitfld.long 0x00 14.--15. " RES ,Read Element Size" "8 bits,16 bits,32 bits,64 bits" bitfld.long 0x00 12.--13. " WES ,Write Element Size" "8 bits,16 bits,32 bits,64 bits" textline " " bitfld.long 0x00 8. " TTYPE ,Transfer Type" "Frame,Block" bitfld.long 0x00 3.--4. " ADDMR ,Addressing Mode Read" "Constant,Post-increment,Reserved,Indexed" textline " " bitfld.long 0x00 1.--2. " ADDMW ,Addressing Mode Write" "Constant,Post-increment,Reserved,Indexed" bitfld.long 0x00 0. " AIM ,Autoinitiation Mode" "Single block,Autoinitiation" line.long 0x04 "EIOFF,Element Index Offset Register" hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination Address Element Index" hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source Address Element Index" line.long 0x08 "FIOFF,Frame Index Offset Register" hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination Address Frame Index" hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source Address Frame Index" tree.end tree "Primary Control Packet 12" group.long (0x180)++0x0b line.long 0x00 "ISADDR,Initial Source Address Register" line.long 0x04 "IDADDR,Initial Destination Address Register" line.long 0x08 "ITCOUNT,Initial Transfer Count Register" hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial Frame Transfer Count" hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial Element Transfer Count" group.long (0x180+0x10)++0x0b line.long 0x00 "CHCTRL,Channel Control Register" bitfld.long 0x00 16.--21. " CHAIN ,Next Channel to be Triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Reserved,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,?..." bitfld.long 0x00 14.--15. " RES ,Read Element Size" "8 bits,16 bits,32 bits,64 bits" bitfld.long 0x00 12.--13. " WES ,Write Element Size" "8 bits,16 bits,32 bits,64 bits" textline " " bitfld.long 0x00 8. " TTYPE ,Transfer Type" "Frame,Block" bitfld.long 0x00 3.--4. " ADDMR ,Addressing Mode Read" "Constant,Post-increment,Reserved,Indexed" textline " " bitfld.long 0x00 1.--2. " ADDMW ,Addressing Mode Write" "Constant,Post-increment,Reserved,Indexed" bitfld.long 0x00 0. " AIM ,Autoinitiation Mode" "Single block,Autoinitiation" line.long 0x04 "EIOFF,Element Index Offset Register" hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination Address Element Index" hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source Address Element Index" line.long 0x08 "FIOFF,Frame Index Offset Register" hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination Address Frame Index" hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source Address Frame Index" tree.end tree "Primary Control Packet 13" group.long (0x1A0)++0x0b line.long 0x00 "ISADDR,Initial Source Address Register" line.long 0x04 "IDADDR,Initial Destination Address Register" line.long 0x08 "ITCOUNT,Initial Transfer Count Register" hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial Frame Transfer Count" hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial Element Transfer Count" group.long (0x1A0+0x10)++0x0b line.long 0x00 "CHCTRL,Channel Control Register" bitfld.long 0x00 16.--21. " CHAIN ,Next Channel to be Triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Reserved,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,?..." bitfld.long 0x00 14.--15. " RES ,Read Element Size" "8 bits,16 bits,32 bits,64 bits" bitfld.long 0x00 12.--13. " WES ,Write Element Size" "8 bits,16 bits,32 bits,64 bits" textline " " bitfld.long 0x00 8. " TTYPE ,Transfer Type" "Frame,Block" bitfld.long 0x00 3.--4. " ADDMR ,Addressing Mode Read" "Constant,Post-increment,Reserved,Indexed" textline " " bitfld.long 0x00 1.--2. " ADDMW ,Addressing Mode Write" "Constant,Post-increment,Reserved,Indexed" bitfld.long 0x00 0. " AIM ,Autoinitiation Mode" "Single block,Autoinitiation" line.long 0x04 "EIOFF,Element Index Offset Register" hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination Address Element Index" hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source Address Element Index" line.long 0x08 "FIOFF,Frame Index Offset Register" hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination Address Frame Index" hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source Address Frame Index" tree.end tree "Primary Control Packet 14" group.long (0x1C0)++0x0b line.long 0x00 "ISADDR,Initial Source Address Register" line.long 0x04 "IDADDR,Initial Destination Address Register" line.long 0x08 "ITCOUNT,Initial Transfer Count Register" hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial Frame Transfer Count" hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial Element Transfer Count" group.long (0x1C0+0x10)++0x0b line.long 0x00 "CHCTRL,Channel Control Register" bitfld.long 0x00 16.--21. " CHAIN ,Next Channel to be Triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Reserved,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,?..." bitfld.long 0x00 14.--15. " RES ,Read Element Size" "8 bits,16 bits,32 bits,64 bits" bitfld.long 0x00 12.--13. " WES ,Write Element Size" "8 bits,16 bits,32 bits,64 bits" textline " " bitfld.long 0x00 8. " TTYPE ,Transfer Type" "Frame,Block" bitfld.long 0x00 3.--4. " ADDMR ,Addressing Mode Read" "Constant,Post-increment,Reserved,Indexed" textline " " bitfld.long 0x00 1.--2. " ADDMW ,Addressing Mode Write" "Constant,Post-increment,Reserved,Indexed" bitfld.long 0x00 0. " AIM ,Autoinitiation Mode" "Single block,Autoinitiation" line.long 0x04 "EIOFF,Element Index Offset Register" hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination Address Element Index" hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source Address Element Index" line.long 0x08 "FIOFF,Frame Index Offset Register" hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination Address Frame Index" hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source Address Frame Index" tree.end tree "Primary Control Packet 15" group.long (0x1E0)++0x0b line.long 0x00 "ISADDR,Initial Source Address Register" line.long 0x04 "IDADDR,Initial Destination Address Register" line.long 0x08 "ITCOUNT,Initial Transfer Count Register" hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial Frame Transfer Count" hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial Element Transfer Count" group.long (0x1E0+0x10)++0x0b line.long 0x00 "CHCTRL,Channel Control Register" bitfld.long 0x00 16.--21. " CHAIN ,Next Channel to be Triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Reserved,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,?..." bitfld.long 0x00 14.--15. " RES ,Read Element Size" "8 bits,16 bits,32 bits,64 bits" bitfld.long 0x00 12.--13. " WES ,Write Element Size" "8 bits,16 bits,32 bits,64 bits" textline " " bitfld.long 0x00 8. " TTYPE ,Transfer Type" "Frame,Block" bitfld.long 0x00 3.--4. " ADDMR ,Addressing Mode Read" "Constant,Post-increment,Reserved,Indexed" textline " " bitfld.long 0x00 1.--2. " ADDMW ,Addressing Mode Write" "Constant,Post-increment,Reserved,Indexed" bitfld.long 0x00 0. " AIM ,Autoinitiation Mode" "Single block,Autoinitiation" line.long 0x04 "EIOFF,Element Index Offset Register" hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination Address Element Index" hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source Address Element Index" line.long 0x08 "FIOFF,Frame Index Offset Register" hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination Address Frame Index" hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source Address Frame Index" tree.end tree "Primary Control Packet 16" group.long (0x200)++0x0b line.long 0x00 "ISADDR,Initial Source Address Register" line.long 0x04 "IDADDR,Initial Destination Address Register" line.long 0x08 "ITCOUNT,Initial Transfer Count Register" hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial Frame Transfer Count" hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial Element Transfer Count" group.long (0x200+0x10)++0x0b line.long 0x00 "CHCTRL,Channel Control Register" bitfld.long 0x00 16.--21. " CHAIN ,Next Channel to be Triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Reserved,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,?..." bitfld.long 0x00 14.--15. " RES ,Read Element Size" "8 bits,16 bits,32 bits,64 bits" bitfld.long 0x00 12.--13. " WES ,Write Element Size" "8 bits,16 bits,32 bits,64 bits" textline " " bitfld.long 0x00 8. " TTYPE ,Transfer Type" "Frame,Block" bitfld.long 0x00 3.--4. " ADDMR ,Addressing Mode Read" "Constant,Post-increment,Reserved,Indexed" textline " " bitfld.long 0x00 1.--2. " ADDMW ,Addressing Mode Write" "Constant,Post-increment,Reserved,Indexed" bitfld.long 0x00 0. " AIM ,Autoinitiation Mode" "Single block,Autoinitiation" line.long 0x04 "EIOFF,Element Index Offset Register" hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination Address Element Index" hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source Address Element Index" line.long 0x08 "FIOFF,Frame Index Offset Register" hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination Address Frame Index" hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source Address Frame Index" tree.end tree "Primary Control Packet 17" group.long (0x220)++0x0b line.long 0x00 "ISADDR,Initial Source Address Register" line.long 0x04 "IDADDR,Initial Destination Address Register" line.long 0x08 "ITCOUNT,Initial Transfer Count Register" hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial Frame Transfer Count" hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial Element Transfer Count" group.long (0x220+0x10)++0x0b line.long 0x00 "CHCTRL,Channel Control Register" bitfld.long 0x00 16.--21. " CHAIN ,Next Channel to be Triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Reserved,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,?..." bitfld.long 0x00 14.--15. " RES ,Read Element Size" "8 bits,16 bits,32 bits,64 bits" bitfld.long 0x00 12.--13. " WES ,Write Element Size" "8 bits,16 bits,32 bits,64 bits" textline " " bitfld.long 0x00 8. " TTYPE ,Transfer Type" "Frame,Block" bitfld.long 0x00 3.--4. " ADDMR ,Addressing Mode Read" "Constant,Post-increment,Reserved,Indexed" textline " " bitfld.long 0x00 1.--2. " ADDMW ,Addressing Mode Write" "Constant,Post-increment,Reserved,Indexed" bitfld.long 0x00 0. " AIM ,Autoinitiation Mode" "Single block,Autoinitiation" line.long 0x04 "EIOFF,Element Index Offset Register" hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination Address Element Index" hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source Address Element Index" line.long 0x08 "FIOFF,Frame Index Offset Register" hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination Address Frame Index" hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source Address Frame Index" tree.end tree "Primary Control Packet 18" group.long (0x240)++0x0b line.long 0x00 "ISADDR,Initial Source Address Register" line.long 0x04 "IDADDR,Initial Destination Address Register" line.long 0x08 "ITCOUNT,Initial Transfer Count Register" hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial Frame Transfer Count" hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial Element Transfer Count" group.long (0x240+0x10)++0x0b line.long 0x00 "CHCTRL,Channel Control Register" bitfld.long 0x00 16.--21. " CHAIN ,Next Channel to be Triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Reserved,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,?..." bitfld.long 0x00 14.--15. " RES ,Read Element Size" "8 bits,16 bits,32 bits,64 bits" bitfld.long 0x00 12.--13. " WES ,Write Element Size" "8 bits,16 bits,32 bits,64 bits" textline " " bitfld.long 0x00 8. " TTYPE ,Transfer Type" "Frame,Block" bitfld.long 0x00 3.--4. " ADDMR ,Addressing Mode Read" "Constant,Post-increment,Reserved,Indexed" textline " " bitfld.long 0x00 1.--2. " ADDMW ,Addressing Mode Write" "Constant,Post-increment,Reserved,Indexed" bitfld.long 0x00 0. " AIM ,Autoinitiation Mode" "Single block,Autoinitiation" line.long 0x04 "EIOFF,Element Index Offset Register" hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination Address Element Index" hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source Address Element Index" line.long 0x08 "FIOFF,Frame Index Offset Register" hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination Address Frame Index" hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source Address Frame Index" tree.end tree "Primary Control Packet 19" group.long (0x260)++0x0b line.long 0x00 "ISADDR,Initial Source Address Register" line.long 0x04 "IDADDR,Initial Destination Address Register" line.long 0x08 "ITCOUNT,Initial Transfer Count Register" hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial Frame Transfer Count" hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial Element Transfer Count" group.long (0x260+0x10)++0x0b line.long 0x00 "CHCTRL,Channel Control Register" bitfld.long 0x00 16.--21. " CHAIN ,Next Channel to be Triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Reserved,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,?..." bitfld.long 0x00 14.--15. " RES ,Read Element Size" "8 bits,16 bits,32 bits,64 bits" bitfld.long 0x00 12.--13. " WES ,Write Element Size" "8 bits,16 bits,32 bits,64 bits" textline " " bitfld.long 0x00 8. " TTYPE ,Transfer Type" "Frame,Block" bitfld.long 0x00 3.--4. " ADDMR ,Addressing Mode Read" "Constant,Post-increment,Reserved,Indexed" textline " " bitfld.long 0x00 1.--2. " ADDMW ,Addressing Mode Write" "Constant,Post-increment,Reserved,Indexed" bitfld.long 0x00 0. " AIM ,Autoinitiation Mode" "Single block,Autoinitiation" line.long 0x04 "EIOFF,Element Index Offset Register" hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination Address Element Index" hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source Address Element Index" line.long 0x08 "FIOFF,Frame Index Offset Register" hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination Address Frame Index" hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source Address Frame Index" tree.end tree "Primary Control Packet 20" group.long (0x280)++0x0b line.long 0x00 "ISADDR,Initial Source Address Register" line.long 0x04 "IDADDR,Initial Destination Address Register" line.long 0x08 "ITCOUNT,Initial Transfer Count Register" hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial Frame Transfer Count" hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial Element Transfer Count" group.long (0x280+0x10)++0x0b line.long 0x00 "CHCTRL,Channel Control Register" bitfld.long 0x00 16.--21. " CHAIN ,Next Channel to be Triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Reserved,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,?..." bitfld.long 0x00 14.--15. " RES ,Read Element Size" "8 bits,16 bits,32 bits,64 bits" bitfld.long 0x00 12.--13. " WES ,Write Element Size" "8 bits,16 bits,32 bits,64 bits" textline " " bitfld.long 0x00 8. " TTYPE ,Transfer Type" "Frame,Block" bitfld.long 0x00 3.--4. " ADDMR ,Addressing Mode Read" "Constant,Post-increment,Reserved,Indexed" textline " " bitfld.long 0x00 1.--2. " ADDMW ,Addressing Mode Write" "Constant,Post-increment,Reserved,Indexed" bitfld.long 0x00 0. " AIM ,Autoinitiation Mode" "Single block,Autoinitiation" line.long 0x04 "EIOFF,Element Index Offset Register" hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination Address Element Index" hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source Address Element Index" line.long 0x08 "FIOFF,Frame Index Offset Register" hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination Address Frame Index" hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source Address Frame Index" tree.end tree "Primary Control Packet 21" group.long (0x2A0)++0x0b line.long 0x00 "ISADDR,Initial Source Address Register" line.long 0x04 "IDADDR,Initial Destination Address Register" line.long 0x08 "ITCOUNT,Initial Transfer Count Register" hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial Frame Transfer Count" hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial Element Transfer Count" group.long (0x2A0+0x10)++0x0b line.long 0x00 "CHCTRL,Channel Control Register" bitfld.long 0x00 16.--21. " CHAIN ,Next Channel to be Triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Reserved,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,?..." bitfld.long 0x00 14.--15. " RES ,Read Element Size" "8 bits,16 bits,32 bits,64 bits" bitfld.long 0x00 12.--13. " WES ,Write Element Size" "8 bits,16 bits,32 bits,64 bits" textline " " bitfld.long 0x00 8. " TTYPE ,Transfer Type" "Frame,Block" bitfld.long 0x00 3.--4. " ADDMR ,Addressing Mode Read" "Constant,Post-increment,Reserved,Indexed" textline " " bitfld.long 0x00 1.--2. " ADDMW ,Addressing Mode Write" "Constant,Post-increment,Reserved,Indexed" bitfld.long 0x00 0. " AIM ,Autoinitiation Mode" "Single block,Autoinitiation" line.long 0x04 "EIOFF,Element Index Offset Register" hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination Address Element Index" hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source Address Element Index" line.long 0x08 "FIOFF,Frame Index Offset Register" hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination Address Frame Index" hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source Address Frame Index" tree.end tree "Primary Control Packet 22" group.long (0x2C0)++0x0b line.long 0x00 "ISADDR,Initial Source Address Register" line.long 0x04 "IDADDR,Initial Destination Address Register" line.long 0x08 "ITCOUNT,Initial Transfer Count Register" hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial Frame Transfer Count" hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial Element Transfer Count" group.long (0x2C0+0x10)++0x0b line.long 0x00 "CHCTRL,Channel Control Register" bitfld.long 0x00 16.--21. " CHAIN ,Next Channel to be Triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Reserved,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,?..." bitfld.long 0x00 14.--15. " RES ,Read Element Size" "8 bits,16 bits,32 bits,64 bits" bitfld.long 0x00 12.--13. " WES ,Write Element Size" "8 bits,16 bits,32 bits,64 bits" textline " " bitfld.long 0x00 8. " TTYPE ,Transfer Type" "Frame,Block" bitfld.long 0x00 3.--4. " ADDMR ,Addressing Mode Read" "Constant,Post-increment,Reserved,Indexed" textline " " bitfld.long 0x00 1.--2. " ADDMW ,Addressing Mode Write" "Constant,Post-increment,Reserved,Indexed" bitfld.long 0x00 0. " AIM ,Autoinitiation Mode" "Single block,Autoinitiation" line.long 0x04 "EIOFF,Element Index Offset Register" hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination Address Element Index" hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source Address Element Index" line.long 0x08 "FIOFF,Frame Index Offset Register" hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination Address Frame Index" hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source Address Frame Index" tree.end tree "Primary Control Packet 23" group.long (0x2E0)++0x0b line.long 0x00 "ISADDR,Initial Source Address Register" line.long 0x04 "IDADDR,Initial Destination Address Register" line.long 0x08 "ITCOUNT,Initial Transfer Count Register" hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial Frame Transfer Count" hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial Element Transfer Count" group.long (0x2E0+0x10)++0x0b line.long 0x00 "CHCTRL,Channel Control Register" bitfld.long 0x00 16.--21. " CHAIN ,Next Channel to be Triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Reserved,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,?..." bitfld.long 0x00 14.--15. " RES ,Read Element Size" "8 bits,16 bits,32 bits,64 bits" bitfld.long 0x00 12.--13. " WES ,Write Element Size" "8 bits,16 bits,32 bits,64 bits" textline " " bitfld.long 0x00 8. " TTYPE ,Transfer Type" "Frame,Block" bitfld.long 0x00 3.--4. " ADDMR ,Addressing Mode Read" "Constant,Post-increment,Reserved,Indexed" textline " " bitfld.long 0x00 1.--2. " ADDMW ,Addressing Mode Write" "Constant,Post-increment,Reserved,Indexed" bitfld.long 0x00 0. " AIM ,Autoinitiation Mode" "Single block,Autoinitiation" line.long 0x04 "EIOFF,Element Index Offset Register" hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination Address Element Index" hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source Address Element Index" line.long 0x08 "FIOFF,Frame Index Offset Register" hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination Address Frame Index" hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source Address Frame Index" tree.end tree "Primary Control Packet 24" group.long (0x300)++0x0b line.long 0x00 "ISADDR,Initial Source Address Register" line.long 0x04 "IDADDR,Initial Destination Address Register" line.long 0x08 "ITCOUNT,Initial Transfer Count Register" hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial Frame Transfer Count" hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial Element Transfer Count" group.long (0x300+0x10)++0x0b line.long 0x00 "CHCTRL,Channel Control Register" bitfld.long 0x00 16.--21. " CHAIN ,Next Channel to be Triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Reserved,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,?..." bitfld.long 0x00 14.--15. " RES ,Read Element Size" "8 bits,16 bits,32 bits,64 bits" bitfld.long 0x00 12.--13. " WES ,Write Element Size" "8 bits,16 bits,32 bits,64 bits" textline " " bitfld.long 0x00 8. " TTYPE ,Transfer Type" "Frame,Block" bitfld.long 0x00 3.--4. " ADDMR ,Addressing Mode Read" "Constant,Post-increment,Reserved,Indexed" textline " " bitfld.long 0x00 1.--2. " ADDMW ,Addressing Mode Write" "Constant,Post-increment,Reserved,Indexed" bitfld.long 0x00 0. " AIM ,Autoinitiation Mode" "Single block,Autoinitiation" line.long 0x04 "EIOFF,Element Index Offset Register" hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination Address Element Index" hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source Address Element Index" line.long 0x08 "FIOFF,Frame Index Offset Register" hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination Address Frame Index" hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source Address Frame Index" tree.end tree "Primary Control Packet 25" group.long (0x320)++0x0b line.long 0x00 "ISADDR,Initial Source Address Register" line.long 0x04 "IDADDR,Initial Destination Address Register" line.long 0x08 "ITCOUNT,Initial Transfer Count Register" hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial Frame Transfer Count" hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial Element Transfer Count" group.long (0x320+0x10)++0x0b line.long 0x00 "CHCTRL,Channel Control Register" bitfld.long 0x00 16.--21. " CHAIN ,Next Channel to be Triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Reserved,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,?..." bitfld.long 0x00 14.--15. " RES ,Read Element Size" "8 bits,16 bits,32 bits,64 bits" bitfld.long 0x00 12.--13. " WES ,Write Element Size" "8 bits,16 bits,32 bits,64 bits" textline " " bitfld.long 0x00 8. " TTYPE ,Transfer Type" "Frame,Block" bitfld.long 0x00 3.--4. " ADDMR ,Addressing Mode Read" "Constant,Post-increment,Reserved,Indexed" textline " " bitfld.long 0x00 1.--2. " ADDMW ,Addressing Mode Write" "Constant,Post-increment,Reserved,Indexed" bitfld.long 0x00 0. " AIM ,Autoinitiation Mode" "Single block,Autoinitiation" line.long 0x04 "EIOFF,Element Index Offset Register" hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination Address Element Index" hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source Address Element Index" line.long 0x08 "FIOFF,Frame Index Offset Register" hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination Address Frame Index" hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source Address Frame Index" tree.end tree "Primary Control Packet 26" group.long (0x340)++0x0b line.long 0x00 "ISADDR,Initial Source Address Register" line.long 0x04 "IDADDR,Initial Destination Address Register" line.long 0x08 "ITCOUNT,Initial Transfer Count Register" hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial Frame Transfer Count" hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial Element Transfer Count" group.long (0x340+0x10)++0x0b line.long 0x00 "CHCTRL,Channel Control Register" bitfld.long 0x00 16.--21. " CHAIN ,Next Channel to be Triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Reserved,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,?..." bitfld.long 0x00 14.--15. " RES ,Read Element Size" "8 bits,16 bits,32 bits,64 bits" bitfld.long 0x00 12.--13. " WES ,Write Element Size" "8 bits,16 bits,32 bits,64 bits" textline " " bitfld.long 0x00 8. " TTYPE ,Transfer Type" "Frame,Block" bitfld.long 0x00 3.--4. " ADDMR ,Addressing Mode Read" "Constant,Post-increment,Reserved,Indexed" textline " " bitfld.long 0x00 1.--2. " ADDMW ,Addressing Mode Write" "Constant,Post-increment,Reserved,Indexed" bitfld.long 0x00 0. " AIM ,Autoinitiation Mode" "Single block,Autoinitiation" line.long 0x04 "EIOFF,Element Index Offset Register" hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination Address Element Index" hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source Address Element Index" line.long 0x08 "FIOFF,Frame Index Offset Register" hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination Address Frame Index" hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source Address Frame Index" tree.end tree "Primary Control Packet 27" group.long (0x360)++0x0b line.long 0x00 "ISADDR,Initial Source Address Register" line.long 0x04 "IDADDR,Initial Destination Address Register" line.long 0x08 "ITCOUNT,Initial Transfer Count Register" hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial Frame Transfer Count" hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial Element Transfer Count" group.long (0x360+0x10)++0x0b line.long 0x00 "CHCTRL,Channel Control Register" bitfld.long 0x00 16.--21. " CHAIN ,Next Channel to be Triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Reserved,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,?..." bitfld.long 0x00 14.--15. " RES ,Read Element Size" "8 bits,16 bits,32 bits,64 bits" bitfld.long 0x00 12.--13. " WES ,Write Element Size" "8 bits,16 bits,32 bits,64 bits" textline " " bitfld.long 0x00 8. " TTYPE ,Transfer Type" "Frame,Block" bitfld.long 0x00 3.--4. " ADDMR ,Addressing Mode Read" "Constant,Post-increment,Reserved,Indexed" textline " " bitfld.long 0x00 1.--2. " ADDMW ,Addressing Mode Write" "Constant,Post-increment,Reserved,Indexed" bitfld.long 0x00 0. " AIM ,Autoinitiation Mode" "Single block,Autoinitiation" line.long 0x04 "EIOFF,Element Index Offset Register" hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination Address Element Index" hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source Address Element Index" line.long 0x08 "FIOFF,Frame Index Offset Register" hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination Address Frame Index" hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source Address Frame Index" tree.end tree "Primary Control Packet 28" group.long (0x380)++0x0b line.long 0x00 "ISADDR,Initial Source Address Register" line.long 0x04 "IDADDR,Initial Destination Address Register" line.long 0x08 "ITCOUNT,Initial Transfer Count Register" hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial Frame Transfer Count" hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial Element Transfer Count" group.long (0x380+0x10)++0x0b line.long 0x00 "CHCTRL,Channel Control Register" bitfld.long 0x00 16.--21. " CHAIN ,Next Channel to be Triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Reserved,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,?..." bitfld.long 0x00 14.--15. " RES ,Read Element Size" "8 bits,16 bits,32 bits,64 bits" bitfld.long 0x00 12.--13. " WES ,Write Element Size" "8 bits,16 bits,32 bits,64 bits" textline " " bitfld.long 0x00 8. " TTYPE ,Transfer Type" "Frame,Block" bitfld.long 0x00 3.--4. " ADDMR ,Addressing Mode Read" "Constant,Post-increment,Reserved,Indexed" textline " " bitfld.long 0x00 1.--2. " ADDMW ,Addressing Mode Write" "Constant,Post-increment,Reserved,Indexed" bitfld.long 0x00 0. " AIM ,Autoinitiation Mode" "Single block,Autoinitiation" line.long 0x04 "EIOFF,Element Index Offset Register" hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination Address Element Index" hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source Address Element Index" line.long 0x08 "FIOFF,Frame Index Offset Register" hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination Address Frame Index" hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source Address Frame Index" tree.end tree.end width 9. tree.open "Working Control Packet Registers" tree "Working Control Packet 0" group.long (0x0800+0x0)++0x07 line.long 0x00 "CSADDR,Current Source Address Register" line.long 0x04 "CDADDR,Current Destination Address Register" rgroup.long (0x0808+0x0)++0x03 line.long 0x00 "CTCOUNT,Current Transfer Count Register" hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current Frame Transfer Count" hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current Element Transfer Count" tree.end tree "Working Control Packet 1" group.long (0x0800+0x10)++0x07 line.long 0x00 "CSADDR,Current Source Address Register" line.long 0x04 "CDADDR,Current Destination Address Register" rgroup.long (0x0808+0x10)++0x03 line.long 0x00 "CTCOUNT,Current Transfer Count Register" hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current Frame Transfer Count" hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current Element Transfer Count" tree.end tree "Working Control Packet 2" group.long (0x0800+0x20)++0x07 line.long 0x00 "CSADDR,Current Source Address Register" line.long 0x04 "CDADDR,Current Destination Address Register" rgroup.long (0x0808+0x20)++0x03 line.long 0x00 "CTCOUNT,Current Transfer Count Register" hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current Frame Transfer Count" hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current Element Transfer Count" tree.end tree "Working Control Packet 3" group.long (0x0800+0x30)++0x07 line.long 0x00 "CSADDR,Current Source Address Register" line.long 0x04 "CDADDR,Current Destination Address Register" rgroup.long (0x0808+0x30)++0x03 line.long 0x00 "CTCOUNT,Current Transfer Count Register" hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current Frame Transfer Count" hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current Element Transfer Count" tree.end tree "Working Control Packet 4" group.long (0x0800+0x40)++0x07 line.long 0x00 "CSADDR,Current Source Address Register" line.long 0x04 "CDADDR,Current Destination Address Register" rgroup.long (0x0808+0x40)++0x03 line.long 0x00 "CTCOUNT,Current Transfer Count Register" hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current Frame Transfer Count" hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current Element Transfer Count" tree.end tree "Working Control Packet 5" group.long (0x0800+0x50)++0x07 line.long 0x00 "CSADDR,Current Source Address Register" line.long 0x04 "CDADDR,Current Destination Address Register" rgroup.long (0x0808+0x50)++0x03 line.long 0x00 "CTCOUNT,Current Transfer Count Register" hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current Frame Transfer Count" hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current Element Transfer Count" tree.end tree "Working Control Packet 6" group.long (0x0800+0x60)++0x07 line.long 0x00 "CSADDR,Current Source Address Register" line.long 0x04 "CDADDR,Current Destination Address Register" rgroup.long (0x0808+0x60)++0x03 line.long 0x00 "CTCOUNT,Current Transfer Count Register" hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current Frame Transfer Count" hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current Element Transfer Count" tree.end tree "Working Control Packet 7" group.long (0x0800+0x70)++0x07 line.long 0x00 "CSADDR,Current Source Address Register" line.long 0x04 "CDADDR,Current Destination Address Register" rgroup.long (0x0808+0x70)++0x03 line.long 0x00 "CTCOUNT,Current Transfer Count Register" hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current Frame Transfer Count" hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current Element Transfer Count" tree.end tree "Working Control Packet 8" group.long (0x0800+0x80)++0x07 line.long 0x00 "CSADDR,Current Source Address Register" line.long 0x04 "CDADDR,Current Destination Address Register" rgroup.long (0x0808+0x80)++0x03 line.long 0x00 "CTCOUNT,Current Transfer Count Register" hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current Frame Transfer Count" hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current Element Transfer Count" tree.end tree "Working Control Packet 9" group.long (0x0800+0x90)++0x07 line.long 0x00 "CSADDR,Current Source Address Register" line.long 0x04 "CDADDR,Current Destination Address Register" rgroup.long (0x0808+0x90)++0x03 line.long 0x00 "CTCOUNT,Current Transfer Count Register" hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current Frame Transfer Count" hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current Element Transfer Count" tree.end tree "Working Control Packet 10" group.long (0x0800+0xA0)++0x07 line.long 0x00 "CSADDR,Current Source Address Register" line.long 0x04 "CDADDR,Current Destination Address Register" rgroup.long (0x0808+0xA0)++0x03 line.long 0x00 "CTCOUNT,Current Transfer Count Register" hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current Frame Transfer Count" hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current Element Transfer Count" tree.end tree "Working Control Packet 12" group.long (0x0800+0xC0)++0x07 line.long 0x00 "CSADDR,Current Source Address Register" line.long 0x04 "CDADDR,Current Destination Address Register" rgroup.long (0x0808+0xC0)++0x03 line.long 0x00 "CTCOUNT,Current Transfer Count Register" hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current Frame Transfer Count" hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current Element Transfer Count" tree.end tree "Working Control Packet 13" group.long (0x0800+0xD0)++0x07 line.long 0x00 "CSADDR,Current Source Address Register" line.long 0x04 "CDADDR,Current Destination Address Register" rgroup.long (0x0808+0xD0)++0x03 line.long 0x00 "CTCOUNT,Current Transfer Count Register" hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current Frame Transfer Count" hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current Element Transfer Count" tree.end tree "Working Control Packet 14" group.long (0x0800+0xE0)++0x07 line.long 0x00 "CSADDR,Current Source Address Register" line.long 0x04 "CDADDR,Current Destination Address Register" rgroup.long (0x0808+0xE0)++0x03 line.long 0x00 "CTCOUNT,Current Transfer Count Register" hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current Frame Transfer Count" hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current Element Transfer Count" tree.end tree "Working Control Packet 15" group.long (0x0800+0xF0)++0x07 line.long 0x00 "CSADDR,Current Source Address Register" line.long 0x04 "CDADDR,Current Destination Address Register" rgroup.long (0x0808+0xF0)++0x03 line.long 0x00 "CTCOUNT,Current Transfer Count Register" hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current Frame Transfer Count" hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current Element Transfer Count" tree.end tree "Working Control Packet 16" group.long (0x0800+0x100)++0x07 line.long 0x00 "CSADDR,Current Source Address Register" line.long 0x04 "CDADDR,Current Destination Address Register" rgroup.long (0x0808+0x100)++0x03 line.long 0x00 "CTCOUNT,Current Transfer Count Register" hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current Frame Transfer Count" hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current Element Transfer Count" tree.end tree "Working Control Packet 17" group.long (0x0800+0x110)++0x07 line.long 0x00 "CSADDR,Current Source Address Register" line.long 0x04 "CDADDR,Current Destination Address Register" rgroup.long (0x0808+0x110)++0x03 line.long 0x00 "CTCOUNT,Current Transfer Count Register" hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current Frame Transfer Count" hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current Element Transfer Count" tree.end tree "Working Control Packet 18" group.long (0x0800+0x120)++0x07 line.long 0x00 "CSADDR,Current Source Address Register" line.long 0x04 "CDADDR,Current Destination Address Register" rgroup.long (0x0808+0x120)++0x03 line.long 0x00 "CTCOUNT,Current Transfer Count Register" hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current Frame Transfer Count" hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current Element Transfer Count" tree.end tree "Working Control Packet 19" group.long (0x0800+0x130)++0x07 line.long 0x00 "CSADDR,Current Source Address Register" line.long 0x04 "CDADDR,Current Destination Address Register" rgroup.long (0x0808+0x130)++0x03 line.long 0x00 "CTCOUNT,Current Transfer Count Register" hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current Frame Transfer Count" hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current Element Transfer Count" tree.end tree "Working Control Packet 20" group.long (0x0800+0x140)++0x07 line.long 0x00 "CSADDR,Current Source Address Register" line.long 0x04 "CDADDR,Current Destination Address Register" rgroup.long (0x0808+0x140)++0x03 line.long 0x00 "CTCOUNT,Current Transfer Count Register" hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current Frame Transfer Count" hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current Element Transfer Count" tree.end tree "Working Control Packet 21" group.long (0x0800+0x150)++0x07 line.long 0x00 "CSADDR,Current Source Address Register" line.long 0x04 "CDADDR,Current Destination Address Register" rgroup.long (0x0808+0x150)++0x03 line.long 0x00 "CTCOUNT,Current Transfer Count Register" hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current Frame Transfer Count" hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current Element Transfer Count" tree.end tree "Working Control Packet 22" group.long (0x0800+0x160)++0x07 line.long 0x00 "CSADDR,Current Source Address Register" line.long 0x04 "CDADDR,Current Destination Address Register" rgroup.long (0x0808+0x160)++0x03 line.long 0x00 "CTCOUNT,Current Transfer Count Register" hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current Frame Transfer Count" hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current Element Transfer Count" tree.end tree "Working Control Packet 23" group.long (0x0800+0x170)++0x07 line.long 0x00 "CSADDR,Current Source Address Register" line.long 0x04 "CDADDR,Current Destination Address Register" rgroup.long (0x0808+0x170)++0x03 line.long 0x00 "CTCOUNT,Current Transfer Count Register" hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current Frame Transfer Count" hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current Element Transfer Count" tree.end tree "Working Control Packet 24" group.long (0x0800+0x180)++0x07 line.long 0x00 "CSADDR,Current Source Address Register" line.long 0x04 "CDADDR,Current Destination Address Register" rgroup.long (0x0808+0x180)++0x03 line.long 0x00 "CTCOUNT,Current Transfer Count Register" hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current Frame Transfer Count" hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current Element Transfer Count" tree.end tree "Working Control Packet 25" group.long (0x0800+0x190)++0x07 line.long 0x00 "CSADDR,Current Source Address Register" line.long 0x04 "CDADDR,Current Destination Address Register" rgroup.long (0x0808+0x190)++0x03 line.long 0x00 "CTCOUNT,Current Transfer Count Register" hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current Frame Transfer Count" hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current Element Transfer Count" tree.end tree "Working Control Packet 26" group.long (0x0800+0x1A0)++0x07 line.long 0x00 "CSADDR,Current Source Address Register" line.long 0x04 "CDADDR,Current Destination Address Register" rgroup.long (0x0808+0x1A0)++0x03 line.long 0x00 "CTCOUNT,Current Transfer Count Register" hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current Frame Transfer Count" hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current Element Transfer Count" tree.end tree "Working Control Packet 27" group.long (0x0800+0x1B0)++0x07 line.long 0x00 "CSADDR,Current Source Address Register" line.long 0x04 "CDADDR,Current Destination Address Register" rgroup.long (0x0808+0x1B0)++0x03 line.long 0x00 "CTCOUNT,Current Transfer Count Register" hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current Frame Transfer Count" hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current Element Transfer Count" tree.end tree "Working Control Packet 28" group.long (0x0800+0x1C0)++0x07 line.long 0x00 "CSADDR,Current Source Address Register" line.long 0x04 "CDADDR,Current Destination Address Register" rgroup.long (0x0808+0x1C0)++0x03 line.long 0x00 "CTCOUNT,Current Transfer Count Register" hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current Frame Transfer Count" hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current Element Transfer Count" tree.end tree.end tree.end width 0xb tree.end tree "DMM (Data Modification Module)" base ad:0xFFFFF700 width 16. group.long 0x00++0x07 line.long 0x00 "GLBCTRL,DMM Global Control Register" bitfld.long 0x00 24. " BUSY ,Busy indicator" "Not received,Received" sif !cpuis("TMS570LS3137-EP") bitfld.long 0x00 18. " CONTCLK ,Continuous RTPCLK output" "Suspended,Continue" else bitfld.long 0x00 18. " CONTCLK ,Continuous DMMCLK input" "Suspended,Continue" endif bitfld.long 0x00 17. " COS ,Continue on suspend" "Suspended,Continue" newline bitfld.long 0x00 16. " RESET ,This bit resets the state machine and the registers to its reset value" "No reset,Reset" bitfld.long 0x00 9.--10. " DDM_WIDTH ,Packet width in Direct Data Mode" "8 bits,16 bits,32 bits,?..." bitfld.long 0x00 8. " TM_DMM ,Packet format" "Trace Mode,Direct Data Mode" newline bitfld.long 0x00 0.--3. " ON/OFF ,DMM module receives data enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" line.long 0x04 "INTSET_SET/CLR,DMM Interrupt Set Register" setclrfld.long 0x04 17. 0x04 17. 0x08 17. " PROG_BUFF ,Programmable buffer interrupt" "No interrupt,Interrupt" setclrfld.long 0x04 16. 0x04 16. 0x08 16. " EO_BUFF ,End of buffer interrupt" "No interrupt,Interrupt" newline setclrfld.long 0x04 15. 0x04 15. 0x08 15. " DEST3REG2 ,Destination 3 Region 2 interrupt" "No interrupt,Interrupt" setclrfld.long 0x04 14. 0x04 14. 0x08 14. " DEST3REG1 ,Destination 3 Region 1 interrupt" "No interrupt,Interrupt" newline setclrfld.long 0x04 13. 0x04 13. 0x08 13. " DEST2REG2 ,Destination 2 Region 2 interrupt" "No interrupt,Interrupt" setclrfld.long 0x04 12. 0x04 12. 0x08 12. " DEST2REG1 ,Destination 2 Region 1 interrupt" "No interrupt,Interrupt" newline setclrfld.long 0x04 11. 0x04 11. 0x08 11. " DEST1REG2 ,Destination 1 Region 2 interrupt" "No interrupt,Interrupt" setclrfld.long 0x04 10. 0x04 10. 0x08 10. " DEST1REG1 ,Destination 1 Region 1 interrupt" "No interrupt,Interrupt" newline setclrfld.long 0x04 9. 0x04 9. 0x08 9. " DEST0REG2 ,Destination 0 Region 2 interrupt" "No interrupt,Interrupt" setclrfld.long 0x04 8. 0x04 8. 0x08 8. " DEST0REG1 ,Destination 0 Region 1 interrupt" "No interrupt,Interrupt" newline setclrfld.long 0x04 7. 0x04 7. 0x08 7. " BUSERROR ,BMM bus error response" "No interrupt,Interrupt" setclrfld.long 0x04 6. 0x04 6. 0x08 6. " BUFF_OVF ,Write buffer overflow interrupt" "No interrupt,Interrupt" newline setclrfld.long 0x04 5. 0x04 5. 0x08 5. " SRC_OVF ,Source overflow interrupt" "No interrupt,Interrupt" setclrfld.long 0x04 4. 0x04 4. 0x08 4. " DEST3_ERRENA ,Destination 3 error interrupt" "No interrupt,Interrupt" newline setclrfld.long 0x04 3. 0x04 3. 0x08 3. " DEST2_ERRENA ,Destination 2 error interrupt" "No interrupt,Interrupt" setclrfld.long 0x04 2. 0x04 2. 0x08 2. " DEST1_ERRENA_ ,Destination 1 error interrupt" "No interrupt,Interrupt" newline setclrfld.long 0x04 1. 0x04 1. 0x08 1. " DEST0_ERRENA ,Destination 0 error interrupt" "No interrupt,Interrupt" setclrfld.long 0x04 0. 0x04 0. 0x08 0. " PACKET_ERR_INT ,Packet error interrupt" "No interrupt,Interrupt" group.long 0x0C++0x07 line.long 0x00 "INTLVL,DMM Interrupt Level Register" bitfld.long 0x00 17. " PROG_BUFF ,Programmable buffer interrupt level" "Level 0,Level 1" bitfld.long 0x00 16. " EO_BUFF ,End of buffer interrupt level" "Level 0,Level 1" bitfld.long 0x00 15. " DEST3REG2 ,Destination 3 Region 2 interrupt level" "Level 0,Level 1" newline bitfld.long 0x00 14. " DEST3REG1 ,Destination 3 Region 1 interrupt level" "Level 0,Level 1" bitfld.long 0x00 13. " DEST2REG2 ,Destination 2 Region 2 Interrupt Level" "Level 0,Level 1" bitfld.long 0x00 12. " DEST2REG1 ,Destination 2 Region 1 interrupt level" "Level 0,Level 1" newline bitfld.long 0x00 11. " DEST1REG2 ,Destination 1 Region 2 interrupt level" "Level 0,Level 1" bitfld.long 0x00 10. " DEST1REG1 ,Destination 1 Region 1 interrupt level" "Level 0,Level 1" bitfld.long 0x00 9. " DEST0REG2 ,Destination 0 Region 2 interrupt level" "Level 0,Level 1" newline bitfld.long 0x00 8. " DEST0REG1 ,Destination 0 Region 1 interrupt level" "Level 0,Level 1" bitfld.long 0x00 7. " BUSERROR ,BMM bus error response" "Level 0,Level 1" bitfld.long 0x00 6. " BUFF_OVF ,Write buffer overflow interrupt level" "Level 0,Level 1" newline bitfld.long 0x00 5. " SRC_OVF ,Source overflow interrupt level" "Level 0,Level 1" bitfld.long 0x00 4. " DEST3_ERRENA ,Destination 3 error interrupt level" "Level 0,Level 1" bitfld.long 0x00 3. " DEST2_ERRENA ,Destination 2 error interrupt level" "Level 0,Level 1" newline bitfld.long 0x00 2. " DEST1_ERRENA ,Destination 1 error interrupt level" "Level 0,Level 1" bitfld.long 0x00 1. " DEST0_ERRENA ,Destination 0 error interrupt level" "Level 0,Level 1" bitfld.long 0x00 0. " PACKET_ERR_INT ,Packet error interrupt level" "Level 0,Level 1" line.long 0x04 "INTFLAG,DMM Interrupt Flag Register" eventfld.long 0x04 17. " PROG_BUFF ,Programmable buffer interrupt flag" "No interrupt,Interrupt" eventfld.long 0x04 16. " EO_BUFF ,End of buffer interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x04 15. " DEST3REG2 ,Destination 3 Region 2 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x04 14. " DEST3REG1 ,Destination 3 Region 1 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x04 13. " DEST2REG2 ,Destination 2 Region 2 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x04 12. " DEST2REG1 ,Destination 2 Region 1 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x04 11. " DEST1REG2 ,Destination 1 Region 2 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x04 10. " DEST1REG1 ,Destination 1 Region 1 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x04 9. " DEST0REG2 ,Destination 0 Region 2 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x04 8. " DEST0REG1 ,Destination 0 Region 1 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x04 7. " BUSERROR ,BMM bus error response" "No interrupt,Interrupt" eventfld.long 0x04 6. " BUFF_OVF ,Write buffer overflow interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x04 5. " SRC_OVF ,Source overflow interrupt flag" "No interrupt,Interrupt" eventfld.long 0x04 4. " DEST3_ERRENA ,Destination 3 error interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x04 3. " DEST2_ERRENA ,Destination 2 error interrupt flag" "No interrupt,Interrupt" eventfld.long 0x04 2. " DEST1_ERRENA ,Destination 1 error interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x04 1. " DEST0_ERRENA ,Destination 0 error interrupt flag" "No interrupt,Interrupt" eventfld.long 0x04 0. " PACKET_ERR_INT ,Packet error interrupt flag" "No interrupt,Interrupt" hgroup.long 0x14++0x03 hide.long 0x00 "OFF1,DMM Interrupt Offset 1 Register" in hgroup.long 0x18++0x03 hide.long 0x00 "OFF2,DMM Interrupt Offset 2 Register" in group.long 0x1C++0x07 line.long 0x00 "DDMDEST,DDM Direct Data Mode Destination Register" line.long 0x04 "DDMBL,DMM Direct Data Mode Blocksize Register" bitfld.long 0x04 0.--3. " BLOCKSIZE ,These bits define the size of the buffer region" "0 B,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,?..." rgroup.long 0x24++0x03 line.long 0x00 "DDMPT,DMM Direct Data Mode Pointer Register" hexmask.long.word 0x00 0.--14. 1. " POINTER ,Hold the pointer to the next entry to be written in the buffer" group.long 0x28++0x4B line.long 0x00 "INTPT,DDM Direct Data Mode Interrupt Pointer Register" hexmask.long.word 0x00 0.--14. 1. " INTPT ,Interrupt Pointer" line.long 0x04 "DEST0REG1,DDM Destination 0 Region 1" hexmask.long.word 0x04 18.--31. 0x04 " BASEADDR ,Base Address" hexmask.long.tbyte 0x04 0.--17. 1. " BLOCKADDR ,Block Address" line.long 0x08 "DEST0BL1,DDM Destination 0 Blocksize 1" bitfld.long 0x08 0.--3. " BLOCKSIZE ,Block Size" "0 kB,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..." line.long 0x0C "DEST0REG2,DDM Destination 0 Region 2" hexmask.long.word 0x0C 18.--31. 0x4 " BASEADDR ,Base Address" hexmask.long.tbyte 0x0C 0.--17. 1. " BLOCKADDR ,Block Address" line.long 0x10 "DEST0BL2,DDM Destination 0 Blocksize 2" bitfld.long 0x10 0.--3. " BLOCKSIZE ,Block Size" "0 kB,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..." line.long 0x14 "DEST1REG1,DDM Destination 1 Region 1" hexmask.long.word 0x14 18.--31. 0x4 " BASEADDR ,Base Address" hexmask.long.tbyte 0x14 0.--17. 1. " BLOCKADDR ,Block Address" line.long 0x18 "DEST1BL1,DDM Destination 1 Blocksize 1" bitfld.long 0x18 0.--3. " BLOCKSIZE ,Block Size" "0 kB,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..." line.long 0x1C "DEST1REG2,DDM Destination 1 Region 2" hexmask.long.word 0x1C 18.--31. 0x4 " BASEADDR ,Base Address" hexmask.long.tbyte 0x1C 0.--17. 1. " BLOCKADDR ,Block Address" line.long 0x20 "DEST1BL2,DDM Destination 1 Blocksize 2" bitfld.long 0x20 0.--3. " BLOCKSIZE ,Block Size" "0 kB,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..." line.long 0x24 "DEST2REG1,DDM Destination 2 Region 1" hexmask.long.word 0x24 18.--31. 0x4 " BASEADDR ,Base Address" hexmask.long.tbyte 0x24 0.--17. 1. " BLOCKADDR ,Block Address" line.long 0x28 "DEST2BL1,DDM Destination 2 Blocksize 1" bitfld.long 0x28 0.--3. " BLOCKSIZE ,Block Size" "0 kB,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..." line.long 0x2C "DEST2REG2,DDM Destination 2 Region 2" hexmask.long.word 0x2C 18.--31. 0x4 " BASEADDR ,Base Address" hexmask.long.tbyte 0x2C 0.--17. 1. " BLOCKADDR ,Block Address" line.long 0x30 "DEST2BL2,DDM Destination 2 Blocksize 2" bitfld.long 0x30 0.--3. " BLOCKSIZE ,Block Size" "0 kB,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..." line.long 0x34 "DEST3REG1,DDM Destination 3 Region 1" hexmask.long.word 0x34 18.--31. 0x4 " BASEADDR ,Base Address" hexmask.long.tbyte 0x34 0.--17. 1. " BLOCKADDR ,Block Address" line.long 0x38 "DEST3BL1,DDM Destination 3 Blocksize 1" bitfld.long 0x38 0.--3. " BLOCKSIZE ,Block Size" "0 kB,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..." line.long 0x3C "DEST3REG2,DDM Destination 3 Region 2" hexmask.long.word 0x3C 18.--31. 0x4 " BASEADDR ,Base Address" hexmask.long.tbyte 0x3C 0.--17. 1. " BLOCKADDR ,Block Address" line.long 0x40 "DEST3BL2,DDM Destination 3 Blocksize 2" bitfld.long 0x40 0.--3. " BLOCKSIZE ,Block Size" "0 kB,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..." line.long 0x44 "PC0,DDM Pin Control 0 (FUNC)" bitfld.long 0x44 18. " ENAFUNC ,DMMENA functional mode pin" "GIO mode,Functional mode" bitfld.long 0x44 17. " DATA15FUNC ,DMMDATA[15] functional mode pin" "GIO mode,Functional mode" newline bitfld.long 0x44 16. " DATA14FUNC ,DMMDATA[14] functional mode pin" "GIO mode,Functional mode" bitfld.long 0x44 15. " DATA13FUNC ,DMMDATA[13] functional mode pin" "GIO mode,Functional mode" newline bitfld.long 0x44 14. " DATA12FUNC ,DMMDATA[12] functional mode pin" "GIO mode,Functional mode" bitfld.long 0x44 13. " DATA11FUNC ,DMMDATA[11] functional mode pin" "GIO mode,Functional mode" newline bitfld.long 0x44 12. " DATA10FUNC ,DMMDATA[10] functional mode pin" "GIO mode,Functional mode" bitfld.long 0x44 11. " DATA9FUNC ,DMMDATA[9] functional mode pin" "GIO mode,Functional mode" newline bitfld.long 0x44 10. " DATA8FUNC ,DMMDATA[8] functional mode pin" "GIO mode,Functional mode" bitfld.long 0x44 9. " DATA7FUNC ,DMMDATA[7] functional mode pin" "GIO mode,Functional mode" newline bitfld.long 0x44 8. " DATA6FUNC ,DMMDATA[6] functional mode pin" "GIO mode,Functional mode" bitfld.long 0x44 7. " DATA5FUNC ,DMMDATA[5] functional mode pin" "GIO mode,Functional mode" newline bitfld.long 0x44 6. " DATA4FUNC ,DMMDATA[4] functional mode pin" "GIO mode,Functional mode" bitfld.long 0x44 5. " DATA3FUNC ,DMMDATA[3] functional mode pin" "GIO mode,Functional mode" newline bitfld.long 0x44 4. " DATA2FUNC ,DMMDATA[2] functional mode pin" "GIO mode,Functional mode" bitfld.long 0x44 3. " DATA1FUNC ,DMMDATA[1] functional mode pin" "GIO mode,Functional mode" newline bitfld.long 0x44 2. " DATA0FUNC ,DMMDATA[0] functional mode pin" "GIO mode,Functional mode" bitfld.long 0x44 1. " CLKFUNC ,DMMCLK functional mode pin" "GIO mode,Functional mode" newline bitfld.long 0x44 0. " SYNCFUNC ,DMMSYNC functional mode pin" "GIO mode,Functional mode" line.long 0x48 "PC1,DDM Pin Control 1 (DIR)" bitfld.long 0x48 18. " ENADIR ,DMMENA direction pin (GIO mode)" "Input,Output" bitfld.long 0x48 17. " DATA15DIR ,DMMDATA[15] direction pin (GIO mode)" "Input,Output" bitfld.long 0x48 16. " DATA14DIR ,DMMDATA[14] direction pin (GIO mode)" "Input,Output" newline bitfld.long 0x48 15. " DATA13DIR ,DMMDATA[13] direction pin (GIO mode)" "Input,Output" bitfld.long 0x48 14. " DATA12DIR ,DMMDATA[12] direction pin (GIO mode)" "Input,Output" bitfld.long 0x48 13. " DATA11DIR ,DMMDATA[11] direction pin (GIO mode)" "Input,Output" newline bitfld.long 0x48 12. " DATA10DIR ,DMMDATA[10] direction pin (GIO mode)" "Input,Output" bitfld.long 0x48 11. " DATA9DIR ,DMMDATA[9] direction pin (GIO mode)" "Input,Output" bitfld.long 0x48 10. " DATA8DIR ,DMMDATA[8] direction pin (GIO mode)" "Input,Output" newline bitfld.long 0x48 9. " DATA7DIR ,DMMDATA[7] direction pin (GIO mode)" "Input,Output" bitfld.long 0x48 8. " DATA6DIR ,DMMDATA[6] direction pin (GIO mode)" "Input,Output" bitfld.long 0x48 7. " DATA5DIR ,DMMDATA[5] direction pin (GIO mode)" "Input,Output" newline bitfld.long 0x48 6. " DATA4DIR ,DMMDATA[4] direction pin (GIO mode)" "Input,Output" bitfld.long 0x48 5. " DATA3DIR ,DMMDATA[3] direction pin (GIO mode)" "Input,Output" bitfld.long 0x48 4. " DATA2DIR ,DMMDATA[2] direction pin (GIO mode)" "Input,Output" newline bitfld.long 0x48 3. " DATA1DIR ,DMMDATA[1] direction pin (GIO mode)" "Input,Output" bitfld.long 0x48 2. " DATA0DIR ,DMMDATA[0] direction pin (GIO mode)" "Input,Output" bitfld.long 0x48 1. " CLKDIR ,DMMCLK direction pin (GIO mode)" "Input,Output" newline bitfld.long 0x48 0. " SYNCDIR ,DMMSYNC direction pin (GIO mode)" "Input,Output" rgroup.long 0x74++0x03 line.long 0x00 "PC2,DDM Pin Control 2 (DIN)" bitfld.long 0x00 18. " ENAIN ,DMMENA input" "Low,High" bitfld.long 0x00 17. " DATA15IN ,DMMDATA[15] input" "Low,High" bitfld.long 0x00 16. " DATA14IN ,DMMDATA[14] input" "Low,High" bitfld.long 0x00 15. " DATA13IN ,DMMDATA[13] input" "Low,High" newline bitfld.long 0x00 14. " DATA12IN ,DMMDATA[12] input" "Low,High" bitfld.long 0x00 13. " DATA11IN ,DMMDATA[11] input" "Low,High" bitfld.long 0x00 12. " DATA10IN ,DMMDATA[10] input" "Low,High" bitfld.long 0x00 11. " DATA9IN ,DMMDATA[9] input" "Low,High" newline bitfld.long 0x00 10. " DATA8IN ,DMMDATA[8] input" "Low,High" bitfld.long 0x00 9. " DATA7IN ,DMMDATA[7] input" "Low,High" bitfld.long 0x00 8. " DATA6IN ,DMMDATA[6] input" "Low,High" bitfld.long 0x00 7. " DATA5IN ,DMMDATA[5] input" "Low,High" newline bitfld.long 0x00 6. " DATA4IN ,DMMDATA[4] input" "Low,High" bitfld.long 0x00 5. " DATA3IN ,DMMDATA[3] input" "Low,High" bitfld.long 0x00 4. " DATA2IN ,DMMDATA[2] input" "Low,High" bitfld.long 0x00 3. " DATA1IN ,DMMDATA[1] input" "Low,High" newline bitfld.long 0x00 2. " DATA0IN ,DMMDATA[0] input" "Low,High" bitfld.long 0x00 1. " CLKIN ,DMMCLK input" "Low,High" bitfld.long 0x00 0. " SYNCIN ,DMMSYNC input" "Low,High" group.long 0x78++0x03 line.long 0x00 "PC3,DMM Pin Control 3 (OUT)" setclrfld.long 0x00 18. 0x04 18. 0x08 18. " ENAOUT_set/clr ,DMMENA output state" "Low,High" setclrfld.long 0x00 17. 0x04 17. 0x08 17. " DATA15OUT_set/clr ,DMMDATA[15] output state" "Low,High" newline setclrfld.long 0x00 16. 0x04 16. 0x08 16. " DATA14OUT_set/clr ,DMMDATA[14] output state" "Low,High" setclrfld.long 0x00 15. 0x04 15. 0x08 15. " DATA13OUT_set/clr ,DMMDATA[13] output state" "Low,High" newline setclrfld.long 0x00 14. 0x04 14. 0x08 14. " DATA12OUT_set/clr ,DMMDATA[12] output state" "Low,High" setclrfld.long 0x00 13. 0x04 13. 0x08 13. " DATA11OUT_set/clr ,DMMDATA[11] output state" "Low,High" newline setclrfld.long 0x00 12. 0x04 12. 0x08 12. " DATA10OUT_set/clr ,DMMDATA[10] output state" "Low,High" setclrfld.long 0x00 11. 0x04 11. 0x08 11. " DATA9OUT_set/clr ,DMMDATA[9] output state" "Low,High" newline setclrfld.long 0x00 10. 0x04 10. 0x08 10. " DATA8OUT_set/clr ,DMMDATA[8] output state" "Low,High" setclrfld.long 0x00 9. 0x04 9. 0x08 9. " DATA7OUT_set/clr ,DMMDATA[7] output state" "Low,High" newline setclrfld.long 0x00 8. 0x04 8. 0x08 8. " DATA6OUT_set/clr ,DMMDATA[6] output state" "Low,High" setclrfld.long 0x00 7. 0x04 7. 0x08 7. " DATA5OUT_set/clr ,DMMDATA[5] output state" "Low,High" newline setclrfld.long 0x00 6. 0x04 6. 0x08 6. " DATA4OUT_set/clr ,DMMDATA[4] output state" "Low,High" setclrfld.long 0x00 5. 0x04 5. 0x08 5. " DATA3OUT_set/clr ,DMMDATA[3] output state" "Low,High" newline setclrfld.long 0x00 4. 0x04 4. 0x08 4. " DATA2OUT_set/clr ,DMMDATA[2] output state" "Low,High" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " DATA1OUT_set/clr ,DMMDATA[1] output state" "Low,High" newline setclrfld.long 0x00 2. 0x04 2. 0x08 2. " DATA0OUT_set/clr ,DMMDATA[0] output state" "Low,High" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " CLKOUT_set/clr ,DMMCLK output state" "Low,High" newline setclrfld.long 0x00 0. 0x04 0. 0x08 0. " SYNCOUT_set/clr ,DMMSYNC output state" "Low,High" sif cpu()==("TMS570LS2124-PGE")||cpu()==("TMS570LS2124-ZWT")||cpu()==("TMS570LS2125-PGE")||cpu()==("TMS570LS2125-ZWT")||(cpu()=="TMS570LS2126")||(cpu()=="TMS570LS2127")||cpu()==("TMS570LS2134-PGE")||cpu()==("TMS570LS2134-ZWT")||cpu()==("TMS570LS2135-PGE")||cpu()==("TMS570LS2135-ZWT")||(cpu()=="TMS570LS2136")||(cpu()=="TMS570LS2137")||cpu()==("TMS570LS3134-PGE")||cpu()==("TMS570LS3134-ZWT")||cpu()==("TMS570LS3135-PGE")||cpu()==("TMS570LS3135-ZWT")||(cpu()=="TMS570LS3136")||(cpu()=="TMS570LS3137-PGE")||(cpu()=="TMS570LS3137-ZWT")||(cpu()=="TMS570LS30336") group.long 0x7C++0x03 line.long 0x00 "DSet,Pin Control 4" group.long 0x80++0x03 line.long 0x00 "DClr,Pin Control 5" endif group.long 0x84++0x0B line.long 0x00 "PC6,DDM Pin Control 6 (PDR)" bitfld.long 0x00 18. " ENAPDR ,DMMENA open drain enable" "Disabled,Enabled" bitfld.long 0x00 17. " DATA15PDR ,DMMDATA[15] open drain enable" "Disabled,Enabled" bitfld.long 0x00 16. " DATA14PDR ,DMMDATA[14] open drain enable" "Disabled,Enabled" newline bitfld.long 0x00 15. " DATA13PDR ,DMMDATA[13] open drain enable" "Disabled,Enabled" bitfld.long 0x00 14. " DATA12PDR ,DMMDATA[12] open drain enable" "Disabled,Enabled" bitfld.long 0x00 13. " DATA11PDR ,DMMDATA[11] open drain enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " DATA10PDR ,DMMDATA[10] open drain enable" "Disabled,Enabled" bitfld.long 0x00 11. " DATA9PDR ,DMMDATA[9] open drain enable" "Disabled,Enabled" bitfld.long 0x00 10. " DATA8PDR ,DMMDATA[8] open drain enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " DATA7PDR ,DMMDATA[7] open drain enable" "Disabled,Enabled" bitfld.long 0x00 8. " DATA6PDR ,DMMDATA[6] open drain enable" "Disabled,Enabled" bitfld.long 0x00 7. " DATA5PDR ,DMMDATA[5] open drain enable" "Disabled,Enabled" newline bitfld.long 0x00 6. " DATA4PDR ,DMMDATA[4] open drain enable" "Disabled,Enabled" bitfld.long 0x00 5. " DATA3PDR ,DMMDATA[3] open drain enable" "Disabled,Enabled" bitfld.long 0x00 4. " DATA2PDR ,DMMDATA[2] open drain enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " DATA1PDR ,DMMDATA[1] open drain enable" "Disabled,Enabled" bitfld.long 0x00 2. " DATA0PDR ,DMMDATA[0] open drain enable" "Disabled,Enabled" bitfld.long 0x00 1. " CLKPDR ,DMMCLK open drain enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " SYNCPDR ,DMMSYNC open drain enable" "Disabled,Enabled" line.long 0x04 "PC7,DMM Pin Control 7 (PDIS)" bitfld.long 0x04 18. " ENAPDIS ,DMMENA pull disable" "Enabled,Disabled" bitfld.long 0x04 17. " DATA15PDIS ,DMMDATA[15] pull disable" "Enabled,Disabled" bitfld.long 0x04 16. " DATA14PDIS ,DMMDATA[14] pull disable" "Enabled,Disabled" bitfld.long 0x04 15. " DATA13PDIS ,DMMDATA[13] pull disable" "Enabled,Disabled" newline bitfld.long 0x04 14. " DATA12PDIS ,DMMDATA[12] pull disable" "Enabled,Disabled" bitfld.long 0x04 13. " DATA11PDIS ,DMMDATA[11] pull disable" "Enabled,Disabled" bitfld.long 0x04 12. " DATA10PDIS ,DMMDATA[10] pull disable" "Enabled,Disabled" bitfld.long 0x04 11. " DATA9PDIS ,DMMDATA[9] pull disable" "Enabled,Disabled" newline bitfld.long 0x04 10. " DATA8PDIS ,DMMDATA[8] pull disable" "Enabled,Disabled" bitfld.long 0x04 9. " DATA7PDIS ,DMMDATA[7] pull disable" "Enabled,Disabled" bitfld.long 0x04 8. " DATA6PDIS ,DMMDATA[6] Pull disable" "Enabled,Disabled" bitfld.long 0x04 7. " DATA5PDIS ,DMMDATA[5] pull disable" "Enabled,Disabled" newline bitfld.long 0x04 6. " DATA4PDIS ,DMMDATA[4] pull disable" "Enabled,Disabled" bitfld.long 0x04 5. " DATA3PDIS ,DMMDATA[3] pull disable" "Enabled,Disabled" bitfld.long 0x04 4. " DATA2PDIS ,DMMDATA[2] Pull disable" "Enabled,Disabled" bitfld.long 0x04 3. " DATA1PDIS ,DMMDATA[1] pull disable" "Enabled,Disabled" newline bitfld.long 0x04 2. " DATA0PDIS ,DMMDATA[0] pull disable" "Enabled,Disabled" bitfld.long 0x04 1. " CLKPDIS ,DMMCLK pull disable" "Enabled,Disabled" bitfld.long 0x04 0. " SYNCPDIS ,DMMSYNC pull disable" "Enabled,Disabled" line.long 0x08 "PC8,DMM Pin Control 8 (PSEL)" bitfld.long 0x08 18. " ENAPSEL ,DMMENA pull select" "Pull down,Pull up" bitfld.long 0x08 17. " DATA15PSEL ,DMMDATA[15] pull select" "Pull down,Pull up" bitfld.long 0x08 16. " DATA14PSEL ,DMMDATA[14] pull select" "Pull down,Pull up" newline bitfld.long 0x08 15. " DATA13PSEL ,DMMDATA[13] pull select" "Pull down,Pull up" bitfld.long 0x08 14. " DATA12PSEL ,DMMDATA[12] pull select" "Pull down,Pull up" bitfld.long 0x08 13. " DATA11PSEL ,DMMDATA[11] pull select" "Pull down,Pull up" newline bitfld.long 0x08 12. " DATA10PSEL ,DMMDATA[10] pull select" "Pull down,Pull up" bitfld.long 0x08 11. " DATA9PSEL ,DMMDATA[9] pull select" "Pull down,Pull up" bitfld.long 0x08 10. " DATA8PSEL ,DMMDATA[8] pull select" "Pull down,Pull up" newline bitfld.long 0x08 9. " DATA7PSEL ,DMMDATA[7] pull select" "Pull down,Pull up" bitfld.long 0x08 8. " DATA6PSEL ,DMMDATA[6] pull select" "Pull down,Pull up" bitfld.long 0x08 7. " DATA5PSEL ,DMMDATA[5] pull select" "Pull down,Pull up" newline bitfld.long 0x08 6. " DATA4PSEL ,DMMDATA[4] pull select" "Pull down,Pull up" bitfld.long 0x08 5. " DATA3PSEL ,DMMDATA[3] pull select" "Pull down,Pull up" bitfld.long 0x08 4. " DATA2PSEL ,DMMDATA[2] pull select" "Pull down,Pull up" newline bitfld.long 0x08 3. " DATA1PSEL ,DMMDATA[1] pull select" "Pull down,Pull up" bitfld.long 0x08 2. " DATA0PSEL ,DMMDATA[0] pull select" "Pull down,Pull up" bitfld.long 0x08 1. " CLKPDSEL ,DMMCLK pull select" "Pull down,Pull up" newline bitfld.long 0x08 0. " SYNCPSEL ,DMMSYNC pull select" "Pull down,Pull up" width 0x0B tree.end tree "ESM (Error Signaling Module)" base ad:0xFFFFF500 width 8. group.long 0x00++0x3 line.long 0x0 "IEPSR1,Influence Error Pin Set/Status Register 1" setclrfld.long 0x00 31. 0x00 31. 0x04 31. " IEPSET[31]_set/clr ,Set/Clear Influence on Error Pin 31 (CCM-R4 - selftest)" "No influence,Influence" setclrfld.long 0x00 28. 0x00 28. 0x04 28. " IEPSET[28]_set/clr ,Set/Clear Influence on Error Pin 28 (B1TCM)" "No influence,Influence" textline " " setclrfld.long 0x00 27. 0x00 27. 0x04 27. " IEPSET[27]_set/clr ,Set/Clear Influence on Error Pin 27 (CPU - selftest)" "No influence,Influence" setclrfld.long 0x00 26. 0x00 26. 0x04 26. " IEPSET[26]_set/clr ,Set/Clear Influence on Error Pin 26 (B0TCM)" "No influence,Influence" textline " " setclrfld.long 0x00 24. 0x00 24. 0x04 24. " IEPSET[24]_set/clr ,Set/Clear Influence on Error Pin 24 (MibSPIP5 - parity)" "No influence,Influence" setclrfld.long 0x00 23. 0x00 23. 0x04 23. " IEPSET[23]_set/clr ,Set/Clear Influence on Error Pin 23 (DCAN2 - parity)" "No influence,Influence" textline " " setclrfld.long 0x00 22. 0x00 22. 0x04 22. " IEPSET[22]_set/clr ,Set/Clear Influence on Error Pin 22 (DCAN3 - parity)" "No influence,Influence" setclrfld.long 0x00 21. 0x00 21. 0x04 21. " IEPSET[21]_set/clr ,Set/Clear Influence on Error Pin 21 (DCAN1 - parity)" "No influence,Influence" textline " " setclrfld.long 0x00 19. 0x00 19. 0x04 19. " IEPSET[19]_set/clr ,Set/Clear Influence on Error Pin 19 (MibADC1 - parity)" "No influence,Influence" setclrfld.long 0x00 18. 0x00 18. 0x04 18. " IEPSET[18]_set/clr ,Set/Clear Influence on Error Pin 18 (MibSPI3 - parity)" "No influence,Influence" textline " " setclrfld.long 0x00 17. 0x00 17. 0x04 17. " IEPSET[17]_set/clr ,Set/Clear Influence on Error Pin 17 (MibSPI1 - parity)" "No influence,Influence" setclrfld.long 0x00 16. 0x00 16. 0x04 16. " IEPSET[16]_set/clr ,Set/Clear Influence on Error Pin 16 (Flexray TU - MPU)" "No influence,Influence" textline " " setclrfld.long 0x00 15. 0x00 25. 0x04 15. " IEPSET[15]_set/clr ,Set/Clear Influence on Error Pin 15 (VIM RAM - parity)" "No influence,Influence" setclrfld.long 0x00 14. 0x00 14. 0x04 14. " IEPSET[14]_set/clr ,Set/Clear Influence on Error Pin 14 (Flexray TU - parity)" "No influence,Influence" textline " " setclrfld.long 0x00 13. 0x00 13. 0x04 13. " IEPSET[13]_set/clr ,Set/Clear Influence on Error Pin 13 (DMA/DMM/AHB-AP - imprecise write error)" "No influence,Influence" setclrfld.long 0x00 12. 0x00 12. 0x04 12. " IEPSET[12]_set/clr ,Set/Clear Influence on Error Pin 12 (Flexray - parity)" "No influence,Influence" textline " " setclrfld.long 0x00 11. 0x00 11. 0x04 11. " IEPSET[11]_set/clr ,Set/Clear Influence on Error Pin 11 (Clock Monitor - interrupt)" "No influence,Influence" setclrfld.long 0x00 10. 0x00 10. 0x04 10. " IEPSET[10]_set/clr ,Set/Clear Influence on Error Pin 10 (PLL - slip)" "No influence,Influence" textline " " setclrfld.long 0x00 9. 0x00 9. 0x04 9. " IEPSET[9]_set/clr ,Set/Clear Influence on Error Pin 9 (HET TU - MPU)" "No influence,Influence" setclrfld.long 0x00 8. 0x00 8. 0x04 8. " IEPSET[8]_set/clr ,Set/Clear Influence on Error Pin 8 (HET TU - parity)" "No influence,Influence" textline " " setclrfld.long 0x00 7. 0x00 7. 0x04 7. " IEPSET[7]_set/clr ,Set/Clear Influence on Error Pin 7 (NHET - parity)" "No influence,Influence" setclrfld.long 0x00 6. 0x00 6. 0x04 6. " IEPSET[6]_set/clr ,Set/Clear Influence on Error Pin 6 (Flash (ATCM) - correctable error)" "No influence,Influence" textline " " setclrfld.long 0x00 5. 0x00 5. 0x04 5. " IEPSET[5]_set/clr ,Set/Clear Influence on Error Pin 5 (DMA/DMM/AHB-AP - imprecise read error)" "No influence,Influence" setclrfld.long 0x00 3. 0x00 3. 0x04 3. " IEPSET[3]_set/clr ,Set/Clear Influence on Error Pin 3 (DMA - parity)" "No influence,Influence" textline " " setclrfld.long 0x00 2. 0x00 2. 0x04 2. " IEPSET[2]_set/clr ,Set/Clear Influence on Error Pin 2 (DMA - MPU)" "No influence,Influence" width 8. group.long 0x08++0x3 line.long 0x0 "IESR1,Interrupt Enable Set/Status Register 1" setclrfld.long 0x00 31. 0x00 31. 0x04 31. " INTENSET[31]_set/clr ,Set/Clear Interrupt Enable 31 (CCM-R4 - selftest)" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x04 28. " INTENSET[28]_set/clr ,Set/Clear Interrupt Enable 28 (B1TCM)" "Disabled,Enabled" textline " " setclrfld.long 0x00 27. 0x00 27. 0x04 27. " INTENSET[27]_set/clr ,Set/Clear Interrupt Enable 27 (CPU - selftest)" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x04 26. " INTENSET[26]_set/clr ,Set/Clear Interrupt Enable 26 (B0TCM)" "Disabled,Enabled" textline " " setclrfld.long 0x00 24. 0x00 24. 0x04 24. " INTENSET[24]_set/clr ,Set/Clear Interrupt Enable 24 (MibSPIP5 - parity)" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x04 23. " INTENSET[23]_set/clr ,Set/Clear Interrupt Enable 23 (DCAN2 - parity)" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x04 22. " INTENSET[22]_set/clr ,Set/Clear Interrupt Enable 22 (DCAN3 - parity)" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x04 21. " INTENSET[21]_set/clr ,Set/Clear Interrupt Enable 21 (DCAN1 - parity)" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x04 19. " INTENSET[19]_set/clr ,Set/Clear Interrupt Enable 19 (MibADC1 - parity)" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x04 18. " INTENSET[18]_set/clr ,Set/Clear Interrupt Enable 18 (MibSPI3 - parity)" "Disabled,Enabled" textline " " setclrfld.long 0x00 17. 0x00 17. 0x04 17. " INTENSET[17]_set/clr ,Set/Clear Interrupt Enable 17 (MibSPI1 - parity)" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x04 16. " INTENSET[16]_set/clr ,Set/Clear Interrupt Enable 16 (Flexray TU - MPU)" "Disabled,Enabled" textline " " setclrfld.long 0x00 15. 0x00 15. 0x04 15. " INTENSET[15]_set/clr ,Set/Clear Interrupt Enable 15 (VIM RAM - parity)" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x04 14. " INTENSET[14]_set/clr ,Set/Clear Interrupt Enable 14 (Flexray TU - parity)" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x04 13. " INTENSET[13]_set/clr ,Set/Clear Interrupt Enable 13 (DMA/DMM/AHB-AP - imprecise write error)" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x04 12. " INTENSET[12]_set/clr ,Set/Clear Interrupt Enable 12 (Flexray - parity)" "Disabled,Enabled" textline " " setclrfld.long 0x00 11. 0x00 11. 0x04 11. " INTENSET[11]_set/clr ,Set/Clear Interrupt Enable 11 (Clock Monitor - interrupt)" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x04 10. " INTENSET[10]_set/clr ,Set/Clear Interrupt Enable 10 (PLL - slip)" "Disabled,Enabled" textline " " setclrfld.long 0x00 9. 0x00 9. 0x04 9. " INTENSET[9]_set/clr ,Set/Clear Interrupt Enable 9 (HET TU - MPU)" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x04 8. " INTENSET[8]_set/clr ,Set/Clear Interrupt Enable 8 (HET TU - parity)" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x04 7. " INTENSET[7]_set/clr ,Set/Clear Interrupt Enable 7 (NHET - parity)" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x04 6. " INTENSET[6]_set/clr ,Set/Clear Interrupt Enable 6 (Flash (ATCM) - correctable error)" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. 0x00 5. 0x04 5. " INTENSET[5]_set/clr ,Set/Clear Interrupt Enable 5 (DMA/DMM/AHB-AP - imprecise read error)" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x04 3. " INTENSET[3]_set/clr ,Set/Clear Interrupt Enable 3 (DMA - parity)" "Disabled,Enabled" textline " " setclrfld.long 0x00 2. 0x00 2. 0x04 2. " INTENSET[2]_set/clr ,Set/Clear Interrupt Enable 2 (DMA - MPU)" "Disabled,Enabled" width 8. group.long 0x10++0x3 line.long 0x0 "ILSR1,Interrupt Level Set/Status Register 1" setclrfld.long 0x00 31. 0x00 31. 0x04 31. " INTLVLSET_set/clr[31] ,Set/Clear Interrupt Level 31 (CCM-R4 - selftest)" "Low,High" setclrfld.long 0x00 28. 0x00 28. 0x04 28. " INTLVLSET_set/clr[28] ,Set/Clear Interrupt Level 28 (B1TCM)" "Low,High" textline " " setclrfld.long 0x00 27. 0x00 27. 0x04 27. " INTLVLSET_set/clr[27] ,Set/Clear Interrupt Level 27 (CPU - selftest)" "Low,High" setclrfld.long 0x00 26. 0x00 26. 0x04 26. " INTLVLSET_set/clr[26] ,Set/Clear Interrupt Level 26 (B0TCM)" "Low,High" textline " " setclrfld.long 0x00 24. 0x00 24. 0x04 24. " INTLVLSET_set/clr[24] ,Set/Clear Interrupt Level 24 (MibSPIP5 - parity)" "Low,High" setclrfld.long 0x00 23. 0x00 23. 0x04 23. " INTLVLSET_set/clr[23] ,Set/Clear Interrupt Level 23 (DCAN2 - parity)" "Low,High" textline " " setclrfld.long 0x00 22. 0x00 22. 0x04 22. " INTLVLSET_set/clr[22] ,Set/Clear Interrupt Level 22 (DCAN3 - parity)" "Low,High" setclrfld.long 0x00 21. 0x00 21. 0x04 21. " INTLVLSET_set/clr[21] ,Set/Clear Interrupt Level 21 (DCAN1 - parity)" "Low,High" textline " " setclrfld.long 0x00 19. 0x00 19. 0x04 19. " INTLVLSET_set/clr[19] ,Set/Clear Interrupt Level 19 (MibADC1 - parity)" "Low,High" setclrfld.long 0x00 18. 0x00 18. 0x04 18. " INTLVLSET_set/clr[18] ,Set/Clear Interrupt Level 18 (MibSPI3 - parity)" "Low,High" textline " " setclrfld.long 0x00 17. 0x00 17. 0x04 17. " INTLVLSET_set/clr[17] ,Set/Clear Interrupt Level 17 (MibSPI1 - parity)" "Low,High" setclrfld.long 0x00 16. 0x00 16. 0x04 16. " INTLVLSET_set/clr[16] ,Set/Clear Interrupt Level 16 (Flexray TU - MPU)" "Low,High" textline " " setclrfld.long 0x00 15. 0x00 15. 0x04 15. " INTLVLSET_set/clr[15] ,Set/Clear Interrupt Level 15 (VIM RAM - parity)" "Low,High" setclrfld.long 0x00 14. 0x00 14. 0x04 14. " INTLVLSET_set/clr[14] ,Set/Clear Interrupt Level 14 (Flexray TU - parity)" "Low,High" textline " " setclrfld.long 0x00 13. 0x00 13. 0x04 13. " INTLVLSET_set/clr[13] ,Set/Clear Interrupt Level 13 (DMA/DMM/AHB-AP - imprecise write error)" "Low,High" setclrfld.long 0x00 12. 0x00 12. 0x04 12. " INTLVLSET_set/clr[12] ,Set/Clear Interrupt Level 12 (Flexray - parity)" "Low,High" textline " " setclrfld.long 0x00 11. 0x00 11. 0x04 11. " INTLVLSET_set/clr[11] ,Set/Clear Interrupt Level 11 (Clock Monitor - interrupt)" "Low,High" setclrfld.long 0x00 10. 0x00 10. 0x04 10. " INTLVLSET_set/clr[10] ,Set/Clear Interrupt Level 10 (PLL - slip)" "Low,High" textline " " setclrfld.long 0x00 9. 0x00 9. 0x04 9. " INTLVLSET_set/clr[9] ,Set/Clear Interrupt Level 9 (HET TU - MPU)" "Low,High" setclrfld.long 0x00 8. 0x00 8. 0x04 8. " INTLVLSET_set/clr[8] ,Set/Clear Interrupt Level 8 (HET TU - parity)" "Low,High" textline " " setclrfld.long 0x00 7. 0x00 7. 0x04 7. " INTLVLSET_set/clr[7] ,Set/Clear Interrupt Level 7 (NHET - parity)" "Low,High" setclrfld.long 0x00 6. 0x00 6. 0x04 6. " INTLVLSET_set/clr[6] ,Set/Clear Interrupt Level 6 (Flash (ATCM) - correctable error)" "Low,High" textline " " setclrfld.long 0x00 5. 0x00 5. 0x04 5. " INTLVLSET_set/clr[5] ,Set/Clear Interrupt Level 5 (DMA/DMM/AHB-AP - imprecise read error)" "Low,High" setclrfld.long 0x00 3. 0x00 3. 0x04 3. " INTLVLSET_set/clr[3] ,Set/Clear Interrupt Level 3 (DMA - parity)" "Low,High" textline " " setclrfld.long 0x00 2. 0x00 2. 0x04 2. " INTLVLSET_set/clr[2] ,Set/Clear Interrupt Level 2 (DMA - MPU)" "Low,High" width 8. group.long 0x18++0x3 line.long 0x0 "SR1,Status Register 1" eventfld.long 0x00 31. " ESF[31] ,Error Status Flag 31 (CCM-R4 - selftest)" "No error,Error" eventfld.long 0x00 28. " ESF[28] ,Error Status Flag 28 (B1TCM)" "No error,Error" eventfld.long 0x00 27. " ESF[27] ,Error Status Flag 27 (CPU - selftest)" "No error,Error" eventfld.long 0x00 26. " ESF[26] ,Error Status Flag 26 (B0TCM)" "No error,Error" textline " " eventfld.long 0x00 24. " ESF[24] ,Error Status Flag 24 (MibSPIP5 - parity)" "No error,Error" eventfld.long 0x00 23. " ESF[23] ,Error Status Flag 23 (DCAN2 - parity)" "No error,Error" eventfld.long 0x00 22. " ESF[22] ,Error Status Flag 22 (DCAN3 - parity)" "No error,Error" eventfld.long 0x00 21. " ESF[21] ,Error Status Flag 21 (DCAN1 - parity)" "No error,Error" textline " " eventfld.long 0x00 19. " ESF[19] ,Error Status Flag 19 (MibADC1 - parity)" "No error,Error" eventfld.long 0x00 18. " ESF[18] ,Error Status Flag 18 (MibSPI3 - parity)" "No error,Error" eventfld.long 0x00 17. " ESF[17] ,Error Status Flag 17 (MibSPI1 - parity)" "No error,Error" eventfld.long 0x00 16. " ESF[16] ,Error Status Flag 16 (Flexray TU - MPU)" "No error,Error" textline " " eventfld.long 0x00 15. " ESF[15] ,Error Status Flag 15 (VIM RAM - parity)" "No error,Error" eventfld.long 0x00 14. " ESF[14] ,Error Status Flag 14 (Flexray TU - parity)" "No error,Error" eventfld.long 0x00 13. " ESF[13] ,Error Status Flag 13 (DMA/DMM/AHB-AP - imprecise write error)" "No error,Error" eventfld.long 0x00 12. " ESF[12] ,Error Status Flag 12 (Flexray - parity)" "No error,Error" textline " " eventfld.long 0x00 11. " ESF[11] ,Error Status Flag 11 (Clock Monitor - interrupt)" "No error,Error" eventfld.long 0x00 10. " ESF[10] ,Error Status Flag 10 (PLL - slip)" "No error,Error" eventfld.long 0x00 9. " ESF[9] ,Error Status Flag 9 (HET TU - MPU)" "No error,Error" eventfld.long 0x00 8. " ESF[8] ,Error Status Flag 8 (HET TU - parity)" "No error,Error" textline " " eventfld.long 0x00 7. " ESF[7] ,Error Status Flag 7 (NHET - parity)" "No error,Error" eventfld.long 0x00 6. " ESF[6] ,Error Status Flag 6 (Flash (ATCM) - correctable error)" "No error,Error" eventfld.long 0x00 5. " ESF[5] ,Error Status Flag 5 (DMA/DMM/AHB-AP - imprecise read error)" "No error,Error" eventfld.long 0x00 3. " ESF[3] ,Error Status Flag 3 (DMA - parity)" "No error,Error" textline " " eventfld.long 0x00 2. " ESF[2] ,Error Status Flag 2 (DMA - MPU)" "No error,Error" group.long 0x1C++0x3 line.long 0x0 "SR2,Status Register 2" eventfld.long 0x00 16. " ESF[16] ,Error Status Flag 16 (Flash (ATCM) - ECC live lock detect)" "No error,Error" eventfld.long 0x00 12. " ESF[12] ,Error Status Flag 12 (B1TCM - address bus parity error)" "No error,Error" eventfld.long 0x00 10. " ESF[10] ,Error Status Flag 10 (B0TCM - address bus parity error)" "No error,Error" textline " " eventfld.long 0x00 8. " ESF[8] ,Error Status Flag 8 (B1TCM - uncorrectable error)" "No error,Error" eventfld.long 0x00 6. " ESF[6] ,Error Status Flag 6 (B0TCM - uncorrectable error)" "No error,Error" eventfld.long 0x00 4. " ESF[4] ,Error Status Flag 4 (Flash (ATCM) - uncorrectable error)" "No error,Error" eventfld.long 0x00 2. " ESF[2] ,Error Status Flag 2 (CCM-R4 - compare)" "No error,Error" group.long 0x20++0x3 line.long 0x0 "SR3,Status Register 3" eventfld.long 0x00 7. " ESF[7] ,Error Status Flag 7 (Flash (ATCM) - ECC uncorrectable error)" "No error,Error" eventfld.long 0x00 5. " ESF[5] ,Error Status Flag 5 (B1TCM - ECC uncorrectable error)" "No error,Error" eventfld.long 0x00 3. " ESF[3] ,Error Status Flag 3 (B0TCM - ECC uncorrectable error)" "No error,Error" width 8. rgroup.long 0x24++0x3 line.long 0x0 "EPSR,Error Pin Status Register" bitfld.long 0x00 0. " EPSF ,Error Pin Status Flag" "Active,Not active" rgroup.long 0x28++0x3 line.long 0x0 "IOFFHR,Interrupt Offset High Register" hexmask.long.byte 0x00 0.--6. 1. " INTOFFH ,Offset High Level Interrupt" rgroup.long 0x2C++0x3 line.long 0x0 "IOFFLR,Interrupt Offset Low Register" hexmask.long.byte 0x00 0.--6. 1. " INTOFFL ,Offset Low Level Interrupt" rgroup.long 0x30++0x3 line.long 0x0 "LTCR,Low-Time Counter Register" hexmask.long.word 0x00 0.--15. 1. " LTC ,Error Pin Low-Time Counter" group.long 0x34++0x3 line.long 0x0 "LTCPR,Low-Time Counter Preload Register" bitfld.long 0x00 14.--15. " LTCP[15:14] ,Low-Time Counter Pre-load Value [15:14]" "0,1,2,3" textline " " hexmask.long.word 0x00 0.--13. 1. " LTCP[13:0] ,Low-Time Counter Pre-load Value [13:0]" group.long 0x38++0x3 line.long 0x0 "EKR,Error Key Register" bitfld.long 0x00 0.--3. " EKEY ,Error Key" "Normal,Normal,Normal,Normal,Normal,LTC,Normal,Normal,Normal,Normal,Forced,Normal,Normal,Normal,Normal,Normal" width 8. group.long 0x3C++0x3 line.long 0x0 "SSR2,Status Shadow Register" eventfld.long 0x00 16. " ESF[16] ,Error Status Flag 16 (Flash (ATCM) - ECC live lock detect)" "No error,Error" eventfld.long 0x00 12. " ESF[12] ,Error Status Flag 12 (B1TCM - address bus parity error)" "No error,Error" eventfld.long 0x00 10. " ESF[10] ,Error Status Flag 10 (B0TCM - address bus parity error)" "No error,Error" eventfld.long 0x00 8. " ESF[8] ,Error Status Flag 8 (B1TCM - uncorrectable error)" "No error,Error" textline " " eventfld.long 0x00 6. " ESF[6] ,Error Status Flag 6 (B0TCM - uncorrectable error)" "No error,Error" eventfld.long 0x00 4. " ESF[4] ,Error Status Flag 4 (Flash (ATCM) - uncorrectable error)" "No error,Error" eventfld.long 0x00 2. " ESF[2] ,Error Status Flag 2 (CCM-R4 - compare)" "No error,Error" width 0xb tree.end tree "Flash_Wrapper" base ad:0xFFF87000 width 15. tree "Flash Configuration Registers" group.long 0x00++0x3 line.long 0x0 "FRDCNTL,Read Control Register" bitfld.long 0x00 24.--27. " IFLUSH_HOLD ,Hold off IFLUSH for This Long" "0 cycles,4 cycles,8 cycles,12 cycles,16 cycles,20 cycles,24 cycles,28 cycles,32 cycles,36 cycles,40 cycles,44 cycles,48 cycles,52 cycles,56 cycles,60 cycles" bitfld.long 0x00 16. " IDL_EN ,Incoming Data Latch" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--11. " RWAIT ,Random Read Wait State" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles" bitfld.long 0x00 4. " ASWSTEN ,Address Setup Wait State Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " RM ,Read Mode" "Non-pipeline mode,Pipeline mode" group.long 0x04++0x3 line.long 0x0 "FSPRD,Special Read Control Register" bitfld.long 0x00 24.--27. " ROM_KEY ,ROM Configurations Only" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" bitfld.long 0x00 16. " DIS-PREEMPT ,Disable Preempt" "No,Yes" textline " " bitfld.long 0x00 1. " RM1 ,Read Margin 1" "Disabled,Enabled" bitfld.long 0x00 0. " RM0 ,Read Margin 0" "Disabled,Enabled" group.long 0x08++0x3 line.long 0x0 "FEDACCTRL1,Error Correction Control Register1" bitfld.long 0x00 24. " SUSP_IGNR ,Suspend Ignore" "Not ignored,Ignored" bitfld.long 0x00 16.--19. " EDACMODE ,Error Correction Mode" "Correction mode,Correction mode,Correction mode,Correction mode,Correction mode,Detection mode,Correction mode,Correction mode,Correction mode,Correction mode,Correction mode,Correction mode,Correction mode,Correction mode,Correction mode,Correction mode" textline " " bitfld.long 0x00 10. " EOFEN ,Error on One Fail Enable" "Disabled,Enabled" bitfld.long 0x00 9. " EZFEN ,Error on Zero Fail Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " EPEN ,Error Profiling Enable" "Disabled,Enabled" bitfld.long 0x00 5. " EOCV ,One Condition Valid" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " EZCV ,Zero Condition Valid" "Disabled,Enabled" bitfld.long 0x00 0.--3. " EDACEN ,Error Detection and Correction Enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" group.long 0x0C++0x3 line.long 0x0 "FEDACCTRL2,Error Correction Control Register2" hexmask.long.word 0x00 0.--15. 1. " SEC_THRESHOLD ,Single Error Correction Threshold" group.long 0x10++0x3 line.long 0x0 "FCOR_ERR_CNT,Error Correction Counter Register" hexmask.long.word 0x00 0.--15. 1. " COR_ERR_CNT ,Correctable Error Counter" rgroup.long 0x14++0x3 line.long 0x0 "FCOR_ERR_ADD,Correctable Error Address" hexmask.long 0x00 3.--26. 0x8 " COR_ERR_ADD ,Error Address" width 15. rgroup.long 0x18++0x3 line.long 0x0 "FCOR_ERR_POS,Correctable Error Position Register" bitfld.long 0x00 9. " ADD_ERR ,Address Error" "No error,Error" bitfld.long 0x00 8. " ECC_ERR ,Error Type" "Data,Check" textline " " hexmask.long.byte 0x00 0.--7. 1. " SERR_POS ,Single Error Position" if (((data.long((ad:0xFFF87000)))&0x1)==0x1) group.long 0x1C++0x3 line.long 0x0 "FEDACSTATUS,Error Status Register" eventfld.long 0x00 12. " D_UNC_ERR ,Diagnostic Un-correctable Error Status Flag" "Not detected,Detected" eventfld.long 0x00 11. " ADD_TAG_ERR ,Address Tag Register Error Status Flag" "Not detected,Detected" textline " " eventfld.long 0x00 10. " ADD_PAR_ERR ,Address Parity Error" "Not detected,Detected" eventfld.long 0x00 9. " BUF_PAR_ERR ,Pipeline Buffer Parity Error Status Flag" "Not detected,Detected" textline " " eventfld.long 0x00 8. " ECC_MUL_ERR ,Multiple bit ECC or Parity Error Status Flag" "Not detected,Detected" eventfld.long 0x00 7. " COM1_MAL_GOOD ,Compare Malfunction Flag" "Not detected,Detected" textline " " eventfld.long 0x00 6. " COM0_MAL_GOOD ,Compare Malfunction Flag" "Not detected,Detected" eventfld.long 0x00 5. " ECC1_MAL_ERR ,ECC Malfunction Status Flag" "Not detected,Detected" textline " " eventfld.long 0x00 4. " ECC0_MAL_ERR ,ECC0 Malfunction Status Flag" "Not detected,Detected" eventfld.long 0x00 3. " D_COR_ERR ,Diagnostic Correctable Error Status Flag" "Not detected,Detected" textline " " eventfld.long 0x00 2. " ERR_ONE_FLG ,Error On One Fail Status Flag" "Not detected,Detected" eventfld.long 0x00 1. " ERR_ZERO_FLG ,Error On Zero Fail Status Flag" "Not detected,Detected" textline " " eventfld.long 0x00 0. " ERR_PRF_FLG ,Error Profiling Status Flag" "Not detected,Detected" elif (((data.long((ad:0xFFF87000)))&0x1)==0x0) group.long 0x1C++0x3 line.long 0x0 "FEDACSTATUS,Error Status Register" eventfld.long 0x00 12. " D_UNC_ERR ,Diagnostic Un-correctable Error Status Flag" "Not detected,Detected" eventfld.long 0x00 10. " ADD_PAR_ERR ,Address Parity Error" "Not detected,Detected" textline " " eventfld.long 0x00 8. " ECC_MUL_ERR ,Multiple bit ECC or Parity Error Status Flag" "Not detected,Detected" eventfld.long 0x00 7. " COM1_MAL_GOOD ,Compare Malfunction Flag" "Not detected,Detected" textline " " eventfld.long 0x00 6. " COM0_MAL_GOOD ,Compare Malfunction Flag" "Not detected,Detected" eventfld.long 0x00 5. " ECC1_MAL_ERR ,ECC Malfunction Status Flag" "Not detected,Detected" textline " " eventfld.long 0x00 4. " ECC0_MAL_ERR ,ECC0 Malfunction Status Flag" "Not detected,Detected" eventfld.long 0x00 3. " D_COR_ERR ,Diagnostic Correctable Error Status Flag" "Not detected,Detected" textline " " eventfld.long 0x00 2. " ERR_ONE_FLG ,Error On One Fail Status Flag" "Not detected,Detected" eventfld.long 0x00 1. " ERR_ZERO_FLG ,Error On Zero Fail Status Flag" "Not detected,Detected" textline " " eventfld.long 0x00 0. " ERR_PRF_FLG ,Error Profiling Status Flag" "Not detected,Detected" endif rgroup.long 0x20++0x3 line.long 0x0 "FUNC_ERR_ADD,Un-correctable Error Address" hexmask.long 0x00 2.--31. 0x4 " UNC_ERR_ADD ,Un-correctable Error Address" width 15. group.long 0x24++0x3 line.long 0x0 "FEDACSDIS,Error Detection Sector Disable" bitfld.long 0x0 29.--31. " BANKID1_INVERSE[2:0] ,Inverted Bank Number 1" "Reserved,Reserved,Reserved,Reserved,Bank 3,Bank 2,Bank 1,Bank 0" bitfld.long 0x0 24.--27. " SECTORID1_INVERSE[3:0] ,Inverted Sector Number 1" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sector 7,Sector 6,Sector 5,Sector 4,Sector 3,Sector 2,Sector 1,Sector 0" textline " " bitfld.long 0x0 21.--23. " BANKID1[2:0] ,Bank Number 1" "Bank 0,Bank 1,Bank 2,Bank 3,?..." bitfld.long 0x0 16.--19. " SECTORID1[3:0] ,Sector Number 1" "Sector 0,Sector 1,Sector 2,Sector 3,Sector 4,Sector 5,Sector 6,Sector 7,?..." textline " " bitfld.long 0x0 13.--15. " BANKID0_INVERSE[2:0] ,Inverted Bank Number 0" "Reserved,Reserved,Reserved,Reserved,Bank 3,Bank 2,Bank 1,Bank 0" bitfld.long 0x0 8.--11. " SECTORID0_INVERSE[3:0] ,Inverted Sector Number 0" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sector 7,Sector 6,Sector 5,Sector 4,Sector 3,Sector 2,Sector 1,Sector 0" textline " " bitfld.long 0x0 5.--7. " BANKID0[2:0] ,Bank Number 0" "Bank 0,Bank 1,Bank 2,Bank 3,?..." bitfld.long 0x0 0.--3. " SECTORID0[3:0] ,Sector Number 0" "Sector 0,Sector 1,Sector 2,Sector 3,Sector 4,Sector 5,Sector 6,Sector 7,?..." group.long 0xc0++0x3 line.long 0x0 "FEDACSDIS1,Error Detection Sector Disable" bitfld.long 0x0 29.--31. " BANKID3_INVERSE[2:0] ,Inverted Bank Number 3" "Reserved,Reserved,Reserved,Reserved,Bank 3,Bank 2,Bank 1,Bank 0" bitfld.long 0x0 24.--27. " SECTORID3_INVERSE[3:0] ,Inverted Sector Number 3" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sector 7,Sector 6,Sector 5,Sector 4,Sector 3,Sector 2,Sector 1,Sector 0" textline " " bitfld.long 0x0 21.--23. " BANKID3[2:0] ,Bank Number 3" "Bank 0,Bank 1,Bank 2,Bank 3,?..." bitfld.long 0x0 16.--19. " SECTORID3[3:0] ,Sector Number 3" "Sector 0,Sector 1,Sector 2,Sector 3,Sector 4,Sector 5,Sector 6,Sector 7,?..." textline " " bitfld.long 0x0 13.--15. " BANKID2_INVERSE[2:0] ,Inverted Bank Number 2" "Reserved,Reserved,Reserved,Reserved,Bank 3,Bank 2,Bank 1,Bank 0" bitfld.long 0x0 8.--11. " SECTORID2_INVERSE[3:0] ,Inverted Sector Number 2" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sector 7,Sector 6,Sector 5,Sector 4,Sector 3,Sector 2,Sector 1,Sector 0" textline " " bitfld.long 0x0 5.--7. " BANKID2[2:0] ,Bank Number 2" "Bank 0,Bank 1,Bank 2,Bank 3,?..." bitfld.long 0x0 0.--3. " SECTORID2[3:0] ,Sector Number 2" "Sector 0,Sector 1,Sector 2,Sector 3,Sector 4,Sector 5,Sector 6,Sector 7,?..." group.long 0x28++0x3 line.long 0x0 "FPRIM_ADD_TAG,Primary Address Tag Register" hexmask.long 0x00 4.--22. 0x10 " PRIM_ADD_TAG ,Primary Address Tag Register" group.long 0x2C++0x3 line.long 0x0 "FREDU_ADD_TAG,Redundant Address Tag Register" hexmask.long 0x00 4.--22. 0x10 " REDU_ADD_TAG ,Redundant Address Tag Register" group.long 0x30++0x3 line.long 0x0 "FBPROT,Bank Protection Register" bitfld.long 0x00 0. " PROTL1DIS ,Level 1 Protection Disabled" "No,Yes" width 15. group.long 0x34++0x3 line.long 0x0 "FBSE,Bank Sector Enable Register" bitfld.long 0x00 15. " BSE[15] ,Bank Sector Enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " BSE[14] ,Bank Sector Enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " BSE[13] ,Bank Sector Enable 13" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " BSE[12] ,Bank Sector Enable 12" "Disabled,Enabled" bitfld.long 0x00 11. " BSE[11] ,Bank Sector Enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " BSE[10] ,Bank Sector Enable 10" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " BSE[9] ,Bank Sector Enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " BSE[8] ,Bank Sector Enable 8" "Disabled,Enabled" bitfld.long 0x00 7. " BSE[7] ,Bank Sector Enable 7" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " BSE[6] ,Bank Sector Enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " BSE[5] ,Bank Sector Enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " BSE[4] ,Bank Sector Enable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " BSE[3] ,Bank Sector Enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " BSE[2] ,Bank Sector Enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " BSE[1] ,Bank Sector Enable 1" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " BSE[0] ,Bank Sector Enable 0" "Disabled,Enabled" width 15. rgroup.long 0x38++0x3 line.long 0x0 "FBUSY,Bank Busy Register" bitfld.long 0x00 7. " BUSY[7] ,Bank Busy 7" "Not busy,Busy" bitfld.long 0x00 6. " BUSY[6] ,Bank Busy 6" "Not busy,Busy" bitfld.long 0x00 5. " BUSY[5] ,Bank Busy 5" "Not busy,Busy" textline " " bitfld.long 0x00 4. " BUSY[4] ,Bank Busy 4" "Not busy,Busy" bitfld.long 0x00 3. " BUSY[3] ,Bank Busy 3" "Not busy,Busy" bitfld.long 0x00 2. " BUSY[2] ,Bank Busy 2" "Not busy,Busy" textline " " bitfld.long 0x00 1. " BUSY[1] ,Bank Busy 1" "Not busy,Busy" bitfld.long 0x00 0. " BUSY[0] ,Bank Busy 0" "Not busy,Busy" width 15. group.long 0x3C++0x3 line.long 0x0 "FBAC,Bank Access Control Register" bitfld.long 0x00 23. " OTPPROTDIS[7] ,OTP Sector Protection Disable 7" "Disabled,Enabled" bitfld.long 0x00 22. " OTPPROTDIS[6] ,OTP Sector Protection Disable 6" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " OTPPROTDIS[5] ,OTP Sector Protection Disable 5" "Disabled,Enabled" bitfld.long 0x00 20. " OTPPROTDIS[4] ,OTP Sector Protection Disable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " OTPPROTDIS[3] ,OTP Sector Protection Disable 3" "Disabled,Enabled" bitfld.long 0x00 18. " OTPPROTDIS[2] ,OTP Sector Protection Disable 2" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " OTPPROTDIS[1] ,OTP Sector Protection Disable 1" "Disabled,Enabled" bitfld.long 0x00 16. " OTPPROTDIS[0] ,OTP Sector Protection Disable 0" "Disabled,Enabled" textline " " hexmask.long.byte 0x00 8.--15. 1. " BAGP[7:0] ,Bank Active Grace Period" hexmask.long.byte 0x00 0.--7. 1. " VREADST[7:0] ,VREAD Setup" width 15. group.long 0x40++0x3 line.long 0x0 "FBFALLBACK,Bank Fallback Power Register" bitfld.long 0x00 24.--27. " FSM_PWRSAV ,Power Saving Clocking Control" "FSM,FSM,FSM,FSM,FSM,FSM,FSM,FSM,FSM,FSM,Off,FSM,FSM,FSM,FSM,FSM" bitfld.long 0x00 16.--19. " VBUS_PWRSAV ,Power Saving Clocking Control" "VBUS,VBUS,VBUS,VBUS,VBUS,VBUS,VBUS,VBUS,VBUS,VBUS,Off,VBUS,VBUS,VBUS,VBUS,VBUS" textline " " bitfld.long 0x00 14.--15. " BANKPWR7[1:0] ,Bank 7 Fallback Power Mode" "Sleep,Standby,Reserved,Active" bitfld.long 0x00 12.--13. " BANKPWR6[1:0] ,Bank 6 Fallback Power Mode" "Sleep,Standby,Reserved,Active" textline " " bitfld.long 0x00 10.--11. " BANKPWR5[1:0] ,Bank 5 Fallback Power Mode" "Sleep,Standby,Reserved,Active" bitfld.long 0x00 8.--9. " BANKPWR4[1:0] ,Bank 4 Fallback Power Mode" "Sleep,Standby,Reserved,Active" textline " " bitfld.long 0x00 6.--7. " BANKPWR3[1:0] ,Bank 3 Fallback Power Mode" "Sleep,Standby,Reserved,Active" bitfld.long 0x00 4.--5. " BANKPWR2[1:0] ,Bank 2 Fallback Power Mode" "Sleep,Standby,Reserved,Active" textline " " bitfld.long 0x00 2.--3. " BANKPWR1[1:0] ,Bank 1 Fallback Power Mode" "Sleep,Standby,Reserved,Active" bitfld.long 0x00 0.--1. " BANKPWR0[1:0] ,Bank 0 Fallback Power Mode" "Sleep,Standby,Reserved,Active" width 15. rgroup.long 0x44++0x3 line.long 0x0 "FBPRDY,Bank/Pump Ready Register" bitfld.long 0x00 15. " PUMPRDY ,Pump Ready" "Not ready,Ready" bitfld.long 0x00 7. " BANKRDY[7] ,Bank Ready 7" "Not ready,Ready" textline " " bitfld.long 0x00 6. " BANKRDY[6] ,Bank Ready 6" "Not ready,Ready" bitfld.long 0x00 5. " BANKRDY[5] ,Bank Ready 5" "Not ready,Ready" textline " " bitfld.long 0x00 4. " BANKRDY[4] ,Bank Ready 4" "Not ready,Ready" bitfld.long 0x00 3. " BANKRDY[3] ,Bank Ready 3" "Not ready,Ready" textline " " bitfld.long 0x00 2. " BANKRDY[2] ,Bank Ready 2" "Not ready,Ready" bitfld.long 0x00 1. " BANKRDY[1] ,Bank Ready 1" "Not ready,Ready" textline " " bitfld.long 0x00 0. " BANKRDY[0] ,Bank Ready 0" "Not ready,Ready" group.long 0x48++0x3 line.long 0x0 "FPAC1,Pump Access Control Register 1" hexmask.long.word 0x00 16.--26. 1. " PSLEEP[10:0] ,Pump Sleep" bitfld.long 0x00 0. " PUMPPWR ,Flash Charge Pump Fallback Power Mode" "Sleep,Active" group.long 0x4C++0x3 line.long 0x0 "FPAC2,Pump Access Control Register 2" hexmask.long.word 0x0 0.--15. 1. " PAGP[15:0] ,Pump Active Grace Period" group.long 0x50++0x3 line.long 0x0 "FMAC,Module Access Control Register" bitfld.long 0x0 0.--2. " BANK[2:0] ,Bank Enable" "Bank 0,Bank 1,Bank 2,Bank 3,Bank 4,Bank 5,Bank 6,Bank7" width 15. rgroup.long 0x54++0x3 line.long 0x0 "FMSTAT,Module Status Register" bitfld.long 0x00 14. " ILA ,Illegal Address" "Not detected,Detected" bitfld.long 0x00 13. " DBF ,Disturbance Test Fail" "Not failed,Failed" textline " " bitfld.long 0x00 12. " PGV ,Program Verify" "Not success,Success" bitfld.long 0x00 11. " PCV ,Precondition Verify" "Not success,Success" textline " " bitfld.long 0x00 10. " EV ,Erase Verify" "Not success,Success" bitfld.long 0x00 9. " CV ,Compact Verify" "Not success,Success" textline " " bitfld.long 0x0 8. " BUSY ,Busy" "Not busy,Busy" bitfld.long 0x0 7. " ERS ,Erase Active" "Not active,Active" textline " " bitfld.long 0x0 6. " PGM ,Program Active" "Not active,Active" bitfld.long 0x0 5. " INVDAT ,Invalid Data" "Not occurred,Occurred" textline " " bitfld.long 0x0 4. " CSTAT ,Command Status" "Not failed,Failed" bitfld.long 0x0 3. " 5VSTAT ,VDD5V Status" "Above lower limit,Below lower limit" textline " " bitfld.long 0x0 2. " ESUSP ,Erase Suspend" "Not occurred,Occurred" bitfld.long 0x0 1. " PSUSP ,Program Suspend" "Not received/processed,Received/processed" textline " " bitfld.long 0x0 0. " SLOCK ,Sector Lock Status" "Not locked,Locked" group.long 0x58++0x3 line.long 0x0 "FEMU_DMSW,EEPROM Emulation Data MSW Register" group.long 0x5c++0x3 line.long 0x0 "FEMU_DLSW,EEPROM Emulation Data LSW Register" group.long 0x60++0x3 line.long 0x0 "FEMU_ECC,EEPROM Emulation ECC Register" hexmask.long.byte 0x00 16.--23. 1. " RD_ECC ,Special RD_ECC for CPU_TYPE=5 Configurations Only" hexmask.long.byte 0x00 0.--7. 1. " EMU_ECC ,Emulation ECC" group.long 0x64++0x3 line.long 0x0 "FLOCK,Flash Lock Register" hexmask.long.word 0x00 0.--15. 1. " ENCOM ,Enable Command Registers" group.long 0x68++0x3 line.long 0x0 "FEMU_ADDR,EEPROM Emulation Address" hexmask.long 0x00 3.--21. 0x8 " EMU_ADDR ,EEPROM Emulation Address" width 15. group.long 0x6C++0x3 line.long 0x0 "FDIAGCTRL,Diagnostic Control Register" bitfld.long 0x00 24. " DIAG_TRIG ,Diagnostic Trigger" "Not triggered,Triggered" bitfld.long 0x00 16.--19. " DIAG_EN_KEY ,Diagnostic Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled" textline " " bitfld.long 0x00 12. " DIAG_ECC_SEL ,Diagnostic SECDED Select" "SECDED0,SECDED1" textline " " bitfld.long 0x00 8.--11. " DIAG_BUF_SEL[3:0] ,Diagnostic Buffer Select" "Instruction 0,Data 0,Instruction 1,Data 1,?..." textline " " bitfld.long 0x00 0.--2. " DIAGMODE[2:0] ,Diagnostic Mode" "Disabled,Correction mode,Syndrome reporting,Same data,Inverted data,Address tag register,Pipeline buffer parity,Disabled" group.long 0x70++0x3 line.long 0x0 "FRAWDATAH,Uncorrected Raw Data High" group.long 0x74++0x3 line.long 0x0 "FRAWDATAL,Uncorrected Raw Data Low" group.long 0x78++0x3 line.long 0x0 "FRAWECC,Uncorrected Raw ECC" hexmask.long.byte 0x00 0.--7. 1. " RAW_ECC[7:0] ,Uncorrected Raw ECC" width 15. group.long 0x7C++0x3 line.long 0x0 "FPAR_OVR,Parity Override" bitfld.long 0x00 16. " BNK_INV_PAR ,Buffer Invert Parity" "Used,Not used" bitfld.long 0x00 12.--15. " BUS_PAR_DIS ,Disable Bus Parity" "Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled" textline " " bitfld.long 0x00 9.--11. " PAR_OVR_KEY ,PAR_OVR_KEY" "DEVCR1,DEVCR1,DEVCR1,DEVCR1,DEVCR1,ADD/DAT_INV_PAR,DEVCR1,DEVCR1" bitfld.long 0x00 8. " ADD_INV_PAR ,Address Odd Parity" "Inverted,Not inverted" textline " " hexmask.long.byte 0x00 0.--7. 1. " DAT_INV_PAR ,Data Odd Parity" tree.end width 10. tree "Flash Voltage Registers" group.long 0x80++0x3 line.long 0x0 "FVREADCT,Voltage Read Control Register" bitfld.long 0x00 0.--3. " VREADCT ,Control the Voltage Level for Read Mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x84++0x3 line.long 0x0 "FVHVCT1,High Voltage Control Register" hexmask.long.byte 0x00 24.--31. 1. " VHVCT_P ,Control the Voltage Level Program" hexmask.long.byte 0x00 16.--23. 1. " VHVCT_E ,Control the Voltage Level Erase" hexmask.long.byte 0x00 8.--15. 1. " VHVCT_C ,Control the Voltage Level Compact" textline " " hexmask.long.byte 0x00 0.--7. 1. " VHVCT_PV ,Control the Voltage Level Program Verify" group.long 0x88++0x3 line.long 0x0 "FVHVCT2,High Voltage Control Register" bitfld.long 0x00 8.--11. " WCT[3:0] ,WCT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " VHVCT_READ[7:0] ,Control the Voltage Level Read Operation" group.long 0x8C++0x3 line.long 0x0 "FVNVCT,Negativ Voltage Control Register" bitfld.long 0x00 0.--3. " VNVCT ,Control the Voltage Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x90++0x3 line.long 0x0 "FVPPCT,High Current Control Register" bitfld.long 0x00 12.--15. " VPPCT_P ,Control the Voltage Level Program Operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " VPPCT_E ,Control the Voltage Level Erase Operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " VPPCT_C ,Control the Voltage Level Compaction Operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x94++0x3 line.long 0x0 "FVWLCT,Wordline Voltage Control Register" bitfld.long 0x00 12.--15. " VWLCT_E ,Control the Voltage Level Erase Operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " VWLCT_C ,Control the Voltage Level Compaction Operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " VWLCT_EV ,Control the Voltage Level Erase Verify" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x98++0x3 line.long 0x0 "FEFUSE,Test Register" bitfld.long 0x00 4.--7. " EFUSE_SOFT_EN ,Efuse Soft Test Enable" "Port 0,Port 0,Port 0,Port 0,Port 0,Port 0,Port 0,Port 0,Port 0,Port 0,Port 1,Port 0,Port 0,Port 0,Port 0,Port 0" bitfld.long 0x00 0.--3. " EFUSE_EN ,Efuse Test Enable" "Port 0,Port 0,Port 0,Port 0,Port 0,Port 0,Port 0,Port 0,Port 0,Port 0,Port 1,Port 0,Port 0,Port 0,Port 0,Port 0" tree.end width 11. tree "Flash Command Registers" group.long 0x100++0x3 line.long 0x0 "FBSTROBES,Bank Signal Strobe Register" bitfld.long 0x00 16. " FCLKEN ,Flash Clock Enable" "Disabled,Enabled" bitfld.long 0x00 8. " CTRLENZ ,Control Enable" "Enabled,Disabled" bitfld.long 0x00 6. " NOCOLRED ,Disables Addressing of Redundant Stick" "No effect,Disabled" textline " " bitfld.long 0x00 5. " PRECOL ,Enables Addressing of Redundant Stick" "No effect,Enabled" bitfld.long 0x00 4. " ENGR ,TI Engineering Sector" "Not active,Active" bitfld.long 0x00 3. " OTP ,Customer OTP Sector" "Not active,Active" textline " " bitfld.long 0x00 2. " TEZ ,Test Enable" "Enable,Disable" group.long 0x104++0x3 line.long 0x0 "FPSTROBES,Pump Signal Strobe Register" bitfld.long 0x00 8. " EXECUTEZ ,Gate Pump Outputs During Program/Erase/Compaction/etc" "Active,Not active" bitfld.long 0x00 1. " 3VPWRDNZ ,3V Pump Module to Power-down Mode" "Active,Not active" bitfld.long 0x00 0. " 5VPWRDNZ ,5V Pump Module to Power-down Mode" "Active,Not active" width 11. group.long 0x108++0x3 line.long 0x0 "FBMODE,Bank Mode Register" bitfld.long 0x00 2. " MODE[2] ,Mode 2" "Low,High" bitfld.long 0x00 1. " MODE[1] ,Mode 1" "Low,High" bitfld.long 0x00 0. " MODE[0] ,Mode 0" "Low,High" group.long 0x10C++0x3 line.long 0x0 "FTCR,TCR Register" bitfld.long 0x00 6. " TCR[6] ,TCR bit 6" "Low,High" bitfld.long 0x00 5. " TCR[5] ,TCR bit 5" "Low,High" bitfld.long 0x00 4. " TCR[4] ,TCR bit 4" "Low,High" bitfld.long 0x00 3. " TCR[3] ,TCR bit 3" "Low,High" textline " " bitfld.long 0x00 2. " TCR[2] ,TCR bit 2" "Low,High" bitfld.long 0x00 1. " TCR[1] ,TCR bit 1" "Low,High" bitfld.long 0x00 0. " TCR[0] ,TCR bit 0" "Low,High" width 11. group.long 0x110++0x3 line.long 0x0 "FADDR,Bank Addr Register" hexmask.long.tbyte 0x00 0.--19. 1. " ADDR ,Address Selected Bank" group.long 0x114++0x3 line.long 0x0 "FWRITE,Bank Write Data Register" group.long 0x118++0x3 line.long 0x0 "FCBIT_SEL,Check Bit Select Register" bitfld.long 0x00 0. " CBIT_SEL ,Check Bit Select" "Low,High" group.long 0x11C++0x3 line.long 0x0 "FTCTRL,Test Control Register" bitfld.long 0x00 8. " WPEN ,Wide Programming Enable" "Disabled,Enabled" bitfld.long 0x00 1. " TESTEN ,Test Enable" "Disabled,Enabled" group.long 0x120++0x3 line.long 0x0 "FWPWRITE0,Flash Wide Programming Write Data Register 0" hexmask.long 0x00 0.--31. 1. " WPDATA[31:0] ,Wide Programming Data[31:0]" group.long 0x124++0x3 line.long 0x0 "FWPWRITE1,Flash Wide Programming Write Data Register 1" hexmask.long 0x00 0.--31. 1. " WPDATA[63:32] ,Wide Programming Data[63:32]" group.long 0x128++0x3 line.long 0x0 "FWPWRITE2,Flash Wide Programming Write Data Register 2" hexmask.long 0x00 0.--31. 1. " WPDATA[95:64] ,Wide Programming Data[95:64]" group.long 0x12C++0x3 line.long 0x0 "FWPWRITE3,Flash Wide Programming Write Data Register 3" hexmask.long 0x00 0.--31. 1. " WPDATA[127:96] ,Wide Programming Data[127:96]" group.long 0x130++0x3 line.long 0x0 "FWPWRITE4,Flash Wide Programming Write Data Register 4" hexmask.long.word 0x00 0.--15. 1. " WPDATA[143:128] ,Wide Programming Data[143:128]" tree.end tree "FSM Registers" width 17. rgroup.long 0x204++0xb line.long 0x0 "FSM_STATE,FSM State Status" bitfld.long 0x00 11. " CTRLENZ ,CTRLENZ Signal Value" "Not generated,Generated" bitfld.long 0x00 10. " EXECUTEZ ,EXEcutez Signal Value" "Not generated,Generated" textline " " bitfld.long 0x00 8. " FSM_ACT ,Flash State Machine is Now Active" "Not active,Active" bitfld.long 0x00 7. " ENGR_ACT ,Engineering Array Signal is Active" "Not active,Active" textline " " bitfld.long 0x00 6. " OPT_ACT ,One Time Programmable Array Signal is Active" "Not active,Active" line.long 0x4 "FSM_STATUS,FSM Status" bitfld.long 0x04 3. " COD_FAIL_PCV ,COD Mode Failed Pre-Compact Verify" "Not failed,Failed" bitfld.long 0x04 2. " NON_OP ,Not Currently Doing an Operation Where EXECUTEZ is Low" "Low,High" textline " " bitfld.long 0x04 1. " OVR_PUL_CNT ,Over Pulse Count" "Not exceeded,Exceeded" bitfld.long 0x04 0. " INV_DAT ,Invalid Data is Detected" "Not detected,Detected" width 17. line.long 0x8 "FSM_COMMAND,FSM Command" hexmask.long.byte 0x08 0.--5. 1. " FSMCMD ,Flash State Machine Command" group.long 0x210++0x1f line.long 0x00 "FSM_P/E_OSU,FSM Program/Erase Operation Setup" hexmask.long.byte 0x00 8.--15. 1. " PGM_OSU ,Program Operation Setup Time" hexmask.long.byte 0x00 0.--7. 1. " ERA_OSU ,Erase Operation Setup Time" line.long 0x04 "FSM_C_OSU,FSM Compact Operation Setup" bitfld.long 0x04 12.--15. " VSTAT_CNT ,Voltage Status Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 0.--11. 1. " CMP_OSU ,Compact Operation Setup Time" line.long 0x08 "FSM_P/E_VSU,FSM Program/Erase Verify Setup" hexmask.long.byte 0x08 8.--15. 1. " PGM_VSU ,Program Verify Setup Time" hexmask.long.byte 0x08 0.--7. 1. " ERA_VSU ,Erase Verify Setup Time" line.long 0x0c "FSM_CMP_VSU,FSM Compare Verify Setup" bitfld.long 0x0c 12.--15. " ADD_EXZ ,Address to EXECUTEZ Low Setup Time" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles" hexmask.long.byte 0x0c 0.--7. 1. " CMP_VSU ,Compact Verify Setup Time" line.long 0x10 "FSM_EX_VAL,FSM EXECUTEZ to Valid Data" hexmask.long.byte 0x10 0.--7. 1. " EXE_VALD ,EXECUTEZ Low to Valid Data" line.long 0x14 "FSM_RD_H,FSM Read Mode Hold" hexmask.long.byte 0x14 0.--7. 1. " RD_H ,Read Mode Hold" line.long 0x18 "FSM_P/C_OH,FSM Program/Compact Operation Hold" hexmask.long.byte 0x18 8.--15. 1. " PGM_OH ,EXECUTEZ High to Mode Change" hexmask.long.byte 0x18 0.--7. 1. " CMP_OH ,EXECUTEZ High to Mode Change" line.long 0x1c "FSM_ERA_OH,FSM Erase Operation Hold" hexmask.long.word 0x1c 0.--15. 1. " ERA_OH ,EXECUTEZ High to Mode Chang" rgroup.long 0x230++0x3 line.long 0x00 "FSM_SAV_PPUL,FSM Saved Program Pulses" hexmask.long.word 0x00 0.--11. 1. " SAV_P_PUL ,Saved Program Pulses" group.long 0x234++0x1b line.long 0x00 "FSM_P/E_VH,FSM Program/Erase Verify Hold" hexmask.long.byte 0x00 8.--15. 1. " PGM_VH ,Program Verify Hold" hexmask.long.byte 0x00 0.--7. 1. " ERA_VH ,Erase Verify Hold" line.long 0x04 "FSM_VWL_STEP,FSM Word Line Voltage Stepping Control" bitfld.long 0x04 20.--23. " VWL_CUR_REP ,Current Value of the VWL_REP Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " VWL_CUR ,Current Level of the Wordline Voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 12.--15. " VWL_CUR_SAV ,Current Wordline Voltage Level Saves While Operation Suspended" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x04 8.--11. " VWL_REP ,Wordline Voltage Repeat Time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " VWL_END ,Wordline Voltage Ending Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " VWL_BEG ,Wordline Voltage Beginning Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "FSM_SWITCH_PNT,FSM Switch Point" hexmask.long.word 0x08 0.--11. 1. " SWITCH_PNT ,Switch Point" line.long 0x0c "FSM_PRG_PW,FSM Program Pulse Width" hexmask.long.word 0x0c 0.--15. 1. " PROG_PUL_WIDTH ,Program Pulse Width" line.long 0x10 "FSM_ERA_PW,FSM Erase Pulse Width" line.long 0x14 "FSM_CMP_PW,FSM Compact Pulse Width" hexmask.long.word 0x14 0.--15. 1. " CMP_PUL_WIDTH ,Compact Pulse Width" line.long 0x18 "FSM_CMP_SEC_SU,FSM Compact Sector Set Up Time" hexmask.long.byte 0x18 0.--7. 1. " CMP_SEC_SU ,Compact Sector Setup Time" rgroup.long 0x250++0x17 line.long 0x00 "FSM_SAV_COD,FSM COD General Storage" bitfld.long 0x00 16. " COD_FAIL_PCV ,COD Mode Failed Pre-Compact Verify" "Not failed,Failed" bitfld.long 0x00 15. " SAV_DID_CV ,Temporary storage of DID_CV Bit During Other COD Operations" "Low,High" bitfld.long 0x00 14. " DID_CV ,Did Compact_verify Sequence" "Low,High" textline " " bitfld.long 0x00 13. " SAV_COD_MODE ,Temporary Storage of COD_MODE During Other COD Operations" "Low,High" bitfld.long 0x00 12. " COD_MODE ,Did Compact_verify Sequence" "Low,High" hexmask.long.word 0x00 0.--11. 1. " SAVE_CMP_PUL ,Save the Compact Pulses" line.long 0x04 "FSM_SAV_ERA_PUL,FSM Saved Erased Pulses" hexmask.long.word 0x04 0.--11. 1. " SAV_ERA_PUL ,Saved Erase Pulses" line.long 0x08 "FSM_TIMER,FSM Timer" width 17. line.long 0x0c "FSM_MODE,FSM MODE Register" bitfld.long 0x0C 16.--17. " PGM_SUBMODE ,Submode Saved During Program Suspend" "Normal,Redundant Column,OTP,Engineering Array" bitfld.long 0x0C 14.--15. " ERA_SUBMODE ,Submode Saved During Erase Suspend" "Normal,Redundant Column,OTP,Engineering Array" textline " " bitfld.long 0x0C 12.--13. " SUBMODE ,Submode Saved During Program Suspend" "Normal,Redundant Column,OTP,Engineering Array" bitfld.long 0x0C 9.--11. " SAV_PGM_MODE ,Mode Saved During Program Suspend" "Read,Program Verify,Program,Erase Verify,Erase,Compact Verify,Compact,?..." textline " " bitfld.long 0x0C 6.--8. " SAV_ERA_MODE ,Mode Saved During Erase Suspend" "Read,Program Verify,Program,Erase Verify,Erase,Compact Verify,Compact,?..." bitfld.long 0x0C 3.--5. " MODE ,Current Flash Mode Operation" "Read,Program Verify,Program,Erase Verify,Erase,Compact Verify,Compact,?..." textline " " bitfld.long 0x0C 0.--2. " CMD ,Current Flash Command Operation" "Program,Erase Sector,Program Sector,Erase Test,Erase Bank,Precondition Verify,Erase Verify,Compaction Verify" width 17. line.long 0x10 "FSM_PGM,FSM Program Bits Register" bitfld.long 0x10 28.--31. " SAV_SEC ,Save Sectors" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 26. " PGM_ECC ,Saved ECC Bit During Program Suspend" "Not saved,Saved" textline " " bitfld.long 0x10 23.--25. " PGM_BANK ,Saved Bank During Program Suspend" "0,1,2,3,4,5,6,7" hexmask.long.tbyte 0x10 0.--22. 1. " PGM_ADDR ,Saved Address During Program Suspend" line.long 0x14 "FSM_ERA,FSM Erase Bits Register" bitfld.long 0x14 26. " ERA_ECC ,Saved ECC Bit During Erase Suspend" "Not saved,Saved" bitfld.long 0x14 23.--25. " EA_BANK ,Saved Bank during Erase Suspend" "Bank 0,Bank 1,Bank 2,Bank 3,Bank 4,Bank 5,Bank 6,Bank 7" textline " " hexmask.long.tbyte 0x14 0.--22. 1. " ERA_ADDR ,Saved Address During Erase Suspend" width 17. group.long 0x268++0xb line.long 0x00 "FSM_ERA_PUL,FSM Maximum Erase Pulses" bitfld.long 0x00 12.--15. " BEG_EC_LEVEL ,Beginning Level for VNVCT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " MAX_PRG_PUL ,Maximum Programming Pulses" line.long 0x04 "FSM_ERA_PUL,FSM Maximum Erase Pulses" bitfld.long 0x04 12.--15. " MAX_EC_LEVEL ,Maximum VNVCT Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 0.--11. 1. " MAX_ERA_PUL ,Maximum Erase Pulses" line.long 0x08 "FSM_CMP_PUL,FSM Maximum Compact Pulses" bitfld.long 0x08 12.--15. " EC_STEP_SIZE ,VNVCT Step Size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" hexmask.long.word 0x08 0.--11. 1. " MAX_CMP_PUL ,Maximum Compact Pulses" rgroup.long 0x274++0x7 line.long 0x00 "FSM_PUL_CNTR,FSM Pulse Counter" bitfld.long 0x00 12.--15. " CUR_EC_LEVEL ,Current VNVCT Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " PUL_CNTR ,Pulse Counter" line.long 0x04 "FSM_SAV_PGM_DAT,FSM Saved Program Data" width 17. group.long 0x27c++0x7 line.long 0x00 "FSM_ST_MACHINE,FSM State Machine" bitfld.long 0x00 15. " PGM_WIDTH ,Programming Width" "16 bits,32 bits" bitfld.long 0x00 14. " ONE_TIME_GOOD ,One Time Good Function" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " RESTRT_ADDR ,Restart Address" "No reset,Reset" bitfld.long 0x00 12. " PRE_CMP_FAIL_STOP ,Pre-compact Fail Stop" "Not stopped,Stopped" textline " " bitfld.long 0x00 11. " DO_REDU_COL ,Do Redundant Columns" "Not active,Active" textline " " bitfld.long 0x00 7.--10. " DBG_SHORT_ROW ,Debugging Short Rows" "Full range,Full range,Full range,Full range,Full range,Two rows/any sector,Full range,Full range,Full range,Full range,Reset,Full range,Full range,Full range,Full range,Full range" textline " " bitfld.long 0x00 6. " BNK_ERA_MODE ,Bank Erase Mode" "Not active,Active" bitfld.long 0x00 5. " PGM_SEC_COF_ENA ,Program Sector Continue on Failure Enable" "Failed,Continue" textline " " bitfld.long 0x00 4. " PREC_STOP_ENA ,Pre-condition Stop Enable" "Stopped,Not stopped" bitfld.long 0x00 3. " DIS_TST_ENA ,Disturbance Test Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " CMD_ENA ,Command Enable" "Disabled,Enabled" bitfld.long 0x00 1. " INV_DATA ,Invert Data" "Not inverted,Inverted" textline " " bitfld.long 0x00 0. " OVERRIDE ,Override" "Normal,Inverted" width 17. line.long 0x04 "FSM_CMD_TST,FSM Command Test" hexmask.long.word 0x04 0.--15. 1. " CMD_TST ,Command Test" if ((d.l(ad:0xFFF87000+0x27c)&0x8000)==0x0) rgroup.long 0x284++0x3 line.long 0x00 "FSM_RD_DATA,FSM Read Data" hexmask.long.word 0x00 0.--15. 1. " RD_DATA[15:0] ,Read Data" else rgroup.long 0x284++0x3 line.long 0x00 "FSM_RD_DATA,FSM Read Data" hexmask.long 0x00 0.--31. 1. " RD_DATA[31:0] ,Read Data" endif group.long 0x288++0x3 line.long 0x00 "FSM_WR_ENA,FSM Test Control" bitfld.long 0x00 0.--2. " WR_ENA ,FSM Write Enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled" rgroup.long 0x28c++0xb line.long 0x00 "FSM_ACC_PP,FSM Accumulate Program Pulses" line.long 0x04 "FSM_ACC_EP,FSM Accumulate Erase Pulses" hexmask.long.word 0x04 0.--15. 1. " ACC_EP ,Accumulate Erase Pulses" line.long 0x08 "FSM_ACC_CP,FSM Accumulate Compact Pulses" hexmask.long.tbyte 0x08 0.--23. 1. " ACC_CP ,Accumulate Compact Pulses" group.long 0x2a0++0xb line.long 0x00 "FSM_ADDR,FSM Address" bitfld.long 0x00 31. " ECC_NOW ,ECC Now Being Executed" "Low,High" bitfld.long 0x00 28.--30. " BANK ,Current Bank" "Bank 0,Bank 1,Bank 2,Bank 3,Bank 4,Bank 5,Bank 6,Bank 7" hexmask.long 0x00 0.--27. 1. " CUR_ADDR ,Current Address" line.long 0x04 "FSM_SECTOR,FSM Sector" hexmask.long.word 0x04 16.--31. 1. " SECT_ERASED ,Sectors Erased" bitfld.long 0x04 4.--7. " SECTOR ,Sector" "Sector 0,Sector 1,Sector 2,Sector 3,Sector 4,Sector 5,Sector 6,Sector 7,?..." bitfld.long 0x04 0.--3. " SEC_OUT ,Sector Output" "Sector 0,Sector 1,Sector 2,Sector 3,Sector 4,Sector 5,Sector 6,Sector 7,?..." line.long 0x08 "FWM_REV_ID,FWM Revision Identification" hexmask.long.word 0x08 16.--31. 1. " MOD_VERSION ,Module Version" hexmask.long.byte 0x08 13.--15. 0x2 " VERSION ,Version" bitfld.long 0x08 8.--12. " FWM_DAY ,Date of Configuration" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,?..." textline " " bitfld.long 0x08 4.--7. " FWM_MON ,Month of Configuration" "1,2,3,4,5,6,7,8,9,10,11,12,?..." hexmask.long.byte 0x08 0.--3. 1. " FWM_YEAR ,Year of Configuration" tree.end width 0xb tree.end tree "PBIST (Programmable Built-In Self-Test)" base ad:0xFFFFE400 width 8. group.long 0x100++0x3 line.long 0x0 "VAR0,Variable Address Register 0" group.long 0x104++0x3 line.long 0x0 "VAR1,Variable Address Register 1" group.long 0x108++0x3 line.long 0x0 "VAR2,Variable Address Register 2" group.long 0x10C++0x3 line.long 0x0 "VAR3,Variable Address Register 3" group.long 0x110++0x3 line.long 0x0 "VL0,Variable Loop Count Register 0" group.long 0x114++0x3 line.long 0x0 "VL1,Variable Loop Count Register 1" group.long 0x118++0x3 line.long 0x0 "VL0,Variable Loop Count Register 0" group.long 0x11C++0x3 line.long 0x0 "VL1,Variable Loop Count Register 1" group.long 0x120++0x3 line.long 0x0 "DD0,DD0 Data Register" group.long 0x124++0x3 line.long 0x0 "DE0,DE0 Data Register" group.long 0x130++0x3 line.long 0x0 "CAR0,Constant Address Register 0" group.long 0x134++0x3 line.long 0x0 "CAR1,Constant Address Register 1" group.long 0x138++0x3 line.long 0x0 "CAR2,Constant Address Register 2" group.long 0x13C++0x3 line.long 0x0 "CAR3,Constant Address Register 3" group.long 0x140++0x3 line.long 0x0 "CL0,Constant Loop Count Register 0" group.long 0x144++0x3 line.long 0x0 "CL1,Constant Loop Count Register 1" group.long 0x148++0x3 line.long 0x0 "CL2,Constant Loop Count Register 2" group.long 0x14C++0x3 line.long 0x0 "CL3,Constant Loop Count Register 3" group.long 0x150++0x3 line.long 0x0 "CIR0,Constant Increment Register 0" group.long 0x154++0x3 line.long 0x0 "CIR1,Constant Increment Register 1" group.long 0x158++0x3 line.long 0x0 "CIR2,Constant Increment Register 2" group.long 0x15C++0x3 line.long 0x0 "CIR3,Constant Increment Register 3" group.long 0x160++0x3 line.long 0x0 "RAMT,RAM Configuration" group.long 0x164++0x3 line.long 0x0 "DLR,Datalogger" group.long 0x168++0x3 line.long 0x0 "CMS,Clock Mux Select" group.long 0x16C++0x3 line.long 0x0 "STR,Program Control" group.long 0x178++0x3 line.long 0x0 "CSR,Chip Select" group.long 0x17C++0x3 line.long 0x0 "FDLY,Fail Delay" group.long 0x180++0x3 line.long 0x0 "PACT,PBIST Activate ROM Clock Enable" group.long 0x184++0x3 line.long 0x0 "IDR,PBIST ID" group.long 0x188++0x3 line.long 0x0 "OVER,PBIST Override" group.long 0x190++0x3 line.long 0x0 "FSRF0,Fail Status Fail - Port 0" group.long 0x194++0x3 line.long 0x0 "FSRF1,Fail Status Fail - Port 1" group.long 0x198++0x3 line.long 0x0 "FSRC0,Fail Status Count - Port 0" group.long 0x19C++0x3 line.long 0x0 "FSRC1,Fail Status Count - Port 1" group.long 0x1A0++0x3 line.long 0x0 "FSRA0,Fail Status Address - Port 0" group.long 0x1A4++0x3 line.long 0x0 "FSRA1,Fail Status Address - Port 1" group.long 0x1A8++0x3 line.long 0x0 "FSRDL0,Fail Status Data - Port 0" group.long 0x1B0++0x3 line.long 0x0 "FSRDL1,Fail Status Data - Port 1" group.long 0x1C0++0x3 line.long 0x0 "ROM,ROM Mask" group.long 0x1C4++0x3 line.long 0x0 "ALGO,ROM Algorithm Mask" group.long 0x1C8++0x3 line.long 0x0 "RINFOL,RAM Info Mask Lower" group.long 0x1CC++0x3 line.long 0x0 "RINFOU,RAM Info Mask Upper" width 0xb tree.end tree "RTP (RAM Trace Port)" sif COMP.AVAILABLE("RTP") base CONVert.ADDRESSTODUALPORT(COMPonent.BASE("RTP",-1)) width 14. group.long 0x00++0x07 line.long 0x00 "RTPGLBCTRL,RTP Global Control Register" sif (cpu()=="TMS570LC4357"||cpu()=="RM57L843-ZWT"||cpu()=="TMS570PSFC61"||cpuis("TMS570LS20216*")||cpu()=="TMS570LS31XX"||cpu()=="TMS570LS21XX"||cpu()=="TMS570LS10XX"||cpu()=="M48L"||cpu()=="TMS570PSFC66") bitfld.long 0x00 24. " TEST ,FIFO RAM test enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 16.--18. " PRESCALER ,Rtpclk=1/prescaler" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 12.--13. " DDM_WIDTH[1:0] ,Word size in DDM" "8 bit,16 bit,32 bit,?..." bitfld.long 0x00 11. " DDM_RW ,Direct data mode read/write" "Read,Write" bitfld.long 0x00 10. " TM_DDM ,Trace mode or direct data mode" "Trace mode,Direct data mode" textline " " bitfld.long 0x00 8.--9. " PW[1:0] ,Port width" "2 pins,4 pins,8 pins,16 pins" bitfld.long 0x00 7. " RESET ,Reset of RTP module" "No reset,Reset" bitfld.long 0x00 6. " CONTCLK ,Continuous RTPCLK enable" "Disabled,Enabled" bitfld.long 0x00 5. " HOVF ,Halt on overflow" "Disabled,Enabled" textline " " sif (cpu()=="TMS570LC4357"||cpu()=="RM57L843-ZWT"||cpu()=="TMS570PSFC66") bitfld.long 0x00 4. " INV_RGN ,Invers trace regions" "Inside,Outside" else bitfld.long 0x00 4. " INVERSE ,Invers trace regions" "Inside,Outside" endif bitfld.long 0x00 0.--3. " ON/OFF ,RTP on or off" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" line.long 0x04 "RTPTRENA,RTP Trace Enable Register" bitfld.long 0x04 24. " ENA4 ,FIFO4 enable" "Disabled,Enabled" sif (cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS20206-PGE")&&cpu()!=("TMS570LS20216-PGE")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS20206-ZWT")&&cpu()!=("TMS570LS20216-ZWT")&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE") bitfld.long 0x04 16. " ENA3 ,FIFO3 enable" "Disabled,Enabled" endif bitfld.long 0x04 8. " ENA2 ,FIFO2 enable" "Disabled,Enabled" bitfld.long 0x04 0. " ENA1 ,FIFO1 enable" "Disabled,Enabled" sif (cpu()=="TMS570LC4357"||cpu()=="RM57L843-ZWT") group.long 0x08++0x03 line.long 0x00 "RTPGSR,RTP Global Status Register" rbitfld.long 0x00 12. " EMPTYSER ,Serializer empty" "Not empty,Empty" rbitfld.long 0x00 11. " EMPTYPER2 ,Peripheral FIFO empty" "Not empty,Empty" rbitfld.long 0x00 10. " EMPTYPER1 ,Peripheral FIFO empty" "Not empty,Empty" rbitfld.long 0x00 9. " EMPTY2 ,FIFO2 empty" "Not empty,Empty" textline " " rbitfld.long 0x00 8. " EMPTY1 ,FIFO1 empty" "Not empty,Empty" eventfld.long 0x00 3. " OVFPER ,Overflow peripheral FIFO" "No overflow,Overflow" eventfld.long 0x00 1. " OVF2 ,Overflow FIFO2" "No overflow,Overflow" eventfld.long 0x00 0. " OVF1 ,Overflow FIFO1" "No overflow,Overflow" else rgroup.long 0x08++0x03 line.long 0x00 "RTPGSR,RTP Global Status Register" bitfld.long 0x00 12. " EMPTYSER ,Serializer empty" "Not empty,Empty" sif (cpu()=="TMS570PSFC66") sif (cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS20206-PGE")&&cpu()!=("TMS570LS20216-PGE")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS20206-ZWT")&&cpu()!=("TMS570LS20216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS20206-ZWT")&&cpu()!=("TMS570LS20216-ZWT")&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE") bitfld.long 0x00 10. " EMPTY3 ,FIFO 3 Empty" "Not empty,Empty" endif else bitfld.long 0x00 11. " EMPTYPER2 ,Peripheral FIFO empty" "Not empty,Empty" bitfld.long 0x00 10. " EMPTYPER1 ,Peripheral FIFO empty" "Not empty,Empty" endif bitfld.long 0x00 9. " EMPTY2 ,FIFO2 empty" "Not empty,Empty" bitfld.long 0x00 8. " EMPTY1 ,FIFO1 empty" "Not empty,Empty" textline " " bitfld.long 0x00 3. " OVFPER ,Overflow peripheral FIFO" "No overflow,Overflow" sif (cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS20206-PGE")&&cpu()!=("TMS570LS20216-PGE")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS20206-ZWT")&&cpu()!=("TMS570LS20216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS20206-ZWT")&&cpu()!=("TMS570LS20216-ZWT")&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE") bitfld.long 0x00 2. " OVFPE3 ,Overflow FIFO3" "No overflow,Overflow" endif bitfld.long 0x00 1. " OVFPE2 ,Overflow FIFO2" "No overflow,Overflow" bitfld.long 0x00 0. " OVFPE1 ,Overflow FIFO1" "No overflow,Overflow" endif group.long 0x0C++0x23 line.long 0x00 "RTPRAM1REG1,RTP RAM 1 Trace Region 1 Register" bitfld.long 0x00 29.--30. " CPU_DMA ,CPU and/or DMA access" "Any,CPU,DMA,?..." bitfld.long 0x00 28. " RW ,Read/write" "Read,Write" bitfld.long 0x00 24.--27. " BLOCKSIZE ,Blocksize" "0,256 B,512 B,1k B,2k B,4k B,8k B,16k B,32k B,64k B,128k B,256k B,?..." hexmask.long.tbyte 0x00 0.--17. 1. " STARTADDR ,Start address" line.long 0x04 "RTPRAM1REG2,RTP RAM 1 Trace Region 2 Register" bitfld.long 0x04 29.--30. " CPU_DMA ,CPU and/or DMA access" "Any,CPU,DMA,?..." bitfld.long 0x04 28. " RW ,Read/write" "Read,Write" bitfld.long 0x04 24.--27. " BLOCKSIZE ,Blocksize" "0,256 B,512 B,1k B,2k B,4k B,8k B,16k B,32k B,64k B,128k B,256k B,?..." hexmask.long.tbyte 0x04 0.--17. 1. " STARTADDR ,Start address" line.long 0x08 "RTPRAM2REG1,RTP RAM 2 Trace Region 1 Register" bitfld.long 0x08 29.--30. " CPU_DMA ,CPU and/or DMA access" "Any,CPU,DMA,?..." bitfld.long 0x08 28. " RW ,Read/write" "Read,Write" bitfld.long 0x08 24.--27. " BLOCKSIZE ,Blocksize" "0,256 B,512 B,1k B,2k B,4k B,8k B,16k B,32k B,64k B,128k B,256k B,?..." hexmask.long.tbyte 0x08 0.--17. 1. " STARTADDR ,Start address" line.long 0x0C "RTPRAM2REG2,RTP RAM 2 Trace Region 2 Register" bitfld.long 0x0C 29.--30. " CPU_DMA ,CPU and/or DMA access" "Any,CPU,DMA,?..." bitfld.long 0x0C 28. " RW ,Read/write" "Read,Write" bitfld.long 0x0C 24.--27. " BLOCKSIZE ,Blocksize" "0,256 B,512 B,1k B,2k B,4k B,8k B,16k B,32k B,64k B,128k B,256k B,?..." hexmask.long.tbyte 0x0C 0.--17. 1. " STARTADDR ,Start address" sif (cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS20206-PGE")&&cpu()!=("TMS570LS20216-PGE")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS20206-ZWT")&&cpu()!=("TMS570LS20216-ZWT")&&cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE") line.long 0x10 "RTPRAM3REG1,RTP RAM 3 Trace Region 1 Register" bitfld.long 0x10 29.--30. " CPU_DMA ,CPU and/or DMA access" "Any,CPU,DMA,?..." bitfld.long 0x10 28. " RW ,Read/write" "Read,Write" bitfld.long 0x10 24.--27. " BLOCKSIZE ,Blocksize" "0,256 B,512 B,1k B,2k B,4k B,8k B,16k B,32k B,64k B,128k B,256k B,?..." hexmask.long.tbyte 0x10 0.--17. 1. " STARTADDR ,Start address" line.long 0x14 "RTPRAM3REG2,RTP RAM 3 Trace Region 2 Register" bitfld.long 0x14 29.--30. " CPU_DMA ,CPU and/or DMA access" "Any,CPU,DMA,?..." bitfld.long 0x14 28. " RW ,Read/write" "Read,Write" bitfld.long 0x14 24.--27. " BLOCKSIZE ,Blocksize" "0,256 B,512 B,1k B,2k B,4k B,8k B,16k B,32k B,64k B,128k B,256k B,?..." hexmask.long.tbyte 0x14 0.--17. 1. " STARTADDR ,Start address" endif line.long 0x18 "RTPPERREG1,RTP Peripheral Trace Region 1 Register" bitfld.long 0x18 29.--30. " CPU_DMA ,CPU and/or DMA access" "Any,CPU,DMA,?..." bitfld.long 0x18 28. " RW ,Read/write" "Read,Write" sif (cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10206-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS20206-PGE")||cpu()==("TMS570LS20216-PGE")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS20206-ZWT")||cpu()==("TMS570LS20216-ZWT")||cpu()=="RM48L952-PGE"||cpu()=="RM48L952-ZWT"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L940-ZWT"||cpu()=="RM48L940-PGE"||cpu()=="RM48L930-ZWT"||cpu()=="RM48L930-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L740-ZWT"||cpu()=="RM48L740-PGE"||cpu()=="RM48L730-ZWT"||cpu()=="RM48L730-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L540-ZWT"||cpu()=="RM48L540-PGE"||cpu()=="RM48L530-ZWT"||cpu()=="RM48L530-PGE") bitfld.long 0x00 24.--27. " BLOCKSIZE ,Trace Region Length" "0 kB,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..." else bitfld.long 0x18 24.--27. " BLOCKSIZE ,Blocksize" "0,256 B,512 B,1k B,2k B,4k B,8k B,16k B,32k B,64k B,128k B,256k B,?..." endif hexmask.long.tbyte 0x18 0.--23. 1. " STARTADDR ,Start address" line.long 0x1C "RTPPERREG2,RTP Peripheral Trace Region 2 Register" bitfld.long 0x1C 29.--30. " CPU_DMA ,CPU and/or DMA access" "Any,CPU,DMA,?..." bitfld.long 0x1C 28. " RW ,Read/write" "Read,Write" sif (cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10206-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS20206-PGE")||cpu()==("TMS570LS20216-PGE")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS20206-ZWT")||cpu()==("TMS570LS20216-ZWT")||cpu()=="RM48L952-PGE"||cpu()=="RM48L952-ZWT"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L940-ZWT"||cpu()=="RM48L940-PGE"||cpu()=="RM48L930-ZWT"||cpu()=="RM48L930-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L740-ZWT"||cpu()=="RM48L740-PGE"||cpu()=="RM48L730-ZWT"||cpu()=="RM48L730-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L540-ZWT"||cpu()=="RM48L540-PGE"||cpu()=="RM48L530-ZWT"||cpu()=="RM48L530-PGE") bitfld.long 0x00 24.--27. " BLOCKSIZE ,Trace Region Length" "0 kB,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..." else bitfld.long 0x1C 24.--27. " BLOCKSIZE ,Blocksize" "0,256 B,512 B,1k B,2k B,4k B,8k B,16k B,32k B,64k B,128k B,256k B,?..." endif hexmask.long.tbyte 0x1C 0.--23. 1. " STARTADDR ,Start address" line.long 0x20 "RTPDDMW,RTP Direct Data Mode Write Register" group.long 0x34++0x07 line.long 0x00 "RTPPC0,RTP Pin Control 0" bitfld.long 0x00 18. " ENAFUNC ,Functional mode of RTPENA pin" "GIO mode,Functional mode" bitfld.long 0x00 17. " CLKFUNC ,Functional mode of RTPCLK pin" "GIO mode,Functional mode" bitfld.long 0x00 16. " SYNCFUNC ,Functional mode of RTPSYNC pin" "GIO mode,Functional mode" textline " " bitfld.long 0x00 15. " DATAFUNC ,Output state of RTPDATA pin 15" "GIO,Functional" bitfld.long 0x00 14. " DATAFUNC ,Output state of RTPDATA pin 14" "GIO,Functional" bitfld.long 0x00 13. " DATAFUNC ,Output state of RTPDATA pin 13" "GIO,Functional" textline " " bitfld.long 0x00 12. " DATAFUNC ,Output state of RTPDATA pin 12" "GIO,Functional" bitfld.long 0x00 11. " DATAFUNC ,Output state of RTPDATA pin 11" "GIO,Functional" bitfld.long 0x00 10. " DATAFUNC ,Output state of RTPDATA pin 10" "GIO,Functional" textline " " bitfld.long 0x00 9. " DATAFUNC ,Output state of RTPDATA pin 9" "GIO,Functional" bitfld.long 0x00 8. " DATAFUNC ,Output state of RTPDATA pin 8" "GIO,Functional" bitfld.long 0x00 7. " DATAFUNC ,Output state of RTPDATA pin 7" "GIO,Functional" textline " " bitfld.long 0x00 6. " DATAFUNC ,Output state of RTPDATA pin 6" "GIO,Functional" bitfld.long 0x00 5. " DATAFUNC ,Output state of RTPDATA pin 5" "GIO,Functional" bitfld.long 0x00 4. " DATAFUNC ,Output state of RTPDATA pin 4" "GIO,Functional" textline " " bitfld.long 0x00 3. " DATAFUNC ,Output state of RTPDATA pin 3" "GIO,Functional" bitfld.long 0x00 2. " DATAFUNC ,Output state of RTPDATA pin 2" "GIO,Functional" bitfld.long 0x00 1. " DATAFUNC ,Output state of RTPDATA pin 1" "GIO,Functional" textline " " bitfld.long 0x00 0. " DATAFUNC ,Output state of RTPDATA pin 0" "GIO,Functional" line.long 0x04 "RTPPC1,RTP Pin Control 1" bitfld.long 0x04 18. " ENADIR ,Direction of RTPENA pin" "Input,Output" bitfld.long 0x04 17. " CLKDIR ,Direction of RTPCLK pin" "Input,Output" bitfld.long 0x04 16. " SYNCDIR ,Direction of RTPSYNC pin" "Input,Output" textline " " bitfld.long 0x04 15. " DATADIR ,Output state of RTPDATA pin 15" "Input,Output" bitfld.long 0x04 14. " DATADIR ,Output state of RTPDATA pin 14" "Input,Output" bitfld.long 0x04 13. " DATADIR ,Output state of RTPDATA pin 13" "Input,Output" textline " " bitfld.long 0x04 12. " DATADIR ,Output state of RTPDATA pin 12" "Input,Output" bitfld.long 0x04 11. " DATADIR ,Output state of RTPDATA pin 11" "Input,Output" bitfld.long 0x04 10. " DATADIR ,Output state of RTPDATA pin 10" "Input,Output" textline " " bitfld.long 0x04 9. " DATADIR ,Output state of RTPDATA pin 9" "Input,Output" bitfld.long 0x04 8. " DATADIR ,Output state of RTPDATA pin 8" "Input,Output" bitfld.long 0x04 7. " DATADIR ,Output state of RTPDATA pin 7" "Input,Output" textline " " bitfld.long 0x04 6. " DATADIR ,Output state of RTPDATA pin 6" "Input,Output" bitfld.long 0x04 5. " DATADIR ,Output state of RTPDATA pin 5" "Input,Output" bitfld.long 0x04 4. " DATADIR ,Output state of RTPDATA pin 4" "Input,Output" textline " " bitfld.long 0x04 3. " DATADIR ,Output state of RTPDATA pin 3" "Input,Output" bitfld.long 0x04 2. " DATADIR ,Output state of RTPDATA pin 2" "Input,Output" bitfld.long 0x04 1. " DATADIR ,Output state of RTPDATA pin 1" "Input,Output" textline " " bitfld.long 0x04 0. " DATADIR ,Output state of RTPDATA pin 0" "Input,Output" rgroup.long 0x3C++0x03 line.long 0x00 "RTPPC2,RTP Pin Control 2" bitfld.long 0x00 18. " ENAIN ,State of RTPENA pin" "Low,High" bitfld.long 0x00 17. " CLKIN ,State of RTPCLK pin" "Low,High" bitfld.long 0x00 16. " SYNCIN ,State of RTPSYNC pin" "Low,High" textline " " bitfld.long 0x00 15. " DATAIN ,Output state of RTPDATA pin 15" "Low,High" bitfld.long 0x00 14. " DATAIN ,Output state of RTPDATA pin 14" "Low,High" bitfld.long 0x00 13. " DATAIN ,Output state of RTPDATA pin 13" "Low,High" textline " " bitfld.long 0x00 12. " DATAIN ,Output state of RTPDATA pin 12" "Low,High" bitfld.long 0x00 11. " DATAIN ,Output state of RTPDATA pin 11" "Low,High" bitfld.long 0x00 10. " DATAIN ,Output state of RTPDATA pin 10" "Low,High" textline " " bitfld.long 0x00 9. " DATAIN ,Output state of RTPDATA pin 9" "Low,High" bitfld.long 0x00 8. " DATAIN ,Output state of RTPDATA pin 8" "Low,High" bitfld.long 0x00 7. " DATAIN ,Output state of RTPDATA pin 7" "Low,High" textline " " bitfld.long 0x00 6. " DATAIN ,Output state of RTPDATA pin 6" "Low,High" bitfld.long 0x00 5. " DATAIN ,Output state of RTPDATA pin 5" "Low,High" bitfld.long 0x00 4. " DATAIN ,Output state of RTPDATA pin 4" "Low,High" textline " " bitfld.long 0x00 3. " DATAIN ,Output state of RTPDATA pin 3" "Low,High" bitfld.long 0x00 2. " DATAIN ,Output state of RTPDATA pin 2" "Low,High" bitfld.long 0x00 1. " DATAIN ,Output state of RTPDATA pin 1" "Low,High" textline " " bitfld.long 0x00 0. " DATAIN ,Output state of RTPDATA pin 0" "Low,High" group.long 0x40++0x17 line.long 0x00 "RTPPC3,RTP Pin Control 3" bitfld.long 0x00 18. " ENAOUT ,Output state of RTPENA pin" "Low,High" bitfld.long 0x00 17. " CLKOUT ,Output state of RTPCLK pin" "Low,High" sif (cpu()=="TMS570LC4357"||cpu()=="RM57L843-ZWT"||cpu()=="TMS570PSFC66") bitfld.long 0x00 16. " SYNCOUT ,Output state of RTPSYNC pins" "Low,High" else bitfld.long 0x00 16. " DATAOUT ,Output state of RTPDATA pins" "Low,High" endif textline " " bitfld.long 0x00 15. " DATAOUT ,Output state of RTPDATA pin 15" "Push/pull,Open drain" bitfld.long 0x00 14. " DATAOUT ,Output state of RTPDATA pin 14" "Push/pull,Open drain" bitfld.long 0x00 13. " DATAOUT ,Output state of RTPDATA pin 13" "Push/pull,Open drain" textline " " bitfld.long 0x00 12. " DATAOUT ,Output state of RTPDATA pin 12" "Push/pull,Open drain" bitfld.long 0x00 11. " DATAOUT ,Output state of RTPDATA pin 11" "Push/pull,Open drain" bitfld.long 0x00 10. " DATAOUT ,Output state of RTPDATA pin 10" "Push/pull,Open drain" textline " " bitfld.long 0x00 9. " DATAOUT ,Output state of RTPDATA pin 9" "Push/pull,Open drain" bitfld.long 0x00 8. " DATAOUT ,Output state of RTPDATA pin 8" "Push/pull,Open drain" bitfld.long 0x00 7. " DATAOUT ,Output state of RTPDATA pin 7" "Push/pull,Open drain" textline " " bitfld.long 0x00 6. " DATAOUT ,Output state of RTPDATA pin 6" "Push/pull,Open drain" bitfld.long 0x00 5. " DATAOUT ,Output state of RTPDATA pin 5" "Push/pull,Open drain" bitfld.long 0x00 4. " DATAOUT ,Output state of RTPDATA pin 4" "Push/pull,Open drain" textline " " bitfld.long 0x00 3. " DATAOUT ,Output state of RTPDATA pin 3" "Push/pull,Open drain" bitfld.long 0x00 2. " DATAOUT ,Output state of RTPDATA pin 2" "Push/pull,Open drain" bitfld.long 0x00 1. " DATAOUT ,Output state of RTPDATA pin 1" "Push/pull,Open drain" textline " " bitfld.long 0x00 0. " DATAOUT ,Output state of RTPDATA pin 0" "Push/pull,Open drain" line.long 0x04 "RTPPC4,RTP Pin Control 4" bitfld.long 0x04 18. " ENASET ,Set output state of RTPENA pin to logic high" "No change,Set high" bitfld.long 0x04 17. " CLKSET ,Set output state of RTPCLK pin to logic high" "No change,Set high" bitfld.long 0x04 16. " SYNCSET ,Set output state of RTPSYNC pin to logic high" "No change,Set high" textline " " bitfld.long 0x04 15. " DATASET ,Output state of RTPDATA pin 15" "Low,High" bitfld.long 0x04 14. " DATASET ,Output state of RTPDATA pin 14" "Low,High" bitfld.long 0x04 13. " DATASET ,Output state of RTPDATA pin 13" "Low,High" textline " " bitfld.long 0x04 12. " DATASET ,Output state of RTPDATA pin 12" "Low,High" bitfld.long 0x04 11. " DATASET ,Output state of RTPDATA pin 11" "Low,High" bitfld.long 0x04 10. " DATASET ,Output state of RTPDATA pin 10" "Low,High" textline " " bitfld.long 0x04 9. " DATASET ,Output state of RTPDATA pin 9" "Low,High" bitfld.long 0x04 8. " DATASET ,Output state of RTPDATA pin 8" "Low,High" bitfld.long 0x04 7. " DATASET ,Output state of RTPDATA pin 7" "Low,High" textline " " bitfld.long 0x04 6. " DATASET ,Output state of RTPDATA pin 6" "Low,High" bitfld.long 0x04 5. " DATASET ,Output state of RTPDATA pin 5" "Low,High" bitfld.long 0x04 4. " DATASET ,Output state of RTPDATA pin 4" "Low,High" textline " " bitfld.long 0x04 3. " DATASET ,Output state of RTPDATA pin 3" "Low,High" bitfld.long 0x04 2. " DATASET ,Output state of RTPDATA pin 2" "Low,High" bitfld.long 0x04 1. " DATASET ,Output state of RTPDATA pin 1" "Low,High" textline " " bitfld.long 0x04 0. " DATASET ,Output state of RTPDATA pin 0" "Low,High" line.long 0x08 "RTPPC5,RTP Pin Control 5" bitfld.long 0x08 18. " ENACLR ,Set output state of RTPENA pin to logic low" "No change,Set low" bitfld.long 0x08 17. " CLKCLR ,Set output state of RTPCLK pin to logic low" "No change,Set low" bitfld.long 0x08 16. " SYNCCLR ,Set output state of RTPSYNC pin to logic low" "No change,Set low" textline " " bitfld.long 0x08 15. " DATACLR ,Output state of RTPDATA pin 15" "Low,High" bitfld.long 0x08 14. " DATACLR ,Output state of RTPDATA pin 14" "Low,High" bitfld.long 0x08 13. " DATACLR ,Output state of RTPDATA pin 13" "Low,High" textline " " bitfld.long 0x08 12. " DATACLR ,Output state of RTPDATA pin 12" "Low,High" bitfld.long 0x08 11. " DATACLR ,Output state of RTPDATA pin 11" "Low,High" bitfld.long 0x08 10. " DATACLR ,Output state of RTPDATA pin 10" "Low,High" textline " " bitfld.long 0x08 9. " DATACLR ,Output state of RTPDATA pin 9" "Low,High" bitfld.long 0x08 8. " DATACLR ,Output state of RTPDATA pin 8" "Low,High" bitfld.long 0x08 7. " DATACLR ,Output state of RTPDATA pin 7" "Low,High" textline " " bitfld.long 0x08 6. " DATACLR ,Output state of RTPDATA pin 6" "Low,High" bitfld.long 0x08 5. " DATACLR ,Output state of RTPDATA pin 5" "Low,High" bitfld.long 0x08 4. " DATACLR ,Output state of RTPDATA pin 4" "Low,High" textline " " bitfld.long 0x08 3. " DATACLR ,Output state of RTPDATA pin 3" "Low,High" bitfld.long 0x08 2. " DATACLR ,Output state of RTPDATA pin 2" "Low,High" bitfld.long 0x08 1. " DATACLR ,Output state of RTPDATA pin 1" "Low,High" textline " " bitfld.long 0x08 0. " DATACLR ,Output state of RTPDATA pin 0" "Low,High" line.long 0x0C "RTPPC6,RTP Pin Control 6" bitfld.long 0x0C 18. " ENAPDR ,Open drain enable of RTPENA pin" "Normal mode,Open drain" bitfld.long 0x0C 17. " CLKPDR ,Open drain enable of RTPCLK pin" "Normal mode,Open drain" bitfld.long 0x0C 16. " SYNCPDR ,Open drain enable of RTPSYNC pin" "Normal mode,Open drain" textline " " bitfld.long 0x0C 15. " DATAPDR ,Output state of RTPDATA pin 15" "Push/pull,Open drain" bitfld.long 0x0C 14. " DATAPDR ,Output state of RTPDATA pin 14" "Push/pull,Open drain" bitfld.long 0x0C 13. " DATAPDR ,Output state of RTPDATA pin 13" "Push/pull,Open drain" textline " " bitfld.long 0x0C 12. " DATAPDR ,Output state of RTPDATA pin 12" "Push/pull,Open drain" bitfld.long 0x0C 11. " DATAPDR ,Output state of RTPDATA pin 11" "Push/pull,Open drain" bitfld.long 0x0C 10. " DATAPDR ,Output state of RTPDATA pin 10" "Push/pull,Open drain" textline " " bitfld.long 0x0C 9. " DATAPDR ,Output state of RTPDATA pin 9" "Push/pull,Open drain" bitfld.long 0x0C 8. " DATAPDR ,Output state of RTPDATA pin 8" "Push/pull,Open drain" bitfld.long 0x0C 7. " DATAPDR ,Output state of RTPDATA pin 7" "Push/pull,Open drain" textline " " bitfld.long 0x0C 6. " DATAPDR ,Output state of RTPDATA pin 6" "Push/pull,Open drain" bitfld.long 0x0C 5. " DATAPDR ,Output state of RTPDATA pin 5" "Push/pull,Open drain" bitfld.long 0x0C 4. " DATAPDR ,Output state of RTPDATA pin 4" "Push/pull,Open drain" textline " " bitfld.long 0x0C 3. " DATAPDR ,Output state of RTPDATA pin 3" "Push/pull,Open drain" bitfld.long 0x0C 2. " DATAPDR ,Output state of RTPDATA pin 2" "Push/pull,Open drain" bitfld.long 0x0C 1. " DATAPDR ,Output state of RTPDATA pin 1" "Push/pull,Open drain" textline " " bitfld.long 0x0C 0. " DATAPDR ,Output state of RTPDATA pin 0" "Push/pull,Open drain" line.long 0x10 "RTPPC7,RTP Pin Control 7" sif (cpu()=="TMS570LC4357"||cpu()=="RM57L843-ZWT") bitfld.long 0x10 18. " ENADIS ,Pull-up/pull-down functionality of RTPENA pin disabled" "No,Yes" bitfld.long 0x10 17. " CLKDIS ,Pull-up/pull-down functionality of RTPCLK pin disabled" "No,Yes" bitfld.long 0x10 16. " SYNCDIS ,Pull-up/pull-down functionality of RTPSYNC pin disabled" "No,Yes" else bitfld.long 0x10 18. " ENAPDIS ,Pull-up/pull-down functionality of RTPENA pin disabled" "No,Yes" bitfld.long 0x10 17. " CLKPDIS ,Pull-up/pull-down functionality of RTPCLK pin disabled" "No,Yes" bitfld.long 0x10 16. " SYNCPDIS ,Pull-up/pull-down functionality of RTPSYNC pin disabled" "No,Yes" endif textline " " bitfld.long 0x10 15. " DATADIS ,Output state of RTPDATA pin 15" "Enabled,Disabled" bitfld.long 0x10 14. " DATADIS ,Output state of RTPDATA pin 14" "Enabled,Disabled" bitfld.long 0x10 13. " DATADIS ,Output state of RTPDATA pin 13" "Enabled,Disabled" textline " " bitfld.long 0x10 12. " DATADIS ,Output state of RTPDATA pin 12" "Enabled,Disabled" bitfld.long 0x10 11. " DATADIS ,Output state of RTPDATA pin 11" "Enabled,Disabled" bitfld.long 0x10 10. " DATADIS ,Output state of RTPDATA pin 10" "Enabled,Disabled" textline " " bitfld.long 0x10 9. " DATADIS ,Output state of RTPDATA pin 9" "Enabled,Disabled" bitfld.long 0x10 8. " DATADIS ,Output state of RTPDATA pin 8" "Enabled,Disabled" bitfld.long 0x10 7. " DATADIS ,Output state of RTPDATA pin 7" "Enabled,Disabled" textline " " bitfld.long 0x10 6. " DATADIS ,Output state of RTPDATA pin 6" "Enabled,Disabled" bitfld.long 0x10 5. " DATADIS ,Output state of RTPDATA pin 5" "Enabled,Disabled" bitfld.long 0x10 4. " DATADIS ,Output state of RTPDATA pin 4" "Enabled,Disabled" textline " " bitfld.long 0x10 3. " DATADIS ,Output state of RTPDATA pin 3" "Enabled,Disabled" bitfld.long 0x10 2. " DATADIS ,Output state of RTPDATA pin 2" "Enabled,Disabled" bitfld.long 0x10 1. " DATADIS ,Output state of RTPDATA pin 1" "Enabled,Disabled" textline " " bitfld.long 0x10 0. " DATADIS ,Output state of RTPDATA pin 0" "Enabled,Disabled" line.long 0x14 "RTPPC8,RTP Pin Control 8" bitfld.long 0x14 18. " ENAPSEL ,Pull select of RTPENA pin" "Pull-down,Pull-up" bitfld.long 0x14 17. " CLKPSEL ,Pull select of RTPCLK pin" "Pull-down,Pull-up" bitfld.long 0x14 16. " SYNCPSEL ,Pull select of RTPSYNC pin" "Pull-down,Pull-up" textline " " bitfld.long 0x14 15. " DATAPSEL ,Output state of RTPDATA pin 15" "Pull-down,Pull-up" bitfld.long 0x14 14. " DATAPSEL ,Output state of RTPDATA pin 14" "Pull-down,Pull-up" bitfld.long 0x14 13. " DATAPSEL ,Output state of RTPDATA pin 13" "Pull-down,Pull-up" textline " " bitfld.long 0x14 12. " DATAPSEL ,Output state of RTPDATA pin 12" "Pull-down,Pull-up" bitfld.long 0x14 11. " DATAPSEL ,Output state of RTPDATA pin 11" "Pull-down,Pull-up" bitfld.long 0x14 10. " DATAPSEL ,Output state of RTPDATA pin 10" "Pull-down,Pull-up" textline " " bitfld.long 0x14 9. " DATAPSEL ,Output state of RTPDATA pin 9" "Pull-down,Pull-up" bitfld.long 0x14 8. " DATAPSEL ,Output state of RTPDATA pin 8" "Pull-down,Pull-up" bitfld.long 0x14 7. " DATAPSEL ,Output state of RTPDATA pin 7" "Pull-down,Pull-up" textline " " bitfld.long 0x14 6. " DATAPSEL ,Output state of RTPDATA pin 6" "Pull-down,Pull-up" bitfld.long 0x14 5. " DATAPSEL ,Output state of RTPDATA pin 5" "Pull-down,Pull-up" bitfld.long 0x14 4. " DATAPSEL ,Output state of RTPDATA pin 4" "Pull-down,Pull-up" textline " " bitfld.long 0x14 3. " DATAPSEL ,Output state of RTPDATA pin 3" "Pull-down,Pull-up" bitfld.long 0x14 2. " DATAPSEL ,Output state of RTPDATA pin 2" "Pull-down,Pull-up" bitfld.long 0x14 1. " DATAPSEL ,Output state of RTPDATA pin 1" "Pull-down,Pull-up" textline " " bitfld.long 0x14 0. " DATAPSEL ,Output state of RTPDATA pin 0" "Pull-down,Pull-up" sif (cpu()!="TMS570LC4357"&&cpu()!="RM57L843-ZWT") group.long 0x58++0x03 line.long 0x00 "RTPIODFTCTRL,RTP IODFT Control" hexmask.long.byte 0x00 8.--11. 1. " IODFTENA ,IO DFT enable" bitfld.long 0x00 1. " LBENA ,Loop back enable" "Analog,Digital" endif endif width 0x0B tree.end tree "RTI (Real Time Interrupt)" base ad:0xFFFFFC00 sif cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232") endian.be endif width 16. group.long 0x00++0x03 line.long 0x00 "GCTRL,Global Control Register" sif (cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS3137-EP")) bitfld.long 0x00 16.--19. " NTUSEL ,Select NTU signal" "NTU0,,,,,NTU1,,,,,NTU2,,,,,NTU3" bitfld.long 0x00 15. " COS ,Continue on suspend" "Stopped,Running" newline else sif (cpu()!="TMS470MF031")&&(cpu()!="TMS470MF042")&&(cpu()!="TMS470MF066"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432"))&&!cpuis("TMS570LS09*")&&!cpuis("TMS570LS07*")&&!cpuis("TMS570LS0232") bitfld.long 0x00 16.--17. " NTUSEL ,Select NTU signal" "NTU0,NTU1,?..." bitfld.long 0x00 15. " COS ,Continue on suspend" "Stopped,Running" newline else bitfld.long 0x00 15. " COS ,Continue on suspend" "Stopped,Running" newline endif endif bitfld.long 0x00 1. " CNT1EN ,Counter 1 enable" "Stopped,Started" bitfld.long 0x00 0. " CNT0EN ,Counter 0 enable" "Stopped,Started" sif (cpu()!="TMS470MF031")&&(cpu()!="TMS470MF042")&&(cpu()!="TMS470MF066"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432"))&&!cpuis("TMS570LS0232") group.long 0x04++0x03 line.long 0x00 "TBCTRL,Timebase Control Register" bitfld.long 0x00 1. " INC ,Increment free running counter" "Not incremented,Incremented" sif cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS3137-EP") newline bitfld.long 0x00 0. " TBEXT ,Time base external" "Clocks FRC0,Not clocks FRC0" else newline bitfld.long 0x00 0. " TBEXT ,Time base external" "UC0,NTU" endif endif group.long 0x08++0x07 line.long 0x00 "CAPCTRL,Capture Control Register" bitfld.long 0x00 1. " CAPCNTR1 ,Capture counter 1" "CES 0,CES 1" bitfld.long 0x00 0. " CAPCNTR0 ,Capture counter 0" "CES 0,CES 1" line.long 0x04 "COMPCTRL,Compare Control Register" bitfld.long 0x04 12. " COMPSEL3 ,Compare select 3" "FRC0,FRC1" bitfld.long 0x04 8. " COMPSEL2 ,Compare select 2" "FRC0,FRC1" bitfld.long 0x04 4. " COMPSEL1 ,Compare select 1" "FRC0,FRC1" newline bitfld.long 0x04 0. " COMPSEL0 ,Compare select 0" "FRC0,FRC1" sif cpuis("TMS570LS3137-EP") hgroup.long 0x10++0x03 hide.long 0x00 "FRC0,Free Running Counter 0 Register" in else group.long 0x10++0x03 line.long 0x00 "FRC0,Free Running Counter 0 Register" endif group.long 0x14++0x07 line.long 0x00 "UC0,Up Counter 0 Register" line.long 0x04 "CPUC0,Compare Up Counter 0 Register" rgroup.long 0x20++0x07 line.long 0x00 "CAFRC0,Capture Free Running Counter 0 Register" line.long 0x04 "CAUC0,Capture Up Counter 0 Register" sif cpuis("TMS570LS3137-EP") hgroup.long 0x30++0x03 hide.long 0x00 "FRC1,Free Running Counter 1 Register" in else group.long 0x30++0x03 line.long 0x00 "FRC1,Free Running Counter 1 Register" endif group.long 0x34++0x07 line.long 0x00 "UC1,Up Counter 1 Register" line.long 0x04 "CPUC1,Compare Up Counter 1 Register" rgroup.long 0x40++0x07 line.long 0x00 "CAFRC1,Capture Free Running Counter 1 Register" line.long 0x04 "CAUC1,Capture Up Counter 1 Register" group.long 0x50++0x1F line.long 0x00 "COMP0,Compare 0 Register" line.long 0x04 "UDCP0,Update Compare 0 Register" line.long 0x08 "COMP1,Compare 1 Register" line.long 0x0C "UDCP1,Update Compare 1 Register" line.long 0x10 "COMP2,Compare 2 Register" line.long 0x14 "UDCP2,Update Compare 2 Register" line.long 0x18 "COMP3,Compare 3 Register" line.long 0x1C "UDCP3,Update Compare 3 Register" sif (cpu()!="TMS470MF031")&&(cpu()!="TMS470MF042")&&(cpu()!="TMS470MF066"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432"))&&!cpuis("TMS570LS09*")&&!cpuis("TMS570LS07*")&&!cpuis("TMS570LS0232") group.long 0x70++0x07 line.long 0x00 "TBLCOMP,External Clock Timebase Low Compare Register" line.long 0x04 "TBHCOMP,External Clock Timebase High Compare Register" endif group.long 0x80++0x03 line.long 0x00 "SETINT_SET/CLR,Set/Clear Interrupt Register" setclrfld.long 0x00 18. 0x00 18. 0x04 18. " SETOVL1IN_SET/CLR ,Free running counter 1 overflow interrupt" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x04 17. " SETOVL0INT_SET/CLR ,Free running counter 0 overflow interrupt" "Disabled,Enabled" sif (cpu()!="TMS470MF031")&&(cpu()!="TMS470MF042")&&(cpu()!="TMS470MF066") newline setclrfld.long 0x00 16. 0x00 16. 0x04 16. " SETTBINT_SET/CLR ,Timebase interrupt" "Disabled,Enabled" sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432"))&&!cpuis("TMS570LS0232") newline setclrfld.long 0x00 11. 0x00 11. 0x04 11. " SETDMA3_SET/CLR ,Compare DMA request 3" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x04 10. " SETDMA2_SET/CLR ,Compare DMA request 2" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x04 9. " SETDMA1_SET/CLR ,Compare DMA request 1" "Disabled,Enabled" newline setclrfld.long 0x00 8. 0x00 8. 0x04 8. " SETDMA0_SET/CLR ,Compare DMA request 0" "Disabled,Enabled" endif newline setclrfld.long 0x00 3. 0x00 3. 0x04 3. " SETINT3_SET/CLR ,Compare interrupt 3" "Disabled,Enabled" else newline setclrfld.long 0x00 3. 0x00 3. 0x04 3. " SETINT3_SET/CLR ,Compare interrupt 3" "Disabled,Enabled" endif newline setclrfld.long 0x00 2. 0x00 2. 0x04 2. " SETINT2_SET/CLR ,Compare interrupt 2" "Disabled,Enabled" setclrfld.long 0x00 1. 0x00 1. 0x04 1. " SETINT1_SET/CLR ,Compare interrupt 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x04 0. " SETINT0_SET/CLR ,Compare interrupt 0" "Disabled,Enabled" group.long 0x88++0x03 line.long 0x00 "INTFLAG,Interrupt Flag Register" eventfld.long 0x00 18. " OVL1INT ,Free running counter 1 overflow interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 17. " OVL0INT ,Free running counter 0 overflow interrupt flag" "No interrupt,Interrupt" sif (cpu()!="TMS470MF031")&&(cpu()!="TMS470MF042")&&(cpu()!="TMS470MF066") newline eventfld.long 0x00 16. " TBINT ,Timebase interrupt flag" "No interrupt,Interrupt" endif newline eventfld.long 0x00 3. " INT3 ,Interrupt flag 3" "No interrupt,Interrupt" eventfld.long 0x00 2. " INT2 ,Interrupt flag 2" "No interrupt,Interrupt" eventfld.long 0x00 1. " INT1 ,Interrupt flag 1" "No interrupt,Interrupt" newline eventfld.long 0x00 0. " INT0 ,Interrupt flag 0" "No interrupt,Interrupt" sif (cpu()!="TMS570PSFC61") group.long 0x90++0x0F line.long 0x00 "DWDCTRL,Digital Watchdog Control Register" line.long 0x04 "DWDPRLD,Digital Watchdog Preload Register" hexmask.long.word 0x04 0.--11. 1. " DWDPRLD ,Digital watchdog preload value" line.long 0x08 "WDSTATUS,Watchdog Status Register" sif (cpu()==("TMS570LC4357")||cpu()==("TMS570LS2126")||cpu()==("TMS570LS2127")||cpu()==("TMS570LS2136")||cpu()==("TMS570LS2137")||cpu()==("TMS570LS2125-PGE")||cpu()==("TMS570LS2125-ZWT")||cpu()==("TMS570LS2135-PGE")||cpu()==("TMS570LS2135-ZWT")||cpu()==("TMS570LS2124-PGE")||cpu()==("TMS570LS2124-ZWT")||cpu()==("TMS570LS2134-PGE")||cpu()==("TMS570LS2134-ZWT")||cpu()==("TMS570LS3134-PGE")||cpu()==("TMS570LS3134-ZWT")||cpu()==("TMS570LS3135-PGE")||cpu()==("TMS570LS3135-ZWT")||cpu()==("TMS570LS3136")||cpu()==("TMS570LS3137-PGE")||cpu()==("TMS570LS3137-ZWT")||cpu()==("TMS570LS30336")||cpuis("RM48L950*")||cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS3137-EP")||cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232")) eventfld.long 0x08 5. " DWWD_ST ,Windowed watchdog status" "Not occurred,Occurred" eventfld.long 0x08 4. " END_TIME_VIOL ,Windowed watchdog end time violation status" "Not occurred,Occurred" eventfld.long 0x08 3. " START_TIME_VIOL ,Windowed watchdog start time violation status" "Not occurred,Occurred" newline eventfld.long 0x08 2. " KEYST ,Watchdog key status" "Not occurred,Occurred" eventfld.long 0x08 1. " DWDST ,Digital watchdog status" "Not occurred,Occurred" else eventfld.long 0x08 2. " KEYST ,Watchdog key status" "Not occurred,Occurred" eventfld.long 0x08 1. " DWDST ,Digital watchdog status" "Not occurred,Occurred" sif (cpu()!="TMS470MF031")&&(cpu()!="TMS470MF042")&&(cpu()!="TMS470MF066") eventfld.long 0x08 0. " AWDST ,Analog watchdog status" "Not occurred,Occurred" endif endif line.long 0x0C "WDKEY,Watchdog Key Register" hexmask.long.word 0x0C 0.--15. 1. " WDKEY ,Watchdog key" rgroup.long 0xA0++0x03 line.long 0x00 "WDCNTR,Digital Watchdog Down Counter" hexmask.long 0x00 0.--24. 1. " DWDCNTR ,Digital watchdog down counter" endif sif (cpu()==("TMS570LC4357")||cpu()==("TMS570LS2126")||cpu()==("TMS570LS2127")||cpu()==("TMS570LS2136")||cpu()==("TMS570LS2137")||cpu()==("TMS570LS2125-PGE")||cpu()==("TMS570LS2125-ZWT")||cpu()==("TMS570LS2135-PGE")||cpu()==("TMS570LS2135-ZWT")||cpu()==("TMS570LS2124-PGE")||cpu()==("TMS570LS2124-ZWT")||cpu()==("TMS570LS2134-PGE")||cpu()==("TMS570LS2134-ZWT")||cpu()==("TMS570LS3134-PGE")||cpu()==("TMS570LS3134-ZWT")||cpu()==("TMS570LS3135-PGE")||cpu()==("TMS570LS3135-ZWT")||cpu()==("TMS570LS3136")||cpu()==("TMS570LS3137-PGE")||cpu()==("TMS570LS3137-ZWT")||cpu()==("TMS570LS30336")||cpuis("RM48L950*")||cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS3137-EP")||cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232")) group.long 0xA4++0x07 line.long 0x00 "WWDRXNCTRL,Digital Windowed Watchdog Reaction Control" sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232")||cpuis("TMS570LS3137-EP")) bitfld.long 0x00 0.--3. " WWDRXN ,The DWWD reaction" "Reset,Reset,Reset,Reset,Reset,Reset,Reset,Reset,Reset,Reset,Interrupt,Reset,Reset,Reset,Reset,Reset" else bitfld.long 0x00 0.--3. " DWDST ,The DWWD reaction" "Reset,Reset,Reset,Reset,Reset,Reset,Reset,Reset,Reset,Reset,Interrupt,Reset,Reset,Reset,Reset,Reset" endif line.long 0x04 "WWDSIZECTRL,Digital Windowed Watchdog Window Size Control" endif sif cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232")||cpuis("TMS570LS3137-EP") group.long 0xAC++0x13 line.long 0x00 "INTCLRENABLE,Compare Interrupt Clear Enable Register" bitfld.long 0x00 24.--27. " INTCLRENABLE3 ,Auto-clear functionality on the compare 3 interrupt enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.long 0x00 16.--19. " INTCLRENABLE2 ,Auto-clear functionality on the compare 2 interrupt enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.long 0x00 8.--11. " INTCLRENABLE1 ,Auto-clear functionality on the compare 1 interrupt enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" newline bitfld.long 0x00 0.--3. " INTCLRENABLE0 ,Auto-clear functionality on the compare 0 interrupt enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" line.long 0x04 "CMP0CLR,Compare 0 Clear Register" line.long 0x08 "CMP1CLR,Compare 1 Clear Register" line.long 0x0C "CMP2CLR,Compare 2 Clear Register" line.long 0x10 "CMP3CLR,Compare 3 Clear Register" endif sif cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232") endian.le endif width 0x0B tree.end tree "STC (Self-Test Controller)" base ad:0xFFFFE600 width 15. group.long 0x00++0x3 line.long 0x0 "GCR0,Global Control Register 0" group.long 0x04++0x3 line.long 0x0 "GCR1,Global Control Register 1" group.long 0x08++0x3 line.long 0x0 "TPR,Run TimeOut Counter Preload Register" group.long 0x0C++0x3 line.long 0x0 "CADDR,Current ROM Address Register" group.long 0x10++0x3 line.long 0x0 "CICR,Current Interval Count Register" group.long 0x14++0x3 line.long 0x0 "GSTAT,SelfTest Global Status Register" group.long 0x18++0x3 line.long 0x0 "FSTAT,Fail Status Register" group.long 0x1C++0x3 line.long 0x0 "CPU1_CURMISR0,CPU1 Current MISR Register)" group.long 0x20++0x3 line.long 0x0 "CPU1_CURMISR1,CPU1 Current MISR Register)" group.long 0x24++0x3 line.long 0x0 "CPU1_CURMISR2,CPU1 Current MISR Register)" group.long 0x28++0x3 line.long 0x0 "CPU1_CURMISR3,CPU1 Current MISR Register)" group.long 0x2C++0x3 line.long 0x0 "CPU2_CURMISR0,CPU2 Current MISR Register)" group.long 0x30++0x3 line.long 0x0 "CPU2_CURMISR1,CPU2 Current MISR Register)" group.long 0x44++0x3 line.long 0x0 "CPU2_CURMISR2,CPU2 Current MISR Register)" group.long 0x48++0x3 line.long 0x0 "CPU2_CURMISR3,CPU2 Current MISR Register)" width 0xb tree.end tree "SYS (System Registers)" base ad:0xFFFFFF00 width 9. tree "System Pin Control Registers" group.long 0x00++0x3 line.long 0x0 "SYSPC1,SYS Pin Control Register 1" bitfld.long 0x00 0. " ECPCLK_FUN ,ECPCLK Function" "GIO,ECPCLK" group.long 0x04++0x3 line.long 0x0 "SYSPC2,SYS Pin Control Register 2" bitfld.long 0x00 0. " ECPCLK_DIR ,ECPCLK Data Direction" "Input,Output" rgroup.long 0x08++0x3 line.long 0x0 "SYSPC3,SYS Pin Control Register 3" bitfld.long 0x00 0. " ECPCLK_DIN ,ECPCLK Data In" "Low,High" if ((((d.l(ad:0xFFFFFF00))&0x01)==0x00)&&(((d.l((ad:0xFFFFFF00+0x04)))&0x01)==0x01)) group.long 0x0C++0x3 line.long 0x0 "SYSPC4,SYS Pin Control Register 4" bitfld.long 0x00 0. " ECPCLK_DOUT ,ECPCLK Data Out Write" "Low,High" else hgroup.long 0x0C++0x3 hide.long 0x0 "SYSPC4,SYS Pin Control Register 4" endif if (((data.long(ad:0xFFFFFF00))&0x01)==0x00) group.long 0x10++0x3 line.long 0x0 "SYSPC5,SYS Pin Control Register 5" bitfld.long 0x00 0. " ECPCLK_SET ,ECPCLK Data Out Set" "Low,High" group.long 0x14++0x3 line.long 0x0 "SYSPC6,SYS Pin Control Register 6" bitfld.long 0x00 0. " ECPCLK_CLR ,ECPCLK Data Out clear" "Low,High" group.long 0x18++0x3 line.long 0x0 "SYSPC7,SYS Pin Control Register 7" bitfld.long 0x00 0. " ECPCLK_ODE ,ECPCLK Open Drain Enable" "Push/pull,Open drain" else hgroup.long 0x10++0x3 hide.long 0x0 "SYSPC5,SYS Pin Control Register 5" hgroup.long 0x14++0x3 hide.long 0x0 "SYSPC6,SYS Pin Control Register 6" hgroup.long 0x18++0x3 hide.long 0x0 "SYSPC7,SYS Pin Control Register 7" endif if (((data.long((ad:0xFFFFFF00+0x04)))&0x01)==0x00) group.long 0x1C++0x3 line.long 0x0 "SYSPC8,SYS Pin Control Register 8" bitfld.long 0x00 0. " ECPCLK_PUE ,ECPCLK Pull Up Enable" "Active,Inactive" group.long 0x20++0x3 line.long 0x0 "SYSPC9,SYS Pin Control Register 9" bitfld.long 0x00 0. " ECPCLK_PS ,ECPCLK Pull Up/Pull Down Select" "Down,Up" else hgroup.long 0x1C++0x3 hide.long 0x0 "SYSPC8,SYS Pin Control Register 8" hgroup.long 0x20++0x3 hide.long 0x0 "SYSPC9,SYS Pin Control Register 9" endif group.long 0x78++0x3 line.long 0x0 "SYSPC10,SYS Pin Control Register 10" bitfld.long 0x00 0. " ECPCLK_SLEW ,ECPCLK Slew Control" "Fast,Slow" tree.end width 9. tree "System SSW PLL BIST Control Registers" group.long 0x24++0x3 line.long 0x0 "SSWPLL1,SSW PLL BIST Control Register 1" hexmask.long.byte 0x00 8.--15. 1. " MOD_PH_CAP_INDEX ,Modulation Phase Capture Index" bitfld.long 0x00 6. " COUNTER_READ_READY ,Counter Read Ready" "Not ready,Ready" textline " " bitfld.long 0x00 5. " COUNTER_RESET ,Counter Reset" "No reset,Reset" bitfld.long 0x00 4. " COUNTER_EN ,Counter Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1.--3. " TAP_COUNTER_DIS[3:1] ,TAP Counter Disable" "Bit 16,Bit 18,Bit 20,Bit 22,Bit 24,Bit 26,Bit 28,Bit 30" bitfld.long 0x00 0. " EXT_COUNTER_EN ,EXT Counter Enable" "PLLCLK,Oscillator input" rgroup.long 0x28++0x3 line.long 0x0 "SSWPLL2,SSW PLL BIST Control Register 2" rgroup.long 0x2C++0x3 line.long 0x0 "SSWPLL3,SSW PLL BIST Control Register 3" tree.end width 7. tree "System Clock Source/Domain Disable Registers" group.long 0x30++0x3 line.long 0x0 "CSDIS,Clock Source Disable Register" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " CLKSR6_OFF_set/clr ,Clock Source 6 (Secondary PLL/Clock Source 6) Off" "Enabled,Disabled" setclrfld.long 0x00 5. 0x04 5. 0x08 5. " CLKSR5_OFF_set/clr ,Clock Source 5 (LPO High Frequency Clock) Off" "Enabled,Disabled" textline " " setclrfld.long 0x00 4. 0x04 4. 0x08 4. " CLKSR4_OFF_set/clr ,Clock Source 4 (LPO Low Frequency Clock) Off" "Enabled,Disabled" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " CLKSR3_OFF_set/clr ,Clock Source 3 (External Clock) Off" "Enabled,Disabled" textline " " setclrfld.long 0x00 2. 0x04 2. 0x08 2. " CLKSR2_OFF_set/clr ,Clock Source 2 (32 kHz Oscillator) Off" "Enabled,Disabled" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " CLKSR1_OFF_set/clr ,Clock Source 1 (PLL) Off" "Enabled,Disabled" textline " " setclrfld.long 0x00 0. 0x04 0. 0x08 0. " CLKSR0_OFF_set/clr ,Clock Source 0 (Oscillator) Off" "Enabled,Disabled" group.long 0x3C++0x3 line.long 0x0 "CDDIS,Clock Domain Disable Register" setclrfld.long 0x00 7. 0x4 7. 0x8 7. " RTICLK2OFF_set/clr ,RTICLK2 Domain Off" "Enabled,Disabled" setclrfld.long 0x00 6. 0x4 6. 0x8 6. " RTICLK1OFF_set/clr ,RTICLK1 Domain Off" "Enabled,Disabled" textline " " setclrfld.long 0x00 5. 0x4 5. 0x8 5. " VCLKA2OFF_set/clr ,VCLKA2 Domain Off" "Enabled,Disabled" setclrfld.long 0x00 4. 0x4 4. 0x8 4. " VCLKA1OFF_set/clr ,VCLKA1 Domain Off" "Enabled,Disabled" textline " " setclrfld.long 0x00 3. 0x4 3. 0x8 3. " VCLK2OFF_set/clr ,VCLK2 Domain Off" "Enabled,Disabled" setclrfld.long 0x00 2. 0x4 2. 0x8 2. " VCLKPOFF_set/clr ,VCLKP Domain Off" "Enabled,Disabled" textline " " setclrfld.long 0x00 1. 0x4 1. 0x8 1. " HCLKOFF_set/clr ,HCLK Domain Off" "Enabled,Disabled" setclrfld.long 0x00 0. 0x4 0. 0x8 0. " GCLKOFF_set/clr ,GCLK Domain Off" "Enabled,Disabled" tree.end textline " " width 13. group.long 0x48++0x3 line.long 0x0 "GHVSRC,GCLK/HCLK/VCLK and VCLK2 Source Register" bitfld.long 0x00 24.--27. " GHVWAKE[3:0] ,GCLK/HCLK/VCLK/VCLK2 Source on Wakeup" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,?..." bitfld.long 0x00 16.--19. " HVLPM[3:0] ,HCLK/VCLK/VCLK2 Source on Wakeup (GCLK Turned Off)" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,?..." textline " " bitfld.long 0x00 0.--3. " GHVSRC[3:0] ,GCLK/HCLK/VCLK/VCLK2 Current Source" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,?..." group.long 0x4C++0x3 line.long 0x0 "VCLKASRC,Peripheral Asynchronous Clock Source Register" bitfld.long 0x00 8.--11. " VCLKA2S[3:0] ,Peripheral Asynchronous Clock 2 Source" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK" bitfld.long 0x00 0.--3. " VCLKA1S[3:0] ,Peripheral Asynchronous Clock 1 Source" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK" group.long 0x50++0x3 line.long 0x0 "RCLKSRC,RTI Clock Source Register" bitfld.long 0x00 24.--25. " RTI2DIV[1:0] ,RTI Clock 2 Divider" "RTICLK2,RTICLK2/2,RTICLK2/4,RTICLK2/8" bitfld.long 0x00 16.--19. " RTI2SRC[3:0] ,RTI Clock 2 Source" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK" textline " " bitfld.long 0x00 8.--9. " RTI1DIV[1:0] ,RTI Clock 1 Divider" "RTICLK1,RTICLK1/2,RTICLK1/4,RTICLK1/8" bitfld.long 0x00 0.--3. " RTI1SRC[3:0] ,RTI Clock 1 Source" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK" width 13. rgroup.long 0x54++0x3 line.long 0x0 "CSVSTAT,Clock Source Valid Status Register" bitfld.long 0x00 7. " CLKSR7V ,Clock Source 7 Valid" "Not valid,Valid" bitfld.long 0x00 6. " CLKSR6V ,Clock Source 6 Valid" "Not valid,Valid" bitfld.long 0x00 5. " CLKSR5V ,Clock Source 5 Valid" "Not valid,Valid" textline " " bitfld.long 0x00 4. " CLKSR4V ,Clock Source 4 Valid" "Not valid,Valid" bitfld.long 0x00 3. " CLKSR3V ,Clock Source 3 Valid" "Not valid,Valid" bitfld.long 0x00 2. " CLKSR2V ,Clock Source 2 Valid" "Not valid,Valid" textline " " bitfld.long 0x00 1. " CLKSR1V ,Clock Source 1 Valid" "Not valid,Valid" bitfld.long 0x00 0. " CLKSR0V ,Clock Source 0 Valid" "Not valid,Valid" width 13. group.long 0x58++0x3 line.long 0x0 "MSTGCR,Memory Self-Test Global Control Register" hexmask.long.byte 0x00 16.--23. 1. " MBIST_ALGSEL ,Selects Different Algorithm for MBIST" bitfld.long 0x00 8.--9. " ROM_DIV[1:0] ,ROM Clock Source Prescaler Divider" "HCLK,HCLK/2,HCLK/4,HCLK/8" bitfld.long 0x00 0.--3. " MSTGENA[3:0] ,Memory Self-Test Controller Global Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" group.long 0x5C++0x3 line.long 0x0 "MINITGCR,Memory Hardware Initialization Global Control Register" bitfld.long 0x00 0.--3. " MINITGENA[3:0] ,Memory Hardware Initialization Global Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" width 13. group.long 0x60++0x3 line.long 0x0 "MSINENA,MBIST Controller/Memory Initialization Enable Register" bitfld.long 0x00 31. " MSIENA31 ,MBIST Controller/Memory Initialization Enable 31" "Disabled,Enabled" bitfld.long 0x00 30. " MSIENA30 ,MBIST Controller/Memory Initialization Enable 30" "Disabled,Enabled" bitfld.long 0x00 29. " MSIENA29 ,MBIST Controller/Memory Initialization Enable 29" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " MSIENA28 ,MBIST Controller/Memory Initialization Enable 28" "Disabled,Enabled" bitfld.long 0x00 27. " MSIENA27 ,MBIST Controller/Memory Initialization Enable 27" "Disabled,Enabled" bitfld.long 0x00 26. " MSIENA26 ,MBIST Controller/Memory Initialization Enable 26" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " MSIENA25 ,MBIST Controller/Memory Initialization Enable 25" "Disabled,Enabled" bitfld.long 0x00 24. " MSIENA24 ,MBIST Controller/Memory Initialization Enable 24" "Disabled,Enabled" bitfld.long 0x00 23. " MSIENA23 ,MBIST Controller/Memory Initialization Enable 23" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " MSIENA22 ,MBIST Controller/Memory Initialization Enable 22" "Disabled,Enabled" bitfld.long 0x00 21. " MSIENA21 ,MBIST Controller/Memory Initialization Enable 21" "Disabled,Enabled" bitfld.long 0x00 20. " MSIENA20 ,MBIST Controller/Memory Initialization Enable 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " MSIENA19 ,MBIST Controller/Memory Initialization Enable 19" "Disabled,Enabled" bitfld.long 0x00 18. " MSIENA18 ,MBIST Controller/Memory Initialization Enable 18" "Disabled,Enabled" bitfld.long 0x00 17. " MSIENA17 ,MBIST Controller/Memory Initialization Enable 17" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " MSIENA16 ,MBIST Controller/Memory Initialization Enable 16" "Disabled,Enabled" bitfld.long 0x00 15. " MSIENA15 ,MBIST Controller/Memory Initialization Enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " MSIENA14 ,MBIST Controller/Memory Initialization Enable 14" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " MSIENA13 ,MBIST Controller/Memory Initialization Enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " MSIENA12 ,MBIST Controller/Memory Initialization Enable 12" "Disabled,Enabled" bitfld.long 0x00 11. " MSIENA11 ,MBIST Controller/Memory Initialization Enable 11" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " MSIENA10 ,MBIST Controller/Memory Initialization Enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " MSIENA9 ,MBIST Controller/Memory Initialization Enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " MSIENA8 ,MBIST Controller/Memory Initialization Enable 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " MSIENA7 ,MBIST Controller/Memory Initialization Enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " MSIENA6 ,MBIST Controller/Memory Initialization Enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " MSIENA5 ,MBIST Controller/Memory Initialization Enable 5" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " MSIENA4 ,MBIST Controller/Memory Initialization Enable 4" "Disabled,Enabled" bitfld.long 0x00 3. " MSIENA3 ,MBIST Controller/Memory Initialization Enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " MSIENA2 ,MBIST Controller/Memory Initialization Enable 2" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " MSIENA1 ,MBIST Controller/Memory Initialization Enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " MSIENA0 ,MBIST Controller/Memory Initialization Enable 0" "Disabled,Enabled" width 13. group.long 0x64++0x3 line.long 0x0 "MSTFAIL,Memory Self-Test Fail Status Register" eventfld.long 0x00 31. " MSTF31 ,Memory Self-Test Fail Status 31" "Not failed,Failed" eventfld.long 0x00 30. " MSTF30 ,Memory Self-Test Fail Status 30" "Not failed,Failed" eventfld.long 0x00 29. " MSTF29 ,Memory Self-Test Fail Status 29" "Not failed,Failed" textline " " eventfld.long 0x00 28. " MSTF28 ,Memory Self-Test Fail Status 28" "Not failed,Failed" eventfld.long 0x00 27. " MSTF27 ,Memory Self-Test Fail Status 27" "Not failed,Failed" eventfld.long 0x00 26. " MSTF26 ,Memory Self-Test Fail Status 26" "Not failed,Failed" textline " " eventfld.long 0x00 25. " MSTF25 ,Memory Self-Test Fail Status 25" "Not failed,Failed" eventfld.long 0x00 24. " MSTF24 ,Memory Self-Test Fail Status 24" "Not failed,Failed" eventfld.long 0x00 23. " MSTF23 ,Memory Self-Test Fail Status 23" "Not failed,Failed" textline " " eventfld.long 0x00 22. " MSTF22 ,Memory Self-Test Fail Status 22" "Not failed,Failed" eventfld.long 0x00 21. " MSTF21 ,Memory Self-Test Fail Status 21" "Not failed,Failed" eventfld.long 0x00 20. " MSTF20 ,Memory Self-Test Fail Status 20" "Not failed,Failed" textline " " eventfld.long 0x00 19. " MSTF19 ,Memory Self-Test Fail Status 19" "Not failed,Failed" eventfld.long 0x00 18. " MSTF18 ,Memory Self-Test Fail Status 18" "Not failed,Failed" eventfld.long 0x00 17. " MSTF17 ,Memory Self-Test Fail Status 17" "Not failed,Failed" textline " " eventfld.long 0x00 16. " MSTF16 ,Memory Self-Test Fail Status 16" "Not failed,Failed" eventfld.long 0x00 15. " MSTF15 ,Memory Self-Test Fail Status 15" "Not failed,Failed" eventfld.long 0x00 14. " MSTF14 ,Memory Self-Test Fail Status 14" "Not failed,Failed" textline " " eventfld.long 0x00 13. " MSTF13 ,Memory Self-Test Fail Status 13" "Not failed,Failed" eventfld.long 0x00 12. " MSTF12 ,Memory Self-Test Fail Status 12" "Not failed,Failed" eventfld.long 0x00 11. " MSTF11 ,Memory Self-Test Fail Status 11" "Not failed,Failed" textline " " eventfld.long 0x00 10. " MSTF10 ,Memory Self-Test Fail Status 10" "Not failed,Failed" eventfld.long 0x00 9. " MSTF9 ,Memory Self-Test Fail Status 9" "Not failed,Failed" eventfld.long 0x00 8. " MSTF8 ,Memory Self-Test Fail Status 8" "Not failed,Failed" textline " " eventfld.long 0x00 7. " MSTF7 ,Memory Self-Test Fail Status 7" "Not failed,Failed" eventfld.long 0x00 6. " MSTF6 ,Memory Self-Test Fail Status 6" "Not failed,Failed" eventfld.long 0x00 5. " MSTF5 ,Memory Self-Test Fail Status 5" "Not failed,Failed" textline " " eventfld.long 0x00 4. " MSTF4 ,Memory Self-Test Fail Status 4" "Not failed,Failed" eventfld.long 0x00 3. " MSTF3 ,Memory Self-Test Fail Status 3" "Not failed,Failed" eventfld.long 0x00 2. " MSTF2 ,Memory Self-Test Fail Status 2" "Not failed,Failed" textline " " eventfld.long 0x00 1. " MSTF1 ,Memory Self-Test Fail Status 1" "Not failed,Failed" eventfld.long 0x00 0. " MSTF0 ,Memory Self-Test Fail Status 0" "Not failed,Failed" width 13. group.long 0x68++0x3 line.long 0x0 "MSTCGSTAT,MSTC Global Status Register" eventfld.long 0x00 8. " MINIDONE ,Memory Hardware Initililization Test Run Complete Status" "Not completed,Completed" eventfld.long 0x00 0. " MSTDONE ,Memory Self-Test Run Complete Status" "Not completed,Completed" group.long 0x6C++0x3 line.long 0x0 "MINISTAT,Memory Hardware Initialization Status Register" eventfld.long 0x00 31. " MIDONE31 ,Memory Hardware Initialization Status 31" "Not completed,Completed" eventfld.long 0x00 30. " MIDONE30 ,Memory Hardware Initialization Status 30" "Not completed,Completed" textline " " eventfld.long 0x00 29. " MIDONE29 ,Memory Hardware Initialization Status 29" "Not completed,Completed" eventfld.long 0x00 28. " MIDONE28 ,Memory Hardware Initialization Status 28" "Not completed,Completed" textline " " eventfld.long 0x00 27. " MIDONE27 ,Memory Hardware Initialization Status 27" "Not completed,Completed" eventfld.long 0x00 26. " MIDONE26 ,Memory Hardware Initialization Status 26" "Not completed,Completed" textline " " eventfld.long 0x00 25. " MIDONE25 ,Memory Hardware Initialization Status 25" "Not completed,Completed" eventfld.long 0x00 24. " MIDONE24 ,Memory Hardware Initialization Status 24" "Not completed,Completed" textline " " eventfld.long 0x00 23. " MIDONE23 ,Memory Hardware Initialization Status 23" "Not completed,Completed" eventfld.long 0x00 22. " MIDONE22 ,Memory Hardware Initialization Status 22" "Not completed,Completed" textline " " eventfld.long 0x00 21. " MIDONE21 ,Memory Hardware Initialization Status 21" "Not completed,Completed" eventfld.long 0x00 20. " MIDONE20 ,Memory Hardware Initialization Status 20" "Not completed,Completed" textline " " eventfld.long 0x00 19. " MIDONE19 ,Memory Hardware Initialization Status 19" "Not completed,Completed" eventfld.long 0x00 18. " MIDONE18 ,Memory Hardware Initialization Status 18" "Not completed,Completed" textline " " eventfld.long 0x00 17. " MIDONE17 ,Memory Hardware Initialization Status 17" "Not completed,Completed" eventfld.long 0x00 16. " MIDONE16 ,Memory Hardware Initialization Status 16" "Not completed,Completed" textline " " eventfld.long 0x00 15. " MIDONE15 ,Memory Hardware Initialization Status 15" "Not completed,Completed" eventfld.long 0x00 14. " MIDONE14 ,Memory Hardware Initialization Status 14" "Not completed,Completed" textline " " eventfld.long 0x00 13. " MIDONE13 ,Memory Hardware Initialization Status 13" "Not completed,Completed" eventfld.long 0x00 12. " MIDONE12 ,Memory Hardware Initialization Status 12" "Not completed,Completed" textline " " eventfld.long 0x00 11. " MIDONE11 ,Memory Hardware Initialization Status 11" "Not completed,Completed" eventfld.long 0x00 10. " MIDONE10 ,Memory Hardware Initialization Status 10" "Not completed,Completed" textline " " eventfld.long 0x00 9. " MIDONE9 ,Memory Hardware Initialization Status 9" "Not completed,Completed" eventfld.long 0x00 8. " MIDONE8 ,Memory Hardware Initialization Status 8" "Not completed,Completed" textline " " eventfld.long 0x00 7. " MIDONE7 ,Memory Hardware Initialization Status 7" "Not completed,Completed" eventfld.long 0x00 6. " MIDONE6 ,Memory Hardware Initialization Status 6" "Not completed,Completed" textline " " eventfld.long 0x00 5. " MIDONE5 ,Memory Hardware Initialization Status 5" "Not completed,Completed" eventfld.long 0x00 4. " MIDONE4 ,Memory Hardware Initialization Status 4" "Not completed,Completed" textline " " eventfld.long 0x00 3. " MIDONE3 ,Memory Hardware Initialization Status 3" "Not completed,Completed" eventfld.long 0x00 2. " MIDONE2 ,Memory Hardware Initialization Status 2" "Not completed,Completed" textline " " eventfld.long 0x00 1. " MIDONE1 ,Memory Hardware Initialization Status 1" "Not completed,Completed" eventfld.long 0x00 0. " MIDONE0 ,Memory Hardware Initialization Status 0" "Not completed,Completed" width 13. group.long 0x70++0x3 line.long 0x0 "PLLCTL1,PLL Control Register 1" bitfld.long 0x00 31. " ROS ,Reset on PLL Cycle Slip" "No reset,Reset" bitfld.long 0x00 29.--30. " BPOS ,Bypass on PLL Slip" "Enabled,Enabled,Disabled,Enabled" bitfld.long 0x00 24.--28. " PLLDIV ,PLL Output Clock Divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" textline " " bitfld.long 0x00 23. " ROF ,Reset on Oscillator Fail" "No reset,Reset" bitfld.long 0x00 16.--21. " REFCLKDIV ,Reference Clock Divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" hexmask.long.word 0x00 0.--15. 1. " PLLMUL ,PLL Multiplication Factor" group.long 0x74++0x3 line.long 0x0 "PLLCTL2,PLL Control Register 2" bitfld.long 0x00 31. " FMENA ,Frequency Modulation Enable" "Disabled,Enabled" hexmask.long.word 0x00 22.--30. 1. " SPREADINGRATE ,Spreadingrate" hexmask.long.word 0x00 12.--20. 1. " BWADJ ,Bandwidth Adjustment" textline " " bitfld.long 0x00 9.--11. " ODPLL ,Internal PLL Output Divider" "/1,/2,/3,/4,/5,/6,/7,/8" hexmask.long.word 0x00 0.--8. 1. " SPR_AMOUNT ,Spreading Amount" rgroup.long 0x7C++0x3 line.long 0x0 "DIEIDL,Die Identification Register, Lower Word" rgroup.long 0x80++0x3 line.long 0x0 "DIEIDH,Die Identification Register Upper Word" width 13. group.long 0x84++0x3 line.long 0x0 "VRCTL,Voltage Regulator Control Register" bitfld.long 0x00 4.--7. " VLPMENA[3:0] ,Voltage Regulator Global Low Power Modes Enable" "Normal,Normal,Normal,Normal,Normal,Normal,Normal,Normal,Normal,Normal,Normal,Normal,Normal,Normal,Normal,Halt" bitfld.long 0x00 0.--3. " VSLEEPENA[3:0] ,Voltage Regulator Sleep Mode Enable" "Nonsleep,Nonsleep,Nonsleep,Nonsleep,Nonsleep,Nonsleep,Nonsleep,Nonsleep,Nonsleep,Nonsleep,Nonsleep,Nonsleep,Nonsleep,Nonsleep,Nonsleep,Sleep" group.long 0x88++0x3 line.long 0x0 "LPOMONCTL,LPO/Clock Monitor Control Register" bitfld.long 0x00 24. " BIAS_ENABLE ,Bias Enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " HFTRIM[3:0] ,High Frequency Oscillator Trim Value" "50 %,56.25 %,62.5 %,68.75 %,75 %,81.25 %,87.5 %,Reserved,100 %,106.25 %,112.5 %,118.75 %,125 %,131.25%,137.5 %,143.75 %" textline " " bitfld.long 0x00 0.--3. " LFTRIM[3:0] ,Low Frequency Oscillator Trim Value" "50 %,56.25 %,62.5 %,68.75 %,75 %,81.25 %,87.5 %,Reserved,100 %,106.25 %,112.5 %,118.75 %,125 %,131.25%,137.5 %,143.75 %" width 13. group.long 0x8C++0x3 line.long 0x0 "CLKTEST,Clock Test Register" bitfld.long 0x00 26. " ALTLIMPCLOCKENABLE ,Alternate Limp Clock Enable" "10-MHz LPO,ALTLIMPCLOCK" textline " " bitfld.long 0x00 25. " RANGEDETCTRL ,Range Detection Control" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " RANGEDETENSSEL ,Range Detection Enable Select" "Hardware,CLKTEST[RANGEDETCTRL]" textline " " bitfld.long 0x00 16.--19. " CLK_TEST_EN[3:0] ,Clock Test Enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled" textline " " bitfld.long 0x00 8.--11. " SEL_GIO_PIN[3:0] ,Clock Source Valid Signal/Clock Source at Functional GIO Pin Select" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 4/pin,?..." textline " " bitfld.long 0x00 0.--3. " SEL_ECP_PIN[3:0] ,Clock at ECP Pin Select" "Oscillator,PLL,32 KHz oscillator,External,LPO low,LPO high,Secondary PLL/Clock Source 6,Reserved,GCLKMCLK,RTICLK1SRC,RTICLK2SRC,AVCLK1,AVCLK2,?..." width 13. group.long 0x90++0x3 line.long 0x0 "DFTCTRLREG,DFT Control Register" bitfld.long 0x00 12.--13. " DFTWRITE ,DFT Logic Access Mode" "Use/Slow,Use/Fast,Screen/Slow,Screen/Fast" bitfld.long 0x00 8.--9. " DFTREAD ,DFT Logic Access" "Use/Slow,Use/Fast,Screen/Slow,Screen/Fast" bitfld.long 0x00 0.--3. " TEST_MODE_KEY ,Test Mode Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" width 13. group.long 0x94++0x3 line.long 0x0 "DFTCTRLREG2,DFT Control Register" bitfld.long 0x00 31. " IMPDF[27] ,DFT Implementation Defined Bit[27]" "Disabled,Enabled" bitfld.long 0x00 30. " IMPDF[26] ,DFT Implementation Defined Bit[26]" "Disabled,Enabled" bitfld.long 0x00 29. " IMPDF[25] ,DFT Implementation Defined Bit[25]" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " IMPDF[24] ,DFT Implementation Defined Bit[24]" "Disabled,Enabled" bitfld.long 0x00 27. " IMPDF[23] ,DFT Implementation Defined Bit[23]" "Disabled,Enabled" bitfld.long 0x00 26. " IMPDF[22] ,DFT Implementation Defined Bit[22]" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " IMPDF[21] ,DFT Implementation Defined Bit[21]" "Disabled,Enabled" bitfld.long 0x00 24. " IMPDF[20] ,DFT Implementation Defined Bit[20]" "Disabled,Enabled" bitfld.long 0x00 23. " IMPDF[19] ,DFT Implementation Defined Bit[19]" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " IMPDF[18] ,DFT Implementation Defined Bit[18]" "Disabled,Enabled" bitfld.long 0x00 21. " IMPDF[17] ,DFT Implementation Defined Bit[17]" "Disabled,Enabled" bitfld.long 0x00 20. " IMPDF[16] ,DFT Implementation Defined Bit[16]" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " IMPDF[15] ,DFT Implementation Defined Bit[15]" "Disabled,Enabled" bitfld.long 0x00 18. " IMPDF[14] ,DFT Implementation Defined Bit[14]" "Disabled,Enabled" bitfld.long 0x00 17. " IMPDF[13] ,DFT Implementation Defined Bit[13]" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " IMPDF[12] ,DFT Implementation Defined Bit[12]" "Disabled,Enabled" bitfld.long 0x00 15. " IMPDF[11] ,DFT Implementation Defined Bit[11]" "Disabled,Enabled" bitfld.long 0x00 14. " IMPDF[10] ,DFT Implementation Defined Bit[10]" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " IMPDF[9] ,DFT Implementation Defined Bit[9]" "Disabled,Enabled" bitfld.long 0x00 12. " IMPDF[8] ,DFT Implementation Defined Bit[8]" "Disabled,Enabled" bitfld.long 0x00 11. " IMPDF[7] ,DFT Implementation Defined Bit[7]" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " IMPDF[6] ,DFT Implementation Defined Bit[6]" "Disabled,Enabled" bitfld.long 0x00 9. " IMPDF[5] ,DFT Implementation Defined Bit[5]" "Disabled,Enabled" bitfld.long 0x00 8. " IMPDF[4] ,DFT Implementation Defined Bit[4]" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " IMPDF[3] ,DFT Implementation Defined Bit[3]" "Disabled,Enabled" bitfld.long 0x00 6. " IMPDF[2] ,DFT Implementation Defined Bit[2]" "Disabled,Enabled" bitfld.long 0x00 5. " IMPDF[1] ,DFT Implementation Defined Bit[1]" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " IMPDF[0] ,DFT Implementation Defined Bit[0]" "Disabled,Enabled" bitfld.long 0x00 0.--3. " TEST_MODE_KEY ,Test Mode Key (Internal TI Use Only)" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" width 13. group.long 0xa0++0x3 line.long 0x0 "GPREG1,General Purpose Register 1" group.long 0xA4++0x3 line.long 0x0 "BTRMSEL,BOOT ROM Select Register" hexmask.long.word 0x00 16.--31. 1. " BTRMSLRST[15:0] ,Boot ROM Select and Reset" bitfld.long 0x00 0.--3. " BTRMSEL[3:0] ,Boot ROM Select" "Reserved,Reserved,Reserved,Reserved,Reserved,Swapped,Reserved,Reserved,Reserved,Reserved,Default,?..." hgroup.long 0xA8++0x3 hide.long 0x0 "IMPFASTS,Imprecise Fault Status Register" in rgroup.long 0xAC++0x3 line.long 0x0 "IMPFTADD,Imprecise Fault Write Address Register" width 14. tree "System Software Interrupt Request Registers" group.long 0xB0++0x3 line.long 0x0 "SSIR1,System Software Interrupt Request 1 Register" hexmask.long.byte 0x00 8.--15. 1. " SSKEY1[7:0] ,System Software Interrupt Request Key" hexmask.long.byte 0x00 0.--7. 1. " SSDATA1[7:0] ,System Software Interrupt Data" group.long 0xFC++0x3 line.long 0x0 "SSIR1_Mirror,System Software Interrupt Request 1 Register (Mirror)" hexmask.long.byte 0x00 8.--15. 1. " SSKEY1[7:0] ,System Software Interrupt Request Key (Mirror)" hexmask.long.byte 0x00 0.--7. 1. " SSDATA1[7:0] ,System Software Interrupt Data (Mirror)" group.long 0xB4++0x3 line.long 0x0 "SSIR2,System Software Interrupt Request 2 Register" hexmask.long.byte 0x00 8.--15. 1. " SSKEY2[7:0] ,System Software Interrupt 2 Request Key" hexmask.long.byte 0x00 0.--7. 1. " SSDATA2[7:0] ,System Software Interrupt 2 Data" group.long 0xB8++0x3 line.long 0x0 "SSIR3,System Software Interrupt Request 3 Register" hexmask.long.byte 0x00 8.--15. 1. " SSKEY3[7:0] ,System Software Interrupt 3 Request Key" hexmask.long.byte 0x00 0.--7. 1. " SSDATA3[7:0] ,System Software Interrupt 3 Data" group.long 0xBC++0x3 line.long 0x0 "SSIR4,System Software Interrupt Request 4 Register" hexmask.long.byte 0x00 8.--15. 1. " SSKEY4[7:0] ,System Software Interrupt 3 Request Key" hexmask.long.byte 0x00 0.--7. 1. " SSDATA4[7:0] ,System Software Interrupt 4 Data" tree.end textline " " width 10. group.long 0xC0++0x3 line.long 0x0 "RAMGCR,RAM Control Register" bitfld.long 0x00 16.--19. " RAM_DFT_EN[3:0] ,Functional Mode RAM DFT Port Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" bitfld.long 0x00 14. " WST_AENA3 ,eSRAM3 Address Phase Wait State Enable" "Disabled,Enabled" bitfld.long 0x00 12. " WST_DENA3 ,eSRAM3 Data Phase Wait State Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " WST_AENA2 ,eSRAM2 Data Phase Wait State Enable" "Disabled,Enabled" bitfld.long 0x00 8. " WST_DENA2 ,eSRAM2 Data Phase Wait State Enable" "Disabled,Enabled" bitfld.long 0x00 6. " WST_AENA1 ,eSRAM1 Address Phase Wait State Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " WST_DENA1 ,eSRAM1 Data Phase Wait State Enable" "Disabled,Enabled" bitfld.long 0x00 2. " WST_AENA0 ,eSRAM0 Data Phase Wait State Enable" "Disabled,Enabled" bitfld.long 0x00 0. " WST_DENA0 ,eSRAM0 Data Phase Wait State Enable" "Disabled,Enabled" group.long 0xC4++0x3 line.long 0x0 "BMMCR1,Bus Matrix Module Control Register1" bitfld.long 0x00 0.--3. " MEMSW[3:0] ,Memory Swap Bit Key" "Reserved,Reserved,Reserved,Reserved,Reserved,Swapped,Reserved,Reserved,Reserved,Reserved,Default,?..." width 10. group.long 0xC8++0x3 line.long 0x0 "BMMCR2,Bus Matrix Module Control Register2" bitfld.long 0x00 6. " PRTY_HPI ,HPI Arbitration Priority" "Fixed,Round robin" bitfld.long 0x00 5. " PRTY_RAM3 ,eSRAM3 Arbitration Priority" "Fixed,Round robin" bitfld.long 0x00 4. " PRTY_RAM2 ,eSRAM2 Arbitration Priority" "Fixed,Round robin" textline " " bitfld.long 0x00 3. " PRTY_CRC ,CRC Arbitration Priority" "Fixed,Round robin" bitfld.long 0x00 2. " PRTY_PRG ,Peripheral Bridge Arbitration Priority" "Fixed,Round robin" bitfld.long 0x00 1. " PRTY_FLASH ,eSRAM1 Arbitration Priority" "Fixed,Round robin" textline " " bitfld.long 0x00 0. " PRTY_RAM0 ,eSRAM0 Arbitration Priority" "Fixed,Round robin" group.long 0xCC++0x3 line.long 0x0 "MMUGCR,MMU Global Control Register" bitfld.long 0x00 0. " MPMENA ,Memory Protection Mode Enable" "MMU/MPU,MPU" width 10. group.long 0xD0++0x3 line.long 0x0 "CLKCNTL,Clock Control Register" bitfld.long 0x00 24.--27. " VCLKR2[3:0] ,VBUS Clock 2 Ratio" "HCLK,HCLK/2,HCLK/3,HCLK/4,HCLK/5,HCLK/6,HCLK/7,HCLK/8,HCLK/9,HCLK/10,HCLK/11,HCLK/12,HCLK/13,HCLK/14,HCLK/15,HCLK/16" bitfld.long 0x00 16.--19. " VCLKR[3:0] ,VBUS Clock Ratio" "HCLK,HCLK/2,HCLK/3,HCLK/4,HCLK/5,HCLK/6,HCLK/7,HCLK/8,HCLK/9,HCLK/10,HCLK/11,HCLK/12,HCLK/13,HCLK/14,HCLK/15,HCLK/16" bitfld.long 0x00 8. " PENA ,Peripheral Enable" "Reset,No reset" group.long 0xD4++0x3 line.long 0x0 "ECPCNTRL,ECP Control Register" bitfld.long 0x00 24. " ECPSSEL ,ECP Source Clock Select for ECP Module" "Oscillator,VCLK" bitfld.long 0x00 23. " ECPCOS ,ECP Continue on Suspend" "Suspended,Continue" bitfld.long 0x00 16.--17. " ECPINSEL ,Select ECP Input Clock Source" "Tied Low,HCLK,External,Tied Low" textline " " hexmask.long.word 0x00 0.--15. 1. " ECPDIV[15:0] ,ECP Divider Value" group.long 0xD8++0x3 line.long 0x0 "DCPGCR,DSP Master Global Control Register" bitfld.long 0x00 0. " DSPSHENA ,DSP Share Enable" "Disabled,Enabled" group.long 0xDC++0x3 line.long 0x0 "DEVCR1,DEV Parity Control Register1" bitfld.long 0x00 0.--3. " DEVPARSEL ,Device Parity Select Bit Key" "Reserved,Reserved,Reserved,Reserved,Reserved,Even,Reserved,Reserved,Reserved,Reserved,Odd,?..." group.long 0xE0++0x3 line.long 0x0 "SYSECR,System Exception Control Register" bitfld.long 0x00 14.--15. " RESET[1:0] ,Software Reset" "Reset,No reset,Reset,Reset" width 10. group.long 0xE4++0x3 line.long 0x0 "SYSESR,System Exception Status Register" eventfld.long 0x00 15. " PORST ,Power-Up Reset" "No reset,Reset" eventfld.long 0x00 14. " OSCRST ,Oscillator Failure/PLL Cycle Slip Reset" "No reset,Reset" eventfld.long 0x00 13. " WDRST ,Watchdog Reset Flag" "No reset,Reset" textline " " eventfld.long 0x00 5. " CPURST ,CPU Reset Flag" "No reset,Reset" eventfld.long 0x00 4. " SWRST ,Software Reset Flag" "No reset,Reset" eventfld.long 0x00 3. " EXTRST ,External Reset Flag" "No reset,Reset" textline " " eventfld.long 0x00 2. " VSWRST ,Wake Up From Voltage Regulator Sleep Mode Reset Flag" "No reset,Reset" group.long 0xE8++0x3 line.long 0x0 "SYSTASR,System Test Abort Status Register" bitfld.long 0x00 0.--4. " EFUSE_Abort[4:0] ,Test Abort Status Flag" "Read: Last operation,Read: Controller times out,Read: Autoload/Not find FuseROM,Read: Autoload/Scan chain,Read: Autoload/Not completed operation,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Write: Cleared" width 10. group.long 0xEC++0x3 line.long 0x0 "GLBSTAT,Global Status Register" eventfld.long 0x00 9. " FBSLIP ,Over Cycle Slip Detection of PLL" "Not detected,Detected" eventfld.long 0x00 8. " RFSLIP ,Under Cycle Slip Detection of PLL" "Not detected,Detected" eventfld.long 0x00 0. " OSCFAIL ,Oscillator Fail Flag" "Not failed,Failed" rgroup.long 0xF0++0x3 line.long 0x0 "DEVID,Device Identification Register" bitfld.long 0x00 31. " CP15 ,CP15 CPU" "CP15,No CP15" hexmask.long.word 0x00 17.--30. 1. " ID ,Device ID" bitfld.long 0x00 13.--16. " TECH ,Device Manufacture Process Technology" "C05,F05,C035,F035,?..." textline " " bitfld.long 0x00 12. " I/O ,Input/Output Voltage" "3.3 V,5 V" bitfld.long 0x00 11. " PPAR ,Peripheral Parity" "No parity,Parity" bitfld.long 0x00 9.--10. " PROGRAM_PARITY ,Program Memory Parity Present" "Not protected,Single bit,ECC,?..." textline " " bitfld.long 0x00 8. " RECC ,RAM ECC" "No ECC,ECC" hexmask.long.byte 0x00 3.--7. 1. " VERSION ,Version" hexmask.long.byte 0x00 0.--2. 1. " PLATFORM_ID ,The TMSx70 Platform ID" hgroup.long 0xF4++0x3 hide.long 0x0 "SSIVEC,Software Interrupt Vector Register" in width 10. group.long 0xF8++0x3 line.long 0x0 "SSIF,System Software Interrupt Flag Register" eventfld.long 0x00 3. " SSI_FLAG4 ,System Software Interrupt Flag 4" "No interrupt,Interrupt" eventfld.long 0x00 2. " SSI_FLAG43 ,System Software Interrupt Flag 3" "No interrupt,Interrupt" textline " " eventfld.long 0x00 1. " SSI_FLAG42 ,System Software Interrupt Flag 2" "No interrupt,Interrupt" eventfld.long 0x00 0. " SSI_FLAG41 ,System Software Interrupt Flag 1" "No interrupt,Interrupt" width 0xb tree.end tree.open "VIM (Vectored Interrupt Manager)" tree "VIM" base ad:0xFFFFFE00 width 9. tree "VIM Offset Vector Registers" rgroup.long 0x00++0x3 line.long 0x0 "IRQINDEX,Index Offset Vector Register" hexmask.long.byte 0x00 0.--7. 1. " IRQIVEC ,IRQ index vector" rgroup.long 0x04++0x3 line.long 0x0 "FIQINDEX,Index Offset Vector Register" hexmask.long.byte 0x00 0.--7. 1. " FIQVEC ,FIQ index offset vector" tree.end width 9. group.long 0x10++0x3 line.long 0x0 "FIRQPR0,Program Control Register" bitfld.long 0x00 31. " FIRQPR_31 ,FIQ/IRQ Program Control 31" "IRQ,FIQ" bitfld.long 0x00 29. " FIRQPR_29 ,FIQ/IRQ Program Control 29" "IRQ,FIQ" bitfld.long 0x00 28. " FIRQPR_28 ,FIQ/IRQ Program Control 28" "IRQ,FIQ" bitfld.long 0x00 27. " FIRQPR_27 ,FIQ/IRQ Program Control 27" "IRQ,FIQ" textline " " bitfld.long 0x00 26. " FIRQPR_26 ,FIQ/IRQ Program Control 26" "IRQ,FIQ" bitfld.long 0x00 25. " FIRQPR_25 ,FIQ/IRQ Program Control 25" "IRQ,FIQ" bitfld.long 0x00 24. " FIRQPR_24 ,FIQ/IRQ Program Control 24" "IRQ,FIQ" bitfld.long 0x00 23. " FIRQPR_23 ,FIQ/IRQ Program Control 23" "IRQ,FIQ" textline " " bitfld.long 0x00 22. " FIRQPR_22 ,FIQ/IRQ Program Control 22" "IRQ,FIQ" bitfld.long 0x00 21. " FIRQPR_21 ,FIQ/IRQ Program Control 21" "IRQ,FIQ" bitfld.long 0x00 20. " FIRQPR_20 ,FIQ/IRQ Program Control 20" "IRQ,FIQ" bitfld.long 0x00 19. " FIRQPR_19 ,FIQ/IRQ Program Control 19" "IRQ,FIQ" textline " " bitfld.long 0x00 18. " FIRQPR_18 ,FIQ/IRQ Program Control 18" "IRQ,FIQ" bitfld.long 0x00 16. " FIRQPR_16 ,FIQ/IRQ Program Control 16" "IRQ,FIQ" bitfld.long 0x00 15. " FIRQPR_15 ,FIQ/IRQ Program Control 15" "IRQ,FIQ" bitfld.long 0x00 14. " FIRQPR_14 ,FIQ/IRQ Program Control 14" "IRQ,FIQ" textline " " bitfld.long 0x00 13. " FIRQPR_13 ,FIQ/IRQ Program Control 13" "IRQ,FIQ" bitfld.long 0x00 12. " FIRQPR_12 ,FIQ/IRQ Program Control 12" "IRQ,FIQ" bitfld.long 0x00 11. " FIRQPR_11 ,FIQ/IRQ Program Control 11" "IRQ,FIQ" bitfld.long 0x00 10. " FIRQPR_10 ,FIQ/IRQ Program Control 10" "IRQ,FIQ" textline " " bitfld.long 0x00 9. " FIRQPR_9 ,FIQ/IRQ Program Control 9" "IRQ,FIQ" bitfld.long 0x00 8. " FIRQPR_8 ,FIQ/IRQ Program Control 8" "IRQ,FIQ" bitfld.long 0x00 7. " FIRQPR_7 ,FIQ/IRQ Program Control 7" "IRQ,FIQ" bitfld.long 0x00 6. " FIRQPR_6 ,FIQ/IRQ Program Control 6" "IRQ,FIQ" textline " " bitfld.long 0x00 5. " FIRQPR_5 ,FIQ/IRQ Program Control 5" "IRQ,FIQ" bitfld.long 0x00 4. " FIRQPR_4 ,FIQ/IRQ Program Control 4" "IRQ,FIQ" bitfld.long 0x00 3. " FIRQPR_3 ,FIQ/IRQ Program Control 3" "IRQ,FIQ" bitfld.long 0x00 2. " FIRQPR_2 ,FIQ/IRQ Program Control 2" "IRQ,FIQ" textline " " bitfld.long 0x00 0. " FIRQPR_0 ,FIQ/IRQ Program Control 0" "IRQ,FIQ" group.long 0x14++0x3 line.long 0x0 "FIRQPR1,Program Control Register" bitfld.long 0x00 30. " FIRQPR_62 ,FIQ/IRQ Program Control 62" "IRQ,FIQ" bitfld.long 0x00 28. " FIRQPR_60 ,FIQ/IRQ Program Control 60" "IRQ,FIQ" bitfld.long 0x00 27. " FIRQPR_59 ,FIQ/IRQ Program Control 59" "IRQ,FIQ" bitfld.long 0x00 26. " FIRQPR_58 ,FIQ/IRQ Program Control 58" "IRQ,FIQ" textline " " bitfld.long 0x00 25. " FIRQPR_57 ,FIQ/IRQ Program Control 57" "IRQ,FIQ" bitfld.long 0x00 24. " FIRQPR_56 ,FIQ/IRQ Program Control 56" "IRQ,FIQ" bitfld.long 0x00 23. " FIRQPR_55 ,FIQ/IRQ Program Control 55" "IRQ,FIQ" bitfld.long 0x00 22. " FIRQPR_54 ,FIQ/IRQ Program Control 54" "IRQ,FIQ" textline " " bitfld.long 0x00 21. " FIRQPR_53 ,FIQ/IRQ Program Control 53" "IRQ,FIQ" bitfld.long 0x00 20. " FIRQPR_52 ,FIQ/IRQ Program Control 52" "IRQ,FIQ" bitfld.long 0x00 19. " FIRQPR_51 ,FIQ/IRQ Program Control 51" "IRQ,FIQ" bitfld.long 0x00 18. " FIRQPR_50 ,FIQ/IRQ Program Control 50" "IRQ,FIQ" textline " " bitfld.long 0x00 17. " FIRQPR_49 ,FIQ/IRQ Program Control 49" "IRQ,FIQ" bitfld.long 0x00 16. " FIRQPR_48 ,FIQ/IRQ Program Control 48" "IRQ,FIQ" bitfld.long 0x00 15. " FIRQPR_47 ,FIQ/IRQ Program Control 47" "IRQ,FIQ" bitfld.long 0x00 14. " FIRQPR_46 ,FIQ/IRQ Program Control 46" "IRQ,FIQ" textline " " bitfld.long 0x00 13. " FIRQPR_45 ,FIQ/IRQ Program Control 45" "IRQ,FIQ" bitfld.long 0x00 12. " FIRQPR_44 ,FIQ/IRQ Program Control 44" "IRQ,FIQ" bitfld.long 0x00 11. " FIRQPR_43 ,FIQ/IRQ Program Control 43" "IRQ,FIQ" bitfld.long 0x00 10. " FIRQPR_42 ,FIQ/IRQ Program Control 42" "IRQ,FIQ" textline " " bitfld.long 0x00 8. " FIRQPR_40 ,FIQ/IRQ Program Control 40" "IRQ,FIQ" bitfld.long 0x00 7. " FIRQPR_39 ,FIQ/IRQ Program Control 39" "IRQ,FIQ" bitfld.long 0x00 6. " FIRQPR_38 ,FIQ/IRQ Program Control 38" "IRQ,FIQ" bitfld.long 0x00 5. " FIRQPR_37 ,FIQ/IRQ Program Control 37" "IRQ,FIQ" textline " " bitfld.long 0x00 4. " FIRQPR_36 ,FIQ/IRQ Program Control 36" "IRQ,FIQ" bitfld.long 0x00 3. " FIRQPR_35 ,FIQ/IRQ Program Control 35" "IRQ,FIQ" bitfld.long 0x00 2. " FIRQPR_34 ,FIQ/IRQ Program Control 34" "IRQ,FIQ" bitfld.long 0x00 1. " FIRQPR_33 ,FIQ/IRQ Program Control 33" "IRQ,FIQ" textline " " bitfld.long 0x00 0. " FIRQPR_32 ,FIQ/IRQ Program Control 32" "IRQ,FIQ" width 9. tree "VIM Pending Interrupt Read Location Registers" rgroup.long 0x20++0x3 line.long 0x0 "INTREQ0,Pending Interrupt Read Location" bitfld.long 0x00 31. " INTREQ_31 ,Interrupt Pending 31" "No interrupt,Interrupt" bitfld.long 0x00 29. " INTREQ_29 ,Interrupt Pending 29" "No interrupt,Interrupt" textline " " bitfld.long 0x00 28. " INTREQ_28 ,Interrupt Pending 28" "No interrupt,Interrupt" bitfld.long 0x00 27. " INTREQ_27 ,Interrupt Pending 27" "No interrupt,Interrupt" textline " " bitfld.long 0x00 26. " INTREQ_26 ,Interrupt Pending 26" "No interrupt,Interrupt" bitfld.long 0x00 25. " INTREQ_25 ,Interrupt Pending 25" "No interrupt,Interrupt" textline " " bitfld.long 0x00 24. " INTREQ_24 ,Interrupt Pending 24" "No interrupt,Interrupt" bitfld.long 0x00 23. " INTREQ_23 ,Interrupt Pending 23" "No interrupt,Interrupt" textline " " bitfld.long 0x00 22. " INTREQ_22 ,Interrupt Pending 22" "No interrupt,Interrupt" bitfld.long 0x00 21. " INTREQ_21 ,Interrupt Pending 21" "No interrupt,Interrupt" textline " " bitfld.long 0x00 20. " INTREQ_20 ,Interrupt Pending 20" "No interrupt,Interrupt" bitfld.long 0x00 19. " INTREQ_19 ,Interrupt Pending 19" "No interrupt,Interrupt" textline " " bitfld.long 0x00 18. " INTREQ_18 ,Interrupt Pending 18" "No interrupt,Interrupt" bitfld.long 0x00 16. " INTREQ_16 ,Interrupt Pending 16" "No interrupt,Interrupt" textline " " bitfld.long 0x00 15. " INTREQ_15 ,Interrupt Pending 15" "No interrupt,Interrupt" bitfld.long 0x00 14. " INTREQ_14 ,Interrupt Pending 14" "No interrupt,Interrupt" textline " " bitfld.long 0x00 13. " INTREQ_13 ,Interrupt Pending 13" "No interrupt,Interrupt" bitfld.long 0x00 12. " INTREQ_12 ,Interrupt Pending 12" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " INTREQ_11 ,Interrupt Pending 11" "No interrupt,Interrupt" bitfld.long 0x00 10. " INTREQ_10 ,Interrupt Pending 10" "No interrupt,Interrupt" textline " " bitfld.long 0x00 9. " INTREQ_9 ,Interrupt Pending 9" "No interrupt,Interrupt" bitfld.long 0x00 8. " INTREQ_8 ,Interrupt Pending 8" "No interrupt,Interrupt" textline " " bitfld.long 0x00 7. " INTREQ_7 ,Interrupt Pending 7" "No interrupt,Interrupt" bitfld.long 0x00 6. " INTREQ_6 ,Interrupt Pending 6" "No interrupt,Interrupt" textline " " bitfld.long 0x00 5. " INTREQ_5 ,Interrupt Pending 5" "No interrupt,Interrupt" bitfld.long 0x00 4. " INTREQ_4 ,Interrupt Pending 4" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " INTREQ_3 ,Interrupt Pending 3" "No interrupt,Interrupt" bitfld.long 0x00 2. " INTREQ_2 ,Interrupt Pending 2" "No interrupt,Interrupt" textline " " bitfld.long 0x00 0. " INTREQ_0 ,Interrupt Pending 0" "No interrupt,Interrupt" rgroup.long 0x24++0x3 line.long 0x0 "INTREQ1,Pending Interrupt Read Location" bitfld.long 0x00 30. " INTREQ_62 ,Interrupt Pending 62" "No interrupt,Interrupt" bitfld.long 0x00 28. " INTREQ_60 ,Interrupt Pending 60" "No interrupt,Interrupt" textline " " bitfld.long 0x00 27. " INTREQ_59 ,Interrupt Pending 59" "No interrupt,Interrupt" bitfld.long 0x00 26. " INTREQ_58 ,Interrupt Pending 58" "No interrupt,Interrupt" textline " " bitfld.long 0x00 25. " INTREQ_57 ,Interrupt Pending 57" "No interrupt,Interrupt" bitfld.long 0x00 24. " INTREQ_56 ,Interrupt Pending 56" "No interrupt,Interrupt" textline " " bitfld.long 0x00 23. " INTREQ_55 ,Interrupt Pending 55" "No interrupt,Interrupt" bitfld.long 0x00 22. " INTREQ_54 ,Interrupt Pending 54" "No interrupt,Interrupt" textline " " bitfld.long 0x00 21. " INTREQ_53 ,Interrupt Pending 53" "No interrupt,Interrupt" bitfld.long 0x00 20. " INTREQ_52 ,Interrupt Pending 52" "No interrupt,Interrupt" textline " " bitfld.long 0x00 19. " INTREQ_51 ,Interrupt Pending 51" "No interrupt,Interrupt" bitfld.long 0x00 18. " INTREQ_50 ,Interrupt Pending 50" "No interrupt,Interrupt" textline " " bitfld.long 0x00 17. " INTREQ_49 ,Interrupt Pending 49" "No interrupt,Interrupt" bitfld.long 0x00 16. " INTREQ_48 ,Interrupt Pending 48" "No interrupt,Interrupt" textline " " bitfld.long 0x00 15. " INTREQ_47 ,Interrupt Pending 47" "No interrupt,Interrupt" bitfld.long 0x00 14. " INTREQ_46 ,Interrupt Pending 46" "No interrupt,Interrupt" textline " " bitfld.long 0x00 13. " INTREQ_45 ,Interrupt Pending 45" "No interrupt,Interrupt" bitfld.long 0x00 12. " INTREQ_44 ,Interrupt Pending 44" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " INTREQ_43 ,Interrupt Pending 43" "No interrupt,Interrupt" bitfld.long 0x00 10. " INTREQ_42 ,Interrupt Pending 42" "No interrupt,Interrupt" textline " " bitfld.long 0x00 8. " INTREQ_40 ,Interrupt Pending 40" "No interrupt,Interrupt" bitfld.long 0x00 7. " INTREQ_39 ,Interrupt Pending 39" "No interrupt,Interrupt" textline " " bitfld.long 0x00 6. " INTREQ_38 ,Interrupt Pending 38" "No interrupt,Interrupt" bitfld.long 0x00 5. " INTREQ_37 ,Interrupt Pending 37" "No interrupt,Interrupt" textline " " bitfld.long 0x00 4. " INTREQ_36 ,Interrupt Pending 36" "No interrupt,Interrupt" bitfld.long 0x00 3. " INTREQ_35 ,Interrupt Pending 35" "No interrupt,Interrupt" textline " " bitfld.long 0x00 2. " INTREQ_34 ,Interrupt Pending 34" "No interrupt,Interrupt" bitfld.long 0x00 1. " INTREQ_33 ,Interrupt Pending 33" "No interrupt,Interrupt" textline " " bitfld.long 0x00 0. " INTREQ_32 ,Interrupt Pending 32" "No interrupt,Interrupt" tree.end width 13. tree "VIM Interrupt Mask Registers" group.long 0x30++0x3 line.long 0x0 "REQMASKSET0,Interrupt Mask Register" setclrfld.long 0x00 31. 0x00 31. 0x10 31. " REQMASK_31_set/clr ,Request Mask 31" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x10 29. " REQMASK_29_set/clr ,Request Mask 29" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x10 28. " REQMASK_28_set/clr ,Request Mask 28" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x10 27. " REQMASK_27_set/clr ,Request Mask 27" "Disabled,Enabled" textline " " setclrfld.long 0x00 26. 0x00 26. 0x10 26. " REQMASK_26_set/clr ,Request Mask 26" "Disabled,Enabled" setclrfld.long 0x00 25. 0x00 25. 0x10 25. " REQMASK_25_set/clr ,Request Mask 25" "Disabled,Enabled" textline " " setclrfld.long 0x00 24. 0x00 24. 0x10 24. " REQMASK_24_set/clr ,Request Mask 24" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x10 23. " REQMASK_23_set/clr ,Request Mask 23" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x10 22. " REQMASK_22_set/clr ,Request Mask 22" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x10 21. " REQMASK_21_set/clr ,Request Mask 21" "Disabled,Enabled" textline " " setclrfld.long 0x00 20. 0x00 20. 0x10 20. " REQMASK_20_set/clr ,Request Mask 20" "Disabled,Enabled" setclrfld.long 0x00 19. 0x00 19. 0x10 19. " REQMASK_19_set/clr ,Request Mask 19" "Disabled,Enabled" textline " " setclrfld.long 0x00 18. 0x00 18. 0x10 18. " REQMASK_18_set/clr ,Request Mask 18" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x10 16. " REQMASK_16_set/clr ,Request Mask 16" "Disabled,Enabled" textline " " setclrfld.long 0x00 15. 0x00 15. 0x10 15. " REQMASK_15_set/clr ,Request Mask 15" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x10 14. " REQMASK_14_set/clr ,Request Mask 14" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x10 13. " REQMASK_13_set/clr ,Request Mask 13" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x10 12. " REQMASK_12_set/clr ,Request Mask 12" "Disabled,Enabled" textline " " setclrfld.long 0x00 11. 0x00 11. 0x10 11. " REQMASK_11_set/clr ,Request Mask 11" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x10 10. " REQMASK_10_set/clr ,Request Mask 10" "Disabled,Enabled" textline " " setclrfld.long 0x00 9. 0x00 9. 0x10 9. " REQMASK_9_set/clr ,Request Mask 9" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x10 8. " REQMASK_8_set/clr ,Request Mask 8" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x10 7. " REQMASK_7_set/clr ,Request Mask 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x10 6. " REQMASK_6_set/clr ,Request Mask 6" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. 0x00 5. 0x10 5. " REQMASK_5_set/clr ,Request Mask 5" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x10 4. " REQMASK_4_set/clr ,Request Mask 4" "Disabled,Enabled" textline " " setclrfld.long 0x00 3. 0x00 3. 0x10 3. " REQMASK_3_set/clr ,Request Mask 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x10 2. " REQMASK_2_set/clr ,Request Mask 2" "Disabled,Enabled" textline " " setclrfld.long 0x00 0. 0x00 0. 0x10 0. " REQMASK_0_set/clr ,Request Mask 0" "Disabled,Enabled" group.long 0x34++0x3 line.long 0x0 "REQMASKSET1,Interrupt Mask Register" setclrfld.long 0x00 30. 0x00 30. 0x10 30. " REQMASK_62_set/clr ,Request Mask 62" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x10 28. " REQMASK_60_set/clr ,Request Mask 60" "Disabled,Enabled" textline " " setclrfld.long 0x00 27. 0x00 27. 0x10 27. " REQMASK_59_set/clr ,Request Mask 59" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x10 26. " REQMASK_58_set/clr ,Request Mask 58" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x10 25. " REQMASK_57_set/clr ,Request Mask 57" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x10 24. " REQMASK_56_set/clr ,Request Mask 56" "Disabled,Enabled" textline " " setclrfld.long 0x00 23. 0x00 23. 0x10 23. " REQMASK_55_set/clr ,Request Mask 55" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x10 22. " REQMASK_54_set/clr ,Request Mask 54" "Disabled,Enabled" textline " " setclrfld.long 0x00 21. 0x00 21. 0x10 21. " REQMASK_53_set/clr ,Request Mask 53" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x10 20. " REQMASK_52_set/clr ,Request Mask 52" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x10 19. " REQMASK_51_set/clr ,Request Mask 51" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x10 18. " REQMASK_50_set/clr ,Request Mask 50" "Disabled,Enabled" textline " " setclrfld.long 0x00 17. 0x00 17. 0x10 17. " REQMASK_49_set/clr ,Request Mask 49" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x10 16. " REQMASK_48_set/clr ,Request Mask 48" "Disabled,Enabled" textline " " setclrfld.long 0x00 15. 0x00 15. 0x10 15. " REQMASK_47_set/clr ,Request Mask 47" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x10 14. " REQMASK_46_set/clr ,Request Mask 46" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x10 13. " REQMASK_45_set/clr ,Request Mask 45" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x10 12. " REQMASK_44_set/clr ,Request Mask 44" "Disabled,Enabled" textline " " setclrfld.long 0x00 11. 0x00 11. 0x10 11. " REQMASK_43_set/clr ,Request Mask 43" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x10 10. " REQMASK_42_set/clr ,Request Mask 42" "Disabled,Enabled" textline " " setclrfld.long 0x00 8. 0x00 8. 0x10 8. " REQMASK_40_set/clr ,Request Mask 40" "Disabled,Enabled" setclrfld.long 0x00 7. 0x00 7. 0x10 7. " REQMASK_39_set/clr ,Request Mask 39" "Disabled,Enabled" textline " " setclrfld.long 0x00 6. 0x00 6. 0x10 6. " REQMASK_38_set/clr ,Request Mask 38" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x10 5. " REQMASK_37_set/clr ,Request Mask 37" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x10 4. " REQMASK_36_set/clr ,Request Mask 36" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x10 3. " REQMASK_35_set/clr ,Request Mask 35" "Disabled,Enabled" textline " " setclrfld.long 0x00 2. 0x00 2. 0x10 2. " REQMASK_34_set/clr ,Request Mask 34" "Disabled,Enabled" setclrfld.long 0x00 1. 0x00 1. 0x10 1. " REQMASK_33_set/clr ,Request Mask 33" "Disabled,Enabled" textline " " setclrfld.long 0x00 0. 0x00 0. 0x10 0. " REQMASK_32_set/clr ,Request Mask 32" "Disabled,Enabled" tree.end width 14. tree "VIM Wake Up Mask Registers" group.long 0x50++0x3 line.long 0x0 "WAKEMASKSET0,Wake-up Mask Register" setclrfld.long 0x00 31. 0x00 31. 0x10 31. " WAKEMASK_31_set/clr ,Wake Up Mask 31" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x10 29. " WAKEMASK_29_set/clr ,Wake Up Mask 29" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x10 28. " WAKEMASK_28_set/clr ,Wake Up Mask 28" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x10 27. " WAKEMASK_27_set/clr ,Wake Up Mask 27" "Disabled,Enabled" textline " " setclrfld.long 0x00 26. 0x00 26. 0x10 26. " WAKEMASK_26_set/clr ,Wake Up Mask 26" "Disabled,Enabled" setclrfld.long 0x00 25. 0x00 25. 0x10 25. " WAKEMASK_25_set/clr ,Wake Up Mask 25" "Disabled,Enabled" textline " " setclrfld.long 0x00 24. 0x00 24. 0x10 24. " WAKEMASK_24_set/clr ,Wake Up Mask 24" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x10 23. " WAKEMASK_23_set/clr ,Wake Up Mask 23" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x10 22. " WAKEMASK_22_set/clr ,Wake Up Mask 22" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x10 21. " WAKEMASK_21_set/clr ,Wake Up Mask 21" "Disabled,Enabled" textline " " setclrfld.long 0x00 20. 0x00 20. 0x10 20. " WAKEMASK_20_set/clr ,Wake Up Mask 20" "Disabled,Enabled" setclrfld.long 0x00 19. 0x00 19. 0x10 19. " WAKEMASK_19_set/clr ,Wake Up Mask 19" "Disabled,Enabled" textline " " setclrfld.long 0x00 18. 0x00 18. 0x10 18. " WAKEMASK_18_set/clr ,Wake Up Mask 18" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x10 16. " WAKEMASK_16_set/clr ,Wake Up Mask 16" "Disabled,Enabled" textline " " setclrfld.long 0x00 15. 0x00 15. 0x10 15. " WAKEMASK_15_set/clr ,Wake Up Mask 15" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x10 14. " WAKEMASK_14_set/clr ,Wake Up Mask 14" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x10 13. " WAKEMASK_13_set/clr ,Wake Up Mask 13" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x10 12. " WAKEMASK_12_set/clr ,Wake Up Mask 12" "Disabled,Enabled" textline " " setclrfld.long 0x00 11. 0x00 11. 0x10 11. " WAKEMASK_11_set/clr ,Wake Up Mask 11" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x10 10. " WAKEMASK_10_set/clr ,Wake Up Mask 10" "Disabled,Enabled" textline " " setclrfld.long 0x00 9. 0x00 9. 0x10 9. " WAKEMASK_9_set/clr ,Wake Up Mask 9" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x10 8. " WAKEMASK_8_set/clr ,Wake Up Mask 8" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x10 7. " WAKEMASK_7_set/clr ,Wake Up Mask 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x10 6. " WAKEMASK_6_set/clr ,Wake Up Mask 6" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. 0x00 5. 0x10 5. " WAKEMASK_5_set/clr ,Wake Up Mask 5" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x10 4. " WAKEMASK_4_set/clr ,Wake Up Mask 4" "Disabled,Enabled" textline " " setclrfld.long 0x00 3. 0x00 3. 0x10 3. " WAKEMASK_3_set/clr ,Wake Up Mask 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x10 2. " WAKEMASK_2_set/clr ,Wake Up Mask 2" "Disabled,Enabled" textline " " setclrfld.long 0x00 0. 0x00 0. 0x10 0. " WAKEMASK_0_set/clr ,Wake Up Mask 0" "Disabled,Enabled" group.long 0x54++0x3 line.long 0x0 "WAKEMASKSET1,Wake-up Mask Register" setclrfld.long 0x00 30. 0x00 30. 0x10 30. " WAKEMASK_62_set/clr ,Wake Up Mask 62" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x10 28. " WAKEMASK_60_set/clr ,Wake Up Mask 60" "Disabled,Enabled" textline " " setclrfld.long 0x00 27. 0x00 27. 0x10 27. " WAKEMASK_59_set/clr ,Wake Up Mask 59" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x10 26. " WAKEMASK_58_set/clr ,Wake Up Mask 58" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x10 25. " WAKEMASK_57_set/clr ,Wake Up Mask 57" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x10 24. " WAKEMASK_56_set/clr ,Wake Up Mask 56" "Disabled,Enabled" textline " " setclrfld.long 0x00 23. 0x00 23. 0x10 23. " WAKEMASK_55_set/clr ,Wake Up Mask 55" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x10 22. " WAKEMASK_54_set/clr ,Wake Up Mask 54" "Disabled,Enabled" textline " " setclrfld.long 0x00 21. 0x00 21. 0x10 21. " WAKEMASK_53_set/clr ,Wake Up Mask 53" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x10 20. " WAKEMASK_52_set/clr ,Wake Up Mask 52" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x10 19. " WAKEMASK_51_set/clr ,Wake Up Mask 51" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x10 18. " WAKEMASK_50_set/clr ,Wake Up Mask 50" "Disabled,Enabled" textline " " setclrfld.long 0x00 17. 0x00 17. 0x10 17. " WAKEMASK_49_set/clr ,Wake Up Mask 49" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x10 16. " WAKEMASK_48_set/clr ,Wake Up Mask 48" "Disabled,Enabled" textline " " setclrfld.long 0x00 15. 0x00 15. 0x10 15. " WAKEMASK_47_set/clr ,Wake Up Mask 47" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x10 14. " WAKEMASK_46_set/clr ,Wake Up Mask 46" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x10 13. " WAKEMASK_45_set/clr ,Wake Up Mask 45" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x10 12. " WAKEMASK_44_set/clr ,Wake Up Mask 44" "Disabled,Enabled" textline " " setclrfld.long 0x00 11. 0x00 11. 0x10 11. " WAKEMASK_43_set/clr ,Wake Up Mask 43" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x10 10. " WAKEMASK_42_set/clr ,Wake Up Mask 42" "Disabled,Enabled" textline " " setclrfld.long 0x00 8. 0x00 8. 0x10 8. " WAKEMASK_40_set/clr ,Wake Up Mask 40" "Disabled,Enabled" setclrfld.long 0x00 7. 0x00 7. 0x10 7. " WAKEMASK_39_set/clr ,Wake Up Mask 39" "Disabled,Enabled" textline " " setclrfld.long 0x00 6. 0x00 6. 0x10 6. " WAKEMASK_38_set/clr ,Wake Up Mask 38" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x10 5. " WAKEMASK_37_set/clr ,Wake Up Mask 37" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x10 4. " WAKEMASK_36_set/clr ,Wake Up Mask 36" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x10 3. " WAKEMASK_35_set/clr ,Wake Up Mask 35" "Disabled,Enabled" textline " " setclrfld.long 0x00 2. 0x00 2. 0x10 2. " WAKEMASK_34_set/clr ,Wake Up Mask 34" "Disabled,Enabled" setclrfld.long 0x00 1. 0x00 1. 0x10 1. " WAKEMASK_33_set/clr ,Wake Up Mask 33" "Disabled,Enabled" textline " " setclrfld.long 0x00 0. 0x00 0. 0x10 0. " WAKEMASK_32_set/clr ,Wake Up Mask 32" "Disabled,Enabled" tree.end width 11. tree "VIM Interrupt Vector Registers" rgroup.long 0x70++0x3 line.long 0x0 "IRQVECREG,IRQ Interrupt Vector Register" rgroup.long 0x74++0x3 line.long 0x0 "FIQVECREG,FIQ Interrupt Vector Register" tree.end width 11. group.long 0x78++0x3 line.long 0x0 "CAPEVT,Capture Event register" hexmask.long.byte 0x00 16.--22. 1. " CAPEVTSRC1[6:0] ,Capture Event Source 1 Mapping Control" hexmask.long.byte 0x00 0.--6. 1. " CAPEVTSRC0[6:0] ,Capture Event Source 0 Mapping Control" width 12. tree "VIM Interrupt Control Registers" group.long 0x80++0x3 line.long 0x0 "CHANCTRL0,VIM Interrupt Control Register 0" hexmask.long.byte 0x00 24.--30. 1. " CHANMAP0[6:0] ,Interrupt CHAN0 Mapping Control" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP1[6:0] ,Interrupt CHAN1 Mapping Control" hexmask.long.byte 0x00 8.--14. 1. " CHANMAP2[6:0] ,Interrupt CHAN2 Mapping Control" textline " " hexmask.long.byte 0x00 0.--6. 1. " CHANMAP3[6:0] ,Interrupt CHAN3 Mapping Control" group.long 0x84++0x3 line.long 0x0 "CHANCTRL1,VIM Interrupt Control Register 1" hexmask.long.byte 0x00 24.--30. 1. " CHANMAP4[6:0] ,Interrupt CHAN4 Mapping Control" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP5[6:0] ,Interrupt CHAN5 Mapping Control" hexmask.long.byte 0x00 8.--14. 1. " CHANMAP6[6:0] ,Interrupt CHAN6 Mapping Control" textline " " hexmask.long.byte 0x00 0.--6. 1. " CHANMAP7[6:0] ,Interrupt CHAN7 Mapping Control" group.long 0x88++0x3 line.long 0x0 "CHANCTRL2,VIM Interrupt Control Register 2" hexmask.long.byte 0x00 24.--30. 1. " CHANMAP8[6:0] ,Interrupt CHAN8 Mapping Control" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP9[6:0] ,Interrupt CHAN9 Mapping Control" hexmask.long.byte 0x00 8.--14. 1. " CHANMAP10[6:0] ,Interrupt CHAN10 Mapping Control" textline " " hexmask.long.byte 0x00 0.--6. 1. " CHANMAP11[6:0] ,Interrupt CHAN11 Mapping Control" group.long 0x8C++0x3 line.long 0x0 "CHANCTRL3,VIM Interrupt Control Register 3" hexmask.long.byte 0x00 24.--30. 1. " CHANMAP12[6:0] ,Interrupt CHAN12 Mapping Control" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP13[6:0] ,Interrupt CHAN13 Mapping Control" hexmask.long.byte 0x00 8.--14. 1. " CHANMAP14[6:0] ,Interrupt CHAN14 Mapping Control" textline " " hexmask.long.byte 0x00 0.--6. 1. " CHANMAP15[6:0] ,Interrupt CHAN15 Mapping Control" group.long 0x90++0x3 line.long 0x0 "CHANCTRL4,VIM Interrupt Control Register 4" hexmask.long.byte 0x00 24.--30. 1. " CHANMAP16[6:0] ,Interrupt CHAN16 Mapping Control" hexmask.long.byte 0x00 8.--14. 1. " CHANMAP18[6:0] ,Interrupt CHAN18 Mapping Control" hexmask.long.byte 0x00 0.--6. 1. " CHANMAP19[6:0] ,Interrupt CHAN19 Mapping Control" group.long 0x94++0x3 line.long 0x0 "CHANCTRL5,VIM Interrupt Control Register 5" hexmask.long.byte 0x00 24.--30. 1. " CHANMAP20[6:0] ,Interrupt CHAN20 Mapping Control" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP21[6:0] ,Interrupt CHAN21 Mapping Control" hexmask.long.byte 0x00 8.--14. 1. " CHANMAP22[6:0] ,Interrupt CHAN22 Mapping Control" textline " " hexmask.long.byte 0x00 0.--6. 1. " CHANMAP23[6:0] ,Interrupt CHAN23 Mapping Control" group.long 0x98++0x3 line.long 0x0 "CHANCTRL6,VIM Interrupt Control Register 6" hexmask.long.byte 0x00 24.--30. 1. " CHANMAP24[6:0] ,Interrupt CHAN24 Mapping Control" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP25[6:0] ,Interrupt CHAN25 Mapping Control" hexmask.long.byte 0x00 8.--14. 1. " CHANMAP26[6:0] ,Interrupt CHAN26 Mapping Control" textline " " hexmask.long.byte 0x00 0.--6. 1. " CHANMAP27[6:0] ,Interrupt CHAN27 Mapping Control" group.long 0x9C++0x3 line.long 0x0 "CHANCTRL7,VIM Interrupt Control Register 7" hexmask.long.byte 0x00 24.--30. 1. " CHANMAP28[6:0] ,Interrupt CHAN28 Mapping Control" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP29[6:0] ,Interrupt CHAN29 Mapping Control" hexmask.long.byte 0x00 8.--14. 1. " CHANMAP30[6:0] ,Interrupt CHAN30 Mapping Control" textline " " hexmask.long.byte 0x00 0.--6. 1. " CHANMAP31[6:0] ,Interrupt CHAN31 Mapping Control" group.long 0xA0++0x3 line.long 0x0 "CHANCTRL8,VIM Interrupt Control Register 8" hexmask.long.byte 0x00 24.--30. 1. " CHANMAP32[6:0] ,Interrupt CHAN32 Mapping Control" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP33[6:0] ,Interrupt CHAN33 Mapping Control" hexmask.long.byte 0x00 8.--14. 1. " CHANMAP34[6:0] ,Interrupt CHAN34 Mapping Control" textline " " hexmask.long.byte 0x00 0.--6. 1. " CHANMAP35[6:0] ,Interrupt CHAN35 Mapping Control" group.long 0xA4++0x3 line.long 0x0 "CHANCTRL9,VIM Interrupt Control Register 9" hexmask.long.byte 0x00 24.--30. 1. " CHANMAP36[6:0] ,Interrupt CHAN36 Mapping Control" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP37[6:0] ,Interrupt CHAN37 Mapping Control" hexmask.long.byte 0x00 8.--14. 1. " CHANMAP38[6:0] ,Interrupt CHAN38 Mapping Control" textline " " hexmask.long.byte 0x00 0.--6. 1. " CHANMAP39[6:0] ,Interrupt CHAN39 Mapping Control" group.long 0xA8++0x3 line.long 0x0 "CHANCTRL10,VIM Interrupt Control Register 10" hexmask.long.byte 0x00 24.--30. 1. " CHANMAP40[6:0] ,Interrupt CHAN40 Mapping Control" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP41[6:0] ,Interrupt CHAN41 Mapping Control" hexmask.long.byte 0x00 8.--14. 1. " CHANMAP42[6:0] ,Interrupt CHAN42 Mapping Control" textline " " hexmask.long.byte 0x00 0.--6. 1. " CHANMAP43[6:0] ,Interrupt CHAN43 Mapping Control" group.long 0xAC++0x3 line.long 0x0 "CHANCTRL11,VIM Interrupt Control Register 11" hexmask.long.byte 0x00 24.--30. 1. " CHANMAP44[6:0] ,Interrupt CHAN44 Mapping Control" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP45[6:0] ,Interrupt CHAN45 Mapping Control" hexmask.long.byte 0x00 8.--14. 1. " CHANMAP46[6:0] ,Interrupt CHAN46 Mapping Control" textline " " hexmask.long.byte 0x00 0.--6. 1. " CHANMAP47[6:0] ,Interrupt CHAN47 Mapping Control" group.long 0xB0++0x3 line.long 0x0 "CHANCTRL12,VIM Interrupt Control Register 12" hexmask.long.byte 0x00 24.--30. 1. " CHANMAP48[6:0] ,Interrupt CHAN48 Mapping Control" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP49[6:0] ,Interrupt CHAN49 Mapping Control" hexmask.long.byte 0x00 8.--14. 1. " CHANMAP50[6:0] ,Interrupt CHAN50 Mapping Control" textline " " hexmask.long.byte 0x00 0.--6. 1. " CHANMAP51[6:0] ,Interrupt CHAN51 Mapping Control" group.long 0xB4++0x3 line.long 0x0 "CHANCTRL13,VIM Interrupt Control Register 13" hexmask.long.byte 0x00 24.--30. 1. " CHANMAP52[6:0] ,Interrupt CHAN52 Mapping Control" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP53[6:0] ,Interrupt CHAN53 Mapping Control" hexmask.long.byte 0x00 8.--14. 1. " CHANMAP54[6:0] ,Interrupt CHAN54 Mapping Control" textline " " hexmask.long.byte 0x00 0.--6. 1. " CHANMAP55[6:0] ,Interrupt CHAN55 Mapping Control" group.long 0xB8++0x3 line.long 0x0 "CHANCTRL14,VIM Interrupt Control Register 14" hexmask.long.byte 0x00 24.--30. 1. " CHANMAP56[6:0] ,Interrupt CHAN56 Mapping Control" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP57[6:0] ,Interrupt CHAN57 Mapping Control" hexmask.long.byte 0x00 8.--14. 1. " CHANMAP58[6:0] ,Interrupt CHAN58 Mapping Control" textline " " hexmask.long.byte 0x00 0.--6. 1. " CHANMAP59[6:0] ,Interrupt CHAN59 Mapping Control" group.long 0xBC++0x3 line.long 0x0 "CHANCTRL15,VIM Interrupt Control Register 15" hexmask.long.byte 0x00 24.--30. 1. " CHANMAP60[6:0] ,Interrupt CHAN60 Mapping Control" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP61[6:0] ,Interrupt CHAN61 Mapping Control" hexmask.long.byte 0x00 8.--14. 1. " CHANMAP62[6:0] ,Interrupt CHAN62 Mapping Control" tree.end width 0xb tree.end tree "VIMPAR" base ad:0xFFFFFD00 width 10. group.long 0xEC++0x03 line.long 0x00 "PARFLG,Interrupt Vector Table Parity Flag Register" eventfld.long 0x00 0. " PARFLG ,Parity error flag" "No error,Error" group.long 0xF0++0x03 line.long 0x00 "PARCTL,Interrupt Vector Table Parity Control Register" bitfld.long 0x00 8. " TEST ,Parity bits mapping" "Not mapped,Mapped" bitfld.long 0x00 0.--3. " PARENA ,VIM parity enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" sif cpuis("TMS570LS3137-EP") if (((per.l.be(ad:0xFFFFFD00+0xEC))&0x01)==0x01) rgroup.long 0xF4++0x03 line.long 0x00 "ADDERR,Address Parity Error Register" hexmask.long.word 0x00 2.--8. 0x04 " ADDERR ,Address parity error" hexmask.long.byte 0x00 0.--1. 0x01 " WO ,Word offset" else rgroup.long 0xF4++0x03 line.long 0x00 "ADDERR,Address Parity Error Register" hexmask.long.byte 0x00 0.--1. 0x01 " WO ,Word Offset" endif else if (((per.long(ad:0xFFFFFD00+0xEC))&0x01)==0x01) rgroup.long 0xF4++0x03 line.long 0x00 "ADDERR,Address Parity Error Register" sif (cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10206-PGE")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS20206-PGE")||cpu()==("TMS570LS20206-ZWT")||cpu()==("TMS570LS20216-PGE")||cpu()==("TMS570LS20216-ZWT")||cpu()==("TMS570PSFC61")||cpu()==("TMS570LS2126")||cpu()==("TMS570LS2127")||cpu()==("TMS570LS2136")||cpu()==("TMS570LS2137")||cpu()==("TMS570LS2125-PGE")||cpu()==("TMS570LS2125-ZWT")||cpu()==("TMS570LS2135-PGE")||cpu()==("TMS570LS2135-ZWT")||cpu()==("TMS570LS2124-PGE")||cpu()==("TMS570LS2124-ZWT")||cpu()==("TMS570LS2134-PGE")||cpu()==("TMS570LS2134-ZWT")||cpu()==("TMS570LS3134-PGE")||cpu()==("TMS570LS3134-ZWT")||cpu()==("TMS570LS3135-PGE")||cpu()==("TMS570LS3135-ZWT")||cpu()==("TMS570LS3136")||cpu()==("TMS570LS3137-PGE")||cpu()==("TMS570LS3137-ZWT")||cpu()==("TMS570LS30336")) hexmask.long.tbyte 0x00 9.--31. 1. " VRO ,VIM RAM offset" endif hexmask.long.word 0x00 2.--8. 0x04 " ADDERR ,Address parity error" hexmask.long.byte 0x00 0.--1. 1. " WO ,Word offset" else rgroup.long 0xF4++0x03 line.long 0x00 "ADDERR,Address Parity Error Register" sif (cpu()==("TMS570PSFC61")||cpu()==("TMS570LS2126")||cpu()==("TMS570LS2127")||cpu()==("TMS570LS2136")||cpu()==("TMS570LS2137")||cpu()==("TMS570LS2125-PGE")||cpu()==("TMS570LS2125-ZWT")||cpu()==("TMS570LS2135-PGE")||cpu()==("TMS570LS2135-ZWT")||cpu()==("TMS570LS2124-PGE")||cpu()==("TMS570LS2124-ZWT")||cpu()==("TMS570LS2134-PGE")||cpu()==("TMS570LS2134-ZWT")||cpu()==("TMS570LS3134-PGE")||cpu()==("TMS570LS3134-ZWT")||cpu()==("TMS570LS3135-PGE")||cpu()==("TMS570LS3135-ZWT")||cpu()==("TMS570LS3136")||cpu()==("TMS570LS3137-PGE")||cpu()==("TMS570LS3137-ZWT")||cpu()==("TMS570LS30336")) hexmask.long.tbyte 0x00 9.--31. 1. " VRO ,VIM RAM offset" endif hexmask.long.byte 0x00 0.--1. 1. " WO ,Word offset" endif endif group.long 0xF8++0x03 line.long 0x00 "FBPARERR,Fall Back Address Parity Error Register" width 0x0B tree.end tree.end tree "POM (Parameter Overlay Module)" base ad:0xFFA04000 width 15. group.long 0x00++0x3 line.long 0x0 "GLBCTRL,Global Control Register" bitfld.long 0x00 0.--3. " ON/OFF ,POM Functionality" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" rgroup.long 0x04++0x3 line.long 0x0 "REV,Revision ID" hexmask.long.byte 0x00 30.--31. 0x1 " SCHEME ,Used to Destinguish Between Different ID Schemes" hexmask.long.word 0x00 16.--27. 0x1 " FUNC ,Indicates the SW Compatible Module Family" hexmask.long.byte 0x00 11.--15. 0x1 " RTL ,RTL Version Number" textline " " hexmask.long.byte 0x00 8.--10. 0x1 " MAJOR ,Major Revision Number" hexmask.long.byte 0x00 6.--7. 0x1 " CUSTOM ,Indicates a Device Specific Implementation" hexmask.long.byte 0x00 0.--5. 0x1 " MINOR ,Minor Revision Number" sif (cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10206-PGE")) group.long 0x08++0x3 line.long 0x0 "CLKCTRL,Clock Gate Control Register" bitfld.long 0x00 0. " DNM ,Reset state" "0,1" else group.long 0x08++0x3 line.long 0x0 "CLKCTRL,Clock Gate Control Register" bitfld.long 0x00 0. " CLKGATE_OFF ,Turn Clock Gating For Entire Module Off" "Enabled,Disabled" endif width 13. tree "Region Size/Start Address Registers" group.long 0x200++0x3 line.long 0x0 "PROGSTART0,Program Region Start Address Register 0" hexmask.long.tbyte 0x00 0.--21. 1. " STARTADDRESS ,Start Address of the Program Memory Region 0" group.long (0x200+0x04)++0x3 line.long 0x0 "OVLSTART0,Overlay Region Start Address Register 0" hexmask.long.tbyte 0x00 0.--21. 1. " STARTADDRESS ,Start Address of Overlay Memory Region 0" group.long (0x200+0x08)++0x3 line.long 0x0 "REGSIZE0,Region Size Register 0" bitfld.long 0x00 0.--3. " SIZE ,Region Size for Program Memory & Overlay Memory 0" "Disabled,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..." group.long 0x210++0x3 line.long 0x0 "PROGSTART1,Program Region Start Address Register 1" hexmask.long.tbyte 0x00 0.--21. 1. " STARTADDRESS ,Start Address of the Program Memory Region 1" group.long (0x210+0x04)++0x3 line.long 0x0 "OVLSTART1,Overlay Region Start Address Register 1" hexmask.long.tbyte 0x00 0.--21. 1. " STARTADDRESS ,Start Address of Overlay Memory Region 1" group.long (0x210+0x08)++0x3 line.long 0x0 "REGSIZE1,Region Size Register 1" bitfld.long 0x00 0.--3. " SIZE ,Region Size for Program Memory & Overlay Memory 1" "Disabled,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..." group.long 0x220++0x3 line.long 0x0 "PROGSTART2,Program Region Start Address Register 2" hexmask.long.tbyte 0x00 0.--21. 1. " STARTADDRESS ,Start Address of the Program Memory Region 2" group.long (0x220+0x04)++0x3 line.long 0x0 "OVLSTART2,Overlay Region Start Address Register 2" hexmask.long.tbyte 0x00 0.--21. 1. " STARTADDRESS ,Start Address of Overlay Memory Region 2" group.long (0x220+0x08)++0x3 line.long 0x0 "REGSIZE2,Region Size Register 2" bitfld.long 0x00 0.--3. " SIZE ,Region Size for Program Memory & Overlay Memory 2" "Disabled,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..." group.long 0x230++0x3 line.long 0x0 "PROGSTART3,Program Region Start Address Register 3" hexmask.long.tbyte 0x00 0.--21. 1. " STARTADDRESS ,Start Address of the Program Memory Region 3" group.long (0x230+0x04)++0x3 line.long 0x0 "OVLSTART3,Overlay Region Start Address Register 3" hexmask.long.tbyte 0x00 0.--21. 1. " STARTADDRESS ,Start Address of Overlay Memory Region 3" group.long (0x230+0x08)++0x3 line.long 0x0 "REGSIZE3,Region Size Register 3" bitfld.long 0x00 0.--3. " SIZE ,Region Size for Program Memory & Overlay Memory 3" "Disabled,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..." group.long 0x240++0x3 line.long 0x0 "PROGSTART4,Program Region Start Address Register 4" hexmask.long.tbyte 0x00 0.--21. 1. " STARTADDRESS ,Start Address of the Program Memory Region 4" group.long (0x240+0x04)++0x3 line.long 0x0 "OVLSTART4,Overlay Region Start Address Register 4" hexmask.long.tbyte 0x00 0.--21. 1. " STARTADDRESS ,Start Address of Overlay Memory Region 4" group.long (0x240+0x08)++0x3 line.long 0x0 "REGSIZE4,Region Size Register 4" bitfld.long 0x00 0.--3. " SIZE ,Region Size for Program Memory & Overlay Memory 4" "Disabled,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..." group.long 0x250++0x3 line.long 0x0 "PROGSTART5,Program Region Start Address Register 5" hexmask.long.tbyte 0x00 0.--21. 1. " STARTADDRESS ,Start Address of the Program Memory Region 5" group.long (0x250+0x04)++0x3 line.long 0x0 "OVLSTART5,Overlay Region Start Address Register 5" hexmask.long.tbyte 0x00 0.--21. 1. " STARTADDRESS ,Start Address of Overlay Memory Region 5" group.long (0x250+0x08)++0x3 line.long 0x0 "REGSIZE5,Region Size Register 5" bitfld.long 0x00 0.--3. " SIZE ,Region Size for Program Memory & Overlay Memory 5" "Disabled,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..." group.long 0x260++0x3 line.long 0x0 "PROGSTART6,Program Region Start Address Register 6" hexmask.long.tbyte 0x00 0.--21. 1. " STARTADDRESS ,Start Address of the Program Memory Region 6" group.long (0x260+0x04)++0x3 line.long 0x0 "OVLSTART6,Overlay Region Start Address Register 6" hexmask.long.tbyte 0x00 0.--21. 1. " STARTADDRESS ,Start Address of Overlay Memory Region 6" group.long (0x260+0x08)++0x3 line.long 0x0 "REGSIZE6,Region Size Register 6" bitfld.long 0x00 0.--3. " SIZE ,Region Size for Program Memory & Overlay Memory 6" "Disabled,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..." group.long 0x270++0x3 line.long 0x0 "PROGSTART7,Program Region Start Address Register 7" hexmask.long.tbyte 0x00 0.--21. 1. " STARTADDRESS ,Start Address of the Program Memory Region 7" group.long (0x270+0x04)++0x3 line.long 0x0 "OVLSTART7,Overlay Region Start Address Register 7" hexmask.long.tbyte 0x00 0.--21. 1. " STARTADDRESS ,Start Address of Overlay Memory Region 7" group.long (0x270+0x08)++0x3 line.long 0x0 "REGSIZE7,Region Size Register 7" bitfld.long 0x00 0.--3. " SIZE ,Region Size for Program Memory & Overlay Memory 7" "Disabled,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..." group.long 0x280++0x3 line.long 0x0 "PROGSTART8,Program Region Start Address Register 8" hexmask.long.tbyte 0x00 0.--21. 1. " STARTADDRESS ,Start Address of the Program Memory Region 8" group.long (0x280+0x04)++0x3 line.long 0x0 "OVLSTART8,Overlay Region Start Address Register 8" hexmask.long.tbyte 0x00 0.--21. 1. " STARTADDRESS ,Start Address of Overlay Memory Region 8" group.long (0x280+0x08)++0x3 line.long 0x0 "REGSIZE8,Region Size Register 8" bitfld.long 0x00 0.--3. " SIZE ,Region Size for Program Memory & Overlay Memory 8" "Disabled,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..." group.long 0x290++0x3 line.long 0x0 "PROGSTART9,Program Region Start Address Register 9" hexmask.long.tbyte 0x00 0.--21. 1. " STARTADDRESS ,Start Address of the Program Memory Region 9" group.long (0x290+0x04)++0x3 line.long 0x0 "OVLSTART9,Overlay Region Start Address Register 9" hexmask.long.tbyte 0x00 0.--21. 1. " STARTADDRESS ,Start Address of Overlay Memory Region 9" group.long (0x290+0x08)++0x3 line.long 0x0 "REGSIZE9,Region Size Register 9" bitfld.long 0x00 0.--3. " SIZE ,Region Size for Program Memory & Overlay Memory 9" "Disabled,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..." group.long 0x2A0++0x3 line.long 0x0 "PROGSTART10,Program Region Start Address Register 10" hexmask.long.tbyte 0x00 0.--21. 1. " STARTADDRESS ,Start Address of the Program Memory Region 10" group.long (0x2A0+0x04)++0x3 line.long 0x0 "OVLSTART10,Overlay Region Start Address Register 10" hexmask.long.tbyte 0x00 0.--21. 1. " STARTADDRESS ,Start Address of Overlay Memory Region 10" group.long (0x2A0+0x08)++0x3 line.long 0x0 "REGSIZE10,Region Size Register 10" bitfld.long 0x00 0.--3. " SIZE ,Region Size for Program Memory & Overlay Memory 10" "Disabled,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..." group.long 0x2B0++0x3 line.long 0x0 "PROGSTART11,Program Region Start Address Register 11" hexmask.long.tbyte 0x00 0.--21. 1. " STARTADDRESS ,Start Address of the Program Memory Region 11" group.long (0x2B0+0x04)++0x3 line.long 0x0 "OVLSTART11,Overlay Region Start Address Register 11" hexmask.long.tbyte 0x00 0.--21. 1. " STARTADDRESS ,Start Address of Overlay Memory Region 11" group.long (0x2B0+0x08)++0x3 line.long 0x0 "REGSIZE11,Region Size Register 11" bitfld.long 0x00 0.--3. " SIZE ,Region Size for Program Memory & Overlay Memory 11" "Disabled,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..." group.long 0x2C0++0x3 line.long 0x0 "PROGSTART12,Program Region Start Address Register 12" hexmask.long.tbyte 0x00 0.--21. 1. " STARTADDRESS ,Start Address of the Program Memory Region 12" group.long (0x2C0+0x04)++0x3 line.long 0x0 "OVLSTART12,Overlay Region Start Address Register 12" hexmask.long.tbyte 0x00 0.--21. 1. " STARTADDRESS ,Start Address of Overlay Memory Region 12" group.long (0x2C0+0x08)++0x3 line.long 0x0 "REGSIZE12,Region Size Register 12" bitfld.long 0x00 0.--3. " SIZE ,Region Size for Program Memory & Overlay Memory 12" "Disabled,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..." group.long 0x2D0++0x3 line.long 0x0 "PROGSTART13,Program Region Start Address Register 13" hexmask.long.tbyte 0x00 0.--21. 1. " STARTADDRESS ,Start Address of the Program Memory Region 13" group.long (0x2D0+0x04)++0x3 line.long 0x0 "OVLSTART13,Overlay Region Start Address Register 13" hexmask.long.tbyte 0x00 0.--21. 1. " STARTADDRESS ,Start Address of Overlay Memory Region 13" group.long (0x2D0+0x08)++0x3 line.long 0x0 "REGSIZE13,Region Size Register 13" bitfld.long 0x00 0.--3. " SIZE ,Region Size for Program Memory & Overlay Memory 13" "Disabled,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..." group.long 0x2E0++0x3 line.long 0x0 "PROGSTART14,Program Region Start Address Register 14" hexmask.long.tbyte 0x00 0.--21. 1. " STARTADDRESS ,Start Address of the Program Memory Region 14" group.long (0x2E0+0x04)++0x3 line.long 0x0 "OVLSTART14,Overlay Region Start Address Register 14" hexmask.long.tbyte 0x00 0.--21. 1. " STARTADDRESS ,Start Address of Overlay Memory Region 14" group.long (0x2E0+0x08)++0x3 line.long 0x0 "REGSIZE14,Region Size Register 14" bitfld.long 0x00 0.--3. " SIZE ,Region Size for Program Memory & Overlay Memory 14" "Disabled,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..." group.long 0x2F0++0x3 line.long 0x0 "PROGSTART15,Program Region Start Address Register 15" hexmask.long.tbyte 0x00 0.--21. 1. " STARTADDRESS ,Start Address of the Program Memory Region 15" group.long (0x2F0+0x04)++0x3 line.long 0x0 "OVLSTART15,Overlay Region Start Address Register 15" hexmask.long.tbyte 0x00 0.--21. 1. " STARTADDRESS ,Start Address of Overlay Memory Region 15" group.long (0x2F0+0x08)++0x3 line.long 0x0 "REGSIZE15,Region Size Register 15" bitfld.long 0x00 0.--3. " SIZE ,Region Size for Program Memory & Overlay Memory 15" "Disabled,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..." group.long 0x300++0x3 line.long 0x0 "PROGSTART16,Program Region Start Address Register 16" hexmask.long.tbyte 0x00 0.--21. 1. " STARTADDRESS ,Start Address of the Program Memory Region 16" group.long (0x300+0x04)++0x3 line.long 0x0 "OVLSTART16,Overlay Region Start Address Register 16" hexmask.long.tbyte 0x00 0.--21. 1. " STARTADDRESS ,Start Address of Overlay Memory Region 16" group.long (0x300+0x08)++0x3 line.long 0x0 "REGSIZE16,Region Size Register 16" bitfld.long 0x00 0.--3. " SIZE ,Region Size for Program Memory & Overlay Memory 16" "Disabled,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..." group.long 0x310++0x3 line.long 0x0 "PROGSTART17,Program Region Start Address Register 17" hexmask.long.tbyte 0x00 0.--21. 1. " STARTADDRESS ,Start Address of the Program Memory Region 17" group.long (0x310+0x04)++0x3 line.long 0x0 "OVLSTART17,Overlay Region Start Address Register 17" hexmask.long.tbyte 0x00 0.--21. 1. " STARTADDRESS ,Start Address of Overlay Memory Region 17" group.long (0x310+0x08)++0x3 line.long 0x0 "REGSIZE17,Region Size Register 17" bitfld.long 0x00 0.--3. " SIZE ,Region Size for Program Memory & Overlay Memory 17" "Disabled,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..." group.long 0x320++0x3 line.long 0x0 "PROGSTART18,Program Region Start Address Register 18" hexmask.long.tbyte 0x00 0.--21. 1. " STARTADDRESS ,Start Address of the Program Memory Region 18" group.long (0x320+0x04)++0x3 line.long 0x0 "OVLSTART18,Overlay Region Start Address Register 18" hexmask.long.tbyte 0x00 0.--21. 1. " STARTADDRESS ,Start Address of Overlay Memory Region 18" group.long (0x320+0x08)++0x3 line.long 0x0 "REGSIZE18,Region Size Register 18" bitfld.long 0x00 0.--3. " SIZE ,Region Size for Program Memory & Overlay Memory 18" "Disabled,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..." group.long 0x330++0x3 line.long 0x0 "PROGSTART19,Program Region Start Address Register 19" hexmask.long.tbyte 0x00 0.--21. 1. " STARTADDRESS ,Start Address of the Program Memory Region 19" group.long (0x330+0x04)++0x3 line.long 0x0 "OVLSTART19,Overlay Region Start Address Register 19" hexmask.long.tbyte 0x00 0.--21. 1. " STARTADDRESS ,Start Address of Overlay Memory Region 19" group.long (0x330+0x08)++0x3 line.long 0x0 "REGSIZE19,Region Size Register 19" bitfld.long 0x00 0.--3. " SIZE ,Region Size for Program Memory & Overlay Memory 19" "Disabled,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..." group.long 0x340++0x3 line.long 0x0 "PROGSTART20,Program Region Start Address Register 20" hexmask.long.tbyte 0x00 0.--21. 1. " STARTADDRESS ,Start Address of the Program Memory Region 20" group.long (0x340+0x04)++0x3 line.long 0x0 "OVLSTART20,Overlay Region Start Address Register 20" hexmask.long.tbyte 0x00 0.--21. 1. " STARTADDRESS ,Start Address of Overlay Memory Region 20" group.long (0x340+0x08)++0x3 line.long 0x0 "REGSIZE20,Region Size Register 20" bitfld.long 0x00 0.--3. " SIZE ,Region Size for Program Memory & Overlay Memory 20" "Disabled,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..." group.long 0x350++0x3 line.long 0x0 "PROGSTART21,Program Region Start Address Register 21" hexmask.long.tbyte 0x00 0.--21. 1. " STARTADDRESS ,Start Address of the Program Memory Region 21" group.long (0x350+0x04)++0x3 line.long 0x0 "OVLSTART21,Overlay Region Start Address Register 21" hexmask.long.tbyte 0x00 0.--21. 1. " STARTADDRESS ,Start Address of Overlay Memory Region 21" group.long (0x350+0x08)++0x3 line.long 0x0 "REGSIZE21,Region Size Register 21" bitfld.long 0x00 0.--3. " SIZE ,Region Size for Program Memory & Overlay Memory 21" "Disabled,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..." group.long 0x360++0x3 line.long 0x0 "PROGSTART22,Program Region Start Address Register 22" hexmask.long.tbyte 0x00 0.--21. 1. " STARTADDRESS ,Start Address of the Program Memory Region 22" group.long (0x360+0x04)++0x3 line.long 0x0 "OVLSTART22,Overlay Region Start Address Register 22" hexmask.long.tbyte 0x00 0.--21. 1. " STARTADDRESS ,Start Address of Overlay Memory Region 22" group.long (0x360+0x08)++0x3 line.long 0x0 "REGSIZE22,Region Size Register 22" bitfld.long 0x00 0.--3. " SIZE ,Region Size for Program Memory & Overlay Memory 22" "Disabled,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..." group.long 0x370++0x3 line.long 0x0 "PROGSTART23,Program Region Start Address Register 23" hexmask.long.tbyte 0x00 0.--21. 1. " STARTADDRESS ,Start Address of the Program Memory Region 23" group.long (0x370+0x04)++0x3 line.long 0x0 "OVLSTART23,Overlay Region Start Address Register 23" hexmask.long.tbyte 0x00 0.--21. 1. " STARTADDRESS ,Start Address of Overlay Memory Region 23" group.long (0x370+0x08)++0x3 line.long 0x0 "REGSIZE23,Region Size Register 23" bitfld.long 0x00 0.--3. " SIZE ,Region Size for Program Memory & Overlay Memory 23" "Disabled,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..." group.long 0x380++0x3 line.long 0x0 "PROGSTART24,Program Region Start Address Register 24" hexmask.long.tbyte 0x00 0.--21. 1. " STARTADDRESS ,Start Address of the Program Memory Region 24" group.long (0x380+0x04)++0x3 line.long 0x0 "OVLSTART24,Overlay Region Start Address Register 24" hexmask.long.tbyte 0x00 0.--21. 1. " STARTADDRESS ,Start Address of Overlay Memory Region 24" group.long (0x380+0x08)++0x3 line.long 0x0 "REGSIZE24,Region Size Register 24" bitfld.long 0x00 0.--3. " SIZE ,Region Size for Program Memory & Overlay Memory 24" "Disabled,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..." group.long 0x390++0x3 line.long 0x0 "PROGSTART25,Program Region Start Address Register 25" hexmask.long.tbyte 0x00 0.--21. 1. " STARTADDRESS ,Start Address of the Program Memory Region 25" group.long (0x390+0x04)++0x3 line.long 0x0 "OVLSTART25,Overlay Region Start Address Register 25" hexmask.long.tbyte 0x00 0.--21. 1. " STARTADDRESS ,Start Address of Overlay Memory Region 25" group.long (0x390+0x08)++0x3 line.long 0x0 "REGSIZE25,Region Size Register 25" bitfld.long 0x00 0.--3. " SIZE ,Region Size for Program Memory & Overlay Memory 25" "Disabled,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..." group.long 0x3A0++0x3 line.long 0x0 "PROGSTART26,Program Region Start Address Register 26" hexmask.long.tbyte 0x00 0.--21. 1. " STARTADDRESS ,Start Address of the Program Memory Region 26" group.long (0x3A0+0x04)++0x3 line.long 0x0 "OVLSTART26,Overlay Region Start Address Register 26" hexmask.long.tbyte 0x00 0.--21. 1. " STARTADDRESS ,Start Address of Overlay Memory Region 26" group.long (0x3A0+0x08)++0x3 line.long 0x0 "REGSIZE26,Region Size Register 26" bitfld.long 0x00 0.--3. " SIZE ,Region Size for Program Memory & Overlay Memory 26" "Disabled,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..." group.long 0x3B0++0x3 line.long 0x0 "PROGSTART27,Program Region Start Address Register 27" hexmask.long.tbyte 0x00 0.--21. 1. " STARTADDRESS ,Start Address of the Program Memory Region 27" group.long (0x3B0+0x04)++0x3 line.long 0x0 "OVLSTART27,Overlay Region Start Address Register 27" hexmask.long.tbyte 0x00 0.--21. 1. " STARTADDRESS ,Start Address of Overlay Memory Region 27" group.long (0x3B0+0x08)++0x3 line.long 0x0 "REGSIZE27,Region Size Register 27" bitfld.long 0x00 0.--3. " SIZE ,Region Size for Program Memory & Overlay Memory 27" "Disabled,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..." group.long 0x3C0++0x3 line.long 0x0 "PROGSTART28,Program Region Start Address Register 28" hexmask.long.tbyte 0x00 0.--21. 1. " STARTADDRESS ,Start Address of the Program Memory Region 28" group.long (0x3C0+0x04)++0x3 line.long 0x0 "OVLSTART28,Overlay Region Start Address Register 28" hexmask.long.tbyte 0x00 0.--21. 1. " STARTADDRESS ,Start Address of Overlay Memory Region 28" group.long (0x3C0+0x08)++0x3 line.long 0x0 "REGSIZE28,Region Size Register 28" bitfld.long 0x00 0.--3. " SIZE ,Region Size for Program Memory & Overlay Memory 28" "Disabled,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..." group.long 0x3D0++0x3 line.long 0x0 "PROGSTART29,Program Region Start Address Register 29" hexmask.long.tbyte 0x00 0.--21. 1. " STARTADDRESS ,Start Address of the Program Memory Region 29" group.long (0x3D0+0x04)++0x3 line.long 0x0 "OVLSTART29,Overlay Region Start Address Register 29" hexmask.long.tbyte 0x00 0.--21. 1. " STARTADDRESS ,Start Address of Overlay Memory Region 29" group.long (0x3D0+0x08)++0x3 line.long 0x0 "REGSIZE29,Region Size Register 29" bitfld.long 0x00 0.--3. " SIZE ,Region Size for Program Memory & Overlay Memory 29" "Disabled,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..." group.long 0x3E0++0x3 line.long 0x0 "PROGSTART30,Program Region Start Address Register 30" hexmask.long.tbyte 0x00 0.--21. 1. " STARTADDRESS ,Start Address of the Program Memory Region 30" group.long (0x3E0+0x04)++0x3 line.long 0x0 "OVLSTART30,Overlay Region Start Address Register 30" hexmask.long.tbyte 0x00 0.--21. 1. " STARTADDRESS ,Start Address of Overlay Memory Region 30" group.long (0x3E0+0x08)++0x3 line.long 0x0 "REGSIZE30,Region Size Register 30" bitfld.long 0x00 0.--3. " SIZE ,Region Size for Program Memory & Overlay Memory 30" "Disabled,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..." group.long 0x3F0++0x3 line.long 0x0 "PROGSTART31,Program Region Start Address Register 31" hexmask.long.tbyte 0x00 0.--21. 1. " STARTADDRESS ,Start Address of the Program Memory Region 31" group.long (0x3F0+0x04)++0x3 line.long 0x0 "OVLSTART31,Overlay Region Start Address Register 31" hexmask.long.tbyte 0x00 0.--21. 1. " STARTADDRESS ,Start Address of Overlay Memory Region 31" group.long (0x3F0+0x08)++0x3 line.long 0x0 "REGSIZE31,Region Size Register 31" bitfld.long 0x00 0.--3. " SIZE ,Region Size for Program Memory & Overlay Memory 31" "Disabled,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..." tree.end width 15. group.long 0xFA0++0x3 line.long 0x0 "CLAIMSET,Claim Set Register" setclrfld.long 0x00 1. 0x00 1. 0x04 1. " SET1_set/clr ,Claim Tag 1" "Not implemented,Implemented" textline " " setclrfld.long 0x00 0. 0x00 0. 0x04 0. " SET0_set/clr ,Claim Tag 0" "Not implemented,Implemented" rgroup.long 0xFCC++0x3 line.long 0x0 "DEVTYPE,Device Type Register" hexmask.long.byte 0x00 4.--7. 1. " SUB_TYPE ,Sub Type" hexmask.long.byte 0x00 0.--3. 1. " MAJOR_TYPE ,Major Type (Debug Control)" rgroup.long 0xFD0++0x3 line.long 0x0 "PERIPHERALID4,Peripheral ID 4 Register" hexmask.long.byte 0x00 4.--7. 1. " 4KB_COUNT ,Only 4 kB Implemented" hexmask.long.byte 0x00 0.--3. 1. " JEP_CONTINUATION_CODE ,JEP106 Code" rgroup.long 0xFE0++0x3 line.long 0x0 "PERIPHERALID0,Peripheral ID 0 Register" hexmask.long.byte 0x00 0.--7. 1. " PART_NUMBER ,Part Number" rgroup.long 0xFE4++0x3 line.long 0x0 "PERIPHERALID1,Peripheral ID 1 Register" hexmask.long.byte 0x00 4.--7. 1. " JEP106_IDENTITY_CODE ,Part of TI JEDEC Number" bitfld.long 0x00 0.--3. " PART_NUMBER ,Part Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xFE8++0x3 line.long 0x0 "PERIPHERALID2,Peripheral ID 2 Register" hexmask.long.byte 0x00 4.--7. 1. " REVISION ,Revision" bitfld.long 0x00 3. " JEDEC ,JEDEC Assigned Value" "Low,High" textline " " hexmask.long.byte 0x0 0.--2. 1. " JEP106_IDENTITY_CODE ,JEP106 Identity Code" rgroup.long 0xFF0++0x3 line.long 0x0 "COMPONENTID0,Component ID 0 Register" hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Preamble" rgroup.long 0xFF4++0x3 line.long 0x0 "COMPONENTID1,Component ID 1 Register" hexmask.long.byte 0x00 4.--7. 1. " COMPONENT_CLASS ,CoreSight Component" hexmask.long.byte 0x00 0.--3. 1. " PREAMBLE ,Preamble" rgroup.long 0xFF8++0x3 line.long 0x0 "COMPONENTID2,Component ID 2 Register" hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Preamble" group.long 0xFFC++0x3 line.long 0x0 "COMPONENTID3,Component ID 3 Register" hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Preamble" width 0xb tree.end tree "EMIF (Asynchronous External Memory Interface)" base ad:0xFFFFE800 width 6. rgroup.long 0x0++0x3 line.long 0x0 "RCSR,Revision Code and Status Register" bitfld.long 0x00 31. " BE ,Big Endian" "Little endian,Big endian" sif (cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10206-PGE")) bitfld.long 0x00 30. " FR , Full Rate" "Half rate,Full rate" endif hexmask.long.word 0x00 16.--29. 1. " MODULE_ID ,Module Identification" textline " " hexmask.long.byte 0x00 8.--15. 1. " MAJOR_REVISION ,Major Revision Number" hexmask.long.byte 0x00 0.--7. 1. " MINOR_REVISION ,Minor Revision Number" width 6. group.long 0x10++0x3 line.long 0x0 "A1CR,Asynchronous 1 Configuration Register (CS0 space)" bitfld.long 0x00 31. " SS ,Select strobe mode" "Normal,Strobe" bitfld.long 0x00 26.--29. " W_SETUP ,Write setup width in EMIF clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--25. " W_STROBE ,Write strobe width in EMIF clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 17.--19. " W_HOLD ,Write hold width in EMIF clock cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x00 13.--16. " R_SETUP ,Read setup width in EMIF clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7.--12. " R_STROBE ,Read strobe width in EMIF clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 4.--6. " R_HOLD ,Read hold width in EMIF clock cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x00 2.--3. " TA ,Minimum turn-around time" "0,1,2,3" bitfld.long 0x00 0.--1. " ASIZE ,Asynchronous data bus width" "8-bit,16-bit,?..." group.long 0x14++0x3 line.long 0x0 "A2CR,Asynchronous 2 Configuration Register (CS1 space)" bitfld.long 0x00 31. " SS ,Select strobe mode" "Normal,Strobe" bitfld.long 0x00 26.--29. " W_SETUP ,Write setup width in EMIF clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--25. " W_STROBE ,Write strobe width in EMIF clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 17.--19. " W_HOLD ,Write hold width in EMIF clock cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x00 13.--16. " R_SETUP ,Read setup width in EMIF clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7.--12. " R_STROBE ,Read strobe width in EMIF clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 4.--6. " R_HOLD ,Read hold width in EMIF clock cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x00 2.--3. " TA ,Minimum turn-around time" "0,1,2,3" bitfld.long 0x00 0.--1. " ASIZE ,Asynchronous data bus width" "8-bit,16-bit,?..." group.long 0x18++0x3 line.long 0x0 "A3CR,Asynchronous 3 Configuration Register (CS2 space)" bitfld.long 0x00 31. " SS ,Select strobe mode" "Normal,Strobe" bitfld.long 0x00 26.--29. " W_SETUP ,Write setup width in EMIF clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--25. " W_STROBE ,Write strobe width in EMIF clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 17.--19. " W_HOLD ,Write hold width in EMIF clock cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x00 13.--16. " R_SETUP ,Read setup width in EMIF clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7.--12. " R_STROBE ,Read strobe width in EMIF clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 4.--6. " R_HOLD ,Read hold width in EMIF clock cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x00 2.--3. " TA ,Minimum turn-around time" "0,1,2,3" bitfld.long 0x00 0.--1. " ASIZE ,Asynchronous data bus width" "8-bit,16-bit,?..." group.long 0x1C++0x3 line.long 0x0 "A4CR,Asynchronous 4 Configuration Register (CS3 space)" bitfld.long 0x00 31. " SS ,Select strobe mode" "Normal,Strobe" bitfld.long 0x00 26.--29. " W_SETUP ,Write setup width in EMIF clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--25. " W_STROBE ,Write strobe width in EMIF clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 17.--19. " W_HOLD ,Write hold width in EMIF clock cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x00 13.--16. " R_SETUP ,Read setup width in EMIF clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7.--12. " R_STROBE ,Read strobe width in EMIF clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 4.--6. " R_HOLD ,Read hold width in EMIF clock cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x00 2.--3. " TA ,Minimum turn-around time" "0,1,2,3" bitfld.long 0x00 0.--1. " ASIZE ,Asynchronous data bus width" "8-bit,16-bit,?..." sif (cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10206-PGE")) group.long 0x40++0x0F line.long 0x00 "EIRR, EMIF Interrupt Raw Register" eventfld.long 0x00 0. " AT , Asynchronous Timeout" "Not occurred,Occurred" line.long 0x04 "EIMR, EMIF Interrupt Mask Register" eventfld.long 0x04 0. " ATM , Asynchronous Timeout Masked" "Not generated,Generated" line.long 0x08 "EIMSR, EMIF Interrupt Mask Set Register" bitfld.long 0x08 0. " ATMSET , Asynchronous Timeout Mask Set" "Disabled,Enabled" line.long 0x0C "EIMCR, EMIF Interrupt Mask Clear Register" bitfld.long 0x0C 0. " ATMCLR , Asynchronous Timeout Mask Clear" "Disabled,Enabled" endif width 0xb tree.end tree "PCR (Peripheral Central Resource)" base ad:0xFFFFE000 width 12. tree "PCR Protection Registers" tree "PCR Memory Protection Registers" group.long 0x00++0x3 line.long 0x0 "PMPROTSET0,Set-only Register to Protect PCS Frames 0 to 31" setclrfld.long 0x00 31. 0x00 31. 0x10 31. " PCS31PROT_set/clr ,Peripheral Memory Frame Protection 31" "Not protected,Protected" setclrfld.long 0x00 30. 0x00 30. 0x10 30. " PCS30PROT_set/clr ,Peripheral Memory Frame Protection 30" "Not protected,Protected" textline " " setclrfld.long 0x00 29. 0x00 29. 0x10 29. " PCS29PROT_set/clr ,Peripheral Memory Frame Protection 29" "Not protected,Protected" setclrfld.long 0x00 28. 0x00 28. 0x10 28. " PCS28PROT_set/clr ,Peripheral Memory Frame Protection 28" "Not protected,Protected" textline " " setclrfld.long 0x00 27. 0x00 27. 0x10 27. " PCS27PROT_set/clr ,Peripheral Memory Frame Protection 27" "Not protected,Protected" setclrfld.long 0x00 26. 0x00 26. 0x10 26. " PCS26PROT_set/clr ,Peripheral Memory Frame Protection 26" "Not protected,Protected" textline " " setclrfld.long 0x00 25. 0x00 25. 0x10 25. " PCS25PROT_set/clr ,Peripheral Memory Frame Protection 25" "Not protected,Protected" setclrfld.long 0x00 24. 0x00 24. 0x10 24. " PCS24PROT_set/clr ,Peripheral Memory Frame Protection 24" "Not protected,Protected" textline " " setclrfld.long 0x00 23. 0x00 23. 0x10 23. " PCS23PROT_set/clr ,Peripheral Memory Frame Protection 23" "Not protected,Protected" setclrfld.long 0x00 22. 0x00 22. 0x10 22. " PCS22PROT_set/clr ,Peripheral Memory Frame Protection 22" "Not protected,Protected" textline " " setclrfld.long 0x00 21. 0x00 21. 0x10 21. " PCS21PROT_set/clr ,Peripheral Memory Frame Protection 21" "Not protected,Protected" setclrfld.long 0x00 20. 0x00 20. 0x10 20. " PCS20PROT_set/clr ,Peripheral Memory Frame Protection 20" "Not protected,Protected" textline " " setclrfld.long 0x00 19. 0x00 19. 0x10 19. " PCS19PROT_set/clr ,Peripheral Memory Frame Protection 19" "Not protected,Protected" setclrfld.long 0x00 18. 0x00 18. 0x10 18. " PCS18PROT_set/clr ,Peripheral Memory Frame Protection 18" "Not protected,Protected" textline " " setclrfld.long 0x00 17. 0x00 17. 0x10 17. " PCS17PROT_set/clr ,Peripheral Memory Frame Protection 17" "Not protected,Protected" setclrfld.long 0x00 16. 0x00 16. 0x10 16. " PCS16PROT_set/clr ,Peripheral Memory Frame Protection 16" "Not protected,Protected" textline " " setclrfld.long 0x00 15. 0x00 15. 0x10 15. " PCS15PROT_set/clr ,Peripheral Memory Frame Protection 15" "Not protected,Protected" setclrfld.long 0x00 14. 0x00 14. 0x10 14. " PCS14PROT_set/clr ,Peripheral Memory Frame Protection 14" "Not protected,Protected" textline " " setclrfld.long 0x00 13. 0x00 13. 0x10 13. " PCS13PROT_set/clr ,Peripheral Memory Frame Protection 13" "Not protected,Protected" setclrfld.long 0x00 12. 0x00 12. 0x10 12. " PCS12PROT_set/clr ,Peripheral Memory Frame Protection 12" "Not protected,Protected" textline " " setclrfld.long 0x00 11. 0x00 11. 0x10 11. " PCS11PROT_set/clr ,Peripheral Memory Frame Protection 11" "Not protected,Protected" setclrfld.long 0x00 10. 0x00 10. 0x10 10. " PCS10PROT_set/clr ,Peripheral Memory Frame Protection 10" "Not protected,Protected" textline " " setclrfld.long 0x00 9. 0x00 9. 0x10 9. " PCS9PROT_set/clr ,Peripheral Memory Frame Protection 9" "Not protected,Protected" setclrfld.long 0x00 8. 0x00 8. 0x10 8. " PCS8PROT_set/clr ,Peripheral Memory Frame Protection 8" "Not protected,Protected" textline " " setclrfld.long 0x00 7. 0x00 7. 0x10 7. " PCS7PROT_set/clr ,Peripheral Memory Frame Protection 7" "Not protected,Protected" setclrfld.long 0x00 6. 0x00 6. 0x10 6. " PCS6PROT_set/clr ,Peripheral Memory Frame Protection 6" "Not protected,Protected" textline " " setclrfld.long 0x00 5. 0x00 5. 0x10 5. " PCS5PROT_set/clr ,Peripheral Memory Frame Protection 5" "Not protected,Protected" setclrfld.long 0x00 4. 0x00 4. 0x10 4. " PCS4PROT_set/clr ,Peripheral Memory Frame Protection 4" "Not protected,Protected" textline " " setclrfld.long 0x00 3. 0x00 3. 0x10 3. " PCS3PROT_set/clr ,Peripheral Memory Frame Protection 3" "Not protected,Protected" setclrfld.long 0x00 2. 0x00 2. 0x10 2. " PCS2PROT_set/clr ,Peripheral Memory Frame Protection 2" "Not protected,Protected" textline " " setclrfld.long 0x00 1. 0x00 1. 0x10 1. " PCS1PROT_set/clr ,Peripheral Memory Frame Protection 1" "Not protected,Protected" setclrfld.long 0x00 0. 0x00 0. 0x10 0. " PCS0PROT_set/clr ,Peripheral Memory Frame Protection 0" "Not protected,Protected" group.long 0x04++0x3 line.long 0x0 "PMPROTSET1,Set-only Register to Protect PCS Frames 32 to 63" setclrfld.long 0x00 31. 0x00 31. 0x10 31. " PCS63PROT_set/clr ,Peripheral Memory Frame Protection 63" "Not protected,Protected" setclrfld.long 0x00 30. 0x00 30. 0x10 30. " PCS62PROT_set/clr ,Peripheral Memory Frame Protection 62" "Not protected,Protected" textline " " setclrfld.long 0x00 29. 0x00 29. 0x10 29. " PCS61PROT_set/clr ,Peripheral Memory Frame Protection 61" "Not protected,Protected" setclrfld.long 0x00 28. 0x00 28. 0x10 28. " PCS60PROT_set/clr ,Peripheral Memory Frame Protection 60" "Not protected,Protected" textline " " setclrfld.long 0x00 27. 0x00 27. 0x10 27. " PCS59PROT_set/clr ,Peripheral Memory Frame Protection 59" "Not protected,Protected" setclrfld.long 0x00 26. 0x00 26. 0x10 26. " PCS58PROT_set/clr ,Peripheral Memory Frame Protection 58" "Not protected,Protected" textline " " setclrfld.long 0x00 25. 0x00 25. 0x10 25. " PCS57PROT_set/clr ,Peripheral Memory Frame Protection 57" "Not protected,Protected" setclrfld.long 0x00 24. 0x00 24. 0x10 24. " PCS56PROT_set/clr ,Peripheral Memory Frame Protection 56" "Not protected,Protected" textline " " setclrfld.long 0x00 23. 0x00 23. 0x10 23. " PCS55PROT_set/clr ,Peripheral Memory Frame Protection 55" "Not protected,Protected" setclrfld.long 0x00 22. 0x00 22. 0x10 22. " PCS54PROT_set/clr ,Peripheral Memory Frame Protection 54" "Not protected,Protected" textline " " setclrfld.long 0x00 21. 0x00 21. 0x10 21. " PCS53PROT_set/clr ,Peripheral Memory Frame Protection 53" "Not protected,Protected" setclrfld.long 0x00 20. 0x00 20. 0x10 20. " PCS52PROT_set/clr ,Peripheral Memory Frame Protection 52" "Not protected,Protected" textline " " setclrfld.long 0x00 19. 0x00 19. 0x10 19. " PCS51PROT_set/clr ,Peripheral Memory Frame Protection 51" "Not protected,Protected" setclrfld.long 0x00 18. 0x00 18. 0x10 18. " PCS50PROT_set/clr ,Peripheral Memory Frame Protection 50" "Not protected,Protected" textline " " setclrfld.long 0x00 17. 0x00 17. 0x10 17. " PCS49PROT_set/clr ,Peripheral Memory Frame Protection 49" "Not protected,Protected" setclrfld.long 0x00 16. 0x00 16. 0x10 16. " PCS48PROT_set/clr ,Peripheral Memory Frame Protection 48" "Not protected,Protected" textline " " setclrfld.long 0x00 15. 0x00 15. 0x10 15. " PCS47PROT_set/clr ,Peripheral Memory Frame Protection 47" "Not protected,Protected" setclrfld.long 0x00 14. 0x00 14. 0x10 14. " PCS46PROT_set/clr ,Peripheral Memory Frame Protection 46" "Not protected,Protected" textline " " setclrfld.long 0x00 13. 0x00 13. 0x10 13. " PCS45PROT_set/clr ,Peripheral Memory Frame Protection 45" "Not protected,Protected" setclrfld.long 0x00 12. 0x00 12. 0x10 12. " PCS44PROT_set/clr ,Peripheral Memory Frame Protection 44" "Not protected,Protected" textline " " setclrfld.long 0x00 11. 0x00 11. 0x10 11. " PCS43PROT_set/clr ,Peripheral Memory Frame Protection 43" "Not protected,Protected" setclrfld.long 0x00 10. 0x00 10. 0x10 10. " PCS42PROT_set/clr ,Peripheral Memory Frame Protection 42" "Not protected,Protected" textline " " setclrfld.long 0x00 9. 0x00 9. 0x10 9. " PCS41PROT_set/clr ,Peripheral Memory Frame Protection 41" "Not protected,Protected" setclrfld.long 0x00 8. 0x00 8. 0x10 8. " PCS40PROT_set/clr ,Peripheral Memory Frame Protection 40" "Not protected,Protected" textline " " setclrfld.long 0x00 7. 0x00 7. 0x10 7. " PCS39PROT_set/clr ,Peripheral Memory Frame Protection 39" "Not protected,Protected" setclrfld.long 0x00 6. 0x00 6. 0x10 6. " PCS38PROT_set/clr ,Peripheral Memory Frame Protection 38" "Not protected,Protected" textline " " setclrfld.long 0x00 5. 0x00 5. 0x10 5. " PCS37PROT_set/clr ,Peripheral Memory Frame Protection 37" "Not protected,Protected" setclrfld.long 0x00 4. 0x00 4. 0x10 4. " PCS36PROT_set/clr ,Peripheral Memory Frame Protection 36" "Not protected,Protected" textline " " setclrfld.long 0x00 3. 0x00 3. 0x10 3. " PCS35PROT_set/clr ,Peripheral Memory Frame Protection 35" "Not protected,Protected" setclrfld.long 0x00 2. 0x00 2. 0x10 2. " PCS34PROT_set/clr ,Peripheral Memory Frame Protection 34" "Not protected,Protected" textline " " setclrfld.long 0x00 1. 0x00 1. 0x10 1. " PCS33PROT_set/clr ,Peripheral Memory Frame Protection 33" "Not protected,Protected" setclrfld.long 0x00 0. 0x00 0. 0x10 0. " PCS32PROT_set/clr ,Peripheral Memory Frame Protection 32" "Not protected,Protected" tree.end width 12. textline " " group.long 0x20++0x3 line.long 0x0 "PPROTSET0,Set-only Register to Protect the 32 Quadrants of PS0 to PS7" setclrfld.long 0x00 31. 0x00 31. 0x20 31. " PCS7QUAD3PROT_set/clr ,Peripheral Protection 7 3" "Not protected,Protected" textline " " setclrfld.long 0x00 30. 0x00 30. 0x20 30. " PCS7QUAD2PROT_set/clr ,Peripheral Protection 7 2" "Not protected,Protected" textline " " setclrfld.long 0x00 29. 0x00 29. 0x20 29. " PCS7QUAD1PROT_set/clr ,Peripheral Protection 7 1" "Not protected,Protected" textline " " setclrfld.long 0x00 28. 0x00 28. 0x20 28. " PCS7QUAD0PROT_set/clr ,Peripheral Protection 7 0" "Not protected,Protected" textline " " setclrfld.long 0x00 27. 0x00 27. 0x20 27. " PCS6QUAD3PROT_set/clr ,Peripheral Protection 6 3" "Not protected,Protected" textline " " setclrfld.long 0x00 26. 0x00 26. 0x20 26. " PCS6QUAD2PROT_set/clr ,Peripheral Protection 6 2" "Not protected,Protected" textline " " setclrfld.long 0x00 25. 0x00 25. 0x20 25. " PCS6QUAD1PROT_set/clr ,Peripheral Protection 6 1" "Not protected,Protected" textline " " setclrfld.long 0x00 24. 0x00 24. 0x20 24. " PCS6QUAD0PROT_set/clr ,Peripheral Protection 6 0" "Not protected,Protected" textline " " setclrfld.long 0x00 23. 0x00 23. 0x20 23. " PCS5QUAD3PROT_set/clr ,Peripheral Protection 5 3" "Not protected,Protected" textline " " setclrfld.long 0x00 22. 0x00 22. 0x20 22. " PCS5QUAD2PROT_set/clr ,Peripheral Protection 5 2" "Not protected,Protected" textline " " setclrfld.long 0x00 21. 0x00 21. 0x20 21. " PCS5QUAD1PROT_set/clr ,Peripheral Protection 5 1" "Not protected,Protected" textline " " setclrfld.long 0x00 20. 0x00 20. 0x20 20. " PCS5QUAD0PROT_set/clr ,Peripheral Protection 5 0" "Not protected,Protected" textline " " setclrfld.long 0x00 19. 0x00 19. 0x20 19. " PCS4QUAD3PROT_set/clr ,Peripheral Protection 4 3" "Not protected,Protected" textline " " setclrfld.long 0x00 18. 0x00 18. 0x20 18. " PCS4QUAD2PROT_set/clr ,Peripheral Protection 4 2" "Not protected,Protected" textline " " setclrfld.long 0x00 17. 0x00 17. 0x20 17. " PCS4QUAD1PROT_set/clr ,Peripheral Protection 4 1" "Not protected,Protected" textline " " setclrfld.long 0x00 16. 0x00 16. 0x20 16. " PCS4QUAD0PROT_set/clr ,Peripheral Protection 4 0" "Not protected,Protected" textline " " setclrfld.long 0x00 15. 0x00 15. 0x20 15. " PCS3QUAD3PROT_set/clr ,Peripheral Protection 3 3" "Not protected,Protected" textline " " setclrfld.long 0x00 14. 0x00 14. 0x20 14. " PCS3QUAD2PROT_set/clr ,Peripheral Protection 3 2" "Not protected,Protected" textline " " setclrfld.long 0x00 13. 0x00 13. 0x20 13. " PCS3QUAD1PROT_set/clr ,Peripheral Protection 3 1" "Not protected,Protected" textline " " setclrfld.long 0x00 12. 0x00 12. 0x20 12. " PCS3QUAD0PROT_set/clr ,Peripheral Protection 3 0" "Not protected,Protected" textline " " setclrfld.long 0x00 11. 0x00 11. 0x20 11. " PCS2QUAD3PROT_set/clr ,Peripheral Protection 2 3" "Not protected,Protected" textline " " setclrfld.long 0x00 10. 0x00 10. 0x20 10. " PCS2QUAD2PROT_set/clr ,Peripheral Protection 2 2" "Not protected,Protected" textline " " setclrfld.long 0x00 9. 0x00 9. 0x20 9. " PCS2QUAD1PROT_set/clr ,Peripheral Protection 2 1" "Not protected,Protected" textline " " setclrfld.long 0x00 8. 0x00 8. 0x20 8. " PCS2QUAD0PROT_set/clr ,Peripheral Protection 2 0" "Not protected,Protected" textline " " setclrfld.long 0x00 7. 0x00 7. 0x20 7. " PCS1QUAD3PROT_set/clr ,Peripheral Protection 1 3" "Not protected,Protected" textline " " setclrfld.long 0x00 6. 0x00 6. 0x20 6. " PCS1QUAD2PROT_set/clr ,Peripheral Protection 1 2" "Not protected,Protected" textline " " setclrfld.long 0x00 5. 0x00 5. 0x20 5. " PCS1QUAD1PROT_set/clr ,Peripheral Protection 1 1" "Not protected,Protected" textline " " setclrfld.long 0x00 4. 0x00 4. 0x20 4. " PCS1QUAD0PROT_set/clr ,Peripheral Protection 1 0" "Not protected,Protected" textline " " setclrfld.long 0x00 3. 0x00 3. 0x20 3. " PCS0QUAD3PROT_set/clr ,Peripheral Protection 0 3" "Not protected,Protected" textline " " setclrfld.long 0x00 2. 0x00 2. 0x20 2. " PCS0QUAD2PROT_set/clr ,Peripheral Protection 0 2" "Not protected,Protected" textline " " setclrfld.long 0x00 1. 0x00 1. 0x20 1. " PCS0QUAD1PROT_set/clr ,Peripheral Protection 0 1" "Not protected,Protected" textline " " setclrfld.long 0x00 0. 0x00 0. 0x20 0. " PCS0QUAD0PROT_set/clr ,Peripheral Protection 0 0" "Not protected,Protected" group.long 0x24++0x3 line.long 0x0 "PPROTSET1,Set-only Register to Protect the 32 Quadrants of PS8 to PS15" setclrfld.long 0x00 31. 0x00 31. 0x20 31. " PCS15QUAD3PROT_set/clr ,Peripheral Protection 15 3" "Not protected,Protected" textline " " setclrfld.long 0x00 30. 0x00 30. 0x20 30. " PCS15QUAD2PROT_set/clr ,Peripheral Protection 15 2" "Not protected,Protected" textline " " setclrfld.long 0x00 29. 0x00 29. 0x20 29. " PCS15QUAD1PROT_set/clr ,Peripheral Protection 15 1" "Not protected,Protected" textline " " setclrfld.long 0x00 28. 0x00 28. 0x20 28. " PCS15QUAD0PROT_set/clr ,Peripheral Protection 15 0" "Not protected,Protected" textline " " setclrfld.long 0x00 27. 0x00 27. 0x20 27. " PCS14QUAD3PROT_set/clr ,Peripheral Protection 14 3" "Not protected,Protected" textline " " setclrfld.long 0x00 26. 0x00 26. 0x20 26. " PCS14QUAD2PROT_set/clr ,Peripheral Protection 14 2" "Not protected,Protected" textline " " setclrfld.long 0x00 25. 0x00 25. 0x20 25. " PCS14QUAD1PROT_set/clr ,Peripheral Protection 14 1" "Not protected,Protected" textline " " setclrfld.long 0x00 24. 0x00 24. 0x20 24. " PCS14QUAD0PROT_set/clr ,Peripheral Protection 14 0" "Not protected,Protected" textline " " setclrfld.long 0x00 23. 0x00 23. 0x20 23. " PCS13QUAD3PROT_set/clr ,Peripheral Protection 13 3" "Not protected,Protected" textline " " setclrfld.long 0x00 22. 0x00 22. 0x20 22. " PCS13QUAD2PROT_set/clr ,Peripheral Protection 13 2" "Not protected,Protected" textline " " setclrfld.long 0x00 21. 0x00 21. 0x20 21. " PCS13QUAD1PROT_set/clr ,Peripheral Protection 13 1" "Not protected,Protected" textline " " setclrfld.long 0x00 20. 0x00 20. 0x20 20. " PCS13QUAD0PROT_set/clr ,Peripheral Protection 13 0" "Not protected,Protected" textline " " setclrfld.long 0x00 19. 0x00 19. 0x20 19. " PCS12QUAD3PROT_set/clr ,Peripheral Protection 12 3" "Not protected,Protected" textline " " setclrfld.long 0x00 18. 0x00 18. 0x20 18. " PCS12QUAD2PROT_set/clr ,Peripheral Protection 12 2" "Not protected,Protected" textline " " setclrfld.long 0x00 17. 0x00 17. 0x20 17. " PCS12QUAD1PROT_set/clr ,Peripheral Protection 12 1" "Not protected,Protected" textline " " setclrfld.long 0x00 16. 0x00 16. 0x20 16. " PCS12QUAD0PROT_set/clr ,Peripheral Protection 12 0" "Not protected,Protected" textline " " setclrfld.long 0x00 15. 0x00 15. 0x20 15. " PCS11QUAD3PROT_set/clr ,Peripheral Protection 11 3" "Not protected,Protected" textline " " setclrfld.long 0x00 14. 0x00 14. 0x20 14. " PCS11QUAD2PROT_set/clr ,Peripheral Protection 11 2" "Not protected,Protected" textline " " setclrfld.long 0x00 13. 0x00 13. 0x20 13. " PCS11QUAD1PROT_set/clr ,Peripheral Protection 11 1" "Not protected,Protected" textline " " setclrfld.long 0x00 12. 0x00 12. 0x20 12. " PCS11QUAD0PROT_set/clr ,Peripheral Protection 11 0" "Not protected,Protected" textline " " setclrfld.long 0x00 11. 0x00 11. 0x20 11. " PCS10QUAD3PROT_set/clr ,Peripheral Protection 10 3" "Not protected,Protected" textline " " setclrfld.long 0x00 10. 0x00 10. 0x20 10. " PCS10QUAD2PROT_set/clr ,Peripheral Protection 10 2" "Not protected,Protected" textline " " setclrfld.long 0x00 9. 0x00 9. 0x20 9. " PCS10QUAD1PROT_set/clr ,Peripheral Protection 10 1" "Not protected,Protected" textline " " setclrfld.long 0x00 8. 0x00 8. 0x20 8. " PCS10QUAD0PROT_set/clr ,Peripheral Protection 10 0" "Not protected,Protected" textline " " setclrfld.long 0x00 7. 0x00 7. 0x20 7. " PCS9QUAD3PROT_set/clr ,Peripheral Protection 9 3" "Not protected,Protected" textline " " setclrfld.long 0x00 6. 0x00 6. 0x20 6. " PCS9QUAD2PROT_set/clr ,Peripheral Protection 9 2" "Not protected,Protected" textline " " setclrfld.long 0x00 5. 0x00 5. 0x20 5. " PCS9QUAD1PROT_set/clr ,Peripheral Protection 9 1" "Not protected,Protected" textline " " setclrfld.long 0x00 4. 0x00 4. 0x20 4. " PCS9QUAD0PROT_set/clr ,Peripheral Protection 9 0" "Not protected,Protected" textline " " setclrfld.long 0x00 3. 0x00 3. 0x20 3. " PCS8QUAD3PROT_set/clr ,Peripheral Protection 8 3" "Not protected,Protected" textline " " setclrfld.long 0x00 2. 0x00 2. 0x20 2. " PCS8QUAD2PROT_set/clr ,Peripheral Protection 8 2" "Not protected,Protected" textline " " setclrfld.long 0x00 1. 0x00 1. 0x20 1. " PCS8QUAD1PROT_set/clr ,Peripheral Protection 8 1" "Not protected,Protected" textline " " setclrfld.long 0x00 0. 0x00 0. 0x20 0. " PCS8QUAD0PROT_set/clr ,Peripheral Protection 8 0" "Not protected,Protected" group.long 0x28++0x3 line.long 0x0 "PPROTSET2,Set-only Register to Protect the 32 Quadrants of PS16 to PS23" setclrfld.long 0x00 31. 0x00 31. 0x20 31. " PCS23QUAD3PROT_set/clr ,Peripheral Protection 23 3" "Not protected,Protected" textline " " setclrfld.long 0x00 30. 0x00 30. 0x20 30. " PCS23QUAD2PROT_set/clr ,Peripheral Protection 23 2" "Not protected,Protected" textline " " setclrfld.long 0x00 29. 0x00 29. 0x20 29. " PCS23QUAD1PROT_set/clr ,Peripheral Protection 23 1" "Not protected,Protected" textline " " setclrfld.long 0x00 28. 0x00 28. 0x20 28. " PCS23QUAD0PROT_set/clr ,Peripheral Protection 23 0" "Not protected,Protected" textline " " setclrfld.long 0x00 27. 0x00 27. 0x20 27. " PCS22QUAD3PROT_set/clr ,Peripheral Protection 22 3" "Not protected,Protected" textline " " setclrfld.long 0x00 26. 0x00 26. 0x20 26. " PCS22QUAD2PROT_set/clr ,Peripheral Protection 22 2" "Not protected,Protected" textline " " setclrfld.long 0x00 25. 0x00 25. 0x20 25. " PCS22QUAD1PROT_set/clr ,Peripheral Protection 22 1" "Not protected,Protected" textline " " setclrfld.long 0x00 24. 0x00 24. 0x20 24. " PCS22QUAD0PROT_set/clr ,Peripheral Protection 22 0" "Not protected,Protected" textline " " setclrfld.long 0x00 23. 0x00 23. 0x20 23. " PCS21QUAD3PROT_set/clr ,Peripheral Protection 21 3" "Not protected,Protected" textline " " setclrfld.long 0x00 22. 0x00 22. 0x20 22. " PCS21QUAD2PROT_set/clr ,Peripheral Protection 21 2" "Not protected,Protected" textline " " setclrfld.long 0x00 21. 0x00 21. 0x20 21. " PCS21QUAD1PROT_set/clr ,Peripheral Protection 21 1" "Not protected,Protected" textline " " setclrfld.long 0x00 20. 0x00 20. 0x20 20. " PCS21QUAD0PROT_set/clr ,Peripheral Protection 21 0" "Not protected,Protected" textline " " setclrfld.long 0x00 19. 0x00 19. 0x20 19. " PCS20QUAD3PROT_set/clr ,Peripheral Protection 20 3" "Not protected,Protected" textline " " setclrfld.long 0x00 18. 0x00 18. 0x20 18. " PCS20QUAD2PROT_set/clr ,Peripheral Protection 20 2" "Not protected,Protected" textline " " setclrfld.long 0x00 17. 0x00 17. 0x20 17. " PCS20QUAD1PROT_set/clr ,Peripheral Protection 20 1" "Not protected,Protected" textline " " setclrfld.long 0x00 16. 0x00 16. 0x20 16. " PCS20QUAD0PROT_set/clr ,Peripheral Protection 20 0" "Not protected,Protected" textline " " setclrfld.long 0x00 15. 0x00 15. 0x20 15. " PCS19QUAD3PROT_set/clr ,Peripheral Protection 19 3" "Not protected,Protected" textline " " setclrfld.long 0x00 14. 0x00 14. 0x20 14. " PCS19QUAD2PROT_set/clr ,Peripheral Protection 19 2" "Not protected,Protected" textline " " setclrfld.long 0x00 13. 0x00 13. 0x20 13. " PCS19QUAD1PROT_set/clr ,Peripheral Protection 19 1" "Not protected,Protected" textline " " setclrfld.long 0x00 12. 0x00 12. 0x20 12. " PCS19QUAD0PROT_set/clr ,Peripheral Protection 19 0" "Not protected,Protected" textline " " setclrfld.long 0x00 11. 0x00 11. 0x20 11. " PCS18QUAD3PROT_set/clr ,Peripheral Protection 18 3" "Not protected,Protected" textline " " setclrfld.long 0x00 10. 0x00 10. 0x20 10. " PCS18QUAD2PROT_set/clr ,Peripheral Protection 18 2" "Not protected,Protected" textline " " setclrfld.long 0x00 9. 0x00 9. 0x20 9. " PCS18QUAD1PROT_set/clr ,Peripheral Protection 18 1" "Not protected,Protected" textline " " setclrfld.long 0x00 8. 0x00 8. 0x20 8. " PCS18QUAD0PROT_set/clr ,Peripheral Protection 18 0" "Not protected,Protected" textline " " setclrfld.long 0x00 7. 0x00 7. 0x20 7. " PCS17QUAD3PROT_set/clr ,Peripheral Protection 17 3" "Not protected,Protected" textline " " setclrfld.long 0x00 6. 0x00 6. 0x20 6. " PCS17QUAD2PROT_set/clr ,Peripheral Protection 17 2" "Not protected,Protected" textline " " setclrfld.long 0x00 5. 0x00 5. 0x20 5. " PCS17QUAD1PROT_set/clr ,Peripheral Protection 17 1" "Not protected,Protected" textline " " setclrfld.long 0x00 4. 0x00 4. 0x20 4. " PCS17QUAD0PROT_set/clr ,Peripheral Protection 17 0" "Not protected,Protected" textline " " setclrfld.long 0x00 3. 0x00 3. 0x20 3. " PCS16QUAD3PROT_set/clr ,Peripheral Protection 16 3" "Not protected,Protected" textline " " setclrfld.long 0x00 2. 0x00 2. 0x20 2. " PCS16QUAD2PROT_set/clr ,Peripheral Protection 16 2" "Not protected,Protected" textline " " setclrfld.long 0x00 1. 0x00 1. 0x20 1. " PCS16QUAD1PROT_set/clr ,Peripheral Protection 16 1" "Not protected,Protected" textline " " setclrfld.long 0x00 0. 0x00 0. 0x20 0. " PCS16QUAD0PROT_set/clr ,Peripheral Protection 16 0" "Not protected,Protected" group.long 0x2C++0x3 line.long 0x0 "PPROTSET3,Set-only Register to Protect the 32 Quadrants of PS24 to PS31" setclrfld.long 0x00 31. 0x00 31. 0x20 31. " PCS31QUAD3PROT_set/clr ,Peripheral Protection 31 3" "Not protected,Protected" textline " " setclrfld.long 0x00 30. 0x00 30. 0x20 30. " PCS31QUAD2PROT_set/clr ,Peripheral Protection 31 2" "Not protected,Protected" textline " " setclrfld.long 0x00 29. 0x00 29. 0x20 29. " PCS31QUAD1PROT_set/clr ,Peripheral Protection 31 1" "Not protected,Protected" textline " " setclrfld.long 0x00 28. 0x00 28. 0x20 28. " PCS31QUAD0PROT_set/clr ,Peripheral Protection 31 0" "Not protected,Protected" textline " " setclrfld.long 0x00 27. 0x00 27. 0x20 27. " PCS30QUAD3PROT_set/clr ,Peripheral Protection 30 3" "Not protected,Protected" textline " " setclrfld.long 0x00 26. 0x00 26. 0x20 26. " PCS30QUAD2PROT_set/clr ,Peripheral Protection 30 2" "Not protected,Protected" textline " " setclrfld.long 0x00 25. 0x00 25. 0x20 25. " PCS30QUAD1PROT_set/clr ,Peripheral Protection 30 1" "Not protected,Protected" textline " " setclrfld.long 0x00 24. 0x00 24. 0x20 24. " PCS30QUAD0PROT_set/clr ,Peripheral Protection 30 0" "Not protected,Protected" textline " " setclrfld.long 0x00 23. 0x00 23. 0x20 23. " PCS29QUAD3PROT_set/clr ,Peripheral Protection 29 3" "Not protected,Protected" textline " " setclrfld.long 0x00 22. 0x00 22. 0x20 22. " PCS29QUAD2PROT_set/clr ,Peripheral Protection 29 2" "Not protected,Protected" textline " " setclrfld.long 0x00 21. 0x00 21. 0x20 21. " PCS29QUAD1PROT_set/clr ,Peripheral Protection 29 1" "Not protected,Protected" textline " " setclrfld.long 0x00 20. 0x00 20. 0x20 20. " PCS29QUAD0PROT_set/clr ,Peripheral Protection 29 0" "Not protected,Protected" textline " " setclrfld.long 0x00 19. 0x00 19. 0x20 19. " PCS28QUAD3PROT_set/clr ,Peripheral Protection 28 3" "Not protected,Protected" textline " " setclrfld.long 0x00 18. 0x00 18. 0x20 18. " PCS28QUAD2PROT_set/clr ,Peripheral Protection 28 2" "Not protected,Protected" textline " " setclrfld.long 0x00 17. 0x00 17. 0x20 17. " PCS28QUAD1PROT_set/clr ,Peripheral Protection 28 1" "Not protected,Protected" textline " " setclrfld.long 0x00 16. 0x00 16. 0x20 16. " PCS28QUAD0PROT_set/clr ,Peripheral Protection 28 0" "Not protected,Protected" textline " " setclrfld.long 0x00 15. 0x00 15. 0x20 15. " PCS27QUAD3PROT_set/clr ,Peripheral Protection 27 3" "Not protected,Protected" textline " " setclrfld.long 0x00 14. 0x00 14. 0x20 14. " PCS27QUAD2PROT_set/clr ,Peripheral Protection 27 2" "Not protected,Protected" textline " " setclrfld.long 0x00 13. 0x00 13. 0x20 13. " PCS27QUAD1PROT_set/clr ,Peripheral Protection 27 1" "Not protected,Protected" textline " " setclrfld.long 0x00 12. 0x00 12. 0x20 12. " PCS27QUAD0PROT_set/clr ,Peripheral Protection 27 0" "Not protected,Protected" textline " " setclrfld.long 0x00 11. 0x00 11. 0x20 11. " PCS26QUAD3PROT_set/clr ,Peripheral Protection 26 3" "Not protected,Protected" textline " " setclrfld.long 0x00 10. 0x00 10. 0x20 10. " PCS26QUAD2PROT_set/clr ,Peripheral Protection 26 2" "Not protected,Protected" textline " " setclrfld.long 0x00 9. 0x00 9. 0x20 9. " PCS26QUAD1PROT_set/clr ,Peripheral Protection 26 1" "Not protected,Protected" textline " " setclrfld.long 0x00 8. 0x00 8. 0x20 8. " PCS26QUAD0PROT_set/clr ,Peripheral Protection 26 0" "Not protected,Protected" textline " " setclrfld.long 0x00 7. 0x00 7. 0x20 7. " PCS25QUAD3PROT_set/clr ,Peripheral Protection 25 3" "Not protected,Protected" textline " " setclrfld.long 0x00 6. 0x00 6. 0x20 6. " PCS25QUAD2PROT_set/clr ,Peripheral Protection 25 2" "Not protected,Protected" textline " " setclrfld.long 0x00 5. 0x00 5. 0x20 5. " PCS25QUAD1PROT_set/clr ,Peripheral Protection 25 1" "Not protected,Protected" textline " " setclrfld.long 0x00 4. 0x00 4. 0x20 4. " PCS25QUAD0PROT_set/clr ,Peripheral Protection 25 0" "Not protected,Protected" textline " " setclrfld.long 0x00 3. 0x00 3. 0x20 3. " PCS24QUAD3PROT_set/clr ,Peripheral Protection 24 3" "Not protected,Protected" textline " " setclrfld.long 0x00 2. 0x00 2. 0x20 2. " PCS24QUAD2PROT_set/clr ,Peripheral Protection 24 2" "Not protected,Protected" textline " " setclrfld.long 0x00 1. 0x00 1. 0x20 1. " PCS24QUAD1PROT_set/clr ,Peripheral Protection 24 1" "Not protected,Protected" textline " " setclrfld.long 0x00 0. 0x00 0. 0x20 0. " PCS24QUAD0PROT_set/clr ,Peripheral Protection 24 0" "Not protected,Protected" tree.end width 15. tree "PCR Power Down Registers" tree "PCR Memory Power Down Registers" group.long 0x60++0x3 line.long 0x0 "PCSPWRDWNSET0,Peripheral Memory Power-Down Set Register 0" setclrfld.long 0x00 31. 0x00 31. 0x10 31. " PCS31PWRDWN_set/clr ,Peripheral Memory Power Down Enable 31" "No power down,Power down" textline " " setclrfld.long 0x00 30. 0x00 30. 0x10 30. " PCS30PWRDWN_set/clr ,Peripheral Memory Power Down Enable 30" "No power down,Power down" textline " " setclrfld.long 0x00 29. 0x00 29. 0x10 29. " PCS29PWRDWN_set/clr ,Peripheral Memory Power Down Enable 29" "No power down,Power down" textline " " setclrfld.long 0x00 28. 0x00 28. 0x10 28. " PCS28PWRDWN_set/clr ,Peripheral Memory Power Down Enable 28" "No power down,Power down" textline " " setclrfld.long 0x00 27. 0x00 27. 0x10 27. " PCS27PWRDWN_set/clr ,Peripheral Memory Power Down Enable 27" "No power down,Power down" textline " " setclrfld.long 0x00 26. 0x00 26. 0x10 26. " PCS26PWRDWN_set/clr ,Peripheral Memory Power Down Enable 26" "No power down,Power down" textline " " setclrfld.long 0x00 25. 0x00 25. 0x10 25. " PCS25PWRDWN_set/clr ,Peripheral Memory Power Down Enable 25" "No power down,Power down" textline " " setclrfld.long 0x00 24. 0x00 24. 0x10 24. " PCS24PWRDWN_set/clr ,Peripheral Memory Power Down Enable 24" "No power down,Power down" textline " " setclrfld.long 0x00 23. 0x00 23. 0x10 23. " PCS23PWRDWN_set/clr ,Peripheral Memory Power Down Enable 23" "No power down,Power down" textline " " setclrfld.long 0x00 22. 0x00 22. 0x10 22. " PCS22PWRDWN_set/clr ,Peripheral Memory Power Down Enable 22" "No power down,Power down" textline " " setclrfld.long 0x00 21. 0x00 21. 0x10 21. " PCS21PWRDWN_set/clr ,Peripheral Memory Power Down Enable 21" "No power down,Power down" textline " " setclrfld.long 0x00 20. 0x00 20. 0x10 20. " PCS20PWRDWN_set/clr ,Peripheral Memory Power Down Enable 20" "No power down,Power down" textline " " setclrfld.long 0x00 19. 0x00 19. 0x10 19. " PCS19PWRDWN_set/clr ,Peripheral Memory Power Down Enable 19" "No power down,Power down" textline " " setclrfld.long 0x00 18. 0x00 18. 0x10 18. " PCS18PWRDWN_set/clr ,Peripheral Memory Power Down Enable 18" "No power down,Power down" textline " " setclrfld.long 0x00 17. 0x00 17. 0x10 17. " PCS17PWRDWN_set/clr ,Peripheral Memory Power Down Enable 17" "No power down,Power down" textline " " setclrfld.long 0x00 16. 0x00 16. 0x10 16. " PCS16PWRDWN_set/clr ,Peripheral Memory Power Down Enable 16" "No power down,Power down" textline " " setclrfld.long 0x00 15. 0x00 15. 0x10 15. " PCS15PWRDWN_set/clr ,Peripheral Memory Power Down Enable 15" "No power down,Power down" textline " " setclrfld.long 0x00 14. 0x00 14. 0x10 14. " PCS14PWRDWN_set/clr ,Peripheral Memory Power Down Enable 14" "No power down,Power down" textline " " setclrfld.long 0x00 13. 0x00 13. 0x10 13. " PCS13PWRDWN_set/clr ,Peripheral Memory Power Down Enable 13" "No power down,Power down" textline " " setclrfld.long 0x00 12. 0x00 12. 0x10 12. " PCS12PWRDWN_set/clr ,Peripheral Memory Power Down Enable 12" "No power down,Power down" textline " " setclrfld.long 0x00 11. 0x00 11. 0x10 11. " PCS11PWRDWN_set/clr ,Peripheral Memory Power Down Enable 11" "No power down,Power down" textline " " setclrfld.long 0x00 10. 0x00 10. 0x10 10. " PCS10PWRDWN_set/clr ,Peripheral Memory Power Down Enable 10" "No power down,Power down" textline " " setclrfld.long 0x00 9. 0x00 9. 0x10 9. " PCS9PWRDWN_set/clr ,Peripheral Memory Power Down Enable 9" "No power down,Power down" textline " " setclrfld.long 0x00 8. 0x00 8. 0x10 8. " PCS8PWRDWN_set/clr ,Peripheral Memory Power Down Enable 8" "No power down,Power down" textline " " setclrfld.long 0x00 7. 0x00 7. 0x10 7. " PCS7PWRDWN_set/clr ,Peripheral Memory Power Down Enable 7" "No power down,Power down" textline " " setclrfld.long 0x00 6. 0x00 6. 0x10 6. " PCS6PWRDWN_set/clr ,Peripheral Memory Power Down Enable 6" "No power down,Power down" textline " " setclrfld.long 0x00 5. 0x00 5. 0x10 5. " PCS5PWRDWN_set/clr ,Peripheral Memory Power Down Enable 5" "No power down,Power down" textline " " setclrfld.long 0x00 4. 0x00 4. 0x10 4. " PCS4PWRDWN_set/clr ,Peripheral Memory Power Down Enable 4" "No power down,Power down" textline " " setclrfld.long 0x00 3. 0x00 3. 0x10 3. " PCS3PWRDWN_set/clr ,Peripheral Memory Power Down Enable 3" "No power down,Power down" textline " " setclrfld.long 0x00 2. 0x00 2. 0x10 2. " PCS2PWRDWN_set/clr ,Peripheral Memory Power Down Enable 2" "No power down,Power down" textline " " setclrfld.long 0x00 1. 0x00 1. 0x10 1. " PCS1PWRDWN_set/clr ,Peripheral Memory Power Down Enable 1" "No power down,Power down" textline " " setclrfld.long 0x00 0. 0x00 0. 0x10 0. " PCS0PWRDWN_set/clr ,Peripheral Memory Power Down Enable 0" "No power down,Power down" group.long 0x64++0x3 line.long 0x0 "PCSPWRDWNSET1,Peripheral Memory Power-Down Set Register 1" setclrfld.long 0x00 31. 0x00 31. 0x10 31. " PCS63PWRDWN_set/clr ,Peripheral Memory Power Down Enable 63" "No power down,Power down" textline " " setclrfld.long 0x00 30. 0x00 30. 0x10 30. " PCS62PWRDWN_set/clr ,Peripheral Memory Power Down Enable 62" "No power down,Power down" textline " " setclrfld.long 0x00 29. 0x00 29. 0x10 29. " PCS61PWRDWN_set/clr ,Peripheral Memory Power Down Enable 61" "No power down,Power down" textline " " setclrfld.long 0x00 28. 0x00 28. 0x10 28. " PCS60PWRDWN_set/clr ,Peripheral Memory Power Down Enable 60" "No power down,Power down" textline " " setclrfld.long 0x00 27. 0x00 27. 0x10 27. " PCS59PWRDWN_set/clr ,Peripheral Memory Power Down Enable 59" "No power down,Power down" textline " " setclrfld.long 0x00 26. 0x00 26. 0x10 26. " PCS58PWRDWN_set/clr ,Peripheral Memory Power Down Enable 58" "No power down,Power down" textline " " setclrfld.long 0x00 25. 0x00 25. 0x10 25. " PCS57PWRDWN_set/clr ,Peripheral Memory Power Down Enable 57" "No power down,Power down" textline " " setclrfld.long 0x00 24. 0x00 24. 0x10 24. " PCS56PWRDWN_set/clr ,Peripheral Memory Power Down Enable 56" "No power down,Power down" textline " " setclrfld.long 0x00 23. 0x00 23. 0x10 23. " PCS55PWRDWN_set/clr ,Peripheral Memory Power Down Enable 55" "No power down,Power down" textline " " setclrfld.long 0x00 22. 0x00 22. 0x10 22. " PCS54PWRDWN_set/clr ,Peripheral Memory Power Down Enable 54" "No power down,Power down" textline " " setclrfld.long 0x00 21. 0x00 21. 0x10 21. " PC531PWRDWN_set/clr ,Peripheral Memory Power Down Enable 53" "No power down,Power down" textline " " setclrfld.long 0x00 20. 0x00 20. 0x10 20. " PCS52PWRDWN_set/clr ,Peripheral Memory Power Down Enable 52" "No power down,Power down" textline " " setclrfld.long 0x00 19. 0x00 19. 0x10 19. " PCS51PWRDWN_set/clr ,Peripheral Memory Power Down Enable 51" "No power down,Power down" textline " " setclrfld.long 0x00 18. 0x00 18. 0x10 18. " PCS50PWRDWN_set/clr ,Peripheral Memory Power Down Enable 50" "No power down,Power down" textline " " setclrfld.long 0x00 17. 0x00 17. 0x10 17. " PCS49PWRDWN_set/clr ,Peripheral Memory Power Down Enable 49" "No power down,Power down" textline " " setclrfld.long 0x00 16. 0x00 16. 0x10 16. " PCS48PWRDWN_set/clr ,Peripheral Memory Power Down Enable 48" "No power down,Power down" textline " " setclrfld.long 0x00 15. 0x00 15. 0x10 15. " PCS47PWRDWN_set/clr ,Peripheral Memory Power Down Enable 47" "No power down,Power down" textline " " setclrfld.long 0x00 14. 0x00 14. 0x10 14. " PCS46PWRDWN_set/clr ,Peripheral Memory Power Down Enable 46" "No power down,Power down" textline " " setclrfld.long 0x00 13. 0x00 13. 0x10 13. " PCS45PWRDWN_set/clr ,Peripheral Memory Power Down Enable 45" "No power down,Power down" textline " " setclrfld.long 0x00 12. 0x00 12. 0x10 12. " PCS44PWRDWN_set/clr ,Peripheral Memory Power Down Enable 44" "No power down,Power down" textline " " setclrfld.long 0x00 11. 0x00 11. 0x10 11. " PCS43PWRDWN_set/clr ,Peripheral Memory Power Down Enable 43" "No power down,Power down" textline " " setclrfld.long 0x00 10. 0x00 10. 0x10 10. " PCS42PWRDWN_set/clr ,Peripheral Memory Power Down Enable 42" "No power down,Power down" textline " " setclrfld.long 0x00 9. 0x00 9. 0x10 9. " PCS41PWRDWN_set/clr ,Peripheral Memory Power Down Enable 41" "No power down,Power down" textline " " setclrfld.long 0x00 8. 0x00 8. 0x10 8. " PCS40PWRDWN_set/clr ,Peripheral Memory Power Down Enable 40" "No power down,Power down" textline " " setclrfld.long 0x00 7. 0x00 7. 0x10 7. " PCS39PWRDWN_set/clr ,Peripheral Memory Power Down Enable 39" "No power down,Power down" textline " " setclrfld.long 0x00 6. 0x00 6. 0x10 6. " PCS38PWRDWN_set/clr ,Peripheral Memory Power Down Enable 38" "No power down,Power down" textline " " setclrfld.long 0x00 5. 0x00 5. 0x10 5. " PCS37PWRDWN_set/clr ,Peripheral Memory Power Down Enable 37" "No power down,Power down" textline " " setclrfld.long 0x00 4. 0x00 4. 0x10 4. " PCS36PWRDWN_set/clr ,Peripheral Memory Power Down Enable 36" "No power down,Power down" textline " " setclrfld.long 0x00 3. 0x00 3. 0x10 3. " PCS35PWRDWN_set/clr ,Peripheral Memory Power Down Enable 35" "No power down,Power down" textline " " setclrfld.long 0x00 2. 0x00 2. 0x10 2. " PCS34PWRDWN_set/clr ,Peripheral Memory Power Down Enable 34" "No power down,Power down" textline " " setclrfld.long 0x00 1. 0x00 1. 0x10 1. " PCS33PWRDWN_set/clr ,Peripheral Memory Power Down Enable 33" "No power down,Power down" textline " " setclrfld.long 0x00 0. 0x00 0. 0x10 0. " PCS32PWRDWN_set/clr ,Peripheral Memory Power Down Enable 32" "No power down,Power down" tree.end width 15. textline " " group.long 0x80++0x3 line.long 0x0 "PSPWRDWNSET0,Peripheral Power-Down Set Register 0" setclrfld.long 0x00 31. 0x00 31. 0x20 31. " PS7QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 7 3" "No power down,Power down" textline " " setclrfld.long 0x00 30. 0x00 30. 0x20 30. " PS7QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 7 2" "No power down,Power down" textline " " setclrfld.long 0x00 29. 0x00 29. 0x20 29. " PS7QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 7 1" "No power down,Power down" textline " " setclrfld.long 0x00 28. 0x00 28. 0x20 28. " PS7QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 7 0" "No power down,Power down" textline " " setclrfld.long 0x00 27. 0x00 27. 0x20 27. " PS6QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 6 3" "No power down,Power down" textline " " setclrfld.long 0x00 26. 0x00 26. 0x20 26. " PS6QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 6 2" "No power down,Power down" textline " " setclrfld.long 0x00 25. 0x00 25. 0x20 25. " PS6QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 6 1" "No power down,Power down" textline " " setclrfld.long 0x00 24. 0x00 24. 0x20 24. " PS6QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 6 0" "No power down,Power down" textline " " setclrfld.long 0x00 23. 0x00 23. 0x20 23. " PS5QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 5 3" "No power down,Power down" textline " " setclrfld.long 0x00 22. 0x00 22. 0x20 22. " PS5QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 5 2" "No power down,Power down" textline " " setclrfld.long 0x00 21. 0x00 21. 0x20 21. " PS5QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 5 1" "No power down,Power down" textline " " setclrfld.long 0x00 20. 0x00 20. 0x20 20. " PS5QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 5 0" "No power down,Power down" textline " " setclrfld.long 0x00 19. 0x00 19. 0x20 19. " PS4QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 4 3" "No power down,Power down" textline " " setclrfld.long 0x00 18. 0x00 18. 0x20 18. " PS4QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 4 2" "No power down,Power down" textline " " setclrfld.long 0x00 17. 0x00 17. 0x20 17. " PS4QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 4 1" "No power down,Power down" textline " " setclrfld.long 0x00 16. 0x00 16. 0x20 16. " PS4QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 4 0" "No power down,Power down" textline " " setclrfld.long 0x00 15. 0x00 15. 0x20 15. " PS3QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 3 3" "No power down,Power down" textline " " setclrfld.long 0x00 14. 0x00 14. 0x20 14. " PS3QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 3 2" "No power down,Power down" textline " " setclrfld.long 0x00 13. 0x00 13. 0x20 13. " PS3QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 3 1" "No power down,Power down" textline " " setclrfld.long 0x00 12. 0x00 12. 0x20 12. " PS3QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 3 0" "No power down,Power down" textline " " setclrfld.long 0x00 11. 0x00 11. 0x20 11. " PS2QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 2 3" "No power down,Power down" textline " " setclrfld.long 0x00 10. 0x00 10. 0x20 10. " PS2QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 2 2" "No power down,Power down" textline " " setclrfld.long 0x00 9. 0x00 9. 0x20 9. " PS2QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 2 1" "No power down,Power down" textline " " setclrfld.long 0x00 8. 0x00 8. 0x20 8. " PS2QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 2 0" "No power down,Power down" textline " " setclrfld.long 0x00 7. 0x00 7. 0x20 7. " PS1QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 1 3" "No power down,Power down" textline " " setclrfld.long 0x00 6. 0x00 6. 0x20 6. " PS1QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 1 2" "No power down,Power down" textline " " setclrfld.long 0x00 5. 0x00 5. 0x20 5. " PS1QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 1 1" "No power down,Power down" textline " " setclrfld.long 0x00 4. 0x00 4. 0x20 4. " PS1QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 1 0" "No power down,Power down" textline " " setclrfld.long 0x00 3. 0x00 3. 0x20 3. " PS0QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 0 3" "No power down,Power down" textline " " setclrfld.long 0x00 2. 0x00 2. 0x20 2. " PS0QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 0 2" "No power down,Power down" textline " " setclrfld.long 0x00 1. 0x00 1. 0x20 1. " PS0QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 0 1" "No power down,Power down" textline " " setclrfld.long 0x00 0. 0x00 0. 0x20 0. " PS0QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 0 0" "No power down,Power down" group.long 0x84++0x3 line.long 0x0 "PSPWRDWNSET1,Peripheral Power-Down Set Register 1" setclrfld.long 0x00 31. 0x00 31. 0x20 31. " PS15QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 15 3" "No power down,Power down" textline " " setclrfld.long 0x00 30. 0x00 30. 0x20 30. " PS15QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 15 2" "No power down,Power down" textline " " setclrfld.long 0x00 29. 0x00 29. 0x20 29. " PS15QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 15 1" "No power down,Power down" textline " " setclrfld.long 0x00 28. 0x00 28. 0x20 28. " PS15QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 15 0" "No power down,Power down" textline " " setclrfld.long 0x00 27. 0x00 27. 0x20 27. " PS14QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 14 3" "No power down,Power down" textline " " setclrfld.long 0x00 26. 0x00 26. 0x20 26. " PS14QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 14 2" "No power down,Power down" textline " " setclrfld.long 0x00 25. 0x00 25. 0x20 25. " PS14QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 14 1" "No power down,Power down" textline " " setclrfld.long 0x00 24. 0x00 24. 0x20 24. " PS14QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 14 0" "No power down,Power down" textline " " setclrfld.long 0x00 23. 0x00 23. 0x20 23. " PS13QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 13 3" "No power down,Power down" textline " " setclrfld.long 0x00 22. 0x00 22. 0x20 22. " PS13QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 13 2" "No power down,Power down" textline " " setclrfld.long 0x00 21. 0x00 21. 0x20 21. " PS13QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 13 1" "No power down,Power down" textline " " setclrfld.long 0x00 20. 0x00 20. 0x20 20. " PS13QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 13 0" "No power down,Power down" textline " " setclrfld.long 0x00 19. 0x00 19. 0x20 19. " PS12QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 12 3" "No power down,Power down" textline " " setclrfld.long 0x00 18. 0x00 18. 0x20 18. " PS12QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 12 2" "No power down,Power down" textline " " setclrfld.long 0x00 17. 0x00 17. 0x20 17. " PS12QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 12 1" "No power down,Power down" textline " " setclrfld.long 0x00 16. 0x00 16. 0x20 16. " PS12QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 12 0" "No power down,Power down" textline " " setclrfld.long 0x00 15. 0x00 15. 0x20 15. " PS11QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 11 3" "No power down,Power down" textline " " setclrfld.long 0x00 14. 0x00 14. 0x20 14. " PS11QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 11 2" "No power down,Power down" textline " " setclrfld.long 0x00 13. 0x00 13. 0x20 13. " PS11QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 11 1" "No power down,Power down" textline " " setclrfld.long 0x00 12. 0x00 12. 0x20 12. " PS11QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 11 0" "No power down,Power down" textline " " setclrfld.long 0x00 11. 0x00 11. 0x20 11. " PS10QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 10 3" "No power down,Power down" textline " " setclrfld.long 0x00 10. 0x00 10. 0x20 10. " PS10QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 10 2" "No power down,Power down" textline " " setclrfld.long 0x00 9. 0x00 9. 0x20 9. " PS10QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 10 1" "No power down,Power down" textline " " setclrfld.long 0x00 8. 0x00 8. 0x20 8. " PS10QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 10 0" "No power down,Power down" textline " " setclrfld.long 0x00 7. 0x00 7. 0x20 7. " PS9QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 9 3" "No power down,Power down" textline " " setclrfld.long 0x00 6. 0x00 6. 0x20 6. " PS9QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 9 2" "No power down,Power down" textline " " setclrfld.long 0x00 5. 0x00 5. 0x20 5. " PS9QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 9 1" "No power down,Power down" textline " " setclrfld.long 0x00 4. 0x00 4. 0x20 4. " PS9QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 9 0" "No power down,Power down" textline " " setclrfld.long 0x00 3. 0x00 3. 0x20 3. " PS8QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 8 3" "No power down,Power down" textline " " setclrfld.long 0x00 2. 0x00 2. 0x20 2. " PS8QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 8 2" "No power down,Power down" textline " " setclrfld.long 0x00 1. 0x00 1. 0x20 1. " PS8QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 8 1" "No power down,Power down" textline " " setclrfld.long 0x00 0. 0x00 0. 0x20 0. " PS8QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 8 0" "No power down,Power down" group.long 0x88++0x3 line.long 0x0 "PSPWRDWNSET2,Peripheral Power-Down Set Register 2" setclrfld.long 0x00 31. 0x00 31. 0x20 31. " PS23QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 23 3" "No power down,Power down" textline " " setclrfld.long 0x00 30. 0x00 30. 0x20 30. " PS23QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 23 2" "No power down,Power down" textline " " setclrfld.long 0x00 29. 0x00 29. 0x20 29. " PS23QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 23 1" "No power down,Power down" textline " " setclrfld.long 0x00 28. 0x00 28. 0x20 28. " PS23QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 23 0" "No power down,Power down" textline " " setclrfld.long 0x00 27. 0x00 27. 0x20 27. " PS22QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 22 3" "No power down,Power down" textline " " setclrfld.long 0x00 26. 0x00 26. 0x20 26. " PS22QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 22 2" "No power down,Power down" textline " " setclrfld.long 0x00 25. 0x00 25. 0x20 25. " PS22QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 22 1" "No power down,Power down" textline " " setclrfld.long 0x00 24. 0x00 24. 0x20 24. " PS22QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 22 0" "No power down,Power down" textline " " setclrfld.long 0x00 23. 0x00 23. 0x20 23. " PS21QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 21 3" "No power down,Power down" textline " " setclrfld.long 0x00 22. 0x00 22. 0x20 22. " PS21QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 21 2" "No power down,Power down" textline " " setclrfld.long 0x00 21. 0x00 21. 0x20 21. " PS21QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 21 1" "No power down,Power down" textline " " setclrfld.long 0x00 20. 0x00 20. 0x20 20. " PS21QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 21 0" "No power down,Power down" textline " " setclrfld.long 0x00 19. 0x00 19. 0x20 19. " PS20QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 20 3" "No power down,Power down" textline " " setclrfld.long 0x00 18. 0x00 18. 0x20 18. " PS20QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 20 2" "No power down,Power down" textline " " setclrfld.long 0x00 17. 0x00 17. 0x20 17. " PS20QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 20 1" "No power down,Power down" textline " " setclrfld.long 0x00 16. 0x00 16. 0x20 16. " PS20QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 20 0" "No power down,Power down" textline " " setclrfld.long 0x00 15. 0x00 15. 0x20 15. " PS19QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 19 3" "No power down,Power down" textline " " setclrfld.long 0x00 14. 0x00 14. 0x20 14. " PS19QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 19 2" "No power down,Power down" textline " " setclrfld.long 0x00 13. 0x00 13. 0x20 13. " PS19QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 19 1" "No power down,Power down" textline " " setclrfld.long 0x00 12. 0x00 12. 0x20 12. " PS19QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 19 0" "No power down,Power down" textline " " setclrfld.long 0x00 11. 0x00 11. 0x20 11. " PS18QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 18 3" "No power down,Power down" textline " " setclrfld.long 0x00 10. 0x00 10. 0x20 10. " PS18QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 18 2" "No power down,Power down" textline " " setclrfld.long 0x00 9. 0x00 9. 0x20 9. " PS18QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 18 1" "No power down,Power down" textline " " setclrfld.long 0x00 8. 0x00 8. 0x20 8. " PS18QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 18 0" "No power down,Power down" textline " " setclrfld.long 0x00 7. 0x00 7. 0x20 7. " PS17QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 17 3" "No power down,Power down" textline " " setclrfld.long 0x00 6. 0x00 6. 0x20 6. " PS17QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 17 2" "No power down,Power down" textline " " setclrfld.long 0x00 5. 0x00 5. 0x20 5. " PS17QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 17 1" "No power down,Power down" textline " " setclrfld.long 0x00 4. 0x00 4. 0x20 4. " PS17QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 17 0" "No power down,Power down" textline " " setclrfld.long 0x00 3. 0x00 3. 0x20 3. " PS16QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 16 3" "No power down,Power down" textline " " setclrfld.long 0x00 2. 0x00 2. 0x20 2. " PS16QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 16 2" "No power down,Power down" textline " " setclrfld.long 0x00 1. 0x00 1. 0x20 1. " PS16QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 16 1" "No power down,Power down" textline " " setclrfld.long 0x00 0. 0x00 0. 0x20 0. " PS16QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 16 0" "No power down,Power down" group.long 0x8C++0x3 line.long 0x0 "PSPWRDWNSET3,Peripheral Power-Down Set Register 3" setclrfld.long 0x00 31. 0x00 31. 0x20 31. " PS31QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 31 3" "No power down,Power down" textline " " setclrfld.long 0x00 30. 0x00 30. 0x20 30. " PS31QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 31 2" "No power down,Power down" textline " " setclrfld.long 0x00 29. 0x00 29. 0x20 29. " PS31QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 31 1" "No power down,Power down" textline " " setclrfld.long 0x00 28. 0x00 28. 0x20 28. " PS31QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 31 0" "No power down,Power down" textline " " setclrfld.long 0x00 27. 0x00 27. 0x20 27. " PS30QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 30 3" "No power down,Power down" textline " " setclrfld.long 0x00 26. 0x00 26. 0x20 26. " PS30QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 30 2" "No power down,Power down" textline " " setclrfld.long 0x00 25. 0x00 25. 0x20 25. " PS30QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 30 1" "No power down,Power down" textline " " setclrfld.long 0x00 24. 0x00 24. 0x20 24. " PS30QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 30 0" "No power down,Power down" textline " " setclrfld.long 0x00 23. 0x00 23. 0x20 23. " PS29QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 29 3" "No power down,Power down" textline " " setclrfld.long 0x00 22. 0x00 22. 0x20 22. " PS29QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 29 2" "No power down,Power down" textline " " setclrfld.long 0x00 21. 0x00 21. 0x20 21. " PS29QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 29 1" "No power down,Power down" textline " " setclrfld.long 0x00 20. 0x00 20. 0x20 20. " PS29QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 29 0" "No power down,Power down" textline " " setclrfld.long 0x00 19. 0x00 19. 0x20 19. " PS28QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 28 3" "No power down,Power down" textline " " setclrfld.long 0x00 18. 0x00 18. 0x20 18. " PS28QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 28 2" "No power down,Power down" textline " " setclrfld.long 0x00 17. 0x00 17. 0x20 17. " PS28QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 28 1" "No power down,Power down" textline " " setclrfld.long 0x00 16. 0x00 16. 0x20 16. " PS28QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 28 0" "No power down,Power down" textline " " setclrfld.long 0x00 15. 0x00 15. 0x20 15. " PS27QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 27 3" "No power down,Power down" textline " " setclrfld.long 0x00 14. 0x00 14. 0x20 14. " PS27QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 27 2" "No power down,Power down" textline " " setclrfld.long 0x00 13. 0x00 13. 0x20 13. " PS27QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 27 1" "No power down,Power down" textline " " setclrfld.long 0x00 12. 0x00 12. 0x20 12. " PS27QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 27 0" "No power down,Power down" textline " " setclrfld.long 0x00 11. 0x00 11. 0x20 11. " PS26QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 26 3" "No power down,Power down" textline " " setclrfld.long 0x00 10. 0x00 10. 0x20 10. " PS26QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 26 2" "No power down,Power down" textline " " setclrfld.long 0x00 9. 0x00 9. 0x20 9. " PS26QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 26 1" "No power down,Power down" textline " " setclrfld.long 0x00 8. 0x00 8. 0x20 8. " PS26QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 26 0" "No power down,Power down" textline " " setclrfld.long 0x00 7. 0x00 7. 0x20 7. " PS25QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 25 3" "No power down,Power down" textline " " setclrfld.long 0x00 6. 0x00 6. 0x20 6. " PS25QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 25 2" "No power down,Power down" textline " " setclrfld.long 0x00 5. 0x00 5. 0x20 5. " PS25QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 25 1" "No power down,Power down" textline " " setclrfld.long 0x00 4. 0x00 4. 0x20 4. " PS25QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 25 0" "No power down,Power down" textline " " setclrfld.long 0x00 3. 0x00 3. 0x20 3. " PS24QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 24 3" "No power down,Power down" textline " " setclrfld.long 0x00 2. 0x00 2. 0x20 2. " PS24QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 24 2" "No power down,Power down" textline " " setclrfld.long 0x00 1. 0x00 1. 0x20 1. " PS24QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 24 1" "No power down,Power down" textline " " setclrfld.long 0x00 0. 0x00 0. 0x20 0. " PS24QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 24 0" "No power down,Power down" tree.end width 0xb tree.end tree.open "RAM Wrapper" tree "RAM_Wrapper_even" base ad:0xFFFFF800 width 14. group.long 0x00++0x13 line.long 0x00 "CTRL,Ram Control Register" bitfld.long 0x00 30. " EMUL_MODE_TRACE_Dis ,Emulation Mode Trace Disable" "No,Yes" bitfld.long 0x00 24.--27. " ADDR_PAR_OVR ,Address Parity Override" "Not inverted,Not inverted,Not inverted,Not inverted,Not inverted,Not inverted,Not inverted,Not inverted,Not inverted,Not inverted,Not inverted,Not inverted,Not inverted,Inverted,Not inverted,Not inverted" textline " " bitfld.long 0x00 16.--19. " ADDR_PAR_DET_Dis ,Address Parity Detect Disable" "Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.long 0x00 8. " ECC_WRT_ENA ,ECC Write Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--3. " ECC_DET_ENA ,ECC Detect Enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" line.long 0x04 "THRESHOLD,Threshold Register" hexmask.long.word 0x04 0.--15. 1. " SEC_THRESHOLD ,Single error correction threshold" line.long 0x08 "OCCUR,Occurrence Register" hexmask.long.word 0x08 0.--15. 1. " SEC_OCCUR ,Single error occurrence counter" width 14. line.long 0x0c "INTCTRL,Interrupt Control Register" bitfld.long 0x0c 0. " SERREN ,Single Error Correct Interrupt Enable" "Disabled,Enabled" line.long 0x10 "ERRSTATUS,Memory Fault Detect Status Register" bitfld.long 0x10 9. " WADDR_PAR_FAIL ,Write Address Parity Failure" "No error,Error" bitfld.long 0x10 8. " RADDR_PAR_FAIL ,Read Address Parity Failure" "No errror,Error" textline " " bitfld.long 0x10 5. " DERR ,DERR (Double Error) Generated" "No error,Error" bitfld.long 0x10 4. " ADDR_COMP_LOG_FAIL ,Address Compare Logic Failure" "Not compared,Compared" textline " " bitfld.long 0x10 2. " ADDR_DEC_FAIL ,Address Decode Failure" "Not failed,Failed" bitfld.long 0x10 0. " SERR ,Single Error Status" "Not occurred,Occurred" rgroup.long 0x14++0x3 line.long 0x00 "SERRADDR,Single Error Address Register" hexmask.long.tbyte 0x00 3.--17. 0x8 " SERRADDR ,Single Error Address" rgroup.long 0x1C++0x3 line.long 0x00 "UERRADDR,Uncorrectable Error Address Register" hexmask.long.tbyte 0x00 3.--22. 0x8 " UERROR_ADDR ,UERROR Address" group.long 0x30++0x3 line.long 0x00 "TEST,RAM Test Register" bitfld.long 0x00 8. " TEST_TRIGGER ,Test Trigger" "Disabled,Enabled" bitfld.long 0x00 6.--7. " TEST_MODE ,Test Mode" "Reserved,Inequality,Equality,?..." textline " " bitfld.long 0x00 0.--3. " TEST_ENA ,Test Enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" group.long 0x38++0x7 line.long 0x00 "ADDRDEC_VECT,Test Mode Vector Register" bitfld.long 0x00 26. " ECC_SELECT ,ECC Select" "Not selected,Selected" hexmask.long.word 0x00 0.--15. 1. " RAM_CHIP_SELECT ,RAM Chip Select" line.long 0x04 "PERRADDR,Parity Error Address Register" hexmask.long.tbyte 0x04 3.--22. 0x8 " PAR_ERR_ADDR ,Parity Error Address" width 0xb tree.end tree "RAM_Wrapper_odd" base ad:0xFFFFF900 width 14. group.long 0x00++0x13 line.long 0x00 "CTRL,Ram Control Register" bitfld.long 0x00 30. " EMUL_MODE_TRACE_Dis ,Emulation Mode Trace Disable" "No,Yes" bitfld.long 0x00 24.--27. " ADDR_PAR_OVR ,Address Parity Override" "Not inverted,Not inverted,Not inverted,Not inverted,Not inverted,Not inverted,Not inverted,Not inverted,Not inverted,Not inverted,Not inverted,Not inverted,Not inverted,Inverted,Not inverted,Not inverted" textline " " bitfld.long 0x00 16.--19. " ADDR_PAR_DET_Dis ,Address Parity Detect Disable" "Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.long 0x00 8. " ECC_WRT_ENA ,ECC Write Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--3. " ECC_DET_ENA ,ECC Detect Enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" line.long 0x04 "THRESHOLD,Threshold Register" hexmask.long.word 0x04 0.--15. 1. " SEC_THRESHOLD ,Single error correction threshold" line.long 0x08 "OCCUR,Occurrence Register" hexmask.long.word 0x08 0.--15. 1. " SEC_OCCUR ,Single error occurrence counter" width 14. line.long 0x0c "INTCTRL,Interrupt Control Register" bitfld.long 0x0c 0. " SERREN ,Single Error Correct Interrupt Enable" "Disabled,Enabled" line.long 0x10 "ERRSTATUS,Memory Fault Detect Status Register" bitfld.long 0x10 9. " WADDR_PAR_FAIL ,Write Address Parity Failure" "No error,Error" bitfld.long 0x10 8. " RADDR_PAR_FAIL ,Read Address Parity Failure" "No errror,Error" textline " " bitfld.long 0x10 5. " DERR ,DERR (Double Error) Generated" "No error,Error" bitfld.long 0x10 4. " ADDR_COMP_LOG_FAIL ,Address Compare Logic Failure" "Not compared,Compared" textline " " bitfld.long 0x10 2. " ADDR_DEC_FAIL ,Address Decode Failure" "Not failed,Failed" bitfld.long 0x10 0. " SERR ,Single Error Status" "Not occurred,Occurred" rgroup.long 0x14++0x3 line.long 0x00 "SERRADDR,Single Error Address Register" hexmask.long.tbyte 0x00 3.--17. 0x8 " SERRADDR ,Single Error Address" rgroup.long 0x1C++0x3 line.long 0x00 "UERRADDR,Uncorrectable Error Address Register" hexmask.long.tbyte 0x00 3.--22. 0x8 " UERROR_ADDR ,UERROR Address" group.long 0x30++0x3 line.long 0x00 "TEST,RAM Test Register" bitfld.long 0x00 8. " TEST_TRIGGER ,Test Trigger" "Disabled,Enabled" bitfld.long 0x00 6.--7. " TEST_MODE ,Test Mode" "Reserved,Inequality,Equality,?..." textline " " bitfld.long 0x00 0.--3. " TEST_ENA ,Test Enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" group.long 0x38++0x7 line.long 0x00 "ADDRDEC_VECT,Test Mode Vector Register" bitfld.long 0x00 26. " ECC_SELECT ,ECC Select" "Not selected,Selected" hexmask.long.word 0x00 0.--15. 1. " RAM_CHIP_SELECT ,RAM Chip Select" line.long 0x04 "PERRADDR,Parity Error Address Register" hexmask.long.tbyte 0x04 3.--22. 0x8 " PAR_ERR_ADDR ,Parity Error Address" width 0xb tree.end tree.end textline " "