; -------------------------------------------------------------------------------- ; @Title: STR91x On-Chip Peripherals ; @Props: Released ; @Author: GAC, (BOB) ; @Changelog: 2006-06-26 GAC ; @Manufacturer: STM - ST Microelectronics N.V. ; @Doc: 12126.pdf (2006-04 Rev 1); STR912_12274.pdf (2006-04 Rev 1) ; STR91xFA_RM_13742.pdf (Rev. 3, 2008-04-21) ; STR91xFA_DS_13495.pdf (Rev. 5, 2008-12-22) ; @Core: ARM966E-S ; @Chip: ; @Copyright: (C) 1989-2017 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: perstr91x.per 17449 2024-02-05 16:59:24Z kwisniewski $ config 16. 8. width 0xB base ad:0x00000000 tree "ARM Core Registers" width 8. tree "ID Registers" rgroup c15:0x0000--0x0000 line.long 0x0 "MIDR,Identity Code" hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer" hexmask.long.byte 0x0 20.--23. 0x1 " SPEC ,Specification Revision" hexmask.long.byte 0x0 16.--19. 0x1 " ARCH ,Architecture Version" hexmask.long.word 0x0 4.--15. 0x1 " PARTNUM ,Part Number" hexmask.long.byte 0x0 0.--3. 0x01 " REV ,Layout Revision" tree.end tree "System Configuration and Control" width 8. group c15:0x1--0x1 line.long 0x0 "CR,Control Register" bitfld.long 0x0 15. " L4 ,Configure Loading TBIT" "Enable,Disable" bitfld.long 0x0 13. " V ,Location of Exception Vectors" "0x00000000,0xFFFF0000" textline " " bitfld.long 0x0 12. " I ,Instruction SRAM Enable" "Disable,Enable" bitfld.long 0x0 7. " B ,Endianism" "Little,Big" bitfld.long 0x0 3. " W ,Write Buffer" "Disable,Enable" bitfld.long 0x0 2. " D ,Data SRAM Enable" "Disable,Enable" tree.end tree "ICEbreaker" width 8. group ice:0x0--0x5 "Debug Control" line.long 0x0 "DBGCTRL,Debug Control Register" bitfld.long 0x0 0x5 " ICE ,EmbeddedICE Disable" "enabled,disabled" bitfld.long 0x0 0x4 " MONITOR ,Monitor Mode Enable" "disabled,enabled" textline " " bitfld.long 0x0 0x3 " STEP ,Single Step" "disabled,enabled" bitfld.long 0x0 0x2 " INTDIS ,Interrupts Disable" "enabled,disabled" bitfld.long 0x0 0x1 " DBGRQ ,Debug Request" "no,yes" bitfld.long 0x0 0x0 " DBGACK ,Debug Acknowledge" "no,yes" line.long 0x4 "DBGSTAT,Debug Status Register" bitfld.long 0x4 0x4 " ITBIT ,ITBIT" "0,1" bitfld.long 0x4 0x3 " SYSCOMP ,SYSCOMP" "0,1" bitfld.long 0x4 0x2 " IFEN ,Interrupts Enable" "disabled,enabled" bitfld.long 0x4 0x1 " DBGRQ ,Debug Request" "no,yes" bitfld.long 0x4 0x0 " DBGACK ,Debug Acknowledge" "no,yes" line.long 0x8 "VECTOR,Vector Catch Register" bitfld.long 0x8 0x7 " FIQ ,FIQ" "dis,ena" bitfld.long 0x8 0x6 " IRQ ,IRQ" "dis,ena" bitfld.long 0x8 0x4 " D_ABO ,D_ABORT" "dis,ena" bitfld.long 0x8 0x3 " P_ABO ,P_ABORT" "dis,ena" bitfld.long 0x8 0x2 " SWI ,SWI" "dis,ena" bitfld.long 0x8 0x1 " UND ,UNDEF" "dis,ena" bitfld.long 0x8 0x0 " RES ,RESET" "dis,ena" line.long 0x10 "COMCTRL,Debug Communication Control Register" bitfld.long 0x10 28.--31. " VERSION ,Version Number" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111" bitfld.long 0x10 0x1 " WRITE ,Write Register Free" "idle,pend" bitfld.long 0x10 0x0 " READ ,Read Register Free" "idle,pend" line.long 0x14 "COMDATA,Debug Communication Data Register" group ice:0x8--0x0d "Watchpoint 0" line.long 0x0 "AV,Address Value" line.long 0x4 "AM,Address Mask" line.long 0x8 "DV,Data Value" line.long 0x0c "DM,Data Mask" line.long 0x10 "CV,Control Value" bitfld.long 0x10 0x8 " ENABLE ,Global Enable for Watchpoint 1" "DIS,ENA" bitfld.long 0x10 0x7 " RANGE ,Assert RANGEOUT Signal" "0 ,1" bitfld.long 0x10 0x6 " CHAIN ,Connect to Watchpoint 0" "0 ,1" bitfld.long 0x10 0x5 " EXTERN ,Depentend from EXTERN Signal" "0 ,1" bitfld.long 0x10 0x4 " nTRANS ,CPU Mode" "User,no User" bitfld.long 0x10 0x3 " nOPC ,Op Fetch" "Inst,Data" bitfld.long 0x10 0x1--0x2 " MAS ,Access Size" "Byte,Word,Long,Res" bitfld.long 0x10 0x0 " nRW ,Read/Write" "R ,W" line.long 0x14 "CM,Control Mask" bitfld.long 0x14 0x7 " RANGE ,Assert RANGEOUT Signal" "ENA,DIS" bitfld.long 0x14 0x6 " CHAIN ,Connect to Watchpoint 0" "ENA,DIS" bitfld.long 0x14 0x5 " EXTERN ,Depentend from EXTERN Signal" "ENA,DIS" bitfld.long 0x14 0x4 " nTRANS ,CPU Mode" "ENA,DIS " bitfld.long 0x14 0x3 " nOPC ,Op Fetch" "ENA ,DIS" bitfld.long 0x14 0x1--0x2 " MAS ,Access Size" "ENA ,Res,Res,DIS" bitfld.long 0x14 0x0 " nRW ,Read/Write" "ENA,DIS" group ice:0x10--0x15 "Watchpoint 1" line.long 0x0 "AV,Address Value" line.long 0x4 "AM,Address Mask" line.long 0x8 "DV,Data Value" line.long 0x0c "DM,Data Mask" line.long 0x10 "CV,Control Value" bitfld.long 0x10 0x8 " ENABLE ,Global Enable for Watchpoint 1" "DIS,ENA" bitfld.long 0x10 0x7 " RANGE ,Assert RANGEOUT Signal" "0 ,1" bitfld.long 0x10 0x6 " CHAIN ,Connect to Watchpoint 0" "0 ,1" bitfld.long 0x10 0x5 " EXTERN ,Depentend from EXTERN Signal" "0 ,1" bitfld.long 0x10 0x4 " nTRANS ,CPU Mode" "User,no User" bitfld.long 0x10 0x3 " nOPC ,Op Fetch" "Inst,Data" bitfld.long 0x10 0x1--0x2 " MAS ,Access Size" "Byte,Word,Long,Res" bitfld.long 0x10 0x0 " nRW ,Read/Write" "R ,w" line.long 0x14 "CM,Control Mask" bitfld.long 0x14 0x7 " RANGE ,Assert RANGEOUT Signal" "ENA,DIS" bitfld.long 0x14 0x6 " CHAIN ,Connect to Watchpoint 0" "ENA,DIS" bitfld.long 0x14 0x5 " EXTERN ,Depentend from EXTERN Signal" "ENA,DIS" bitfld.long 0x14 0x4 " nTRANS ,CPU Mode" "ENA,DIS " bitfld.long 0x14 0x3 " nOPC ,Op Fetch" "ENA ,DIS" bitfld.long 0x14 0x1--0x2 " MAS ,Access Size" "ENA ,Res,Res,DIS" bitfld.long 0x14 0x0 " nRW ,Read/Write" "ENA,DIS" tree.end width 0xb tree.end tree "FMI (Flash Memory Interface)" base asd:0x54000000 width 0xF group.long 0x0++0x7 line.long 0x0 "FMI_BBSR,Boot Bank Size Register" bitfld.long 0x0 0.--3. " BBSIZE[3:0] ,Boot Bank Size" "32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,?..." line.long 0x4 "FMI_NBBSR,Non-Boot Bank Size Register" bitfld.long 0x4 0.--3. " NBBSIZE[3:0] ,Non-Boot Bank Size" "8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,?..." group.long 0xC++0x7 line.long 0x0 "FMI_BBADR,Boot Bank Base Address Register" hexmask.long.tbyte 0x0 0.--23. 1. " BBADDR[23:0] ,Boot Bank Base Address" line.long 0x4 "FMI_NBBADR,Non-Boot Bank Base Address Register" hexmask.long.tbyte 0x4 0.--23. 1. " NBBADDR[23:0] ,Non-Boot Bank Base Address" group.long 0x18++0x3 line.long 0x0 "FMI_CR,FMI Control Register" sif (cpuis("STR910FA*")||cpuis("STR911FA*")||cpuis("STR912FA*")) bitfld.long 0x00 8. " WWS ,Write Wait States" "1 cycle,2 cycles" bitfld.long 0x00 7. " OMIE ,Out of Memory Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. " BERRIE ,Flash Bank Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " NBBEN ,Flash Non Boot Bank enable" "Disabled,Enabled" bitfld.long 0x00 3. " BBEN ,Flash Boot Bank enable" "Disabled,Enabled" else bitfld.long 0x00 8. " WWS ,Write Wait States" "1 cycle,2 cycles" bitfld.long 0x00 7. " OMIE ,Out of Memory Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. " BERRIE ,Flash Bank Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " B1EN ,Flash Bank 1 Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " B0EN ,Flash Bank 0 Enable" "Disabled,Enabled" endif group.long 0x1C++0x3 line.long 0x0 "FMI_SR,FMI Status Register" bitfld.long 0x00 4. " PFQBCEN ,PFQBCEN Status" "Disabled,Enabled" eventfld.long 0x00 3. " OM ,Out of Memory Error" "No error,Error" eventfld.long 0x00 1. " B1ERR ,Flash Bank 1 Error" "No error,Error" textline " " eventfld.long 0x00 0. " B0ERR ,Flash Bank 0 Error" "No error,Error" group.long 0x20++0x3 sif (cpuis("STR910FA*")||cpuis("STR911FA*")||cpuis("STR912FA*")) line.long 0x0 "FMI_BCE16ADDR,BC 16th Entry Target Address register" hexmask.long.tbyte 0x0 0.--23. 1. " BCE16ADDR[23:0] ,Branch Cache 16th Entry Target Address" else line.long 0x0 "FMI_BCE5ADDR,BC Fifth Entry Target Address Register" hexmask.long.tbyte 0x0 0.--23. 1. " BCE5ADDR[23:0] ,Branch Cache Fifth Entry Target Address" endif width 0xB tree.end tree "EMI (External Memory Interface)" base asd:0x74000000 sif (!cpuis("STR910FAM*")&&!cpuis("STR911FAM*")) width 12. group.long 0x0++0x03 line.long 0x0 "EMI_ICR1,Bank 1 Idle Cycle Control Register" bitfld.long 0x0 0.--3. " IDCY[3:0] ,Idle Cycles" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles" group.long 0x20++0x03 line.long 0x0 "EMI_ICR2,Bank 2 Idle Cycle Control Register" bitfld.long 0x0 0.--3. " IDCY[3:0] ,Idle Cycles" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles" group.long 0x40++0x03 line.long 0x0 "EMI_ICR3,Bank 3 Idle Cycle Control Register" bitfld.long 0x0 0.--3. " IDCY[3:0] ,Idle Cycles" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles" group.long 0xE0++0x03 line.long 0x0 "EMI_ICR0,Bank 0 Idle Cycle Control Register" bitfld.long 0x0 0.--3. " IDCY[3:0] ,Idle Cycles" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles" group.long 0x4++0x03 line.long 0x0 "EMI_RCR1,Bank 1 Read Wait State Control Register" bitfld.long 0x0 0.--4. " WSTRD[4:0] ,Read Wait States" "No state,1 state,2 states,3 states,4 states,5 states,6 states,7 states,8 states,9 states,10 states,11 states,12 states,13 states,14 states,15 states,16 states,17 states,18 states,19 states,20 states,21 states,22 states,23 states,24 states,25 states,26 states,27 states,28 states,29 states,30 states,31 states" group.long 0x24++0x03 line.long 0x0 "EMI_RCR2,Bank 2 Read Wait State Control Register" bitfld.long 0x0 0.--4. " WSTRD[4:0] ,Read Wait States" "No state,1 state,2 states,3 states,4 states,5 states,6 states,7 states,8 states,9 states,10 states,11 states,12 states,13 states,14 states,15 states,16 states,17 states,18 states,19 states,20 states,21 states,22 states,23 states,24 states,25 states,26 states,27 states,28 states,29 states,30 states,31 states" group.long 0x44++0x03 line.long 0x0 "EMI_RCR3,Bank 3 Read Wait State Control Register" bitfld.long 0x0 0.--4. " WSTRD[4:0] ,Read Wait States" "No state,1 state,2 states,3 states,4 states,5 states,6 states,7 states,8 states,9 states,10 states,11 states,12 states,13 states,14 states,15 states,16 states,17 states,18 states,19 states,20 states,21 states,22 states,23 states,24 states,25 states,26 states,27 states,28 states,29 states,30 states,31 states" group.long 0xE4++0x03 line.long 0x0 "EMI_RCR0,Bank 0 Read Wait State Control Register" bitfld.long 0x0 0.--4. " WSTRD[4:0] ,Read Wait States" "No state,1 state,2 states,3 states,4 states,5 states,6 states,7 states,8 states,9 states,10 states,11 states,12 states,13 states,14 states,15 states,16 states,17 states,18 states,19 states,20 states,21 states,22 states,23 states,24 states,25 states,26 states,27 states,28 states,29 states,30 states,31 states" group.long 0x8++0x03 line.long 0x0 "EMI_WCR1,Bank 1 Write Wait State Control Register" bitfld.long 0x0 0.--4. " WSTWR[4:0] ,Write Wait States" "No state,1 state,2 states,3 states,4 states,5 states,6 states,7 states,8 states,9 states,10 states,11 states,12 states,13 states,14 states,15 states,16 states,17 states,18 states,19 states,20 states,21 states,22 states,23 states,24 states,25 states,26 states,27 states,28 states,29 states,30 states,31 states" group.long 0x28++0x03 line.long 0x0 "EMI_WCR2,Bank 2 Write Wait State Control Register" bitfld.long 0x0 0.--4. " WSTWR[4:0] ,Write Wait States" "No state,1 state,2 states,3 states,4 states,5 states,6 states,7 states,8 states,9 states,10 states,11 states,12 states,13 states,14 states,15 states,16 states,17 states,18 states,19 states,20 states,21 states,22 states,23 states,24 states,25 states,26 states,27 states,28 states,29 states,30 states,31 states" group.long 0x48++0x03 line.long 0x0 "EMI_WCR3,Bank 3 Write Wait State Control Register" bitfld.long 0x0 0.--4. " WSTWR[4:0] ,Write Wait States" "No state,1 state,2 states,3 states,4 states,5 states,6 states,7 states,8 states,9 states,10 states,11 states,12 states,13 states,14 states,15 states,16 states,17 states,18 states,19 states,20 states,21 states,22 states,23 states,24 states,25 states,26 states,27 states,28 states,29 states,30 states,31 states" group.long 0xE8++0x03 line.long 0x0 "EMI_WCR0,Bank 0 Write Wait State Control Register" bitfld.long 0x0 0.--4. " WSTWR[4:0] ,Write Wait States" "No state,1 state,2 states,3 states,4 states,5 states,6 states,7 states,8 states,9 states,10 states,11 states,12 states,13 states,14 states,15 states,16 states,17 states,18 states,19 states,20 states,21 states,22 states,23 states,24 states,25 states,26 states,27 states,28 states,29 states,30 states,31 states" group.long 0xC++0x03 line.long 0x0 "EMI_OECR1,Bank 1 Output Enable Control Register" bitfld.long 0x0 0.--3. " WSTOEN[3:0] ,Output Enable Assertion Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2C++0x03 line.long 0x0 "EMI_OECR2,Bank 2 Output Enable Control Register" bitfld.long 0x0 0.--3. " WSTOEN[3:0] ,Output Enable Assertion Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4C++0x03 line.long 0x0 "EMI_OECR3,Bank 3 Output Enable Control Register" bitfld.long 0x0 0.--3. " WSTOEN[3:0] ,Output Enable Assertion Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xEC++0x03 line.long 0x0 "EMI_OECR0,Bank 0 Output Enable Control Register" bitfld.long 0x0 0.--3. " WSTOEN[3:0] ,Output Enable Assertion Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x10++0x03 line.long 0x0 "EMI_WECR1,Bank 1 Write Enable Control Register" bitfld.long 0x0 0.--3. " WSTWEN[3:0] ,Write Enable Assertion Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x30++0x03 line.long 0x0 "EMI_WECR2,Bank 2 Write Enable Control Register" bitfld.long 0x0 0.--3. " WSTWEN[3:0] ,Write Enable Assertion Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x50++0x03 line.long 0x0 "EMI_WECR3,Bank 3 Write Enable Control Register" bitfld.long 0x0 0.--3. " WSTWEN[3:0] ,Write Enable Assertion Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xF0++0x03 line.long 0x0 "EMI_WECR0,Bank 0 Write Enable Control Register" bitfld.long 0x0 0.--3. " WSTWEN[3:0] ,Write Enable Assertion Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif (cpuis("STR910FA*")||cpuis("STR911FA*")||cpuis("STR912FA*")) if ((((d.l(asd:(0x5C002000+0xAC)))&0x1)==0x1)&&(((d.l(asd:(0x5C002000+0x34)))&0x40)==0x40)&&(((d.l(asd:(0x74000000+0x14)))&0x30)==0x0)&&(((d.l(asd:(0x74000000+0x14)))&0x20000)==0x20000)&&(((d.l(asd:(0x74000000+0x14)))&0x200)==0x200)) group.long 0x14++0x03 line.long 0x0 "EMI_BCR1,Bank 1 Control Register" bitfld.long 0x00 18.--19. " BWLEN ,Burst write transfer length" "4-transfer,8-transfer,Reserved,Continuous burst" bitfld.long 0x00 17. " SYNCWRITEDEV ,Synchronous write access device" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 16. " BMWRITE ,Burst mode write" "No burst,Burst" bitfld.long 0x00 10.--11. " BRLEN ,Burst Read Transfer Length" "4-transfer,8-transfer,16-transfer,Continuous" textline " " bitfld.long 0x00 9. " SYNCREADDEV ,Synchronous read access device" "Asynchronous,Synchronous" bitfld.long 0x00 8. " BPM ,Burst and Page Mode Read Selection" "Normal,Burst/Page" textline " " bitfld.long 0x00 4.--5. " MW ,Memory width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write protect" "Not protected,Protected" textline " " bitfld.long 0x00 0. " BLE ,Byte Lane Enable" "Disabled,Enabled" elif ((((d.l(asd:(0x5C002000+0xAC)))&0x1)==0x1)&&(((d.l(asd:(0x5C002000+0x34)))&0x40)==0x40)&&(((d.l(asd:(0x74000000+0x14)))&0x30)==0x0)&&(((d.l(asd:(0x74000000+0x14)))&0x20000)==0x20000)&&(((d.l(asd:(0x74000000+0x14)))&0x200)==0x0)) group.long 0x14++0x03 line.long 0x0 "EMI_BCR1,Bank 1 Control Register" bitfld.long 0x00 18.--19. " BWLEN ,Burst write transfer length" "4-transfer,8-transfer,Reserved,Continuous burst" bitfld.long 0x00 17. " SYNCWRITEDEV ,Synchronous write access device" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 16. " BMWRITE ,Burst mode write" "No burst,Burst" bitfld.long 0x00 10.--11. " BRLEN ,Burst Read Transfer Length" "4-transfer,8-transfer,16-transfer,?..." textline " " bitfld.long 0x00 9. " SYNCREADDEV ,Synchronous read access device" "Asynchronous,Synchronous" bitfld.long 0x00 8. " BPM ,Burst and Page Mode Read Selection" "Normal,Burst/Page" textline " " bitfld.long 0x00 4.--5. " MW ,Memory width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write protect" "Not protected,Protected" textline " " bitfld.long 0x00 0. " BLE ,Byte Lane Enable" "Disabled,Enabled" elif ((((d.l(asd:(0x5C002000+0xAC)))&0x1)==0x1)&&(((d.l(asd:(0x5C002000+0x34)))&0x40)==0x40)&&(((d.l(asd:(0x74000000+0x14)))&0x30)==0x0)&&(((d.l(asd:(0x74000000+0x14)))&0x20000)==0x0)&&(((d.l(asd:(0x74000000+0x14)))&0x200)==0x200)) group.long 0x14++0x03 line.long 0x0 "EMI_BCR1,Bank 1 Control Register" bitfld.long 0x00 18.--19. " BWLEN ,Burst write transfer length" "4-transfer,8-transfer,?..." bitfld.long 0x00 17. " SYNCWRITEDEV ,Synchronous write access device" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 16. " BMWRITE ,Burst mode write" "No burst,Burst" bitfld.long 0x00 10.--11. " BRLEN ,Burst Read Transfer Length" "4-transfer,8-transfer,16-transfer,Continuous" textline " " bitfld.long 0x00 9. " SYNCREADDEV ,Synchronous read access device" "Asynchronous,Synchronous" bitfld.long 0x00 8. " BPM ,Burst and Page Mode Read Selection" "Normal,Burst/Page" textline " " bitfld.long 0x00 4.--5. " MW ,Memory width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write protect" "Not protected,Protected" textline " " bitfld.long 0x00 0. " BLE ,Byte Lane Enable" "Disabled,Enabled" elif ((((d.l(asd:(0x5C002000+0xAC)))&0x1)==0x0)&&(((d.l(asd:(0x5C002000+0x34)))&0x40)==0x40)&&(((d.l(asd:(0x74000000+0x14)))&0x30)==0x0)&&(((d.l(asd:(0x74000000+0x14)))&0x20000)==0x20000)&&(((d.l(asd:(0x74000000+0x14)))&0x200)==0x200)) group.long 0x14++0x03 line.long 0x0 "EMI_BCR1,Bank 1 Control Register" bitfld.long 0x00 18.--19. " BWLEN ,Burst write transfer length" "4-transfer,8-transfer,Reserved,Continuous burst" bitfld.long 0x00 17. " SYNCWRITEDEV ,Synchronous write access device" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 16. " BMWRITE ,Burst mode write" "No burst,Burst" bitfld.long 0x00 10.--11. " BRLEN ,Burst Read Transfer Length" "4-transfer,8-transfer,16-transfer,Continuous" textline " " bitfld.long 0x00 9. " SYNCREADDEV ,Synchronous read access device" "Asynchronous,Synchronous" bitfld.long 0x00 8. " BPM ,Burst and Page Mode Read Selection" "Normal,Burst/Page" textline " " bitfld.long 0x00 4.--5. " MW ,Memory width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write protect" "Not protected,Protected" textline " " bitfld.long 0x00 0. " BLE ,Byte Lane Enable" "Disabled,?..." elif ((((d.l(asd:(0x5C002000+0xAC)))&0x1)==0x0)&&(((d.l(asd:(0x5C002000+0x34)))&0x40)==0x40)&&(((d.l(asd:(0x74000000+0x14)))&0x30)==0x0)&&(((d.l(asd:(0x74000000+0x14)))&0x20000)==0x20000)&&(((d.l(asd:(0x74000000+0x14)))&0x200)==0x0)) group.long 0x14++0x03 line.long 0x0 "EMI_BCR1,Bank 1 Control Register" bitfld.long 0x00 18.--19. " BWLEN ,Burst write transfer length" "4-transfer,8-transfer,Reserved,Continuous burst" bitfld.long 0x00 17. " SYNCWRITEDEV ,Synchronous write access device" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 16. " BMWRITE ,Burst mode write" "No burst,Burst" bitfld.long 0x00 10.--11. " BRLEN ,Burst Read Transfer Length" "4-transfer,8-transfer,16-transfer,?..." textline " " bitfld.long 0x00 9. " SYNCREADDEV ,Synchronous read access device" "Asynchronous,Synchronous" bitfld.long 0x00 8. " BPM ,Burst and Page Mode Read Selection" "Normal,Burst/Page" textline " " bitfld.long 0x00 4.--5. " MW ,Memory width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write protect" "Not protected,Protected" textline " " bitfld.long 0x00 0. " BLE ,Byte Lane Enable" "Disabled,?..." elif ((((d.l(asd:(0x5C002000+0xAC)))&0x1)==0x0)&&(((d.l(asd:(0x5C002000+0x34)))&0x40)==0x40)&&(((d.l(asd:(0x74000000+0x14)))&0x30)==0x0)&&(((d.l(asd:(0x74000000+0x14)))&0x20000)==0x0)&&(((d.l(asd:(0x74000000+0x14)))&0x200)==0x200)) group.long 0x14++0x03 line.long 0x0 "EMI_BCR1,Bank 1 Control Register" bitfld.long 0x00 18.--19. " BWLEN ,Burst write transfer length" "4-transfer,8-transfer,?..." bitfld.long 0x00 17. " SYNCWRITEDEV ,Synchronous write access device" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 16. " BMWRITE ,Burst mode write" "No burst,Burst" bitfld.long 0x00 10.--11. " BRLEN ,Burst Read Transfer Length" "4-transfer,8-transfer,16-transfer,Continuous" textline " " bitfld.long 0x00 9. " SYNCREADDEV ,Synchronous read access device" "Asynchronous,Synchronous" bitfld.long 0x00 8. " BPM ,Burst and Page Mode Read Selection" "Normal,Burst/Page" textline " " bitfld.long 0x00 4.--5. " MW ,Memory width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write protect" "Not protected,Protected" textline " " bitfld.long 0x00 0. " BLE ,Byte Lane Enable" "Disabled,?..." elif ((((d.l(asd:(0x5C002000+0xAC)))&0x1)==0x0)&&(((d.l(asd:(0x5C002000+0x34)))&0x40)==0x40)&&(((d.l(asd:(0x74000000+0x14)))&0x30)==0x0)&&(((d.l(asd:(0x74000000+0x14)))&0x20000)==0x0)&&(((d.l(asd:(0x74000000+0x14)))&0x200)==0x0)) group.long 0x14++0x03 line.long 0x0 "EMI_BCR1,Bank 1 Control Register" bitfld.long 0x00 18.--19. " BWLEN ,Burst write transfer length" "4-transfer,8-transfer,?..." bitfld.long 0x00 17. " SYNCWRITEDEV ,Synchronous write access device" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 16. " BMWRITE ,Burst mode write" "No burst,Burst" bitfld.long 0x00 10.--11. " BRLEN ,Burst Read Transfer Length" "4-transfer,8-transfer,16-transfer,?..." textline " " bitfld.long 0x00 9. " SYNCREADDEV ,Synchronous read access device" "Asynchronous,Synchronous" bitfld.long 0x00 8. " BPM ,Burst and Page Mode Read Selection" "Normal,Burst/Page" textline " " bitfld.long 0x00 4.--5. " MW ,Memory width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write protect" "Not protected,Protected" textline " " bitfld.long 0x00 0. " BLE ,Byte Lane Enable" "Disabled,?..." elif ((((d.l(asd:(0x5C002000+0xAC)))&0x1)==0x1)&&(((d.l(asd:(0x74000000+0x14)))&0x20000)==0x20000)&&(((d.l(asd:(0x74000000+0x14)))&0x200)==0x200)) group.long 0x14++0x03 line.long 0x0 "EMI_BCR1,Bank 1 Control Register" bitfld.long 0x00 18.--19. " BWLEN ,Burst write transfer length" "4-transfer,8-transfer,Reserved,Continuous burst" bitfld.long 0x00 17. " SYNCWRITEDEV ,Synchronous write access device" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 16. " BMWRITE ,Burst mode write" "No burst,Burst" bitfld.long 0x00 10.--11. " BRLEN ,Burst Read Transfer Length" "4-transfer,8-transfer,16-transfer,Continuous" textline " " bitfld.long 0x00 9. " SYNCREADDEV ,Synchronous read access device" "Asynchronous,Synchronous" bitfld.long 0x00 8. " BPM ,Burst and Page Mode Read Selection" "Normal,Burst" textline " " bitfld.long 0x00 4.--5. " MW ,Memory width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write protect" "Not protected,Protected" textline " " bitfld.long 0x00 0. " BLE ,Byte Lane Enable" "Disabled,Enabled" elif ((((d.l(asd:(0x5C002000+0xAC)))&0x1)==0x1)&&(((d.l(asd:(0x74000000+0x14)))&0x20000)==0x20000)&&(((d.l(asd:(0x74000000+0x14)))&0x200)==0x0)) group.long 0x14++0x03 line.long 0x0 "EMI_BCR1,Bank 1 Control Register" bitfld.long 0x00 18.--19. " BWLEN ,Burst write transfer length" "4-transfer,8-transfer,Reserved,Continuous burst" bitfld.long 0x00 17. " SYNCWRITEDEV ,Synchronous write access device" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 16. " BMWRITE ,Burst mode write" "No burst,Burst" bitfld.long 0x00 10.--11. " BRLEN ,Burst Read Transfer Length" "4-transfer,8-transfer,16-transfer,?..." textline " " bitfld.long 0x00 9. " SYNCREADDEV ,Synchronous read access device" "Asynchronous,Synchronous" bitfld.long 0x00 8. " BPM ,Burst and Page Mode Read Selection" "Normal,Burst" textline " " bitfld.long 0x00 4.--5. " MW ,Memory width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write protect" "Not protected,Protected" textline " " bitfld.long 0x00 0. " BLE ,Byte Lane Enable" "Disabled,Enabled" elif ((((d.l(asd:(0x5C002000+0xAC)))&0x1)==0x1)&&(((d.l(asd:(0x74000000+0x14)))&0x20000)==0x0)&&(((d.l(asd:(0x74000000+0x14)))&0x200)==0x200)) group.long 0x14++0x03 line.long 0x0 "EMI_BCR1,Bank 1 Control Register" bitfld.long 0x00 18.--19. " BWLEN ,Burst write transfer length" "4-transfer,8-transfer,?..." bitfld.long 0x00 17. " SYNCWRITEDEV ,Synchronous write access device" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 16. " BMWRITE ,Burst mode write" "No burst,Burst" bitfld.long 0x00 10.--11. " BRLEN ,Burst Read Transfer Length" "4-transfer,8-transfer,16-transfer,Continuous" textline " " bitfld.long 0x00 9. " SYNCREADDEV ,Synchronous read access device" "Asynchronous,Synchronous" bitfld.long 0x00 8. " BPM ,Burst and Page Mode Read Selection" "Normal,Burst" textline " " bitfld.long 0x00 4.--5. " MW ,Memory width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write protect" "Not protected,Protected" textline " " bitfld.long 0x00 0. " BLE ,Byte Lane Enable" "Disabled,Enabled" elif ((((d.l(asd:(0x5C002000+0xAC)))&0x1)==0x1)&&(((d.l(asd:(0x74000000+0x14)))&0x20000)==0x0)&&(((d.l(asd:(0x74000000+0x14)))&0x200)==0x0)) group.long 0x14++0x03 line.long 0x0 "EMI_BCR1,Bank 1 Control Register" bitfld.long 0x00 18.--19. " BWLEN ,Burst write transfer length" "4-transfer,8-transfer,?..." bitfld.long 0x00 17. " SYNCWRITEDEV ,Synchronous write access device" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 16. " BMWRITE ,Burst mode write" "No burst,Burst" bitfld.long 0x00 10.--11. " BRLEN ,Burst Read Transfer Length" "4-transfer,8-transfer,16-transfer,?..." textline " " bitfld.long 0x00 9. " SYNCREADDEV ,Synchronous read access device" "Asynchronous,Synchronous" bitfld.long 0x00 8. " BPM ,Burst and Page Mode Read Selection" "Normal,Burst" textline " " bitfld.long 0x00 4.--5. " MW ,Memory width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write protect" "Not protected,Protected" textline " " bitfld.long 0x00 0. " BLE ,Byte Lane Enable" "Disabled,Enabled" elif ((((d.l(asd:(0x5C002000+0xAC)))&0x1)==0x0)&&(((d.l(asd:(0x74000000+0x14)))&0x20000)==0x20000)&&(((d.l(asd:(0x74000000+0x14)))&0x200)==0x200)) group.long 0x14++0x03 line.long 0x0 "EMI_BCR1,Bank 1 Control Register" bitfld.long 0x00 18.--19. " BWLEN ,Burst write transfer length" "4-transfer,8-transfer,Reserved,Continuous burst" bitfld.long 0x00 17. " SYNCWRITEDEV ,Synchronous write access device" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 16. " BMWRITE ,Burst mode write" "No burst,Burst" bitfld.long 0x00 10.--11. " BRLEN ,Burst Read Transfer Length" "4-transfer,8-transfer,16-transfer,Continuous" textline " " bitfld.long 0x00 9. " SYNCREADDEV ,Synchronous read access device" "Asynchronous,Synchronous" bitfld.long 0x00 8. " BPM ,Burst and Page Mode Read Selection" "Normal,Burst" textline " " bitfld.long 0x00 4.--5. " MW ,Memory width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write protect" "Not protected,Protected" textline " " bitfld.long 0x00 0. " BLE ,Byte Lane Enable" "Disabled,?..." elif ((((d.l(asd:(0x5C002000+0xAC)))&0x1)==0x0)&&(((d.l(asd:(0x74000000+0x14)))&0x20000)==0x20000)&&(((d.l(asd:(0x74000000+0x14)))&0x200)==0x0)) group.long 0x14++0x03 line.long 0x0 "EMI_BCR1,Bank 1 Control Register" bitfld.long 0x00 18.--19. " BWLEN ,Burst write transfer length" "4-transfer,8-transfer,Reserved,Continuous burst" bitfld.long 0x00 17. " SYNCWRITEDEV ,Synchronous write access device" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 16. " BMWRITE ,Burst mode write" "No burst,Burst" bitfld.long 0x00 10.--11. " BRLEN ,Burst Read Transfer Length" "4-transfer,8-transfer,16-transfer,?..." textline " " bitfld.long 0x00 9. " SYNCREADDEV ,Synchronous read access device" "Asynchronous,Synchronous" bitfld.long 0x00 8. " BPM ,Burst and Page Mode Read Selection" "Normal,Burst" textline " " bitfld.long 0x00 4.--5. " MW ,Memory width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write protect" "Not protected,Protected" textline " " bitfld.long 0x00 0. " BLE ,Byte Lane Enable" "Disabled,?..." elif ((((d.l(asd:(0x5C002000+0xAC)))&0x1)==0x0)&&(((d.l(asd:(0x74000000+0x14)))&0x20000)==0x0)&&(((d.l(asd:(0x74000000+0x14)))&0x200)==0x200)) group.long 0x14++0x03 line.long 0x0 "EMI_BCR1,Bank 1 Control Register" bitfld.long 0x00 18.--19. " BWLEN ,Burst write transfer length" "4-transfer,8-transfer,?..." bitfld.long 0x00 17. " SYNCWRITEDEV ,Synchronous write access device" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 16. " BMWRITE ,Burst mode write" "No burst,Burst" bitfld.long 0x00 10.--11. " BRLEN ,Burst Read Transfer Length" "4-transfer,8-transfer,16-transfer,Continuous" textline " " bitfld.long 0x00 9. " SYNCREADDEV ,Synchronous read access device" "Asynchronous,Synchronous" bitfld.long 0x00 8. " BPM ,Burst and Page Mode Read Selection" "Normal,Burst" textline " " bitfld.long 0x00 4.--5. " MW ,Memory width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write protect" "Not protected,Protected" textline " " bitfld.long 0x00 0. " BLE ,Byte Lane Enable" "Disabled,?..." else group.long 0x14++0x03 line.long 0x0 "EMI_BCR1,Bank 1 Control Register" bitfld.long 0x00 18.--19. " BWLEN ,Burst write transfer length" "4-transfer,8-transfer,?..." bitfld.long 0x00 17. " SYNCWRITEDEV ,Synchronous write access device" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 16. " BMWRITE ,Burst mode write" "No burst,Burst" bitfld.long 0x00 10.--11. " BRLEN ,Burst Read Transfer Length" "4-transfer,8-transfer,16-transfer,?..." textline " " bitfld.long 0x00 9. " SYNCREADDEV ,Synchronous read access device" "Asynchronous,Synchronous" bitfld.long 0x00 8. " BPM ,Burst and Page Mode Read Selection" "Normal,Burst" textline " " bitfld.long 0x00 4.--5. " MW ,Memory width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write protect" "Not protected,Protected" textline " " bitfld.long 0x00 0. " BLE ,Byte Lane Enable" "Disabled,?..." endif if ((((d.l(asd:(0x5C002000+0xAC)))&0x1)==0x1)&&(((d.l(asd:(0x5C002000+0x34)))&0x40)==0x40)&&(((d.l(asd:(0x74000000+0x34)))&0x30)==0x0)&&(((d.l(asd:(0x74000000+0x34)))&0x20000)==0x20000)&&(((d.l(asd:(0x74000000+0x34)))&0x200)==0x200)) group.long 0x34++0x03 line.long 0x0 "EMI_BCR2,Bank 2 Control Register" bitfld.long 0x00 18.--19. " BWLEN ,Burst write transfer length" "4-transfer,8-transfer,Reserved,Continuous burst" bitfld.long 0x00 17. " SYNCWRITEDEV ,Synchronous write access device" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 16. " BMWRITE ,Burst mode write" "No burst,Burst" bitfld.long 0x00 10.--11. " BRLEN ,Burst Read Transfer Length" "4-transfer,8-transfer,16-transfer,Continuous" textline " " bitfld.long 0x00 9. " SYNCREADDEV ,Synchronous read access device" "Asynchronous,Synchronous" bitfld.long 0x00 8. " BPM ,Burst and Page Mode Read Selection" "Normal,Burst/Page" textline " " bitfld.long 0x00 4.--5. " MW ,Memory width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write protect" "Not protected,Protected" textline " " bitfld.long 0x00 0. " BLE ,Byte Lane Enable" "Disabled,Enabled" elif ((((d.l(asd:(0x5C002000+0xAC)))&0x1)==0x1)&&(((d.l(asd:(0x5C002000+0x34)))&0x40)==0x40)&&(((d.l(asd:(0x74000000+0x34)))&0x30)==0x0)&&(((d.l(asd:(0x74000000+0x34)))&0x20000)==0x20000)&&(((d.l(asd:(0x74000000+0x34)))&0x200)==0x0)) group.long 0x34++0x03 line.long 0x0 "EMI_BCR2,Bank 2 Control Register" bitfld.long 0x00 18.--19. " BWLEN ,Burst write transfer length" "4-transfer,8-transfer,Reserved,Continuous burst" bitfld.long 0x00 17. " SYNCWRITEDEV ,Synchronous write access device" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 16. " BMWRITE ,Burst mode write" "No burst,Burst" bitfld.long 0x00 10.--11. " BRLEN ,Burst Read Transfer Length" "4-transfer,8-transfer,16-transfer,?..." textline " " bitfld.long 0x00 9. " SYNCREADDEV ,Synchronous read access device" "Asynchronous,Synchronous" bitfld.long 0x00 8. " BPM ,Burst and Page Mode Read Selection" "Normal,Burst/Page" textline " " bitfld.long 0x00 4.--5. " MW ,Memory width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write protect" "Not protected,Protected" textline " " bitfld.long 0x00 0. " BLE ,Byte Lane Enable" "Disabled,Enabled" elif ((((d.l(asd:(0x5C002000+0xAC)))&0x1)==0x1)&&(((d.l(asd:(0x5C002000+0x34)))&0x40)==0x40)&&(((d.l(asd:(0x74000000+0x34)))&0x30)==0x0)&&(((d.l(asd:(0x74000000+0x34)))&0x20000)==0x0)&&(((d.l(asd:(0x74000000+0x34)))&0x200)==0x200)) group.long 0x34++0x03 line.long 0x0 "EMI_BCR2,Bank 2 Control Register" bitfld.long 0x00 18.--19. " BWLEN ,Burst write transfer length" "4-transfer,8-transfer,?..." bitfld.long 0x00 17. " SYNCWRITEDEV ,Synchronous write access device" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 16. " BMWRITE ,Burst mode write" "No burst,Burst" bitfld.long 0x00 10.--11. " BRLEN ,Burst Read Transfer Length" "4-transfer,8-transfer,16-transfer,Continuous" textline " " bitfld.long 0x00 9. " SYNCREADDEV ,Synchronous read access device" "Asynchronous,Synchronous" bitfld.long 0x00 8. " BPM ,Burst and Page Mode Read Selection" "Normal,Burst/Page" textline " " bitfld.long 0x00 4.--5. " MW ,Memory width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write protect" "Not protected,Protected" textline " " bitfld.long 0x00 0. " BLE ,Byte Lane Enable" "Disabled,Enabled" elif ((((d.l(asd:(0x5C002000+0xAC)))&0x1)==0x0)&&(((d.l(asd:(0x5C002000+0x34)))&0x40)==0x40)&&(((d.l(asd:(0x74000000+0x34)))&0x30)==0x0)&&(((d.l(asd:(0x74000000+0x34)))&0x20000)==0x20000)&&(((d.l(asd:(0x74000000+0x34)))&0x200)==0x200)) group.long 0x34++0x03 line.long 0x0 "EMI_BCR2,Bank 2 Control Register" bitfld.long 0x00 18.--19. " BWLEN ,Burst write transfer length" "4-transfer,8-transfer,Reserved,Continuous burst" bitfld.long 0x00 17. " SYNCWRITEDEV ,Synchronous write access device" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 16. " BMWRITE ,Burst mode write" "No burst,Burst" bitfld.long 0x00 10.--11. " BRLEN ,Burst Read Transfer Length" "4-transfer,8-transfer,16-transfer,Continuous" textline " " bitfld.long 0x00 9. " SYNCREADDEV ,Synchronous read access device" "Asynchronous,Synchronous" bitfld.long 0x00 8. " BPM ,Burst and Page Mode Read Selection" "Normal,Burst/Page" textline " " bitfld.long 0x00 4.--5. " MW ,Memory width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write protect" "Not protected,Protected" textline " " bitfld.long 0x00 0. " BLE ,Byte Lane Enable" "Disabled,?..." elif ((((d.l(asd:(0x5C002000+0xAC)))&0x1)==0x0)&&(((d.l(asd:(0x5C002000+0x34)))&0x40)==0x40)&&(((d.l(asd:(0x74000000+0x34)))&0x30)==0x0)&&(((d.l(asd:(0x74000000+0x34)))&0x20000)==0x20000)&&(((d.l(asd:(0x74000000+0x34)))&0x200)==0x0)) group.long 0x34++0x03 line.long 0x0 "EMI_BCR2,Bank 2 Control Register" bitfld.long 0x00 18.--19. " BWLEN ,Burst write transfer length" "4-transfer,8-transfer,Reserved,Continuous burst" bitfld.long 0x00 17. " SYNCWRITEDEV ,Synchronous write access device" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 16. " BMWRITE ,Burst mode write" "No burst,Burst" bitfld.long 0x00 10.--11. " BRLEN ,Burst Read Transfer Length" "4-transfer,8-transfer,16-transfer,?..." textline " " bitfld.long 0x00 9. " SYNCREADDEV ,Synchronous read access device" "Asynchronous,Synchronous" bitfld.long 0x00 8. " BPM ,Burst and Page Mode Read Selection" "Normal,Burst/Page" textline " " bitfld.long 0x00 4.--5. " MW ,Memory width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write protect" "Not protected,Protected" textline " " bitfld.long 0x00 0. " BLE ,Byte Lane Enable" "Disabled,?..." elif ((((d.l(asd:(0x5C002000+0xAC)))&0x1)==0x0)&&(((d.l(asd:(0x5C002000+0x34)))&0x40)==0x40)&&(((d.l(asd:(0x74000000+0x34)))&0x30)==0x0)&&(((d.l(asd:(0x74000000+0x34)))&0x20000)==0x0)&&(((d.l(asd:(0x74000000+0x34)))&0x200)==0x200)) group.long 0x34++0x03 line.long 0x0 "EMI_BCR2,Bank 2 Control Register" bitfld.long 0x00 18.--19. " BWLEN ,Burst write transfer length" "4-transfer,8-transfer,?..." bitfld.long 0x00 17. " SYNCWRITEDEV ,Synchronous write access device" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 16. " BMWRITE ,Burst mode write" "No burst,Burst" bitfld.long 0x00 10.--11. " BRLEN ,Burst Read Transfer Length" "4-transfer,8-transfer,16-transfer,Continuous" textline " " bitfld.long 0x00 9. " SYNCREADDEV ,Synchronous read access device" "Asynchronous,Synchronous" bitfld.long 0x00 8. " BPM ,Burst and Page Mode Read Selection" "Normal,Burst/Page" textline " " bitfld.long 0x00 4.--5. " MW ,Memory width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write protect" "Not protected,Protected" textline " " bitfld.long 0x00 0. " BLE ,Byte Lane Enable" "Disabled,?..." elif ((((d.l(asd:(0x5C002000+0xAC)))&0x1)==0x0)&&(((d.l(asd:(0x5C002000+0x34)))&0x40)==0x40)&&(((d.l(asd:(0x74000000+0x34)))&0x30)==0x0)&&(((d.l(asd:(0x74000000+0x34)))&0x20000)==0x0)&&(((d.l(asd:(0x74000000+0x34)))&0x200)==0x0)) group.long 0x34++0x03 line.long 0x0 "EMI_BCR2,Bank 2 Control Register" bitfld.long 0x00 18.--19. " BWLEN ,Burst write transfer length" "4-transfer,8-transfer,?..." bitfld.long 0x00 17. " SYNCWRITEDEV ,Synchronous write access device" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 16. " BMWRITE ,Burst mode write" "No burst,Burst" bitfld.long 0x00 10.--11. " BRLEN ,Burst Read Transfer Length" "4-transfer,8-transfer,16-transfer,?..." textline " " bitfld.long 0x00 9. " SYNCREADDEV ,Synchronous read access device" "Asynchronous,Synchronous" bitfld.long 0x00 8. " BPM ,Burst and Page Mode Read Selection" "Normal,Burst/Page" textline " " bitfld.long 0x00 4.--5. " MW ,Memory width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write protect" "Not protected,Protected" textline " " bitfld.long 0x00 0. " BLE ,Byte Lane Enable" "Disabled,?..." elif ((((d.l(asd:(0x5C002000+0xAC)))&0x1)==0x1)&&(((d.l(asd:(0x74000000+0x34)))&0x20000)==0x20000)&&(((d.l(asd:(0x74000000+0x34)))&0x200)==0x200)) group.long 0x34++0x03 line.long 0x0 "EMI_BCR2,Bank 2 Control Register" bitfld.long 0x00 18.--19. " BWLEN ,Burst write transfer length" "4-transfer,8-transfer,Reserved,Continuous burst" bitfld.long 0x00 17. " SYNCWRITEDEV ,Synchronous write access device" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 16. " BMWRITE ,Burst mode write" "No burst,Burst" bitfld.long 0x00 10.--11. " BRLEN ,Burst Read Transfer Length" "4-transfer,8-transfer,16-transfer,Continuous" textline " " bitfld.long 0x00 9. " SYNCREADDEV ,Synchronous read access device" "Asynchronous,Synchronous" bitfld.long 0x00 8. " BPM ,Burst and Page Mode Read Selection" "Normal,Burst" textline " " bitfld.long 0x00 4.--5. " MW ,Memory width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write protect" "Not protected,Protected" textline " " bitfld.long 0x00 0. " BLE ,Byte Lane Enable" "Disabled,Enabled" elif ((((d.l(asd:(0x5C002000+0xAC)))&0x1)==0x1)&&(((d.l(asd:(0x74000000+0x34)))&0x20000)==0x20000)&&(((d.l(asd:(0x74000000+0x34)))&0x200)==0x0)) group.long 0x34++0x03 line.long 0x0 "EMI_BCR2,Bank 2 Control Register" bitfld.long 0x00 18.--19. " BWLEN ,Burst write transfer length" "4-transfer,8-transfer,Reserved,Continuous burst" bitfld.long 0x00 17. " SYNCWRITEDEV ,Synchronous write access device" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 16. " BMWRITE ,Burst mode write" "No burst,Burst" bitfld.long 0x00 10.--11. " BRLEN ,Burst Read Transfer Length" "4-transfer,8-transfer,16-transfer,?..." textline " " bitfld.long 0x00 9. " SYNCREADDEV ,Synchronous read access device" "Asynchronous,Synchronous" bitfld.long 0x00 8. " BPM ,Burst and Page Mode Read Selection" "Normal,Burst" textline " " bitfld.long 0x00 4.--5. " MW ,Memory width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write protect" "Not protected,Protected" textline " " bitfld.long 0x00 0. " BLE ,Byte Lane Enable" "Disabled,Enabled" elif ((((d.l(asd:(0x5C002000+0xAC)))&0x1)==0x1)&&(((d.l(asd:(0x74000000+0x34)))&0x20000)==0x0)&&(((d.l(asd:(0x74000000+0x34)))&0x200)==0x200)) group.long 0x34++0x03 line.long 0x0 "EMI_BCR2,Bank 2 Control Register" bitfld.long 0x00 18.--19. " BWLEN ,Burst write transfer length" "4-transfer,8-transfer,?..." bitfld.long 0x00 17. " SYNCWRITEDEV ,Synchronous write access device" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 16. " BMWRITE ,Burst mode write" "No burst,Burst" bitfld.long 0x00 10.--11. " BRLEN ,Burst Read Transfer Length" "4-transfer,8-transfer,16-transfer,Continuous" textline " " bitfld.long 0x00 9. " SYNCREADDEV ,Synchronous read access device" "Asynchronous,Synchronous" bitfld.long 0x00 8. " BPM ,Burst and Page Mode Read Selection" "Normal,Burst" textline " " bitfld.long 0x00 4.--5. " MW ,Memory width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write protect" "Not protected,Protected" textline " " bitfld.long 0x00 0. " BLE ,Byte Lane Enable" "Disabled,Enabled" elif ((((d.l(asd:(0x5C002000+0xAC)))&0x1)==0x1)&&(((d.l(asd:(0x74000000+0x34)))&0x20000)==0x0)&&(((d.l(asd:(0x74000000+0x34)))&0x200)==0x0)) group.long 0x34++0x03 line.long 0x0 "EMI_BCR2,Bank 2 Control Register" bitfld.long 0x00 18.--19. " BWLEN ,Burst write transfer length" "4-transfer,8-transfer,?..." bitfld.long 0x00 17. " SYNCWRITEDEV ,Synchronous write access device" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 16. " BMWRITE ,Burst mode write" "No burst,Burst" bitfld.long 0x00 10.--11. " BRLEN ,Burst Read Transfer Length" "4-transfer,8-transfer,16-transfer,?..." textline " " bitfld.long 0x00 9. " SYNCREADDEV ,Synchronous read access device" "Asynchronous,Synchronous" bitfld.long 0x00 8. " BPM ,Burst and Page Mode Read Selection" "Normal,Burst" textline " " bitfld.long 0x00 4.--5. " MW ,Memory width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write protect" "Not protected,Protected" textline " " bitfld.long 0x00 0. " BLE ,Byte Lane Enable" "Disabled,Enabled" elif ((((d.l(asd:(0x5C002000+0xAC)))&0x1)==0x0)&&(((d.l(asd:(0x74000000+0x34)))&0x20000)==0x20000)&&(((d.l(asd:(0x74000000+0x34)))&0x200)==0x200)) group.long 0x34++0x03 line.long 0x0 "EMI_BCR2,Bank 2 Control Register" bitfld.long 0x00 18.--19. " BWLEN ,Burst write transfer length" "4-transfer,8-transfer,Reserved,Continuous burst" bitfld.long 0x00 17. " SYNCWRITEDEV ,Synchronous write access device" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 16. " BMWRITE ,Burst mode write" "No burst,Burst" bitfld.long 0x00 10.--11. " BRLEN ,Burst Read Transfer Length" "4-transfer,8-transfer,16-transfer,Continuous" textline " " bitfld.long 0x00 9. " SYNCREADDEV ,Synchronous read access device" "Asynchronous,Synchronous" bitfld.long 0x00 8. " BPM ,Burst and Page Mode Read Selection" "Normal,Burst" textline " " bitfld.long 0x00 4.--5. " MW ,Memory width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write protect" "Not protected,Protected" textline " " bitfld.long 0x00 0. " BLE ,Byte Lane Enable" "Disabled,?..." elif ((((d.l(asd:(0x5C002000+0xAC)))&0x1)==0x0)&&(((d.l(asd:(0x74000000+0x34)))&0x20000)==0x20000)&&(((d.l(asd:(0x74000000+0x34)))&0x200)==0x0)) group.long 0x34++0x03 line.long 0x0 "EMI_BCR2,Bank 2 Control Register" bitfld.long 0x00 18.--19. " BWLEN ,Burst write transfer length" "4-transfer,8-transfer,Reserved,Continuous burst" bitfld.long 0x00 17. " SYNCWRITEDEV ,Synchronous write access device" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 16. " BMWRITE ,Burst mode write" "No burst,Burst" bitfld.long 0x00 10.--11. " BRLEN ,Burst Read Transfer Length" "4-transfer,8-transfer,16-transfer,?..." textline " " bitfld.long 0x00 9. " SYNCREADDEV ,Synchronous read access device" "Asynchronous,Synchronous" bitfld.long 0x00 8. " BPM ,Burst and Page Mode Read Selection" "Normal,Burst" textline " " bitfld.long 0x00 4.--5. " MW ,Memory width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write protect" "Not protected,Protected" textline " " bitfld.long 0x00 0. " BLE ,Byte Lane Enable" "Disabled,?..." elif ((((d.l(asd:(0x5C002000+0xAC)))&0x1)==0x0)&&(((d.l(asd:(0x74000000+0x34)))&0x20000)==0x0)&&(((d.l(asd:(0x74000000+0x34)))&0x200)==0x200)) group.long 0x34++0x03 line.long 0x0 "EMI_BCR2,Bank 2 Control Register" bitfld.long 0x00 18.--19. " BWLEN ,Burst write transfer length" "4-transfer,8-transfer,?..." bitfld.long 0x00 17. " SYNCWRITEDEV ,Synchronous write access device" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 16. " BMWRITE ,Burst mode write" "No burst,Burst" bitfld.long 0x00 10.--11. " BRLEN ,Burst Read Transfer Length" "4-transfer,8-transfer,16-transfer,Continuous" textline " " bitfld.long 0x00 9. " SYNCREADDEV ,Synchronous read access device" "Asynchronous,Synchronous" bitfld.long 0x00 8. " BPM ,Burst and Page Mode Read Selection" "Normal,Burst" textline " " bitfld.long 0x00 4.--5. " MW ,Memory width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write protect" "Not protected,Protected" textline " " bitfld.long 0x00 0. " BLE ,Byte Lane Enable" "Disabled,?..." else group.long 0x34++0x03 line.long 0x0 "EMI_BCR2,Bank 2 Control Register" bitfld.long 0x00 18.--19. " BWLEN ,Burst write transfer length" "4-transfer,8-transfer,?..." bitfld.long 0x00 17. " SYNCWRITEDEV ,Synchronous write access device" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 16. " BMWRITE ,Burst mode write" "No burst,Burst" bitfld.long 0x00 10.--11. " BRLEN ,Burst Read Transfer Length" "4-transfer,8-transfer,16-transfer,?..." textline " " bitfld.long 0x00 9. " SYNCREADDEV ,Synchronous read access device" "Asynchronous,Synchronous" bitfld.long 0x00 8. " BPM ,Burst and Page Mode Read Selection" "Normal,Burst" textline " " bitfld.long 0x00 4.--5. " MW ,Memory width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write protect" "Not protected,Protected" textline " " bitfld.long 0x00 0. " BLE ,Byte Lane Enable" "Disabled,?..." endif if ((((d.l(asd:(0x5C002000+0xAC)))&0x1)==0x1)&&(((d.l(asd:(0x5C002000+0x34)))&0x40)==0x40)&&(((d.l(asd:(0x74000000+0x54)))&0x30)==0x0)&&(((d.l(asd:(0x74000000+0x54)))&0x20000)==0x20000)&&(((d.l(asd:(0x74000000+0x54)))&0x200)==0x200)) group.long 0x54++0x03 line.long 0x0 "EMI_BCR3,Bank 3 Control Register" bitfld.long 0x00 18.--19. " BWLEN ,Burst write transfer length" "4-transfer,8-transfer,Reserved,Continuous burst" bitfld.long 0x00 17. " SYNCWRITEDEV ,Synchronous write access device" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 16. " BMWRITE ,Burst mode write" "No burst,Burst" bitfld.long 0x00 10.--11. " BRLEN ,Burst Read Transfer Length" "4-transfer,8-transfer,16-transfer,Continuous" textline " " bitfld.long 0x00 9. " SYNCREADDEV ,Synchronous read access device" "Asynchronous,Synchronous" bitfld.long 0x00 8. " BPM ,Burst and Page Mode Read Selection" "Normal,Burst/Page" textline " " bitfld.long 0x00 4.--5. " MW ,Memory width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write protect" "Not protected,Protected" textline " " bitfld.long 0x00 0. " BLE ,Byte Lane Enable" "Disabled,Enabled" elif ((((d.l(asd:(0x5C002000+0xAC)))&0x1)==0x1)&&(((d.l(asd:(0x5C002000+0x34)))&0x40)==0x40)&&(((d.l(asd:(0x74000000+0x54)))&0x30)==0x0)&&(((d.l(asd:(0x74000000+0x54)))&0x20000)==0x20000)&&(((d.l(asd:(0x74000000+0x54)))&0x200)==0x0)) group.long 0x54++0x03 line.long 0x0 "EMI_BCR3,Bank 3 Control Register" bitfld.long 0x00 18.--19. " BWLEN ,Burst write transfer length" "4-transfer,8-transfer,Reserved,Continuous burst" bitfld.long 0x00 17. " SYNCWRITEDEV ,Synchronous write access device" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 16. " BMWRITE ,Burst mode write" "No burst,Burst" bitfld.long 0x00 10.--11. " BRLEN ,Burst Read Transfer Length" "4-transfer,8-transfer,16-transfer,?..." textline " " bitfld.long 0x00 9. " SYNCREADDEV ,Synchronous read access device" "Asynchronous,Synchronous" bitfld.long 0x00 8. " BPM ,Burst and Page Mode Read Selection" "Normal,Burst/Page" textline " " bitfld.long 0x00 4.--5. " MW ,Memory width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write protect" "Not protected,Protected" textline " " bitfld.long 0x00 0. " BLE ,Byte Lane Enable" "Disabled,Enabled" elif ((((d.l(asd:(0x5C002000+0xAC)))&0x1)==0x1)&&(((d.l(asd:(0x5C002000+0x34)))&0x40)==0x40)&&(((d.l(asd:(0x74000000+0x54)))&0x30)==0x0)&&(((d.l(asd:(0x74000000+0x54)))&0x20000)==0x0)&&(((d.l(asd:(0x74000000+0x54)))&0x200)==0x200)) group.long 0x54++0x03 line.long 0x0 "EMI_BCR3,Bank 3 Control Register" bitfld.long 0x00 18.--19. " BWLEN ,Burst write transfer length" "4-transfer,8-transfer,?..." bitfld.long 0x00 17. " SYNCWRITEDEV ,Synchronous write access device" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 16. " BMWRITE ,Burst mode write" "No burst,Burst" bitfld.long 0x00 10.--11. " BRLEN ,Burst Read Transfer Length" "4-transfer,8-transfer,16-transfer,Continuous" textline " " bitfld.long 0x00 9. " SYNCREADDEV ,Synchronous read access device" "Asynchronous,Synchronous" bitfld.long 0x00 8. " BPM ,Burst and Page Mode Read Selection" "Normal,Burst/Page" textline " " bitfld.long 0x00 4.--5. " MW ,Memory width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write protect" "Not protected,Protected" textline " " bitfld.long 0x00 0. " BLE ,Byte Lane Enable" "Disabled,Enabled" elif ((((d.l(asd:(0x5C002000+0xAC)))&0x1)==0x0)&&(((d.l(asd:(0x5C002000+0x34)))&0x40)==0x40)&&(((d.l(asd:(0x74000000+0x54)))&0x30)==0x0)&&(((d.l(asd:(0x74000000+0x54)))&0x20000)==0x20000)&&(((d.l(asd:(0x74000000+0x54)))&0x200)==0x200)) group.long 0x54++0x03 line.long 0x0 "EMI_BCR3,Bank 3 Control Register" bitfld.long 0x00 18.--19. " BWLEN ,Burst write transfer length" "4-transfer,8-transfer,Reserved,Continuous burst" bitfld.long 0x00 17. " SYNCWRITEDEV ,Synchronous write access device" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 16. " BMWRITE ,Burst mode write" "No burst,Burst" bitfld.long 0x00 10.--11. " BRLEN ,Burst Read Transfer Length" "4-transfer,8-transfer,16-transfer,Continuous" textline " " bitfld.long 0x00 9. " SYNCREADDEV ,Synchronous read access device" "Asynchronous,Synchronous" bitfld.long 0x00 8. " BPM ,Burst and Page Mode Read Selection" "Normal,Burst/Page" textline " " bitfld.long 0x00 4.--5. " MW ,Memory width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write protect" "Not protected,Protected" textline " " bitfld.long 0x00 0. " BLE ,Byte Lane Enable" "Disabled,?..." elif ((((d.l(asd:(0x5C002000+0xAC)))&0x1)==0x0)&&(((d.l(asd:(0x5C002000+0x34)))&0x40)==0x40)&&(((d.l(asd:(0x74000000+0x54)))&0x30)==0x0)&&(((d.l(asd:(0x74000000+0x54)))&0x20000)==0x20000)&&(((d.l(asd:(0x74000000+0x54)))&0x200)==0x0)) group.long 0x54++0x03 line.long 0x0 "EMI_BCR3,Bank 3 Control Register" bitfld.long 0x00 18.--19. " BWLEN ,Burst write transfer length" "4-transfer,8-transfer,Reserved,Continuous burst" bitfld.long 0x00 17. " SYNCWRITEDEV ,Synchronous write access device" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 16. " BMWRITE ,Burst mode write" "No burst,Burst" bitfld.long 0x00 10.--11. " BRLEN ,Burst Read Transfer Length" "4-transfer,8-transfer,16-transfer,?..." textline " " bitfld.long 0x00 9. " SYNCREADDEV ,Synchronous read access device" "Asynchronous,Synchronous" bitfld.long 0x00 8. " BPM ,Burst and Page Mode Read Selection" "Normal,Burst/Page" textline " " bitfld.long 0x00 4.--5. " MW ,Memory width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write protect" "Not protected,Protected" textline " " bitfld.long 0x00 0. " BLE ,Byte Lane Enable" "Disabled,?..." elif ((((d.l(asd:(0x5C002000+0xAC)))&0x1)==0x0)&&(((d.l(asd:(0x5C002000+0x34)))&0x40)==0x40)&&(((d.l(asd:(0x74000000+0x54)))&0x30)==0x0)&&(((d.l(asd:(0x74000000+0x54)))&0x20000)==0x0)&&(((d.l(asd:(0x74000000+0x54)))&0x200)==0x200)) group.long 0x54++0x03 line.long 0x0 "EMI_BCR3,Bank 3 Control Register" bitfld.long 0x00 18.--19. " BWLEN ,Burst write transfer length" "4-transfer,8-transfer,?..." bitfld.long 0x00 17. " SYNCWRITEDEV ,Synchronous write access device" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 16. " BMWRITE ,Burst mode write" "No burst,Burst" bitfld.long 0x00 10.--11. " BRLEN ,Burst Read Transfer Length" "4-transfer,8-transfer,16-transfer,Continuous" textline " " bitfld.long 0x00 9. " SYNCREADDEV ,Synchronous read access device" "Asynchronous,Synchronous" bitfld.long 0x00 8. " BPM ,Burst and Page Mode Read Selection" "Normal,Burst/Page" textline " " bitfld.long 0x00 4.--5. " MW ,Memory width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write protect" "Not protected,Protected" textline " " bitfld.long 0x00 0. " BLE ,Byte Lane Enable" "Disabled,?..." elif ((((d.l(asd:(0x5C002000+0xAC)))&0x1)==0x0)&&(((d.l(asd:(0x5C002000+0x34)))&0x40)==0x40)&&(((d.l(asd:(0x74000000+0x54)))&0x30)==0x0)&&(((d.l(asd:(0x74000000+0x54)))&0x20000)==0x0)&&(((d.l(asd:(0x74000000+0x54)))&0x200)==0x0)) group.long 0x54++0x03 line.long 0x0 "EMI_BCR3,Bank 3 Control Register" bitfld.long 0x00 18.--19. " BWLEN ,Burst write transfer length" "4-transfer,8-transfer,?..." bitfld.long 0x00 17. " SYNCWRITEDEV ,Synchronous write access device" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 16. " BMWRITE ,Burst mode write" "No burst,Burst" bitfld.long 0x00 10.--11. " BRLEN ,Burst Read Transfer Length" "4-transfer,8-transfer,16-transfer,?..." textline " " bitfld.long 0x00 9. " SYNCREADDEV ,Synchronous read access device" "Asynchronous,Synchronous" bitfld.long 0x00 8. " BPM ,Burst and Page Mode Read Selection" "Normal,Burst/Page" textline " " bitfld.long 0x00 4.--5. " MW ,Memory width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write protect" "Not protected,Protected" textline " " bitfld.long 0x00 0. " BLE ,Byte Lane Enable" "Disabled,?..." elif ((((d.l(asd:(0x5C002000+0xAC)))&0x1)==0x1)&&(((d.l(asd:(0x74000000+0x54)))&0x20000)==0x20000)&&(((d.l(asd:(0x74000000+0x54)))&0x200)==0x200)) group.long 0x54++0x03 line.long 0x0 "EMI_BCR3,Bank 3 Control Register" bitfld.long 0x00 18.--19. " BWLEN ,Burst write transfer length" "4-transfer,8-transfer,Reserved,Continuous burst" bitfld.long 0x00 17. " SYNCWRITEDEV ,Synchronous write access device" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 16. " BMWRITE ,Burst mode write" "No burst,Burst" bitfld.long 0x00 10.--11. " BRLEN ,Burst Read Transfer Length" "4-transfer,8-transfer,16-transfer,Continuous" textline " " bitfld.long 0x00 9. " SYNCREADDEV ,Synchronous read access device" "Asynchronous,Synchronous" bitfld.long 0x00 8. " BPM ,Burst and Page Mode Read Selection" "Normal,Burst" textline " " bitfld.long 0x00 4.--5. " MW ,Memory width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write protect" "Not protected,Protected" textline " " bitfld.long 0x00 0. " BLE ,Byte Lane Enable" "Disabled,Enabled" elif ((((d.l(asd:(0x5C002000+0xAC)))&0x1)==0x1)&&(((d.l(asd:(0x74000000+0x54)))&0x20000)==0x20000)&&(((d.l(asd:(0x74000000+0x54)))&0x200)==0x0)) group.long 0x54++0x03 line.long 0x0 "EMI_BCR3,Bank 3 Control Register" bitfld.long 0x00 18.--19. " BWLEN ,Burst write transfer length" "4-transfer,8-transfer,Reserved,Continuous burst" bitfld.long 0x00 17. " SYNCWRITEDEV ,Synchronous write access device" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 16. " BMWRITE ,Burst mode write" "No burst,Burst" bitfld.long 0x00 10.--11. " BRLEN ,Burst Read Transfer Length" "4-transfer,8-transfer,16-transfer,?..." textline " " bitfld.long 0x00 9. " SYNCREADDEV ,Synchronous read access device" "Asynchronous,Synchronous" bitfld.long 0x00 8. " BPM ,Burst and Page Mode Read Selection" "Normal,Burst" textline " " bitfld.long 0x00 4.--5. " MW ,Memory width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write protect" "Not protected,Protected" textline " " bitfld.long 0x00 0. " BLE ,Byte Lane Enable" "Disabled,Enabled" elif ((((d.l(asd:(0x5C002000+0xAC)))&0x1)==0x1)&&(((d.l(asd:(0x74000000+0x54)))&0x20000)==0x0)&&(((d.l(asd:(0x74000000+0x54)))&0x200)==0x200)) group.long 0x54++0x03 line.long 0x0 "EMI_BCR3,Bank 3 Control Register" bitfld.long 0x00 18.--19. " BWLEN ,Burst write transfer length" "4-transfer,8-transfer,?..." bitfld.long 0x00 17. " SYNCWRITEDEV ,Synchronous write access device" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 16. " BMWRITE ,Burst mode write" "No burst,Burst" bitfld.long 0x00 10.--11. " BRLEN ,Burst Read Transfer Length" "4-transfer,8-transfer,16-transfer,Continuous" textline " " bitfld.long 0x00 9. " SYNCREADDEV ,Synchronous read access device" "Asynchronous,Synchronous" bitfld.long 0x00 8. " BPM ,Burst and Page Mode Read Selection" "Normal,Burst" textline " " bitfld.long 0x00 4.--5. " MW ,Memory width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write protect" "Not protected,Protected" textline " " bitfld.long 0x00 0. " BLE ,Byte Lane Enable" "Disabled,Enabled" elif ((((d.l(asd:(0x5C002000+0xAC)))&0x1)==0x1)&&(((d.l(asd:(0x74000000+0x54)))&0x20000)==0x0)&&(((d.l(asd:(0x74000000+0x54)))&0x200)==0x0)) group.long 0x54++0x03 line.long 0x0 "EMI_BCR3,Bank 3 Control Register" bitfld.long 0x00 18.--19. " BWLEN ,Burst write transfer length" "4-transfer,8-transfer,?..." bitfld.long 0x00 17. " SYNCWRITEDEV ,Synchronous write access device" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 16. " BMWRITE ,Burst mode write" "No burst,Burst" bitfld.long 0x00 10.--11. " BRLEN ,Burst Read Transfer Length" "4-transfer,8-transfer,16-transfer,?..." textline " " bitfld.long 0x00 9. " SYNCREADDEV ,Synchronous read access device" "Asynchronous,Synchronous" bitfld.long 0x00 8. " BPM ,Burst and Page Mode Read Selection" "Normal,Burst" textline " " bitfld.long 0x00 4.--5. " MW ,Memory width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write protect" "Not protected,Protected" textline " " bitfld.long 0x00 0. " BLE ,Byte Lane Enable" "Disabled,Enabled" elif ((((d.l(asd:(0x5C002000+0xAC)))&0x1)==0x0)&&(((d.l(asd:(0x74000000+0x54)))&0x20000)==0x20000)&&(((d.l(asd:(0x74000000+0x54)))&0x200)==0x200)) group.long 0x54++0x03 line.long 0x0 "EMI_BCR3,Bank 3 Control Register" bitfld.long 0x00 18.--19. " BWLEN ,Burst write transfer length" "4-transfer,8-transfer,Reserved,Continuous burst" bitfld.long 0x00 17. " SYNCWRITEDEV ,Synchronous write access device" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 16. " BMWRITE ,Burst mode write" "No burst,Burst" bitfld.long 0x00 10.--11. " BRLEN ,Burst Read Transfer Length" "4-transfer,8-transfer,16-transfer,Continuous" textline " " bitfld.long 0x00 9. " SYNCREADDEV ,Synchronous read access device" "Asynchronous,Synchronous" bitfld.long 0x00 8. " BPM ,Burst and Page Mode Read Selection" "Normal,Burst" textline " " bitfld.long 0x00 4.--5. " MW ,Memory width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write protect" "Not protected,Protected" textline " " bitfld.long 0x00 0. " BLE ,Byte Lane Enable" "Disabled,?..." elif ((((d.l(asd:(0x5C002000+0xAC)))&0x1)==0x0)&&(((d.l(asd:(0x74000000+0x54)))&0x20000)==0x20000)&&(((d.l(asd:(0x74000000+0x54)))&0x200)==0x0)) group.long 0x54++0x03 line.long 0x0 "EMI_BCR3,Bank 3 Control Register" bitfld.long 0x00 18.--19. " BWLEN ,Burst write transfer length" "4-transfer,8-transfer,Reserved,Continuous burst" bitfld.long 0x00 17. " SYNCWRITEDEV ,Synchronous write access device" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 16. " BMWRITE ,Burst mode write" "No burst,Burst" bitfld.long 0x00 10.--11. " BRLEN ,Burst Read Transfer Length" "4-transfer,8-transfer,16-transfer,?..." textline " " bitfld.long 0x00 9. " SYNCREADDEV ,Synchronous read access device" "Asynchronous,Synchronous" bitfld.long 0x00 8. " BPM ,Burst and Page Mode Read Selection" "Normal,Burst" textline " " bitfld.long 0x00 4.--5. " MW ,Memory width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write protect" "Not protected,Protected" textline " " bitfld.long 0x00 0. " BLE ,Byte Lane Enable" "Disabled,?..." elif ((((d.l(asd:(0x5C002000+0xAC)))&0x1)==0x0)&&(((d.l(asd:(0x74000000+0x54)))&0x20000)==0x0)&&(((d.l(asd:(0x74000000+0x54)))&0x200)==0x200)) group.long 0x54++0x03 line.long 0x0 "EMI_BCR3,Bank 3 Control Register" bitfld.long 0x00 18.--19. " BWLEN ,Burst write transfer length" "4-transfer,8-transfer,?..." bitfld.long 0x00 17. " SYNCWRITEDEV ,Synchronous write access device" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 16. " BMWRITE ,Burst mode write" "No burst,Burst" bitfld.long 0x00 10.--11. " BRLEN ,Burst Read Transfer Length" "4-transfer,8-transfer,16-transfer,Continuous" textline " " bitfld.long 0x00 9. " SYNCREADDEV ,Synchronous read access device" "Asynchronous,Synchronous" bitfld.long 0x00 8. " BPM ,Burst and Page Mode Read Selection" "Normal,Burst" textline " " bitfld.long 0x00 4.--5. " MW ,Memory width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write protect" "Not protected,Protected" textline " " bitfld.long 0x00 0. " BLE ,Byte Lane Enable" "Disabled,?..." else group.long 0x54++0x03 line.long 0x0 "EMI_BCR3,Bank 3 Control Register" bitfld.long 0x00 18.--19. " BWLEN ,Burst write transfer length" "4-transfer,8-transfer,?..." bitfld.long 0x00 17. " SYNCWRITEDEV ,Synchronous write access device" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 16. " BMWRITE ,Burst mode write" "No burst,Burst" bitfld.long 0x00 10.--11. " BRLEN ,Burst Read Transfer Length" "4-transfer,8-transfer,16-transfer,?..." textline " " bitfld.long 0x00 9. " SYNCREADDEV ,Synchronous read access device" "Asynchronous,Synchronous" bitfld.long 0x00 8. " BPM ,Burst and Page Mode Read Selection" "Normal,Burst" textline " " bitfld.long 0x00 4.--5. " MW ,Memory width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write protect" "Not protected,Protected" textline " " bitfld.long 0x00 0. " BLE ,Byte Lane Enable" "Disabled,?..." endif if ((((d.l(asd:(0x5C002000+0xAC)))&0x1)==0x1)&&(((d.l(asd:(0x5C002000+0x34)))&0x40)==0x40)&&(((d.l(asd:(0x74000000+0xF4)))&0x30)==0x0)&&(((d.l(asd:(0x74000000+0xF4)))&0x20000)==0x20000)&&(((d.l(asd:(0x74000000+0xF4)))&0x200)==0x200)) group.long 0xF4++0x03 line.long 0x0 "EMI_BCR0,Bank 0 Control Register" bitfld.long 0x00 18.--19. " BWLEN ,Burst write transfer length" "4-transfer,8-transfer,Reserved,Continuous burst" bitfld.long 0x00 17. " SYNCWRITEDEV ,Synchronous write access device" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 16. " BMWRITE ,Burst mode write" "No burst,Burst" bitfld.long 0x00 10.--11. " BRLEN ,Burst Read Transfer Length" "4-transfer,8-transfer,16-transfer,Continuous" textline " " bitfld.long 0x00 9. " SYNCREADDEV ,Synchronous read access device" "Asynchronous,Synchronous" bitfld.long 0x00 8. " BPM ,Burst and Page Mode Read Selection" "Normal,Burst/Page" textline " " bitfld.long 0x00 4.--5. " MW ,Memory width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write protect" "Not protected,Protected" textline " " bitfld.long 0x00 0. " BLE ,Byte Lane Enable" "Disabled,Enabled" elif ((((d.l(asd:(0x5C002000+0xAC)))&0x1)==0x1)&&(((d.l(asd:(0x5C002000+0x34)))&0x40)==0x40)&&(((d.l(asd:(0x74000000+0xF4)))&0x30)==0x0)&&(((d.l(asd:(0x74000000+0xF4)))&0x20000)==0x20000)&&(((d.l(asd:(0x74000000+0xF4)))&0x200)==0x0)) group.long 0xF4++0x03 line.long 0x0 "EMI_BCR0,Bank 0 Control Register" bitfld.long 0x00 18.--19. " BWLEN ,Burst write transfer length" "4-transfer,8-transfer,Reserved,Continuous burst" bitfld.long 0x00 17. " SYNCWRITEDEV ,Synchronous write access device" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 16. " BMWRITE ,Burst mode write" "No burst,Burst" bitfld.long 0x00 10.--11. " BRLEN ,Burst Read Transfer Length" "4-transfer,8-transfer,16-transfer,?..." textline " " bitfld.long 0x00 9. " SYNCREADDEV ,Synchronous read access device" "Asynchronous,Synchronous" bitfld.long 0x00 8. " BPM ,Burst and Page Mode Read Selection" "Normal,Burst/Page" textline " " bitfld.long 0x00 4.--5. " MW ,Memory width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write protect" "Not protected,Protected" textline " " bitfld.long 0x00 0. " BLE ,Byte Lane Enable" "Disabled,Enabled" elif ((((d.l(asd:(0x5C002000+0xAC)))&0x1)==0x1)&&(((d.l(asd:(0x5C002000+0x34)))&0x40)==0x40)&&(((d.l(asd:(0x74000000+0xF4)))&0x30)==0x0)&&(((d.l(asd:(0x74000000+0xF4)))&0x20000)==0x0)&&(((d.l(asd:(0x74000000+0xF4)))&0x200)==0x200)) group.long 0xF4++0x03 line.long 0x0 "EMI_BCR0,Bank 0 Control Register" bitfld.long 0x00 18.--19. " BWLEN ,Burst write transfer length" "4-transfer,8-transfer,?..." bitfld.long 0x00 17. " SYNCWRITEDEV ,Synchronous write access device" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 16. " BMWRITE ,Burst mode write" "No burst,Burst" bitfld.long 0x00 10.--11. " BRLEN ,Burst Read Transfer Length" "4-transfer,8-transfer,16-transfer,Continuous" textline " " bitfld.long 0x00 9. " SYNCREADDEV ,Synchronous read access device" "Asynchronous,Synchronous" bitfld.long 0x00 8. " BPM ,Burst and Page Mode Read Selection" "Normal,Burst/Page" textline " " bitfld.long 0x00 4.--5. " MW ,Memory width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write protect" "Not protected,Protected" textline " " bitfld.long 0x00 0. " BLE ,Byte Lane Enable" "Disabled,Enabled" elif ((((d.l(asd:(0x5C002000+0xAC)))&0x1)==0x0)&&(((d.l(asd:(0x5C002000+0x34)))&0x40)==0x40)&&(((d.l(asd:(0x74000000+0xF4)))&0x30)==0x0)&&(((d.l(asd:(0x74000000+0xF4)))&0x20000)==0x20000)&&(((d.l(asd:(0x74000000+0xF4)))&0x200)==0x200)) group.long 0xF4++0x03 line.long 0x0 "EMI_BCR0,Bank 0 Control Register" bitfld.long 0x00 18.--19. " BWLEN ,Burst write transfer length" "4-transfer,8-transfer,Reserved,Continuous burst" bitfld.long 0x00 17. " SYNCWRITEDEV ,Synchronous write access device" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 16. " BMWRITE ,Burst mode write" "No burst,Burst" bitfld.long 0x00 10.--11. " BRLEN ,Burst Read Transfer Length" "4-transfer,8-transfer,16-transfer,Continuous" textline " " bitfld.long 0x00 9. " SYNCREADDEV ,Synchronous read access device" "Asynchronous,Synchronous" bitfld.long 0x00 8. " BPM ,Burst and Page Mode Read Selection" "Normal,Burst/Page" textline " " bitfld.long 0x00 4.--5. " MW ,Memory width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write protect" "Not protected,Protected" textline " " bitfld.long 0x00 0. " BLE ,Byte Lane Enable" "Disabled,?..." elif ((((d.l(asd:(0x5C002000+0xAC)))&0x1)==0x0)&&(((d.l(asd:(0x5C002000+0x34)))&0x40)==0x40)&&(((d.l(asd:(0x74000000+0xF4)))&0x30)==0x0)&&(((d.l(asd:(0x74000000+0xF4)))&0x20000)==0x20000)&&(((d.l(asd:(0x74000000+0xF4)))&0x200)==0x0)) group.long 0xF4++0x03 line.long 0x0 "EMI_BCR0,Bank 0 Control Register" bitfld.long 0x00 18.--19. " BWLEN ,Burst write transfer length" "4-transfer,8-transfer,Reserved,Continuous burst" bitfld.long 0x00 17. " SYNCWRITEDEV ,Synchronous write access device" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 16. " BMWRITE ,Burst mode write" "No burst,Burst" bitfld.long 0x00 10.--11. " BRLEN ,Burst Read Transfer Length" "4-transfer,8-transfer,16-transfer,?..." textline " " bitfld.long 0x00 9. " SYNCREADDEV ,Synchronous read access device" "Asynchronous,Synchronous" bitfld.long 0x00 8. " BPM ,Burst and Page Mode Read Selection" "Normal,Burst/Page" textline " " bitfld.long 0x00 4.--5. " MW ,Memory width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write protect" "Not protected,Protected" textline " " bitfld.long 0x00 0. " BLE ,Byte Lane Enable" "Disabled,?..." elif ((((d.l(asd:(0x5C002000+0xAC)))&0x1)==0x0)&&(((d.l(asd:(0x5C002000+0x34)))&0x40)==0x40)&&(((d.l(asd:(0x74000000+0xF4)))&0x30)==0x0)&&(((d.l(asd:(0x74000000+0xF4)))&0x20000)==0x0)&&(((d.l(asd:(0x74000000+0xF4)))&0x200)==0x200)) group.long 0xF4++0x03 line.long 0x0 "EMI_BCR0,Bank 0 Control Register" bitfld.long 0x00 18.--19. " BWLEN ,Burst write transfer length" "4-transfer,8-transfer,?..." bitfld.long 0x00 17. " SYNCWRITEDEV ,Synchronous write access device" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 16. " BMWRITE ,Burst mode write" "No burst,Burst" bitfld.long 0x00 10.--11. " BRLEN ,Burst Read Transfer Length" "4-transfer,8-transfer,16-transfer,Continuous" textline " " bitfld.long 0x00 9. " SYNCREADDEV ,Synchronous read access device" "Asynchronous,Synchronous" bitfld.long 0x00 8. " BPM ,Burst and Page Mode Read Selection" "Normal,Burst/Page" textline " " bitfld.long 0x00 4.--5. " MW ,Memory width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write protect" "Not protected,Protected" textline " " bitfld.long 0x00 0. " BLE ,Byte Lane Enable" "Disabled,?..." elif ((((d.l(asd:(0x5C002000+0xAC)))&0x1)==0x0)&&(((d.l(asd:(0x5C002000+0x34)))&0x40)==0x40)&&(((d.l(asd:(0x74000000+0xF4)))&0x30)==0x0)&&(((d.l(asd:(0x74000000+0xF4)))&0x20000)==0x0)&&(((d.l(asd:(0x74000000+0xF4)))&0x200)==0x0)) group.long 0xF4++0x03 line.long 0x0 "EMI_BCR0,Bank 0 Control Register" bitfld.long 0x00 18.--19. " BWLEN ,Burst write transfer length" "4-transfer,8-transfer,?..." bitfld.long 0x00 17. " SYNCWRITEDEV ,Synchronous write access device" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 16. " BMWRITE ,Burst mode write" "No burst,Burst" bitfld.long 0x00 10.--11. " BRLEN ,Burst Read Transfer Length" "4-transfer,8-transfer,16-transfer,?..." textline " " bitfld.long 0x00 9. " SYNCREADDEV ,Synchronous read access device" "Asynchronous,Synchronous" bitfld.long 0x00 8. " BPM ,Burst and Page Mode Read Selection" "Normal,Burst/Page" textline " " bitfld.long 0x00 4.--5. " MW ,Memory width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write protect" "Not protected,Protected" textline " " bitfld.long 0x00 0. " BLE ,Byte Lane Enable" "Disabled,?..." elif ((((d.l(asd:(0x5C002000+0xAC)))&0x1)==0x1)&&(((d.l(asd:(0x74000000+0xF4)))&0x20000)==0x20000)&&(((d.l(asd:(0x74000000+0xF4)))&0x200)==0x200)) group.long 0xF4++0x03 line.long 0x0 "EMI_BCR0,Bank 0 Control Register" bitfld.long 0x00 18.--19. " BWLEN ,Burst write transfer length" "4-transfer,8-transfer,Reserved,Continuous burst" bitfld.long 0x00 17. " SYNCWRITEDEV ,Synchronous write access device" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 16. " BMWRITE ,Burst mode write" "No burst,Burst" bitfld.long 0x00 10.--11. " BRLEN ,Burst Read Transfer Length" "4-transfer,8-transfer,16-transfer,Continuous" textline " " bitfld.long 0x00 9. " SYNCREADDEV ,Synchronous read access device" "Asynchronous,Synchronous" bitfld.long 0x00 8. " BPM ,Burst and Page Mode Read Selection" "Normal,Burst" textline " " bitfld.long 0x00 4.--5. " MW ,Memory width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write protect" "Not protected,Protected" textline " " bitfld.long 0x00 0. " BLE ,Byte Lane Enable" "Disabled,Enabled" elif ((((d.l(asd:(0x5C002000+0xAC)))&0x1)==0x1)&&(((d.l(asd:(0x74000000+0xF4)))&0x20000)==0x20000)&&(((d.l(asd:(0x74000000+0xF4)))&0x200)==0x0)) group.long 0xF4++0x03 line.long 0x0 "EMI_BCR0,Bank 0 Control Register" bitfld.long 0x00 18.--19. " BWLEN ,Burst write transfer length" "4-transfer,8-transfer,Reserved,Continuous burst" bitfld.long 0x00 17. " SYNCWRITEDEV ,Synchronous write access device" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 16. " BMWRITE ,Burst mode write" "No burst,Burst" bitfld.long 0x00 10.--11. " BRLEN ,Burst Read Transfer Length" "4-transfer,8-transfer,16-transfer,?..." textline " " bitfld.long 0x00 9. " SYNCREADDEV ,Synchronous read access device" "Asynchronous,Synchronous" bitfld.long 0x00 8. " BPM ,Burst and Page Mode Read Selection" "Normal,Burst" textline " " bitfld.long 0x00 4.--5. " MW ,Memory width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write protect" "Not protected,Protected" textline " " bitfld.long 0x00 0. " BLE ,Byte Lane Enable" "Disabled,Enabled" elif ((((d.l(asd:(0x5C002000+0xAC)))&0x1)==0x1)&&(((d.l(asd:(0x74000000+0xF4)))&0x20000)==0x0)&&(((d.l(asd:(0x74000000+0xF4)))&0x200)==0x200)) group.long 0xF4++0x03 line.long 0x0 "EMI_BCR0,Bank 0 Control Register" bitfld.long 0x00 18.--19. " BWLEN ,Burst write transfer length" "4-transfer,8-transfer,?..." bitfld.long 0x00 17. " SYNCWRITEDEV ,Synchronous write access device" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 16. " BMWRITE ,Burst mode write" "No burst,Burst" bitfld.long 0x00 10.--11. " BRLEN ,Burst Read Transfer Length" "4-transfer,8-transfer,16-transfer,Continuous" textline " " bitfld.long 0x00 9. " SYNCREADDEV ,Synchronous read access device" "Asynchronous,Synchronous" bitfld.long 0x00 8. " BPM ,Burst and Page Mode Read Selection" "Normal,Burst" textline " " bitfld.long 0x00 4.--5. " MW ,Memory width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write protect" "Not protected,Protected" textline " " bitfld.long 0x00 0. " BLE ,Byte Lane Enable" "Disabled,Enabled" elif ((((d.l(asd:(0x5C002000+0xAC)))&0x1)==0x1)&&(((d.l(asd:(0x74000000+0xF4)))&0x20000)==0x0)&&(((d.l(asd:(0x74000000+0xF4)))&0x200)==0x0)) group.long 0xF4++0x03 line.long 0x0 "EMI_BCR0,Bank 0 Control Register" bitfld.long 0x00 18.--19. " BWLEN ,Burst write transfer length" "4-transfer,8-transfer,?..." bitfld.long 0x00 17. " SYNCWRITEDEV ,Synchronous write access device" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 16. " BMWRITE ,Burst mode write" "No burst,Burst" bitfld.long 0x00 10.--11. " BRLEN ,Burst Read Transfer Length" "4-transfer,8-transfer,16-transfer,?..." textline " " bitfld.long 0x00 9. " SYNCREADDEV ,Synchronous read access device" "Asynchronous,Synchronous" bitfld.long 0x00 8. " BPM ,Burst and Page Mode Read Selection" "Normal,Burst" textline " " bitfld.long 0x00 4.--5. " MW ,Memory width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write protect" "Not protected,Protected" textline " " bitfld.long 0x00 0. " BLE ,Byte Lane Enable" "Disabled,Enabled" elif ((((d.l(asd:(0x5C002000+0xAC)))&0x1)==0x0)&&(((d.l(asd:(0x74000000+0xF4)))&0x20000)==0x20000)&&(((d.l(asd:(0x74000000+0xF4)))&0x200)==0x200)) group.long 0xF4++0x03 line.long 0x0 "EMI_BCR0,Bank 0 Control Register" bitfld.long 0x00 18.--19. " BWLEN ,Burst write transfer length" "4-transfer,8-transfer,Reserved,Continuous burst" bitfld.long 0x00 17. " SYNCWRITEDEV ,Synchronous write access device" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 16. " BMWRITE ,Burst mode write" "No burst,Burst" bitfld.long 0x00 10.--11. " BRLEN ,Burst Read Transfer Length" "4-transfer,8-transfer,16-transfer,Continuous" textline " " bitfld.long 0x00 9. " SYNCREADDEV ,Synchronous read access device" "Asynchronous,Synchronous" bitfld.long 0x00 8. " BPM ,Burst and Page Mode Read Selection" "Normal,Burst" textline " " bitfld.long 0x00 4.--5. " MW ,Memory width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write protect" "Not protected,Protected" textline " " bitfld.long 0x00 0. " BLE ,Byte Lane Enable" "Disabled,?..." elif ((((d.l(asd:(0x5C002000+0xAC)))&0x1)==0x0)&&(((d.l(asd:(0x74000000+0xF4)))&0x20000)==0x20000)&&(((d.l(asd:(0x74000000+0xF4)))&0x200)==0x0)) group.long 0xF4++0x03 line.long 0x0 "EMI_BCR0,Bank 0 Control Register" bitfld.long 0x00 18.--19. " BWLEN ,Burst write transfer length" "4-transfer,8-transfer,Reserved,Continuous burst" bitfld.long 0x00 17. " SYNCWRITEDEV ,Synchronous write access device" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 16. " BMWRITE ,Burst mode write" "No burst,Burst" bitfld.long 0x00 10.--11. " BRLEN ,Burst Read Transfer Length" "4-transfer,8-transfer,16-transfer,?..." textline " " bitfld.long 0x00 9. " SYNCREADDEV ,Synchronous read access device" "Asynchronous,Synchronous" bitfld.long 0x00 8. " BPM ,Burst and Page Mode Read Selection" "Normal,Burst" textline " " bitfld.long 0x00 4.--5. " MW ,Memory width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write protect" "Not protected,Protected" textline " " bitfld.long 0x00 0. " BLE ,Byte Lane Enable" "Disabled,?..." elif ((((d.l(asd:(0x5C002000+0xAC)))&0x1)==0x0)&&(((d.l(asd:(0x74000000+0xF4)))&0x20000)==0x0)&&(((d.l(asd:(0x74000000+0xF4)))&0x200)==0x200)) group.long 0xF4++0x03 line.long 0x0 "EMI_BCR0,Bank 0 Control Register" bitfld.long 0x00 18.--19. " BWLEN ,Burst write transfer length" "4-transfer,8-transfer,?..." bitfld.long 0x00 17. " SYNCWRITEDEV ,Synchronous write access device" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 16. " BMWRITE ,Burst mode write" "No burst,Burst" bitfld.long 0x00 10.--11. " BRLEN ,Burst Read Transfer Length" "4-transfer,8-transfer,16-transfer,Continuous" textline " " bitfld.long 0x00 9. " SYNCREADDEV ,Synchronous read access device" "Asynchronous,Synchronous" bitfld.long 0x00 8. " BPM ,Burst and Page Mode Read Selection" "Normal,Burst" textline " " bitfld.long 0x00 4.--5. " MW ,Memory width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write protect" "Not protected,Protected" textline " " bitfld.long 0x00 0. " BLE ,Byte Lane Enable" "Disabled,?..." else group.long 0xF4++0x03 line.long 0x0 "EMI_BCR0,Bank 0 Control Register" bitfld.long 0x00 18.--19. " BWLEN ,Burst write transfer length" "4-transfer,8-transfer,?..." bitfld.long 0x00 17. " SYNCWRITEDEV ,Synchronous write access device" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 16. " BMWRITE ,Burst mode write" "No burst,Burst" bitfld.long 0x00 10.--11. " BRLEN ,Burst Read Transfer Length" "4-transfer,8-transfer,16-transfer,?..." textline " " bitfld.long 0x00 9. " SYNCREADDEV ,Synchronous read access device" "Asynchronous,Synchronous" bitfld.long 0x00 8. " BPM ,Burst and Page Mode Read Selection" "Normal,Burst" textline " " bitfld.long 0x00 4.--5. " MW ,Memory width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write protect" "Not protected,Protected" textline " " bitfld.long 0x00 0. " BLE ,Byte Lane Enable" "Disabled,?..." endif group.long 0x1C++0x03 line.long 0x0 "EMI_BRDCR1,Bank 1 burst read wait delay register" bitfld.long 0x0 0.--4. " WSTBRD[4:0] ,Burst read wait states" "No state,1 state,2 states,3 states,4 states,5 states,6 states,7 states,8 states,9 states,10 states,11 states,12 states,13 states,14 states,15 states,16 states,17 states,18 states,19 states,20 states,21 states,22 states,23 states,24 states,25 states,26 states,27 states,28 states,29 states,30 states,31 states" group.long 0x3C++0x03 line.long 0x0 "EMI_BRDCR2,Bank 2 burst read wait delay register" bitfld.long 0x0 0.--4. " WSTBRD[4:0] ,Burst read wait states" "No state,1 state,2 states,3 states,4 states,5 states,6 states,7 states,8 states,9 states,10 states,11 states,12 states,13 states,14 states,15 states,16 states,17 states,18 states,19 states,20 states,21 states,22 states,23 states,24 states,25 states,26 states,27 states,28 states,29 states,30 states,31 states" group.long 0x5C++0x03 line.long 0x0 "EMI_BRDCR3,Bank 3 burst read wait delay register" bitfld.long 0x0 0.--4. " WSTBRD[4:0] ,Burst read wait states" "No state,1 state,2 states,3 states,4 states,5 states,6 states,7 states,8 states,9 states,10 states,11 states,12 states,13 states,14 states,15 states,16 states,17 states,18 states,19 states,20 states,21 states,22 states,23 states,24 states,25 states,26 states,27 states,28 states,29 states,30 states,31 states" group.long 0xFC++0x03 line.long 0x0 "EMI_BRDCR0,Bank 0 burst read wait delay register" bitfld.long 0x0 0.--4. " WSTBRD[4:0] ,Burst read wait states" "No state,1 state,2 states,3 states,4 states,5 states,6 states,7 states,8 states,9 states,10 states,11 states,12 states,13 states,14 states,15 states,16 states,17 states,18 states,19 states,20 states,21 states,22 states,23 states,24 states,25 states,26 states,27 states,28 states,29 states,30 states,31 states" if (((d.l(asd:(0x5C002000+0xAC)))&0x2)==0x2) group.long 0x204++0x3 line.long 0x00 "EMI_CCR,Clock control register" bitfld.long 0x00 0. " BCLKEN ,BCLK enable" "Active during bus asscess,?..." else group.long 0x204++0x3 line.long 0x00 "EMI_CCR,Clock control register" bitfld.long 0x00 0. " BCLKEN ,BCLK enable" "Active during bus asscess,Always running" endif else if ((((data.long(asd:(0x74000000+0x14)))&0x30)==0x0)&&(((data.long(asd:(0x5C002000+0x34)))&0x40)==0x40)) group.long 0x14++0x03 line.long 0x0 "EMI_BCR1,Bank 1 Control Register" bitfld.long 0x00 10.--11. " PLEN[1:0] ,Page Mode Read Transfer Length" "4-transfer,8-transfer,?..." bitfld.long 0x00 8. " PM ,Page Mode Read Selection" "Normal,Page mode" bitfld.long 0x00 4.--5. " MW[1:0] ,Memory Width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write Protect" "Not protected,Protected" else group.long 0x14++0x3 line.long 0x0 "EMI_BCR1,Bank 1 Control Register" bitfld.long 0x00 10.--11. " PLEN[1:0] ,Page Mode Read Transfer Length" "4-transfer,8-transfer,?..." bitfld.long 0x00 8. " PM ,Page Mode Read Selection" "Normal,?..." bitfld.long 0x00 4.--5. " MW[1:0] ,Memory Width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write Protect" "Not protected,Protected" endif if ((((data.long(asd:(0x74000000+0x34)))&0x30)==0x0)&&(((data.long(asd:(0x5C002000+0x34)))&0x40)==0x40)) group.long 0x34++0x03 line.long 0x0 "EMI_BCR2,Bank 2 Control Register" bitfld.long 0x00 10.--11. " PLEN[1:0] ,Page Mode Read Transfer Length" "4-transfer,8-transfer,?..." bitfld.long 0x00 8. " PM ,Page Mode Read Selection" "Normal,Page mode" bitfld.long 0x00 4.--5. " MW[1:0] ,Memory Width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write Protect" "Not protected,Protected" else group.long 0x34++0x3 line.long 0x0 "EMI_BCR2,Bank 2 Control Register" bitfld.long 0x00 10.--11. " PLEN[1:0] ,Page Mode Read Transfer Length" "4-transfer,8-transfer,?..." bitfld.long 0x00 8. " PM ,Page Mode Read Selection" "Normal,?..." bitfld.long 0x00 4.--5. " MW[1:0] ,Memory Width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write Protect" "Not protected,Protected" endif if ((((data.long(asd:(0x74000000+0x54)))&0x30)==0x0)&&(((data.long(asd:(0x5C002000+0x34)))&0x40)==0x40)) group.long 0x54++0x03 line.long 0x0 "EMI_BCR3,Bank 3 Control Register" bitfld.long 0x00 10.--11. " PLEN[1:0] ,Page Mode Read Transfer Length" "4-transfer,8-transfer,?..." bitfld.long 0x00 8. " PM ,Page Mode Read Selection" "Normal,Page mode" bitfld.long 0x00 4.--5. " MW[1:0] ,Memory Width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write Protect" "Not protected,Protected" else group.long 0x54++0x3 line.long 0x0 "EMI_BCR3,Bank 3 Control Register" bitfld.long 0x00 10.--11. " PLEN[1:0] ,Page Mode Read Transfer Length" "4-transfer,8-transfer,?..." bitfld.long 0x00 8. " PM ,Page Mode Read Selection" "Normal,?..." bitfld.long 0x00 4.--5. " MW[1:0] ,Memory Width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write Protect" "Not protected,Protected" endif if ((((data.long(asd:(0x74000000+0xF4)))&0x30)==0x0)&&(((data.long(asd:(0x5C002000+0x34)))&0x40)==0x40)) group.long 0xF4++0x03 line.long 0x0 "EMI_BCR0,Bank 0 Control Register" bitfld.long 0x00 10.--11. " PLEN[1:0] ,Page Mode Read Transfer Length" "4-transfer,8-transfer,?..." bitfld.long 0x00 8. " PM ,Page Mode Read Selection" "Normal,Page mode" bitfld.long 0x00 4.--5. " MW[1:0] ,Memory Width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write Protect" "Not protected,Protected" else group.long 0xF4++0x3 line.long 0x0 "EMI_BCR0,Bank 0 Control Register" bitfld.long 0x00 10.--11. " PLEN[1:0] ,Page Mode Read Transfer Length" "4-transfer,8-transfer,?..." bitfld.long 0x00 8. " PM ,Page Mode Read Selection" "Normal,?..." bitfld.long 0x00 4.--5. " MW[1:0] ,Memory Width" "8-bit,16-bit,?..." bitfld.long 0x00 3. " WP ,Write Protect" "Not protected,Protected" endif endif width 0xB endif tree.end tree "SCU (System Control Unit)" base asd:0x5C002000 width 0xF sif (cpuis("STR910FA*")||cpuis("STR911FA*")||cpuis("STR912FA*")) group.long 0x0++0x7 line.long 0x0 "SCU_CLKCNTR,Clock Control Register" sif (cpuis("STR910FAW*")||cpuis("STR910FAZ*")||cpuis("STR911FAW*")||cpuis("STR911FAZ*")||cpuis("STR912FAW*")||cpuis("STR912FAZ*")) bitfld.long 0x00 17.--18. " EMIRATIO ,External Memory Interface Ratio" "HCLK,HCLK/2,?..." bitfld.long 0x00 16. " FMISEL ,Flash Memory Interface Clock Divider" "RCLK,RCLK/2" textline " " else bitfld.long 0x00 16. " FMISEL ,Flash Memory Interface Clock Divider" "RCLK,RCLK/2" textline " " endif bitfld.long 0x00 14. " TIM23SEL ,Timers 2 and 3 external clock enable" "Disabled,Enabled" bitfld.long 0x00 13. " TIM01SEL ,Timers 0 and 1 external clock enable" "Disabled,Enabled" textline " " sif (cpuis("STR912*")) bitfld.long 0x00 12. " PHYSEL ,MII_PHYCLK Enable" "Disabled,Enabled" textline " " endif sif (cpuis("STR911*")||cpuis("STR912*")) bitfld.long 0x00 10.--11. " USBSEL ,USB 48 MHz Clock Selection" "fMSTR,fMSTR/2,USB_CLK48M,?..." textline " " endif bitfld.long 0x00 9. " BRSEL ,Baud Rate Clock Selection" "fMSTR/2,fMSTR" bitfld.long 0x00 7.--8. " APBDIV ,PCLK Divider" "RCLK,RCLK/2,RCLK/4,RCLK/8" textline " " bitfld.long 0x00 5.--6. " AHBDIV ,HCLK Divider" "RCLK,RCLK/2,RCLK/4,?..." bitfld.long 0x00 2.--4. " RCLKDIV ,RCLK Divider" "fMSTR,fMSTR/2,fMSTR/4,fMSTR/8,fMSTR/16,fMSTR/1024,?..." textline " " bitfld.long 0x00 0.--1. " MCLKSEL ,Main Clock Source" "fPLL,fRTC,fOSC,?..." line.long 0x4 "SCU_PLLCONF,PLL Configuration Register" bitfld.long 0x04 19. " PLL_EN ,PLL Enable" "Disabled,Enabled" bitfld.long 0x04 16.--18. " PLL_PDIV ,PLL Post-Divider" "0,1,2,3,4,5,?..." textline " " hexmask.long.byte 0x04 8.--15. 1. " PLL_NDIV ,PLL Feedback Divider" hexmask.long.byte 0x04 0.--7. 1. " PLL_MDIV ,PLL Pre-Divider" group.long 0x8++0xB line.long 0x0 "SCU_SYSSTATUS,System Status Register" eventfld.long 0x00 5. " SRAM_ERR ,SRAM Error Event Flag" "Not Occurred,Occurred" eventfld.long 0x00 4. " ACK_PFQBC ,ACK PFQBC Event Flag" "Not Occurred,Occurred" textline " " eventfld.long 0x00 3. " LVD_RST ,LVD Reset Event Flag" "Not Occurred,Occurred" eventfld.long 0x00 2. " WDG_RST ,WDG Reset Event Flag" "Not Occurred,Occurred" textline " " eventfld.long 0x00 1. " LOCK_LOST ,LOCK LOST Event Flag" "Not Occurred,Occurred" eventfld.long 0x00 0. " LOCK ,LOCK Event Flag" "Not Occurred,Occurred" line.long 0x4 "SCU_PWRMNG,Power Management Register" bitfld.long 0x4 4. " FLASH_PD_DBG ,Flash Power Down in Debug Mode" "No power down,Power down" bitfld.long 0x4 3. " CPU_INTR ,Special Interrupt Mode" "RCLKDIV,Full Speed" textline " " bitfld.long 0x4 0.--2. " PWR_MODE ,Power Mode Control" "Run,Idle,Sleep,?..." line.long 0x8 "SCU_ITCMSK,Interrupt Mask Register" bitfld.long 0x08 4. " MSK_LVD_RST ,LVD Reset Interrupt Mask" "Not masked,Masked" bitfld.long 0x08 3. " MSK_SRAM_ERR ,SRAM Error Interrupt Mask" "Not masked,Masked" textline " " bitfld.long 0x08 2. " MSK_ACK_PFQBC ,ACK PFQBC Interrupt Mask" "Not masked,Masked" bitfld.long 0x08 1. " MSK_LOCK_LOST ,LOCK LOST Interrupt Mask" "Not masked,Masked" textline " " bitfld.long 0x08 0. " MSK_LOCK ,LOCK Interrupt Mask" "Not masked,Masked" width 0xB tree "Peripheral Registers" group.long 0x14++0x3 line.long 0x0 "SCU_PCGR0,Peripheral Clock Gating Register 0" sif (cpuis("STR912*")) bitfld.long 0x00 11. " MAC ,Ethernet Peripheral Clock Gating" "Stopped,Running" textline " " endif sif (cpuis("STR911*")||cpuis("STR912*")) bitfld.long 0x00 10. " USB48M ,USB 48 MHz Clock Gating" "Stopped,Running" textline " " bitfld.long 0x00 9. " USB ,USB Peripheral Clock Gating" "Stopped,Running" textline " " endif bitfld.long 0x00 8. " DMA ,DMA Peripheral Clock Gating" "Stopped,Running" textline " " sif (cpuis("STR910FAW*")||cpuis("STR910FAZ*")||cpuis("STR911FAW*")||cpuis("STR911FAZ*")||cpuis("STR912FAW*")||cpuis("STR912FAZ*")) bitfld.long 0x00 7. " EXT_MEM_CLK ,External Memory Clock Gating" "Stopped,Running" bitfld.long 0x00 6. " EMI ,EMI Peripheral Clock Gating" "Stopped,Running" textline " " endif bitfld.long 0x00 5. " VIC ,VIC Peripheral Clock Gating" "Stopped,Running" bitfld.long 0x00 4. " SRAM_ARBITER ,SRAM Arbiter Clock Gating" "Stopped,Running" textline " " bitfld.long 0x00 3. " SRAM ,SRAM Clock Gating" "Stopped,Running" bitfld.long 0x00 1. " PQFBC ,PQFBC Clock Gating" "Stopped,Running" textline " " bitfld.long 0x00 0. " FMI ,FMI Clock Gating" "Stopped,Running" group.long 0x18++0x3 line.long 0x0 "SCU_PCGR1,Peripheral Clock Gating Register 1" bitfld.long 0x00 24. " RTC ,RTC Clock Gating" "Stopped,Running" bitfld.long 0x0 23. " GPIO9 ,GPIO9 Port Clock Gating" "Stopped,Running" textline " " bitfld.long 0x0 22. " GPIO8 ,GPIO8 Port Clock Gating" "Stopped,Running" bitfld.long 0x0 21. " GPIO7 ,GPIO7 Port Clock Gating" "Stopped,Running" textline " " bitfld.long 0x0 20. " GPIO6 ,GPIO6 Port Clock Gating" "Stopped,Running" bitfld.long 0x0 19. " GPIO5 ,GPIO5 Port Clock Gating" "Stopped,Running" textline " " bitfld.long 0x0 18. " GPIO4 ,GPIO4 Port Clock Gating" "Stopped,Running" bitfld.long 0x0 17. " GPIO3 ,GPIO3 Port Clock Gating" "Stopped,Running" textline " " bitfld.long 0x0 16. " GPIO2 ,GPIO2 Port Clock Gating" "Stopped,Running" bitfld.long 0x0 15. " GPIO1 ,GPIO1 Port Clock Gating" "Stopped,Running" textline " " bitfld.long 0x0 14. " GPIO0 ,GPIO0 Port Clock Gating" "Stopped,Running" bitfld.long 0x00 13. " WIU ,WIU Peripheral Clock Gating" "Stopped,Running" textline " " bitfld.long 0x00 11. " ADC ,ADC Clock Gating" "Stopped,Running" bitfld.long 0x00 10. " CAN ,CAN Peripheral Clock Gating" "Stopped,Running" textline " " bitfld.long 0x00 9. " SSP1 ,SSP1 Peripheral Clock Gating" "Stopped,Running" bitfld.long 0x00 8. " SSP0 ,SSP0 Peripheral Clock Gating" "Stopped,Running" textline " " bitfld.long 0x00 7. " I2C1 ,I2C1 Peripheral Clock Gating" "Stopped,Running" bitfld.long 0x00 6. " I2C0 ,I2C0 Peripheral Clock Gating" "Stopped,Running" textline " " bitfld.long 0x00 5. " UART2 ,UART2 Peripheral Clock Gating" "Stopped,Running" bitfld.long 0x00 4. " UART1 ,UART1 Peripheral Clock Gating" "Stopped,Running" textline " " bitfld.long 0x00 3. " UART0 ,UART0 Peripheral Clock Gating" "Stopped,Running" bitfld.long 0x00 2. " MC ,Motor Control Peripheral Clock Gating" "Stopped,Running" textline " " bitfld.long 0x00 1. " TIM23 ,Timers 2 and 3 Clock Gating" "Stopped,Running" bitfld.long 0x00 0. " TIM01 ,Timers 0 and 1 Clock Gating" "Stopped,Running" group.long 0x1C++0x3 line.long 0x0 "SCU_PRR0,Peripheral Reset Register 0" bitfld.long 0x00 12. " RST_PFQBC_AHB ,PFQBC AHB Reset" "Reset,No reset" textline " " sif (cpuis("STR912*")) bitfld.long 0x00 11. " RST_MAC ,Ethernet Peripheral Reset" "Reset,No reset" textline " " endif sif (cpuis("STR911*")||cpuis("STR912*")) bitfld.long 0x00 9. " RST_USB ,USB Peripheral Reset" "Reset,No reset" textline " " endif bitfld.long 0x00 8. " RST_DMA ,DMA Peripheral Reset" "Reset,No reset" textline " " sif (cpuis("STR910FAW*")||cpuis("STR910FAZ*")||cpuis("STR911FAW*")||cpuis("STR911FAZ*")||cpuis("STR912FAW*")||cpuis("STR912FAZ*")) bitfld.long 0x00 6. " RST_EMI ,EMI Peripheral Reset" "Reset,No reset" textline " " endif bitfld.long 0x00 5. " RST_VIC ,VIC Peripheral Reset" "Reset,No reset" textline " " bitfld.long 0x00 4. " RST_SRAM_ARBITER ,SRAM Arbiter Reset" "Reset,No reset" textline " " bitfld.long 0x00 1. " RST_PQFBC ,PQFBC Reset" "Reset,No reset" textline " " bitfld.long 0x00 0. " RST_FMI ,FMI Reset" "Reset,No reset" group.long 0x20++0x3 line.long 0x0 "SCU_PRR1,Peripheral Reset Register 1" bitfld.long 0x00 24. " RTC ,RTC Reset" "Reset,No reset" bitfld.long 0x0 23. " GPIO9 ,GPIO9 Port Reset" "Reset,No reset" textline " " bitfld.long 0x0 22. " GPIO8 ,GPIO8 Port Reset" "Reset,No reset" bitfld.long 0x0 21. " GPIO7 ,GPIO7 Port Reset" "Reset,No reset" textline " " bitfld.long 0x0 20. " GPIO6 ,GPIO6 Port Reset" "Reset,No reset" bitfld.long 0x0 19. " GPIO5 ,GPIO5 Port Reset" "Reset,No reset" textline " " bitfld.long 0x0 18. " GPIO4 ,GPIO4 Port Reset" "Reset,No reset" bitfld.long 0x0 17. " GPIO3 ,GPIO3 Port Reset" "Reset,No reset" textline " " bitfld.long 0x0 16. " GPIO2 ,GPIO2 Port Reset" "Reset,No reset" bitfld.long 0x0 15. " GPIO1 ,GPIO1 Port Reset" "Reset,No reset" textline " " bitfld.long 0x0 14. " GPIO0 ,GPIO0 Port Reset" "Reset,No reset" bitfld.long 0x00 13. " WIU ,WIU Peripheral Reset" "Reset,No reset" textline " " bitfld.long 0x00 11. " ADC ,ADC Reset" "Reset,No reset" bitfld.long 0x00 10. " CAN ,CAN Peripheral Reset" "Reset,No reset" textline " " bitfld.long 0x00 9. " SSP1 ,SSP1 Peripheral Reset" "Reset,No reset" bitfld.long 0x00 8. " SSP0 ,SSP0 Peripheral Reset" "Reset,No reset" textline " " bitfld.long 0x00 7. " I2C1 ,I2C1 Peripheral Reset" "Reset,No reset" bitfld.long 0x00 6. " I2C0 ,I2C0 Peripheral Reset" "Reset,No reset" textline " " bitfld.long 0x00 5. " UART2 ,UART2 Peripheral Reset" "Reset,No reset" bitfld.long 0x00 4. " UART1 ,UART1 Peripheral Reset" "Reset,No reset" textline " " bitfld.long 0x00 3. " UART0 ,UART0 Peripheral Reset" "Reset,No reset" bitfld.long 0x00 2. " MC ,Motor Control Peripheral Reset" "Reset,No reset" textline " " bitfld.long 0x00 1. " TIM23 ,Timers 2 and 3 Reset" "Reset,No reset" bitfld.long 0x00 0. " TIM01 ,Timers 0 and 1 Reset" "Reset,No reset" tree.end width 0xC tree "Gating Registers" textline " " group.long 0x24++0x3 line.long 0x0 "SCU_MGR0,Idle Mode Gating Mask Register 0" sif (cpuis("STR912*")) bitfld.long 0x00 11. " MSK_MAC ,Ethernet Peripheral Gating Mask" "Stopped,Running" textline " " endif sif (cpuis("STR911*")||cpuis("STR912*")) bitfld.long 0x00 10. " MSK_USB48M ,USB 48 MHz Clock Gating Mask" "Stopped,Running" textline " " bitfld.long 0x00 9. " MSK_USB ,USB Peripheral Clock Gating Mask" "Stopped,Running" textline " " endif bitfld.long 0x00 8. " MSK_DMA ,DMA Peripheral Clock Gating Mask" "Stopped,Running" textline " " sif (cpuis("STR910FAW*")||cpuis("STR910FAZ*")||cpuis("STR911FAW*")||cpuis("STR911FAZ*")||cpuis("STR912FAW*")||cpuis("STR912FAZ*")) bitfld.long 0x00 7. " MSK_EXT_MEM_CLK ,External Memory Clock Gating Mask" "Stopped,Running" textline " " bitfld.long 0x00 6. " MSK_EMI ,EMI Peripheral Clock Gating Mask" "Stopped,Running" textline " " endif bitfld.long 0x00 5. " MSK_VIC ,VIC Peripheral Clock Gating Mask" "Stopped,Running" bitfld.long 0x00 4. " MSK_SRAM_ARBITER ,SRAM Arbiter Clock Gating Mask" "Stopped,Running" textline " " bitfld.long 0x00 3. " MSK_SRAM ,SRAM Clock Gating Mask" "Stopped,Running" bitfld.long 0x00 1. " MSK_PQFBC ,PQFBC Clock Gating Mask" "Stopped,Running" group.long 0x28++0x3 line.long 0x0 "SCU_MGR1,Idle Mode Gating Mask Register 1" bitfld.long 0x00 24. " RTC ,RTC Clock Gating Mask" "Stopped,Running" bitfld.long 0x0 23. " GPIO9 ,GPIO9 Port Clock Gating Mask" "Stopped,Running" textline " " bitfld.long 0x0 22. " GPIO8 ,GPIO8 Port Clock Gating Mask" "Stopped,Running" bitfld.long 0x0 21. " GPIO7 ,GPIO7 Port Clock Gating Mask" "Stopped,Running" textline " " bitfld.long 0x0 20. " GPIO6 ,GPIO6 Port Clock Gating Mask" "Stopped,Running" bitfld.long 0x0 19. " GPIO5 ,GPIO5 Port Clock Gating Mask" "Stopped,Running" textline " " bitfld.long 0x0 18. " GPIO4 ,GPIO4 Port Clock Gating Mask" "Stopped,Running" bitfld.long 0x0 17. " GPIO3 ,GPIO3 Port Clock Gating Mask" "Stopped,Running" textline " " bitfld.long 0x0 16. " GPIO2 ,GPIO2 Port Clock Gating Mask" "Stopped,Running" bitfld.long 0x0 15. " GPIO1 ,GPIO1 Port Clock Gating Mask" "Stopped,Running" textline " " bitfld.long 0x0 14. " GPIO0 ,GPIO0 Port Clock Gating Mask" "Stopped,Running" bitfld.long 0x00 13. " WIU ,WIU Peripheral Clock Gating Mask" "Stopped,Running" textline " " bitfld.long 0x00 12. " WDG ,WDG Peripheral Clock Gating Mask" "Stopped,Running" bitfld.long 0x00 11. " ADC ,ADC Clock Gating Mask" "Stopped,Running" textline " " bitfld.long 0x00 10. " CAN ,CAN Peripheral Clock Gating Mask" "Stopped,Running" bitfld.long 0x00 9. " SSP1 ,SSP1 Peripheral Clock Gating Mask" "Stopped,Running" textline " " bitfld.long 0x00 8. " SSP0 ,SSP0 Peripheral Clock Gating Mask" "Stopped,Running" bitfld.long 0x00 7. " I2C1 ,I2C1 Peripheral Clock Gating Mask" "Stopped,Running" textline " " bitfld.long 0x00 6. " I2C0 ,I2C0 Peripheral Clock Gating Mask" "Stopped,Running" bitfld.long 0x00 5. " UART2 ,UART2 Peripheral Clock Gating Mask" "Stopped,Running" textline " " bitfld.long 0x00 4. " UART1 ,UART1 Peripheral Clock Gating Mask" "Stopped,Running" bitfld.long 0x00 3. " UART0 ,UART0 Peripheral Clock Gating Mask" "Stopped,Running" textline " " bitfld.long 0x00 2. " MC ,Motor Control Peripheral Clock Gating Mask" "Stopped,Running" bitfld.long 0x00 1. " TIM23 ,Timers 2 and 3 Clock Gating Mask" "Stopped,Running" textline " " bitfld.long 0x00 0. " TIM01 ,Timers 0 and 1 Clock Gating Mask" "Stopped,Running" group.long 0x2C++0x3 line.long 0x0 "SCU_PECGR0,Peripheral Emulation Clock Gating Register 0" sif (cpuis("STR912*")) bitfld.long 0x00 11. " MAC ,Ethernet Peripheral Clock Gating (emulation mode)" "Stopped,Running" textline " " endif sif (cpuis("STR911*")||cpuis("STR912*")) bitfld.long 0x00 10. " USB48M ,USB 48 MHz Clock Gating (emulation mode)" "Stopped,Running" textline " " bitfld.long 0x00 9. " USB ,USB Peripheral Clock Gating (emulation mode)" "Stopped,Running" textline " " endif bitfld.long 0x00 8. " DMA ,DMA Peripheral Clock Gating (emulation mode)" "Stopped,Running" textline " " sif (cpuis("STR910FAW*")||cpuis("STR910FAZ*")||cpuis("STR911FAW*")||cpuis("STR911FAZ*")||cpuis("STR912FAW*")||cpuis("STR912FAZ*")) bitfld.long 0x00 7. " EXT_MEM_CLK ,External Memory Clock Gating (emulation mode)" "Stopped,Running" textline " " bitfld.long 0x00 6. " EMI ,EMI Peripheral Clock Gating (emulation mode)" "Stopped,Running" endif textline " " bitfld.long 0x00 5. " VIC ,VIC Peripheral Clock Gating (emulation mode)" "Stopped,Running" bitfld.long 0x00 4. " SRAM_ARBITER ,SRAM Arbiter Clock Gating (emulation mode)" "Stopped,Running" textline " " bitfld.long 0x00 3. " SRAM ,SRAM Clock Gating (emulation mode)" "Stopped,Running" bitfld.long 0x00 1. " PQFBC ,PQFBC Clock Gating (emulation mode)" "Stopped,Running" textline " " bitfld.long 0x00 0. " FMI ,FMI Clock Gating (emulation mode)" "Stopped,Running" group.long 0x30++0x3 line.long 0x0 "SCU_PECGR1,Peripheral Emulation Clock Gating Register 1" bitfld.long 0x00 23. " GPIO9 ,GPIO9 Port Clock Gating (emulation mode)" "Stopped,Running" bitfld.long 0x00 22. " GPIO8 ,GPIO8 Port Clock Gating (emulation mode)" "Stopped,Running" textline " " bitfld.long 0x00 21. " GPIO7 ,GPIO7 Port Clock Gating (emulation mode)" "Stopped,Running" bitfld.long 0x00 20. " GPIO6 ,GPIO6 Port Clock Gating (emulation mode)" "Stopped,Running" textline " " bitfld.long 0x00 19. " GPIO5 ,GPIO5 Port Clock Gating (emulation mode)" "Stopped,Running" bitfld.long 0x00 18. " GPIO4 ,GPIO4 Port Clock Gating (emulation mode)" "Stopped,Running" textline " " bitfld.long 0x00 17. " GPIO3 ,GPIO3 Port Clock Gating (emulation mode)" "Stopped,Running" bitfld.long 0x00 16. " GPIO2 ,GPIO3 Port Clock Gating (emulation mode)" "Stopped,Running" textline " " bitfld.long 0x00 15. " GPIO1 ,GPIO1 Port Clock Gating (emulation mode)" "Stopped,Running" bitfld.long 0x00 14. " GPIO0 ,GPIO0 Port Clock Gating (emulation mode)" "Stopped,Running" textline " " bitfld.long 0x00 13. " WIU ,WIU Peripheral Clock Gating (emulation mode)" "Stopped,Running" bitfld.long 0x00 12. " WDG ,WDG Peripheral Clock Gating (emulation mode)" "Stopped,Running" textline " " bitfld.long 0x00 11. " ADC ,ADC Clock Gating (emulation mode)" "Stopped,Running" bitfld.long 0x00 10. " CAN ,CAN Peripheral Clock Gating (emulation mode)" "Stopped,Running" textline " " bitfld.long 0x00 9. " SSP1 ,SSP1 Peripheral Clock Gating (emulation mode)" "Stopped,Running" bitfld.long 0x00 8. " SSP0 ,SSP0 Peripheral Clock Gating (emulation mode)" "Stopped,Running" textline " " bitfld.long 0x00 7. " I2C1 ,I2C1 Peripheral Clock Gating (emulation mode)" "Stopped,Running" bitfld.long 0x00 6. " I2C0 ,I2C0 Peripheral Clock Gating (emulation mode)" "Stopped,Running" textline " " bitfld.long 0x00 5. " UART2 ,UART2 Peripheral Clock Gating (emulation mode)" "Stopped,Running" bitfld.long 0x00 4. " UART1 ,UART1 Peripheral Clock Gating (emulation mode)" "Stopped,Running" textline " " bitfld.long 0x00 3. " UART0 ,UART0 Peripheral Clock Gating (emulation mode)" "Stopped,Running" bitfld.long 0x0 2. " MC ,Motor Control Peripheral Clock Gating (emulation mode)" "Stopped,Running" textline " " bitfld.long 0x0 1. " TIM23 ,Timers 2 and 3 Clock Gating (emulation mode)" "Stopped,Running" bitfld.long 0x0 0. " TIM01 ,Timers 0 and 1 Clock Gating (emulation mode)" "Stopped,Running" tree.end textline " " width 0xB group.long 0x34++0x3 line.long 0x0 "SCU_SCR0,System Configuration Register 0" bitfld.long 0x00 14. " P30_SELEDBG ,GPIO Port 3 External Debug Configuration" "Not for EDR/ETM,For EDR/ETM" bitfld.long 0x00 13. " EXT_ETMT_EDBGR ,ETM Trigger/External Debug Selection" "Debug Request,ETM Trigger" textline " " bitfld.long 0x0 12. " UART_IRDA2 ,UART2 IrDA Mode Selection" "UART,IrDA" bitfld.long 0x0 11. " UART_IRDA1 ,UART1 IrDA Mode Selection" "UART,IrDA" textline " " bitfld.long 0x0 10. " UART_IRDA0 ,UART0 IrDA Mode Selection" "UART,IrDA" sif (cpuis("STR910FAW*")||cpuis("STR910FAZ*")||cpuis("STR911FAW*")||cpuis("STR911FAZ*")||cpuis("STR912FAW*")||cpuis("STR912FAZ*")) bitfld.long 0x00 8. " EMI_ALE_LNGT ,EMI Active Level Length" "1-cycle,2-cycle" textline " " bitfld.long 0x00 7. " EMI_ALE_POLR ,EMI Active Level Polarity" "Low,High" textline " " bitfld.long 0x00 6. " EMI_MUX ,EMI Mux/Demux" "Multiplexed,Demultiplexed" endif textline " " bitfld.long 0x00 5. " SRAM_LK_EN ,SRAM Arbiter Lock Transfer Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3.--4. " SRAM_SIZE ,SRAM Size" "32 KB,64 KB,96 KB,?..." bitfld.long 0x00 2. " WSR_AHB ,AHB Wait State Enable" "No state,1 state" textline " " bitfld.long 0x00 1. " WSR_DTCM ,DTCM Wait State Enable" "No state,1 state" bitfld.long 0x00 0. " EN_PFQBC ,PFQBC Unit Enable" "Disabled,Enabled" width 0x0E tree "GPIO Output/Input Registers" group.long 0x44++0x3 line.long 0x0 "SCU_GPIOOUT0,GPIO Output Register 0" sif (cpuis("STR910FAW*")||cpuis("STR910FAZ*")||cpuis("STR911FAW*")||cpuis("STR911FAZ*")||cpuis("STR912FAW*")||cpuis("STR912FAZ*")) bitfld.long 0x00 14.--15. " P0.7OUT ,GPIO Port 0 Output 7 Control" "Input,GPIO_0.7,EMI_CS3n,ETM_TRSYNC" bitfld.long 0x00 12.--13. " P0.6OUT ,GPIO Port 0 Output 6 Control" "Input,GPIO_0.6,EMI_CS2n,ETM_PSTAT2" bitfld.long 0x00 10.--11. " P0.5OUT ,GPIO Port 0 Output 5 Control" "Input,GPIO_0.5,EMI_CS1n,ETM_PSTAT1" textline " " bitfld.long 0x00 8.--9. " P0.4OUT ,GPIO Port 0 Output 4 Control" "Input,GPIO_0.4,EMI_CS0n,ETM_PSTAT0" bitfld.long 0x00 6.--7. " P0.3OUT ,GPIO Port 0 Output 3 Control" "Input,GPIO_0.3,I2C1_DOUT,ETM_PCK3" bitfld.long 0x00 4.--5. " P0.2OUT ,GPIO Port 0 Output 2 Control" "Input,GPIO_0.2,I2C1_CLKOUT,ETM_PCK2" textline " " bitfld.long 0x00 2.--3. " P0.1OUT ,GPIO Port 0 Output 1 Control" "Input,GPIO_0.1,I2C0_DOUT,ETM_PCK1" bitfld.long 0x00 0.--1. " P0.0OUT ,GPIO Port 0 Output 0 Control" "Input,GPIO_0.0,I2C0_CLKOUT,ETM_PCK0" else bitfld.long 0x00 14.--15. " P0.7OUT ,GPIO Port 0 Output 7 Control" "Input,GPIO_0.7,Reserved,ETM_TRSYNC" bitfld.long 0x00 12.--13. " P0.6OUT ,GPIO Port 0 Output 6 Control" "Input,GPIO_0.6,Reserved,ETM_PSTAT2" bitfld.long 0x00 10.--11. " P0.5OUT ,GPIO Port 0 Output 5 Control" "Input,GPIO_0.5,Reserved,ETM_PSTAT1" textline " " bitfld.long 0x00 8.--9. " P0.4OUT ,GPIO Port 0 Output 4 Control" "Input,GPIO_0.4,Reserved,ETM_PSTAT0" bitfld.long 0x00 6.--7. " P0.3OUT ,GPIO Port 0 Output 3 Control" "Input,GPIO_0.3,I2C1_DOUT,ETM_PCK3" bitfld.long 0x00 4.--5. " P0.2OUT ,GPIO Port 0 Output 2 Control" "Input,GPIO_0.2,I2C1_CLKOUT,ETM_PCK2" textline " " bitfld.long 0x00 2.--3. " P0.1OUT ,GPIO Port 0 Output 1 Control" "Input,GPIO_0.1,I2C0_DOUT,ETM_PCK1" bitfld.long 0x00 0.--1. " P0.0OUT ,GPIO Port 0 Output 0 Control" "Input,GPIO_0.0,I2C0_CLKOUT,ETM_PCK0" endif group.long 0x48++0x3 line.long 0x0 "SCU_GPIOOUT1,GPIO Output Register 1" sif (cpuis("STR912*")) bitfld.long 0x00 14.--15. " P1.7OUT ,GPIO Port 1 Output 7 Control" "Input,GPIO_1.7,MII_MDC,ETM_TRCLK" bitfld.long 0x00 12.--13. " P1.6OUT ,GPIO Port 1 Output 6 Control" "Input,GPIO_1.6,CAN_TX,I2C0_DOUT" bitfld.long 0x00 10.--11. " P1.5OUT ,GPIO Port 1 Output 5 Control" "Input,GPIO_1.5,UART2_TX,ETM_TRCLK" textline " " bitfld.long 0x00 8.--9. " P1.4OUT ,GPIO Port 1 Output 4 Control" "Input,GPIO_1.4,MII_TXD3,I2C0_CLKOUT" bitfld.long 0x00 6.--7. " P1.3OUT ,GPIO Port 1 Output 3 Control" "Input,GPIO_1.3,MII_TXD2,SSP1_NSS" bitfld.long 0x00 4.--5. " P1.2OUT ,GPIO Port 1 Output 2 Control" "Input,GPIO_1.2,MII_TXD1,UART0_TX" textline " " bitfld.long 0x00 2.--3. " P1.1OUT ,GPIO Port 1 Output 1 Control" "Input,GPIO_1.1,MII_TXD0,SSP1_MOSI" bitfld.long 0x00 0.--1. " P1.0OUT ,GPIO Port 1 Output 0 Control" "Input,GPIO_1.0,UART1_TX,SSP1_SCLK" else bitfld.long 0x00 14.--15. " P1.7OUT ,GPIO Port 1 Output 7 Control" "Input,GPIO_1.7,Reserved,ETM_TRCLK" bitfld.long 0x00 12.--13. " P1.6OUT ,GPIO Port 1 Output 6 Control" "Input,GPIO_1.6,CAN_TX,I2C0_DOUT" bitfld.long 0x00 10.--11. " P1.5OUT ,GPIO Port 1 Output 5 Control" "Input,GPIO_1.5,UART2_TX,ETM_TRCLK" textline " " bitfld.long 0x00 8.--9. " P1.4OUT ,GPIO Port 1 Output 4 Control" "Input,GPIO_1.4,Reserved,I2C0_CLKOUT" bitfld.long 0x00 6.--7. " P1.3OUT ,GPIO Port 1 Output 3 Control" "Input,GPIO_1.3,Reserved,SSP1_NSS" bitfld.long 0x00 4.--5. " P1.2OUT ,GPIO Port 1 Output 2 Control" "Input,GPIO_1.2,Reserved,UART0_TX" textline " " bitfld.long 0x00 2.--3. " P1.1OUT ,GPIO Port 1 Output 1 Control" "Input,GPIO_1.1,Reserved,SSP1_MOSI" bitfld.long 0x00 0.--1. " P1.0OUT ,GPIO Port 1 Output 0 Control" "Input,GPIO_1.0,UART1_TX,SSP1_SCLK" endif group.long 0x4C++0x3 line.long 0x0 "SCU_GPIOOUT2,GPIO Output Register 2" bitfld.long 0x00 14.--15. " P2.7OUT ,GPIO Port 2 Output 7 Control" "Input,GPIO_2.7,SSP0_NSS,ETM_TRSYNC" bitfld.long 0x00 12.--13. " P2.6OUT ,GPIO Port 2 Output 6 Control" "Input,GPIO_2.6,SSP0_MISO,ETM_PSTAT2" bitfld.long 0x00 10.--11. " P2.5OUT ,GPIO Port 2 Output 5 Control" "Input,GPIO_2.5,SSP0_MOSI,ETM_PSTAT1" textline " " bitfld.long 0x00 8.--9. " P2.4OUT ,GPIO Port 2 Output 4 Control" "Input,GPIO_2.4,SSP0_SCLK,ETM_PSTAT0" bitfld.long 0x00 6.--7. " P2.3OUT ,GPIO Port 2 Output 3 Control" "Input,GPIO_2.3,I2C1_DOUT,ETM_PCK3" bitfld.long 0x00 4.--5. " P2.2OUT ,GPIO Port 2 Output 2 Control" "Input,GPIO_2.2,I2C1_CLKOUT,ETM_PCK2" textline " " bitfld.long 0x00 2.--3. " P2.1OUT ,GPIO Port 2 Output 1 Control" "Input,GPIO_2.1,I2C0_DOUT,ETM_PCK1" bitfld.long 0x00 0.--1. " P2.0OUT ,GPIO Port 2 Output 0 Control" "Input,GPIO_2.0,I2C0_CLKOUT,ETM_PCK0" group.long 0x50++0x3 line.long 0x0 "SCU_GPIOOUT3,GPIO Output Register 3" bitfld.long 0x00 14.--15. " P3.7OUT ,GPIO Port 3 Output 7 Control" "Input,GPIO_3.7,SSP1_NSS,TIM1_OCMP1" bitfld.long 0x00 12.--13. " P3.6OUT ,GPIO Port 3 Output 6 Control" "Input,GPIO_3.6,SSP1_MOSI,CAN_TX" bitfld.long 0x00 10.--11. " P3.5OUT ,GPIO Port 3 Output 5 Control" "Input,GPIO_3.5,SSP1_MISO,UART2_TX" textline " " bitfld.long 0x00 8.--9. " P3.4OUT ,GPIO Port 3 Output 4 Control" "Input,GPIO_3.4,SSP1_SCLK,UART0_TX" bitfld.long 0x00 6.--7. " P3.3OUT ,GPIO Port 3 Output 3 Control" "Input,GPIO_3.3,UART1_TX,UART0_RTS" bitfld.long 0x00 4.--5. " P3.2OUT ,GPIO Port 3 Output 2 Control" "Input,GPIO_3.2,CAN_TX,UART0_DTR" textline " " bitfld.long 0x00 2.--3. " P3.1OUT ,GPIO Port 3 Output 1 Control" "Input,GPIO_3.1,UART0_TX,TIM1_OCMP1" bitfld.long 0x00 0.--1. " P3.0OUT ,GPIO Port 3 Output 0 Control" "Input,GPIO_3.0,UART2_TX,TIM0_OCMP1" group.long 0x54++0x3 line.long 0x0 "SCU_GPIOOUT4,GPIO Output Register 4" bitfld.long 0x00 14.--15. " P4.7OUT ,GPIO Port 4 Output 7 Control" "Input,GPIO_4.7,TIM3_OCMP2,ETM_TRSYNC" bitfld.long 0x00 12.--13. " P4.6OUT ,GPIO Port 4 Output 6 Control" "Input,GPIO_4.6,TIM3_OCMP1,ETM_PSTAT2" bitfld.long 0x00 10.--11. " P4.5OUT ,GPIO Port 4 Output 5 Control" "Input,GPIO_4.5,TIM2_OCMP2,ETM_PSTAT1" textline " " bitfld.long 0x00 8.--9. " P4.4OUT ,GPIO Port 4 Output 4 Control" "Input,GPIO_4.4,TIM2_OCMP1,ETM_PSTAT0" bitfld.long 0x00 6.--7. " P4.3OUT ,GPIO Port 4 Output 3 Control" "Input,GPIO_4.3,TIM1_OCMP2,ETM_PCK3" bitfld.long 0x00 4.--5. " P4.2OUT ,GPIO Port 4 Output 2 Control" "Input,GPIO_4.2,TIM1_OCMP,ETM_PCK2" textline " " bitfld.long 0x00 2.--3. " P4.1OUT ,GPIO Port 4 Output 1 Control" "Input,GPIO_4.1,TIM0_OCMP2,ETM_PCK1" bitfld.long 0x00 0.--1. " P4.0OUT ,GPIO Port 4 Output 0 Control" "Input,GPIO_4.0,TIM0_OCMP1,ETM_PCK0" group.long 0x58++0x3 line.long 0x0 "SCU_GPIOOUT5,GPIO Output Register 5" sif (cpuis("STR912*")) bitfld.long 0x00 14.--15. " P5.7OUT ,GPIO Port 5 Output 7 Control" "Input,GPIO_5.7,SSP0_NSS,EMI_CS3n" bitfld.long 0x00 12.--13. " P5.6OUT ,GPIO Port 5 Output 6 Control" "Input,GPIO_5.6,SSP0_MISO,EMI_CS2n" bitfld.long 0x00 10.--11. " P5.5OUT ,GPIO Port 5 Output 5 Control" "Input,GPIO_5.5,SSP0_MOSI,EMI_CS1n" textline " " bitfld.long 0x00 8.--9. " P5.4OUT ,GPIO Port 5 Output 4 Control" "Input,GPIO_5.4,SSP0_SCLK,EMI_CS0n" bitfld.long 0x00 6.--7. " P5.3OUT ,GPIO Port 5 Output 3 Control" "Input,GPIO_5.3,MII_TX_EN,TIM2_OCMP1" bitfld.long 0x00 4.--5. " P5.2OUT ,GPIO Port 5 Output 2 Control" "Input,GPIO_5.2,MII_PHYCLK,TIM3_OCMP1" textline " " bitfld.long 0x00 2.--3. " P5.1OUT ,GPIO Port 5 Output 1 Control" "Input,GPIO_5.1,CAN_TX,UART2_TX" bitfld.long 0x00 0.--1. " P5.0OUT ,GPIO Port 5 Output 0 Control" "Input,GPIO_5.0,ETM_TRCLK,UART0_TX" elif (cpuis("STR910FAW*")||cpuis("STR910FAZ*")||cpuis("STR911FAW*")||cpuis("STR911FAZ*")) bitfld.long 0x00 14.--15. " P5.7OUT ,GPIO Port 5 Output 7 Control" "Input,GPIO_5.7,SSP0_NSS,EMI_CS3n" bitfld.long 0x00 12.--13. " P5.6OUT ,GPIO Port 5 Output 6 Control" "Input,GPIO_5.6,SSP0_MISO,EMI_CS2n" bitfld.long 0x00 10.--11. " P5.5OUT ,GPIO Port 5 Output 5 Control" "Input,GPIO_5.5,SSP0_MOSI,EMI_CS1n" textline " " bitfld.long 0x00 8.--9. " P5.4OUT ,GPIO Port 5 Output 4 Control" "Input,GPIO_5.4,SSP0_SCLK,EMI_CS0n" bitfld.long 0x00 6.--7. " P5.3OUT ,GPIO Port 5 Output 3 Control" "Input,GPIO_5.3,Reserved,TIM2_OCMP1" bitfld.long 0x00 4.--5. " P5.2OUT ,GPIO Port 5 Output 2 Control" "Input,GPIO_5.2,Reserved,TIM3_OCMP1" textline " " bitfld.long 0x00 2.--3. " P5.1OUT ,GPIO Port 5 Output 1 Control" "Input,GPIO_5.1,CAN_TX,UART2_TX" bitfld.long 0x00 0.--1. " P5.0OUT ,GPIO Port 5 Output 0 Control" "Input,GPIO_5.0,ETM_TRCLK,UART0_TX" else bitfld.long 0x00 14.--15. " P5.7OUT ,GPIO Port 5 Output 7 Control" "Input,GPIO_5.7,SSP0_NSS,?..." bitfld.long 0x00 12.--13. " P5.6OUT ,GPIO Port 5 Output 6 Control" "Input,GPIO_5.6,SSP0_MISO,?..." bitfld.long 0x00 10.--11. " P5.5OUT ,GPIO Port 5 Output 5 Control" "Input,GPIO_5.5,SSP0_MOSI,?..." textline " " bitfld.long 0x00 8.--9. " P5.4OUT ,GPIO Port 5 Output 4 Control" "Input,GPIO_5.4,SSP0_SCLK,?..." bitfld.long 0x00 6.--7. " P5.3OUT ,GPIO Port 5 Output 3 Control" "Input,GPIO_5.3,Reserved,TIM2_OCMP1" bitfld.long 0x00 4.--5. " P5.2OUT ,GPIO Port 5 Output 2 Control" "Input,GPIO_5.2,Reserved,TIM3_OCMP1" textline " " bitfld.long 0x00 2.--3. " P5.1OUT ,GPIO Port 5 Output 1 Control" "Input,GPIO_5.1,CAN_TX,UART2_TX" bitfld.long 0x00 0.--1. " P5.0OUT ,GPIO Port 5 Output 0 Control" "Input,GPIO_5.0,ETM_TRCLK,UART0_TX" endif group.long 0x5C++0x3 line.long 0x0 "SCU_GPIOOUT6,GPIO Output Register 6" bitfld.long 0x00 14.--15. " P6.7OUT ,GPIO Port 6 Output 7 Control" "Input,GPIO_6.7,TIM3_OCMP2,UART0_TX" bitfld.long 0x00 12.--13. " P6.6OUT ,GPIO Port 6 Output 6 Control" "Input,GPIO_6.6,TIM3_OCMP1,ETM_TRCLK" bitfld.long 0x00 10.--11. " P6.5OUT ,GPIO Port 6 Output 5 Control" "Input,GPIO_6.5,TIM2_OCMP2,MC_WL" textline " " bitfld.long 0x00 8.--9. " P6.4OUT ,GPIO Port 6 Output 4 Control" "Input,GPIO_6.4,TIM2_OCMP1,MC_WH" bitfld.long 0x00 6.--7. " P6.3OUT ,GPIO Port 6 Output 3 Control" "Input,GPIO_6.3,TIM1_OCMP2,MC_VL" bitfld.long 0x00 4.--5. " P6.2OUT ,GPIO Port 6 Output 2 Control" "Input,GPIO_6.2,TIM1_OCMP1,MC_VH" textline " " bitfld.long 0x00 2.--3. " P6.1OUT ,GPIO Port 6 Output 1 Control" "Input,GPIO_6.1,TIM0_OCMP2,MC_UL" bitfld.long 0x00 0.--1. " P6.0OUT ,GPIO Port 6 Output 0 Control" "Input,GPIO_6.0,TIM0_OCMP1,MC_UH" group.long 0x60++0x3 line.long 0x0 "SCU_GPIOOUT7,GPIO Output Register 7" sif (cpuis("STR910FAW*")||cpuis("STR910FAZ*")||cpuis("STR911FAW*")||cpuis("STR911FAZ*")||cpuis("STR912FAW*")||cpuis("STR912FAZ*")) bitfld.long 0x00 14.--15. " P7.7OUT ,GPIO Port 7 Output 7 Control" "Input,GPIO_7.7,EMI_CS0n,EMI_A7/23" bitfld.long 0x00 12.--13. " P7.6OUT ,GPIO Port 7 Output 6 Control" "Input,GPIO_7.6,EMI_A6/22,EMI_CS1n" bitfld.long 0x00 10.--11. " P7.5OUT ,GPIO Port 7 Output 5 Control" "Input,GPIO_7.5,EMI_A5/21,EMI_CS2n" textline " " bitfld.long 0x00 8.--9. " P7.4OUT ,GPIO Port 7 Output 4 Control" "Input,GPIO_7.4,EMI_A4/20,EMI_CS3n" bitfld.long 0x00 6.--7. " P7.3OUT ,GPIO Port 7 Output 3 Control" "Input,GPIO_7.3,EMI_A3/19,ETM_PCK3" bitfld.long 0x00 4.--5. " P7.2OUT ,GPIO Port 7 Output 2 Control" "Input,GPIO_7.2,EMI_A2/18,ETM_PCK2" textline " " bitfld.long 0x00 2.--3. " P7.1OUT ,GPIO Port 7 Output 1 Control" "Input,GPIO_7.1,EMI_A1/17,ETM_PCK1" bitfld.long 0x00 0.--1. " P7.0OUT ,GPIO Port 7 Output 0 Control" "Input,GPIO_7.0,EMI_A0/16,ETM_PCK0" else bitfld.long 0x00 14.--15. " P7.7OUT ,GPIO Port 7 Output 7 Control" "Input,GPIO_7.7,?..." bitfld.long 0x00 12.--13. " P7.6OUT ,GPIO Port 7 Output 6 Control" "Input,GPIO_7.6,?..." bitfld.long 0x00 10.--11. " P7.5OUT ,GPIO Port 7 Output 5 Control" "Input,GPIO_7.5,?..." textline " " bitfld.long 0x00 8.--9. " P7.4OUT ,GPIO Port 7 Output 4 Control" "Input,GPIO_7.4,?..." bitfld.long 0x00 6.--7. " P7.3OUT ,GPIO Port 7 Output 3 Control" "Input,GPIO_7.3,Reserved,ETM_PCK3" bitfld.long 0x00 4.--5. " P7.2OUT ,GPIO Port 7 Output 2 Control" "Input,GPIO_7.2,Reserved,ETM_PCK2" textline " " bitfld.long 0x00 2.--3. " P7.1OUT ,GPIO Port 7 Output 1 Control" "Input,GPIO_7.1,Reserved,ETM_PCK1" bitfld.long 0x00 0.--1. " P7.0OUT ,GPIO Port 7 Output 0 Control" "Input,GPIO_7.0,Reserved,ETM_PCK0" endif group.long 0x64++0x3 line.long 0x0 "SCU_GPIOIN0,GPIO Input Register 0" bitfld.long 0x0 7. " P0.7IN ,GPIO Port 0 Input 7 Control" "Not connected,TIM2_ICAP2" bitfld.long 0x0 6. " P0.6IN ,GPIO Port 0 Input 6 Control" "Not connected,TIM2_ICAP1" textline " " bitfld.long 0x0 5. " P0.5IN ,GPIO Port 0 Input 5 Control" "Not connected,TIM0_ICAP2" bitfld.long 0x0 4. " P0.4IN ,GPIO Port 0 Input 4 Control" "Not connected,TIM0_ICAP1" textline " " bitfld.long 0x0 3. " P0.3IN ,GPIO Port 0 Input 3 Control" "Not connected,I2C1_DIN" bitfld.long 0x0 2. " P0.2IN ,GPIO Port 0 Input 2 Control" "Not connected,I2C1_CLKIN" textline " " bitfld.long 0x0 1. " P0.1IN ,GPIO Port 0 Input 1 Control" "Not connected,I2C0_DIN" bitfld.long 0x0 0. " P0.0IN ,GPIO Port 0 Input 0 Control" "Not connected,I2C0_CLKIN" group.long 0x68++0x3 line.long 0x0 "SCU_GPIOIN1,GPIO Input Register 1" bitfld.long 0x0 7. " P1.7IN ,GPIO Port 1 Input 7 Control" "Not connected,ETM_EXTRIG" bitfld.long 0x0 6. " P1.6IN ,GPIO Port 1 Input 6 Control" "Not connected,I2C0_DIN" textline " " bitfld.long 0x0 5. " P1.5IN ,GPIO Port 1 Input 5 Control" "Not connected,CAN_RX" bitfld.long 0x0 4. " P1.4IN ,GPIO Port 1 Input 4 Control" "Not connected,I2C0_CLKIN" textline " " bitfld.long 0x0 3. " P1.3IN ,GPIO Port 1 Input 3 Control" "Not connected,UART2_RX" bitfld.long 0x0 2. " P1.2IN ,GPIO Port 1 Input 2 Control" "Not connected,SSP1_MISO" textline " " bitfld.long 0x0 1. " P1.1IN ,GPIO Port 1 Input 1 Control" "Not connected,UART1_RX" bitfld.long 0x0 0. " P1.0IN ,GPIO Port 1 Input 0 Control" "Not connected,ETM_EXTRIG" group.long 0x6C++0x3 line.long 0x0 "SCU_GPIOIN2,GPIO Input Register 2" bitfld.long 0x0 7. " P2.7IN ,GPIO Port 2 Input 7 Control" "Not connected,SSP0_NSS" bitfld.long 0x0 6. " P2.6IN ,GPIO Port 2 Input 6 Control" "Not connected,SSP0_MISO" textline " " bitfld.long 0x0 5. " P2.5IN ,GPIO Port 2 Input 5 Control" "Not connected,SSP0_MOSI" bitfld.long 0x0 4. " P2.4IN ,GPIO Port 2 Input 4 Control" "Not connected,SSP0_SCLK" textline " " bitfld.long 0x0 3. " P2.3IN ,GPIO Port 2 Input 3 Control" "Not connected,I2C1_DIN" bitfld.long 0x0 2. " P2.2IN ,GPIO Port 2 Input 2 Control" "Not connected,I2C1_CLKIN" textline " " bitfld.long 0x0 1. " P2.1IN ,GPIO Port 2 Input 1 Control" "Not connected,I2C0_DIN" bitfld.long 0x0 0. " P2.0IN ,GPIO Port 2 Input 0 Control" "Not connected,I2C0_CLKIN" group.long 0x70++0x3 line.long 0x0 "SCU_GPIOIN3,GPIO Input Register 3" bitfld.long 0x0 7. " P3.7IN ,GPIO Port 3 Input 7 Control" "Not connected,SSP1_NSS" bitfld.long 0x0 6. " P3.6IN ,GPIO Port 3 Input 6 Control" "Not connected,SSP1_MOSI" textline " " bitfld.long 0x0 5. " P3.5IN ,GPIO Port 3 Input 5 Control" "Not connected,SSP1_MISO" bitfld.long 0x0 4. " P3.4IN ,GPIO Port 3 Input 4 Control" "Not connected,SSP1_SCLK" textline " " bitfld.long 0x0 3. " P3.3IN ,GPIO Port 3 Input 3 Control" "Not connected,CAN_RX" bitfld.long 0x0 2. " P3.2IN ,GPIO Port 3 Input 2 Control" "Not connected,UART1_RxD" textline " " bitfld.long 0x0 1. " P3.1IN ,GPIO Port 3 Input 1 Control" "Not connected,UART2_RxD" bitfld.long 0x0 0. " P3.0IN ,GPIO Port 3 Input 0 Control" "Not connected,UART0_RxD" group.long 0x74++0x3 line.long 0x0 "SCU_GPIOIN4,GPIO Input Register 4" bitfld.long 0x0 7. " P4.7IN ,GPIO Port 4 Input 7 Control" "Not connected,TIM3_ICAP2" bitfld.long 0x0 6. " P4.6IN ,GPIO Port 4 Input 6 Control" "Not connected,TIM3_ICAP1" textline " " bitfld.long 0x0 5. " P4.5IN ,GPIO Port 4 Input 5 Control" "Not connected,TIM2_ICAP2" bitfld.long 0x0 4. " P4.4IN ,GPIO Port 4 Input 4 Control" "Not connected,TIM2_ICAP1" textline " " bitfld.long 0x0 3. " P4.3IN ,GPIO Port 4 Input 3 Control" "Not connected,TIM1_ICAP2" bitfld.long 0x0 2. " P4.2IN ,GPIO Port 4 Input 2 Control" "Not connected,TIM1_ICAP1" textline " " bitfld.long 0x0 1. " P4.1IN ,GPIO Port 4 Input 1 Control" "Not connected,TIM0_ICAP2" bitfld.long 0x0 0. " P4.0IN ,GPIO Port 4 Input 0 Control" "Not connected,TIM0_ICAP1" group.long 0x78++0x3 line.long 0x0 "SCU_GPIOIN5,GPIO Input Register 5" bitfld.long 0x0 7. " P5.7IN ,GPIO Port 5 Input 7 Control" "Not connected,SSP0_NSS" bitfld.long 0x0 6. " P5.6IN ,GPIO Port 5 Input 6 Control" "Not connected,SSP0_MISO" textline " " bitfld.long 0x0 5. " P5.5IN ,GPIO Port 5 Input 5 Control" "Not connected,SSP0_MOSI" bitfld.long 0x0 4. " P5.4IN ,GPIO Port 5 Input 4 Control" "Not connected,SSP0_SCLK" textline " " bitfld.long 0x0 3. " P5.3IN ,GPIO Port 5 Input 3 Control" "Not connected,ETM_EXTRIG" bitfld.long 0x0 2. " P5.2IN ,GPIO Port 5 Input 2 Control" "Not connected,UART2_RxD" textline " " bitfld.long 0x0 1. " P5.1IN ,GPIO Port 5 Input 1 Control" "Not connected,UART0_RxD" bitfld.long 0x0 0. " P5.0IN ,GPIO Port 5 Input 0 Control" "Not connected,CAN_RX" group.long 0x7C++0x3 line.long 0x0 "SCU_GPIOIN6,GPIO Input Register 6" bitfld.long 0x0 7. " P6.7IN ,GPIO Port 6 Input 7 Control" "Not connected,ETM_EXTRIG" bitfld.long 0x0 6. " P6.6IN ,GPIO Port 6 Input 6 Control" "Not connected,UART0_RxD" textline " " bitfld.long 0x0 5. " P6.5IN ,GPIO Port 6 Input 5 Control" "Not connected,TIM2_ICAP2" bitfld.long 0x0 4. " P6.4IN ,GPIO Port 6 Input 4 Control" "Not connected,TIM2_ICAP1" textline " " bitfld.long 0x0 3. " P6.3IN ,GPIO Port 6 Input 3 Control" "Not connected,TIM1_ICAP2" bitfld.long 0x0 2. " P6.2IN ,GPIO Port 6 Input 2 Control" "Not connected,TIM1_ICAP1" textline " " bitfld.long 0x0 1. " P6.1IN ,GPIO Port 6 Input 1 Control" "Not connected,TIM0_ICAP2" bitfld.long 0x0 0. " P6.0IN ,GPIO Port 6 Input 0 Control" "Not connected,TIM0_ICAP1" group.long 0x80++0x3 line.long 0x0 "SCU_GPIOIN7,GPIO Input Register 7" bitfld.long 0x0 7. " P7.7IN ,GPIO Port 7 Input 7 Control" "Not connected,TIM3_ICAP2" bitfld.long 0x0 6. " P7.6IN ,GPIO Port 7 Input 6 Control" "Not connected,TIM3_ICAP1" textline " " bitfld.long 0x0 5. " P7.5IN ,GPIO Port 7 Input 5 Control" "Not connected,ETM_EXTRIG" bitfld.long 0x0 4. " P7.4IN ,GPIO Port 7 Input 4 Control" "Not connected,UART0_RxD" textline " " bitfld.long 0x0 3. " P7.3IN ,GPIO Port 7 Input 3 Control" "Not connected,TIM2_ICAP2" bitfld.long 0x0 2. " P7.2IN ,GPIO Port 7 Input 2 Control" "Not connected,TIM2_ICAP1" textline " " bitfld.long 0x0 1. " P7.1IN ,GPIO Port 7 Input 1 Control" "Not connected,TIM0_ICAP2" bitfld.long 0x0 0. " P7.0IN ,GPIO Port 7 Input 0 Control" "Not connected,TIM0_ICAP1" tree.end width 0xF tree "GPIO Type Registers" textline " " group.long 0x84++0x3 line.long 0x0 "SCU_GPIOTYPE0,GPIO Type Register 0" bitfld.long 0x0 7. " TYPE7 ,GPIO Output Type 7" "Push-pull,Open collector" bitfld.long 0x0 6. " TYPE6 ,GPIO Output Type 6" "Push-pull,Open collector" bitfld.long 0x0 5. " TYPE5 ,GPIO Output Type 5" "Push-pull,Open collector" textline " " bitfld.long 0x0 4. " TYPE4 ,GPIO Output Type 4" "Push-pull,Open collector" bitfld.long 0x0 3. " TYPE3 ,GPIO Output Type 3" "Push-pull,Open collector" bitfld.long 0x0 2. " TYPE2 ,GPIO Output Type 2" "Push-pull,Open collector" textline " " bitfld.long 0x0 1. " TYPE1 ,GPIO Output Type 1" "Push-pull,Open collector" bitfld.long 0x0 0. " TYPE0 ,GPIO Output Type 0" "Push-pull,Open collector" group.long 0x88++0x3 line.long 0x0 "SCU_GPIOTYPE1,GPIO Type Register 1" bitfld.long 0x0 7. " TYPE7 ,GPIO Output Type 7" "Push-pull,Open collector" bitfld.long 0x0 6. " TYPE6 ,GPIO Output Type 6" "Push-pull,Open collector" bitfld.long 0x0 5. " TYPE5 ,GPIO Output Type 5" "Push-pull,Open collector" textline " " bitfld.long 0x0 4. " TYPE4 ,GPIO Output Type 4" "Push-pull,Open collector" bitfld.long 0x0 3. " TYPE3 ,GPIO Output Type 3" "Push-pull,Open collector" bitfld.long 0x0 2. " TYPE2 ,GPIO Output Type 2" "Push-pull,Open collector" textline " " bitfld.long 0x0 1. " TYPE1 ,GPIO Output Type 1" "Push-pull,Open collector" bitfld.long 0x0 0. " TYPE0 ,GPIO Output Type 0" "Push-pull,Open collector" group.long 0x8C++0x3 line.long 0x0 "SCU_GPIOTYPE2,GPIO Type Register 2" bitfld.long 0x0 7. " TYPE7 ,GPIO Output Type 7" "Push-pull,Open collector" bitfld.long 0x0 6. " TYPE6 ,GPIO Output Type 6" "Push-pull,Open collector" bitfld.long 0x0 5. " TYPE5 ,GPIO Output Type 5" "Push-pull,Open collector" textline " " bitfld.long 0x0 4. " TYPE4 ,GPIO Output Type 4" "Push-pull,Open collector" bitfld.long 0x0 3. " TYPE3 ,GPIO Output Type 3" "Push-pull,Open collector" bitfld.long 0x0 2. " TYPE2 ,GPIO Output Type 2" "Push-pull,Open collector" textline " " bitfld.long 0x0 1. " TYPE1 ,GPIO Output Type 1" "Push-pull,Open collector" bitfld.long 0x0 0. " TYPE0 ,GPIO Output Type 0" "Push-pull,Open collector" group.long 0x90++0x3 line.long 0x0 "SCU_GPIOTYPE3,GPIO Type Register 3" bitfld.long 0x0 7. " TYPE7 ,GPIO Output Type 7" "Push-pull,Open collector" bitfld.long 0x0 6. " TYPE6 ,GPIO Output Type 6" "Push-pull,Open collector" bitfld.long 0x0 5. " TYPE5 ,GPIO Output Type 5" "Push-pull,Open collector" textline " " bitfld.long 0x0 4. " TYPE4 ,GPIO Output Type 4" "Push-pull,Open collector" bitfld.long 0x0 3. " TYPE3 ,GPIO Output Type 3" "Push-pull,Open collector" bitfld.long 0x0 2. " TYPE2 ,GPIO Output Type 2" "Push-pull,Open collector" textline " " bitfld.long 0x0 1. " TYPE1 ,GPIO Output Type 1" "Push-pull,Open collector" bitfld.long 0x0 0. " TYPE0 ,GPIO Output Type 0" "Push-pull,Open collector" group.long 0x94++0x3 line.long 0x0 "SCU_GPIOTYPE4,GPIO Type Register 4" bitfld.long 0x0 7. " TYPE7 ,GPIO Output Type 7" "Push-pull,Open collector" bitfld.long 0x0 6. " TYPE6 ,GPIO Output Type 6" "Push-pull,Open collector" bitfld.long 0x0 5. " TYPE5 ,GPIO Output Type 5" "Push-pull,Open collector" textline " " bitfld.long 0x0 4. " TYPE4 ,GPIO Output Type 4" "Push-pull,Open collector" bitfld.long 0x0 3. " TYPE3 ,GPIO Output Type 3" "Push-pull,Open collector" bitfld.long 0x0 2. " TYPE2 ,GPIO Output Type 2" "Push-pull,Open collector" textline " " bitfld.long 0x0 1. " TYPE1 ,GPIO Output Type 1" "Push-pull,Open collector" bitfld.long 0x0 0. " TYPE0 ,GPIO Output Type 0" "Push-pull,Open collector" group.long 0x98++0x3 line.long 0x0 "SCU_GPIOTYPE5,GPIO Type Register 5" bitfld.long 0x0 7. " TYPE7 ,GPIO Output Type 7" "Push-pull,Open collector" bitfld.long 0x0 6. " TYPE6 ,GPIO Output Type 6" "Push-pull,Open collector" bitfld.long 0x0 5. " TYPE5 ,GPIO Output Type 5" "Push-pull,Open collector" textline " " bitfld.long 0x0 4. " TYPE4 ,GPIO Output Type 4" "Push-pull,Open collector" bitfld.long 0x0 3. " TYPE3 ,GPIO Output Type 3" "Push-pull,Open collector" bitfld.long 0x0 2. " TYPE2 ,GPIO Output Type 2" "Push-pull,Open collector" textline " " bitfld.long 0x0 1. " TYPE1 ,GPIO Output Type 1" "Push-pull,Open collector" bitfld.long 0x0 0. " TYPE0 ,GPIO Output Type 0" "Push-pull,Open collector" group.long 0x9C++0x3 line.long 0x0 "SCU_GPIOTYPE6,GPIO Type Register 6" bitfld.long 0x0 7. " TYPE7 ,GPIO Output Type 7" "Push-pull,Open collector" bitfld.long 0x0 6. " TYPE6 ,GPIO Output Type 6" "Push-pull,Open collector" bitfld.long 0x0 5. " TYPE5 ,GPIO Output Type 5" "Push-pull,Open collector" textline " " bitfld.long 0x0 4. " TYPE4 ,GPIO Output Type 4" "Push-pull,Open collector" bitfld.long 0x0 3. " TYPE3 ,GPIO Output Type 3" "Push-pull,Open collector" bitfld.long 0x0 2. " TYPE2 ,GPIO Output Type 2" "Push-pull,Open collector" textline " " bitfld.long 0x0 1. " TYPE1 ,GPIO Output Type 1" "Push-pull,Open collector" bitfld.long 0x0 0. " TYPE0 ,GPIO Output Type 0" "Push-pull,Open collector" group.long 0xA0++0x3 line.long 0x0 "SCU_GPIOTYPE7,GPIO Type Register 7" bitfld.long 0x0 7. " TYPE7 ,GPIO Output Type 7" "Push-pull,Open collector" bitfld.long 0x0 6. " TYPE6 ,GPIO Output Type 6" "Push-pull,Open collector" bitfld.long 0x0 5. " TYPE5 ,GPIO Output Type 5" "Push-pull,Open collector" textline " " bitfld.long 0x0 4. " TYPE4 ,GPIO Output Type 4" "Push-pull,Open collector" bitfld.long 0x0 3. " TYPE3 ,GPIO Output Type 3" "Push-pull,Open collector" bitfld.long 0x0 2. " TYPE2 ,GPIO Output Type 2" "Push-pull,Open collector" textline " " bitfld.long 0x0 1. " TYPE1 ,GPIO Output Type 1" "Push-pull,Open collector" bitfld.long 0x0 0. " TYPE0 ,GPIO Output Type 0" "Push-pull,Open collector" group.long 0xA4++0x3 line.long 0x0 "SCU_GPIOTYPE8,GPIO Type Register 8" bitfld.long 0x0 7. " TYPE7 ,GPIO Output Type 7" "Push-pull,Open collector" bitfld.long 0x0 6. " TYPE6 ,GPIO Output Type 6" "Push-pull,Open collector" bitfld.long 0x0 5. " TYPE5 ,GPIO Output Type 5" "Push-pull,Open collector" textline " " bitfld.long 0x0 4. " TYPE4 ,GPIO Output Type 4" "Push-pull,Open collector" bitfld.long 0x0 3. " TYPE3 ,GPIO Output Type 3" "Push-pull,Open collector" bitfld.long 0x0 2. " TYPE2 ,GPIO Output Type 2" "Push-pull,Open collector" textline " " bitfld.long 0x0 1. " TYPE1 ,GPIO Output Type 1" "Push-pull,Open collector" bitfld.long 0x0 0. " TYPE0 ,GPIO Output Type 0" "Push-pull,Open collector" group.long 0xA8++0x3 line.long 0x0 "SCU_GPIOTYPE9,GPIO Type Register 9" bitfld.long 0x0 7. " TYPE7 ,GPIO Output Type 7" "Push-pull,Open collector" bitfld.long 0x0 6. " TYPE6 ,GPIO Output Type 6" "Push-pull,Open collector" bitfld.long 0x0 5. " TYPE5 ,GPIO Output Type 5" "Push-pull,Open collector" textline " " bitfld.long 0x0 4. " TYPE4 ,GPIO Output Type 4" "Push-pull,Open collector" bitfld.long 0x0 3. " TYPE3 ,GPIO Output Type 3" "Push-pull,Open collector" bitfld.long 0x0 2. " TYPE2 ,GPIO Output Type 2" "Push-pull,Open collector" textline " " bitfld.long 0x0 1. " TYPE1 ,GPIO Output Type 1" "Push-pull,Open collector" bitfld.long 0x0 0. " TYPE0 ,GPIO Output Type 0" "Push-pull,Open collector" tree.end textline " " width 0xD group.long 0xAC++0x3 line.long 0x0 "SCU_EMI,GPIO External Memory Interface Register" bitfld.long 0x0 2. " BYTE_EN ,Byte Select control" "Normal,Byte select signals" textline " " bitfld.long 0x0 1. " BCLK_EN ,BCLK enable" "Enabled,Disabled" bitfld.long 0x0 0. " GPIOEMI ,GPIO EMI Selection" "GPIO,EMI" group.long 0xB0++0x3 line.long 0x0 "SCU_WKUPSEL,Wakeup Selection Register" bitfld.long 0x0 9.--11. " WKUP_SEL7 ,Wake-Up/External Interrupt Port 7 Selection" "EXINT24,EXINT25,EXINT26,EXINT27,EXINT28,EXINT29,EXINT30,EXINT31" bitfld.long 0x0 6.--8. " WKUP_SEL6 ,Wake-Up/External Interrupt Port 6 Selection" "EXINT16,EXINT17,EXINT18,EXINT19,EXINT20,EXINT21,EXINT22,EXINT23" bitfld.long 0x0 3.--5. " WKUP_SEL5 ,Wake-Up/External Interrupt Port 5 Selection" "EXINT8,EXINT9,EXINT10,EXINT11,EXINT12,EXINT13,EXINT14,EXINT15" textline " " sif (cpuis("STR911*")||cpuis("STR912*")) bitfld.long 0x0 0.--2. " WKUP_SEL3 ,Wake-Up/External Interrupt Port 3 Selection" "RTC,USB,EXINT2,EXINT3,EXINT4,EXINT5,EXINT6,EXINT7" else bitfld.long 0x0 0.--2. " WKUP_SEL3 ,Wake-Up/External Interrupt Port 3 Selection" "RTC,Reserved,EXINT2,EXINT3,EXINT4,EXINT5,EXINT6,EXINT7" endif group.long 0xBC++0x3 line.long 0x0 "SCU_GPIOANA,GPIO Analog Mode Register" bitfld.long 0x0 8. " ACG ,ADC automatic clock gated mode" "Disabled,Enabled" bitfld.long 0x0 7. " P47A ,GPIO Port 4 Analog Control 7" "Off,On" bitfld.long 0x0 6. " P46A ,GPIO Port 4 Analog Control 6" "Off,On" bitfld.long 0x0 5. " P45A ,GPIO Port 4 Analog Control 5" "Off,On" textline " " bitfld.long 0x0 4. " P44A ,GPIO Port 4 Analog Control 4" "Off,On" bitfld.long 0x0 3. " P43A ,GPIO Port 4 Analog Control 3" "Off,On" bitfld.long 0x0 2. " P42A ,GPIO Port 4 Analog Control 2" "Off,On" textline " " bitfld.long 0x0 1. " P41A ,GPIO Port 4 Analog Control 1" "Off,On" bitfld.long 0x0 0. " P40A ,GPIO Port 4 Analog Control 0" "Off,On" else width 0xF group.long 0x0++0x7 line.long 0x0 "SCU_CLKCNTR,Clock Control Register" bitfld.long 0x00 17.--18. " EMIRATIO[1:0] ,External Memory Interface Ratio" "HCLK,HCLK/2,?..." bitfld.long 0x00 16. " FMISEL ,Flash Memory Interface Clock Divider" "RCLK,RCLK/2" textline " " bitfld.long 0x00 14. " TIM23SEL ,Timers 2 and 3 Clock Selection" "fMSTR/PRSC_TIM23[15:0]+1,EXTCLK_T2T3[fEXTTIM]" bitfld.long 0x00 13. " TIM01SEL ,Timers 0 and 1 Clock Selection" "fMSTR/PRSC_TIM01[15:0]+1,EXTCLK_T0T1[fEXTTIM]" textline " " bitfld.long 0x00 12. " PHYSEL ,MII_PHYCLK Enable" "Disabled,Enabled" bitfld.long 0x00 10.--11. " USBSEL[1:0] ,USB 48 MHz Clock Selection" "fMSTR,fMSTR/2,USB_CLK48M,?..." textline " " bitfld.long 0x00 9. " BRSEL ,Baud Rate Clock Selection" "fMSTR/2,fMSTR" bitfld.long 0x00 7.--8. " APBDIV[1:0] ,PCLK Divider" "RCLK,RCLK/2,RCLK/4,RCLK/8" textline " " bitfld.long 0x00 5.--6. " AHBDIV[1:0] ,HCLK Divider" "RCLK,RCLK/2,RCLK/4,?..." bitfld.long 0x00 2.--4. " RCLKDIV[2:0] ,RCLK Divider" "fMSTR,fMSTR/2,fMSTR/4,fMSTR/8,fMSTR/16,fMSTR/1024,?..." textline " " bitfld.long 0x00 0.--1. " MCLKSEL[1:0] ,Main Clock Source" "fPLL,fRTC,fOSC,?..." line.long 0x4 "SCU_PLLCONF,PLL Configuration Register" bitfld.long 0x04 19. " PLL_EN ,PLL Enable" "Disabled,Enabled" bitfld.long 0x04 16.--18. " PLL_PDIV[2:0] ,PLL Post-Divider" "0,1,2,3,4,5,6,7" textline " " hexmask.long.byte 0x04 8.--15. 1. " PLL_NDIV[7:0] ,PLL Feedback Divider" hexmask.long.byte 0x04 0.--7. 1. " PLL_MDIV[7:0] ,PLL Pre-Divider" group.long 0x8++0x3 line.long 0x0 "SCU_SYSSTATUS,System Status Register" eventfld.long 0x00 5. " SRAM_ERR ,SRAM Error Event Flag" "Occurred,Not Occurred" eventfld.long 0x00 4. " ACK_PFQBC ,ACK PFQBC Event Flag" "Occurred,Not Occurred" textline " " eventfld.long 0x00 3. " LVD_RST ,LVD Reset Event Flag" "Occurred,Not Occurred" eventfld.long 0x00 2. " WDG_RST ,WDG Reset Event Flag" "Occurred,Not Occurred" textline " " eventfld.long 0x00 1. " LOCK_LOST ,LOCK LOST Event Flag" "Occurred,Not Occurred" eventfld.long 0x00 0. " LOCK ,LOCK Event Flag" "Occurred,Not Occurred" group.long 0xC++0x3 line.long 0x0 "SCU_PWRMNG,Power Management Register" bitfld.long 0x0 4. " FLASH_PD_DBG ,Flash Power Down in Debug Mode" "No power down,Power down" bitfld.long 0x0 3. " CPU_INTR ,Special Interrupt Mode" "RCLKDIV[2:0],Full" textline " " bitfld.long 0x0 0.--2. " PWR_MODE[2:0] ,Power Mode Control" "Run,Idle,Sleep,?..." group.long 0x10++0x3 line.long 0x0 "SCU_ITCMSK,Interrupt Mask Register" bitfld.long 0x00 4. " MSK_LVD_RST ,LVD Reset Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 3. " MSK_SRAM_ERR ,SRAM Error Interrupt Mask" "Not masked,Masked" textline " " bitfld.long 0x00 2. " MSK_ACK_PFQBC ,ACK PFQBC Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 1. " MSK_LOCK_LOST ,LOCK LOST Interrupt Mask" "Not masked,Masked" textline " " bitfld.long 0x00 0. " MSK_LOCK ,LOCK Interrupt Mask" "Not masked,Masked" width 0xB tree "Peripheral Registers" group.long 0x14++0x3 line.long 0x0 "SCU_PCGR0,Peripheral Clock Gating Register 0" bitfld.long 0x00 11. " MAC ,Ethernet Peripheral Clock Gating" "Stopped,Running" bitfld.long 0x00 10. " USB48M ,USB 48 MHz Clock Gating" "Stopped,Running" textline " " bitfld.long 0x00 9. " USB ,USB Peripheral Clock Gating" "Stopped,Running" bitfld.long 0x00 8. " DMA ,DMA Peripheral Clock Gating" "Stopped,Running" textline " " bitfld.long 0x00 7. " EXT_MEM_CLK ,External Memory Clock Gating" "Stopped,Running" bitfld.long 0x00 6. " EMI ,EMI Peripheral Clock Gating" "Stopped,Running" textline " " bitfld.long 0x00 5. " VIC ,VIC Peripheral Clock Gating" "Stopped,Running" bitfld.long 0x00 4. " SRAM_ARBITER ,SRAM Arbiter Clock Gating" "Stopped,Running" textline " " bitfld.long 0x00 3. " SRAM ,SRAM Clock Gating" "Stopped,Running" bitfld.long 0x00 1. " PQFBC ,PQFBC Clock Gating" "Stopped,Running" textline " " bitfld.long 0x00 0. " FMI ,FMI Clock Gating" "Stopped,Running" group.long 0x18++0x3 line.long 0x0 "SCU_PCGR1,Peripheral Clock Gating Register 1" bitfld.long 0x00 24. " RTC ,RTC Clock Gating" "Stopped,Running" bitfld.long 0x0 23. " GPIO9 ,GPIO9 Port Clock Gating" "Stopped,Running" textline " " bitfld.long 0x0 22. " GPIO8 ,GPIO8 Port Clock Gating" "Stopped,Running" bitfld.long 0x0 21. " GPIO7 ,GPIO7 Port Clock Gating" "Stopped,Running" textline " " bitfld.long 0x0 20. " GPIO6 ,GPIO6 Port Clock Gating" "Stopped,Running" bitfld.long 0x0 19. " GPIO5 ,GPIO5 Port Clock Gating" "Stopped,Running" textline " " bitfld.long 0x0 18. " GPIO4 ,GPIO4 Port Clock Gating" "Stopped,Running" bitfld.long 0x0 17. " GPIO3 ,GPIO3 Port Clock Gating" "Stopped,Running" textline " " bitfld.long 0x0 16. " GPIO2 ,GPIO2 Port Clock Gating" "Stopped,Running" bitfld.long 0x0 15. " GPIO1 ,GPIO1 Port Clock Gating" "Stopped,Running" textline " " bitfld.long 0x0 14. " GPIO0 ,GPIO0 Port Clock Gating" "Stopped,Running" bitfld.long 0x00 13. " WIU ,WIU Peripheral Clock Gating" "Stopped,Running" textline " " bitfld.long 0x00 12. " WDG ,WDG Peripheral Clock Gating" "Stopped,Running" bitfld.long 0x00 11. " ADC ,ADC Clock Gating" "Stopped,Running" textline " " bitfld.long 0x00 10. " CAN ,CAN Peripheral Clock Gating" "Stopped,Running" bitfld.long 0x00 9. " SSP1 ,SSP1 Peripheral Clock Gating" "Stopped,Running" textline " " bitfld.long 0x00 8. " SSP0 ,SSP0 Peripheral Clock Gating" "Stopped,Running" bitfld.long 0x00 7. " I2C1 ,I2C1 Peripheral Clock Gating" "Stopped,Running" textline " " bitfld.long 0x00 6. " I2C0 ,I2C0 Peripheral Clock Gating" "Stopped,Running" bitfld.long 0x00 5. " UART2 ,UART2 Peripheral Clock Gating" "Stopped,Running" textline " " bitfld.long 0x00 4. " UART1 ,UART1 Peripheral Clock Gating" "Stopped,Running" bitfld.long 0x00 3. " UART0 ,UART0 Peripheral Clock Gating" "Stopped,Running" textline " " bitfld.long 0x00 2. " MC ,Motor Control Peripheral Clock Gating" "Stopped,Running" bitfld.long 0x00 1. " TIM23 ,Timers 2 and 3 Clock Gating" "Stopped,Running" textline " " bitfld.long 0x00 0. " TIM01 ,Timers 0 and 1 Clock Gating" "Stopped,Running" group.long 0x1C++0x3 line.long 0x0 "SCU_PRR0,Peripheral Reset Register 0" bitfld.long 0x00 12. " RST_PFQBC_AHB ,PFQBC AHB Reset" "Reset,No reset" bitfld.long 0x00 11. " RST_MAC ,Ethernet Peripheral Reset" "Reset,No reset" textline " " bitfld.long 0x00 9. " RST_USB ,USB Peripheral Reset" "Reset,No reset" bitfld.long 0x00 8. " RST_DMA ,DMA Peripheral Reset" "Reset,No reset" textline " " bitfld.long 0x00 6. " RST_EMI ,EMI Peripheral Reset" "Reset,No reset" bitfld.long 0x00 5. " RST_VIC ,VIC Peripheral Reset" "Reset,No reset" textline " " bitfld.long 0x00 4. " RST_SRAM_ARBITER ,SRAM Arbiter Reset" "Reset,No reset" bitfld.long 0x00 1. " RST_PQFBC ,PQFBC Reset" "Reset,No reset" textline " " bitfld.long 0x00 0. " RST_FMI ,FMI Reset" "Reset,No reset" group.long 0x20++0x3 line.long 0x0 "SCU_PRR1,Peripheral Reset Register 1" bitfld.long 0x00 24. " RTC ,RTC Reset" "Reset,No reset" bitfld.long 0x0 23. " GPIO9 ,GPIO9 Port Reset" "Reset,No reset" textline " " bitfld.long 0x0 22. " GPIO8 ,GPIO8 Port Reset" "Reset,No reset" bitfld.long 0x0 21. " GPIO7 ,GPIO7 Port Reset" "Reset,No reset" textline " " bitfld.long 0x0 20. " GPIO6 ,GPIO6 Port Reset" "Reset,No reset" bitfld.long 0x0 19. " GPIO5 ,GPIO5 Port Reset" "Reset,No reset" textline " " bitfld.long 0x0 18. " GPIO4 ,GPIO4 Port Reset" "Reset,No reset" bitfld.long 0x0 17. " GPIO3 ,GPIO3 Port Reset" "Reset,No reset" textline " " bitfld.long 0x0 16. " GPIO2 ,GPIO2 Port Reset" "Reset,No reset" bitfld.long 0x0 15. " GPIO1 ,GPIO1 Port Reset" "Reset,No reset" textline " " bitfld.long 0x0 14. " GPIO0 ,GPIO0 Port Reset" "Reset,No reset" bitfld.long 0x00 13. " WIU ,WIU Peripheral Reset" "Reset,No reset" textline " " bitfld.long 0x00 12. " WDG ,WDG Peripheral Reset" "Reset,No reset" bitfld.long 0x00 11. " ADC ,ADC Reset" "Reset,No reset" textline " " bitfld.long 0x00 10. " CAN ,CAN Peripheral Reset" "Reset,No reset" bitfld.long 0x00 9. " SSP1 ,SSP1 Peripheral Reset" "Reset,No reset" textline " " bitfld.long 0x00 8. " SSP0 ,SSP0 Peripheral Reset" "Reset,No reset" bitfld.long 0x00 7. " I2C1 ,I2C1 Peripheral Reset" "Reset,No reset" textline " " bitfld.long 0x00 6. " I2C0 ,I2C0 Peripheral Reset" "Reset,No reset" bitfld.long 0x00 5. " UART2 ,UART2 Peripheral Reset" "Reset,No reset" textline " " bitfld.long 0x00 4. " UART1 ,UART1 Peripheral Reset" "Reset,No reset" bitfld.long 0x00 3. " UART0 ,UART0 Peripheral Reset" "Reset,No reset" textline " " bitfld.long 0x00 2. " MC ,Motor Control Peripheral Reset" "Reset,No reset" bitfld.long 0x00 1. " TIM23 ,Timers 2 and 3 Reset" "Reset,No reset" textline " " bitfld.long 0x00 0. " TIM01 ,Timers 0 and 1 Reset" "Reset,No reset" tree.end width 0xC tree "Gating Registers" textline " " group.long 0x24++0x3 line.long 0x0 "SCU_MGR0,Idle Mode Gating Mask Register 0" bitfld.long 0x00 11. " MSK_MAC ,Ethernet Peripheral Gating Mask" "Stopped,Running" bitfld.long 0x00 10. " MSK_USB48M ,USB 48 MHz Clock Gating Mask" "Stopped,Running" bitfld.long 0x00 9. " MSK_USB ,USB Peripheral Clock Gating Mask" "Stopped,Running" textline " " bitfld.long 0x00 8. " MSK_DMA ,DMA Peripheral Clock Gating Mask" "Stopped,Running" bitfld.long 0x00 7. " MSK_EXT_MEM_CLK ,External Memory Clock Gating Mask" "Stopped,Running" bitfld.long 0x00 6. " MSK_EMI ,EMI Peripheral Clock Gating Mask" "Stopped,Running" textline " " bitfld.long 0x00 5. " MSK_VIC ,VIC Peripheral Clock Gating Mask" "Stopped,Running" bitfld.long 0x00 4. " MSK_SRAM_ARBITER ,SRAM Arbiter Clock Gating Mask" "Stopped,Running" bitfld.long 0x00 3. " MSK_SRAM ,SRAM Clock Gating Mask" "Stopped,Running" textline " " bitfld.long 0x00 1. " MSK_PQFBC ,PQFBC Clock Gating Mask" "Stopped,Running" group.long 0x28++0x3 line.long 0x0 "SCU_MGR1,Idle Mode Gating Mask Register 1" bitfld.long 0x00 24. " RTC ,RTC Clock Gating Mask" "Stopped,Running" bitfld.long 0x0 23. " GPIO9 ,GPIO9 Port Clock Gating Mask" "Stopped,Running" bitfld.long 0x0 22. " GPIO8 ,GPIO8 Port Clock Gating Mask" "Stopped,Running" textline " " bitfld.long 0x0 21. " GPIO7 ,GPIO7 Port Clock Gating Mask" "Stopped,Running" bitfld.long 0x0 20. " GPIO6 ,GPIO6 Port Clock Gating Mask" "Stopped,Running" bitfld.long 0x0 19. " GPIO5 ,GPIO5 Port Clock Gating Mask" "Stopped,Running" textline " " bitfld.long 0x0 18. " GPIO4 ,GPIO4 Port Clock Gating Mask" "Stopped,Running" bitfld.long 0x0 17. " GPIO3 ,GPIO3 Port Clock Gating Mask" "Stopped,Running" bitfld.long 0x0 16. " GPIO2 ,GPIO2 Port Clock Gating Mask" "Stopped,Running" textline " " bitfld.long 0x0 15. " GPIO1 ,GPIO1 Port Clock Gating Mask" "Stopped,Running" bitfld.long 0x0 14. " GPIO0 ,GPIO0 Port Clock Gating Mask" "Stopped,Running" bitfld.long 0x00 13. " WIU ,WIU Peripheral Clock Gating Mask" "Stopped,Running" textline " " bitfld.long 0x00 12. " WDG ,WDG Peripheral Clock Gating Mask" "Stopped,Running" bitfld.long 0x00 11. " ADC ,ADC Clock Gating Mask" "Stopped,Running" bitfld.long 0x00 10. " CAN ,CAN Peripheral Clock Gating Mask" "Stopped,Running" textline " " bitfld.long 0x00 9. " SSP1 ,SSP1 Peripheral Clock Gating Mask" "Stopped,Running" bitfld.long 0x00 8. " SSP0 ,SSP0 Peripheral Clock Gating Mask" "Stopped,Running" bitfld.long 0x00 7. " I2C1 ,I2C1 Peripheral Clock Gating Mask" "Stopped,Running" textline " " bitfld.long 0x00 6. " I2C0 ,I2C0 Peripheral Clock Gating Mask" "Stopped,Running" bitfld.long 0x00 5. " UART2 ,UART2 Peripheral Clock Gating Mask" "Stopped,Running" bitfld.long 0x00 4. " UART1 ,UART1 Peripheral Clock Gating Mask" "Stopped,Running" textline " " bitfld.long 0x00 3. " UART0 ,UART0 Peripheral Clock Gating Mask" "Stopped,Running" bitfld.long 0x00 2. " MC ,Motor Control Peripheral Clock Gating Mask" "Stopped,Running" bitfld.long 0x00 1. " TIM23 ,Timers 2 and 3 Clock Gating Mask" "Stopped,Running" textline " " bitfld.long 0x00 0. " TIM01 ,Timers 0 and 1 Clock Gating Mask" "Stopped,Running" group.long 0x2C++0x3 line.long 0x0 "SCU_PECGR0,Peripheral Emulation Clock Gating Register 0" bitfld.long 0x00 11. " MAC ,Ethernet Peripheral Clock Gating" "Stopped,Running" bitfld.long 0x00 10. " USB48M ,USB 48 MHz Clock Gating" "Stopped,Running" bitfld.long 0x00 9. " USB ,USB Peripheral Clock Gating" "Stopped,Running" textline " " bitfld.long 0x00 8. " DMA ,DMA Peripheral Clock Gating" "Stopped,Running" bitfld.long 0x00 7. " EXT_MEM_CLK ,External Memory Clock Gating" "Stopped,Running" bitfld.long 0x00 6. " EMI ,EMI Peripheral Clock Gating" "Stopped,Running" textline " " bitfld.long 0x00 5. " VIC ,VIC Peripheral Clock Gating" "Stopped,Running" bitfld.long 0x00 4. " SRAM_ARBITER ,SRAM Arbiter Clock Gating" "Stopped,Running" bitfld.long 0x00 3. " SRAM ,SRAM Clock Gating" "Stopped,Running" textline " " bitfld.long 0x00 1. " PQFBC ,PQFBC Clock Gating" "Stopped,Running" bitfld.long 0x00 0. " FMI ,FMI Clock Gating" "Stopped,Running" group.long 0x30++0x3 line.long 0x0 "SCU_PECGR1,Peripheral Emulation Clock Gating Register 1" bitfld.long 0x00 23. " GPIO9 ,GPIO9 Port Clock Gating" "Stopped,Running" bitfld.long 0x00 22. " GPIO8 ,GPIO8 Port Clock Gating" "Stopped,Running" bitfld.long 0x00 21. " GPIO7 ,GPIO7 Port Clock Gating" "Stopped,Running" textline " " bitfld.long 0x00 20. " GPIO6 ,GPIO6 Port Clock Gating" "Stopped,Running" bitfld.long 0x00 19. " GPIO5 ,GPIO5 Port Clock Gating" "Stopped,Running" bitfld.long 0x00 18. " GPIO4 ,GPIO4 Port Clock Gating" "Stopped,Running" textline " " bitfld.long 0x00 17. " GPIO3 ,GPIO3 Port Clock Gating" "Stopped,Running" bitfld.long 0x00 16. " GPIO2 ,GPIO3 Port Clock Gating" "Stopped,Running" bitfld.long 0x00 15. " GPIO1 ,GPIO1 Port Clock Gating" "Stopped,Running" textline " " bitfld.long 0x00 14. " GPIO0 ,GPIO0 Port Clock Gating" "Stopped,Running" bitfld.long 0x00 13. " WIU ,WIU Peripheral Clock Gating" "Stopped,Running" bitfld.long 0x00 12. " WDG ,WDG Peripheral Clock Gating" "Stopped,Running" textline " " bitfld.long 0x00 11. " ADC ,ADC Clock Gating" "Stopped,Running" bitfld.long 0x00 10. " CAN ,CAN Peripheral Clock Gating" "Stopped,Running" bitfld.long 0x00 9. " SSP1 ,SSP1 Peripheral Clock Gating" "Stopped,Running" textline " " bitfld.long 0x00 8. " SSP0 ,SSP0 Peripheral Clock Gating" "Stopped,Running" bitfld.long 0x00 7. " I2C1 ,I2C1 Peripheral Clock Gating" "Stopped,Running" bitfld.long 0x00 6. " I2C0 ,I2C0 Peripheral Clock Gating" "Stopped,Running" textline " " bitfld.long 0x00 5. " UART2 ,UART2 Peripheral Clock Gating" "Stopped,Running" bitfld.long 0x00 4. " UART1 ,UART1 Peripheral Clock Gating" "Stopped,Running" bitfld.long 0x00 3. " UART0 ,UART0 Peripheral Clock Gating" "Stopped,Running" textline " " bitfld.long 0x0 2. " MC ,Motor Control Peripheral Clock Gating" "Stopped,Running" bitfld.long 0x0 1. " TIM23 ,Timers 2 and 3 Clock Gating" "Stopped,Running" bitfld.long 0x0 0. " TIM01 ,Timers 0 and 1 Clock Gating" "Stopped,Running" tree.end textline " " width 0xB group.long 0x34++0x3 line.long 0x0 "SCU_SCR0,System Configuration Register 0" bitfld.long 0x00 14. " P30_SELEDBG ,GPIO Port 3 External Debug Configuration" "Not EDR/ETM,EDR/ETM" bitfld.long 0x00 13. " EXT_ETMT_EDBGR ,ETM Trigger/External Debug Selection" "Request,Trigger" bitfld.long 0x0 12. " UART_IRDA2 ,UART2 IrDA Mode Selection" "UART,IrDA" textline " " bitfld.long 0x0 11. " UART_IRDA1 ,UART1 IrDA Mode Selection" "UART,IrDA" bitfld.long 0x0 10. " UART_IRDA0 ,UART0 IrDA Mode Selection" "UART,IrDA" bitfld.long 0x00 8. " EMI_ALE_LNGT ,EMI Active Level Length" "1-cycle,2-cycle" textline " " bitfld.long 0x00 7. " EMI_ALE_POLR ,EMI Active Level Polarity" "Low,High" bitfld.long 0x00 6. " EMI_MUX ,EMI Mux/Demux" "Multiplexed,Demultiplexed" bitfld.long 0x00 5. " SRAM_LK_EN ,SRAM Arbiter Lock Transfer Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3.--4. " SRAM_SIZE[1:0] ,SRAM Size" "32-KB,64-KB,96-KB,?..." bitfld.long 0x00 2. " WSR_AHB ,AHB Wait State Enable" "No state,1 state" bitfld.long 0x00 1. " WSR_DTCM ,DTCM Wait State Enable" "No state,1 state" textline " " bitfld.long 0x00 0. " EN_PFQBC ,PFQBC Unit Enable" "Disabled,Enabled" group.long 0x38++0x3 line.long 0x0 "SCU_SCR1,System Configuration Register 1" group.long 0x3C++0x3 line.long 0x0 "SCU_SCR2,System Configuration Register 2" width 0x0E tree "GPIO Output/Input Registers" group.long 0x44++0x3 line.long 0x0 "SCU_GPIOOUT0,GPIO Output Register 0" bitfld.long 0x00 14.--15. " P0.7OUT[1:0] ,GPIO Port 0 Output 7 Control" "Input,GPIO_0.7,EMI_CS30,ETM_TRSYNC" bitfld.long 0x00 12.--13. " P0.6OUT[1:0] ,GPIO Port 0 Output 6 Control" "Input,GPIO_0.6,EMI_CS20,ETM_PSTAT2" bitfld.long 0x00 10.--11. " P0.5OUT[1:0] ,GPIO Port 0 Output 5 Control" "Input,GPIO_0.5,EMI_CS10,ETM_PSTAT1" textline " " bitfld.long 0x00 8.--9. " P0.4OUT[1:0] ,GPIO Port 0 Output 4 Control" "Input,GPIO_0.4,EMI_CS00,ETM_PSTAT0" bitfld.long 0x00 6.--7. " P0.3OUT[1:0] ,GPIO Port 0 Output 3 Control" "Input,GPIO_0.3,I2C1_DOUT,ETM_PCK3" bitfld.long 0x00 4.--5. " P0.2OUT[1:0] ,GPIO Port 0 Output 2 Control" "Input,GPIO_0.2,I2C1_CLKOUT,ETM_PCK2" textline " " bitfld.long 0x00 2.--3. " P0.1OUT[1:0] ,GPIO Port 0 Output 1 Control" "Input,GPIO_0.1,I2C0_DOUT,ETM_PCK1" bitfld.long 0x00 0.--1. " P0.0OUT[1:0] ,GPIO Port 0 Output 0 Control" "Input,GPIO_0.0,I2C0_CLKOUT,ETM_PCK0" group.long 0x48++0x3 line.long 0x0 "SCU_GPIOOUT1,GPIO Output Register 1" bitfld.long 0x00 14.--15. " P1.7OUT[1:0] ,GPIO Port 1 Output 7 Control" "Input,GPIO_1.7,MII_MDC,ETM_TRCLK" bitfld.long 0x00 12.--13. " P1.6OUT[1:0] ,GPIO Port 1 Output 6 Control" "Input,GPIO_1.6,CAN_TX,I2C0_DOUT" bitfld.long 0x00 10.--11. " P1.5OUT[1:0] ,GPIO Port 1 Output 5 Control" "Input,GPIO_1.5,UART2_TX,ETM_TRCLK" textline " " bitfld.long 0x00 8.--9. " P1.4OUT[1:0] ,GPIO Port 1 Output 4 Control" "Input,GPIO_1.4,MII_TXD3,I2C0_CLKOUT" bitfld.long 0x00 6.--7. " P1.3OUT[1:0] ,GPIO Port 1 Output 3 Control" "Input,GPIO_1.3,MII_TXD2,SSP1_NSS" bitfld.long 0x00 4.--5. " P1.2OUT[1:0] ,GPIO Port 1 Output 2 Control" "Input,GPIO_1.2,MII_TXD1,UART0_TX" textline " " bitfld.long 0x00 2.--3. " P1.1OUT[1:0] ,GPIO Port 1 Output 1 Control" "Input,GPIO_1.1,MII_TXD0,SSP1_MOSI" bitfld.long 0x00 0.--1. " P1.0OUT[1:0] ,GPIO Port 1 Output 0 Control" "Input,GPIO_1.0,UART1_TX,SSP1_SCLK" group.long 0x4C++0x3 line.long 0x0 "SCU_GPIOOUT2,GPIO Output Register 2" bitfld.long 0x00 14.--15. " P2.7OUT[1:0] ,GPIO Port 2 Output 7 Control" "Input,GPIO_2.7,SSP0_NSS,ETM_TRSYNC" bitfld.long 0x00 12.--13. " P2.6OUT[1:0] ,GPIO Port 2 Output 6 Control" "Input,GPIO_2.6,SSP0_MISO,ETM_PSTAT2" bitfld.long 0x00 10.--11. " P2.5OUT[1:0] ,GPIO Port 2 Output 5 Control" "Input,GPIO_2.5,SSP0_MOSI,ETM_PSTAT1" textline " " bitfld.long 0x00 8.--9. " P2.4OUT[1:0] ,GPIO Port 2 Output 4 Control" "Input,GPIO_2.4,SSP0_SCLK,ETM_PSTAT0" bitfld.long 0x00 6.--7. " P2.3OUT[1:0] ,GPIO Port 2 Output 3 Control" "Input,GPIO_2.3,I2C1_DOUT,ETM_PCK3" bitfld.long 0x00 4.--5. " P2.2OUT[1:0] ,GPIO Port 2 Output 2 Control" "Input,GPIO_2.2,I2C1_CLKOUT,ETM_PCK2" textline " " bitfld.long 0x00 2.--3. " P2.1OUT[1:0] ,GPIO Port 2 Output 1 Control" "Input,GPIO_2.1,I2C0_DOUT,ETM_PCK1" bitfld.long 0x00 0.--1. " P2.0OUT[1:0] ,GPIO Port 2 Output 0 Control" "Input,GPIO_2.0,I2C0_CLKOUT,ETM_PCK0" group.long 0x50++0x3 line.long 0x0 "SCU_GPIOOUT3,GPIO Output Register 3" bitfld.long 0x00 14.--15. " P3.7OUT[1:0] ,GPIO Port 3 Output 7 Control" "Input,GPIO_3.7,SSP1_NSS,TIM1_OCMP1" bitfld.long 0x00 12.--13. " P3.6OUT[1:0] ,GPIO Port 3 Output 6 Control" "Input,GPIO_3.6,SSP1_MOSI,CAN_TX" bitfld.long 0x00 10.--11. " P3.5OUT[1:0] ,GPIO Port 3 Output 5 Control" "Input,GPIO_3.5,SSP1_MISO,UART2_TX" textline " " bitfld.long 0x00 8.--9. " P3.4OUT[1:0] ,GPIO Port 3 Output 4 Control" "Input,GPIO_3.4,SSP1_SCLK,UART0_TX" bitfld.long 0x00 6.--7. " P3.3OUT[1:0] ,GPIO Port 3 Output 3 Control" "Input,GPIO_3.3,UART1_TX,UART0_RTS" bitfld.long 0x00 4.--5. " P3.2OUT[1:0] ,GPIO Port 3 Output 2 Control" "Input,GPIO_3.2,CAN_TX,UART0_DTR" textline " " bitfld.long 0x00 2.--3. " P3.1OUT[1:0] ,GPIO Port 3 Output 1 Control" "Input,GPIO_3.1,UART0_TX,TIM1_OCMP1" bitfld.long 0x00 0.--1. " P3.0OUT[1:0] ,GPIO Port 3 Output 0 Control" "Input,GPIO_3.0,UART2_TX,TIM0_OCMP1" group.long 0x54++0x3 line.long 0x0 "SCU_GPIOOUT4,GPIO Output Register 4" bitfld.long 0x00 14.--15. " P4.7OUT[1:0] ,GPIO Port 4 Output 7 Control" "Input,GPIO_4.7,TIM3_OCMP2,ETM_TRSYNC" bitfld.long 0x00 12.--13. " P4.6OUT[1:0] ,GPIO Port 4 Output 6 Control" "Input,GPIO_4.6,TIM3_OCMP1,ETM_PSTAT2" bitfld.long 0x00 10.--11. " P4.5OUT[1:0] ,GPIO Port 4 Output 5 Control" "Input,GPIO_4.5,TIM2_OCMP2,ETM_PSTAT1" textline " " bitfld.long 0x00 8.--9. " P4.4OUT[1:0] ,GPIO Port 4 Output 4 Control" "Input,GPIO_4.4,TIM2_OCMP1,ETM_PSTAT0" bitfld.long 0x00 6.--7. " P4.3OUT[1:0] ,GPIO Port 4 Output 3 Control" "Input,GPIO_4.3,TIM1_OCMP2,ETM_PCK3" bitfld.long 0x00 4.--5. " P4.2OUT[1:0] ,GPIO Port 4 Output 2 Control" "Input,GPIO_4.2,TIM1_OCMP,ETM_PCK2" textline " " bitfld.long 0x00 2.--3. " P4.1OUT[1:0] ,GPIO Port 4 Output 1 Control" "Input,GPIO_4.1,TIM0_OCMP2,ETM_PCK1" bitfld.long 0x00 0.--1. " P4.0OUT[1:0] ,GPIO Port 4 Output 0 Control" "Input,GPIO_4.0,TIM0_OCMP1,ETM_PCK0" group.long 0x58++0x3 line.long 0x0 "SCU_GPIOOUT5,GPIO Output Register 5" bitfld.long 0x00 14.--15. " P5.7OUT[1:0] ,GPIO Port 5 Output 7 Control" "Input,GPIO_5.7,SSP0_NSS,EMI_CS35" bitfld.long 0x00 12.--13. " P5.6OUT[1:0] ,GPIO Port 5 Output 6 Control" "Input,GPIO_5.6,SSP0_MISO,EMI_CS25" bitfld.long 0x00 10.--11. " P5.5OUT[1:0] ,GPIO Port 5 Output 5 Control" "Input,GPIO_5.5,SSP0_MOSI,EMI_CS15" textline " " bitfld.long 0x00 8.--9. " P5.4OUT[1:0] ,GPIO Port 5 Output 4 Control" "Input,GPIO_5.4,SSP0_SCLK,EMI_CS05" bitfld.long 0x00 6.--7. " P5.3OUT[1:0] ,GPIO Port 5 Output 3 Control" "Input,GPIO_5.3,MII_TX_EN,TIM2_OCMP1" bitfld.long 0x00 4.--5. " P5.2OUT[1:0] ,GPIO Port 5 Output 2 Control" "Input,GPIO_5.2,MII_PHYCLK,TIM3_OCMP1" textline " " bitfld.long 0x00 2.--3. " P5.1OUT[1:0] ,GPIO Port 5 Output 1 Control" "Input,GPIO_5.1,CAN_TX,UART2_TX" bitfld.long 0x00 0.--1. " P5.0OUT[1:0] ,GPIO Port 5 Output 0 Control" "Input,GPIO_5.0,ETM_TRCLK,UART0_TX" group.long 0x5C++0x3 line.long 0x0 "SCU_GPIOOUT6,GPIO Output Register 6" bitfld.long 0x00 14.--15. " P6.7OUT[1:0] ,GPIO Port 6 Output 7 Control" "Input,GPIO_6.7,TIM3_OCMP2,UART0_TX" bitfld.long 0x00 12.--13. " P6.6OUT[1:0] ,GPIO Port 6 Output 6 Control" "Input,GPIO_6.6,TIM3_OCMP1,ETM_TRCLK" bitfld.long 0x00 10.--11. " P6.5OUT[1:0] ,GPIO Port 6 Output 5 Control" "Input,GPIO_6.5,TIM2_OCMP2,MC_WL" textline " " bitfld.long 0x00 8.--9. " P6.4OUT[1:0] ,GPIO Port 6 Output 4 Control" "Input,GPIO_6.4,TIM2_OCMP1,MC_WH" bitfld.long 0x00 6.--7. " P6.3OUT[1:0] ,GPIO Port 6 Output 3 Control" "Input,GPIO_6.3,TIM1_OCMP2,MC_VL" bitfld.long 0x00 4.--5. " P6.2OUT[1:0] ,GPIO Port 6 Output 2 Control" "Input,GPIO_6.2,TIM1_OCMP1,MC_VH" textline " " bitfld.long 0x00 2.--3. " P6.1OUT[1:0] ,GPIO Port 6 Output 1 Control" "Input,GPIO_6.1,TIM0_OCMP2,MC_UL" bitfld.long 0x00 0.--1. " P6.0OUT[1:0] ,GPIO Port 6 Output 0 Control" "Input,GPIO_6.0,TIM0_OCMP1,MC_UH" group.long 0x60++0x3 line.long 0x0 "SCU_GPIOOUT7,GPIO Output Register 7" bitfld.long 0x00 14.--15. " P7.7OUT[1:0] ,GPIO Port 7 Output 7 Control" "Input,GPIO_7.7,EMI_CS0,EMI_A7/23" bitfld.long 0x00 12.--13. " P7.6OUT[1:0] ,GPIO Port 7 Output 6 Control" "Input,GPIO_7.6,EMI_A6/22,EMI_CS17" bitfld.long 0x00 10.--11. " P7.5OUT[1:0] ,GPIO Port 7 Output 5 Control" "Input,GPIO_7.5,EMI_A5/21,EMI_CS27" textline " " bitfld.long 0x00 8.--9. " P7.4OUT[1:0] ,GPIO Port 7 Output 4 Control" "Input,GPIO_7.4,EMI_A4/20,EMI_CS37" bitfld.long 0x00 6.--7. " P7.3OUT[1:0] ,GPIO Port 7 Output 3 Control" "Input,GPIO_7.3,EMI_A3/19,ETM_PCK3" bitfld.long 0x00 4.--5. " P7.2OUT[1:0] ,GPIO Port 7 Output 2 Control" "Input,GPIO_7.2,EMI_A2/18,ETM_PCK2" textline " " bitfld.long 0x00 2.--3. " P7.1OUT[1:0] ,GPIO Port 7 Output 1 Control" "Input,GPIO_7.1,EMI_A1/17,ETM_PCK1" bitfld.long 0x00 0.--1. " P7.0OUT[1:0] ,GPIO Port 7 Output 0 Control" "Input,GPIO_7.0,EMI_A0/16,ETM_PCK0" group.long 0x64++0x3 line.long 0x0 "SCU_GPIOIN0,GPIO Input Register 0" bitfld.long 0x0 7. " P0.7IN ,GPIO Port 0 Input 7 Control" "Not connected,TIM2_ICAP2" bitfld.long 0x0 6. " P0.6IN ,GPIO Port 0 Input 6 Control" "Not connected,TIM2_ICAP1" bitfld.long 0x0 5. " P0.5IN ,GPIO Port 0 Input 5 Control" "Not connected,TIM0_ICAP2" textline " " bitfld.long 0x0 4. " P0.4IN ,GPIO Port 0 Input 4 Control" "Not connected,TIM0_ICAP1" bitfld.long 0x0 3. " P0.3IN ,GPIO Port 0 Input 3 Control" "Not connected,I2C1_DIN" bitfld.long 0x0 2. " P0.2IN ,GPIO Port 0 Input 2 Control" "Not connected,I2C1_CLKIN" textline " " bitfld.long 0x0 1. " P0.1IN ,GPIO Port 0 Input 1 Control" "Not connected,I2C0_DIN" bitfld.long 0x0 0. " P0.0IN ,GPIO Port 0 Input 0 Control" "Not connected,I2C0_CLKIN" group.long 0x68++0x3 line.long 0x0 "SCU_GPIOIN1,GPIO Input Register 1" bitfld.long 0x0 7. " P1.7IN ,GPIO Port 1 Input 7 Control" "Not connected,ETM_EXTRIG" bitfld.long 0x0 6. " P1.6IN ,GPIO Port 1 Input 6 Control" "Not connected,I2C0_DIN" bitfld.long 0x0 5. " P1.5IN ,GPIO Port 1 Input 5 Control" "Not connected,CAN_RX" textline " " bitfld.long 0x0 4. " P1.4IN ,GPIO Port 1 Input 4 Control" "Not connected,I2C0_CLKIN" bitfld.long 0x0 3. " P1.3IN ,GPIO Port 1 Input 3 Control" "Not connected,UART2_RX" bitfld.long 0x0 2. " P1.2IN ,GPIO Port 1 Input 2 Control" "Not connected,SSP1_MISO" textline " " bitfld.long 0x0 1. " P1.1IN ,GPIO Port 1 Input 1 Control" "Not connected,UART1_RX" bitfld.long 0x0 0. " P1.0IN ,GPIO Port 1 Input 0 Control" "Not connected,ETM_EXTRIG" group.long 0x6C++0x3 line.long 0x0 "SCU_GPIOIN2,GPIO Input Register 2" bitfld.long 0x0 7. " P2.7IN ,GPIO Port 2 Input 7 Control" "Not connected,SSP0_NSS" bitfld.long 0x0 6. " P2.6IN ,GPIO Port 2 Input 6 Control" "Not connected,SSP0_MISO" bitfld.long 0x0 5. " P2.5IN ,GPIO Port 2 Input 5 Control" "Not connected,SSP0_MOSI" textline " " bitfld.long 0x0 4. " P2.4IN ,GPIO Port 2 Input 4 Control" "Not connected,SSP0_SCLK" bitfld.long 0x0 3. " P2.3IN ,GPIO Port 2 Input 3 Control" "Not connected,I2C1_DIN" bitfld.long 0x0 2. " P2.2IN ,GPIO Port 2 Input 2 Control" "Not connected,I2C1_CLKIN" textline " " bitfld.long 0x0 1. " P2.1IN ,GPIO Port 2 Input 1 Control" "Not connected,I2C0_DIN" bitfld.long 0x0 0. " P2.0IN ,GPIO Port 2 Input 0 Control" "Not connected,I2C0_CLKIN" group.long 0x70++0x3 line.long 0x0 "SCU_GPIOIN3,GPIO Input Register 3" bitfld.long 0x0 7. " P3.7IN ,GPIO Port 3 Input 7 Control" "Not connected,SSP1_NSS" bitfld.long 0x0 6. " P3.6IN ,GPIO Port 3 Input 6 Control" "Not connected,SSP1_MOSI" bitfld.long 0x0 5. " P3.5IN ,GPIO Port 3 Input 5 Control" "Not connected,SSP1_MISO" textline " " bitfld.long 0x0 4. " P3.4IN ,GPIO Port 3 Input 4 Control" "Not connected,SSP1_SCLK" bitfld.long 0x0 3. " P3.3IN ,GPIO Port 3 Input 3 Control" "Not connected,CAN_RX" bitfld.long 0x0 2. " P3.2IN ,GPIO Port 3 Input 2 Control" "Not connected,UART1_RxD" textline " " bitfld.long 0x0 1. " P3.1IN ,GPIO Port 3 Input 1 Control" "Not connected,UART2_RxD" bitfld.long 0x0 0. " P3.0IN ,GPIO Port 3 Input 0 Control" "Not connected,UART0_RxD" group.long 0x74++0x3 line.long 0x0 "SCU_GPIOIN4,GPIO Input Register 4" bitfld.long 0x0 7. " P4.7IN ,GPIO Port 4 Input 7 Control" "Not connected,TIM3_ICAP2" bitfld.long 0x0 6. " P4.6IN ,GPIO Port 4 Input 6 Control" "Not connected,TIM3_ICAP1" bitfld.long 0x0 5. " P4.5IN ,GPIO Port 4 Input 5 Control" "Not connected,TIM2_ICAP2" textline " " bitfld.long 0x0 4. " P4.4IN ,GPIO Port 4 Input 4 Control" "Not connected,TIM2_ICAP1" bitfld.long 0x0 3. " P4.3IN ,GPIO Port 4 Input 3 Control" "Not connected,TIM1_ICAP2" bitfld.long 0x0 2. " P4.2IN ,GPIO Port 4 Input 2 Control" "Not connected,TIM1_ICAP1" textline " " bitfld.long 0x0 1. " P4.1IN ,GPIO Port 4 Input 1 Control" "Not connected,TIM0_ICAP2" bitfld.long 0x0 0. " P4.0IN ,GPIO Port 4 Input 0 Control" "Not connected,TIM0_ICAP1" group.long 0x78++0x3 line.long 0x0 "SCU_GPIOIN5,GPIO Input Register 5" bitfld.long 0x0 7. " P5.7IN ,GPIO Port 5 Input 7 Control" "Not connected,SSP0_NSS" bitfld.long 0x0 6. " P5.6IN ,GPIO Port 5 Input 6 Control" "Not connected,SSP0_MISO" bitfld.long 0x0 5. " P5.5IN ,GPIO Port 5 Input 5 Control" "Not connected,SSP0_MOSI" textline " " bitfld.long 0x0 4. " P5.4IN ,GPIO Port 5 Input 4 Control" "Not connected,SSP0_SCLK" bitfld.long 0x0 3. " P5.3IN ,GPIO Port 5 Input 3 Control" "Not connected,ETM_EXTRIG" bitfld.long 0x0 2. " P5.2IN ,GPIO Port 5 Input 2 Control" "Not connected,UART2_RxD" textline " " bitfld.long 0x0 1. " P5.1IN ,GPIO Port 5 Input 1 Control" "Not connected,UART0_RxD" bitfld.long 0x0 0. " P5.0IN ,GPIO Port 5 Input 0 Control" "Not connected,CAN_RX" group.long 0x7C++0x3 line.long 0x0 "SCU_GPIOIN6,GPIO Input Register 6" bitfld.long 0x0 7. " P6.7IN ,GPIO Port 6 Input 7 Control" "Not connected,ETM_EXTRIG" bitfld.long 0x0 6. " P6.6IN ,GPIO Port 6 Input 6 Control" "Not connected,UART0_RxD" bitfld.long 0x0 5. " P6.5IN ,GPIO Port 6 Input 5 Control" "Not connected,TIM2_ICAP2" textline " " bitfld.long 0x0 4. " P6.4IN ,GPIO Port 6 Input 4 Control" "Not connected,TIM2_ICAP1" bitfld.long 0x0 3. " P6.3IN ,GPIO Port 6 Input 3 Control" "Not connected,TIM1_ICAP2" bitfld.long 0x0 2. " P6.2IN ,GPIO Port 6 Input 2 Control" "Not connected,TIM1_ICAP1" textline " " bitfld.long 0x0 1. " P6.1IN ,GPIO Port 6 Input 1 Control" "Not connected,TIM0_ICAP2" bitfld.long 0x0 0. " P6.0IN ,GPIO Port 6 Input 0 Control" "Not connected,TIM0_ICAP1" group.long 0x80++0x3 line.long 0x0 "SCU_GPIOIN7,GPIO Input Register 7" bitfld.long 0x0 7. " P7.7IN ,GPIO Port 7 Input 7 Control" "Not connected,TIM3_ICAP2" bitfld.long 0x0 6. " P7.6IN ,GPIO Port 7 Input 6 Control" "Not connected,TIM3_ICAP1" bitfld.long 0x0 5. " P7.5IN ,GPIO Port 7 Input 5 Control" "Not connected,ETM_EXTRIG" textline " " bitfld.long 0x0 4. " P7.4IN ,GPIO Port 7 Input 4 Control" "Not connected,UART0_RxD" bitfld.long 0x0 3. " P7.3IN ,GPIO Port 7 Input 3 Control" "Not connected,TIM2_ICAP2" bitfld.long 0x0 2. " P7.2IN ,GPIO Port 7 Input 2 Control" "Not connected,TIM2_ICAP1" textline " " bitfld.long 0x0 1. " P7.1IN ,GPIO Port 7 Input 1 Control" "Not connected,TIM0_ICAP2" bitfld.long 0x0 0. " P7.0IN ,GPIO Port 7 Input 0 Control" "Not connected,TIM0_ICAP1" tree.end width 0xF tree "GPIO Type Registers" textline " " group.long 0x84++0x3 line.long 0x0 "SCU_GPIOTYPE0,GPIO Type Register 0" bitfld.long 0x0 7. " TYPE7 ,GPIO Output Type 7" "Push-pull,Open collector" bitfld.long 0x0 6. " TYPE6 ,GPIO Output Type 6" "Push-pull,Open collector" bitfld.long 0x0 5. " TYPE5 ,GPIO Output Type 5" "Push-pull,Open collector" textline " " bitfld.long 0x0 4. " TYPE4 ,GPIO Output Type 4" "Push-pull,Open collector" bitfld.long 0x0 3. " TYPE3 ,GPIO Output Type 3" "Push-pull,Open collector" bitfld.long 0x0 2. " TYPE2 ,GPIO Output Type 2" "Push-pull,Open collector" textline " " bitfld.long 0x0 1. " TYPE1 ,GPIO Output Type 1" "Push-pull,Open collector" bitfld.long 0x0 0. " TYPE0 ,GPIO Output Type 0" "Push-pull,Open collector" group.long 0x88++0x3 line.long 0x0 "SCU_GPIOTYPE1,GPIO Type Register 1" bitfld.long 0x0 7. " TYPE7 ,GPIO Output Type 7" "Push-pull,Open collector" bitfld.long 0x0 6. " TYPE6 ,GPIO Output Type 6" "Push-pull,Open collector" bitfld.long 0x0 5. " TYPE5 ,GPIO Output Type 5" "Push-pull,Open collector" textline " " bitfld.long 0x0 4. " TYPE4 ,GPIO Output Type 4" "Push-pull,Open collector" bitfld.long 0x0 3. " TYPE3 ,GPIO Output Type 3" "Push-pull,Open collector" bitfld.long 0x0 2. " TYPE2 ,GPIO Output Type 2" "Push-pull,Open collector" textline " " bitfld.long 0x0 1. " TYPE1 ,GPIO Output Type 1" "Push-pull,Open collector" bitfld.long 0x0 0. " TYPE0 ,GPIO Output Type 0" "Push-pull,Open collector" group.long 0x8C++0x3 line.long 0x0 "SCU_GPIOTYPE2,GPIO Type Register 2" bitfld.long 0x0 7. " TYPE7 ,GPIO Output Type 7" "Push-pull,Open collector" bitfld.long 0x0 6. " TYPE6 ,GPIO Output Type 6" "Push-pull,Open collector" bitfld.long 0x0 5. " TYPE5 ,GPIO Output Type 5" "Push-pull,Open collector" textline " " bitfld.long 0x0 4. " TYPE4 ,GPIO Output Type 4" "Push-pull,Open collector" bitfld.long 0x0 3. " TYPE3 ,GPIO Output Type 3" "Push-pull,Open collector" bitfld.long 0x0 2. " TYPE2 ,GPIO Output Type 2" "Push-pull,Open collector" textline " " bitfld.long 0x0 1. " TYPE1 ,GPIO Output Type 1" "Push-pull,Open collector" bitfld.long 0x0 0. " TYPE0 ,GPIO Output Type 0" "Push-pull,Open collector" group.long 0x90++0x3 line.long 0x0 "SCU_GPIOTYPE3,GPIO Type Register 3" bitfld.long 0x0 7. " TYPE7 ,GPIO Output Type 7" "Push-pull,Open collector" bitfld.long 0x0 6. " TYPE6 ,GPIO Output Type 6" "Push-pull,Open collector" bitfld.long 0x0 5. " TYPE5 ,GPIO Output Type 5" "Push-pull,Open collector" textline " " bitfld.long 0x0 4. " TYPE4 ,GPIO Output Type 4" "Push-pull,Open collector" bitfld.long 0x0 3. " TYPE3 ,GPIO Output Type 3" "Push-pull,Open collector" bitfld.long 0x0 2. " TYPE2 ,GPIO Output Type 2" "Push-pull,Open collector" textline " " bitfld.long 0x0 1. " TYPE1 ,GPIO Output Type 1" "Push-pull,Open collector" bitfld.long 0x0 0. " TYPE0 ,GPIO Output Type 0" "Push-pull,Open collector" group.long 0x94++0x3 line.long 0x0 "SCU_GPIOTYPE4,GPIO Type Register 4" bitfld.long 0x0 7. " TYPE7 ,GPIO Output Type 7" "Push-pull,Open collector" bitfld.long 0x0 6. " TYPE6 ,GPIO Output Type 6" "Push-pull,Open collector" bitfld.long 0x0 5. " TYPE5 ,GPIO Output Type 5" "Push-pull,Open collector" textline " " bitfld.long 0x0 4. " TYPE4 ,GPIO Output Type 4" "Push-pull,Open collector" bitfld.long 0x0 3. " TYPE3 ,GPIO Output Type 3" "Push-pull,Open collector" bitfld.long 0x0 2. " TYPE2 ,GPIO Output Type 2" "Push-pull,Open collector" textline " " bitfld.long 0x0 1. " TYPE1 ,GPIO Output Type 1" "Push-pull,Open collector" bitfld.long 0x0 0. " TYPE0 ,GPIO Output Type 0" "Push-pull,Open collector" group.long 0x98++0x3 line.long 0x0 "SCU_GPIOTYPE5,GPIO Type Register 5" bitfld.long 0x0 7. " TYPE7 ,GPIO Output Type 7" "Push-pull,Open collector" bitfld.long 0x0 6. " TYPE6 ,GPIO Output Type 6" "Push-pull,Open collector" bitfld.long 0x0 5. " TYPE5 ,GPIO Output Type 5" "Push-pull,Open collector" textline " " bitfld.long 0x0 4. " TYPE4 ,GPIO Output Type 4" "Push-pull,Open collector" bitfld.long 0x0 3. " TYPE3 ,GPIO Output Type 3" "Push-pull,Open collector" bitfld.long 0x0 2. " TYPE2 ,GPIO Output Type 2" "Push-pull,Open collector" textline " " bitfld.long 0x0 1. " TYPE1 ,GPIO Output Type 1" "Push-pull,Open collector" bitfld.long 0x0 0. " TYPE0 ,GPIO Output Type 0" "Push-pull,Open collector" group.long 0x9C++0x3 line.long 0x0 "SCU_GPIOTYPE6,GPIO Type Register 6" bitfld.long 0x0 7. " TYPE7 ,GPIO Output Type 7" "Push-pull,Open collector" bitfld.long 0x0 6. " TYPE6 ,GPIO Output Type 6" "Push-pull,Open collector" bitfld.long 0x0 5. " TYPE5 ,GPIO Output Type 5" "Push-pull,Open collector" textline " " bitfld.long 0x0 4. " TYPE4 ,GPIO Output Type 4" "Push-pull,Open collector" bitfld.long 0x0 3. " TYPE3 ,GPIO Output Type 3" "Push-pull,Open collector" bitfld.long 0x0 2. " TYPE2 ,GPIO Output Type 2" "Push-pull,Open collector" textline " " bitfld.long 0x0 1. " TYPE1 ,GPIO Output Type 1" "Push-pull,Open collector" bitfld.long 0x0 0. " TYPE0 ,GPIO Output Type 0" "Push-pull,Open collector" group.long 0xA0++0x3 line.long 0x0 "SCU_GPIOTYPE7,GPIO Type Register 7" bitfld.long 0x0 7. " TYPE7 ,GPIO Output Type 7" "Push-pull,Open collector" bitfld.long 0x0 6. " TYPE6 ,GPIO Output Type 6" "Push-pull,Open collector" bitfld.long 0x0 5. " TYPE5 ,GPIO Output Type 5" "Push-pull,Open collector" textline " " bitfld.long 0x0 4. " TYPE4 ,GPIO Output Type 4" "Push-pull,Open collector" bitfld.long 0x0 3. " TYPE3 ,GPIO Output Type 3" "Push-pull,Open collector" bitfld.long 0x0 2. " TYPE2 ,GPIO Output Type 2" "Push-pull,Open collector" textline " " bitfld.long 0x0 1. " TYPE1 ,GPIO Output Type 1" "Push-pull,Open collector" bitfld.long 0x0 0. " TYPE0 ,GPIO Output Type 0" "Push-pull,Open collector" group.long 0xA4++0x3 line.long 0x0 "SCU_GPIOTYPE8,GPIO Type Register 8" bitfld.long 0x0 7. " TYPE7 ,GPIO Output Type 7" "Push-pull,Open collector" bitfld.long 0x0 6. " TYPE6 ,GPIO Output Type 6" "Push-pull,Open collector" bitfld.long 0x0 5. " TYPE5 ,GPIO Output Type 5" "Push-pull,Open collector" textline " " bitfld.long 0x0 4. " TYPE4 ,GPIO Output Type 4" "Push-pull,Open collector" bitfld.long 0x0 3. " TYPE3 ,GPIO Output Type 3" "Push-pull,Open collector" bitfld.long 0x0 2. " TYPE2 ,GPIO Output Type 2" "Push-pull,Open collector" textline " " bitfld.long 0x0 1. " TYPE1 ,GPIO Output Type 1" "Push-pull,Open collector" bitfld.long 0x0 0. " TYPE0 ,GPIO Output Type 0" "Push-pull,Open collector" group.long 0xA8++0x3 line.long 0x0 "SCU_GPIOTYPE9,GPIO Type Register 9" bitfld.long 0x0 7. " TYPE7 ,GPIO Output Type 7" "Push-pull,Open collector" bitfld.long 0x0 6. " TYPE6 ,GPIO Output Type 6" "Push-pull,Open collector" bitfld.long 0x0 5. " TYPE5 ,GPIO Output Type 5" "Push-pull,Open collector" textline " " bitfld.long 0x0 4. " TYPE4 ,GPIO Output Type 4" "Push-pull,Open collector" bitfld.long 0x0 3. " TYPE3 ,GPIO Output Type 3" "Push-pull,Open collector" bitfld.long 0x0 2. " TYPE2 ,GPIO Output Type 2" "Push-pull,Open collector" textline " " bitfld.long 0x0 1. " TYPE1 ,GPIO Output Type 1" "Push-pull,Open collector" bitfld.long 0x0 0. " TYPE0 ,GPIO Output Type 0" "Push-pull,Open collector" tree.end textline " " width 0xD group.long 0xAC++0x3 line.long 0x0 "SCU_EMI,GPIO External Memory Interface Register" bitfld.long 0x0 2. " EMI_WR_CONF ,EMI_WRLn And EMI_WRHn Pins Configuration" "Normal,Byte select signals" textline " " bitfld.long 0x0 1. " EMI_BCLK ,EMI_BCLK Clock Out Disable" "Enabled,Disabled" bitfld.long 0x0 0. " GPIOEMI ,GPIO EMI Selection" "GPIO,EMI" group.long 0xB0++0x3 line.long 0x0 "SCU_WKUPSEL,Wakeup Selection Register" bitfld.long 0x0 9.--11. " WKUP_SEL7[2:0] ,Wake-Up/External Interrupt Port 7 Selection" "EXINT24,EXINT25,EXINT26,EXINT27,EXINT28,EXINT29,EXINT30,EXINT31" bitfld.long 0x0 6.--8. " WKUP_SEL6[2:0] ,Wake-Up/External Interrupt Port 6 Selection" "EXINT16,EXINT17,EXINT18,EXINT19,EXINT20,EXINT21,EXINT22,EXINT23" bitfld.long 0x0 3.--5. " WKUP_SEL5[2:0] ,Wake-Up/External Interrupt Port 5 Selection" "EXINT8,EXINT9,EXINT10,EXINT11,EXINT12,EXINT13,EXINT14,EXINT15" textline " " bitfld.long 0x0 0.--2. " WKUP_SEL3[2:0] ,Wake-Up/External Interrupt Port 3 Selection" "RTC,USB,EXINT2,EXINT3,EXINT4,EXINT5,EXINT6,EXINT7" group.long 0xBC++0x3 line.long 0x0 "SCU_GPIOANA,GPIO Analog Mode Register" bitfld.long 0x0 7. " P47A ,GPIO Port 4 Analog Control 7" "Off,On" bitfld.long 0x0 6. " P46A ,GPIO Port 4 Analog Control 6" "Off,On" bitfld.long 0x0 5. " P45A ,GPIO Port 4 Analog Control 5" "Off,On" textline " " bitfld.long 0x0 4. " P44A ,GPIO Port 4 Analog Control 4" "Off,On" bitfld.long 0x0 3. " P43A ,GPIO Port 4 Analog Control 3" "Off,On" bitfld.long 0x0 2. " P42A ,GPIO Port 4 Analog Control 2" "Off,On" textline " " bitfld.long 0x0 1. " P41A ,GPIO Port 4 Analog Control 1" "Off,On" bitfld.long 0x0 0. " P40A ,GPIO Port 4 Analog Control 0" "Off,On" endif width 0xB tree.end tree.open "GPIO (General Purpose I/O Ports)" width 12. base asd:0x58006000 tree "GPIO0 (General Purpose I/O Port 0)" group.byte 0x3FC++0x0 line.byte 0x0 "GPIO0_DATA,GPIO0 Data Register" bitfld.byte 0x0 7. " D7 ,GPIO0 Data 7" "L,H" bitfld.byte 0x0 6. " D6 ,GPIO0 Data 6" "L,H" bitfld.byte 0x0 5. " D5 ,GPIO0 Data 5" "L,H" bitfld.byte 0x0 4. " D4 ,GPIO0 Data 4" "L,H" bitfld.byte 0x0 3. " D3 ,GPIO0 Data 3" "L,H" bitfld.byte 0x0 2. " D2 ,GPIO0 Data 2" "L,H" bitfld.byte 0x0 1. " D1 ,GPIO0 Data 1" "L,H" bitfld.byte 0x0 0. " D0 ,GPIO0 Data 0" "L,H" group.byte 0x400++0x0 line.byte 0x0 "GPIO0_DIR,GPIO0 Data Direction Register" bitfld.byte 0x0 7. " DIR7 ,GPIO0 Data Direction 7" "Input,Output" bitfld.byte 0x0 6. " DIR6 ,GPIO0 Data Direction 6" "Input,Output" bitfld.byte 0x0 5. " DIR5 ,GPIO0 Data Direction 5" "Input,Output" textline " " bitfld.byte 0x0 4. " DIR4 ,GPIO0 Data Direction 4" "Input,Output" bitfld.byte 0x0 3. " DIR3 ,GPIO0 Data Direction 3" "Input,Output" bitfld.byte 0x0 2. " DIR2 ,GPIO0 Data Direction 2" "Input,Output" textline " " bitfld.byte 0x0 1. " DIR1 ,GPIO0 Data Direction 1" "Input,Output" bitfld.byte 0x0 0. " DIR0 ,GPIO0 Data Direction 0" "Input,Output" group.byte 0x420++0x0 line.byte 0x0 "GPIO0_SEL,GPIO0 Mode Control Register" bitfld.byte 0x0 7. " GPIO0SEL7 ,GPIO0 Mode Control 7" "GPIO,?..." bitfld.byte 0x0 6. " GPIO0SEL6 ,GPIO0 Mode Control 6" "GPIO,?..." bitfld.byte 0x0 5. " GPIO0SEL5 ,GPIO0 Mode Control 5" "GPIO,?..." textline " " bitfld.byte 0x0 4. " GPIO0SEL4 ,GPIO0 Mode Control 4" "GPIO,?..." bitfld.byte 0x0 3. " GPIO0SEL3 ,GPIO0 Mode Control 3" "GPIO,?..." bitfld.byte 0x0 2. " GPIO0SEL2 ,GPIO0 Mode Control 2" "GPIO,?..." textline " " bitfld.byte 0x0 1. " GPIO0SEL1 ,GPIO0 Mode Control 1" "GPIO,?..." bitfld.byte 0x0 0. " GPIO0SEL0 ,GPIO0 Mode Control 0" "GPIO,?..." tree.end base asd:0x58007000 tree "GPIO1 (General Purpose I/O Port 1)" group.byte 0x3FC++0x0 line.byte 0x0 "GPIO1_DATA,GPIO1 Data Register" bitfld.byte 0x0 7. " D7 ,GPIO1 Data 7" "L,H" bitfld.byte 0x0 6. " D6 ,GPIO1 Data 6" "L,H" bitfld.byte 0x0 5. " D5 ,GPIO1 Data 5" "L,H" bitfld.byte 0x0 4. " D4 ,GPIO1 Data 4" "L,H" bitfld.byte 0x0 3. " D3 ,GPIO1 Data 3" "L,H" bitfld.byte 0x0 2. " D2 ,GPIO1 Data 2" "L,H" bitfld.byte 0x0 1. " D1 ,GPIO1 Data 1" "L,H" bitfld.byte 0x0 0. " D0 ,GPIO1 Data 0" "L,H" group.byte 0x400++0x0 line.byte 0x0 "GPIO1_DIR,GPIO1 Data Direction Register" bitfld.byte 0x0 7. " DIR7 ,GPIO1 Data Direction 7" "Input,Output" bitfld.byte 0x0 6. " DIR6 ,GPIO1 Data Direction 6" "Input,Output" bitfld.byte 0x0 5. " DIR5 ,GPIO1 Data Direction 5" "Input,Output" textline " " bitfld.byte 0x0 4. " DIR4 ,GPIO1 Data Direction 4" "Input,Output" bitfld.byte 0x0 3. " DIR3 ,GPIO1 Data Direction 3" "Input,Output" bitfld.byte 0x0 2. " DIR2 ,GPIO1 Data Direction 2" "Input,Output" textline " " bitfld.byte 0x0 1. " DIR1 ,GPIO1 Data Direction 1" "Input,Output" bitfld.byte 0x0 0. " DIR0 ,GPIO1 Data Direction 0" "Input,Output" group.byte 0x420++0x0 line.byte 0x0 "GPIO1_SEL,GPIO1 Mode Control Register" bitfld.byte 0x0 7. " GPIO1SEL7 ,GPIO1 Mode Control 7" "GPIO,?..." bitfld.byte 0x0 6. " GPIO1SEL6 ,GPIO1 Mode Control 6" "GPIO,?..." bitfld.byte 0x0 5. " GPIO1SEL5 ,GPIO1 Mode Control 5" "GPIO,?..." textline " " bitfld.byte 0x0 4. " GPIO1SEL4 ,GPIO1 Mode Control 4" "GPIO,?..." bitfld.byte 0x0 3. " GPIO1SEL3 ,GPIO1 Mode Control 3" "GPIO,?..." bitfld.byte 0x0 2. " GPIO1SEL2 ,GPIO1 Mode Control 2" "GPIO,?..." textline " " bitfld.byte 0x0 1. " GPIO1SEL1 ,GPIO1 Mode Control 1" "GPIO,?..." bitfld.byte 0x0 0. " GPIO1SEL0 ,GPIO1 Mode Control 0" "GPIO,?..." tree.end base asd:0x58008000 tree "GPIO2 (General Purpose I/O Port 2)" group.byte 0x3FC++0x0 line.byte 0x0 "GPIO2_DATA,GPIO2 Data Register" bitfld.byte 0x0 7. " D7 ,GPIO2 Data 7" "L,H" bitfld.byte 0x0 6. " D6 ,GPIO2 Data 6" "L,H" bitfld.byte 0x0 5. " D5 ,GPIO2 Data 5" "L,H" bitfld.byte 0x0 4. " D4 ,GPIO2 Data 4" "L,H" bitfld.byte 0x0 3. " D3 ,GPIO2 Data 3" "L,H" bitfld.byte 0x0 2. " D2 ,GPIO2 Data 2" "L,H" bitfld.byte 0x0 1. " D1 ,GPIO2 Data 1" "L,H" bitfld.byte 0x0 0. " D0 ,GPIO2 Data 0" "L,H" group.byte 0x400++0x0 line.byte 0x0 "GPIO2_DIR,GPIO2 Data Direction Register" bitfld.byte 0x0 7. " DIR7 ,GPIO2 Data Direction 7" "Input,Output" bitfld.byte 0x0 6. " DIR6 ,GPIO2 Data Direction 6" "Input,Output" bitfld.byte 0x0 5. " DIR5 ,GPIO2 Data Direction 5" "Input,Output" textline " " bitfld.byte 0x0 4. " DIR4 ,GPIO2 Data Direction 4" "Input,Output" bitfld.byte 0x0 3. " DIR3 ,GPIO2 Data Direction 3" "Input,Output" bitfld.byte 0x0 2. " DIR2 ,GPIO2 Data Direction 2" "Input,Output" textline " " bitfld.byte 0x0 1. " DIR1 ,GPIO2 Data Direction 1" "Input,Output" bitfld.byte 0x0 0. " DIR0 ,GPIO2 Data Direction 0" "Input,Output" group.byte 0x420++0x0 line.byte 0x0 "GPIO2_SEL,GPIO2 Mode Control Register" bitfld.byte 0x0 7. " GPIO2SEL7 ,GPIO2 Mode Control 7" "GPIO,?..." bitfld.byte 0x0 6. " GPIO2SEL6 ,GPIO2 Mode Control 6" "GPIO,?..." bitfld.byte 0x0 5. " GPIO2SEL5 ,GPIO2 Mode Control 5" "GPIO,?..." textline " " bitfld.byte 0x0 4. " GPIO2SEL4 ,GPIO2 Mode Control 4" "GPIO,?..." bitfld.byte 0x0 3. " GPIO2SEL3 ,GPIO2 Mode Control 3" "GPIO,?..." bitfld.byte 0x0 2. " GPIO2SEL2 ,GPIO2 Mode Control 2" "GPIO,?..." textline " " bitfld.byte 0x0 1. " GPIO2SEL1 ,GPIO2 Mode Control 1" "GPIO,?..." bitfld.byte 0x0 0. " GPIO2SEL0 ,GPIO2 Mode Control 0" "GPIO,?..." tree.end base asd:0x58009000 tree "GPIO3 (General Purpose I/O Port 3)" group.byte 0x3FC++0x0 line.byte 0x0 "GPIO3_DATA,GPIO3 Data Register" bitfld.byte 0x0 7. " D7 ,GPIO3 Data 7" "L,H" bitfld.byte 0x0 6. " D6 ,GPIO3 Data 6" "L,H" bitfld.byte 0x0 5. " D5 ,GPIO3 Data 5" "L,H" bitfld.byte 0x0 4. " D4 ,GPIO3 Data 4" "L,H" bitfld.byte 0x0 3. " D3 ,GPIO3 Data 3" "L,H" bitfld.byte 0x0 2. " D2 ,GPIO3 Data 2" "L,H" bitfld.byte 0x0 1. " D1 ,GPIO3 Data 1" "L,H" bitfld.byte 0x0 0. " D0 ,GPIO3 Data 0" "L,H" group.byte 0x400++0x0 line.byte 0x0 "GPIO3_DIR,GPIO3 Data Direction Register" bitfld.byte 0x0 7. " DIR7 ,GPIO3 Data Direction 7" "Input,Output" bitfld.byte 0x0 6. " DIR6 ,GPIO3 Data Direction 6" "Input,Output" bitfld.byte 0x0 5. " DIR5 ,GPIO3 Data Direction 5" "Input,Output" textline " " bitfld.byte 0x0 4. " DIR4 ,GPIO3 Data Direction 4" "Input,Output" bitfld.byte 0x0 3. " DIR3 ,GPIO3 Data Direction 3" "Input,Output" bitfld.byte 0x0 2. " DIR2 ,GPIO3 Data Direction 2" "Input,Output" textline " " bitfld.byte 0x0 1. " DIR1 ,GPIO3 Data Direction 1" "Input,Output" bitfld.byte 0x0 0. " DIR0 ,GPIO3 Data Direction 0" "Input,Output" group.byte 0x420++0x0 line.byte 0x0 "GPIO3_SEL,GPIO3 Mode Control Register" bitfld.byte 0x0 7. " GPIO3SEL7 ,GPIO3 Mode Control 7" "GPIO,?..." bitfld.byte 0x0 6. " GPIO3SEL6 ,GPIO3 Mode Control 6" "GPIO,?..." bitfld.byte 0x0 5. " GPIO3SEL5 ,GPIO3 Mode Control 5" "GPIO,?..." textline " " bitfld.byte 0x0 4. " GPIO3SEL4 ,GPIO3 Mode Control 4" "GPIO,?..." bitfld.byte 0x0 3. " GPIO3SEL3 ,GPIO3 Mode Control 3" "GPIO,?..." bitfld.byte 0x0 2. " GPIO3SEL2 ,GPIO3 Mode Control 2" "GPIO,?..." textline " " bitfld.byte 0x0 1. " GPIO3SEL1 ,GPIO3 Mode Control 1" "GPIO,?..." bitfld.byte 0x0 0. " GPIO3SEL0 ,GPIO3 Mode Control 0" "GPIO,?..." tree.end base asd:0x5800A000 tree "GPIO4 (General Purpose I/O Port 4)" group.byte 0x3FC++0x0 line.byte 0x0 "GPIO4_DATA,GPIO4 Data Register" bitfld.byte 0x0 7. " D7 ,GPIO4 Data 7" "L,H" bitfld.byte 0x0 6. " D6 ,GPIO4 Data 6" "L,H" bitfld.byte 0x0 5. " D5 ,GPIO4 Data 5" "L,H" bitfld.byte 0x0 4. " D4 ,GPIO4 Data 4" "L,H" bitfld.byte 0x0 3. " D3 ,GPIO4 Data 3" "L,H" bitfld.byte 0x0 2. " D2 ,GPIO4 Data 2" "L,H" bitfld.byte 0x0 1. " D1 ,GPIO4 Data 1" "L,H" bitfld.byte 0x0 0. " D0 ,GPIO4 Data 0" "L,H" group.byte 0x400++0x0 line.byte 0x0 "GPIO4_DIR,GPIO4 Data Direction Register" bitfld.byte 0x0 7. " DIR7 ,GPIO4 Data Direction 7" "Input,Output" bitfld.byte 0x0 6. " DIR6 ,GPIO4 Data Direction 6" "Input,Output" bitfld.byte 0x0 5. " DIR5 ,GPIO4 Data Direction 5" "Input,Output" textline " " bitfld.byte 0x0 4. " DIR4 ,GPIO4 Data Direction 4" "Input,Output" bitfld.byte 0x0 3. " DIR3 ,GPIO4 Data Direction 3" "Input,Output" bitfld.byte 0x0 2. " DIR2 ,GPIO4 Data Direction 2" "Input,Output" textline " " bitfld.byte 0x0 1. " DIR1 ,GPIO4 Data Direction 1" "Input,Output" bitfld.byte 0x0 0. " DIR0 ,GPIO4 Data Direction 0" "Input,Output" group.byte 0x420++0x0 line.byte 0x0 "GPIO4_SEL,GPIO4 Mode Control Register" bitfld.byte 0x0 7. " GPIO4SEL7 ,GPIO4 Mode Control 7" "GPIO,?..." bitfld.byte 0x0 6. " GPIO4SEL6 ,GPIO4 Mode Control 6" "GPIO,?..." bitfld.byte 0x0 5. " GPIO4SEL5 ,GPIO4 Mode Control 5" "GPIO,?..." textline " " bitfld.byte 0x0 4. " GPIO4SEL4 ,GPIO4 Mode Control 4" "GPIO,?..." bitfld.byte 0x0 3. " GPIO4SEL3 ,GPIO4 Mode Control 3" "GPIO,?..." bitfld.byte 0x0 2. " GPIO4SEL2 ,GPIO4 Mode Control 2" "GPIO,?..." textline " " bitfld.byte 0x0 1. " GPIO4SEL1 ,GPIO4 Mode Control 1" "GPIO,?..." bitfld.byte 0x0 0. " GPIO4SEL0 ,GPIO4 Mode Control 0" "GPIO,?..." tree.end base asd:0x5800B000 tree "GPIO5 (General Purpose I/O Port 5)" group.byte 0x3FC++0x0 line.byte 0x0 "GPIO5_DATA,GPIO5 Data Register" bitfld.byte 0x0 7. " D7 ,GPIO5 Data 7" "L,H" bitfld.byte 0x0 6. " D6 ,GPIO5 Data 6" "L,H" bitfld.byte 0x0 5. " D5 ,GPIO5 Data 5" "L,H" bitfld.byte 0x0 4. " D4 ,GPIO5 Data 4" "L,H" bitfld.byte 0x0 3. " D3 ,GPIO5 Data 3" "L,H" bitfld.byte 0x0 2. " D2 ,GPIO5 Data 2" "L,H" bitfld.byte 0x0 1. " D1 ,GPIO5 Data 1" "L,H" bitfld.byte 0x0 0. " D0 ,GPIO5 Data 0" "L,H" group.byte 0x400++0x0 line.byte 0x0 "GPIO5_DIR,GPIO5 Data Direction Register" bitfld.byte 0x0 7. " DIR7 ,GPIO5 Data Direction 7" "Input,Output" bitfld.byte 0x0 6. " DIR6 ,GPIO5 Data Direction 6" "Input,Output" bitfld.byte 0x0 5. " DIR5 ,GPIO5 Data Direction 5" "Input,Output" textline " " bitfld.byte 0x0 4. " DIR4 ,GPIO5 Data Direction 4" "Input,Output" bitfld.byte 0x0 3. " DIR3 ,GPIO5 Data Direction 3" "Input,Output" bitfld.byte 0x0 2. " DIR2 ,GPIO5 Data Direction 2" "Input,Output" textline " " bitfld.byte 0x0 1. " DIR1 ,GPIO5 Data Direction 1" "Input,Output" bitfld.byte 0x0 0. " DIR0 ,GPIO5 Data Direction 0" "Input,Output" group.byte 0x420++0x0 line.byte 0x0 "GPIO5_SEL,GPIO5 Mode Control Register" bitfld.byte 0x0 7. " GPIO5SEL7 ,GPIO5 Mode Control 7" "GPIO,?..." bitfld.byte 0x0 6. " GPIO5SEL6 ,GPIO5 Mode Control 6" "GPIO,?..." bitfld.byte 0x0 5. " GPIO5SEL5 ,GPIO5 Mode Control 5" "GPIO,?..." textline " " bitfld.byte 0x0 4. " GPIO5SEL4 ,GPIO5 Mode Control 4" "GPIO,?..." bitfld.byte 0x0 3. " GPIO5SEL3 ,GPIO5 Mode Control 3" "GPIO,?..." bitfld.byte 0x0 2. " GPIO5SEL2 ,GPIO5 Mode Control 2" "GPIO,?..." textline " " bitfld.byte 0x0 1. " GPIO5SEL1 ,GPIO5 Mode Control 1" "GPIO,?..." bitfld.byte 0x0 0. " GPIO5SEL0 ,GPIO5 Mode Control 0" "GPIO,?..." tree.end base asd:0x5800C000 tree "GPIO6 (General Purpose I/O Port 6)" group.byte 0x3FC++0x0 line.byte 0x0 "GPIO6_DATA,GPIO6 Data Register" bitfld.byte 0x0 7. " D7 ,GPIO6 Data 7" "L,H" bitfld.byte 0x0 6. " D6 ,GPIO6 Data 6" "L,H" bitfld.byte 0x0 5. " D5 ,GPIO6 Data 5" "L,H" bitfld.byte 0x0 4. " D4 ,GPIO6 Data 4" "L,H" bitfld.byte 0x0 3. " D3 ,GPIO6 Data 3" "L,H" bitfld.byte 0x0 2. " D2 ,GPIO6 Data 2" "L,H" bitfld.byte 0x0 1. " D1 ,GPIO6 Data 1" "L,H" bitfld.byte 0x0 0. " D0 ,GPIO6 Data 0" "L,H" group.byte 0x400++0x0 line.byte 0x0 "GPIO6_DIR,GPIO6 Data Direction Register" bitfld.byte 0x0 7. " DIR7 ,GPIO6 Data Direction 7" "Input,Output" bitfld.byte 0x0 6. " DIR6 ,GPIO6 Data Direction 6" "Input,Output" bitfld.byte 0x0 5. " DIR5 ,GPIO6 Data Direction 5" "Input,Output" textline " " bitfld.byte 0x0 4. " DIR4 ,GPIO6 Data Direction 4" "Input,Output" bitfld.byte 0x0 3. " DIR3 ,GPIO6 Data Direction 3" "Input,Output" bitfld.byte 0x0 2. " DIR2 ,GPIO6 Data Direction 2" "Input,Output" textline " " bitfld.byte 0x0 1. " DIR1 ,GPIO6 Data Direction 1" "Input,Output" bitfld.byte 0x0 0. " DIR0 ,GPIO6 Data Direction 0" "Input,Output" group.byte 0x420++0x0 line.byte 0x0 "GPIO6_SEL,GPIO6 Mode Control Register" bitfld.byte 0x0 7. " GPIO6SEL7 ,GPIO6 Mode Control 7" "GPIO,?..." bitfld.byte 0x0 6. " GPIO6SEL6 ,GPIO6 Mode Control 6" "GPIO,?..." bitfld.byte 0x0 5. " GPIO6SEL5 ,GPIO6 Mode Control 5" "GPIO,?..." textline " " bitfld.byte 0x0 4. " GPIO6SEL4 ,GPIO6 Mode Control 4" "GPIO,?..." bitfld.byte 0x0 3. " GPIO6SEL3 ,GPIO6 Mode Control 3" "GPIO,?..." bitfld.byte 0x0 2. " GPIO6SEL2 ,GPIO6 Mode Control 2" "GPIO,?..." textline " " bitfld.byte 0x0 1. " GPIO6SEL1 ,GPIO6 Mode Control 1" "GPIO,?..." bitfld.byte 0x0 0. " GPIO6SEL0 ,GPIO6 Mode Control 0" "GPIO,?..." tree.end base asd:0x5800D000 tree "GPIO7 (General Purpose I/O Port 7)" group.byte 0x3FC++0x0 line.byte 0x0 "GPIO7_DATA,GPIO7 Data Register" bitfld.byte 0x0 7. " D7 ,GPIO7 Data 7" "L,H" bitfld.byte 0x0 6. " D6 ,GPIO7 Data 6" "L,H" bitfld.byte 0x0 5. " D5 ,GPIO7 Data 5" "L,H" bitfld.byte 0x0 4. " D4 ,GPIO7 Data 4" "L,H" bitfld.byte 0x0 3. " D3 ,GPIO7 Data 3" "L,H" bitfld.byte 0x0 2. " D2 ,GPIO7 Data 2" "L,H" bitfld.byte 0x0 1. " D1 ,GPIO7 Data 1" "L,H" bitfld.byte 0x0 0. " D0 ,GPIO7 Data 0" "L,H" group.byte 0x400++0x0 line.byte 0x0 "GPIO7_DIR,GPIO7 Data Direction Register" bitfld.byte 0x0 7. " DIR7 ,GPIO7 Data Direction 7" "Input,Output" bitfld.byte 0x0 6. " DIR6 ,GPIO7 Data Direction 6" "Input,Output" bitfld.byte 0x0 5. " DIR5 ,GPIO7 Data Direction 5" "Input,Output" textline " " bitfld.byte 0x0 4. " DIR4 ,GPIO7 Data Direction 4" "Input,Output" bitfld.byte 0x0 3. " DIR3 ,GPIO7 Data Direction 3" "Input,Output" bitfld.byte 0x0 2. " DIR2 ,GPIO7 Data Direction 2" "Input,Output" textline " " bitfld.byte 0x0 1. " DIR1 ,GPIO7 Data Direction 1" "Input,Output" bitfld.byte 0x0 0. " DIR0 ,GPIO7 Data Direction 0" "Input,Output" group.byte 0x420++0x0 line.byte 0x0 "GPIO7_SEL,GPIO7 Mode Control Register" bitfld.byte 0x0 7. " GPIO7SEL7 ,GPIO7 Mode Control 7" "GPIO,?..." bitfld.byte 0x0 6. " GPIO7SEL6 ,GPIO7 Mode Control 6" "GPIO,?..." bitfld.byte 0x0 5. " GPIO7SEL5 ,GPIO7 Mode Control 5" "GPIO,?..." textline " " bitfld.byte 0x0 4. " GPIO7SEL4 ,GPIO7 Mode Control 4" "GPIO,?..." bitfld.byte 0x0 3. " GPIO7SEL3 ,GPIO7 Mode Control 3" "GPIO,?..." bitfld.byte 0x0 2. " GPIO7SEL2 ,GPIO7 Mode Control 2" "GPIO,?..." textline " " bitfld.byte 0x0 1. " GPIO7SEL1 ,GPIO7 Mode Control 1" "GPIO,?..." bitfld.byte 0x0 0. " GPIO7SEL0 ,GPIO7 Mode Control 0" "GPIO,?..." tree.end base asd:0x5800E000 tree "GPIO8 (General Purpose I/O Port 8)" group.byte 0x3FC++0x0 line.byte 0x0 "GPIO8_DATA,GPIO8 Data Register" bitfld.byte 0x0 7. " D7 ,GPIO8 Data 7" "L,H" bitfld.byte 0x0 6. " D6 ,GPIO8 Data 6" "L,H" bitfld.byte 0x0 5. " D5 ,GPIO8 Data 5" "L,H" bitfld.byte 0x0 4. " D4 ,GPIO8 Data 4" "L,H" bitfld.byte 0x0 3. " D3 ,GPIO8 Data 3" "L,H" bitfld.byte 0x0 2. " D2 ,GPIO8 Data 2" "L,H" bitfld.byte 0x0 1. " D1 ,GPIO8 Data 1" "L,H" bitfld.byte 0x0 0. " D0 ,GPIO8 Data 0" "L,H" group.byte 0x400++0x0 line.byte 0x0 "GPIO8_DIR,GPIO8 Data Direction Register" bitfld.byte 0x0 7. " DIR7 ,GPIO8 Data Direction 7" "Input,Output" bitfld.byte 0x0 6. " DIR6 ,GPIO8 Data Direction 6" "Input,Output" bitfld.byte 0x0 5. " DIR5 ,GPIO8 Data Direction 5" "Input,Output" textline " " bitfld.byte 0x0 4. " DIR4 ,GPIO8 Data Direction 4" "Input,Output" bitfld.byte 0x0 3. " DIR3 ,GPIO8 Data Direction 3" "Input,Output" bitfld.byte 0x0 2. " DIR2 ,GPIO8 Data Direction 2" "Input,Output" textline " " bitfld.byte 0x0 1. " DIR1 ,GPIO8 Data Direction 1" "Input,Output" bitfld.byte 0x0 0. " DIR0 ,GPIO8 Data Direction 0" "Input,Output" group.byte 0x420++0x0 line.byte 0x0 "GPIO8_SEL,GPIO8 Mode Control Register" bitfld.byte 0x0 7. " GPIO8SEL7 ,GPIO8 Mode Control 7" "GPIO,?..." bitfld.byte 0x0 6. " GPIO8SEL6 ,GPIO8 Mode Control 6" "GPIO,?..." bitfld.byte 0x0 5. " GPIO8SEL5 ,GPIO8 Mode Control 5" "GPIO,?..." textline " " bitfld.byte 0x0 4. " GPIO8SEL4 ,GPIO8 Mode Control 4" "GPIO,?..." bitfld.byte 0x0 3. " GPIO8SEL3 ,GPIO8 Mode Control 3" "GPIO,?..." bitfld.byte 0x0 2. " GPIO8SEL2 ,GPIO8 Mode Control 2" "GPIO,?..." textline " " bitfld.byte 0x0 1. " GPIO8SEL1 ,GPIO8 Mode Control 1" "GPIO,?..." bitfld.byte 0x0 0. " GPIO8SEL0 ,GPIO8 Mode Control 0" "GPIO,?..." tree.end base asd:0x5800F000 tree "GPIO9 (General Purpose I/O Port 9)" group.byte 0x3FC++0x0 line.byte 0x0 "GPIO9_DATA,GPIO9 Data Register" bitfld.byte 0x0 7. " D7 ,GPIO9 Data 7" "L,H" bitfld.byte 0x0 6. " D6 ,GPIO9 Data 6" "L,H" bitfld.byte 0x0 5. " D5 ,GPIO9 Data 5" "L,H" bitfld.byte 0x0 4. " D4 ,GPIO9 Data 4" "L,H" bitfld.byte 0x0 3. " D3 ,GPIO9 Data 3" "L,H" bitfld.byte 0x0 2. " D2 ,GPIO9 Data 2" "L,H" bitfld.byte 0x0 1. " D1 ,GPIO9 Data 1" "L,H" bitfld.byte 0x0 0. " D0 ,GPIO9 Data 0" "L,H" group.byte 0x400++0x0 line.byte 0x0 "GPIO9_DIR,GPIO9 Data Direction Register" bitfld.byte 0x0 7. " DIR7 ,GPIO9 Data Direction 7" "Input,Output" bitfld.byte 0x0 6. " DIR6 ,GPIO9 Data Direction 6" "Input,Output" bitfld.byte 0x0 5. " DIR5 ,GPIO9 Data Direction 5" "Input,Output" textline " " bitfld.byte 0x0 4. " DIR4 ,GPIO9 Data Direction 4" "Input,Output" bitfld.byte 0x0 3. " DIR3 ,GPIO9 Data Direction 3" "Input,Output" bitfld.byte 0x0 2. " DIR2 ,GPIO9 Data Direction 2" "Input,Output" textline " " bitfld.byte 0x0 1. " DIR1 ,GPIO9 Data Direction 1" "Input,Output" bitfld.byte 0x0 0. " DIR0 ,GPIO9 Data Direction 0" "Input,Output" group.byte 0x420++0x0 line.byte 0x0 "GPIO9_SEL,GPIO9 Mode Control Register" bitfld.byte 0x0 7. " GPIO9SEL7 ,GPIO9 Mode Control 7" "GPIO,?..." bitfld.byte 0x0 6. " GPIO9SEL6 ,GPIO9 Mode Control 6" "GPIO,?..." bitfld.byte 0x0 5. " GPIO9SEL5 ,GPIO9 Mode Control 5" "GPIO,?..." textline " " bitfld.byte 0x0 4. " GPIO9SEL4 ,GPIO9 Mode Control 4" "GPIO,?..." bitfld.byte 0x0 3. " GPIO9SEL3 ,GPIO9 Mode Control 3" "GPIO,?..." bitfld.byte 0x0 2. " GPIO9SEL2 ,GPIO9 Mode Control 2" "GPIO,?..." textline " " bitfld.byte 0x0 1. " GPIO9SEL1 ,GPIO9 Mode Control 1" "GPIO,?..." bitfld.byte 0x0 0. " GPIO9SEL0 ,GPIO9 Mode Control 0" "GPIO,?..." tree.end width 0xB tree.end tree.open "VIC (Vectored Interrupt Controller)" base asd:0xFFFFF000 width 13. sif (cpuis("STR910FA*")||cpuis("STR911FA*")||cpuis("STR912FA*")) tree "VIC0 (Vectored Interrupt Controller 0)" rgroup.long 0x0++0x3 line.long 0x0 "VIC0_ISR,IRQ Status Register" bitfld.long 0x0 15. " IRQSTATUS_ADC ,IRQ Status 15 (ADC)" "No interrupt,Interrupt" bitfld.long 0x0 14. " IRQSTATUS_MC ,IRQ Status 14 (Motor Control)" "No interrupt,Interrupt" textline " " bitfld.long 0x0 13. " IRQSTATUS_CAN ,IRQ Status 13 (CAN)" "No interrupt,Interrupt" bitfld.long 0x0 12. " IRQSTATUS_DMA ,IRQ Status 12 (DMA)" "No interrupt,Interrupt" textline " " sif (cpuis("STR912*")) bitfld.long 0x0 11. " IRQSTATUS_ENET ,IRQ Status 11 (Ethernet MAC)" "No interrupt,Interrupt" bitfld.long 0x0 10. " IRQSTATUS_SCU ,IRQ Status 10 (System Control Unit)" "No interrupt,Interrupt" else bitfld.long 0x0 10. " IRQSTATUS_SCU ,IRQ Status 10 (System Control Unit)" "No interrupt,Interrupt" endif textline " " sif (cpuis("STR911*")||cpuis("STR912*")) bitfld.long 0x0 9. " IRQSTATUS_USBL ,IRQ Status 9 (USB Low Priority)" "No interrupt,Interrupt" bitfld.long 0x0 8. " IRQSTATUS_USBH ,IRQ Status 8 (USB High Priority)" "No interrupt,Interrupt" textline " " endif bitfld.long 0x0 7. " IRQSTATUS_TIM3 ,IRQ Status 7 (Timer 3)" "No interrupt,Interrupt" bitfld.long 0x0 6. " IRQSTATUS_TIM2 ,IRQ Status 6 (Timer 2)" "No interrupt,Interrupt" textline " " bitfld.long 0x0 5. " IRQSTATUS_TIM1 ,IRQ Status 5 (Timer 1)" "No interrupt,Interrupt" bitfld.long 0x0 4. " IRQSTATUS_TIM0 ,IRQ Status 4 (Timer 0)" "No interrupt,Interrupt" textline " " bitfld.long 0x0 3. " IRQSTATUS_CPURX ,IRQ Status 3 (CPU Debug Transmit Command)" "No interrupt,Interrupt" bitfld.long 0x0 2. " IRQSTATUS_CPUTX ,IRQ Status 2 (CPU Debug Receive Command)" "No interrupt,Interrupt" textline " " bitfld.long 0x0 1. " IRQSTATUS_SOFT ,IRQ Status 1 (Software)" "No interrupt,Interrupt" bitfld.long 0x0 0. " IRQSTATUS_WDT ,IRQ Status 0 (Watchdog)" "No interrupt,Interrupt" rgroup.long 0x4++0x3 line.long 0x0 "VIC0_FSR,FIQ Status Register" bitfld.long 0x0 15. " FIQSTATUS_ADC ,FIQ Status 15 (ADC)" "No interrupt,Interrupt" bitfld.long 0x0 14. " FIQSTATUS_MC ,FIQ Status 14 (Motor Control)" "No interrupt,Interrupt" textline " " bitfld.long 0x0 13. " FIQSTATUS_CAN ,FIQ Status 13 (CAN)" "No interrupt,Interrupt" bitfld.long 0x0 12. " FIQSTATUS_DMA ,FIQ Status 12 (DMA)" "No interrupt,Interrupt" textline " " sif (cpuis("STR912*")) bitfld.long 0x0 11. " FIQSTATUS_ENET ,FIQ Status 11 (Ethernet MAC)" "No interrupt,Interrupt" bitfld.long 0x0 10. " FIQSTATUS_SCU ,FIQ Status 10 (System Control Unit)" "No interrupt,Interrupt" else bitfld.long 0x0 10. " FIQSTATUS_SCU ,FIQ Status 10 (System Control Unit)" "No interrupt,Interrupt" endif textline " " sif (cpuis("STR911*")||cpuis("STR912*")) bitfld.long 0x0 9. " FIQSTATUS_USBL ,FIQ Status 9 (USB Low Priority)" "No interrupt,Interrupt" bitfld.long 0x0 8. " FIQSTATUS_USBH ,FIQ Status 8 (USB High Priority)" "No interrupt,Interrupt" textline " " endif bitfld.long 0x0 7. " FIQSTATUS_TIM3 ,FIQ Status 7 (Timer 3)" "No interrupt,Interrupt" bitfld.long 0x0 6. " FIQSTATUS_TIM2 ,FIQ Status 6 (Timer 2)" "No interrupt,Interrupt" textline " " bitfld.long 0x0 5. " FIQSTATUS_TIM1 ,FIQ Status 5 (Timer 1)" "No interrupt,Interrupt" bitfld.long 0x0 4. " FIQSTATUS_TIM0 ,FIQ Status 4 (Timer 0)" "No interrupt,Interrupt" textline " " bitfld.long 0x0 3. " FIQSTATUS_CPUTX ,FIQ Status 3 (CPU Debug Transmit Command)" "No interrupt,Interrupt" bitfld.long 0x0 2. " FIQSTATUS_CPURX ,FIQ Status 2 (CPU Debug Receive Command)" "No interrupt,Interrupt" textline " " bitfld.long 0x0 1. " FIQSTATUS_SOFT ,FIQ Status 1 (Software)" "No interrupt,Interrupt" bitfld.long 0x0 0. " FIQSTATUS_WDT ,FIQ Status 0 (Watchdog)" "No interrupt,Interrupt" rgroup.long 0x8++0x3 line.long 0x0 "VIC0_RINTSR,Raw Interrupt Status Register" bitfld.long 0x0 15. " RAWINTR_ADC ,Raw Interrupt Status 15 (ADC)" "No interrupt,Interrupt" bitfld.long 0x0 14. " RAWINTR_MC ,Raw Interrupt Status 14 (Motor Control)" "No interrupt,Interrupt" textline " " bitfld.long 0x0 13. " RAWINTR_CAN ,Raw Interrupt Status 13 (CAN)" "No interrupt,Interrupt" bitfld.long 0x0 12. " RAWINTR_DMA ,Raw Interrupt Status 12 (DMA)" "No interrupt,Interrupt" textline " " sif (cpuis("STR912*")) bitfld.long 0x0 11. " RAWINTR_ENET ,Raw Interrupt Status 11 (Ethernet MAC)" "No interrupt,Interrupt" bitfld.long 0x0 10. " RAWINTR_SCU ,Raw Interrupt Status 10 (System Control Unit)" "No interrupt,Interrupt" else bitfld.long 0x0 10. " RAWINTR_SCU ,Raw Interrupt Status 10 (System Control Unit)" "No interrupt,Interrupt" endif textline " " sif (cpuis("STR911*")||cpuis("STR912*")) bitfld.long 0x0 9. " RAWINTR_USBL ,Raw Interrupt Status 9 (USB Low Priority)" "No interrupt,Interrupt" bitfld.long 0x0 8. " RAWINTR_USBH ,Raw Interrupt Status 8 (USB High Priority)" "No interrupt,Interrupt" textline " " endif bitfld.long 0x0 7. " RAWINTR_TIM3 ,Raw Interrupt Status 7 (Timer 3)" "No interrupt,Interrupt" bitfld.long 0x0 6. " RAWINTR_TIM2 ,Raw Interrupt Status 6 (Timer 2)" "No interrupt,Interrupt" textline " " bitfld.long 0x0 5. " RAWINTR_TIM1 ,Raw Interrupt Status 5 (Timer 1)" "No interrupt,Interrupt" bitfld.long 0x0 4. " RAWINTR_TIM0 ,Raw Interrupt Status 4 (Timer 0)" "No interrupt,Interrupt" textline " " bitfld.long 0x0 3. " RAWINTR_CPUTX ,Raw Interrupt Status 3 (CPU Debug Transmit Command)" "No interrupt,Interrupt" bitfld.long 0x0 2. " RAWINTR_CPURX ,Raw Interrupt Status 2 (CPU Debug Receive Command)" "No interrupt,Interrupt" textline " " bitfld.long 0x0 1. " RAWINTR_SOFT ,Raw Interrupt Status 1 (Software)" "No interrupt,Interrupt" bitfld.long 0x0 0. " RAWINTR_WDT ,Raw Interrupt Status 0 (Watchdog)" "No interrupt,Interrupt" group.long 0xC++0x3 line.long 0x0 "VIC0_INTSR,Interrupt Select Register" bitfld.long 0x0 15. " INTSELECT_ADC ,Interrupt Selection 15 (ADC)" "IRQ,FIQ" bitfld.long 0x0 14. " INTSELECT_MC ,Interrupt Selection 14 (Motor Control)" "IRQ,FIQ" textline " " bitfld.long 0x0 13. " INTSELECT_CAN ,Interrupt Selection 13 (CAN)" "IRQ,FIQ" bitfld.long 0x0 12. " INTSELECT_DMA ,Interrupt Selection 12 (DMA)" "IRQ,FIQ" textline " " sif (cpuis("STR912*")) bitfld.long 0x0 11. " INTSELECT_ENET ,Interrupt Selection 11 (Ethernet MAC)" "IRQ,FIQ" bitfld.long 0x0 10. " INTSELECT_SCU ,Interrupt Selection 10 (System Control Unit)" "IRQ,FIQ" else bitfld.long 0x0 10. " INTSELECT_SCU ,Interrupt Selection 10 (System Control Unit)" "IRQ,FIQ" endif textline " " sif (cpuis("STR911*")||cpuis("STR912*")) bitfld.long 0x0 9. " INTSELECT_USBL ,Interrupt Selection 9 (USB Low Priority)" "IRQ,FIQ" bitfld.long 0x0 8. " INTSELECT_USBH ,Interrupt Selection 8 (USB High Priority)" "IRQ,FIQ" textline " " endif bitfld.long 0x0 7. " INTSELECT_TIM3 ,Interrupt Selection 7 (Timer 3)" "IRQ,FIQ" bitfld.long 0x0 6. " INTSELECT_TIM2 ,Interrupt Selection 6 (Timer 2)" "IRQ,FIQ" textline " " bitfld.long 0x0 5. " INTSELECT_TIM1 ,Interrupt Selection 5 (Timer 1)" "IRQ,FIQ" bitfld.long 0x0 4. " INTSELECT_TIM0 ,Interrupt Selection 4 (Timer 0)" "IRQ,FIQ" textline " " bitfld.long 0x0 3. " INTSELECT_CPUTX ,Interrupt Selection 3 (CPU Debug Transmit Command)" "IRQ,FIQ" bitfld.long 0x0 2. " INTSELECT_CPURX ,Interrupt Selection 2 (CPU Debug Receive Command)" "IRQ,FIQ" textline " " bitfld.long 0x0 1. " INTSELECT_SOFT ,Interrupt Selection 1 (Software)" "IRQ,FIQ" bitfld.long 0x0 0. " INTSELECT_WDT ,Interrupt Selection 0 (Watchdog)" "IRQ,FIQ" group.long 0x10++0x3 line.long 0x0 "VIC0_INTER,Interrupt Enable Register" setclrfld.long 0x0 15. 0x0 15. 0x4 15. " INTENABLE_ADC_set/clr ,Interrupt Enable 15 (ADC)" "Disabled,Enabled" setclrfld.long 0x0 14. 0x0 14. 0x4 14. " INTENABLE_MC_set/clr ,Interrupt Enable 14 (Motor Control)" "Disabled,Enabled" textline " " setclrfld.long 0x0 13. 0x0 13. 0x4 13. " INTENABLE_CAN_set/clr ,Interrupt Enable 13 (CAN)" "Disabled,Enabled" setclrfld.long 0x0 12. 0x0 12. 0x4 12. " INTENABLE_DMA_set/clr ,Interrupt Enable 12 (DMA)" "Disabled,Enabled" textline " " sif (cpuis("STR912*")) setclrfld.long 0x0 11. 0x0 11. 0x4 11. " INTENABLE_ENET_set/clr ,Interrupt Enable 11 (Ethernet MAC)" "Disabled,Enabled" setclrfld.long 0x0 10. 0x0 10. 0x4 10. " INTENABLE_SCU_set/clr ,Interrupt Enable 10 (System Control Unit)" "Disabled,Enabled" else setclrfld.long 0x0 10. 0x0 10. 0x4 10. " INTENABLE_SCU_set/clr ,Interrupt Enable 10 (System Control Unit)" "Disabled,Enabled" endif textline " " sif (cpuis("STR911*")||cpuis("STR912*")) setclrfld.long 0x0 9. 0x0 9. 0x4 9. " INTENABLE_USBL_set/clr ,Interrupt Enable 9 (USB Low Priority)" "Disabled,Enabled" setclrfld.long 0x0 8. 0x0 8. 0x4 8. " INTENABLE_USBH_set/clr ,Interrupt Enable 8 (USB High Priority)" "Disabled,Enabled" textline " " endif setclrfld.long 0x0 7. 0x0 7. 0x4 7. " INTENABLE_TIM3_set/clr ,Interrupt Enable 7 (Timer 3)" "Disabled,Enabled" setclrfld.long 0x0 6. 0x0 6. 0x4 6. " INTENABLE_TIM2_set/clr ,Interrupt Enable 6 (Timer 2)" "Disabled,Enabled" textline " " setclrfld.long 0x0 5. 0x0 5. 0x4 5. " INTENABLE_TIM1_set/clr ,Interrupt Enable 5 (Timer 1)" "Disabled,Enabled" setclrfld.long 0x0 4. 0x0 4. 0x4 4. " INTENABLE_TIM0_set/clr ,Interrupt Enable 4 (Timer 0)" "Disabled,Enabled" textline " " setclrfld.long 0x0 3. 0x0 3. 0x4 3. " INTENABLE_CPUTX_set/clr ,Interrupt Enable 3 (CPU Debug Transmit Command)" "Disabled,Enabled" setclrfld.long 0x0 2. 0x0 2. 0x4 2. " INTENABLE_CPURX_set/clr ,Interrupt Enable 2 (CPU Debug Receive Command)" "Disabled,Enabled" textline " " setclrfld.long 0x0 1. 0x0 1. 0x4 1. " INTENABLE_SOFT_set/clr ,Interrupt Enable 1 (Software)" "Disabled,Enabled" setclrfld.long 0x0 0. 0x0 0. 0x4 0. " INTENABLE_WDT_set/clr ,Interrupt Enable 0 (Watchdog)" "Disabled,Enabled" group.long 0x18++0x3 line.long 0x0 "VIC0_SWINTR,Software Interrupt Register" setclrfld.long 0x0 15. 0x0 15. 0x4 15. " SOFTINT_ADC_set/clr ,Software Interrupt 15 (ADC)" "No interrupt,Interrupt" setclrfld.long 0x0 14. 0x0 14. 0x4 14. " SOFTINT_MC_set/clr ,Software Interrupt 14 (Motor Control)" "No interrupt,Interrupt" textline " " setclrfld.long 0x0 13. 0x0 13. 0x4 13. " SOFTINT_CAN_set/clr ,Software Interrupt 13 (CAN)" "No interrupt,Interrupt" setclrfld.long 0x0 12. 0x0 12. 0x4 12. " SOFTINT_DMA_set/clr ,Software Interrupt 12 (DMA)" "No interrupt,Interrupt" textline " " sif (cpuis("STR912*")) setclrfld.long 0x0 11. 0x0 11. 0x4 11. " SOFTINT_ENET_set/clr ,Software Interrupt 11 (Ethernet MAC)" "No interrupt,Interrupt" setclrfld.long 0x0 10. 0x0 10. 0x4 10. " SOFTINT_SCU_set/clr ,Software Interrupt 10 (System Control Unit)" "No interrupt,Interrupt" else setclrfld.long 0x0 10. 0x0 10. 0x4 10. " SOFTINT_SCU_set/clr ,Software Interrupt 10 (System Control Unit)" "No interrupt,Interrupt" endif textline " " sif (cpuis("STR911*")||cpuis("STR912*")) setclrfld.long 0x0 9. 0x0 9. 0x4 9. " SOFTINT_USBL_set/clr ,Software Interrupt 9 (USB Low Priority)" "No interrupt,Interrupt" setclrfld.long 0x0 8. 0x0 8. 0x4 8. " SOFTINT_USBH_set/clr ,Software Interrupt 8 (USB High Priority)" "No interrupt,Interrupt" textline " " endif setclrfld.long 0x0 7. 0x0 7. 0x4 7. " SOFTINT7_TIM3_set/clr ,Software Interrupt 7 (Timer 3)" "No interrupt,Interrupt" setclrfld.long 0x0 6. 0x0 6. 0x4 6. " SOFTINT_TIM2_set/clr ,Software Interrupt 6 (Timer 2)" "No interrupt,Interrupt" textline " " setclrfld.long 0x0 5. 0x0 5. 0x4 5. " SOFTINT_TIM1_set/clr ,Software Interrupt 5 (Timer 1)" "No interrupt,Interrupt" setclrfld.long 0x0 4. 0x0 4. 0x4 4. " SOFTINT_TIM0_set/clr ,Software Interrupt 4 (Timer 0)" "No interrupt,Interrupt" textline " " setclrfld.long 0x0 3. 0x0 3. 0x4 3. " SOFTINT_CPUTX_set/clr ,Software Interrupt 3 (CPU Debug Transmit Command)" "No interrupt,Interrupt" setclrfld.long 0x0 2. 0x0 2. 0x4 2. " SOFTINT_CPURX_set/clr ,Software Interrupt 2 (CPU Debug Receive Command)" "No interrupt,Interrupt" textline " " setclrfld.long 0x0 1. 0x0 1. 0x4 1. " SOFTINT_SOFT_set/clr ,Software Interrupt 1 (Software)" "No interrupt,Interrupt" setclrfld.long 0x0 0. 0x0 0. 0x4 0. " SOFTINT_WDT_set/clr ,Software Interrupt 0 (Watchdog)" "No interrupt,Interrupt" group.long 0x20++0x3 line.long 0x0 "VIC0_PER,Protection Enable Register" bitfld.long 0x0 0. " PROT ,Protection" "Not protected,Protected" width 0xC tree "Vector Registers" hgroup.long 0x30++0x3 hide.long 0x0 "VIC0_VAR,Current Vector Address Register" in group.long 0x34++0x3 line.long 0x0 "VIC0_DVAR,Default Vector Address Register" group.long 0x100++0x3 line.long 0x0 "VIC0_VA0R,Vector Address 0 Register" group.long 0x104++0x3 line.long 0x0 "VIC0_VA1R,Vector Address 1 Register" group.long 0x108++0x3 line.long 0x0 "VIC0_VA2R,Vector Address 2 Register" group.long 0x10C++0x3 line.long 0x0 "VIC0_VA3R,Vector Address 3 Register" group.long 0x110++0x3 line.long 0x0 "VIC0_VA4R,Vector Address 4 Register" group.long 0x114++0x3 line.long 0x0 "VIC0_VA5R,Vector Address 5 Register" group.long 0x118++0x3 line.long 0x0 "VIC0_VA6R,Vector Address 6 Register" group.long 0x11C++0x3 line.long 0x0 "VIC0_VA7R,Vector Address 7 Register" group.long 0x120++0x3 line.long 0x0 "VIC0_VA8R,Vector Address 8 Register" group.long 0x124++0x3 line.long 0x0 "VIC0_VA9R,Vector Address 9 Register" group.long 0x128++0x3 line.long 0x0 "VIC0_VA10R,Vector Address 10 Register" group.long 0x12C++0x3 line.long 0x0 "VIC0_VA11R,Vector Address 11 Register" group.long 0x130++0x3 line.long 0x0 "VIC0_VA12R,Vector Address 12 Register" group.long 0x134++0x3 line.long 0x0 "VIC0_VA13R,Vector Address 13 Register" group.long 0x138++0x3 line.long 0x0 "VIC0_VA14R,Vector Address 14 Register" group.long 0x13C++0x3 line.long 0x0 "VIC0_VA15R,Vector Address 15 Register" group.long 0x200++0x3 line.long 0x0 "VIC0_VC0R,Vector Control 0 Register" bitfld.long 0x0 5. " E0 ,Vector Interrupt 0 Enable" "Disabled,Enabled" bitfld.long 0x0 0.--4. " VectorCntl0[4:0] ,Vector Control 0" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 8,Source 9,Source 10,Source 11,Source 12,Source 13,Source 14,Source 15,?..." group.long 0x204++0x3 line.long 0x0 "VIC0_VC1R,Vector Control 1 Register" bitfld.long 0x0 5. " E1 ,Vector Interrupt 1 Enable" "Disabled,Enabled" bitfld.long 0x0 0.--4. " VectorCntl1[4:0] ,Vector Control 1" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 8,Source 9,Source 10,Source 11,Source 12,Source 13,Source 14,Source 15,?..." group.long 0x208++0x3 line.long 0x0 "VIC0_VC2R,Vector Control 2 Register" bitfld.long 0x0 5. " E2 ,Vector Interrupt 2 Enable" "Disabled,Enabled" bitfld.long 0x0 0.--4. " VectorCntl2[4:0] ,Vector Control 2" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 8,Source 9,Source 10,Source 11,Source 12,Source 13,Source 14,Source 15,?..." group.long 0x20C++0x3 line.long 0x0 "VIC0_VC3R,Vector Control 3 Register" bitfld.long 0x0 5. " E3 ,Vector Interrupt 3 Enable" "Disabled,Enabled" bitfld.long 0x0 0.--4. " VectorCntl3[4:0] ,Vector Control 3" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 8,Source 9,Source 10,Source 11,Source 12,Source 13,Source 14,Source 15,?..." group.long 0x210++0x3 line.long 0x0 "VIC0_VC4R,Vector Control 4 Register" bitfld.long 0x0 5. " E4 ,Vector Interrupt 4 Enable" "Disabled,Enabled" bitfld.long 0x0 0.--4. " VectorCntl4[4:0] ,Vector Control 4" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 8,Source 9,Source 10,Source 11,Source 12,Source 13,Source 14,Source 15,?..." group.long 0x214++0x3 line.long 0x0 "VIC0_VC5R,Vector Control 5 Register" bitfld.long 0x0 5. " E5 ,Vector Interrupt 5 Enable" "Disabled,Enabled" bitfld.long 0x0 0.--4. " VectorCntl5[4:0] ,Vector Control 5" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 8,Source 9,Source 10,Source 11,Source 12,Source 13,Source 14,Source 15,?..." group.long 0x218++0x3 line.long 0x0 "VIC0_VC6R,Vector Control 6 Register" bitfld.long 0x0 5. " E6 ,Vector Interrupt 6 Enable" "Disabled,Enabled" bitfld.long 0x0 0.--4. " VectorCntl6[4:0] ,Vector Control 6" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 8,Source 9,Source 10,Source 11,Source 12,Source 13,Source 14,Source 15,?..." group.long 0x21C++0x3 line.long 0x0 "VIC0_VC7R,Vector Control 7 Register" bitfld.long 0x0 5. " E7 ,Vector Interrupt 7 Enable" "Disabled,Enabled" bitfld.long 0x0 0.--4. " VectorCntl7[4:0] ,Vector Control 7" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 8,Source 9,Source 10,Source 11,Source 12,Source 13,Source 14,Source 15,?..." group.long 0x220++0x3 line.long 0x0 "VIC0_VC8R,Vector Control 8 Register" bitfld.long 0x0 5. " E8 ,Vector Interrupt 8 Enable" "Disabled,Enabled" bitfld.long 0x0 0.--4. " VectorCntl8[4:0] ,Vector Control 8" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 8,Source 9,Source 10,Source 11,Source 12,Source 13,Source 14,Source 15,?..." group.long 0x224++0x3 line.long 0x0 "VIC0_VC9R,Vector Control 9 Register" bitfld.long 0x0 5. " E9 ,Vector Interrupt 9 Enable" "Disabled,Enabled" bitfld.long 0x0 0.--4. " VectorCntl9[4:0] ,Vector Control 9" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 8,Source 9,Source 10,Source 11,Source 12,Source 13,Source 14,Source 15,?..." group.long 0x228++0x3 line.long 0x0 "VIC0_VC10R,Vector Control 10 Register" bitfld.long 0x0 5. " E10 ,Vector Interrupt 10 Enable" "Disabled,Enabled" bitfld.long 0x0 0.--4. " VectorCntl10[4:0] ,Vector Control 10" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 8,Source 9,Source 10,Source 11,Source 12,Source 13,Source 14,Source 15,?..." group.long 0x22C++0x3 line.long 0x0 "VIC0_VC11R,Vector Control 11 Register" bitfld.long 0x0 5. " E11 ,Vector Interrupt 11 Enable" "Disabled,Enabled" bitfld.long 0x0 0.--4. " VectorCntl11[4:0] ,Vector Control 11" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 8,Source 9,Source 10,Source 11,Source 12,Source 13,Source 14,Source 15,?..." group.long 0x230++0x3 line.long 0x0 "VIC0_VC12R,Vector Control 12 Register" bitfld.long 0x0 5. " E12 ,Vector Interrupt 12 Enable" "Disabled,Enabled" bitfld.long 0x0 0.--4. " VectorCntl12[4:0] ,Vector Control 12" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 8,Source 9,Source 10,Source 11,Source 12,Source 13,Source 14,Source 15,?..." group.long 0x234++0x3 line.long 0x0 "VIC0_VC13R,Vector Control 13 Register" bitfld.long 0x0 5. " E13 ,Vector Interrupt 13 Enable" "Disabled,Enabled" bitfld.long 0x0 0.--4. " VectorCntl13[4:0] ,Vector Control 13" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 8,Source 9,Source 10,Source 11,Source 12,Source 13,Source 14,Source 15,?..." group.long 0x238++0x3 line.long 0x0 "VIC0_VC14R,Vector Control 14 Register" bitfld.long 0x0 5. " E14 ,Vector Interrupt 14 Enable" "Disabled,Enabled" bitfld.long 0x0 0.--4. " VectorCntl14[4:0] ,Vector Control 14" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 8,Source 9,Source 10,Source 11,Source 12,Source 13,Source 14,Source 15,?..." group.long 0x23C++0x3 line.long 0x0 "VIC0_VC15R,Vector Control 15 Register" bitfld.long 0x0 5. " E15 ,Vector Interrupt 15 Enable" "Disabled,Enabled" bitfld.long 0x0 0.--4. " VectorCntl15[4:0] ,Vector Control 15" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 8,Source 9,Source 10,Source 11,Source 12,Source 13,Source 14,Source 15,?..." tree.end tree.end base asd:0xFC000000 tree "VIC1 (Vectored Interrupt Controller 1)" rgroup.long 0x0++0x3 line.long 0x0 "VIC1_ISR,IRQ Status Register" bitfld.long 0x0 15. " IRQSTATUS_PFQ-BC ,IRQ Status 15 (Prefetch Queue and Branch)" "No interrupt,Interrupt" sif (cpuis("STR911*")||cpuis("STR912*")) bitfld.long 0x0 14. " IRQSTATUS_USBBR ,IRQ Status 14 (USB Bus Resume)" "No interrupt,Interrupt" endif textline " " bitfld.long 0x0 13. " IRQSTATUS_WIU3 ,IRQ Status 13 (P7.0 to P7.7)" "No interrupt,Interrupt" bitfld.long 0x0 12. " IRQSTATUS_WIU2 ,IRQ Status 12 (pins P6.0 to P6.7" "No interrupt,Interrupt" textline " " bitfld.long 0x0 11. " IRQSTATUS_WIU1 ,IRQ Status 11 (pins P5.0 to P5.7)" "No interrupt,Interrupt" bitfld.long 0x0 10. " IRQSTATUS_WIU0 ,IRQ Status 10 (RTC or USB Resume or pins P3.2 to P3.7)" "No interrupt,Interrupt" textline " " bitfld.long 0x0 9. " IRQSTATUS_WIUALL ,IRQ Status 9 (All 32 inputs of Wake-Up unit)" "No interrupt,Interrupt" bitfld.long 0x0 8. " IRQSTATUS_RTC ,IRQ Status 8 (Alarm or Tamper or Periodic Timer)" "No interrupt,Interrupt" textline " " bitfld.long 0x0 7. " IRQSTATUS_SCU ,IRQ Status 7 (LVD early warning / Brownout)" "No interrupt,Interrupt" bitfld.long 0x0 6. " IRQSTATUS_SSP1 ,IRQ Status 6 (SSP1)" "No interrupt,Interrupt" textline " " bitfld.long 0x0 5. " IRQSTATUS_SSP0 ,IRQ Status 5 (SSP0)" "No interrupt,Interrupt" bitfld.long 0x0 4. " IRQSTATUS_I2C1 ,IRQ Status 4 (I2C channel 1)" "No interrupt,Interrupt" textline " " bitfld.long 0x0 3. " IRQSTATUS_I2C0 ,IRQ Status (I2C channel 0)" "No interrupt,Interrupt" bitfld.long 0x0 2. " IRQSTATUS_UART2 ,IRQ Status (UART channel 2)" "No interrupt,Interrupt" textline " " bitfld.long 0x0 1. " IRQSTATUS_UART1 ,IRQ Status (UART channel 1)" "No interrupt,Interrupt" bitfld.long 0x0 0. " IRQSTATUS_UART0 ,IRQ Status (UART channel 0)" "No interrupt,Interrupt" rgroup.long 0x4++0x3 line.long 0x0 "VIC1_FSR,FIQ Status Register" bitfld.long 0x0 15. " FIQSTATUS_PFQ-BC ,FIQ Status 15 (Prefetch Queue and Branch)" "No interrupt,Interrupt" sif (cpuis("STR911*")||cpuis("STR912*")) bitfld.long 0x0 14. " FIQSTATUS_USBBR ,FIQ Status 14 (USB Bus Resume)" "No interrupt,Interrupt" endif textline " " bitfld.long 0x0 13. " FIQSTATUS_WIU3 ,FIQ Status 13 (P7.0 to P7.7)" "No interrupt,Interrupt" bitfld.long 0x0 12. " FIQSTATUS_WIU2 ,FIQ Status 12 (pins P6.0 to P6.7" "No interrupt,Interrupt" textline " " bitfld.long 0x0 11. " FIQSTATUS_WIU1 ,FIQ Status 11 (pins P5.0 to P5.7)" "No interrupt,Interrupt" bitfld.long 0x0 10. " FIQSTATUS_WIU0 ,FIQ Status 10 ( RTC or USB Resume or pins P3.2 to P3.7)" "No interrupt,Interrupt" textline " " bitfld.long 0x0 9. " FIQSTATUS_WIUALL ,FIQ Status 9 (All 32 inputs of Wake-Up unit)" "No interrupt,Interrupt" bitfld.long 0x0 8. " FIQSTATUS_RTC ,FIQ Status 8 (Alarm or Tamper or Periodic Timer)" "No interrupt,Interrupt" textline " " bitfld.long 0x0 7. " FIQSTATUS_SCU ,FIQ Status 7 (LVD early warning / Brownout)" "No interrupt,Interrupt" bitfld.long 0x0 6. " FIQSTATUS_SSP1 ,FIQ Status 6 (SSP1)" "No interrupt,Interrupt" textline " " bitfld.long 0x0 5. " FIQSTATUS_SSP0 ,FIQ Status 5 (SSP0)" "No interrupt,Interrupt" bitfld.long 0x0 4. " FIQSTATUS_I2C1 ,FIQ Status 4 (I2C channel 1)" "No interrupt,Interrupt" textline " " bitfld.long 0x0 3. " FIQSTATUS_I2C0 ,FIQ Status (I2C channel 0)" "No interrupt,Interrupt" bitfld.long 0x0 2. " FIQSTATUS_UART2 ,FIQ Status (UART channel 2)" "No interrupt,Interrupt" textline " " bitfld.long 0x0 1. " FIQSTATUS_UART1 ,FIQ Status (UART channel 1)" "No interrupt,Interrupt" bitfld.long 0x0 0. " FIQSTATUS_UART0 ,FIQ Status (UART channel 0)" "No interrupt,Interrupt" rgroup.long 0x8++0x3 line.long 0x0 "VIC1_RINTSR,Raw Interrupt Status Register" bitfld.long 0x0 15. " RAWINTR_PFQ-BC ,Raw Interrupt Status 15 (Prefetch Queue and Branch)" "No interrupt,Interrupt" sif (cpuis("STR911*")||cpuis("STR912*")) bitfld.long 0x0 14. " RAWINTR_USBBR ,Raw Interrupt Status 14 (USB Bus Resume)" "No interrupt,Interrupt" endif textline " " bitfld.long 0x0 13. " RAWINTR_WIU3 ,Raw Interrupt Status 13 (P7.0 to P7.7)" "No interrupt,Interrupt" bitfld.long 0x0 12. " RAWINTR_WIU2 ,Raw Interrupt Status 12 (pins P6.0 to P6.7" "No interrupt,Interrupt" textline " " bitfld.long 0x0 11. " RAWINTR_WIU1 ,Raw Interrupt Status 11 (pins P5.0 to P5.7)" "No interrupt,Interrupt" bitfld.long 0x0 10. " RAWINTR_WIU0 ,Raw Interrupt Status 10 ( RTC or USB Resume or pins P3.2 to P3.7)" "No interrupt,Interrupt" textline " " bitfld.long 0x0 9. " RAWINTR_WIUALL ,Raw Interrupt Status 9 (All 32 inputs of Wake-Up unit)" "No interrupt,Interrupt" bitfld.long 0x0 8. " RAWINTR_RTC ,Raw Interrupt Status 8 (Alarm or Tamper or Periodic Timer)" "No interrupt,Interrupt" textline " " bitfld.long 0x0 7. " RAWINTR_SCU ,Raw Interrupt Status 7 (LVD early warning / Brownout)" "No interrupt,Interrupt" bitfld.long 0x0 6. " RAWINTR_SSP1 ,Raw Interrupt Status 6 (SSP1)" "No interrupt,Interrupt" textline " " bitfld.long 0x0 5. " RAWINTR_SSP0 ,Raw Interrupt Status 5 (SSP0)" "No interrupt,Interrupt" bitfld.long 0x0 4. " RAWINTR_I2C1 ,Raw Interrupt Status 4 (I2C channel 1)" "No interrupt,Interrupt" textline " " bitfld.long 0x0 3. " RAWINTR_I2C0 ,Raw Interrupt Status (I2C channel 0)" "No interrupt,Interrupt" bitfld.long 0x0 2. " RAWINTR_UART2 ,Raw Interrupt Status (UART channel 2)" "No interrupt,Interrupt" textline " " bitfld.long 0x0 1. " RAWINTR_UART1 ,Raw Interrupt Status (UART channel 1)" "No interrupt,Interrupt" bitfld.long 0x0 0. " RAWINTR_UART0 ,Raw Interrupt Status (UART channel 0)" "No interrupt,Interrupt" group.long 0xC++0x3 line.long 0x0 "VIC1_INTSR,Interrupt Select Register" bitfld.long 0x0 15. " INTSELECT_PFQ-BC ,Interrupt Selection 15 (Prefetch Queue and Branch)" "IRQ,FIQ" sif (cpuis("STR911*")||cpuis("STR912*")) bitfld.long 0x0 14. " INTSELECT_USBBR ,Interrupt Selection 14 (USB Bus Resume)" "IRQ,FIQ" endif textline " " bitfld.long 0x0 13. " INTSELECT_WIU3 ,Interrupt Selection 13 (P7.0 to P7.7)" "IRQ,FIQ" bitfld.long 0x0 12. " INTSELECT_WIU2 ,Interrupt Selection 12 (pins P6.0 to P6.7" "IRQ,FIQ" textline " " bitfld.long 0x0 11. " INTSELECT_WIU1 ,Interrupt Selection 11 (pins P5.0 to P5.7)" "IRQ,FIQ" bitfld.long 0x0 10. " INTSELECT_WIU0 ,Interrupt Selection 10 ( RTC or USB Resume or pins P3.2 to P3.7)" "IRQ,FIQ" textline " " bitfld.long 0x0 9. " INTSELECT_WIUALL ,Interrupt Selection 9 (All 32 inputs of Wake-Up unit)" "IRQ,FIQ" bitfld.long 0x0 8. " INTSELECT_RTC ,Interrupt Selection 8 (Alarm or Tamper or Periodic Timer)" "IRQ,FIQ" textline " " bitfld.long 0x0 7. " INTSELECT_SCU ,Interrupt Selection 7 (LVD early warning / Brownout)" "IRQ,FIQ" bitfld.long 0x0 6. " INTSELECT_SSP1 ,Interrupt Selection 6 (SSP1)" "IRQ,FIQ" textline " " bitfld.long 0x0 5. " INTSELECT_SSP0 ,Interrupt Selection 5 (SSP0)" "IRQ,FIQ" bitfld.long 0x0 4. " INTSELECT_I2C1 ,Interrupt Selection 4 (I2C channel 1)" "IRQ,FIQ" textline " " bitfld.long 0x0 3. " INTSELECT_I2C0 ,Interrupt Selection (I2C channel 0)" "IRQ,FIQ" bitfld.long 0x0 2. " INTSELECT_UART2 ,Interrupt Selection (UART channel 2)" "IRQ,FIQ" textline " " bitfld.long 0x0 1. " INTSELECT_UART1 ,Interrupt Selection (UART channel 1)" "IRQ,FIQ" bitfld.long 0x0 0. " INTSELECT_UART0 ,Interrupt Selection (UART channel 0)" "IRQ,FIQ" group.long 0x10++0x3 line.long 0x0 "VIC1_INTER,Interrupt Enable Register" setclrfld.long 0x0 15. 0x0 15. 0x4 15. " INTENABLE_PFQ-BC_set/clr ,Interrupt Enable 15 (Prefetch Queue and Branch)" "Disabled,Enabled" sif (cpuis("STR911*")||cpuis("STR912*")) setclrfld.long 0x0 14. 0x0 14. 0x4 14. " INTENABLE_USBBR_set/clr ,Interrupt Enable 14 (USB Bus Resume)" "Disabled,Enabled" endif textline " " setclrfld.long 0x0 13. 0x0 13. 0x4 13. " INTENABLE_WIU3_set/clr ,Interrupt Enable 13 (P7.0 to P7.7)" "Disabled,Enabled" setclrfld.long 0x0 12. 0x0 12. 0x4 12. " INTENABLE_WIU2_set/clr ,Interrupt Enable 12 (pins P6.0 to P6.7" "Disabled,Enabled" textline " " setclrfld.long 0x0 11. 0x0 11. 0x4 11. " INTENABLE_WIU1_set/clr ,Interrupt Enable 11 (pins P5.0 to P5.7)" "Disabled,Enabled" setclrfld.long 0x0 10. 0x0 10. 0x4 10. " INTENABLE_WIU0_set/clr ,Interrupt Enable 10 ( RTC or USB Resume or pins P3.2 to P3.7)" "Disabled,Enabled" textline " " setclrfld.long 0x0 9. 0x0 9. 0x4 9. " INTENABLE_WIUALL_set/clr ,Interrupt Enable 9 (All 32 inputs of Wake-Up unit)" "Disabled,Enabled" setclrfld.long 0x0 8. 0x0 8. 0x4 8. " INTENABLE_RTC_set/clr ,Interrupt Enable 8 (Alarm or Tamper or Periodic Timer)" "Disabled,Enabled" textline " " setclrfld.long 0x0 7. 0x0 7. 0x4 7. " INTENABLE_SCU_set/clr ,Interrupt Enable 7 (LVD early warning / Brownout)" "Disabled,Enabled" setclrfld.long 0x0 6. 0x0 6. 0x4 6. " INTENABLE_SSP1_set/clr ,Interrupt Enable 6 (SSP1)" "Disabled,Enabled" textline " " setclrfld.long 0x0 5. 0x0 5. 0x4 5. " INTENABLE_SSP0_set/clr ,Interrupt Enable 5 (SSP0)" "Disabled,Enabled" setclrfld.long 0x0 4. 0x0 4. 0x4 4. " INTENABLE_I2C1_set/clr ,Interrupt Enable 4 (I2C channel 1)" "Disabled,Enabled" textline " " setclrfld.long 0x0 3. 0x0 3. 0x4 3. " INTENABLE_I2C0_set/clr ,Interrupt Enable (I2C channel 0)" "Disabled,Enabled" setclrfld.long 0x0 2. 0x0 2. 0x4 2. " INTENABLE_UART2_set/clr ,Interrupt Enable (UART channel 2)" "Disabled,Enabled" textline " " setclrfld.long 0x0 1. 0x0 1. 0x4 1. " INTENABLE_UART1_set/clr ,Interrupt Enable (UART channel 1)" "Disabled,Enabled" setclrfld.long 0x0 0. 0x0 0. 0x4 0. " INTENABLE_UART0_set/clr ,Interrupt Enable (UART channel 0)" "Disabled,Enabled" group.long 0x18++0x3 line.long 0x0 "VIC1_SWINTR,Software Interrupt Register" setclrfld.long 0x0 15. 0x0 15. 0x4 15. " SOFTINT_PFQ-BC_set/clr ,Software Interrupt 15 (Prefetch Queue and Branch)" "No interrupt,Interrupt" sif (cpuis("STR911*")||cpuis("STR912*")) setclrfld.long 0x0 14. 0x0 14. 0x4 14. " SOFTINT_USBBR_set/clr ,Software Interrupt 14 (USB Bus Resume)" "No interrupt,Interrupt" endif textline " " setclrfld.long 0x0 13. 0x0 13. 0x4 13. " SOFTINT_WIU3_set/clr ,Software Interrupt 13 (P7.0 to P7.7)" "No interrupt,Interrupt" setclrfld.long 0x0 12. 0x0 12. 0x4 12. " SOFTINT_WIU2_set/clr ,Software Interrupt 12 (pins P6.0 to P6.7" "No interrupt,Interrupt" textline " " setclrfld.long 0x0 11. 0x0 11. 0x4 11. " SOFTINT_WIU1_set/clr ,Software Interrupt 11 (pins P5.0 to P5.7)" "No interrupt,Interrupt" setclrfld.long 0x0 10. 0x0 10. 0x4 10. " SOFTINT_WIU0_set/clr ,Software Interrupt 10 ( RTC or USB Resume or pins P3.2 to P3.7)" "No interrupt,Interrupt" textline " " setclrfld.long 0x0 9. 0x0 9. 0x4 9. " SOFTINT_WIUALL_set/clr ,Software Interrupt 9 (All 32 inputs of Wake-Up unit)" "No interrupt,Interrupt" setclrfld.long 0x0 8. 0x0 8. 0x4 8. " SOFTINT_RTC_set/clr ,Software Interrupt 8 (Alarm or Tamper or Periodic Timer)" "No interrupt,Interrupt" textline " " setclrfld.long 0x0 7. 0x0 7. 0x4 7. " SOFTINT_SCU_set/clr ,Software Interrupt 7 (LVD early warning / Brownout)" "No interrupt,Interrupt" setclrfld.long 0x0 6. 0x0 6. 0x4 6. " SOFTINT_SSP1_set/clr ,Software Interrupt 6 (SSP1)" "No interrupt,Interrupt" textline " " setclrfld.long 0x0 5. 0x0 5. 0x4 5. " SOFTINT_SSP0_set/clr ,Software Interrupt 5 (SSP0)" "No interrupt,Interrupt" setclrfld.long 0x0 4. 0x0 4. 0x4 4. " SOFTINT_I2C1_set/clr ,Software Interrupt 4 (I2C channel 1)" "No interrupt,Interrupt" textline " " setclrfld.long 0x0 3. 0x0 3. 0x4 3. " SOFTINT_I2C0_set/clr ,Software Interrupt (I2C channel 0)" "No interrupt,Interrupt" setclrfld.long 0x0 2. 0x0 2. 0x4 2. " SOFTINT_UART2_set/clr ,Software Interrupt (UART channel 2)" "No interrupt,Interrupt" textline " " setclrfld.long 0x0 1. 0x0 1. 0x4 1. " SOFTINT_UART1_set/clr ,Software Interrupt (UART channel 1)" "No interrupt,Interrupt" setclrfld.long 0x0 0. 0x0 0. 0x4 0. " SOFTINT_UART0_set/clr ,Software Interrupt (UART channel 0)" "No interrupt,Interrupt" group.long 0x20++0x3 line.long 0x0 "VIC1_PER,Protection Enable Register" bitfld.long 0x0 0. " PROT ,Protection" "Not protected,Protected" width 0xC tree "Vector Registers" hgroup.long 0x30++0x3 hide.long 0x0 "VIC1_VAR,Current Vector Address Register" in group.long 0x34++0x3 line.long 0x0 "VIC1_DVAR,Default Vector Address Register" group.long 0x100++0x3 line.long 0x0 "VIC1_VA0R,Vector Address 0 Register" group.long 0x104++0x3 line.long 0x0 "VIC1_VA1R,Vector Address 1 Register" group.long 0x108++0x3 line.long 0x0 "VIC1_VA2R,Vector Address 2 Register" group.long 0x10C++0x3 line.long 0x0 "VIC1_VA3R,Vector Address 3 Register" group.long 0x110++0x3 line.long 0x0 "VIC1_VA4R,Vector Address 4 Register" group.long 0x114++0x3 line.long 0x0 "VIC1_VA5R,Vector Address 5 Register" group.long 0x118++0x3 line.long 0x0 "VIC1_VA6R,Vector Address 6 Register" group.long 0x11C++0x3 line.long 0x0 "VIC1_VA7R,Vector Address 7 Register" group.long 0x120++0x3 line.long 0x0 "VIC1_VA8R,Vector Address 8 Register" group.long 0x124++0x3 line.long 0x0 "VIC1_VA9R,Vector Address 9 Register" group.long 0x128++0x3 line.long 0x0 "VIC1_VA10R,Vector Address 10 Register" group.long 0x12C++0x3 line.long 0x0 "VIC1_VA11R,Vector Address 11 Register" group.long 0x130++0x3 line.long 0x0 "VIC1_VA12R,Vector Address 12 Register" group.long 0x134++0x3 line.long 0x0 "VIC1_VA13R,Vector Address 13 Register" group.long 0x138++0x3 line.long 0x0 "VIC1_VA14R,Vector Address 14 Register" group.long 0x13C++0x3 line.long 0x0 "VIC1_VA15R,Vector Address 15 Register" group.long 0x200++0x3 line.long 0x0 "VIC1_VC0R,Vector Control 0 Register" bitfld.long 0x0 5. " E0 ,Vector Interrupt 0 Enable" "Disabled,Enabled" bitfld.long 0x0 0.--4. " VectorCntl0[4:0] ,Vector Control 0" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 8,Source 9,Source 10,Source 11,Source 12,Source 13,Source 14,Source 15,?..." group.long 0x204++0x3 line.long 0x0 "VIC1_VC1R,Vector Control 1 Register" bitfld.long 0x0 5. " E1 ,Vector Interrupt 1 Enable" "Disabled,Enabled" bitfld.long 0x0 0.--4. " VectorCntl1[4:0] ,Vector Control 1" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 8,Source 9,Source 10,Source 11,Source 12,Source 13,Source 14,Source 15,?..." group.long 0x208++0x3 line.long 0x0 "VIC1_VC2R,Vector Control 2 Register" bitfld.long 0x0 5. " E2 ,Vector Interrupt 2 Enable" "Disabled,Enabled" bitfld.long 0x0 0.--4. " VectorCntl2[4:0] ,Vector Control 2" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 8,Source 9,Source 10,Source 11,Source 12,Source 13,Source 14,Source 15,?..." group.long 0x20C++0x3 line.long 0x0 "VIC1_VC3R,Vector Control 3 Register" bitfld.long 0x0 5. " E3 ,Vector Interrupt 3 Enable" "Disabled,Enabled" bitfld.long 0x0 0.--4. " VectorCntl3[4:0] ,Vector Control 3" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 8,Source 9,Source 10,Source 11,Source 12,Source 13,Source 14,Source 15,?..." group.long 0x210++0x3 line.long 0x0 "VIC1_VC4R,Vector Control 4 Register" bitfld.long 0x0 5. " E4 ,Vector Interrupt 4 Enable" "Disabled,Enabled" bitfld.long 0x0 0.--4. " VectorCntl4[4:0] ,Vector Control 4" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 8,Source 9,Source 10,Source 11,Source 12,Source 13,Source 14,Source 15,?..." group.long 0x214++0x3 line.long 0x0 "VIC1_VC5R,Vector Control 5 Register" bitfld.long 0x0 5. " E5 ,Vector Interrupt 5 Enable" "Disabled,Enabled" bitfld.long 0x0 0.--4. " VectorCntl5[4:0] ,Vector Control 5" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 8,Source 9,Source 10,Source 11,Source 12,Source 13,Source 14,Source 15,?..." group.long 0x218++0x3 line.long 0x0 "VIC1_VC6R,Vector Control 6 Register" bitfld.long 0x0 5. " E6 ,Vector Interrupt 6 Enable" "Disabled,Enabled" bitfld.long 0x0 0.--4. " VectorCntl6[4:0] ,Vector Control 6" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 8,Source 9,Source 10,Source 11,Source 12,Source 13,Source 14,Source 15,?..." group.long 0x21C++0x3 line.long 0x0 "VIC1_VC7R,Vector Control 7 Register" bitfld.long 0x0 5. " E7 ,Vector Interrupt 7 Enable" "Disabled,Enabled" bitfld.long 0x0 0.--4. " VectorCntl7[4:0] ,Vector Control 7" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 8,Source 9,Source 10,Source 11,Source 12,Source 13,Source 14,Source 15,?..." group.long 0x220++0x3 line.long 0x0 "VIC1_VC8R,Vector Control 8 Register" bitfld.long 0x0 5. " E8 ,Vector Interrupt 8 Enable" "Disabled,Enabled" bitfld.long 0x0 0.--4. " VectorCntl8[4:0] ,Vector Control 8" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 8,Source 9,Source 10,Source 11,Source 12,Source 13,Source 14,Source 15,?..." group.long 0x224++0x3 line.long 0x0 "VIC1_VC9R,Vector Control 9 Register" bitfld.long 0x0 5. " E9 ,Vector Interrupt 9 Enable" "Disabled,Enabled" bitfld.long 0x0 0.--4. " VectorCntl9[4:0] ,Vector Control 9" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 8,Source 9,Source 10,Source 11,Source 12,Source 13,Source 14,Source 15,?..." group.long 0x228++0x3 line.long 0x0 "VIC1_VC10R,Vector Control 10 Register" bitfld.long 0x0 5. " E10 ,Vector Interrupt 10 Enable" "Disabled,Enabled" bitfld.long 0x0 0.--4. " VectorCntl10[4:0] ,Vector Control 10" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 8,Source 9,Source 10,Source 11,Source 12,Source 13,Source 14,Source 15,?..." group.long 0x22C++0x3 line.long 0x0 "VIC1_VC11R,Vector Control 11 Register" bitfld.long 0x0 5. " E11 ,Vector Interrupt 11 Enable" "Disabled,Enabled" bitfld.long 0x0 0.--4. " VectorCntl11[4:0] ,Vector Control 11" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 8,Source 9,Source 10,Source 11,Source 12,Source 13,Source 14,Source 15,?..." group.long 0x230++0x3 line.long 0x0 "VIC1_VC12R,Vector Control 12 Register" bitfld.long 0x0 5. " E12 ,Vector Interrupt 12 Enable" "Disabled,Enabled" bitfld.long 0x0 0.--4. " VectorCntl12[4:0] ,Vector Control 12" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 8,Source 9,Source 10,Source 11,Source 12,Source 13,Source 14,Source 15,?..." group.long 0x234++0x3 line.long 0x0 "VIC1_VC13R,Vector Control 13 Register" bitfld.long 0x0 5. " E13 ,Vector Interrupt 13 Enable" "Disabled,Enabled" bitfld.long 0x0 0.--4. " VectorCntl13[4:0] ,Vector Control 13" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 8,Source 9,Source 10,Source 11,Source 12,Source 13,Source 14,Source 15,?..." group.long 0x238++0x3 line.long 0x0 "VIC1_VC14R,Vector Control 14 Register" bitfld.long 0x0 5. " E14 ,Vector Interrupt 14 Enable" "Disabled,Enabled" bitfld.long 0x0 0.--4. " VectorCntl14[4:0] ,Vector Control 14" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 8,Source 9,Source 10,Source 11,Source 12,Source 13,Source 14,Source 15,?..." group.long 0x23C++0x3 line.long 0x0 "VIC1_VC15R,Vector Control 15 Register" bitfld.long 0x0 5. " E15 ,Vector Interrupt 15 Enable" "Disabled,Enabled" bitfld.long 0x0 0.--4. " VectorCntl15[4:0] ,Vector Control 15" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 8,Source 9,Source 10,Source 11,Source 12,Source 13,Source 14,Source 15,?..." tree.end tree.end else width 20. base asd:0xFFFFF000 tree "VIC0 (Vectored Interrupt Controller 0)" rgroup.long 0x0++0x3 line.long 0x0 "VIC0_ISR,IRQ Status Register" bitfld.long 0x0 15. " IRQStatus15 ,IRQ Status 15" "No interrupt,Interrupt" bitfld.long 0x0 14. " IRQStatus14 ,IRQ Status 14" "No interrupt,Interrupt" textline " " bitfld.long 0x0 13. " IRQStatus13 ,IRQ Status 13" "No interrupt,Interrupt" bitfld.long 0x0 12. " IRQStatus12 ,IRQ Status 12" "No interrupt,Interrupt" textline " " bitfld.long 0x0 11. " IRQStatus11 ,IRQ Status 11" "No interrupt,Interrupt" bitfld.long 0x0 10. " IRQStatus10 ,IRQ Status 10" "No interrupt,Interrupt" textline " " bitfld.long 0x0 9. " IRQStatus9 ,IRQ Status 9" "No interrupt,Interrupt" bitfld.long 0x0 8. " IRQStatus8 ,IRQ Status 8" "No interrupt,Interrupt" textline " " bitfld.long 0x0 7. " IRQStatus7 ,IRQ Status 7" "No interrupt,Interrupt" bitfld.long 0x0 6. " IRQStatus6 ,IRQ Status 6" "No interrupt,Interrupt" textline " " bitfld.long 0x0 5. " IRQStatus5 ,IRQ Status 5" "No interrupt,Interrupt" bitfld.long 0x0 4. " IRQStatus4 ,IRQ Status 4" "No interrupt,Interrupt" textline " " bitfld.long 0x0 3. " IRQStatus3 ,IRQ Status 3" "No interrupt,Interrupt" bitfld.long 0x0 2. " IRQStatus2 ,IRQ Status 2" "No interrupt,Interrupt" textline " " bitfld.long 0x0 1. " IRQStatus1 ,IRQ Status 1" "No interrupt,Interrupt" bitfld.long 0x0 0. " IRQStatus0 ,IRQ Status 0" "No interrupt,Interrupt" rgroup.long 0x4++0x3 line.long 0x0 "VIC0_FSR,FIQ Status Register" bitfld.long 0x0 15. " FIQStatus15 ,FIQ Status 15" "No interrupt,Interrupt" bitfld.long 0x0 14. " FIQStatus14 ,FIQ Status 14" "No interrupt,Interrupt" textline " " bitfld.long 0x0 13. " FIQStatus13 ,FIQ Status 13" "No interrupt,Interrupt" bitfld.long 0x0 12. " FIQStatus12 ,FIQ Status 12" "No interrupt,Interrupt" textline " " bitfld.long 0x0 11. " FIQStatus11 ,FIQ Status 11" "No interrupt,Interrupt" bitfld.long 0x0 10. " FIQStatus10 ,FIQ Status 10" "No interrupt,Interrupt" textline " " bitfld.long 0x0 9. " FIQStatus9 ,FIQ Status 9" "No interrupt,Interrupt" bitfld.long 0x0 8. " FIQStatus8 ,FIQ Status 8" "No interrupt,Interrupt" textline " " bitfld.long 0x0 7. " FIQStatus7 ,FIQ Status 7" "No interrupt,Interrupt" bitfld.long 0x0 6. " FIQStatus6 ,FIQ Status 6" "No interrupt,Interrupt" textline " " bitfld.long 0x0 5. " FIQStatus5 ,FIQ Status 5" "No interrupt,Interrupt" bitfld.long 0x0 4. " FIQStatus4 ,FIQ Status 4" "No interrupt,Interrupt" textline " " bitfld.long 0x0 3. " FIQStatus3 ,FIQ Status 3" "No interrupt,Interrupt" bitfld.long 0x0 2. " FIQStatus2 ,FIQ Status 2" "No interrupt,Interrupt" textline " " bitfld.long 0x0 1. " FIQStatus1 ,FIQ Status 1" "No interrupt,Interrupt" bitfld.long 0x0 0. " FIQStatus0 ,FIQ Status 0" "No interrupt,Interrupt" rgroup.long 0x8++0x3 line.long 0x0 "VIC0_RINTSR,Raw Interrupt Status Register" bitfld.long 0x0 15. " RawIntr15 ,Raw Interrupt Status 15" "Inactivated,Activated" bitfld.long 0x0 14. " RawIntr14 ,Raw Interrupt Status 14" "Inactivated,Activated" textline " " bitfld.long 0x0 13. " RawIntr13 ,Raw Interrupt Status 13" "Inactivated,Activated" bitfld.long 0x0 12. " RawIntr12 ,Raw Interrupt Status 12" "Inactivated,Activated" textline " " bitfld.long 0x0 11. " RawIntr11 ,Raw Interrupt Status 11" "Inactivated,Activated" bitfld.long 0x0 10. " RawIntr10 ,Raw Interrupt Status 10" "Inactivated,Activated" textline " " bitfld.long 0x0 9. " RawIntr9 ,Raw Interrupt Status 9" "Inactivated,Activated" bitfld.long 0x0 8. " RawIntr8 ,Raw Interrupt Status 8" "Inactivated,Activated" textline " " bitfld.long 0x0 7. " RawIntr7 ,Raw Interrupt Status 7" "Inactivated,Activated" bitfld.long 0x0 6. " RawIntr6 ,Raw Interrupt Status 6" "Inactivated,Activated" textline " " bitfld.long 0x0 5. " RawIntr5 ,Raw Interrupt Status 5" "Inactivated,Activated" bitfld.long 0x0 4. " RawIntr4 ,Raw Interrupt Status 4" "Inactivated,Activated" textline " " bitfld.long 0x0 3. " RawIntr3 ,Raw Interrupt Status 3" "Inactivated,Activated" bitfld.long 0x0 2. " RawIntr2 ,Raw Interrupt Status 2" "Inactivated,Activated" textline " " bitfld.long 0x0 1. " RawIntr1 ,Raw Interrupt Status 1" "Inactivated,Activated" bitfld.long 0x0 0. " RawIntr0 ,Raw Interrupt Status 0" "Inactivated,Activated" group.long 0xC++0x3 line.long 0x0 "VIC0_INTSR,Interrupt Select Register" bitfld.long 0x0 15. " IntSelect15 ,Interrupt Selection 15" "IRQ,FIQ" bitfld.long 0x0 14. " IntSelect14 ,Interrupt Selection 14" "IRQ,FIQ" textline " " bitfld.long 0x0 13. " IntSelect13 ,Interrupt Selection 13" "IRQ,FIQ" bitfld.long 0x0 12. " IntSelect12 ,Interrupt Selection 12" "IRQ,FIQ" textline " " bitfld.long 0x0 11. " IntSelect11 ,Interrupt Selection 11" "IRQ,FIQ" bitfld.long 0x0 10. " IntSelect10 ,Interrupt Selection 10" "IRQ,FIQ" textline " " bitfld.long 0x0 9. " IntSelect9 ,Interrupt Selection 9" "IRQ,FIQ" bitfld.long 0x0 8. " IntSelect8 ,Interrupt Selection 8" "IRQ,FIQ" textline " " bitfld.long 0x0 7. " IntSelect7 ,Interrupt Selection 7" "IRQ,FIQ" bitfld.long 0x0 6. " IntSelect6 ,Interrupt Selection 6" "IRQ,FIQ" textline " " bitfld.long 0x0 5. " IntSelect5 ,Interrupt Selection 5" "IRQ,FIQ" bitfld.long 0x0 4. " IntSelect4 ,Interrupt Selection 4" "IRQ,FIQ" textline " " bitfld.long 0x0 3. " IntSelect3 ,Interrupt Selection 3" "IRQ,FIQ" bitfld.long 0x0 2. " IntSelect2 ,Interrupt Selection 2" "IRQ,FIQ" textline " " bitfld.long 0x0 1. " IntSelect1 ,Interrupt Selection 1" "IRQ,FIQ" bitfld.long 0x0 0. " IntSelect0 ,Interrupt Selection 0" "IRQ,FIQ" group.long 0x10++0x3 line.long 0x0 "VIC0_INTER/INTECR,Interrupt Enable Register" setclrfld.long 0x0 15. 0x0 15. 0x4 15. " IntEnable15_Clear/Set ,Interrupt Enable 15" "Disabled,Enabled" setclrfld.long 0x0 14. 0x0 14. 0x4 14. " IntEnable14_Clear/Set ,Interrupt Enable 14" "Disabled,Enabled" textline " " setclrfld.long 0x0 13. 0x0 13. 0x4 13. " IntEnable13_Clear/Set ,Interrupt Enable 13" "Disabled,Enabled" setclrfld.long 0x0 12. 0x0 12. 0x4 12. " IntEnable12_Clear/Set ,Interrupt Enable 12" "Disabled,Enabled" textline " " setclrfld.long 0x0 11. 0x0 11. 0x4 11. " IntEnable11_Clear/Set ,Interrupt Enable 11" "Disabled,Enabled" setclrfld.long 0x0 10. 0x0 10. 0x4 10. " IntEnable10_Clear/Set ,Interrupt Enable 10" "Disabled,Enabled" textline " " setclrfld.long 0x0 9. 0x0 9. 0x4 9. " IntEnable9_Clear/Set ,Interrupt Enable 9" "Disabled,Enabled" setclrfld.long 0x0 8. 0x0 8. 0x4 8. " IntEnable8_Clear/Set ,Interrupt Enable 8" "Disabled,Enabled" textline " " setclrfld.long 0x0 7. 0x0 7. 0x4 7. " IntEnable7_Clear/Set ,Interrupt Enable 7" "Disabled,Enabled" setclrfld.long 0x0 6. 0x0 6. 0x4 6. " IntEnable6_Clear/Set ,Interrupt Enable 6" "Disabled,Enabled" textline " " setclrfld.long 0x0 5. 0x0 5. 0x4 5. " IntEnable5_Clear/Set ,Interrupt Enable 5" "Disabled,Enabled" setclrfld.long 0x0 4. 0x0 4. 0x4 4. " IntEnable4_Clear/Set ,Interrupt Enable 4" "Disabled,Enabled" textline " " setclrfld.long 0x0 3. 0x0 3. 0x4 3. " IntEnable3_Clear/Set ,Interrupt Enable 3" "Disabled,Enabled" setclrfld.long 0x0 2. 0x0 2. 0x4 2. " IntEnable2_Clear/Set ,Interrupt Enable 2" "Disabled,Enabled" textline " " setclrfld.long 0x0 1. 0x0 1. 0x4 1. " IntEnable1_Clear/Set ,Interrupt Enable 1" "Disabled,Enabled" setclrfld.long 0x0 0. 0x0 0. 0x4 0. " IntEnable0_Clear/Set ,Interrupt Enable 0" "Disabled,Enabled" group.long 0x18++0x3 line.long 0x0 "VIC0_SWINTR,Software Interrupt Register" setclrfld.long 0x0 15. 0x0 15. 0x4 15. " SoftInt15_Clear/Set ,Software Interrupt 15" "Not activated,Activated" setclrfld.long 0x0 14. 0x0 14. 0x4 14. " SoftInt14_Clear/Set ,Software Interrupt 14" "Not activated,Activated" textline " " setclrfld.long 0x0 13. 0x0 13. 0x4 13. " SoftInt13_Clear/Set ,Software Interrupt 13" "Not activated,Activated" setclrfld.long 0x0 12. 0x0 12. 0x4 12. " SoftInt12_Clear/Set ,Software Interrupt 12" "Not activated,Activated" textline " " setclrfld.long 0x0 11. 0x0 11. 0x4 11. " SoftInt11_Clear/Set ,Software Interrupt 11" "Not activated,Activated" setclrfld.long 0x0 10. 0x0 10. 0x4 10. " SoftInt10_Clear/Set ,Software Interrupt 10" "Not activated,Activated" textline " " setclrfld.long 0x0 9. 0x0 9. 0x4 9. " SoftInt9_Clear/Set ,Software Interrupt 9" "Not activated,Activated" setclrfld.long 0x0 8. 0x0 8. 0x4 8. " SoftInt8_Clear/Set ,Software Interrupt 8" "Not activated,Activated" textline " " setclrfld.long 0x0 7. 0x0 7. 0x4 7. " SoftInt7_Clear/Set ,Software Interrupt 7" "Not activated,Activated" setclrfld.long 0x0 6. 0x0 6. 0x4 6. " SoftInt6_Clear/Set ,Software Interrupt 6" "Not activated,Activated" textline " " setclrfld.long 0x0 5. 0x0 5. 0x4 5. " SoftInt5_Clear/Set ,Software Interrupt 5" "Not activated,Activated" setclrfld.long 0x0 4. 0x0 4. 0x4 4. " SoftInt4_Clear/Set ,Software Interrupt 4" "Not activated,Activated" textline " " setclrfld.long 0x0 3. 0x0 3. 0x4 3. " SoftInt3_Clear/Set ,Software Interrupt 3" "Not activated,Activated" setclrfld.long 0x0 2. 0x0 2. 0x4 2. " SoftInt2_Clear/Set ,Software Interrupt 2" "Not activated,Activated" textline " " setclrfld.long 0x0 1. 0x0 1. 0x4 1. " SoftInt1_Clear/Set ,Software Interrupt 1" "Not activated,Activated" setclrfld.long 0x0 0. 0x0 0. 0x4 0. " SoftInt0_Clear/Set ,Software Interrupt 0" "Not activated,Activated" group.long 0x20++0x3 line.long 0x0 "VIC0_PER,Protection Enable Register" bitfld.long 0x0 0. " PROT ,Protection" "Not protected,Protected" width 0xC tree "Vector Registers" hgroup.long 0x30++0x3 hide.long 0x0 "VIC0_VAR,Current Vector Address Register" in group.long 0x34++0x3 line.long 0x0 "VIC0_DVAR,Default Vector Address Register" group.long 0x100++0x3 line.long 0x0 "VIC0_VA0R,Vector Address 0 Register" group.long 0x104++0x3 line.long 0x0 "VIC0_VA1R,Vector Address 1 Register" group.long 0x108++0x3 line.long 0x0 "VIC0_VA2R,Vector Address 2 Register" group.long 0x10C++0x3 line.long 0x0 "VIC0_VA3R,Vector Address 3 Register" group.long 0x110++0x3 line.long 0x0 "VIC0_VA4R,Vector Address 4 Register" group.long 0x114++0x3 line.long 0x0 "VIC0_VA5R,Vector Address 5 Register" group.long 0x118++0x3 line.long 0x0 "VIC0_VA6R,Vector Address 6 Register" group.long 0x11C++0x3 line.long 0x0 "VIC0_VA7R,Vector Address 7 Register" group.long 0x120++0x3 line.long 0x0 "VIC0_VA8R,Vector Address 8 Register" group.long 0x124++0x3 line.long 0x0 "VIC0_VA9R,Vector Address 9 Register" group.long 0x128++0x3 line.long 0x0 "VIC0_VA10R,Vector Address 10 Register" group.long 0x12C++0x3 line.long 0x0 "VIC0_VA11R,Vector Address 11 Register" group.long 0x130++0x3 line.long 0x0 "VIC0_VA12R,Vector Address 12 Register" group.long 0x134++0x3 line.long 0x0 "VIC0_VA13R,Vector Address 13 Register" group.long 0x138++0x3 line.long 0x0 "VIC0_VA14R,Vector Address 14 Register" group.long 0x13C++0x3 line.long 0x0 "VIC0_VA15R,Vector Address 15 Register" group.long 0x200++0x3 line.long 0x0 "VIC0_VC0R,Vector Control 0 Register" bitfld.long 0x0 5. " E0 ,Vector Interrupt 0 Enable" "Disabled,Enabled" bitfld.long 0x0 0.--4. " VectorCntl0[4:0] ,Vector Control 0" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 8,Source 9,Source 10,Source 11,Source 12,Source 13,Source 14,Source 15,?..." group.long 0x204++0x3 line.long 0x0 "VIC0_VC1R,Vector Control 1 Register" bitfld.long 0x0 5. " E1 ,Vector Interrupt 1 Enable" "Disabled,Enabled" bitfld.long 0x0 0.--4. " VectorCntl1[4:0] ,Vector Control 1" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 8,Source 9,Source 10,Source 11,Source 12,Source 13,Source 14,Source 15,?..." group.long 0x208++0x3 line.long 0x0 "VIC0_VC2R,Vector Control 2 Register" bitfld.long 0x0 5. " E2 ,Vector Interrupt 2 Enable" "Disabled,Enabled" bitfld.long 0x0 0.--4. " VectorCntl2[4:0] ,Vector Control 2" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 8,Source 9,Source 10,Source 11,Source 12,Source 13,Source 14,Source 15,?..." group.long 0x20C++0x3 line.long 0x0 "VIC0_VC3R,Vector Control 3 Register" bitfld.long 0x0 5. " E3 ,Vector Interrupt 3 Enable" "Disabled,Enabled" bitfld.long 0x0 0.--4. " VectorCntl3[4:0] ,Vector Control 3" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 8,Source 9,Source 10,Source 11,Source 12,Source 13,Source 14,Source 15,?..." group.long 0x210++0x3 line.long 0x0 "VIC0_VC4R,Vector Control 4 Register" bitfld.long 0x0 5. " E4 ,Vector Interrupt 4 Enable" "Disabled,Enabled" bitfld.long 0x0 0.--4. " VectorCntl4[4:0] ,Vector Control 4" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 8,Source 9,Source 10,Source 11,Source 12,Source 13,Source 14,Source 15,?..." group.long 0x214++0x3 line.long 0x0 "VIC0_VC5R,Vector Control 5 Register" bitfld.long 0x0 5. " E5 ,Vector Interrupt 5 Enable" "Disabled,Enabled" bitfld.long 0x0 0.--4. " VectorCntl5[4:0] ,Vector Control 5" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 8,Source 9,Source 10,Source 11,Source 12,Source 13,Source 14,Source 15,?..." group.long 0x218++0x3 line.long 0x0 "VIC0_VC6R,Vector Control 6 Register" bitfld.long 0x0 5. " E6 ,Vector Interrupt 6 Enable" "Disabled,Enabled" bitfld.long 0x0 0.--4. " VectorCntl6[4:0] ,Vector Control 6" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 8,Source 9,Source 10,Source 11,Source 12,Source 13,Source 14,Source 15,?..." group.long 0x21C++0x3 line.long 0x0 "VIC0_VC7R,Vector Control 7 Register" bitfld.long 0x0 5. " E7 ,Vector Interrupt 7 Enable" "Disabled,Enabled" bitfld.long 0x0 0.--4. " VectorCntl7[4:0] ,Vector Control 7" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 8,Source 9,Source 10,Source 11,Source 12,Source 13,Source 14,Source 15,?..." group.long 0x220++0x3 line.long 0x0 "VIC0_VC8R,Vector Control 8 Register" bitfld.long 0x0 5. " E8 ,Vector Interrupt 8 Enable" "Disabled,Enabled" bitfld.long 0x0 0.--4. " VectorCntl8[4:0] ,Vector Control 8" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 8,Source 9,Source 10,Source 11,Source 12,Source 13,Source 14,Source 15,?..." group.long 0x224++0x3 line.long 0x0 "VIC0_VC9R,Vector Control 9 Register" bitfld.long 0x0 5. " E9 ,Vector Interrupt 9 Enable" "Disabled,Enabled" bitfld.long 0x0 0.--4. " VectorCntl9[4:0] ,Vector Control 9" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 8,Source 9,Source 10,Source 11,Source 12,Source 13,Source 14,Source 15,?..." group.long 0x228++0x3 line.long 0x0 "VIC0_VC10R,Vector Control 10 Register" bitfld.long 0x0 5. " E10 ,Vector Interrupt 10 Enable" "Disabled,Enabled" bitfld.long 0x0 0.--4. " VectorCntl10[4:0] ,Vector Control 10" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 8,Source 9,Source 10,Source 11,Source 12,Source 13,Source 14,Source 15,?..." group.long 0x22C++0x3 line.long 0x0 "VIC0_VC11R,Vector Control 11 Register" bitfld.long 0x0 5. " E11 ,Vector Interrupt 11 Enable" "Disabled,Enabled" bitfld.long 0x0 0.--4. " VectorCntl11[4:0] ,Vector Control 11" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 8,Source 9,Source 10,Source 11,Source 12,Source 13,Source 14,Source 15,?..." group.long 0x230++0x3 line.long 0x0 "VIC0_VC12R,Vector Control 12 Register" bitfld.long 0x0 5. " E12 ,Vector Interrupt 12 Enable" "Disabled,Enabled" bitfld.long 0x0 0.--4. " VectorCntl12[4:0] ,Vector Control 12" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 8,Source 9,Source 10,Source 11,Source 12,Source 13,Source 14,Source 15,?..." group.long 0x234++0x3 line.long 0x0 "VIC0_VC13R,Vector Control 13 Register" bitfld.long 0x0 5. " E13 ,Vector Interrupt 13 Enable" "Disabled,Enabled" bitfld.long 0x0 0.--4. " VectorCntl13[4:0] ,Vector Control 13" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 8,Source 9,Source 10,Source 11,Source 12,Source 13,Source 14,Source 15,?..." group.long 0x238++0x3 line.long 0x0 "VIC0_VC14R,Vector Control 14 Register" bitfld.long 0x0 5. " E14 ,Vector Interrupt 14 Enable" "Disabled,Enabled" bitfld.long 0x0 0.--4. " VectorCntl14[4:0] ,Vector Control 14" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 8,Source 9,Source 10,Source 11,Source 12,Source 13,Source 14,Source 15,?..." group.long 0x23C++0x3 line.long 0x0 "VIC0_VC15R,Vector Control 15 Register" bitfld.long 0x0 5. " E15 ,Vector Interrupt 15 Enable" "Disabled,Enabled" bitfld.long 0x0 0.--4. " VectorCntl15[4:0] ,Vector Control 15" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 8,Source 9,Source 10,Source 11,Source 12,Source 13,Source 14,Source 15,?..." tree.end tree.end base asd:0xFC000000 width 20. tree "VIC1 (Vectored Interrupt Controller 1)" rgroup.long 0x0++0x3 line.long 0x0 "VIC1_ISR,IRQ Status Register" bitfld.long 0x0 15. " IRQStatus15 ,IRQ Status 15" "No interrupt,Interrupt" bitfld.long 0x0 14. " IRQStatus14 ,IRQ Status 14" "No interrupt,Interrupt" textline " " bitfld.long 0x0 13. " IRQStatus13 ,IRQ Status 13" "No interrupt,Interrupt" bitfld.long 0x0 12. " IRQStatus12 ,IRQ Status 12" "No interrupt,Interrupt" textline " " bitfld.long 0x0 11. " IRQStatus11 ,IRQ Status 11" "No interrupt,Interrupt" bitfld.long 0x0 10. " IRQStatus10 ,IRQ Status 10" "No interrupt,Interrupt" textline " " bitfld.long 0x0 9. " IRQStatus9 ,IRQ Status 9" "No interrupt,Interrupt" bitfld.long 0x0 8. " IRQStatus8 ,IRQ Status 8" "No interrupt,Interrupt" textline " " bitfld.long 0x0 7. " IRQStatus7 ,IRQ Status 7" "No interrupt,Interrupt" bitfld.long 0x0 6. " IRQStatus6 ,IRQ Status 6" "No interrupt,Interrupt" textline " " bitfld.long 0x0 5. " IRQStatus5 ,IRQ Status 5" "No interrupt,Interrupt" bitfld.long 0x0 4. " IRQStatus4 ,IRQ Status 4" "No interrupt,Interrupt" textline " " bitfld.long 0x0 3. " IRQStatus3 ,IRQ Status 3" "No interrupt,Interrupt" bitfld.long 0x0 2. " IRQStatus2 ,IRQ Status 2" "No interrupt,Interrupt" textline " " bitfld.long 0x0 1. " IRQStatus1 ,IRQ Status 1" "No interrupt,Interrupt" bitfld.long 0x0 0. " IRQStatus0 ,IRQ Status 0" "No interrupt,Interrupt" rgroup.long 0x4++0x3 line.long 0x0 "VIC1_FSR,FIQ Status Register" bitfld.long 0x0 15. " FIQStatus15 ,FIQ Status 15" "No interrupt,Interrupt" bitfld.long 0x0 14. " FIQStatus14 ,FIQ Status 14" "No interrupt,Interrupt" textline " " bitfld.long 0x0 13. " FIQStatus13 ,FIQ Status 13" "No interrupt,Interrupt" bitfld.long 0x0 12. " FIQStatus12 ,FIQ Status 12" "No interrupt,Interrupt" textline " " bitfld.long 0x0 11. " FIQStatus11 ,FIQ Status 11" "No interrupt,Interrupt" bitfld.long 0x0 10. " FIQStatus10 ,FIQ Status 10" "No interrupt,Interrupt" textline " " bitfld.long 0x0 9. " FIQStatus9 ,FIQ Status 9" "No interrupt,Interrupt" bitfld.long 0x0 8. " FIQStatus8 ,FIQ Status 8" "No interrupt,Interrupt" textline " " bitfld.long 0x0 7. " FIQStatus7 ,FIQ Status 7" "No interrupt,Interrupt" bitfld.long 0x0 6. " FIQStatus6 ,FIQ Status 6" "No interrupt,Interrupt" textline " " bitfld.long 0x0 5. " FIQStatus5 ,FIQ Status 5" "No interrupt,Interrupt" bitfld.long 0x0 4. " FIQStatus4 ,FIQ Status 4" "No interrupt,Interrupt" textline " " bitfld.long 0x0 3. " FIQStatus3 ,FIQ Status 3" "No interrupt,Interrupt" bitfld.long 0x0 2. " FIQStatus2 ,FIQ Status 2" "No interrupt,Interrupt" textline " " bitfld.long 0x0 1. " FIQStatus1 ,FIQ Status 1" "No interrupt,Interrupt" bitfld.long 0x0 0. " FIQStatus0 ,FIQ Status 0" "No interrupt,Interrupt" rgroup.long 0x8++0x3 line.long 0x0 "VIC1_RINTSR,Raw Interrupt Status Register" bitfld.long 0x0 15. " RawIntr15 ,Raw Interrupt Status 15" "Inactivated,Activated" bitfld.long 0x0 14. " RawIntr14 ,Raw Interrupt Status 14" "Inactivated,Activated" textline " " bitfld.long 0x0 13. " RawIntr13 ,Raw Interrupt Status 13" "Inactivated,Activated" bitfld.long 0x0 12. " RawIntr12 ,Raw Interrupt Status 12" "Inactivated,Activated" textline " " bitfld.long 0x0 11. " RawIntr11 ,Raw Interrupt Status 11" "Inactivated,Activated" bitfld.long 0x0 10. " RawIntr10 ,Raw Interrupt Status 10" "Inactivated,Activated" textline " " bitfld.long 0x0 9. " RawIntr9 ,Raw Interrupt Status 9" "Inactivated,Activated" bitfld.long 0x0 8. " RawIntr8 ,Raw Interrupt Status 8" "Inactivated,Activated" textline " " bitfld.long 0x0 7. " RawIntr7 ,Raw Interrupt Status 7" "Inactivated,Activated" bitfld.long 0x0 6. " RawIntr6 ,Raw Interrupt Status 6" "Inactivated,Activated" textline " " bitfld.long 0x0 5. " RawIntr5 ,Raw Interrupt Status 5" "Inactivated,Activated" bitfld.long 0x0 4. " RawIntr4 ,Raw Interrupt Status 4" "Inactivated,Activated" textline " " bitfld.long 0x0 3. " RawIntr3 ,Raw Interrupt Status 3" "Inactivated,Activated" bitfld.long 0x0 2. " RawIntr2 ,Raw Interrupt Status 2" "Inactivated,Activated" textline " " bitfld.long 0x0 1. " RawIntr1 ,Raw Interrupt Status 1" "Inactivated,Activated" bitfld.long 0x0 0. " RawIntr0 ,Raw Interrupt Status 0" "Inactivated,Activated" group.long 0xC++0x3 line.long 0x0 "VIC1_INTSR,Interrupt Select Register" bitfld.long 0x0 15. " IntSelect15 ,Interrupt Selection 15" "IRQ,FIQ" bitfld.long 0x0 14. " IntSelect14 ,Interrupt Selection 14" "IRQ,FIQ" textline " " bitfld.long 0x0 13. " IntSelect13 ,Interrupt Selection 13" "IRQ,FIQ" bitfld.long 0x0 12. " IntSelect12 ,Interrupt Selection 12" "IRQ,FIQ" textline " " bitfld.long 0x0 11. " IntSelect11 ,Interrupt Selection 11" "IRQ,FIQ" bitfld.long 0x0 10. " IntSelect10 ,Interrupt Selection 10" "IRQ,FIQ" textline " " bitfld.long 0x0 9. " IntSelect9 ,Interrupt Selection 9" "IRQ,FIQ" bitfld.long 0x0 8. " IntSelect8 ,Interrupt Selection 8" "IRQ,FIQ" textline " " bitfld.long 0x0 7. " IntSelect7 ,Interrupt Selection 7" "IRQ,FIQ" bitfld.long 0x0 6. " IntSelect6 ,Interrupt Selection 6" "IRQ,FIQ" textline " " bitfld.long 0x0 5. " IntSelect5 ,Interrupt Selection 5" "IRQ,FIQ" bitfld.long 0x0 4. " IntSelect4 ,Interrupt Selection 4" "IRQ,FIQ" textline " " bitfld.long 0x0 3. " IntSelect3 ,Interrupt Selection 3" "IRQ,FIQ" bitfld.long 0x0 2. " IntSelect2 ,Interrupt Selection 2" "IRQ,FIQ" textline " " bitfld.long 0x0 1. " IntSelect1 ,Interrupt Selection 1" "IRQ,FIQ" bitfld.long 0x0 0. " IntSelect0 ,Interrupt Selection 0" "IRQ,FIQ" group.long 0x10++0x3 line.long 0x0 "VIC1_INTER/INTECR,Interrupt Enable Register" setclrfld.long 0x0 15. 0x0 15. 0x4 15. " IntEnable15_Clear/Set ,Interrupt Enable 15" "Disabled,Enabled" setclrfld.long 0x0 14. 0x0 14. 0x4 14. " IntEnable14_Clear/Set ,Interrupt Enable 14" "Disabled,Enabled" textline " " setclrfld.long 0x0 13. 0x0 13. 0x4 13. " IntEnable13_Clear/Set ,Interrupt Enable 13" "Disabled,Enabled" setclrfld.long 0x0 12. 0x0 12. 0x4 12. " IntEnable12_Clear/Set ,Interrupt Enable 12" "Disabled,Enabled" textline " " setclrfld.long 0x0 11. 0x0 11. 0x4 11. " IntEnable11_Clear/Set ,Interrupt Enable 11" "Disabled,Enabled" setclrfld.long 0x0 10. 0x0 10. 0x4 10. " IntEnable10_Clear/Set ,Interrupt Enable 10" "Disabled,Enabled" textline " " setclrfld.long 0x0 9. 0x0 9. 0x4 9. " IntEnable9_Clear/Set ,Interrupt Enable 9" "Disabled,Enabled" setclrfld.long 0x0 8. 0x0 8. 0x4 8. " IntEnable8_Clear/Set ,Interrupt Enable 8" "Disabled,Enabled" textline " " setclrfld.long 0x0 7. 0x0 7. 0x4 7. " IntEnable7_Clear/Set ,Interrupt Enable 7" "Disabled,Enabled" setclrfld.long 0x0 6. 0x0 6. 0x4 6. " IntEnable6_Clear/Set ,Interrupt Enable 6" "Disabled,Enabled" textline " " setclrfld.long 0x0 5. 0x0 5. 0x4 5. " IntEnable5_Clear/Set ,Interrupt Enable 5" "Disabled,Enabled" setclrfld.long 0x0 4. 0x0 4. 0x4 4. " IntEnable4_Clear/Set ,Interrupt Enable 4" "Disabled,Enabled" textline " " setclrfld.long 0x0 3. 0x0 3. 0x4 3. " IntEnable3_Clear/Set ,Interrupt Enable 3" "Disabled,Enabled" setclrfld.long 0x0 2. 0x0 2. 0x4 2. " IntEnable2_Clear/Set ,Interrupt Enable 2" "Disabled,Enabled" textline " " setclrfld.long 0x0 1. 0x0 1. 0x4 1. " IntEnable1_Clear/Set ,Interrupt Enable 1" "Disabled,Enabled" setclrfld.long 0x0 0. 0x0 0. 0x4 0. " IntEnable0_Clear/Set ,Interrupt Enable 0" "Disabled,Enabled" group.long 0x18++0x3 line.long 0x0 "VIC1_SWINTR,Software Interrupt Register" setclrfld.long 0x0 15. 0x0 15. 0x4 15. " SoftInt15_Clear/Set ,Software Interrupt 15" "Not activated,Activated" setclrfld.long 0x0 14. 0x0 14. 0x4 14. " SoftInt14_Clear/Set ,Software Interrupt 14" "Not activated,Activated" textline " " setclrfld.long 0x0 13. 0x0 13. 0x4 13. " SoftInt13_Clear/Set ,Software Interrupt 13" "Not activated,Activated" setclrfld.long 0x0 12. 0x0 12. 0x4 12. " SoftInt12_Clear/Set ,Software Interrupt 12" "Not activated,Activated" textline " " setclrfld.long 0x0 11. 0x0 11. 0x4 11. " SoftInt11_Clear/Set ,Software Interrupt 11" "Not activated,Activated" setclrfld.long 0x0 10. 0x0 10. 0x4 10. " SoftInt10_Clear/Set ,Software Interrupt 10" "Not activated,Activated" textline " " setclrfld.long 0x0 9. 0x0 9. 0x4 9. " SoftInt9_Clear/Set ,Software Interrupt 9" "Not activated,Activated" setclrfld.long 0x0 8. 0x0 8. 0x4 8. " SoftInt8_Clear/Set ,Software Interrupt 8" "Not activated,Activated" textline " " setclrfld.long 0x0 7. 0x0 7. 0x4 7. " SoftInt7_Clear/Set ,Software Interrupt 7" "Not activated,Activated" setclrfld.long 0x0 6. 0x0 6. 0x4 6. " SoftInt6_Clear/Set ,Software Interrupt 6" "Not activated,Activated" textline " " setclrfld.long 0x0 5. 0x0 5. 0x4 5. " SoftInt5_Clear/Set ,Software Interrupt 5" "Not activated,Activated" setclrfld.long 0x0 4. 0x0 4. 0x4 4. " SoftInt4_Clear/Set ,Software Interrupt 4" "Not activated,Activated" textline " " setclrfld.long 0x0 3. 0x0 3. 0x4 3. " SoftInt3_Clear/Set ,Software Interrupt 3" "Not activated,Activated" setclrfld.long 0x0 2. 0x0 2. 0x4 2. " SoftInt2_Clear/Set ,Software Interrupt 2" "Not activated,Activated" textline " " setclrfld.long 0x0 1. 0x0 1. 0x4 1. " SoftInt1_Clear/Set ,Software Interrupt 1" "Not activated,Activated" setclrfld.long 0x0 0. 0x0 0. 0x4 0. " SoftInt0_Clear/Set ,Software Interrupt 0" "Not activated,Activated" group.long 0x20++0x3 line.long 0x0 "VIC1_PER,Protection Enable Register" bitfld.long 0x0 0. " PROT ,Protection" "Not protected,Protected" width 0xC tree "Vector Registers" hgroup.long 0x30++0x3 hide.long 0x0 "VIC1_VAR,Current Vector Address Register" in group.long 0x34++0x3 line.long 0x0 "VIC1_DVAR,Default Vector Address Register" group.long 0x100++0x3 line.long 0x0 "VIC1_VA0R,Vector Address 0 Register" group.long 0x104++0x3 line.long 0x0 "VIC1_VA1R,Vector Address 1 Register" group.long 0x108++0x3 line.long 0x0 "VIC1_VA2R,Vector Address 2 Register" group.long 0x10C++0x3 line.long 0x0 "VIC1_VA3R,Vector Address 3 Register" group.long 0x110++0x3 line.long 0x0 "VIC1_VA4R,Vector Address 4 Register" group.long 0x114++0x3 line.long 0x0 "VIC1_VA5R,Vector Address 5 Register" group.long 0x118++0x3 line.long 0x0 "VIC1_VA6R,Vector Address 6 Register" group.long 0x11C++0x3 line.long 0x0 "VIC1_VA7R,Vector Address 7 Register" group.long 0x120++0x3 line.long 0x0 "VIC1_VA8R,Vector Address 8 Register" group.long 0x124++0x3 line.long 0x0 "VIC1_VA9R,Vector Address 9 Register" group.long 0x128++0x3 line.long 0x0 "VIC1_VA10R,Vector Address 10 Register" group.long 0x12C++0x3 line.long 0x0 "VIC1_VA11R,Vector Address 11 Register" group.long 0x130++0x3 line.long 0x0 "VIC1_VA12R,Vector Address 12 Register" group.long 0x134++0x3 line.long 0x0 "VIC1_VA13R,Vector Address 13 Register" group.long 0x138++0x3 line.long 0x0 "VIC1_VA14R,Vector Address 14 Register" group.long 0x13C++0x3 line.long 0x0 "VIC1_VA15R,Vector Address 15 Register" group.long 0x200++0x3 line.long 0x0 "VIC1_VC0R,Vector Control 0 Register" bitfld.long 0x0 5. " E0 ,Vector Interrupt 0 Enable" "Disabled,Enabled" bitfld.long 0x0 0.--4. " VectorCntl0[4:0] ,Vector Control 0" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 8,Source 9,Source 10,Source 11,Source 12,Source 13,Source 14,Source 15,?..." group.long 0x204++0x3 line.long 0x0 "VIC1_VC1R,Vector Control 1 Register" bitfld.long 0x0 5. " E1 ,Vector Interrupt 1 Enable" "Disabled,Enabled" bitfld.long 0x0 0.--4. " VectorCntl1[4:0] ,Vector Control 1" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 8,Source 9,Source 10,Source 11,Source 12,Source 13,Source 14,Source 15,?..." group.long 0x208++0x3 line.long 0x0 "VIC1_VC2R,Vector Control 2 Register" bitfld.long 0x0 5. " E2 ,Vector Interrupt 2 Enable" "Disabled,Enabled" bitfld.long 0x0 0.--4. " VectorCntl2[4:0] ,Vector Control 2" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 8,Source 9,Source 10,Source 11,Source 12,Source 13,Source 14,Source 15,?..." group.long 0x20C++0x3 line.long 0x0 "VIC1_VC3R,Vector Control 3 Register" bitfld.long 0x0 5. " E3 ,Vector Interrupt 3 Enable" "Disabled,Enabled" bitfld.long 0x0 0.--4. " VectorCntl3[4:0] ,Vector Control 3" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 8,Source 9,Source 10,Source 11,Source 12,Source 13,Source 14,Source 15,?..." group.long 0x210++0x3 line.long 0x0 "VIC1_VC4R,Vector Control 4 Register" bitfld.long 0x0 5. " E4 ,Vector Interrupt 4 Enable" "Disabled,Enabled" bitfld.long 0x0 0.--4. " VectorCntl4[4:0] ,Vector Control 4" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 8,Source 9,Source 10,Source 11,Source 12,Source 13,Source 14,Source 15,?..." group.long 0x214++0x3 line.long 0x0 "VIC1_VC5R,Vector Control 5 Register" bitfld.long 0x0 5. " E5 ,Vector Interrupt 5 Enable" "Disabled,Enabled" bitfld.long 0x0 0.--4. " VectorCntl5[4:0] ,Vector Control 5" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 8,Source 9,Source 10,Source 11,Source 12,Source 13,Source 14,Source 15,?..." group.long 0x218++0x3 line.long 0x0 "VIC1_VC6R,Vector Control 6 Register" bitfld.long 0x0 5. " E6 ,Vector Interrupt 6 Enable" "Disabled,Enabled" bitfld.long 0x0 0.--4. " VectorCntl6[4:0] ,Vector Control 6" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 8,Source 9,Source 10,Source 11,Source 12,Source 13,Source 14,Source 15,?..." group.long 0x21C++0x3 line.long 0x0 "VIC1_VC7R,Vector Control 7 Register" bitfld.long 0x0 5. " E7 ,Vector Interrupt 7 Enable" "Disabled,Enabled" bitfld.long 0x0 0.--4. " VectorCntl7[4:0] ,Vector Control 7" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 8,Source 9,Source 10,Source 11,Source 12,Source 13,Source 14,Source 15,?..." group.long 0x220++0x3 line.long 0x0 "VIC1_VC8R,Vector Control 8 Register" bitfld.long 0x0 5. " E8 ,Vector Interrupt 8 Enable" "Disabled,Enabled" bitfld.long 0x0 0.--4. " VectorCntl8[4:0] ,Vector Control 8" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 8,Source 9,Source 10,Source 11,Source 12,Source 13,Source 14,Source 15,?..." group.long 0x224++0x3 line.long 0x0 "VIC1_VC9R,Vector Control 9 Register" bitfld.long 0x0 5. " E9 ,Vector Interrupt 9 Enable" "Disabled,Enabled" bitfld.long 0x0 0.--4. " VectorCntl9[4:0] ,Vector Control 9" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 8,Source 9,Source 10,Source 11,Source 12,Source 13,Source 14,Source 15,?..." group.long 0x228++0x3 line.long 0x0 "VIC1_VC10R,Vector Control 10 Register" bitfld.long 0x0 5. " E10 ,Vector Interrupt 10 Enable" "Disabled,Enabled" bitfld.long 0x0 0.--4. " VectorCntl10[4:0] ,Vector Control 10" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 8,Source 9,Source 10,Source 11,Source 12,Source 13,Source 14,Source 15,?..." group.long 0x22C++0x3 line.long 0x0 "VIC1_VC11R,Vector Control 11 Register" bitfld.long 0x0 5. " E11 ,Vector Interrupt 11 Enable" "Disabled,Enabled" bitfld.long 0x0 0.--4. " VectorCntl11[4:0] ,Vector Control 11" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 8,Source 9,Source 10,Source 11,Source 12,Source 13,Source 14,Source 15,?..." group.long 0x230++0x3 line.long 0x0 "VIC1_VC12R,Vector Control 12 Register" bitfld.long 0x0 5. " E12 ,Vector Interrupt 12 Enable" "Disabled,Enabled" bitfld.long 0x0 0.--4. " VectorCntl12[4:0] ,Vector Control 12" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 8,Source 9,Source 10,Source 11,Source 12,Source 13,Source 14,Source 15,?..." group.long 0x234++0x3 line.long 0x0 "VIC1_VC13R,Vector Control 13 Register" bitfld.long 0x0 5. " E13 ,Vector Interrupt 13 Enable" "Disabled,Enabled" bitfld.long 0x0 0.--4. " VectorCntl13[4:0] ,Vector Control 13" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 8,Source 9,Source 10,Source 11,Source 12,Source 13,Source 14,Source 15,?..." group.long 0x238++0x3 line.long 0x0 "VIC1_VC14R,Vector Control 14 Register" bitfld.long 0x0 5. " E14 ,Vector Interrupt 14 Enable" "Disabled,Enabled" bitfld.long 0x0 0.--4. " VectorCntl14[4:0] ,Vector Control 14" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 8,Source 9,Source 10,Source 11,Source 12,Source 13,Source 14,Source 15,?..." group.long 0x23C++0x3 line.long 0x0 "VIC1_VC15R,Vector Control 15 Register" bitfld.long 0x0 5. " E15 ,Vector Interrupt 15 Enable" "Disabled,Enabled" bitfld.long 0x0 0.--4. " VectorCntl15[4:0] ,Vector Control 15" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 8,Source 9,Source 10,Source 11,Source 12,Source 13,Source 14,Source 15,?..." tree.end tree.end endif width 0xB tree.end tree "WIU (Wake-Up/Interrupt Unit)" base asd:0x58001000 width 10. group.long 0x0++0xB line.long 0x0 "WIU_CTRL,WIU Control Register" bitfld.long 0x0 1. " INT_EN ,Global WIU Interrupt Enable" "Disabled,Enabled" sif (!cpuis("STR910FA*")&&!cpuis("STR911FA*")&&!cpuis("STR912FA*")) bitfld.long 0x0 0. " WKUP-INT ,Wake-Up Enable" "Disabled,Enabled" endif line.long 0x4 "WIU_MR,WIU Mask Register" bitfld.long 0x4 31. " WUM31 ,WIU Mask 31" "Disabled,Enabled" bitfld.long 0x4 30. " WUM30 ,WIU Mask 30" "Disabled,Enabled" bitfld.long 0x4 29. " WUM29 ,WIU Mask 29" "Disabled,Enabled" textline " " bitfld.long 0x4 28. " WUM28 ,WIU Mask 28" "Disabled,Enabled" bitfld.long 0x4 27. " WUM27 ,WIU Mask 27" "Disabled,Enabled" bitfld.long 0x4 26. " WUM26 ,WIU Mask 26" "Disabled,Enabled" textline " " bitfld.long 0x4 25. " WUM25 ,WIU Mask 25" "Disabled,Enabled" bitfld.long 0x4 24. " WUM24 ,WIU Mask 24" "Disabled,Enabled" bitfld.long 0x4 23. " WUM23 ,WIU Mask 23" "Disabled,Enabled" textline " " bitfld.long 0x4 22. " WUM22 ,WIU Mask 22" "Disabled,Enabled" bitfld.long 0x4 21. " WUM21 ,WIU Mask 21" "Disabled,Enabled" bitfld.long 0x4 20. " WUM20 ,WIU Mask 20" "Disabled,Enabled" textline " " bitfld.long 0x4 19. " WUM19 ,WIU Mask 19" "Disabled,Enabled" bitfld.long 0x4 18. " WUM18 ,WIU Mask 18" "Disabled,Enabled" bitfld.long 0x4 17. " WUM17 ,WIU Mask 17" "Disabled,Enabled" textline " " bitfld.long 0x4 16. " WUM16 ,WIU Mask 16" "Disabled,Enabled" bitfld.long 0x4 15. " WUM15 ,WIU Mask 15" "Disabled,Enabled" bitfld.long 0x4 14. " WUM14 ,WIU Mask 14" "Disabled,Enabled" textline " " bitfld.long 0x4 13. " WUM13 ,WIU Mask 13" "Disabled,Enabled" bitfld.long 0x4 12. " WUM12 ,WIU Mask 12" "Disabled,Enabled" bitfld.long 0x4 11. " WUM11 ,WIU Mask 11" "Disabled,Enabled" textline " " bitfld.long 0x4 10. " WUM10 ,WIU Mask 10" "Disabled,Enabled" bitfld.long 0x4 9. " WUM9 ,WIU Mask 9" "Disabled,Enabled" bitfld.long 0x4 8. " WUM8 ,WIU Mask 8" "Disabled,Enabled" textline " " bitfld.long 0x4 7. " WUM7 ,WIU Mask 7" "Disabled,Enabled" bitfld.long 0x4 6. " WUM6 ,WIU Mask 6" "Disabled,Enabled" bitfld.long 0x4 5. " WUM5 ,WIU Mask 5" "Disabled,Enabled" textline " " bitfld.long 0x4 4. " WUM4 ,WIU Mask 4" "Disabled,Enabled" bitfld.long 0x4 3. " WUM3 ,WIU Mask 3" "Disabled,Enabled" bitfld.long 0x4 2. " WUM2 ,WIU Mask 2" "Disabled,Enabled" line.long 0x8 "WIU_TR,WIU Trigger Register" bitfld.long 0x8 31. " WUT31 ,Wake-Up Trigger Polarity 31" "Falling,Rising" bitfld.long 0x8 30. " WUT30 ,Wake-Up Trigger Polarity 30" "Falling,Rising" bitfld.long 0x8 29. " WUT29 ,Wake-Up Trigger Polarity 29" "Falling,Rising" textline " " bitfld.long 0x8 28. " WUT28 ,Wake-Up Trigger Polarity 28" "Falling,Rising" bitfld.long 0x8 27. " WUT27 ,Wake-Up Trigger Polarity 27" "Falling,Rising" bitfld.long 0x8 26. " WUT26 ,Wake-Up Trigger Polarity 26" "Falling,Rising" textline " " bitfld.long 0x8 25. " WUT25 ,Wake-Up Trigger Polarity 25" "Falling,Rising" bitfld.long 0x8 24. " WUT24 ,Wake-Up Trigger Polarity 24" "Falling,Rising" bitfld.long 0x8 23. " WUT23 ,Wake-Up Trigger Polarity 23" "Falling,Rising" textline " " bitfld.long 0x8 22. " WUT22 ,Wake-Up Trigger Polarity 22" "Falling,Rising" bitfld.long 0x8 21. " WUT21 ,Wake-Up Trigger Polarity 21" "Falling,Rising" bitfld.long 0x8 20. " WUT20 ,Wake-Up Trigger Polarity 20" "Falling,Rising" textline " " bitfld.long 0x8 19. " WUT19 ,Wake-Up Trigger Polarity 19" "Falling,Rising" bitfld.long 0x8 18. " WUT18 ,Wake-Up Trigger Polarity 18" "Falling,Rising" bitfld.long 0x8 17. " WUT17 ,Wake-Up Trigger Polarity 17" "Falling,Rising" textline " " bitfld.long 0x8 16. " WUT16 ,Wake-Up Trigger Polarity 16" "Falling,Rising" bitfld.long 0x8 15. " WUT15 ,Wake-Up Trigger Polarity 15" "Falling,Rising" bitfld.long 0x8 14. " WUT14 ,Wake-Up Trigger Polarity 14" "Falling,Rising" textline " " bitfld.long 0x8 13. " WUT13 ,Wake-Up Trigger Polarity 13" "Falling,Rising" bitfld.long 0x8 12. " WUT12 ,Wake-Up Trigger Polarity 12" "Falling,Rising" bitfld.long 0x8 11. " WUT11 ,Wake-Up Trigger Polarity 11" "Falling,Rising" textline " " bitfld.long 0x8 10. " WUT10 ,Wake-Up Trigger Polarity 10" "Falling,Rising" bitfld.long 0x8 9. " WUT9 ,Wake-Up Trigger Polarity 9" "Falling,Rising" bitfld.long 0x8 8. " WUT8 ,Wake-Up Trigger Polarity 8" "Falling,Rising" textline " " bitfld.long 0x8 7. " WUT7 ,Wake-Up Trigger Polarity 7" "Falling,Rising" bitfld.long 0x8 6. " WUT6 ,Wake-Up Trigger Polarity 6" "Falling,Rising" bitfld.long 0x8 5. " WUT5 ,Wake-Up Trigger Polarity 5" "Falling,Rising" textline " " bitfld.long 0x8 4. " WUT4 ,Wake-Up Trigger Polarity 4" "Falling,Rising" bitfld.long 0x8 3. " WUT3 ,Wake-Up Trigger Polarity 3" "Falling,Rising" bitfld.long 0x8 2. " WUT2 ,Wake-Up Trigger Polarity 2" "Falling,Rising" group.long 0xC++0x7 line.long 0x0 "WIU_PR,WIU Pending Register" setclrfld.long 0x0 31. 0x4 31. 0x0 31. " WUP31_Clear/Set ,WIU Pending 31" "No wake-up,Wake-up" setclrfld.long 0x0 30. 0x4 30. 0x0 30. " WUP30_Clear/Set ,WIU Pending 30" "No wake-up,Wake-up" textline " " setclrfld.long 0x0 29. 0x4 29. 0x0 29. " WUP29_Clear/Set ,WIU Pending 29" "No wake-up,Wake-up" setclrfld.long 0x0 28. 0x4 28. 0x0 28. " WUP28_Clear/Set ,WIU Pending 28" "No wake-up,Wake-up" textline " " setclrfld.long 0x0 27. 0x4 27. 0x0 27. " WUP27_Clear/Set ,WIU Pending 27" "No wake-up,Wake-up" setclrfld.long 0x0 26. 0x4 26. 0x0 26. " WUP26_Clear/Set ,WIU Pending 26" "No wake-up,Wake-up" textline " " setclrfld.long 0x0 25. 0x4 25. 0x0 25. " WUP25_Clear/Set ,WIU Pending 25" "No wake-up,Wake-up" setclrfld.long 0x0 24. 0x4 24. 0x0 24. " WUP24_Clear/Set ,WIU Pending 24" "No wake-up,Wake-up" textline " " setclrfld.long 0x0 23. 0x4 23. 0x0 23. " WUP23_Clear/Set ,WIU Pending 23" "No wake-up,Wake-up" setclrfld.long 0x0 22. 0x4 22. 0x0 22. " WUP22_Clear/Set ,WIU Pending 22" "No wake-up,Wake-up" textline " " setclrfld.long 0x0 21. 0x4 21. 0x0 21. " WUP21_Clear/Set ,WIU Pending 21" "No wake-up,Wake-up" setclrfld.long 0x0 20. 0x4 20. 0x0 20. " WUP20_Clear/Set ,WIU Pending 20" "No wake-up,Wake-up" textline " " setclrfld.long 0x0 19. 0x4 19. 0x0 19. " WUP19_Clear/Set ,WIU Pending 19" "No wake-up,Wake-up" setclrfld.long 0x0 18. 0x4 18. 0x0 18. " WUP18_Clear/Set ,WIU Pending 18" "No wake-up,Wake-up" textline " " setclrfld.long 0x0 17. 0x4 17. 0x0 17. " WUP17_Clear/Set ,WIU Pending 17" "No wake-up,Wake-up" setclrfld.long 0x0 16. 0x4 16. 0x0 16. " WUP16_Clear/Set ,WIU Pending 16" "No wake-up,Wake-up" textline " " setclrfld.long 0x0 15. 0x4 15. 0x0 15. " WUP15_Clear/Set ,WIU Pending 15" "No wake-up,Wake-up" setclrfld.long 0x0 14. 0x4 14. 0x0 14. " WUP14_Clear/Set ,WIU Pending 14" "No wake-up,Wake-up" textline " " setclrfld.long 0x0 13. 0x4 13. 0x0 13. " WUP13_Clear/Set ,WIU Pending 13" "No wake-up,Wake-up" setclrfld.long 0x0 12. 0x4 12. 0x0 12. " WUP12_Clear/Set ,WIU Pending 12" "No wake-up,Wake-up" textline " " setclrfld.long 0x0 11. 0x4 11. 0x0 11. " WUP11_Clear/Set ,WIU Pending 11" "No wake-up,Wake-up" setclrfld.long 0x0 10. 0x4 10. 0x0 10. " WUP10_Clear/Set ,WIU Pending 10" "No wake-up,Wake-up" textline " " setclrfld.long 0x0 9. 0x4 9. 0x0 9. " WUP9_Clear/Set ,WIU Pending 9" "No wake-up,Wake-up" setclrfld.long 0x0 8. 0x4 8. 0x0 8. " WUP8_Clear/Set ,WIU Pending 8" "No wake-up,Wake-up" textline " " setclrfld.long 0x0 7. 0x4 7. 0x0 7. " WUP7_Clear/Set ,WIU Pending 7" "No wake-up,Wake-up" setclrfld.long 0x0 6. 0x4 6. 0x0 6. " WUP6_Clear/Set ,WIU Pending 6" "No wake-up,Wake-up" textline " " setclrfld.long 0x0 5. 0x4 5. 0x0 5. " WUP5_Clear/Set ,WIU Pending 5" "No wake-up,Wake-up" setclrfld.long 0x0 4. 0x4 4. 0x0 4. " WUP4_Clear/Set ,WIU Pending 4" "No wake-up,Wake-up" textline " " setclrfld.long 0x0 3. 0x4 3. 0x0 3. " WUP3_Clear/Set ,WIU Pending 3" "No wake-up,Wake-up" setclrfld.long 0x0 2. 0x4 2. 0x0 2. " WUP2_Clear/Set ,WIU Pending 2" "No wake-up,Wake-up" width 0xB tree.end tree "RTC (Real Time Clock)" base asd:0x5C001000 width 10. if (((data.long(asd:(0x5C001000+0xC)))&0x80)==0x80) group.long 0x0++0x7 line.long 0x0 "RTC_TR,RTC Time Register" bitfld.long 0x00 28.--29. " DT[1:0] ,Date Tens in BCD Format" "0,1,2,3" bitfld.long 0x00 24.--27. " DU[3:0] ,Date Units in BCD Format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." bitfld.long 0x00 20.--21. " HT[1:0] ,Hour Tens in BCD Format" "0,1,2,-" textline " " bitfld.long 0x00 16.--19. " HU[3:0] ,Hour Units in BCD Format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." bitfld.long 0x00 12.--14. " MIT[2:0] ,Minute Tens in BCD Format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. " MIU[3:0] ,Minute Units in BCD Format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." textline " " bitfld.long 0x00 4.--6. " ST[2:0] ,Second Tens in BCD Format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. " SU[3:0] ,Second Units in BCD Format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." line.long 0x4 "RTC_DTR,RTC Date Register" bitfld.long 0x04 28.--31. " CT[3:0] ,Century Tens in BCD Format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." bitfld.long 0x04 24.--27. " CU[3:0] ,Century Units in BCD Format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." bitfld.long 0x04 20.--23. " YT[3:0] ,Year Tens in BCD Format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." textline " " bitfld.long 0x04 16.--19. " YU[3:0] ,Year Units in BCD Format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." bitfld.long 0x04 12. " MT ,Month Tens in BCD Format" "0,1" bitfld.long 0x04 8.--11. " MU[3:0] ,Month Units in BCD Format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." textline " " bitfld.long 0x04 0.--3. " WDU[3:0] ,Weekday Units in BCD Format" "-,1,2,3,4,5,6,7,-,-,-,-,-,?..." else rgroup.long 0x0++0x7 line.long 0x0 "RTC_TR,RTC Time Register" bitfld.long 0x00 28.--29. " DT[1:0] ,Date Tens in BCD Format" "0,1,2,3" bitfld.long 0x00 24.--27. " DU[3:0] ,Date Units in BCD Format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." bitfld.long 0x00 20.--21. " HT[1:0] ,Hour Tens in BCD Format" "0,1,2,-" textline " " bitfld.long 0x00 16.--19. " HU[3:0] ,Hour Units in BCD Format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." bitfld.long 0x00 12.--14. " MIT[2:0] ,Minute Tens in BCD Format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. " MIU[3:0] ,Minute Units in BCD Format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." textline " " bitfld.long 0x00 4.--6. " ST[2:0] ,Second Tens in BCD Format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. " SU[3:0] ,Second Units in BCD Format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." line.long 0x4 "RTC_DTR,RTC Date Register" bitfld.long 0x04 28.--31. " CT[3:0] ,Century Tens in BCD Format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." bitfld.long 0x04 24.--27. " CU[3:0] ,Century Units in BCD Format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." bitfld.long 0x04 20.--23. " YT[3:0] ,Year Tens in BCD Format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." textline " " bitfld.long 0x04 16.--19. " YU[3:0] ,Year Units in BCD Format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." bitfld.long 0x04 12. " MT ,Month Tens in BCD Format" "0,1" bitfld.long 0x04 8.--11. " MU[3:0] ,Month Units in BCD Format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." textline " " bitfld.long 0x04 0.--3. " WDU[3:0] ,Weekday Units in BCD Format" "-,1,2,3,4,5,6,7,-,-,-,-,-,?..." endif group.long 0x8++0x7 line.long 0x0 "RTC_ATR,RTC Alarm Time Register" bitfld.long 0x00 28.--29. " ADT[1:0] ,Alarm Date Tens in BCD Format" "0,1,2,3" bitfld.long 0x00 24.--27. " ADU[3:0] ,Alarm Date Units in BCD Format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." bitfld.long 0x00 20.--21. " AHT[1:0] ,Alarm Hour Tens in BCD Format" "0,1,2,-" textline " " bitfld.long 0x00 16.--19. " AHU[3:0] ,Alarm Hour Units in BCD Format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." bitfld.long 0x00 12.--14. " AMIT[2:0] ,Alarm Minute Tens in BCD Format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 8.--11. " AMIU[3:0] ,Alarm Minute Units in BCD Format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." textline " " bitfld.long 0x00 4.--6. " AST[2:0] ,Alarm Second Tens in BCD Format" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. " ASU[3:0] ,Alarm Second Units in BCD Format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." line.long 0x4 "RTC_CR,RTC Control Register" bitfld.long 0x04 23. " AIE ,Alarm Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 22. " TIE ,Tamper Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 21. " PIE ,Periodic Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 20. " AE ,Alarm Enable" "Disabled,Enabled" bitfld.long 0x04 16.--19. " PISEL[3:0] ,Periodic Interrupt Selection" "Reserved,2 Hz,16 Hz,Reserved,128 Hz,Reserved,Reserved,Reserved,1024 Hz,?..." bitfld.long 0x04 7. " W ,Write Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 6. " C ,Calibration Clock Output Enable" "Disabled,Enabled" bitfld.long 0x04 4. " TM ,Tamper Mode" "Low/high,Closed/opened" bitfld.long 0x04 3. " PWR ,SRAM VBATT Power Control" "Disconnected,Connected" textline " " bitfld.long 0x04 2. " TIS ,Trigger Selection" "Low,High" bitfld.long 0x04 0. " TE ,Tamper Input Enable" "Disabled,Enabled" hgroup.long 0x10++0x3 hide.long 0x0 "RTC_SR,RTC Status Register" in if (((data.long(asd:(0x5C001000+0xC)))&0x80)==0x80) group.long 0x14++0x3 line.long 0x0 "RTC_MILR,RTC Millisecond Register" bitfld.long 0x0 8.--11. " MSH[3:0] ,Millisecond Hundreds in BCD Format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." bitfld.long 0x0 4.--7. " MST[3:0] ,Millisecond Tens in BCD Format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." bitfld.long 0x0 0.--3. " MSU[3:0] ,Millisecond Units in BCD Format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." else rgroup.long 0x14++0x3 line.long 0x0 "RTC_MILR,RTC Millisecond Register" bitfld.long 0x0 8.--11. " MSH[3:0] ,Millisecond Hundreds in BCD Format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." bitfld.long 0x0 4.--7. " MST[3:0] ,Millisecond Tens in BCD Format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." bitfld.long 0x0 0.--3. " MSU[3:0] ,Millisecond Units in BCD Format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." endif width 0xB tree.end tree "WDG (Watchdog Timer)" base asd:0x5C00B000 width 9. if (((data.word(asd:0x5C00B000))&0x1)==0x0) group.word 0x0++0x1 line.word 0x0 "WDG_CR,WDG Control Register" bitfld.word 0x0 2. " EE ,External Clock Enable" "PCLK,RTC" bitfld.word 0x0 0. " WE ,Watchdog Enable Bit" "Timer,Watchdog" bitfld.word 0x0 1. " SC ,Counting Start" "Stopped,Started" else group.word 0x0++0x1 line.word 0x0 "WDG_CR,WDG Control Register" bitfld.word 0x0 2. " EE ,External Clock Enable" "PCLK,RTC" bitfld.word 0x0 0. " WE ,Watchdog Enable Bit" "Timer,Watchdog" endif group.word 0x4++0x1 line.word 0x0 "WDG_PR,WDG Prescaler Register" hexmask.word.byte 0x0 0.--7. 1. " PR[7:0] ,Prescaler Value" group.word 0x8++0x1 line.word 0x0 "WDG_VR,WDG Preload Value Register" rgroup.word 0xC++0x1 line.word 0x0 "WDG_CNT,WDG Counter Register" if (((data.word(asd:0x5C00B000))&0x1)==0x0) group.word 0x10++0x1 line.word 0x0 "WDG_SR,WDG Status Register" bitfld.word 0x0 0. " EC ,End of Count Pending" "Not ended,Ended" else group.word 0x10++0x1 line.word 0x0 "WDG_SR,WDG Status Register" endif group.word 0x14++0x1 line.word 0x0 "WDG_MR,WDG Mask Register" bitfld.word 0x0 0. " ECM ,End of Count Mask" "Disabled,Enabled" if (((data.word(asd:0x5C00B000))&0x1)==0x1) group.word 0x18++0x1 line.word 0x0 "WDG_KR,WDG Key Register" hexmask.word 0x0 0.--15. 1. " K[15:0] ,Key Value" else rgroup.word 0x18++0x1 line.word 0x0 "WDG_KR,WDG Key Register" hexmask.word 0x0 0.--15. 1. " K[15:0] ,Key Value" endif width 0xB tree.end tree.open "TIM (16-Bit Timer)" width 10. base asd:0x58002000 tree "TIM0 (16-Bit Timer 0)" rgroup.long 0x0++0x17 line.long 0x0 "TIM0_IC1R,Input Capture Register 1" hexmask.long.word 0x00 0.--15. 1. " IC1R ,IC 1 Captured value" line.long 0x4 "TIM0_IC2R,Input Capture Register 2" hexmask.long.word 0x04 0.--15. 1. " IC2R ,IC 2 Captured value" line.long 0x8 "TIM0_OC1R,Output Compare Register 1" hexmask.long.word 0x08 0.--15. 1. " OC1R ,OC 1 Compare value" line.long 0xC "TIM0_OC2R,Output Compare Register 2" hexmask.long.word 0x0C 0.--15. 1. " OC2R ,OC 2 Compare value" line.long 0x10 "TIM0_CNTR,Counter Register" hexmask.long.word 0x10 0.--15. 1. " OCR2 ,Counter value" line.long 0x14 "TIM0_CR1,Control Register 1" bitfld.long 0x14 15. " EN ,Counter Enable" "Disabled,Enabled" bitfld.long 0x14 14. " PWMI ,PWM Input Mode Enable" "Disabled,Enabled" bitfld.long 0x14 12.--13. " DMAS ,DMA Source Selection" "IC1,OC1,IC2,OC2" textline " " bitfld.long 0x14 11. " FOLV2 ,Forced Output Compare 2" "No effect,OLVL2->OCMP2" bitfld.long 0x14 10. " FOLV1 ,Forced Output Compare 1" "No effect,OLVL1->OCMP1" bitfld.long 0x14 9. " OLVL2 ,Output Level 2" "Low,High" textline " " bitfld.long 0x14 8. " OLVL1 ,Output Level 1" "Low,High" bitfld.long 0x14 7. " OC2E ,Output Compare 2 Enable" "Disabled,Enabled" bitfld.long 0x14 6. " OC1E ,Output Compare 1 Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 5. " OPM ,One Pulse Mode" "Not activated,Activated" bitfld.long 0x14 4. " PWM ,Pulse Width Modulation Mode" "Not activated,Activated" bitfld.long 0x14 3. " IEDG2 ,Input Edge 2" "Falling,Rising" textline " " bitfld.long 0x14 2. " IEDG1 ,Input Edge 1" "Falling,Rising" bitfld.long 0x14 1. " EXEDG ,External Clock Edge" "Falling,Rising" bitfld.long 0x14 0. " ECKEN ,External Clock Enable" "Internal,External" if (0<2) group.long 0x18++0x3 line.long 0x0 "TIM0_CR2,Control Register 2" bitfld.long 0x00 15. " IC1IE ,Input Capture 1 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. " OC1IE ,Output Compare 1 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 13. " TOIE ,Timer Overflow Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " IC2IE ,Input Capture 2 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " OC2IE ,Output Compare 2 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10. " DMAE ,DMA Enable" "Disabled,Enabled" textline " " hexmask.long.byte 0x00 0.--7. 1. " CC ,Clock Control" else group.long 0x18++0x3 line.long 0x0 "TIM0_CR2,Control Register 2" bitfld.long 0x00 15. " IC1IE ,Input Capture 1 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. " OC1IE ,Output Compare 1 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 13. " TOIE ,Timer Overflow Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " IC2IE ,Input Capture 2 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " OC2IE ,Output Compare 2 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10. " DMAE ,DMA Enable" "Disabled,?..." textline " " hexmask.long.byte 0x00 0.--7. 1. " CC ,Clock Control" endif group.long 0x1C++0x3 line.long 0x0 "TIM_SR,Status Register" bitfld.long 0x00 15. " ICF1 ,Input Capture Flag 1" "Not captured,Captured" bitfld.long 0x00 14. " OCF1 ,Output Compare Flag 1" "Not matched,Matched" bitfld.long 0x00 13. " TOF ,Timer Overflow Flag" "No overflow,Overflow" textline " " bitfld.long 0x00 12. " ICF2 ,Input Capture Flag 2" "Not captured,Captured" bitfld.long 0x00 11. " OCF2 ,Output Compare Flag 2" "Not matched,Matched" tree.end base asd:0x58003000 tree "TIM1 (16-Bit Timer 1)" rgroup.long 0x0++0x17 line.long 0x0 "TIM1_IC1R,Input Capture Register 1" hexmask.long.word 0x00 0.--15. 1. " IC1R ,IC 1 Captured value" line.long 0x4 "TIM1_IC2R,Input Capture Register 2" hexmask.long.word 0x04 0.--15. 1. " IC2R ,IC 2 Captured value" line.long 0x8 "TIM1_OC1R,Output Compare Register 1" hexmask.long.word 0x08 0.--15. 1. " OC1R ,OC 1 Compare value" line.long 0xC "TIM1_OC2R,Output Compare Register 2" hexmask.long.word 0x0C 0.--15. 1. " OC2R ,OC 2 Compare value" line.long 0x10 "TIM1_CNTR,Counter Register" hexmask.long.word 0x10 0.--15. 1. " OCR2 ,Counter value" line.long 0x14 "TIM1_CR1,Control Register 1" bitfld.long 0x14 15. " EN ,Counter Enable" "Disabled,Enabled" bitfld.long 0x14 14. " PWMI ,PWM Input Mode Enable" "Disabled,Enabled" bitfld.long 0x14 12.--13. " DMAS ,DMA Source Selection" "IC1,OC1,IC2,OC2" textline " " bitfld.long 0x14 11. " FOLV2 ,Forced Output Compare 2" "No effect,OLVL2->OCMP2" bitfld.long 0x14 10. " FOLV1 ,Forced Output Compare 1" "No effect,OLVL1->OCMP1" bitfld.long 0x14 9. " OLVL2 ,Output Level 2" "Low,High" textline " " bitfld.long 0x14 8. " OLVL1 ,Output Level 1" "Low,High" bitfld.long 0x14 7. " OC2E ,Output Compare 2 Enable" "Disabled,Enabled" bitfld.long 0x14 6. " OC1E ,Output Compare 1 Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 5. " OPM ,One Pulse Mode" "Not activated,Activated" bitfld.long 0x14 4. " PWM ,Pulse Width Modulation Mode" "Not activated,Activated" bitfld.long 0x14 3. " IEDG2 ,Input Edge 2" "Falling,Rising" textline " " bitfld.long 0x14 2. " IEDG1 ,Input Edge 1" "Falling,Rising" bitfld.long 0x14 1. " EXEDG ,External Clock Edge" "Falling,Rising" bitfld.long 0x14 0. " ECKEN ,External Clock Enable" "Internal,External" if (1<2) group.long 0x18++0x3 line.long 0x0 "TIM1_CR2,Control Register 2" bitfld.long 0x00 15. " IC1IE ,Input Capture 1 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. " OC1IE ,Output Compare 1 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 13. " TOIE ,Timer Overflow Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " IC2IE ,Input Capture 2 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " OC2IE ,Output Compare 2 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10. " DMAE ,DMA Enable" "Disabled,Enabled" textline " " hexmask.long.byte 0x00 0.--7. 1. " CC ,Clock Control" else group.long 0x18++0x3 line.long 0x0 "TIM1_CR2,Control Register 2" bitfld.long 0x00 15. " IC1IE ,Input Capture 1 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. " OC1IE ,Output Compare 1 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 13. " TOIE ,Timer Overflow Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " IC2IE ,Input Capture 2 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " OC2IE ,Output Compare 2 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10. " DMAE ,DMA Enable" "Disabled,?..." textline " " hexmask.long.byte 0x00 0.--7. 1. " CC ,Clock Control" endif group.long 0x1C++0x3 line.long 0x0 "TIM_SR,Status Register" bitfld.long 0x00 15. " ICF1 ,Input Capture Flag 1" "Not captured,Captured" bitfld.long 0x00 14. " OCF1 ,Output Compare Flag 1" "Not matched,Matched" bitfld.long 0x00 13. " TOF ,Timer Overflow Flag" "No overflow,Overflow" textline " " bitfld.long 0x00 12. " ICF2 ,Input Capture Flag 2" "Not captured,Captured" bitfld.long 0x00 11. " OCF2 ,Output Compare Flag 2" "Not matched,Matched" tree.end base asd:0x58004000 tree "TIM2 (16-Bit Timer 2)" rgroup.long 0x0++0x17 line.long 0x0 "TIM2_IC1R,Input Capture Register 1" hexmask.long.word 0x00 0.--15. 1. " IC1R ,IC 1 Captured value" line.long 0x4 "TIM2_IC2R,Input Capture Register 2" hexmask.long.word 0x04 0.--15. 1. " IC2R ,IC 2 Captured value" line.long 0x8 "TIM2_OC1R,Output Compare Register 1" hexmask.long.word 0x08 0.--15. 1. " OC1R ,OC 1 Compare value" line.long 0xC "TIM2_OC2R,Output Compare Register 2" hexmask.long.word 0x0C 0.--15. 1. " OC2R ,OC 2 Compare value" line.long 0x10 "TIM2_CNTR,Counter Register" hexmask.long.word 0x10 0.--15. 1. " OCR2 ,Counter value" line.long 0x14 "TIM2_CR1,Control Register 1" bitfld.long 0x14 15. " EN ,Counter Enable" "Disabled,Enabled" bitfld.long 0x14 14. " PWMI ,PWM Input Mode Enable" "Disabled,Enabled" bitfld.long 0x14 12.--13. " DMAS ,DMA Source Selection" "IC1,OC1,IC2,OC2" textline " " bitfld.long 0x14 11. " FOLV2 ,Forced Output Compare 2" "No effect,OLVL2->OCMP2" bitfld.long 0x14 10. " FOLV1 ,Forced Output Compare 1" "No effect,OLVL1->OCMP1" bitfld.long 0x14 9. " OLVL2 ,Output Level 2" "Low,High" textline " " bitfld.long 0x14 8. " OLVL1 ,Output Level 1" "Low,High" bitfld.long 0x14 7. " OC2E ,Output Compare 2 Enable" "Disabled,Enabled" bitfld.long 0x14 6. " OC1E ,Output Compare 1 Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 5. " OPM ,One Pulse Mode" "Not activated,Activated" bitfld.long 0x14 4. " PWM ,Pulse Width Modulation Mode" "Not activated,Activated" bitfld.long 0x14 3. " IEDG2 ,Input Edge 2" "Falling,Rising" textline " " bitfld.long 0x14 2. " IEDG1 ,Input Edge 1" "Falling,Rising" bitfld.long 0x14 1. " EXEDG ,External Clock Edge" "Falling,Rising" bitfld.long 0x14 0. " ECKEN ,External Clock Enable" "Internal,External" if (2<2) group.long 0x18++0x3 line.long 0x0 "TIM2_CR2,Control Register 2" bitfld.long 0x00 15. " IC1IE ,Input Capture 1 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. " OC1IE ,Output Compare 1 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 13. " TOIE ,Timer Overflow Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " IC2IE ,Input Capture 2 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " OC2IE ,Output Compare 2 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10. " DMAE ,DMA Enable" "Disabled,Enabled" textline " " hexmask.long.byte 0x00 0.--7. 1. " CC ,Clock Control" else group.long 0x18++0x3 line.long 0x0 "TIM2_CR2,Control Register 2" bitfld.long 0x00 15. " IC1IE ,Input Capture 1 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. " OC1IE ,Output Compare 1 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 13. " TOIE ,Timer Overflow Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " IC2IE ,Input Capture 2 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " OC2IE ,Output Compare 2 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10. " DMAE ,DMA Enable" "Disabled,?..." textline " " hexmask.long.byte 0x00 0.--7. 1. " CC ,Clock Control" endif group.long 0x1C++0x3 line.long 0x0 "TIM_SR,Status Register" bitfld.long 0x00 15. " ICF1 ,Input Capture Flag 1" "Not captured,Captured" bitfld.long 0x00 14. " OCF1 ,Output Compare Flag 1" "Not matched,Matched" bitfld.long 0x00 13. " TOF ,Timer Overflow Flag" "No overflow,Overflow" textline " " bitfld.long 0x00 12. " ICF2 ,Input Capture Flag 2" "Not captured,Captured" bitfld.long 0x00 11. " OCF2 ,Output Compare Flag 2" "Not matched,Matched" tree.end base asd:0x58005000 tree "TIM3 (16-Bit Timer 3)" rgroup.long 0x0++0x17 line.long 0x0 "TIM3_IC1R,Input Capture Register 1" hexmask.long.word 0x00 0.--15. 1. " IC1R ,IC 1 Captured value" line.long 0x4 "TIM3_IC2R,Input Capture Register 2" hexmask.long.word 0x04 0.--15. 1. " IC2R ,IC 2 Captured value" line.long 0x8 "TIM3_OC1R,Output Compare Register 1" hexmask.long.word 0x08 0.--15. 1. " OC1R ,OC 1 Compare value" line.long 0xC "TIM3_OC2R,Output Compare Register 2" hexmask.long.word 0x0C 0.--15. 1. " OC2R ,OC 2 Compare value" line.long 0x10 "TIM3_CNTR,Counter Register" hexmask.long.word 0x10 0.--15. 1. " OCR2 ,Counter value" line.long 0x14 "TIM3_CR1,Control Register 1" bitfld.long 0x14 15. " EN ,Counter Enable" "Disabled,Enabled" bitfld.long 0x14 14. " PWMI ,PWM Input Mode Enable" "Disabled,Enabled" bitfld.long 0x14 12.--13. " DMAS ,DMA Source Selection" "IC1,OC1,IC2,OC2" textline " " bitfld.long 0x14 11. " FOLV2 ,Forced Output Compare 2" "No effect,OLVL2->OCMP2" bitfld.long 0x14 10. " FOLV1 ,Forced Output Compare 1" "No effect,OLVL1->OCMP1" bitfld.long 0x14 9. " OLVL2 ,Output Level 2" "Low,High" textline " " bitfld.long 0x14 8. " OLVL1 ,Output Level 1" "Low,High" bitfld.long 0x14 7. " OC2E ,Output Compare 2 Enable" "Disabled,Enabled" bitfld.long 0x14 6. " OC1E ,Output Compare 1 Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 5. " OPM ,One Pulse Mode" "Not activated,Activated" bitfld.long 0x14 4. " PWM ,Pulse Width Modulation Mode" "Not activated,Activated" bitfld.long 0x14 3. " IEDG2 ,Input Edge 2" "Falling,Rising" textline " " bitfld.long 0x14 2. " IEDG1 ,Input Edge 1" "Falling,Rising" bitfld.long 0x14 1. " EXEDG ,External Clock Edge" "Falling,Rising" bitfld.long 0x14 0. " ECKEN ,External Clock Enable" "Internal,External" if (3<2) group.long 0x18++0x3 line.long 0x0 "TIM3_CR2,Control Register 2" bitfld.long 0x00 15. " IC1IE ,Input Capture 1 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. " OC1IE ,Output Compare 1 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 13. " TOIE ,Timer Overflow Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " IC2IE ,Input Capture 2 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " OC2IE ,Output Compare 2 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10. " DMAE ,DMA Enable" "Disabled,Enabled" textline " " hexmask.long.byte 0x00 0.--7. 1. " CC ,Clock Control" else group.long 0x18++0x3 line.long 0x0 "TIM3_CR2,Control Register 2" bitfld.long 0x00 15. " IC1IE ,Input Capture 1 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. " OC1IE ,Output Compare 1 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 13. " TOIE ,Timer Overflow Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " IC2IE ,Input Capture 2 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " OC2IE ,Output Compare 2 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10. " DMAE ,DMA Enable" "Disabled,?..." textline " " hexmask.long.byte 0x00 0.--7. 1. " CC ,Clock Control" endif group.long 0x1C++0x3 line.long 0x0 "TIM_SR,Status Register" bitfld.long 0x00 15. " ICF1 ,Input Capture Flag 1" "Not captured,Captured" bitfld.long 0x00 14. " OCF1 ,Output Compare Flag 1" "Not matched,Matched" bitfld.long 0x00 13. " TOF ,Timer Overflow Flag" "No overflow,Overflow" textline " " bitfld.long 0x00 12. " ICF2 ,Input Capture Flag 2" "Not captured,Captured" bitfld.long 0x00 11. " OCF2 ,Output Compare Flag 2" "Not matched,Matched" tree.end width 0xB tree.end tree "ENET (MAC/DMA Controller with DMA)" sif (!cpuis("STR910FA*")&&!cpuis("STR911FA*")) base asd:0x7C000000 width 10. tree "DMA Registers" group.long 0x0++0xF line.long 0x0 "ENET_SCR,DMA Status/Control Register" bitfld.long 0x00 28.--31. " TX_FIFO_SIZE ,Transmit FIFO Size" "Reserved,2x32-bit,4x32-bit,8x32-bit,16x32-bit,32x32-bit,?..." bitfld.long 0x00 26.--27. " TX_IO_DATA_WIDTH ,Transmit Data Bus Width" "8-bit,16-bit,32-bit,?..." textline " " bitfld.long 0x00 24.--25. " TX_CHAN_STATUS ,Transmit Channel Information" "Not present,Low,High,?..." bitfld.long 0x00 20.--23. " RX_FIFO_SIZE ,Receive FIFO Size" "Reserved,2x32-bit,4x32-bit,8x32-bit,16x32-bit,32x32-bit,?..." textline " " bitfld.long 0x00 18.--19. " RX_IO_DATA_WIDTH ,Receive Data Bus Width" "8-bit,16-bit,32-bit,?..." bitfld.long 0x00 16.--17. " RX_CHAN_STATUS ,Receive Channel Information" "Reserved,Low,High,?..." textline " " hexmask.long.byte 0x00 8.--15. 1. " REVISION ,Revision Number" bitfld.long 0x00 6.--7. " TX_MAX_BURST_SIZE ,Transmit Maximum Burst Size" "INCR16,INCR8,INCR4,SINGLE" textline " " bitfld.long 0x00 4.--5. " RX_MAX_BURST_SIZE ,Receive Maximum Burst Size" "INCR16,INCR8,INCR4,SINGLE" bitfld.long 0x00 1. " LOOPB ,Loopback Mode" "Normal,Loopback" textline " " bitfld.long 0x00 0. " SRESET ,MAC DMA Software Reset" "No reset,Reset" line.long 0x4 "ENET_IER,DMA Interrupt Enable Register" bitfld.long 0x04 31. " TX_CURR_DONE_EN ,TX_CURR_DONE Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 28. " MAC-802.3_INT_EN ,MAC-802.3 Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 25. " TX_MERR_INT_EN ,TX_MERR Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 23. " TX_DONE_EN ,TX_DONE Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 22. " TX_NEXT_EN ,TX_NEXT Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 19. " TX_TO_EN ,TX_TO Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 18. " TX_ENTRY_EN ,TX_ENTRY Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 17. " TX_FULL_EN ,TX_FULL Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 16. " TX_EMPTY_EN ,TX_EMPTY Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 15. " RX_CURR_DONE_EN ,RX_CURR_DONE Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 9. " RX_MERR_INT_EN ,RX_MERR Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 7. " RX_DONE_EN ,RX_DONE Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 6. " RX_NEXT_EN ,RX_NEXT Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 5. " PACKET_LOST_EN ,PACKET_LOST Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 3. " RX_TO_EN ,RX_TO Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 2. " RX_ENTRY_EN ,RX_ENTRY Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 1. " RX_FULL_EN ,RX_FULL Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 0. " RX_EMPTY_EN ,RX_EMPTY Interrupt Enable" "Disabled,Enabled" line.long 0x8 "ENET_ISR,DMA Interrupt Status Register" eventfld.long 0x08 31. " TX_CURR_DONE ,TX_CURR_DONE Interrupt Flag" "No interrupt,Interrupt" eventfld.long 0x08 28. " MAC-802.3_INT ,MAC-802.3 Interrupt Flag (Not Used)" "No interrupt,Interrupt" textline " " eventfld.long 0x08 25. " TX_MERR_INT ,TX_MERR Interrupt Flag" "No interrupt,Interrupt" eventfld.long 0x08 23. " TX_DONE ,TX_DONE Interrupt Flag" "No interrupt,Interrupt" textline " " eventfld.long 0x08 22. " TX_NEXT ,TX_NEXT Interrupt Flag" "No interrupt,Interrupt" eventfld.long 0x08 19. " TX_TO ,TX_TO Timeout Interrupt Flag" "No interrupt,Interrupt" textline " " eventfld.long 0x08 18. " TXENTRY ,TX_ENTRY Interrupt Flag" "No interrupt,Interrupt" eventfld.long 0x08 17. " TX_FULL ,TX_FULL Interrupt Flag" "No interrupt,Interrupt" textline " " eventfld.long 0x08 16. " TX_EMPTY ,TX_EMPTY Interrupt Flag" "No interrupt,Interrupt" eventfld.long 0x08 15. " RX_CURR_DONE ,RX_CURR_DONE Interrupt Flag" "No interrupt,Interrupt" textline " " eventfld.long 0x08 9. " RX_MERR_INT ,RX_MERR Interrupt Flag" "No interrupt,Interrupt" eventfld.long 0x08 7. " RX_DONE ,RX_DONE Interrupt Flag" "No interrupt,Interrupt" textline " " eventfld.long 0x08 6. " RX_NEXT ,RX_NEXT Interrupt Flag" "No interrupt,Interrupt" eventfld.long 0x08 5. " PACKET_LOST ,PACKET_LOST Interrupt Flag" "No interrupt,Interrupt" textline " " eventfld.long 0x08 3. " RX_TO ,RX_TO Interrupt Flag" "No interrupt,Interrupt" eventfld.long 0x08 2. " RXENTRY ,RX_ENTRY Interrupt Flag" "No interrupt,Interrupt" textline " " eventfld.long 0x08 1. " RX_FULL ,RX_FULL Interrupt Flag" "No interrupt,Interrupt" eventfld.long 0x08 0. " RX_EMPTY ,RX_EMPTY Interrupt Flag" "No interrupt,Interrupt" line.long 0xC "ENET_CCR,Clock Configuration Register" bitfld.long 0xC 2.--3. " SEL_CLK ,Clock Configuration" "PCLK,2xPCLK,?..." tree.end width 0xD tree "RX Registers" group.long 0x10++0x3 line.long 0x0 "ENET_RXSTR,RX Start Register" hexmask.long.word 0x0 8.--23. 1. " DFETCH_DLY ,Descriptor Fetch Delay" bitfld.long 0x0 7. " COLL_SEEN ,Late Collision Seen Control" "No action,Discarded" textline " " bitfld.long 0x0 6. " RUNT_FRAME ,Damaged Frame Control" "No action,Discarded" bitfld.long 0x0 5. " FILTER_FAIL ,Address Filtering Fail Control" "No action,Discarded" textline " " bitfld.long 0x0 2. " START_FETCH ,Fetching Start Control" "No effect,Started" eventfld.long 0x0 0. " DMA_EN ,DMA Enable" "Disabled,Enabled" if ((((d.l(asd:(0x7C000000+0x18)))&0x1)==0x1)&&(((d.l(asd:(0x7C000000+0x14)))&0x1000)==0x0000)) group.long 0x14++0x3 line.long 0x0 "ENET_RXCR,RX Control Register" hexmask.long.word 0x0 22.--31. 0x40 " ADDR_WRAP ,DMA Address Counter Wrap Location" bitfld.long 0x0 17.--21. " ENTRY_TRIG ,Entry Trigger Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 15. " DLY_EN ,DMA Trigger Delay Enable" "Disabled,Enabled" bitfld.long 0x0 14. " NXT_EN ,Next Descriptor Fetch Mode Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 12. " CONT_EN ,Continuous Mode Enable" "Normal,Continuous" hexmask.long.word 0x0 0.--11. 1. " DMA_XFERCOUNT ,DMA Transfer Count" elif ((((d.l(asd:(0x7C000000+0x18)))&0x1)==0x1)&&(((d.l(asd:(0x7C000000+0x14)))&0x1000)==0x1000)) group.long 0x14++0x3 line.long 0x0 "ENET_RXCR,RX Control Register" hexmask.long.word 0x0 22.--31. 0x40 " ADDR_WRAP ,DMA Address Counter Wrap Location" bitfld.long 0x0 17.--21. " ENTRY_TRIG ,Entry Trigger Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 15. " DLY_EN ,DMA Trigger Delay Enable" "Disabled,Enabled" bitfld.long 0x0 14. " NXT_EN ,Next Descriptor Fetch Mode Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 12. " CONT_EN ,Continuous Mode Enable" "Normal,Continuous" elif ((((d.l(asd:(0x7C000000+0x18)))&0x1)==0x0)&&(((d.l(asd:(0x7C000000+0x14)))&0x1000)==0x0000)) group.long 0x14++0x3 line.long 0x0 "ENET_RXCR,RX Control Register" bitfld.long 0x0 17.--21. " ENTRY_TRIG ,Entry Trigger Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 15. " DLY_EN ,DMA Trigger Delay Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 14. " NXT_EN ,Next Descriptor Fetch Mode Enable" "Disabled,Enabled" bitfld.long 0x0 12. " CONT_EN ,Continuous Mode Enable" "Normal,Continuous" textline " " hexmask.long.word 0x0 0.--11. 1. " DMA_XFERCOUNT ,DMA Transfer Count" else group.long 0x14++0x3 line.long 0x0 "ENET_RXCR,RX Control Register" bitfld.long 0x0 17.--21. " ENTRY_TRIG ,Entry Trigger Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 15. " DLY_EN ,DMA Trigger Delay Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 14. " NXT_EN ,Next Descriptor Fetch Mode Enable" "Disabled,Enabled" bitfld.long 0x0 12. " CONT_EN ,Continuous Mode Enable" "Normal,Continuous" endif group.long 0x18++0x7 line.long 0x0 "ENET_RXSAR,RX Start Address Register" hexmask.long 0x0 2.--31. 0x4 " RXADDR ,Master DMA Transfer Start Address" bitfld.long 0x0 1. " FIX_ADDR ,Fixed Address" "Not fixed,Fixed" textline " " bitfld.long 0x0 0. " WRAP_EN ,Wrap Enable" "Disabled,Enabled" line.long 0x4 "ENET_RXNDAR,RX Next Descriptor Address Register" hexmask.long 0x4 2.--31. 0x4 " DESCADDR ,RX DMA Next Descriptor Pointer" bitfld.long 0x4 0. " NPOL_EN ,Next Descriptor Polling Enable" "Disabled,Enabled" rgroup.long 0x20++0xF line.long 0x0 "ENET_RXCAR,RX Current Address Register" line.long 0x4 "ENET_RXCTCR,RX Current Transfer Count Register" hexmask.long.word 0x4 0.--11. 1. " CXFER ,RX DMA Current Transfer Count" line.long 0x8 "ENET_RXTOR,RX Time-Out Register" hexmask.long.word 0x8 0.--15. 1. " RXTO ,RX FIFO Time-Out Value" line.long 0xC "ENET_RXSR,RX Status Register" hexmask.long.byte 0x0C 24.--29. 1. " ENTRIES ,RX FIFO Entry Count" hexmask.long.byte 0x0C 16.--20. 1. " DMA_POINTER ,DMA RX FIFO Pointer" textline " " hexmask.long.byte 0x0C 8.--12. 1. " IO_POINTER ,I/O RX FIFO Value" bitfld.long 0x0C 3. " DELAY_T ,RX FIFO Time-Out Flag" "Normal,Expired" textline " " bitfld.long 0x0C 2. " ENTRY_T ,RX FIFO Entry Threshold Flag" "Normal,Reached" bitfld.long 0x0C 1. " FULL ,RX FIFO Full Flag" "Normal,Full" textline " " bitfld.long 0x0C 0. " EMPTY ,RX FIFO Empty Flag" "Normal,Empty" tree.end width 13. tree "TX Registers" textline " " group.long 0x30++0x3 line.long 0x0 "ENET_TXSTR,TX Start Register" hexmask.long.word 0x00 8.--23. 1. " DFETCH_DLY ,Descriptor Fetch Delay" bitfld.long 0x00 5. " UNDER_RUN ,Underrun Enable (Packet retransmition without an error when underrun)" "Normal,Enabled" textline " " bitfld.long 0x00 2. " START_FETCH ,Fetching Start Control" "No effect,Started" eventfld.long 0x00 0. " DMA_EN ,DMA Enable" "Disabled,Enabled" if ((((d.l(asd:(0x7C000000+0x38)))&0x1)==0x1)&&(((d.l(asd:(0x7C000000+0x34)))&0x1000)==0x0000)) group.long 0x34++0x3 line.long 0x0 "ENET_TXCR,TX Control Register" hexmask.long 0x0 22.--31. 0x4 " ADDR_WRAP ,DMA Address Counter Wrap Location" bitfld.long 0x0 17.--21. " ENTRY_TRIG ,Entry Trigger Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 15. " DLY_EN ,DMA Trigger Delay Enable" "Disabled,Enabled" bitfld.long 0x0 14. " NXT_EN ,Next Descriptor Fetch Mode Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 12. " CONT_EN ,Continuous Mode Enable" "Normal,Continuous" hexmask.long.word 0x0 0.--11. 1. " DMA_XFERCOUNT ,DMA Transfer Count" elif ((((d.l(asd:(0x7C000000+0x38)))&0x1)==0x1)&&(((d.l(asd:(0x7C000000+0x34)))&0x1000)==0x1000)) group.long 0x34++0x3 line.long 0x0 "ENET_TXCR,TX Control Register" hexmask.long 0x0 22.--31. 0x4 " ADDR_WRAP ,DMA Address Counter Wrap Location" bitfld.long 0x0 17.--21. " ENTRY_TRIG ,Entry Trigger Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 15. " DLY_EN ,DMA Trigger Delay Enable" "Disabled,Enabled" bitfld.long 0x0 14. " NXT_EN ,Next Descriptor Fetch Mode Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 12. " CONT_EN ,Continuous Mode Enable" "Normal,Continuous" elif ((((d.l(asd:(0x7C000000+0x38)))&0x1)==0x0)&&(((d.l(asd:(0x7C000000+0x34)))&0x1000)==0x0000)) group.long 0x34++0x3 line.long 0x0 "ENET_TXCR,TX Control Register" bitfld.long 0x0 17.--21. " ENTRY_TRIG ,Entry Trigger Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 15. " DLY_EN ,DMA Trigger Delay Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 14. " NXT_EN ,Next Descriptor Fetch Mode Enable" "Disabled,Enabled" bitfld.long 0x0 12. " CONT_EN ,Continuous Mode Enable" "Normal,Continuous" textline " " hexmask.long.word 0x0 0.--11. 1. " DMA_XFERCOUNT ,DMA Transfer Count" else group.long 0x34++0x3 line.long 0x0 "ENET_TXCR,TX Control Register" bitfld.long 0x0 17.--21. " ENTRY_TRIG ,Entry Trigger Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 15. " DLY_EN ,DMA Trigger Delay Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 14. " NXT_EN ,Next Descriptor Fetch Mode Enable" "Disabled,Enabled" bitfld.long 0x0 12. " CONT_EN ,Continuous Mode Enable" "Normal,Continuous" endif group.long 0x38++0x7 line.long 0x0 "ENET_TXSAR,TX Start Address Register" hexmask.long 0x0 2.--31. 0x4 " TXADDR ,Master DMA Transfer Start Address" bitfld.long 0x0 1. " FIX_ADDR ,Fixed Address" "Not fixed,Fixed" textline " " bitfld.long 0x0 0. " WRAP_EN ,Wrap Enable" "Disabled,Enabled" line.long 0x4 "ENET_TXNDAR,TX Next Descriptor Address Register" hexmask.long 0x4 2.--31. 0x4 " DESCADDR ,TX DMA Next Descriptor Pointer" bitfld.long 0x4 0. " NPOL_EN ,Next Descriptor Polling Enable" "Disabled,Enabled" rgroup.long 0x40++0xF line.long 0x0 "ENET_TXCAR,TX Current Address Register" line.long 0x4 "ENET_TXCTCR,TX Current Transfer Count Register" hexmask.long.word 0x4 0.--11. 1. " CXFER ,TX DMA Current Transfer Count" line.long 0x8 "ENET_TXTOR,TX Time-Out Register" hexmask.long.word 0x8 0.--15. 1. " TXTO ,TX FIFO Time-Out Value" line.long 0xC "ENET_TXSR,TX Status Register" hexmask.long.byte 0x0C 24.--29. 1. " ENTRIES ,TX FIFO Entry Count" hexmask.long.byte 0x0C 16.--20. 1. " DMA_POINTER ,DMA TX FIFO Pointer" textline " " hexmask.long.byte 0x0C 8.--12. 1. " IO_POINTER ,IO TX FIFO Pointer" bitfld.long 0x0C 3. " DELAY_T ,TX FIFO Time-Out Flag" "Not expired,Expired" textline " " bitfld.long 0x0C 2. " ENTRY_T ,TX FIFO Entry Threshold Flag" "Not reached,Reached" bitfld.long 0x0C 1. " FULL ,TX FIFO Full Flag" "Not full,Full" textline " " eventfld.long 0x0C 0. " EMPTY ,TX FIFO Empty Flag" "Not empty,Empty" tree.end textline " " width 0xA group.long 0x400++0x3 line.long 0x0 "ENET_MCR,MAC Control Register" bitfld.long 0x00 31. " RA ,Receive All" "Not all,All" bitfld.long 0x00 30. " EN ,Endianity" "Little,Big" textline " " bitfld.long 0x00 24.--25. " PS ,Prescaler" "fHCLK<=50 MHz,50 MHzLT,Conversion when CDATALT,Conversion when CDATALT,Conversion when CDATALT,Conversion when CDATALT,Conversion when CDATALT,Conversion when CDATALT,Conversion when CDATALT,Conversion when CDATA